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author Vas Crabb <vas@vastheman.com>2018-12-23 09:44:47 +1100
committer Vas Crabb <vas@vastheman.com>2018-12-23 09:44:47 +1100
commit655bfff256169b99eccda06216dcaae31a475b02 (patch)
tree93600780978c77febf79d953bcb373af61afd6ac /src
parent482cb17d57441f059d027365ca93aacbd971ddfa (diff)
srcclean (nw)
Diffstat (limited to 'src')
-rw-r--r--src/devices/bus/nes_ctrl/ctrl.h4
-rw-r--r--src/devices/cpu/dspp/dspp.cpp150
-rw-r--r--src/devices/cpu/dspp/dspp.h152
-rw-r--r--src/devices/cpu/dspp/dsppdrc.cpp92
-rw-r--r--src/devices/cpu/dspp/dsppfe.cpp84
-rw-r--r--src/devices/cpu/e132xs/32xsdefs.h2
-rw-r--r--src/devices/cpu/mcs51/axc51-core.cpp14
-rw-r--r--src/devices/cpu/mcs51/axc51-core.h6
-rw-r--r--src/devices/cpu/mcs51/axc51-core_dasm.cpp102
-rw-r--r--src/devices/cpu/mcs51/axc51-core_dasm.h6
-rw-r--r--src/devices/cpu/powerpc/ppccom.h8
-rw-r--r--src/devices/cpu/powerpc/ppcdrc.cpp2
-rw-r--r--src/devices/machine/spg2xx.h8
-rw-r--r--src/devices/machine/t10mmc.cpp4
-rw-r--r--src/devices/sound/scspdsp.cpp2
-rw-r--r--src/devices/sound/swp30.cpp8
-rw-r--r--src/devices/video/i82730.h2
-rw-r--r--src/mame/audio/mario.cpp4
-rw-r--r--src/mame/drivers/balsente.cpp2
-rw-r--r--src/mame/drivers/brkthru.cpp2
-rw-r--r--src/mame/drivers/esripsys.cpp2
-rw-r--r--src/mame/drivers/fastinvaders.cpp4
-rw-r--r--src/mame/drivers/funworld.cpp26
-rw-r--r--src/mame/drivers/goldstar.cpp82
-rw-r--r--src/mame/drivers/gsword.cpp2
-rw-r--r--src/mame/drivers/harddriv.cpp26
-rw-r--r--src/mame/drivers/hh_tms1k.cpp24
-rw-r--r--src/mame/drivers/hikaru.cpp4
-rw-r--r--src/mame/drivers/hp3478a.cpp86
-rw-r--r--src/mame/drivers/hp95lx.cpp36
-rw-r--r--src/mame/drivers/konamim2.cpp134
-rw-r--r--src/mame/drivers/m24.cpp22
-rw-r--r--src/mame/drivers/mdisk.cpp12
-rw-r--r--src/mame/drivers/megasys1.cpp2
-rw-r--r--src/mame/drivers/midtunit.cpp10
-rw-r--r--src/mame/drivers/midwunit.cpp10
-rw-r--r--src/mame/drivers/midxunit.cpp12
-rw-r--r--src/mame/drivers/minivideo.cpp4
-rw-r--r--src/mame/drivers/monon_color.cpp26
-rw-r--r--src/mame/drivers/mupid2.cpp20
-rw-r--r--src/mame/drivers/nes.cpp6
-rw-r--r--src/mame/drivers/nes_vt.cpp6
-rw-r--r--src/mame/drivers/overdriv.cpp4
-rw-r--r--src/mame/drivers/pasopia7.cpp2
-rw-r--r--src/mame/drivers/pgm2.cpp4
-rw-r--r--src/mame/drivers/pocketc.cpp6
-rw-r--r--src/mame/drivers/psx.cpp4
-rw-r--r--src/mame/drivers/rainbow.cpp34
-rw-r--r--src/mame/drivers/rulechan.cpp116
-rw-r--r--src/mame/drivers/samcoupe.cpp2
-rw-r--r--src/mame/drivers/seta2.cpp2
-rw-r--r--src/mame/drivers/snesb.cpp130
-rw-r--r--src/mame/drivers/vii.cpp40
-rw-r--r--src/mame/drivers/vsmile.cpp24
-rw-r--r--src/mame/drivers/ymmu100.cpp4
-rw-r--r--src/mame/includes/playmark.h2
-rw-r--r--src/mame/includes/seta2.h2
-rw-r--r--src/mame/includes/spacefb.h2
-rw-r--r--src/mame/layout/hp3478a.lay8
-rw-r--r--src/mame/layout/rulechan.lay6
-rw-r--r--src/mame/machine/3dom2.cpp244
-rw-r--r--src/mame/machine/3dom2.h654
-rw-r--r--src/mame/machine/3dom2_defs.h1000
-rw-r--r--src/mame/machine/3dom2_te.cpp810
-rw-r--r--src/mame/machine/genpin.cpp2
-rw-r--r--src/mame/machine/midwunit.cpp10
-rw-r--r--src/mame/machine/midxunit.cpp10
-rw-r--r--src/mame/video/galaxian.cpp4
-rw-r--r--src/mame/video/k054156_k054157_k056832.h2
-rw-r--r--src/mame/video/midtunit.cpp4
-rw-r--r--src/mame/video/midtunit.h18
-rw-r--r--src/mame/video/midtunit.ipp104
-rw-r--r--src/mame/video/pc1251.cpp2
-rw-r--r--src/mame/video/seta2.cpp74
-rw-r--r--src/mame/video/ssv.cpp14
75 files changed, 2277 insertions, 2277 deletions
diff --git a/src/devices/bus/nes_ctrl/ctrl.h b/src/devices/bus/nes_ctrl/ctrl.h
index 1050ce0e45f..24a58b4f53c 100644
--- a/src/devices/bus/nes_ctrl/ctrl.h
+++ b/src/devices/bus/nes_ctrl/ctrl.h
@@ -7,8 +7,8 @@
**********************************************************************
- Known Issues:
- - Currently the FC expansion port is emulated as a control port
+ Known Issues:
+ - Currently the FC expansion port is emulated as a control port
**********************************************************************/
diff --git a/src/devices/cpu/dspp/dspp.cpp b/src/devices/cpu/dspp/dspp.cpp
index d8d8e7055e1..411365bbc29 100644
--- a/src/devices/cpu/dspp/dspp.cpp
+++ b/src/devices/cpu/dspp/dspp.cpp
@@ -33,7 +33,7 @@ enum
#define SINGLE_INSTRUCTION_MODE (0)
-#define CACHE_SIZE (4 * 1024 * 1024) // FIXME
+#define CACHE_SIZE (4 * 1024 * 1024) // FIXME
// FIXME!!!
/* compilation boundaries -- how far back/forward does the analysis extend? */
#define COMPILE_BACKWARDS_BYTES 128
@@ -54,46 +54,46 @@ enum
// MACROS
//**************************************************************************
-//#define DSPI_FLAG_CC_CARRY 0x0001
-//#define DSPI_FLAG_CC_ZERO 0x0002
-//#define DSPI_FLAG_CC_NEG 0x0004
-//#define DSPI_FLAG_CC_OVER 0x0008
-//#define DSPI_FLAG_CC_EXACT 0x0010
-//#define DSPI_FLAG_AUDLOCK 0x0020
-//#define DSPI_FLAG_SLEEP 0x0040
-//#define DSPI_FLAG_CC_MASK 0x001f
-
-#define DSPX_CONTROL_GWILLING 0x0001
-#define DSPX_CONTROL_STEP_CYCLE 0x0002
-#define DSPX_CONTROL_STEP_PC 0x0004
-#define DSPX_CONTROL_SNOOP 0x0008
-
-#define DSPX_RESET_DSPP 0x0001
-#define DSPX_RESET_INPUT 0x0002
-#define DSPX_RESET_OUTPUT 0x0004
-
-#define DSPX_F_DMA_NEXTVALID 0x0001
-#define DSPX_F_DMA_GO_FOREVER 0x0002
-#define DSPX_F_INT_DMANEXT_EN 0x0004
-#define DSPX_F_SHADOW_SET_DMANEXT 0x00040000
-#define DSPX_F_SHADOW_SET_FOREVER 0x00020000
-#define DSPX_F_SHADOW_SET_NEXTVALID 0x00010000
-#define DSPX_F_SHADOW_SET_ADDRESS_COUNT 0x80000000
-
-#define DSPX_F_INT_TIMER 0x00000100
-#define DSPX_F_INT_INPUT_UNDER 0x00000080
-#define DSPX_F_INT_INPUT_OVER 0x00000040
-#define DSPX_F_INT_OUTPUT_UNDER 0x00000020
-#define DSPX_F_INT_OUTPUT_OVER 0x00000010
-#define DSPX_F_INT_UNDEROVER 0x00000008
-#define DSPX_F_INT_CONSUMED 0x00000002
-#define DSPX_F_INT_DMANEXT 0x00000001
-
-#define DSPX_F_INT_ALL_DMA (DSPX_F_INT_DMANEXT | DSPX_F_INT_CONSUMED | DSPX_F_INT_UNDEROVER)
-
-#define DSPX_FLD_INT_SOFT_WIDTH 16 /* width of the field and the number of interrupts */
-#define DSPX_FLD_INT_SOFT_SHIFT 16
-#define DSPX_FLD_INT_SOFT_MASK (0xffff0000)
+//#define DSPI_FLAG_CC_CARRY 0x0001
+//#define DSPI_FLAG_CC_ZERO 0x0002
+//#define DSPI_FLAG_CC_NEG 0x0004
+//#define DSPI_FLAG_CC_OVER 0x0008
+//#define DSPI_FLAG_CC_EXACT 0x0010
+//#define DSPI_FLAG_AUDLOCK 0x0020
+//#define DSPI_FLAG_SLEEP 0x0040
+//#define DSPI_FLAG_CC_MASK 0x001f
+
+#define DSPX_CONTROL_GWILLING 0x0001
+#define DSPX_CONTROL_STEP_CYCLE 0x0002
+#define DSPX_CONTROL_STEP_PC 0x0004
+#define DSPX_CONTROL_SNOOP 0x0008
+
+#define DSPX_RESET_DSPP 0x0001
+#define DSPX_RESET_INPUT 0x0002
+#define DSPX_RESET_OUTPUT 0x0004
+
+#define DSPX_F_DMA_NEXTVALID 0x0001
+#define DSPX_F_DMA_GO_FOREVER 0x0002
+#define DSPX_F_INT_DMANEXT_EN 0x0004
+#define DSPX_F_SHADOW_SET_DMANEXT 0x00040000
+#define DSPX_F_SHADOW_SET_FOREVER 0x00020000
+#define DSPX_F_SHADOW_SET_NEXTVALID 0x00010000
+#define DSPX_F_SHADOW_SET_ADDRESS_COUNT 0x80000000
+
+#define DSPX_F_INT_TIMER 0x00000100
+#define DSPX_F_INT_INPUT_UNDER 0x00000080
+#define DSPX_F_INT_INPUT_OVER 0x00000040
+#define DSPX_F_INT_OUTPUT_UNDER 0x00000020
+#define DSPX_F_INT_OUTPUT_OVER 0x00000010
+#define DSPX_F_INT_UNDEROVER 0x00000008
+#define DSPX_F_INT_CONSUMED 0x00000002
+#define DSPX_F_INT_DMANEXT 0x00000001
+
+#define DSPX_F_INT_ALL_DMA (DSPX_F_INT_DMANEXT | DSPX_F_INT_CONSUMED | DSPX_F_INT_UNDEROVER)
+
+#define DSPX_FLD_INT_SOFT_WIDTH 16 /* width of the field and the number of interrupts */
+#define DSPX_FLD_INT_SOFT_SHIFT 16
+#define DSPX_FLD_INT_SOFT_MASK (0xffff0000)
@@ -378,14 +378,14 @@ void dspp_device::state_string_export(const device_state_entry &entry, std::stri
{
case STATE_GENFLAGS:
str = string_format("%c%c.%c%c%c%c%c",
- m_core->m_flag_audlock ? 'A' : '.',
- m_core->m_flag_sleep ? 'S' : '.',
- m_core->m_flag_carry ? 'C' : '.',
- m_core->m_flag_zero ? 'Z' : '.',
- m_core->m_flag_neg ? 'N' : '.',
- m_core->m_flag_over ? 'V' : '.',
- m_core->m_flag_exact ? 'E' : '.');
- break;
+ m_core->m_flag_audlock ? 'A' : '.',
+ m_core->m_flag_sleep ? 'S' : '.',
+ m_core->m_flag_carry ? 'C' : '.',
+ m_core->m_flag_zero ? 'Z' : '.',
+ m_core->m_flag_neg ? 'N' : '.',
+ m_core->m_flag_over ? 'V' : '.',
+ m_core->m_flag_exact ? 'E' : '.');
+ break;
}
}
@@ -732,7 +732,7 @@ void dspp_device::execute_run()
return;
}
- bool check_debugger = ((device_t::machine().debug_flags & DEBUG_FLAG_ENABLED) != 0);
+ bool check_debugger = ((device_t::machine().debug_flags & DEBUG_FLAG_ENABLED) != 0);
do
{
@@ -742,8 +742,8 @@ void dspp_device::execute_run()
// Only run if enabled
if (m_dspx_control & DSPX_CONTROL_GWILLING)
{
- if (check_debugger)
- debugger_instruction_hook(m_core->m_pc);
+ if (check_debugger)
+ debugger_instruction_hook(m_core->m_pc);
m_core->m_op = read_op(m_core->m_pc);
update_pc();
@@ -775,7 +775,7 @@ inline void dspp_device::exec_super_special()
switch (sel)
{
- case 1: // BAC
+ case 1: // BAC
{
m_core->m_pc = m_core->m_acc >> 4;
break;
@@ -1116,70 +1116,70 @@ inline void dspp_device::exec_arithmetic()
switch (alu_op)
{
- case 0: // _TRA
+ case 0: // _TRA
{
alu_res = alu_a;
m_core->m_flag_over = 0;
m_core->m_flag_carry = 0;
break;
}
- case 1: // _NEG
+ case 1: // _NEG
{
alu_res = -alu_b;
m_core->m_flag_over = 0;
m_core->m_flag_carry = 0;
break;
}
- case 2: // _+
+ case 2: // _+
{
alu_res = alu_a + alu_b;
m_core->m_flag_over = (((alu_a & 0x80000) == (alu_b & 0x80000) && (alu_a & 0x80000) != (alu_res & 0x80000)));
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
break;
}
- case 3: // _+C
+ case 3: // _+C
{
alu_res = alu_a + (m_core->m_flag_carry << 4);
m_core->m_flag_over = 0;
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
break;
}
- case 4: // _-
+ case 4: // _-
{
alu_res = alu_a - alu_b;
m_core->m_flag_over = ((alu_a & 0x80000) == (~alu_b & 0x80000) && (alu_a & 0x80000) != (alu_res & 0x80000));
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
break;
}
- case 5: // _-B
+ case 5: // _-B
{
alu_res = alu_a - (m_core->m_flag_carry << 4);
m_core->m_flag_over = 0;
m_core->m_flag_carry = (alu_res & 0x00100000) != 0;
break;
}
- case 6: // _++
+ case 6: // _++
{
alu_res = alu_a + 1;
m_core->m_flag_over = !(alu_a & 0x80000) && (alu_res & 0x80000);
m_core->m_flag_carry = 0;
break;
}
- case 7: // _--
+ case 7: // _--
{
alu_res = alu_a - 1;
m_core->m_flag_over = (alu_a & 0x80000) && !(alu_res & 0x80000);
m_core->m_flag_carry = 0;
break;
}
- case 8: // _TRL
+ case 8: // _TRL
{
alu_res = alu_a;
m_core->m_flag_over = 0;
m_core->m_flag_carry = 0;
break;
}
- case 9: // _NOT
+ case 9: // _NOT
{
alu_res = ~alu_a;
m_core->m_flag_over = 0;
@@ -2630,17 +2630,17 @@ void dspp_device::dump_state()
printf("DSPX_CHANNEL_SQXD: %08X %s\n", m_dspx_channel_sqxd, GetBinary(buffer, m_dspx_channel_sqxd, 32));
#if 0
- uint32_t m_dspx_shadow_current_addr;
- uint32_t m_dspx_shadow_current_count;
- uint32_t m_dspx_shadow_next_addr;
- uint32_t m_dspx_shadow_next_count;
- uint32_t m_dspx_dmanext_int;
- uint32_t m_dspx_dmanext_enable;
- uint32_t m_dspx_consumed_int;
- uint32_t m_dspx_consumed_enable;
- uint32_t m_dspx_underover_int;
- uint32_t m_dspx_underover_enable;
- uint32_t m_dspx_audio_time;
- uint16_t m_dspx_audio_duration;
+ uint32_t m_dspx_shadow_current_addr;
+ uint32_t m_dspx_shadow_current_count;
+ uint32_t m_dspx_shadow_next_addr;
+ uint32_t m_dspx_shadow_next_count;
+ uint32_t m_dspx_dmanext_int;
+ uint32_t m_dspx_dmanext_enable;
+ uint32_t m_dspx_consumed_int;
+ uint32_t m_dspx_consumed_enable;
+ uint32_t m_dspx_underover_int;
+ uint32_t m_dspx_underover_enable;
+ uint32_t m_dspx_audio_time;
+ uint16_t m_dspx_audio_duration;
#endif
}
diff --git a/src/devices/cpu/dspp/dspp.h b/src/devices/cpu/dspp/dspp.h
index 848c2931714..155ba4acbd1 100644
--- a/src/devices/cpu/dspp/dspp.h
+++ b/src/devices/cpu/dspp/dspp.h
@@ -105,9 +105,9 @@ private:
static const uint32_t OUTPUT_FIFO_MASK = OUTPUT_FIFO_DEPTH - 1;
// Handlers
- devcb_write_line m_int_handler;
- devcb_read8 m_dma_read_handler;
- devcb_write8 m_dma_write_handler;
+ devcb_write_line m_int_handler;
+ devcb_read8 m_dma_read_handler;
+ devcb_write8 m_dma_write_handler;
// Internal functions
uint16_t read_op(offs_t pc);
@@ -157,8 +157,8 @@ private:
bool m_isdrc;
// Address spaces
- const address_space_config m_code_config;
- const address_space_config m_data_config;
+ const address_space_config m_code_config;
+ const address_space_config m_data_config;
address_space * m_code;
address_space * m_data;
memory_access_cache<1, -1, ENDIANNESS_BIG> *m_code_cache;
@@ -167,26 +167,26 @@ private:
struct dspp_internal_state
{
// Internal state
- int m_icount;
- uint16_t m_pc;
- uint16_t m_stack[PC_STACK_DEPTH];
- uint32_t m_stack_ptr;
- uint16_t m_rbase[4];
- uint32_t m_acc;
- uint32_t m_tclock;
-
- uint32_t m_flag_carry;
- uint32_t m_flag_zero;
- uint32_t m_flag_neg;
- uint32_t m_flag_over;
- uint32_t m_flag_exact;
- uint32_t m_flag_audlock;
- uint32_t m_flag_sleep;
-
- uint32_t m_partial_int;
- uint16_t m_op;
- uint32_t m_opidx;
- int32_t m_writeback;
+ int m_icount;
+ uint16_t m_pc;
+ uint16_t m_stack[PC_STACK_DEPTH];
+ uint32_t m_stack_ptr;
+ uint16_t m_rbase[4];
+ uint32_t m_acc;
+ uint32_t m_tclock;
+
+ uint32_t m_flag_carry;
+ uint32_t m_flag_zero;
+ uint32_t m_flag_neg;
+ uint32_t m_flag_over;
+ uint32_t m_flag_exact;
+ uint32_t m_flag_audlock;
+ uint32_t m_flag_sleep;
+
+ uint32_t m_partial_int;
+ uint16_t m_op;
+ uint32_t m_opidx;
+ int32_t m_writeback;
const char *m_format;
uint32_t m_arg0;
@@ -201,54 +201,54 @@ private:
// DMA
struct fifo_dma
{
- uint32_t m_current_addr;
- int32_t m_current_count;
- uint32_t m_next_addr;
- uint32_t m_next_count;
- uint32_t m_prev_value;
- uint32_t m_prev_current;
- uint8_t m_go_forever;
- uint8_t m_next_valid;
- uint8_t m_reserved;
- uint16_t m_fifo[DMA_FIFO_DEPTH];
- uint32_t m_dma_ptr;
- uint32_t m_dspi_ptr;
- uint32_t m_depth;
+ uint32_t m_current_addr;
+ int32_t m_current_count;
+ uint32_t m_next_addr;
+ uint32_t m_next_count;
+ uint32_t m_prev_value;
+ uint32_t m_prev_current;
+ uint8_t m_go_forever;
+ uint8_t m_next_valid;
+ uint8_t m_reserved;
+ uint16_t m_fifo[DMA_FIFO_DEPTH];
+ uint32_t m_dma_ptr;
+ uint32_t m_dspi_ptr;
+ uint32_t m_depth;
} m_fifo_dma[NUM_DMA_CHANNELS];
// Oscillator
- uint32_t m_last_frame_clock;
- uint32_t m_last_osc_count;
- uint32_t m_osc_phase;
- uint32_t m_osc_freq;
+ uint32_t m_last_frame_clock;
+ uint32_t m_last_osc_count;
+ uint32_t m_osc_phase;
+ uint32_t m_osc_freq;
// Output FIFO
- uint16_t m_outputs[NUM_OUTPUTS];
- uint16_t m_output_fifo[OUTPUT_FIFO_DEPTH];
- uint32_t m_output_fifo_start;
- uint32_t m_output_fifo_count;
+ uint16_t m_outputs[NUM_OUTPUTS];
+ uint16_t m_output_fifo[OUTPUT_FIFO_DEPTH];
+ uint32_t m_output_fifo_start;
+ uint32_t m_output_fifo_count;
// External control registers
- uint32_t m_dspx_control;
- uint32_t m_dspx_reset;
- uint32_t m_dspx_int_enable;
- uint32_t m_dspx_channel_enable;
- uint32_t m_dspx_channel_complete;
- uint32_t m_dspx_channel_direction;
- uint32_t m_dspx_channel_8bit;
- uint32_t m_dspx_channel_sqxd;
- uint32_t m_dspx_shadow_current_addr;
- uint32_t m_dspx_shadow_current_count;
- uint32_t m_dspx_shadow_next_addr;
- uint32_t m_dspx_shadow_next_count;
- uint32_t m_dspx_dmanext_int;
- uint32_t m_dspx_dmanext_enable;
- uint32_t m_dspx_consumed_int;
- uint32_t m_dspx_consumed_enable;
- uint32_t m_dspx_underover_int;
- uint32_t m_dspx_underover_enable;
- uint32_t m_dspx_audio_time;
- uint16_t m_dspx_audio_duration;
+ uint32_t m_dspx_control;
+ uint32_t m_dspx_reset;
+ uint32_t m_dspx_int_enable;
+ uint32_t m_dspx_channel_enable;
+ uint32_t m_dspx_channel_complete;
+ uint32_t m_dspx_channel_direction;
+ uint32_t m_dspx_channel_8bit;
+ uint32_t m_dspx_channel_sqxd;
+ uint32_t m_dspx_shadow_current_addr;
+ uint32_t m_dspx_shadow_current_count;
+ uint32_t m_dspx_shadow_next_addr;
+ uint32_t m_dspx_shadow_next_count;
+ uint32_t m_dspx_dmanext_int;
+ uint32_t m_dspx_dmanext_enable;
+ uint32_t m_dspx_consumed_int;
+ uint32_t m_dspx_consumed_enable;
+ uint32_t m_dspx_underover_int;
+ uint32_t m_dspx_underover_enable;
+ uint32_t m_dspx_audio_time;
+ uint16_t m_dspx_audio_duration;
//
// DRC
@@ -256,11 +256,11 @@ private:
// Core state
/* internal stuff */
- bool m_cache_dirty;
- drc_cache m_cache;
- std::unique_ptr<drcuml_state> m_drcuml;
- std::unique_ptr<dspp_frontend> m_drcfe;
- uint32_t m_drcoptions;
+ bool m_cache_dirty;
+ drc_cache m_cache;
+ std::unique_ptr<drcuml_state> m_drcuml;
+ std::unique_ptr<dspp_frontend> m_drcfe;
+ uint32_t m_drcoptions;
/* internal compiler state */
struct compiler_state
@@ -275,12 +275,12 @@ public: // TODO
void alloc_handle(drcuml_state *drcuml, uml::code_handle **handleptr, const char *name);
void load_fast_iregs(drcuml_block &block);
void save_fast_iregs(drcuml_block &block);
-// void arm7_drc_init();
-// void arm7_drc_exit();
+// void arm7_drc_init();
+// void arm7_drc_exit();
void execute_run_drc();
-// void arm7drc_set_options(uint32_t options);
-// void arm7drc_add_fastram(offs_t start, offs_t end, uint8_t readonly, void *base);
-// void arm7drc_add_hotspot(offs_t pc, uint32_t opcode, uint32_t cycles);
+// void arm7drc_set_options(uint32_t options);
+// void arm7drc_add_fastram(offs_t start, offs_t end, uint8_t readonly, void *base);
+// void arm7drc_add_hotspot(offs_t pc, uint32_t opcode, uint32_t cycles);
void flush_cache();
void compile_block(offs_t pc);
void cfunc_get_cycles();
diff --git a/src/devices/cpu/dspp/dsppdrc.cpp b/src/devices/cpu/dspp/dsppdrc.cpp
index 6c1e60b4874..2d27885e34b 100644
--- a/src/devices/cpu/dspp/dsppdrc.cpp
+++ b/src/devices/cpu/dspp/dsppdrc.cpp
@@ -23,7 +23,7 @@ using namespace uml;
// map variables
#define MAPVAR_PC M0
#define MAPVAR_CYCLES M1
-#define MAPVAR_ACC M2
+#define MAPVAR_ACC M2
// exit codes
#define EXECUTE_OUT_OF_CYCLES 0
@@ -59,8 +59,8 @@ static void cfunc_unimplemented(void *param)
void dspp_device::cfunc_unimplemented()
{
-// uint64_t op = m_core->m_arg0;
-// fatalerror("PC=%08X: Unimplemented op %04X%08X\n", m_core->m_pc, (uint32_t)(op >> 32), (uint32_t)(op));
+// uint64_t op = m_core->m_arg0;
+// fatalerror("PC=%08X: Unimplemented op %04X%08X\n", m_core->m_pc, (uint32_t)(op >> 32), (uint32_t)(op));
}
@@ -408,7 +408,7 @@ void dspp_device::static_generate_entry_point()
/* forward references */
alloc_handle(m_drcuml.get(), &m_nocode, "nocode");
-// alloc_handle(m_drcuml.get(), &m_exception[EXCEPTION_INTERRUPT], "exception_interrupt");
+// alloc_handle(m_drcuml.get(), &m_exception[EXCEPTION_INTERRUPT], "exception_interrupt");
alloc_handle(m_drcuml.get(), &m_entry, "entry");
UML_HANDLE(block, *m_entry); // handle entry
@@ -427,11 +427,11 @@ void dspp_device::static_generate_entry_point()
UML_JMPc(block, COND_Z, skip); // jz skip
#endif
-// UML_MOV(block, I0, mem(&m_core->m_pc)); // mov i0,nextpc
-// UML_MOV(block, I1, 0); // mov i1,0
-// UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
+// UML_MOV(block, I0, mem(&m_core->m_pc)); // mov i0,nextpc
+// UML_MOV(block, I1, 0); // mov i1,0
+// UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT]
-// UML_LABEL(block, skip);
+// UML_LABEL(block, skip);
/* generate a hash jump via the current mode and PC */
UML_HASHJMP(block, 0, mem(&m_core->m_pc), *m_nocode); // hashjmp <mode>,<pc>,nocode
@@ -516,7 +516,7 @@ void dspp_device::generate_sequence_instruction(drcuml_block &block, compiler_st
{
UML_MOV(block, mem(&m_core->m_pc), desc->pc); // mov [pc],desc->pc
UML_DMOV(block, mem(&m_core->m_arg0), desc->opptr.q[0]); // dmov [m_arg0],*desc->opptr.q // FIXME
-// UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc
+// UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc
}
}
}
@@ -657,7 +657,7 @@ void adsp21062_device::generate_jump(drcuml_block &block, compiler_state *compil
compiler->labelnum = compiler_temp.labelnum;
/* reset the mapvar to the current cycles and account for skipped slots */
-// compiler->cycles += desc->skipslots;
+// compiler->cycles += desc->skipslots;
UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
@@ -667,8 +667,8 @@ bool dspp_device::generate_complex_branch_opcode(drcuml_block &block, compiler_s
code_label skip_label = compiler->labelnum++;
-// generate_branch_target(block, compiler, desc, op & 0x3ff, ef2);
-// generate_condition(block, compiler, desc, ef1, true, skip_label, true);
+// generate_branch_target(block, compiler, desc, op & 0x3ff, ef2);
+// generate_condition(block, compiler, desc, ef1, true, skip_label, true);
generate_branch(block, compiler, desc);
UML_LABEL(block, skip_label);
@@ -775,93 +775,93 @@ bool dspp_device::generate_arithmetic_opcode(drcuml_block &block, compiler_state
// ACC_RESULT = I1?
switch (alu_op)
{
- case 0: // _TRA
+ case 0: // _TRA
// alu_res = alu_a;
UML_MOV(block, I2, I0);
break;
- case 1: // _NEG
+ case 1: // _NEG
// alu_res = -alu_b;
UML_SUB(block, I2, 0, I1);
break;
- case 2: // _+
+ case 2: // _+
// alu_res = alu_a + alu_b;
UML_ADD(block, I2, I0, I1);
// if ((alu_a & 0x80000) == (alu_b & 0x80000) &&
- // (alu_a & 0x80000) != (alu_res & 0x80000))
- // m_core->m_flags |= DSPI_FLAG_CC_OVER;
+ // (alu_a & 0x80000) != (alu_res & 0x80000))
+ // m_core->m_flags |= DSPI_FLAG_CC_OVER;
- // if (alu_res & 0x00100000)
- // m_core->m_flags |= DSPI_FLAG_CC_CARRY;
+ // if (alu_res & 0x00100000)
+ // m_core->m_flags |= DSPI_FLAG_CC_CARRY;
- // CC_V_MODIFIED(desc);
- // CC_C_MODIFIED(desc);
+ // CC_V_MODIFIED(desc);
+ // CC_C_MODIFIED(desc);
break;
- case 3: // _+C
+ case 3: // _+C
UML_ADD(block, I2, I0, mew);
- // alu_res = alu_a + (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
+ // alu_res = alu_a + (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
- // if (alu_res & 0x00100000)
- // m_core->m_flags |= DSPI_FLAG_CC_CARRY;
+ // if (alu_res & 0x00100000)
+ // m_core->m_flags |= DSPI_FLAG_CC_CARRY;
CC_C_USED(desc);
CC_C_MODIFIED(desc);
break;
- case 4: // _-
- // alu_res = alu_a - alu_b;
+ case 4: // _-
+ // alu_res = alu_a - alu_b;
UML_SUB(block, I2, I0, I1);
- // if ((alu_a & 0x80000) == (~alu_b & 0x80000) &&
- // (alu_a & 0x80000) != (alu_res & 0x80000))
- // m_core->m_flags |= DSPI_FLAG_CC_OVER;
+ // if ((alu_a & 0x80000) == (~alu_b & 0x80000) &&
+ // (alu_a & 0x80000) != (alu_res & 0x80000))
+ // m_core->m_flags |= DSPI_FLAG_CC_OVER;
- // if (alu_res & 0x00100000)
- // m_core->m_flags |= DSPI_FLAG_CC_CARRY;
+ // if (alu_res & 0x00100000)
+ // m_core->m_flags |= DSPI_FLAG_CC_CARRY;
CC_C_MODIFIED(desc);
CC_V_MODIFIED(desc);
break;
- case 5: // _-B
- // alu_res = alu_a - (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
+ case 5: // _-B
+ // alu_res = alu_a - (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
- // if (alu_res & 0x00100000)
- // m_core->m_flags |= DSPI_FLAG_CC_CARRY;
+ // if (alu_res & 0x00100000)
+ // m_core->m_flags |= DSPI_FLAG_CC_CARRY;
CC_C_USED(desc);
CC_C_MODIFIED(desc);
break;
- case 6: // _++
+ case 6: // _++
UML_ADD(block, I2, I0, 1);
- // alu_res = alu_a + 1;
+ // alu_res = alu_a + 1;
- // if (!(alu_a & 0x80000) && (alu_res & 0x80000))
- // m_core->m_flags |= DSPI_FLAG_CC_OVER;
+ // if (!(alu_a & 0x80000) && (alu_res & 0x80000))
+ // m_core->m_flags |= DSPI_FLAG_CC_OVER;
CC_V_MODIFIED(desc);
break;
- case 7: // _--
+ case 7: // _--
// alu_res = alu_a - 1;
UML_SUB(block, I2, I0, 1);
// if ((alu_a & 0x80000) && !(alu_res & 0x80000))
- // m_core->m_flags |= DSPI_FLAG_CC_OVER;
+ // m_core->m_flags |= DSPI_FLAG_CC_OVER;
CC_V_MODIFIED(desc);
break;
- case 8: // _TRL
+ case 8: // _TRL
//alu_res = alu_a;
UML_MOV(block, I2, I0);
break;
- case 9: // _NOT
+ case 9: // _NOT
//alu_res = ~alu_a;
UML_XOR(block, I2, I0, 0xffff);
break;
@@ -919,7 +919,7 @@ bool dspp_device::generate_arithmetic_opcode(drcuml_block &block, compiler_state
if (alu_op < 8)
{
// Arithmetic
-// m_core->m_acc = sign_extend20(alu_res) >> shift;
+// m_core->m_acc = sign_extend20(alu_res) >> shift;
// TODO: Sign Extend to 20-bits
UML_SHR(block, I2, I2, shift);
@@ -928,7 +928,7 @@ bool dspp_device::generate_arithmetic_opcode(drcuml_block &block, compiler_state
else
{
// Logical
-// m_core->m_acc = (alu_res & 0xfffff) >> shift;
+// m_core->m_acc = (alu_res & 0xfffff) >> shift;
UML_AND(block, I2, 0xfffff);
UML_SHR(block, I2, I2, shift);
UML_MAPVAR(block, MAPVAR_ACC, I2);
diff --git a/src/devices/cpu/dspp/dsppfe.cpp b/src/devices/cpu/dspp/dsppfe.cpp
index 533a020ab89..7ea800d6162 100644
--- a/src/devices/cpu/dspp/dsppfe.cpp
+++ b/src/devices/cpu/dspp/dsppfe.cpp
@@ -118,7 +118,7 @@ bool dspp_frontend::describe_special(uint16_t op, opcode_desc &desc)
// Super-special
switch ((op >> 7) & 7)
{
- case 1: // BAC - TODO: MERGE?
+ case 1: // BAC - TODO: MERGE?
{
//desc.regin[0] = m_acc;
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
@@ -167,8 +167,8 @@ bool dspp_frontend::describe_special(uint16_t op, opcode_desc &desc)
case 3: // BFM
{
// TODO: What sort of branch is this?
-// desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
-// desc.targetpc = 0; // FIXME
+// desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
+// desc.targetpc = 0; // FIXME
return false;
}
case 4: // MOVEREG
@@ -290,7 +290,7 @@ bool dspp_frontend::describe_arithmetic(uint16_t op, opcode_desc &desc)
// Does it read memory?
// Does it write memory?
-// parse_operands(numops);
+// parse_operands(numops);
if (muxa == 3 || muxb == 3)
{
@@ -349,94 +349,94 @@ bool dspp_frontend::describe_arithmetic(uint16_t op, opcode_desc &desc)
switch (alu_op)
{
- case 0: // _TRA
+ case 0: // _TRA
{
-// alu_res = alu_a;
+// alu_res = alu_a;
break;
}
- case 1: // _NEG
+ case 1: // _NEG
{
-// alu_res = -alu_b;
+// alu_res = -alu_b;
break;
}
- case 2: // _+
+ case 2: // _+
{
-// alu_res = alu_a + alu_b;
+// alu_res = alu_a + alu_b;
-// if ((alu_a & 0x80000) == (alu_b & 0x80000) &&
-// (alu_a & 0x80000) != (alu_res & 0x80000))
-// m_core->m_flags |= DSPI_FLAG_CC_OVER;
+// if ((alu_a & 0x80000) == (alu_b & 0x80000) &&
+// (alu_a & 0x80000) != (alu_res & 0x80000))
+// m_core->m_flags |= DSPI_FLAG_CC_OVER;
-// if (alu_res & 0x00100000)
-// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
+// if (alu_res & 0x00100000)
+// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
-// CC_V_MODIFIED(desc);
-// CC_C_MODIFIED(desc);
+// CC_V_MODIFIED(desc);
+// CC_C_MODIFIED(desc);
break;
}
- case 3: // _+C
+ case 3: // _+C
{
-// alu_res = alu_a + (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
+// alu_res = alu_a + (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
-// if (alu_res & 0x00100000)
-// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
+// if (alu_res & 0x00100000)
+// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
CC_C_USED(desc);
CC_C_MODIFIED(desc);
break;
}
- case 4: // _-
+ case 4: // _-
{
-// alu_res = alu_a - alu_b;
+// alu_res = alu_a - alu_b;
-// if ((alu_a & 0x80000) == (~alu_b & 0x80000) &&
-// (alu_a & 0x80000) != (alu_res & 0x80000))
-// m_core->m_flags |= DSPI_FLAG_CC_OVER;
+// if ((alu_a & 0x80000) == (~alu_b & 0x80000) &&
+// (alu_a & 0x80000) != (alu_res & 0x80000))
+// m_core->m_flags |= DSPI_FLAG_CC_OVER;
-// if (alu_res & 0x00100000)
-// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
+// if (alu_res & 0x00100000)
+// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
CC_C_MODIFIED(desc);
CC_V_MODIFIED(desc);
break;
}
- case 5: // _-B
+ case 5: // _-B
{
-// alu_res = alu_a - (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
+// alu_res = alu_a - (m_core->m_flags & DSPI_FLAG_CC_CARRY) ? (1 << 4) : 0;
-// if (alu_res & 0x00100000)
-// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
+// if (alu_res & 0x00100000)
+// m_core->m_flags |= DSPI_FLAG_CC_CARRY;
CC_C_USED(desc);
CC_C_MODIFIED(desc);
break;
}
- case 6: // _++
+ case 6: // _++
{
-// alu_res = alu_a + 1;
+// alu_res = alu_a + 1;
-// if (!(alu_a & 0x80000) && (alu_res & 0x80000))
-// m_core->m_flags |= DSPI_FLAG_CC_OVER;
+// if (!(alu_a & 0x80000) && (alu_res & 0x80000))
+// m_core->m_flags |= DSPI_FLAG_CC_OVER;
CC_V_MODIFIED(desc);
break;
}
- case 7: // _--
+ case 7: // _--
{
-// alu_res = alu_a - 1;
+// alu_res = alu_a - 1;
-// if ((alu_a & 0x80000) && !(alu_res & 0x80000))
-// m_core->m_flags |= DSPI_FLAG_CC_OVER;
+// if ((alu_a & 0x80000) && !(alu_res & 0x80000))
+// m_core->m_flags |= DSPI_FLAG_CC_OVER;
CC_V_MODIFIED(desc);
break;
}
- case 8: // _TRL
+ case 8: // _TRL
{
//alu_res = alu_a;
break;
}
- case 9: // _NOT
+ case 9: // _NOT
{
//alu_res = ~alu_a;
break;
diff --git a/src/devices/cpu/e132xs/32xsdefs.h b/src/devices/cpu/e132xs/32xsdefs.h
index b2348360a24..78413ec5863 100644
--- a/src/devices/cpu/e132xs/32xsdefs.h
+++ b/src/devices/cpu/e132xs/32xsdefs.h
@@ -173,7 +173,7 @@
#define N_SHIFT 2
#define V_SHIFT 3
#define S_SHIFT 18
-#define ILC_SHIFT 19
+#define ILC_SHIFT 19
/* SR flags */
#define GET_C ( SR & C_MASK) // bit 0 //CARRY
diff --git a/src/devices/cpu/mcs51/axc51-core.cpp b/src/devices/cpu/mcs51/axc51-core.cpp
index 339b69940c7..ddf22f27880 100644
--- a/src/devices/cpu/mcs51/axc51-core.cpp
+++ b/src/devices/cpu/mcs51/axc51-core.cpp
@@ -2,19 +2,19 @@
// copyright-holders:David Haywood
/*****************************************************************************
- AXC51-CORE (AppoTech Inc.)
+ AXC51-CORE (AppoTech Inc.)
- used in
+ used in
- AX208 SoC
+ AX208 SoC
- Notes:
+ Notes:
- AX208:
- The CPU has a bootloader that sets a few things up + copies data to RAM
- from the Flash meomry. This will need to be simulated.
+ AX208:
+ The CPU has a bootloader that sets a few things up + copies data to RAM
+ from the Flash meomry. This will need to be simulated.
*****************************************************************************/
diff --git a/src/devices/cpu/mcs51/axc51-core.h b/src/devices/cpu/mcs51/axc51-core.h
index 3d2429bb55a..6d86c682b2e 100644
--- a/src/devices/cpu/mcs51/axc51-core.h
+++ b/src/devices/cpu/mcs51/axc51-core.h
@@ -2,11 +2,11 @@
// copyright-holders:David Haywood
/*****************************************************************************
- AXC51-CORE (AppoTech Inc.)
+ AXC51-CORE (AppoTech Inc.)
- used in
+ used in
- AX208 SoC
+ AX208 SoC
*****************************************************************************/
diff --git a/src/devices/cpu/mcs51/axc51-core_dasm.cpp b/src/devices/cpu/mcs51/axc51-core_dasm.cpp
index 344d1a139db..85c5fa566a8 100644
--- a/src/devices/cpu/mcs51/axc51-core_dasm.cpp
+++ b/src/devices/cpu/mcs51/axc51-core_dasm.cpp
@@ -2,11 +2,11 @@
// copyright-holders:David Haywood
/*****************************************************************************
- AXC51-CORE (AppoTech Inc.)
+ AXC51-CORE (AppoTech Inc.)
- used in
+ used in
- AX208 SoC
+ AX208 SoC
*****************************************************************************/
@@ -17,12 +17,12 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
// SFR Registers
//0x80 -
- { 0x81, "SP" }, // Stack Pointer
+ { 0x81, "SP" }, // Stack Pointer
//0x82 -
//0x83 -
//0x84 -
//0x85 -
- { 0x86, "DPCON" }, // Data Pointer Configure Register
+ { 0x86, "DPCON" }, // Data Pointer Configure Register
{ 0x87, "PCON0" }, // Power Control 0
//0x88 -
//0x89 -
@@ -37,7 +37,7 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
//0x92 -
//0x93 -
//0x94 -
- { 0x95, "IE2" }, // Interrupt Enable 2
+ { 0x95, "IE2" }, // Interrupt Enable 2
{ 0x96, "UARTBAUDH" }, // UART Baud (high)
{ 0x97, "PWKEN" }, // Port Wakeup Enable
{ 0x98, "PWKPND" }, //Port Wakeup Flag
@@ -54,14 +54,14 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
{ 0xA3, "GP2" }, // (General Purpose Register 2)
{ 0xA4, "GP3" }, // (General Purpose Register 3)
{ 0xA5, "DACCON" }, // DAC Control Register
- { 0xA6, "DACLCH" }, // DAC Left Channel
+ { 0xA6, "DACLCH" }, // DAC Left Channel
{ 0xA7, "DACRCH" }, // DAC Right Channel
{ 0xA8, "IE0" }, // Interrupt Enable 0
{ 0xA9, "IE1" }, // Interrupt Enable 1
//0xAA -
//0xAB -
- { 0xAC, "TMR3CON" }, // Timer3 Control
- { 0xAD, "TMR3CNT" }, // Timer3 Counter
+ { 0xAC, "TMR3CON" }, // Timer3 Control
+ { 0xAD, "TMR3CNT" }, // Timer3 Counter
{ 0xAE, "TMR3PR" }, // Timer3 Period
{ 0xAF, "TMR3PSR" }, // Timer3 Pre-scalar
//0xB0 -
@@ -87,25 +87,25 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
//0xC4 -
//0xC5 -
//0xC6 -
- { 0xC7, "LCDPR" }, // LCD CS Pulse Width Register
- { 0xC8, "LCDTCON" }, // LCD WR Pulse Timing Control Register
+ { 0xC7, "LCDPR" }, // LCD CS Pulse Width Register
+ { 0xC8, "LCDTCON" }, // LCD WR Pulse Timing Control Register
//0xC9 -
//0xCA -
//0xCB -
//0xCC -
//0xCD -
//0xCE -
- { 0xCF, "MICCON" }, // MIC Control
- { 0xD0, "PSW" }, // Processor Status Word
+ { 0xCF, "MICCON" }, // MIC Control
+ { 0xD0, "PSW" }, // Processor Status Word
{ 0xD1, "PGCON" }, // Power Gate Control Register
- { 0xD2, "ADCCON" }, // SARADC Control
+ { 0xD2, "ADCCON" }, // SARADC Control
{ 0xD3, "PCON2" }, // Power Control 2
{ 0xD4, "ADCDATAL" }, // SARADC Buffer Low Byte Control
- { 0xD5, "ADCDATAH" }, // SARADC Buffer High Byte Control
+ { 0xD5, "ADCDATAH" }, // SARADC Buffer High Byte Control
{ 0xD6, "SPIDMAADDR" }, // SPI DMA Start Address
{ 0xD7, "SPIDMACNT" }, // SPI DMA counter
{ 0xD8, "SPICON" }, // SPI Control
- { 0xD9, "SPIBUF" }, // SPI Data Buffer
+ { 0xD9, "SPIBUF" }, // SPI Data Buffer
{ 0xDA, "SPIBAUD" }, // SPI Baud Rate
{ 0xDB, "CLKCON" }, // Clock Control
// 0xDC -
@@ -122,7 +122,7 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
{ 0xE7, "ER01" }, // ER01 /
{ 0xE8, "ER10" }, // ER10 \- ER1 (16-bit)
{ 0xE9, "ER11" }, // ER11 /
- { 0XEA, "ER20" }, // ER20 \- ER2 (16-bit)
+ { 0xEA, "ER20" }, // ER20 \- ER2 (16-bit)
{ 0xEB, "ER21" }, // ER21 /
{ 0xEC, "ER30" }, // ER30 \- ER3 (16-bit)
{ 0xED, "ER31" }, // ER31 /
@@ -138,12 +138,12 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
{ 0xF7, "WDTCON" }, // Watchdog Control
{ 0xF8, "TMR0CON" }, // Timer0 Control
{ 0xF9, "TMR0CNT" }, // Timer0 Counter
- { 0xFA, "TMR0PR" }, // Timer0 Period
+ { 0xFA, "TMR0PR" }, // Timer0 Period
{ 0xFB, "TMR0PSR" }, // Timer0 Pre-scalar
- { 0xFC, "UARTSTA" }, // UART Status
+ { 0xFC, "UARTSTA" }, // UART Status
{ 0xFD, "UARTCON" }, // UART Control
{ 0xFE, "UARTBAUD" }, // UART Baud (low)
- { 0xFF, "UARTDATA" }, // UART Communication Data
+ { 0xFF, "UARTDATA" }, // UART Communication Data
// Upper Registers
@@ -163,7 +163,7 @@ const axc51core_disassembler::mem_info axc51core_disassembler::axc51core_names[]
{ 0x3040, "ADCBAUD" }, //S ARADC Baud
- { 0x3070, "DACPTR" }, // DAC DMA Pointer
+ { 0x3070, "DACPTR" }, // DAC DMA Pointer
{ 0x3071, "DACCNT" }, // DAC DMA Counter
{ -1 }
@@ -175,104 +175,104 @@ axc51core_disassembler::axc51core_disassembler() : mcs51_disassembler(axc51core_
/* Extended 16-bit Opcodes
Opcode/params | Operation | Flags touched
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
INCDPi | |
| DPTRi = DPTRi + 1 |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
DECDPi | |
| DPTRi = DPTRi - 1 |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ADDDPi | |
| DPTRi = DPTRi + {R8, B} |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
SUBDPi | |
| DPTRi = DPTRi - {R8, B} |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
INC2DPi | |
| DPTRi = DPTRi + 2 |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
DEC2DPi | |
| DPTRi = DPTRi - 2 |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ROTR8 | |
EACC, ER8 | Rotate Right ACC by R8 &0x3 bits |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ROTL8 | |
EACC, ER8 | Rotate Left ACC by R8 &0x3 bits |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ADD16 | |
ERp, DPTRi, ERn | ERp = XRAM + ERn + EC | EZ, EC
DPTRi, ERn, ERp | XRAM = ERn + ERp + EC |
ERp, ERn, ERm | ERp = ERn + ERm + EC |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
SUB16 | |
ERp, DPTRi, ERn | ERp = XRAM - ERn - EC | EZ, EC
DPTRi, ERn, ERp | XRAM = ERn - ERp - EC |
ERp, ERn, ERm | ERp = ERn - ERm - EC |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
NOT16 | |
ERn | ERn = ~ERn |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
CLR16 | |
ERn | ERn = 0 |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
INC16 | |
ERn | ERn = ERn + 1 | EZ
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
DEC16 | |
ERn | ERn = ERn - 1 | EZ
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ANL16 | |
ERn, DPTRi | ERn = XRAM & ERn | EZ
DPTRi, ERn | XRAM = XRAM & ERn |
ERn, ERm | ERn = ERn & ERm |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ORL16 | |
ERn, DPTRi | ERn = XRAM | ERn | EZ
DPTRi, ERn | XRAM = XRAM | ERn |
ERn, ERm | ERn = ERn | ERm |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
XRL16 | |
ERn, DPTRi | ERn = XRAM ^ ERn | EZ
DPTRi, ERn | XRAM = XRAM ^ ERn |
ERn, ERm | ERn = ERn ^ ERm |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
MOV16 | |
ERn, DPTRi | ERn = XRAM | EZ
DPTRi, ERn | XRAM = ERn |
ERn, ERm | ERn = ERm |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
MUL16 (signed) | |
ERn, ERm | {ERn, ERm} = ERn * ERm |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
MULS16 (sign, satur) | |
ERn, ERm | {ERn, ERm} = ERn * ERm |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ROTR16 | |
ERn, ER8 | Rotate Right ERn by ER8 & 0xf bits |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ROTL16 | |
ERn, ER8 | Rotate Left ERn by ER8 & 0xf bits |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
SHIFTL (lsl) | |
ERn, ER8 | ERn = ERn >> (ER8 & 0xf) |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
SHIFTR (asr) | |
ERn, ER8 | ERn = ERn >> (ER8 & 0xf) |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
ADD16 (saturate) | |
-ERp, DPTRi, ERn | ERp = XRAM + ERn + EC | EZ, EC
+ERp, DPTRi, ERn | ERp = XRAM + ERn + EC | EZ, EC
DPTRi, ERn, ERp | XRAM = ERn + ERp + EC |
ERp, ERn, ERm | ERp = ERn + ERm + EC |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
SUB16 (saturate) | |
-ERp, DPTRi, ERn | ERp = XRAM - ERn - EC | EZ, EC
+ERp, DPTRi, ERn | ERp = XRAM - ERn - EC | EZ, EC
DPTRi, ERn, ERp | XRAM = ERn - ERp - EC |
ERp, ERn, ERm | ERp = ERn - ERm - EC |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
SWAP16 | |
ERn | Swap upper and lower 8-bits of ERn |
-----------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------
access to 16-bit registers is mapped in SFR space, from 0xE6 (note, changing SFR bank does NOT update the actual registers)
diff --git a/src/devices/cpu/mcs51/axc51-core_dasm.h b/src/devices/cpu/mcs51/axc51-core_dasm.h
index 9eccdd921fd..3f720fef568 100644
--- a/src/devices/cpu/mcs51/axc51-core_dasm.h
+++ b/src/devices/cpu/mcs51/axc51-core_dasm.h
@@ -2,11 +2,11 @@
// copyright-holders:David Haywood
/*****************************************************************************
- AXC51-CORE (AppoTech Inc.)
+ AXC51-CORE (AppoTech Inc.)
- used in
+ used in
- AX208 SoC
+ AX208 SoC
*****************************************************************************/
diff --git a/src/devices/cpu/powerpc/ppccom.h b/src/devices/cpu/powerpc/ppccom.h
index ef3f917c426..918ca62a4c4 100644
--- a/src/devices/cpu/powerpc/ppccom.h
+++ b/src/devices/cpu/powerpc/ppccom.h
@@ -303,10 +303,10 @@ enum
#define MSR603_TGPR 0x00020000 /* Temporary GPR Remapping */
/* ESA Save and Restore Register bits - 602 */
-#define SPR602_ESASRR_EE 0x00000001 /* External Interrupt Enable */
-#define SPR602_ESASRR_SA 0x00000002 /* Supervisor access mode */
-#define SPR602_ESASRR_AP 0x00000004 /* Access privilege state */
-#define SPR602_ESASRR_PR 0x00000008 /* Privilege Level */
+#define SPR602_ESASRR_EE 0x00000001 /* External Interrupt Enable */
+#define SPR602_ESASRR_SA 0x00000002 /* Supervisor access mode */
+#define SPR602_ESASRR_AP 0x00000004 /* Access privilege state */
+#define SPR602_ESASRR_PR 0x00000008 /* Privilege Level */
/* DSISR bits for DSI/alignment exceptions */
#define DSISR_DIRECT 0x80000000 /* DSI: direct-store error interrupt */
diff --git a/src/devices/cpu/powerpc/ppcdrc.cpp b/src/devices/cpu/powerpc/ppcdrc.cpp
index e783328bf4b..00c635fc95c 100644
--- a/src/devices/cpu/powerpc/ppcdrc.cpp
+++ b/src/devices/cpu/powerpc/ppcdrc.cpp
@@ -578,7 +578,7 @@ static void cfunc_ppccom_mismatch(void *param)
void ppc_device::ppc_cfunc_ppccom_mismatch()
{
-// printf("cfunc_ppccom_mismatch %08X\n", m_core->pc);
+// printf("cfunc_ppccom_mismatch %08X\n", m_core->pc);
}
static void cfunc_ppccom_tlb_fill(void *param)
diff --git a/src/devices/machine/spg2xx.h b/src/devices/machine/spg2xx.h
index e851531693f..0573daef7ac 100644
--- a/src/devices/machine/spg2xx.h
+++ b/src/devices/machine/spg2xx.h
@@ -27,11 +27,11 @@
ND - unknown - Wireless Air 60
ND - Likely many more
- Also on this hardware:
+ Also on this hardware:
- name PCB ID ROM width TSOP pads ROM size SEEPROM die markings
- Radica Play TV Football 2 L7278 x16 48 not dumped no Sunplus
- Dream Life ? x16 48 not dumped no Sunplus
+ name PCB ID ROM width TSOP pads ROM size SEEPROM die markings
+ Radica Play TV Football 2 L7278 x16 48 not dumped no Sunplus
+ Dream Life ? x16 48 not dumped no Sunplus
**********************************************************************/
diff --git a/src/devices/machine/t10mmc.cpp b/src/devices/machine/t10mmc.cpp
index af1fd7e75d9..c20f29296e4 100644
--- a/src/devices/machine/t10mmc.cpp
+++ b/src/devices/machine/t10mmc.cpp
@@ -797,8 +797,8 @@ void t10mmc::WriteData( uint8_t *data, int dataLength )
m_device->logerror("Ch 1 route: %x vol: %x\n", data[10], data[11]);
m_device->logerror("Ch 2 route: %x vol: %x\n", data[12], data[13]);
m_device->logerror("Ch 3 route: %x vol: %x\n", data[14], data[15]);
- m_cdda->set_output_gain(0, data[17] ? 1.0f : 0.0f);
- m_cdda->set_output_gain(1, data[19] ? 1.0f : 0.0f);
+ m_cdda->set_output_gain(0, data[17] ? 1.0f : 0.0f);
+ m_cdda->set_output_gain(1, data[19] ? 1.0f : 0.0f);
break;
}
break;
diff --git a/src/devices/sound/scspdsp.cpp b/src/devices/sound/scspdsp.cpp
index 678411b361f..ea84b1e72b9 100644
--- a/src/devices/sound/scspdsp.cpp
+++ b/src/devices/sound/scspdsp.cpp
@@ -160,7 +160,7 @@ void SCSPDSP::Step()
else if (IRA <= 0x2F)
INPUTS = MIXS[IRA - 0x20] << 4; //MIXS is 20 bit
else if (IRA <= 0x31)
- INPUTS = EXTS[IRA - 0x30] << 8; //EXTS is 16 bit
+ INPUTS = EXTS[IRA - 0x30] << 8; //EXTS is 16 bit
else
return;
diff --git a/src/devices/sound/swp30.cpp b/src/devices/sound/swp30.cpp
index 0bcb43cda0e..56870df5ec7 100644
--- a/src/devices/sound/swp30.cpp
+++ b/src/devices/sound/swp30.cpp
@@ -117,7 +117,7 @@
offset is o << 10. There are no alignment issues, e.g. you can have
a buffer at 0x28000 which is 0x10000 samples long.
-
+
fp<nnn> fixed point 2.14 value associated with instruction nnn
of<nn> 16-bits offset associated with instruction 3*nn
lfo<nn> LFO registers
@@ -561,7 +561,7 @@ u16 swp30_device::freq_r(offs_t offset)
void swp30_device::freq_w(offs_t offset, u16 data)
{
u8 chan = offset >> 6;
- // delta is 4*256 per octave, positive means higher freq, e.g 4.10 format.
+ // delta is 4*256 per octave, positive means higher freq, e.g 4.10 format.
s16 v = data & 0x2000 ? data | 0xc000 : data;
if(0 && m_freq[chan] != data)
logerror("snd chan %02x freq %c%c %d.%03x\n", chan, data & 0x8000 ? '#' : '.', data & 0x4000 ? '#' : '.', v / 1024, (v < 0 ? -v : v) & 0x3ff);
@@ -697,8 +697,8 @@ template<int sel> void swp30_device::prg_lfo_w(offs_t offset, u16 data)
offs_t adr = (offset >> 6)*2 + sel;
m_program_plfo[adr] = data;
- static const int dt[8] = { 0, 32, 64, 128, 256, 512, 1024, 2048 };
- static const int sh[8] = { 0, 0, 1, 2, 3, 4, 5, 6 };
+ static const int dt[8] = { 0, 32, 64, 128, 256, 512, 1024, 2048 };
+ static const int sh[8] = { 0, 0, 1, 2, 3, 4, 5, 6 };
int scale = (data >> 5) & 7;
int step = ((data & 31) << sh[scale]) + dt[scale];
diff --git a/src/devices/video/i82730.h b/src/devices/video/i82730.h
index e0b1c4729d6..03165358a22 100644
--- a/src/devices/video/i82730.h
+++ b/src/devices/video/i82730.h
@@ -18,7 +18,7 @@
//**************************************************************************
#define I82730_UPDATE_ROW(name) \
- void name(bitmap_rgb32 &bitmap, uint16_t *data, uint8_t lc, uint16_t y, int x_count)
+ void name(bitmap_rgb32 &bitmap, uint16_t *data, uint8_t lc, uint16_t y, int x_count)
// ======================> i82730_device
diff --git a/src/mame/audio/mario.cpp b/src/mame/audio/mario.cpp
index 95c073be458..f9b912e8305 100644
--- a/src/mame/audio/mario.cpp
+++ b/src/mame/audio/mario.cpp
@@ -638,9 +638,9 @@ void mario_state::masao_sound_map(address_map &map)
void mario_state::mario_audio(machine_config &config)
{
#if USE_8039
- i8039_device &audiocpu(I8039(config, "audiocpu", I8035_CLOCK)); /* 730 kHz */
+ i8039_device &audiocpu(I8039(config, "audiocpu", I8035_CLOCK)); /* 730 kHz */
#else
- m58715_device &audiocpu(M58715(config, m_audiocpu, I8035_CLOCK)); /* 730 kHz */
+ m58715_device &audiocpu(M58715(config, m_audiocpu, I8035_CLOCK)); /* 730 kHz */
#endif
audiocpu.set_addrmap(AS_PROGRAM, &mario_state::mario_sound_map);
audiocpu.set_addrmap(AS_IO, &mario_state::mario_sound_io_map);
diff --git a/src/mame/drivers/balsente.cpp b/src/mame/drivers/balsente.cpp
index 6b74d513ae6..55685a5dc79 100644
--- a/src/mame/drivers/balsente.cpp
+++ b/src/mame/drivers/balsente.cpp
@@ -2279,7 +2279,7 @@ ROM_END
-Pin 11 : CHANNEL A
-Pin 12 : CHANNEL B
-Pin 13 : key (unused)
--Pin 14 : GND
+-Pin 14 : GND
*/
ROM_START( triviaes4 )
ROM_REGION( 0x20000, "maincpu", 0 ) // all 27256, ROM loading order probably wrong
diff --git a/src/mame/drivers/brkthru.cpp b/src/mame/drivers/brkthru.cpp
index 4ac5a5466fe..80788e9a28c 100644
--- a/src/mame/drivers/brkthru.cpp
+++ b/src/mame/drivers/brkthru.cpp
@@ -766,7 +766,7 @@ ROM_START( darwin )
// A PCB has been found with the first PROM substituted with a TBP28S42 (4b56a744) SHA1(5fdc336d90c8a289c146c66f241dd217fc11bf35), see brkthrut ROM loading for how they did it.
// With that in mind, there's a one byte difference at 0x55 (0xf0 instead of 0x70). It is unknown if it's bitrot or if it's intended.
- ROM_REGION( 0x0200, "proms", 0 )
+ ROM_REGION( 0x0200, "proms", 0 )
ROM_LOAD( "df.12", 0x0000, 0x0100, CRC(89b952ef) SHA1(77dc4020a2e25f81fae1182d58993cf09d13af00) ) /* red and green component */
ROM_LOAD( "df.13", 0x0100, 0x0100, CRC(d595e91d) SHA1(5e9793f6602455c79afdc855cd13183a7f48ab1e) ) /* blue component */
diff --git a/src/mame/drivers/esripsys.cpp b/src/mame/drivers/esripsys.cpp
index 7d6b0b55da9..16ddf2c927b 100644
--- a/src/mame/drivers/esripsys.cpp
+++ b/src/mame/drivers/esripsys.cpp
@@ -692,7 +692,7 @@ void esripsys_state::esripsys(machine_config &config)
/* Video hardware */
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(ESRIPSYS_PIXEL_CLOCK, ESRIPSYS_HTOTAL, ESRIPSYS_HBLANK_END, ESRIPSYS_HBLANK_START,
- ESRIPSYS_VTOTAL, ESRIPSYS_VBLANK_END, ESRIPSYS_VBLANK_START);
+ ESRIPSYS_VTOTAL, ESRIPSYS_VBLANK_END, ESRIPSYS_VBLANK_START);
m_screen->set_screen_update(FUNC(esripsys_state::screen_update_esripsys));
m_screen->set_video_attributes(VIDEO_ALWAYS_UPDATE);
diff --git a/src/mame/drivers/fastinvaders.cpp b/src/mame/drivers/fastinvaders.cpp
index 29a0cf5cae0..2fe2640fef1 100644
--- a/src/mame/drivers/fastinvaders.cpp
+++ b/src/mame/drivers/fastinvaders.cpp
@@ -129,7 +129,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(fastinvaders_state::scanline_timer)
{
//logerror("scanline\n");
m_dma8257->dreq1_w(0x01);
- m_dma8257->hlda_w(1);
+ m_dma8257->hlda_w(1);
}
*/
}
@@ -204,7 +204,7 @@ WRITE8_MEMBER(fastinvaders_state::dark_2_clr)
m_dma8257->dreq2_w(0x00);
}
/* if (!data)
- {
+ {
m_dma1 = 0;
}
*/
diff --git a/src/mame/drivers/funworld.cpp b/src/mame/drivers/funworld.cpp
index 7842a114092..4419e967472 100644
--- a/src/mame/drivers/funworld.cpp
+++ b/src/mame/drivers/funworld.cpp
@@ -4517,24 +4517,24 @@ ROM_END
New Biliard 98
CPUs:
- 1x R65C02P2 u1 8-bit Microprocessor - main
- 1x MC68B45P u8 CRT Controller (CRTC)
- 2x MC68B21CP u29, u30 Peripheral Interface Adapter
- 1x 89C10 u34 Programmable Sound Generator - sound
- 1x TDA2003 u33 Audio Amplifier - sound
- 1x oscillator 16.000000MHz os1
+ 1x R65C02P2 u1 8-bit Microprocessor - main
+ 1x MC68B45P u8 CRT Controller (CRTC)
+ 2x MC68B21CP u29, u30 Peripheral Interface Adapter
+ 1x 89C10 u34 Programmable Sound Generator - sound
+ 1x TDA2003 u33 Audio Amplifier - sound
+ 1x oscillator 16.000000MHz os1
ROMs:
- 3x 27C256 u2, u20, u21 dumped
- 1x AM27S29PC u25 dumped
+ 3x 27C256 u2, u20, u21 dumped
+ 1x AM27S29PC u25 dumped
RAMs:
- 1x KM6264BL-10L-12 u13
- 1x GM76C28A-10 u3
+ 1x KM6264BL-10L-12 u13
+ 1x GM76C28A-10 u3
PLDs:
- 2x GAL20V8A-25LP u22, u23 read protected
- 1x PALCE16V8H-15PC/4 u5 read protected
+ 2x GAL20V8A-25LP u22, u23 read protected
+ 1x PALCE16V8H-15PC/4 u5 read protected
Others:
1x 28x2 JAMMA edge connector
@@ -4544,7 +4544,7 @@ ROM_END
Notes:
PCB is marked: "top" and "C.M.C. POOL 10" on component side
- PCB is marked: "bottom" and "POOL 10 C.M.C" on solder side
+ PCB is marked: "bottom" and "POOL 10 C.M.C" on solder side
*/
ROM_START( biliard )
diff --git a/src/mame/drivers/goldstar.cpp b/src/mame/drivers/goldstar.cpp
index c1d8b53a209..7a31ddf98f9 100644
--- a/src/mame/drivers/goldstar.cpp
+++ b/src/mame/drivers/goldstar.cpp
@@ -799,8 +799,8 @@ WRITE8_MEMBER(goldstar_state::cm_coincount_w)
machine().bookkeeping().coin_counter_w(3, data & 0x08); /* Counter 4 Coin D */
machine().bookkeeping().coin_counter_w(4, data & 0x01); /* Counter 5 Payout */
-// if (data & 0x86) // triggered by fb2010
-// popmessage("counters: %02X", data);
+// if (data & 0x86) // triggered by fb2010
+// popmessage("counters: %02X", data);
}
void cmaster_state::cm_portmap(address_map &map)
@@ -5057,125 +5057,125 @@ static INPUT_PORTS_START( fb2010 ) // hit 'start1' to init NVRAM for first time
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings")
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats")
PORT_START("DSW1")
- PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:1")
+ PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:1")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:2")
+ PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:2")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:5")
+ PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
+ PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW2")
- PORT_DIPNAME( 0x01, 0x01, "Double Up" ) PORT_DIPLOCATION("DSW2:1")
+ PORT_DIPNAME( 0x01, 0x01, "Double Up" ) PORT_DIPLOCATION("DSW2:1")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
- PORT_DIPNAME( 0x02, 0x02, "Skill Spin" ) PORT_DIPLOCATION("DSW2:2")
+ PORT_DIPNAME( 0x02, 0x02, "Skill Spin" ) PORT_DIPLOCATION("DSW2:2")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:3")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:5")
+ PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8")
+ PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW3")
- PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:1")
+ PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:1")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:2")
+ PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:2")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:3")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:5")
+ PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:8")
+ PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW4")
- PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:1")
+ PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:1")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:2")
+ PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:2")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:3")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:5")
+ PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:8")
+ PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW5")
- PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:1")
+ PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:1")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:2")
+ PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:2")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:3")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x08, 0x08, "Show Odds / Title" ) PORT_DIPLOCATION("DSW5:4")
+ PORT_DIPNAME( 0x08, 0x08, "Show Odds / Title" ) PORT_DIPLOCATION("DSW5:4")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:5")
+ PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, "Show 'Game' Text" ) PORT_DIPLOCATION("DSW5:8") // causes corruption in D-Up game?
diff --git a/src/mame/drivers/gsword.cpp b/src/mame/drivers/gsword.cpp
index e47324fab48..b00a0829919 100644
--- a/src/mame/drivers/gsword.cpp
+++ b/src/mame/drivers/gsword.cpp
@@ -692,7 +692,7 @@ static INPUT_PORTS_START( gsword )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unused ) ) PORT_DIPLOCATION("A:2")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("A:3,4,5")
+ PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("A:3,4,5")
PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
PORT_DIPSETTING( 0x04, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
diff --git a/src/mame/drivers/harddriv.cpp b/src/mame/drivers/harddriv.cpp
index ea2dd4ca874..6e3406f6ed9 100644
--- a/src/mame/drivers/harddriv.cpp
+++ b/src/mame/drivers/harddriv.cpp
@@ -1523,7 +1523,7 @@ void harddriv_state::driver_msp(machine_config &config)
m_msp->set_pixel_clock(5000000);
m_msp->set_pixels_per_clock(2);
m_msp->output_int().set(FUNC(harddriv_state::hdmsp_irq_gen));
- m_msp->set_screen("screen");
+ m_msp->set_screen("screen");
config.device_remove("slapstic");
}
@@ -1550,18 +1550,18 @@ void harddriv_state::multisync_nomsp(machine_config &config)
/* Multisync board with MSP (used by Hard Drivin' compact) */
void harddriv_state::multisync_msp(machine_config &config)
{
- multisync_nomsp(config);
-
- /* basic machine hardware */
- TMS34010(config, m_msp, XTAL(50'000'000));
- m_msp->set_addrmap(AS_PROGRAM, &harddriv_state::driver_msp_map);
- m_msp->set_halt_on_reset(true);
- m_msp->set_pixel_clock(5000000);
- m_msp->set_pixels_per_clock(2);
- m_msp->output_int().set(FUNC(harddriv_state::hdmsp_irq_gen));
- m_msp->set_screen("screen");
-
- config.device_remove("slapstic");
+ multisync_nomsp(config);
+
+ /* basic machine hardware */
+ TMS34010(config, m_msp, XTAL(50'000'000));
+ m_msp->set_addrmap(AS_PROGRAM, &harddriv_state::driver_msp_map);
+ m_msp->set_halt_on_reset(true);
+ m_msp->set_pixel_clock(5000000);
+ m_msp->set_pixels_per_clock(2);
+ m_msp->output_int().set(FUNC(harddriv_state::hdmsp_irq_gen));
+ m_msp->set_screen("screen");
+
+ config.device_remove("slapstic");
}
diff --git a/src/mame/drivers/hh_tms1k.cpp b/src/mame/drivers/hh_tms1k.cpp
index b13260315e6..11fdf0425e9 100644
--- a/src/mame/drivers/hh_tms1k.cpp
+++ b/src/mame/drivers/hh_tms1k.cpp
@@ -6121,19 +6121,19 @@ void bshipb_state::bshipb(machine_config &config)
/* sound hardware */
SPEAKER(config, "mono").front_center();
SN76477(config, m_sn);
- m_sn->set_noise_params(RES_K(47), RES_K(100), CAP_P(47)); // R18, R17, C8
- m_sn->set_decay_res(RES_M(3.3)); // R16
- m_sn->set_attack_params(CAP_U(0.47), RES_K(15)); // C7, R20
- m_sn->set_amp_res(RES_K(100)); // R19
- m_sn->set_feedback_res(RES_K(39)); // R7
- m_sn->set_vco_params(5.0 * RES_VOLTAGE_DIVIDER(RES_K(47), RES_K(33)), CAP_U(0.01), RES_K(270)); // R15/R14, C5, switchable R5/R3/R4
+ m_sn->set_noise_params(RES_K(47), RES_K(100), CAP_P(47)); // R18, R17, C8
+ m_sn->set_decay_res(RES_M(3.3)); // R16
+ m_sn->set_attack_params(CAP_U(0.47), RES_K(15)); // C7, R20
+ m_sn->set_amp_res(RES_K(100)); // R19
+ m_sn->set_feedback_res(RES_K(39)); // R7
+ m_sn->set_vco_params(5.0 * RES_VOLTAGE_DIVIDER(RES_K(47), RES_K(33)), CAP_U(0.01), RES_K(270)); // R15/R14, C5, switchable R5/R3/R4
m_sn->set_pitch_voltage(5.0);
- m_sn->set_slf_params(CAP_U(22), RES_K(750)); // switchable C4, switchable R13/R12
- m_sn->set_oneshot_params(0, RES_INF); // NC, switchable R11
- m_sn->set_vco_mode(0); // switchable
- m_sn->set_mixer_params(0, 0, 0); // switchable, GND, GND
- m_sn->set_envelope_params(1, 0); // Vreg, GND
- m_sn->set_enable(0); // switchable
+ m_sn->set_slf_params(CAP_U(22), RES_K(750)); // switchable C4, switchable R13/R12
+ m_sn->set_oneshot_params(0, RES_INF); // NC, switchable R11
+ m_sn->set_vco_mode(0); // switchable
+ m_sn->set_mixer_params(0, 0, 0); // switchable, GND, GND
+ m_sn->set_envelope_params(1, 0); // Vreg, GND
+ m_sn->set_enable(0); // switchable
m_sn->add_route(ALL_OUTPUTS, "mono", 0.35);
}
diff --git a/src/mame/drivers/hikaru.cpp b/src/mame/drivers/hikaru.cpp
index f7d455bfe1f..22aebe99321 100644
--- a/src/mame/drivers/hikaru.cpp
+++ b/src/mame/drivers/hikaru.cpp
@@ -531,8 +531,8 @@ void hikaru_state::hikaru(machine_config &config)
PALETTE(config, "palette", 0x1000);
-// SPEAKER(config, "lspeaker").front_left();
-// SPEAKER(config, "rspeaker").front_right();
+// SPEAKER(config, "lspeaker").front_left();
+// SPEAKER(config, "rspeaker").front_right();
// MCFG_DEVICE_ADD("aica", AICA, (XTAL(33'868'800)*2)/3) // 67.7376MHz(2*33.8688MHz), div 3 for audio block // 33.8688MHz on Board
// MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
diff --git a/src/mame/drivers/hp3478a.cpp b/src/mame/drivers/hp3478a.cpp
index 7de7253a65e..d77af3c8327 100644
--- a/src/mame/drivers/hp3478a.cpp
+++ b/src/mame/drivers/hp3478a.cpp
@@ -11,7 +11,7 @@
*
* Current status : runs, AD LINK ERROR on stock ROM due to unimplemented AD link
* - patching the AD comms, we get to a mostly functional state (for patch examples,
-* see https://github.com/fenugrec/hp3478a_rompatch )
+* see https://github.com/fenugrec/hp3478a_rompatch )
*
* TODO
* - split out LCD driver code. It seems common to other HP equipment of the
@@ -34,7 +34,7 @@ ROM : 2764 (64kbit, org 8kB)
RAM : 5101 , 256 * 4bit (!), battery-backed calibration data
GPIB: i8291
Display : unknown; similar protocol for HP 3457A documented on
- http://www.eevblog.com/forum/projects/led-display-for-hp-3457a-multimeter-i-did-it-)/25/
+ http://www.eevblog.com/forum/projects/led-display-for-hp-3457a-multimeter-i-did-it-)/25/
@@ -47,7 +47,7 @@ P20 : disp.clk1
P21 : !CS for GPIB, and disp.IWA
P22 : !CS for DIPswitch; disp.ISA (for instructions)
P23 = !OE for RAM ; disp.sync (enable instruction)
-P24 = disp.PWO (enable)
+P24 = disp.PWO (enable)
P25 = disp.clk2
P26 : address bit12 ! (0x1000) => hardware banking
P27 : data out thru isol, to analog CPU
@@ -65,18 +65,18 @@ T1 : data in thru isol, from analog CPU (opcodes jt1 / jnt1)
#define CPU_CLOCK XTAL(5'856'000)
/* port pin/bit defs. Would be nice if mcs48.h had these */
-#define P20 (1 << 0)
-#define P21 (1 << 1)
-#define P22 (1 << 2)
-#define P23 (1 << 3)
-#define P24 (1 << 4)
-#define P25 (1 << 5)
-#define P26 (1 << 6)
-#define P27 (1 << 7)
+#define P20 (1 << 0)
+#define P21 (1 << 1)
+#define P22 (1 << 2)
+#define P23 (1 << 3)
+#define P24 (1 << 4)
+#define P25 (1 << 5)
+#define P26 (1 << 6)
+#define P27 (1 << 7)
-#define A12_PIN P26
+#define A12_PIN P26
#define CALRAM_CS P23
#define DIPSWITCH_CS P22
#define GPIB_CS P21
@@ -87,7 +87,7 @@ T1 : data in thru isol, from analog CPU (opcodes jt1 / jnt1)
#define DISP_IWA P21
#define DISP_CK1 P20
//don't care about CK2 since it's supposed to be a delayed copy of CK1
-#define DISP_MASK (DISP_PWO | DISP_SYNC | DISP_ISA | DISP_IWA | DISP_CK1) //used for edge detection
+#define DISP_MASK (DISP_PWO | DISP_SYNC | DISP_ISA | DISP_IWA | DISP_CK1) //used for edge detection
// IO banking : indexes of m_iobank maps
#define CALRAM_ENTRY 0
@@ -97,13 +97,13 @@ T1 : data in thru isol, from analog CPU (opcodes jt1 / jnt1)
/**** optional debug outputs, must be before #include logmacro.*/
#define DEBUG_PORTS (LOG_GENERAL << 1)
#define DEBUG_BANKING (LOG_GENERAL << 2)
-#define DEBUG_BUS (LOG_GENERAL << 3) //not used after all
+#define DEBUG_BUS (LOG_GENERAL << 3) //not used after all
#define DEBUG_KEYPAD (LOG_GENERAL << 4)
-#define DEBUG_LCD (LOG_GENERAL << 5) //low level
+#define DEBUG_LCD (LOG_GENERAL << 5) //low level
#define DEBUG_LCD2 (LOG_GENERAL << 6)
#define DEBUG_CAL (LOG_GENERAL << 7)
-#define VERBOSE (DEBUG_BUS) //can be combined, like (DEBUG_CAL | DEBUG_KEYPAD)
+#define VERBOSE (DEBUG_BUS) //can be combined, like (DEBUG_CAL | DEBUG_KEYPAD)
#include "logmacro.h"
@@ -130,7 +130,7 @@ public:
protected:
virtual void machine_start() override;
- //virtual void machine_reset() override; //not needed?
+ //virtual void machine_reset() override; //not needed?
DECLARE_READ8_MEMBER(p1read);
DECLARE_WRITE8_MEMBER(p1write);
@@ -176,14 +176,14 @@ protected:
REG_C,
DISCARD
} m_lcdiwa;
- uint8_t m_lcd_chrbuf[12]; //raw digits (not ASCII)
- uint8_t m_lcd_text[13]; //mapped to ASCII, only for debug output
+ uint8_t m_lcd_chrbuf[12]; //raw digits (not ASCII)
+ uint8_t m_lcd_text[13]; //mapped to ASCII, only for debug output
uint32_t m_lcd_segdata[12];
///////////////////////////
- uint8_t m_p2_oldstate; //used to detect edges on Port2 IO pins. Should be saveable ?
- uint8_t m_p1_oldstate; //for P17 edge detection (WDT reset)
+ uint8_t m_p2_oldstate; //used to detect edges on Port2 IO pins. Should be saveable ?
+ uint8_t m_p1_oldstate; //for P17 edge detection (WDT reset)
};
@@ -200,7 +200,7 @@ READ8_MEMBER( hp3478a_state::p1read )
// for each column, set Px=0 for pressed buttons (active low)
for (i = 0; i < 4; i++) {
if (!(data & (0x10 << i))) {
- data &= (0xF0 | m_keypad[i]->read()); //not sure if the undefined upper bits will read as 1 ?
+ data &= (0xF0 | m_keypad[i]->read()); //not sure if the undefined upper bits will read as 1 ?
}
}
LOGMASKED(DEBUG_KEYPAD, "port1 read: 0x%02X\n", data);
@@ -383,8 +383,8 @@ void hp3478a_state::lcd_map_chars()
int i;
LOGMASKED(DEBUG_LCD2, "LCD : map ");
for (i=0; i < 12; i++) {
- bool dp = m_lcd_chrbuf[i] & 0x40; //check decimal point. Needs to be mapped to seg_bit16
- bool comma = m_lcd_chrbuf[i] & 0x80; //check comma, maps to seg17
+ bool dp = m_lcd_chrbuf[i] & 0x40; //check decimal point. Needs to be mapped to seg_bit16
+ bool comma = m_lcd_chrbuf[i] & 0x80; //check comma, maps to seg17
m_lcd_text[i] = (m_lcd_chrbuf[i] & 0x3F) + 0x40;
m_lcd_segdata[i] = hpcharset[m_lcd_chrbuf[i] & 0x3F] | (dp << 16) | (comma << 17);
LOGMASKED(DEBUG_LCD2, "[%02X>%04X] ", m_lcd_chrbuf[i] & 0x3F, m_lcd_segdata[i]);
@@ -399,10 +399,10 @@ uint32_t hp3478a_state::lcd_set_display(uint32_t segin)
}
// ISA command bytes
-#define DISP_ISA_WANNUN 0xBC //annunciators
-#define DISP_ISA_WA 0x0A //low nibbles
-#define DISP_ISA_WB 0x1A //hi nib
-#define DISP_ISA_WC 0x2A // "extended bit" ?
+#define DISP_ISA_WANNUN 0xBC //annunciators
+#define DISP_ISA_WA 0x0A //low nibbles
+#define DISP_ISA_WB 0x1A //hi nib
+#define DISP_ISA_WC 0x2A // "extended bit" ?
/** LCD serial interface state machine. I cheat and don't implement all commands.
* Also, it's not clear when exactly the display should be updated. After each regA/regB write
@@ -413,14 +413,14 @@ void hp3478a_state::lcd_interface(uint8_t p2new)
bool pwo_state, sync_state, isa_state, iwa_state;
pwo_state = p2new & DISP_PWO;
- sync_state = p2new & DISP_SYNC;
+ sync_state = p2new & DISP_SYNC;
isa_state = p2new & DISP_ISA;
iwa_state = p2new & DISP_IWA;
if (!((p2new ^ m_p2_oldstate) & DISP_CK1)) {
// no clock edge : boring.
//LOGMASKED(DEBUG_LCD, "LCD : pwo(%d), sync(%d), isa(%d), iwa(%d)\n",
- // pwo_state, sync_state, isa_state, iwa_state);
+ // pwo_state, sync_state, isa_state, iwa_state);
return;
}
@@ -490,7 +490,7 @@ void hp3478a_state::lcd_interface(uint8_t p2new)
m_lcdiwa = lcd_iwatype::ANNUNS;
break;
case DISP_ISA_WA:
- m_lcd_want = 100; //no, doesn't fit in a uint64, but only the first 36 bits are significant.
+ m_lcd_want = 100; //no, doesn't fit in a uint64, but only the first 36 bits are significant.
m_lcdiwa = lcd_iwatype::REG_A;
break;
case DISP_ISA_WB:
@@ -551,7 +551,7 @@ void hp3478a_state::lcd_interface(uint8_t p2new)
//shouldn't get extra bits, but we have nothing better to do so just reset the shiftreg.
m_lcd_bitcount = 0;
m_lcd_bitbuf = 0;
- break; //case SELECTED_IWA
+ break; //case SELECTED_IWA
}
return;
@@ -578,7 +578,7 @@ void hp3478a_state::machine_start()
void hp3478a_state::i8039_map(address_map &map)
{
- map(0x0000, 0x0fff).bankr("bank0"); // CPU address space (4kB), banked according to P26 pin
+ map(0x0000, 0x0fff).bankr("bank0"); // CPU address space (4kB), banked according to P26 pin
}
void hp3478a_state::i8039_io(address_map &map)
@@ -595,7 +595,7 @@ void hp3478a_state::io_bank(address_map &map)
{
map.unmap_value_high();
map(0x000, 0x0ff).ram().region("nvram", 0).share("nvram").w(FUNC(hp3478a_state::nvwrite));
- map(0x100, 0x107).ram().share("gpibregs"); //XXX TODO : connect to i8291.cpp
+ map(0x100, 0x107).ram().share("gpibregs"); //XXX TODO : connect to i8291.cpp
map(0x200, 0x2ff).portr("DIP");
}
@@ -605,17 +605,17 @@ void hp3478a_state::io_bank(address_map &map)
******************************************************************************/
static INPUT_PORTS_START( hp3478a )
/* keypad bit matrix:
- 0x08|0x04|0x02|0x01
- col.0 : (nc)|shift|ACA|DCA
- col.1 : 4W|2W|ACV|DCV
- col.2 : int|dn|up|auto
- col.3 : (nc)|loc|srq|sgl
+ 0x08|0x04|0x02|0x01
+ col.0 : (nc)|shift|ACA|DCA
+ col.1 : 4W|2W|ACV|DCV
+ col.2 : int|dn|up|auto
+ col.3 : (nc)|loc|srq|sgl
*/
PORT_START("COL.0")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("DCA")
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("ACA")
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("SHIFT")
- PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) //nothing on 0x08
+ PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) //nothing on 0x08
PORT_START("COL.1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("DCV")
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("ACV")
@@ -630,7 +630,7 @@ static INPUT_PORTS_START( hp3478a )
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON12 ) PORT_NAME("SGL")
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON13 ) PORT_NAME("SRQ")
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON14 ) PORT_NAME("LOC")
- PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) //nothing on 0x08
+ PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) //nothing on 0x08
PORT_START("CAL_EN")
PORT_CONFNAME(1, 0, "CAL")
@@ -713,9 +713,9 @@ void hp3478a_state::hp3478a(machine_config &config)
******************************************************************************/
ROM_START( hp3478a )
ROM_REGION( 0x2000, "maincpu", 0 )
- ROM_LOAD("rom_dc118.bin", 0, 0x2000, CRC(10097ced) SHA1(bd665cf7e07e63f825b2353c8322ed8a4376b3bd)) //main CPU ROM, can match other datecodes too
+ ROM_LOAD("rom_dc118.bin", 0, 0x2000, CRC(10097ced) SHA1(bd665cf7e07e63f825b2353c8322ed8a4376b3bd)) //main CPU ROM, can match other datecodes too
- ROM_REGION( 0x100, "nvram", 0 ) /* Calibration RAM, battery-backed */
+ ROM_REGION( 0x100, "nvram", 0 ) /* Calibration RAM, battery-backed */
ROM_LOAD( "calram.bin", 0, 0x100, NO_DUMP)
ROM_END
diff --git a/src/mame/drivers/hp95lx.cpp b/src/mame/drivers/hp95lx.cpp
index 66bcc85e93e..2e287a9a956 100644
--- a/src/mame/drivers/hp95lx.cpp
+++ b/src/mame/drivers/hp95lx.cpp
@@ -17,19 +17,19 @@
DAC (1 channel; can be used as tone generator)
512KB or 1MB of RAM
1MB of BIOS ROM (banked)
- P/N 18-5301 ABD \\ HN62318BFC26
+ P/N 18-5301 ABD \\ HN62318BFC26
LCD, 240x128 pixels (40x16 chars in MDA-compatible text mode)
To do:
- - blue on green LCD palette
- - native keyboard
- - 1MB model
- - identify RTC core
+ - blue on green LCD palette
+ - native keyboard
+ - 1MB model
+ - identify RTC core
- everything else
- Technical info:
+ Technical info:
- http://web.archive.org/web/20071012040320/http://www.daniel-hertrich.de/download/95lx_devguide.zip
- - http://cd.textfiles.com/blackphilesii/PHILES/HP95/HP95DEV.ZIP
+ - http://cd.textfiles.com/blackphilesii/PHILES/HP95/HP95DEV.ZIP
Useful links:
- https://hermocom.com/hplx/view-all-hp-palmtop-articles/41-95lx
@@ -43,12 +43,12 @@
- http://web.archive.org/web/20150423014908/http://www.sp.uconn.edu/~mchem1/HPLX.shtml
HPLX-L mailing list archive
- Software:
- - http://www.retroisle.com/others/hp95lx/software.php
- - http://www.mizj.com/
- - http://www.hp200lx.net/
- - http://www.nic.funet.fi/index/misc/hp95lx/Index
- - http://cd.textfiles.com/blackphilesii/PHILES/HP95/
+ Software:
+ - http://www.retroisle.com/others/hp95lx/software.php
+ - http://www.mizj.com/
+ - http://www.hp200lx.net/
+ - http://www.nic.funet.fi/index/misc/hp95lx/Index
+ - http://cd.textfiles.com/blackphilesii/PHILES/HP95/
***************************************************************************/
@@ -614,12 +614,12 @@ WRITE8_MEMBER(hp95lx_state::video_register_w)
m_disp_start_addr = ((data & 0x3f) << 8) | (m_disp_start_addr & 0x00ff);
break;
- case 0x0d:
+ case 0x0d:
m_disp_start_addr = ((data & 0xff) << 0) | (m_disp_start_addr & 0xff00);
break;
case 0x0e:
- m_cursor_addr = ((data & 0x3f) << 8) | (m_cursor_addr & 0x00ff);
+ m_cursor_addr = ((data & 0x3f) << 8) | (m_cursor_addr & 0x00ff);
break;
case 0x0f:
@@ -699,9 +699,9 @@ void hp95lx_state::hp95lx_io(address_map &map)
map(0x0020, 0x002f).rw("pic8259", FUNC(pic8259_device::read), FUNC(pic8259_device::write));
map(0x0040, 0x004f).rw("pit8254", FUNC(pit8254_device::read), FUNC(pit8254_device::write));
map(0x0060, 0x0063).rw(FUNC(hp95lx_state::keyboard_r), FUNC(hp95lx_state::keyboard_w));
-// map(0x0090, 0x009f).w(FUNC(hp95lx_state::debug_w));
+// map(0x0090, 0x009f).w(FUNC(hp95lx_state::debug_w));
map(0x03b0, 0x03bf).rw(FUNC(hp95lx_state::video_r), FUNC(hp95lx_state::video_w));
-// map(0x0070, 0x007f) RTC
+// map(0x0070, 0x007f) RTC
map(0xd300, 0xd30f).rw(FUNC(hp95lx_state::d300_r), FUNC(hp95lx_state::d300_w));
map(0xe300, 0xe30f).rw(FUNC(hp95lx_state::e300_r), FUNC(hp95lx_state::e300_w));
map(0xf300, 0xf31f).rw(FUNC(hp95lx_state::f300_r), FUNC(hp95lx_state::f300_w));
@@ -748,7 +748,7 @@ MACHINE_CONFIG_START(hp95lx_state::hp95lx)
NVRAM(config, "nvram2", nvram_device::DEFAULT_ALL_0); // RAM
NVRAM(config, "nvram3", nvram_device::DEFAULT_ALL_0); // card slot
- // XXX When the AC adapter is plugged in, the LCD refresh rate is 73.14 Hz.
+ // XXX When the AC adapter is plugged in, the LCD refresh rate is 73.14 Hz.
// XXX When the AC adapter is not plugged in (ie, running off of batteries) the refresh rate is 56.8 Hz.
MCFG_SCREEN_ADD_MONOCHROME("screen", LCD, rgb_t::white())
MCFG_SCREEN_UPDATE_DRIVER(hp95lx_state, screen_update)
diff --git a/src/mame/drivers/konamim2.cpp b/src/mame/drivers/konamim2.cpp
index bb94e96d49c..efb4cdec75a 100644
--- a/src/mame/drivers/konamim2.cpp
+++ b/src/mame/drivers/konamim2.cpp
@@ -7,37 +7,37 @@
driver by Phil Bennett
- NOTE:
-
- * All games are marked MACHINE_NOT_WORKING due to the rare case
- where the PowerPC DRC blows up, causing MAME to crash. In reality,
- there is a good chance of being able to play through a round or
- three with no issues on all of the parent sets.
-
- TODO:
-
- * Fix DRC crashes
- o Crashes on DRC translation of 0x40028604
- * Fix texture compression
- * Sort out CD images
- * Fix Polystars blending issues
- * Fix PowerPC 602 Protection Only mode handling.
- * Implement CDDA muting
-
- DONE
- * Fix Polystars blending
- * Fix missing music in Polystars
+ NOTE:
+
+ * All games are marked MACHINE_NOT_WORKING due to the rare case
+ where the PowerPC DRC blows up, causing MAME to crash. In reality,
+ there is a good chance of being able to play through a round or
+ three with no issues on all of the parent sets.
+
+ TODO:
+
+ * Fix DRC crashes
+ o Crashes on DRC translation of 0x40028604
+ * Fix texture compression
+ * Sort out CD images
+ * Fix Polystars blending issues
+ * Fix PowerPC 602 Protection Only mode handling.
+ * Implement CDDA muting
+
+ DONE
+ * Fix Polystars blending
+ * Fix missing music in Polystars
* Fix music playing too early
- * Fix missing music and sound in Hell Night/Evil Night
- * Fix incorrect speed in Heat of 11 and Total Vice (partially)
+ * Fix missing music and sound in Hell Night/Evil Night
+ * Fix incorrect speed in Heat of 11 and Total Vice (partially)
- // Polystars/Total Vice
- if (pc == 0x40035958)
- gpr[11] = 1;
+ // Polystars/Total Vice
+ if (pc == 0x40035958)
+ gpr[11] = 1;
- // Everything else
- if (pc == 0x400385c8)
- gpr[11] = 0;
+ // Everything else
+ if (pc == 0x400385c8)
+ gpr[11] = 0;
@@ -243,9 +243,9 @@ Notes:
#include "screen.h"
#include "speaker.h"
-#define M2_CLOCK XTAL(66'666'700)
+#define M2_CLOCK XTAL(66'666'700)
-#define ENABLE_SDBG 0
+#define ENABLE_SDBG 0
/*************************************
@@ -323,7 +323,7 @@ public:
{
// 8000 = /Reset
// 4000 = C000 ... DOIO DMA ... 4000
-// m_ata->write_dmack(data & 0x4000 ? ASSERT_LINE : CLEAR_LINE);
+// m_ata->write_dmack(data & 0x4000 ? ASSERT_LINE : CLEAR_LINE);
if (!(data & 0x8000))
{
@@ -365,9 +365,9 @@ private:
cdrom_file *m_available_cdroms;
// Konami SIO
- uint16_t m_sio_data;
+ uint16_t m_sio_data;
- uint32_t m_ata_int; // TEST
+ uint32_t m_ata_int; // TEST
emu_timer *m_atapi_timer;
TIMER_CALLBACK_MEMBER( atapi_delay )
@@ -435,7 +435,7 @@ WRITE16_MEMBER( konamim2_state::rdac_out )
WRITE_LINE_MEMBER( konamim2_state::ata_int )
{
-// m_atapi_timer->adjust( attotime::from_msec(10), state );
+// m_atapi_timer->adjust( attotime::from_msec(10), state );
m_ata_int = state;
}
@@ -448,14 +448,14 @@ WRITE_LINE_MEMBER( konamim2_state::ata_int )
READ16_MEMBER( konamim2_state::konami_io0_r )
{
-// printf("IO R: %08X\n", offset);
+// printf("IO R: %08X\n", offset);
switch (offset)
{
/*
- 0 = 160
+ 0 = 160
1 = 32
- 2 = -96
+ 2 = -96
10 = -1888
FF = -32480
@@ -503,7 +503,7 @@ READ16_MEMBER( konamim2_state::konami_io0_r )
case 5: return 0; // P2 Y
case 6: return 0; // P3 Y?
case 7: return 0; //??
- case 8: return ioport("P5")->read();
+ case 8: return ioport("P5")->read();
}
//return rand();
@@ -513,7 +513,7 @@ READ16_MEMBER( konamim2_state::konami_io0_r )
WRITE16_MEMBER( konamim2_state::konami_io0_w )
{
// 9: 0000, 0xFFF
-// printf("IO W: %08x %08x\n", offset, data);
+// printf("IO W: %08x %08x\n", offset, data);
}
/*
@@ -545,7 +545,7 @@ READ16_MEMBER( konamim2_state::konami_io1_r )
{
uint16_t data = 0;
-// printf("%s: PORT R: [%x] MASK:%.8x\n", machine().describe_context(), offset, mem_mask);
+// printf("%s: PORT R: [%x] MASK:%.8x\n", machine().describe_context(), offset, mem_mask);
switch (offset)
{
@@ -609,13 +609,13 @@ WRITE16_MEMBER( konamim2_state::konami_io1_w )
// 0x8000 = ?
logerror("%s: PORT W: [%x] %x, MASK:%.8x\n", machine().describe_context(), offset, data, mem_mask);
-// printf("CDDA is: %s\n", data & 0x2000 ? "ENABLED" : "MUTE");
+// printf("CDDA is: %s\n", data & 0x2000 ? "ENABLED" : "MUTE");
machine().bookkeeping().coin_counter_w(0, (data >> 11) & 1);
machine().bookkeeping().coin_counter_w(1, (data >> 12) & 1);
-// m_cdda->set_output_gain(0, data & 0x2000 ? 1.0 : 0.0);
-// m_cdda->set_output_gain(1, data & 0x2000 ? 1.0 : 0.0);
+// m_cdda->set_output_gain(0, data & 0x2000 ? 1.0 : 0.0);
+// m_cdda->set_output_gain(1, data & 0x2000 ? 1.0 : 0.0);
}
@@ -762,7 +762,7 @@ void konamim2_state::m2_map(address_map &map)
map(0x37c00010, 0x37c0001f).rw(FUNC(konamim2_state::konami_sio_r), FUNC(konamim2_state::konami_sio_w));
map(0x37e00000, 0x37e0000f).rw(FUNC(konamim2_state::konami_io1_r), FUNC(konamim2_state::konami_io1_w));
map(0x3f000000, 0x3fffffff).rw(FUNC(konamim2_state::konami_ide_r), FUNC(konamim2_state::konami_ide_w)); // Endian flipped???
-// map(0x3f000000, 0x3fffffff).rw("ata", FUNC(ata_interface_device::read_cs0), FUNC(ata_interface_device::write_cs0));
+// map(0x3f000000, 0x3fffffff).rw("ata", FUNC(ata_interface_device::read_cs0), FUNC(ata_interface_device::write_cs0));
#if 0
map(0x36c00000, 0x36cfffff).rw(m48t58_r, m48t58_w)
@@ -770,10 +770,10 @@ void konamim2_state::m2_map(address_map &map)
map(0x37400000, 0x37400003).w(eeprom_w)
map(0x37600000, 0x37600000).w(atapi_dma_w)
map(0x37a00000, 0x37a0003f).rw(kacio_r, kacio_w)
- map(0x37c00010, 0x37c0001f).rw(sio_r, sio_w) // Konami 11k
- map(0x37e00000, 0x37e0000f).rw(port_r, port_w) // Konami? - 37e00006 = Read
- map(0x3e000000, 0x3effffff).rw(ymz0_r, ymz0_w) // Konami - Evil Night / Total Vice
- map(0x3e900000, 0x3e9fffff).rw(ymz1_r, ymz1_w) // Konami
+ map(0x37c00010, 0x37c0001f).rw(sio_r, sio_w) // Konami 11k
+ map(0x37e00000, 0x37e0000f).rw(port_r, port_w) // Konami? - 37e00006 = Read
+ map(0x3e000000, 0x3effffff).rw(ymz0_r, ymz0_w) // Konami - Evil Night / Total Vice
+ map(0x3e900000, 0x3e9fffff).rw(ymz1_r, ymz1_w) // Konami
#endif
}
@@ -1205,7 +1205,7 @@ void konamim2_state::konamim2(machine_config &config)
void konamim2_state::set_ntsc(machine_config &config)
{
-// m_screen->set_raw(11750000, 766, 126, 126+640, 260, 20, 20+240); // TODO
+// m_screen->set_raw(11750000, 766, 126, 126+640, 260, 20, 20+240); // TODO
m_screen->set_refresh_hz(59.360001);
m_screen->set_size(768, 262);
m_screen->set_visarea(126, 126+640-1, 20, 20+240-1);
@@ -1255,7 +1255,7 @@ void konamim2_state::totlvice(machine_config &config)
{
konamim2(config);
add_ymz280b(config);
-// set_arcres(config);
+// set_arcres(config);
set_ntsc2(config);
}
@@ -1353,8 +1353,8 @@ ROM_START( evilngt )
ROM_REGION64_BE( 0x200000, "boot", 0 )
ROM_LOAD16_WORD( "636a01.8q", 0x000000, 0x200000, CRC(7b1dc738) SHA1(32ae8e7ddd38fcc70b4410275a2cc5e9a0d7d33b) )
- ROM_REGION16_BE( 0x80, "eeprom", 0 ) /* EEPROM default contents */
- ROM_LOAD( "93c46.7k", 0x000000, 0x000080, CRC(60ae825e) SHA1(fd61db9667c53dd12700a0fe202fcd1e3d35d206) )
+ ROM_REGION16_BE( 0x80, "eeprom", 0 ) /* EEPROM default contents */
+ ROM_LOAD( "93c46.7k", 0x000000, 0x000080, CRC(60ae825e) SHA1(fd61db9667c53dd12700a0fe202fcd1e3d35d206) )
ROM_REGION( 0x2000, "m48t58", 0 ) /* timekeeper SRAM */
ROM_LOAD( "m48t58y.9n", 0x000000, 0x002000, CRC(e887ca1f) SHA1(54205f01b1ceba1d5f4d979fc30be1add8116e90) )
@@ -1489,7 +1489,7 @@ void konamim2_state::install_m48t58()
void konamim2_state::install_ymz280b()
{
read8_delegate read_delegate(FUNC(ymz280b_device::read), &(*m_ymz280b));
- write8_delegate write_delegate(FUNC(ymz280b_device::write), &(*m_ymz280b));
+ write8_delegate write_delegate(FUNC(ymz280b_device::write), &(*m_ymz280b));
m_ppc1->space(AS_PROGRAM).install_readwrite_handler(0x3e800000, 0x3e80000f, read_delegate, write_delegate, 0xff00ff0000000000ULL);
m_ppc2->space(AS_PROGRAM).install_readwrite_handler(0x3e800000, 0x3e80000f, read_delegate, write_delegate, 0xff00ff0000000000ULL);
@@ -1674,19 +1674,19 @@ void konamim2_state::dump_task_command(int ref, const std::vector<std::string> &
task.t_DefaultMsgPort = cpu.read_dword(space, address + offsetof(Task, t_DefaultMsgPort), true);
task.pt_UserData = cpu.read_dword(space, address + offsetof(Task, pt_UserData), true);
-// m2ptr pt_ThreadTask; /* I am a thread of what task? */
-// uint32_t t_WaitBits; /* signals being waited for */
-// uint32_t t_SigBits; /* signals received */
-// uint32_t t_AllocatedSigs; /* signals allocated */
-// m2ptr pt_StackBase; /* base of stack */
-// int32_t t_StackSize; /* size of stack */
-// uint32_t t_MaxUSecs; /* quantum length in usecs */
-// TimerTicks t_ElapsedTime; /* time spent running this task */
-// uint32_t t_NumTaskLaunch; /* # times launched this task */
-// uint32_t t_Flags; /* task flags */
-// Item t_Module; /* the module we live within */
-// Item t_DefaultMsgPort; /* default task msgport */
-// m2ptr pt_UserData; /* user-private data */
+// m2ptr pt_ThreadTask; /* I am a thread of what task? */
+// uint32_t t_WaitBits; /* signals being waited for */
+// uint32_t t_SigBits; /* signals received */
+// uint32_t t_AllocatedSigs; /* signals allocated */
+// m2ptr pt_StackBase; /* base of stack */
+// int32_t t_StackSize; /* size of stack */
+// uint32_t t_MaxUSecs; /* quantum length in usecs */
+// TimerTicks t_ElapsedTime; /* time spent running this task */
+// uint32_t t_NumTaskLaunch; /* # times launched this task */
+// uint32_t t_Flags; /* task flags */
+// Item t_Module; /* the module we live within */
+// Item t_DefaultMsgPort; /* default task msgport */
+// m2ptr pt_UserData; /* user-private data */
con.printf("**** Task Info @ %08X ****\n", address);
con.printf("Next: %08X\n", task.t.pn_Next);
@@ -1712,7 +1712,7 @@ void konamim2_state::dump_task_command(int ref, const std::vector<std::string> &
con.printf("StackSize: %08X\n", task.t_StackSize);
con.printf("MaxUSecs: %08X\n", task.t_MaxUSecs);
con.printf("ElapsedTime: %016llu\n", (uint64_t)task.t_ElapsedTime.tt_Lo + ((uint64_t)task.t_ElapsedTime.tt_Hi << 32ull));
- con.printf("NumTaskLaunch: %u\n", task.t_NumTaskLaunch);
+ con.printf("NumTaskLaunch: %u\n", task.t_NumTaskLaunch);
con.printf("Flags: %08X\n", task.t_Flags);
con.printf("Module: %08X\n", task.t_Module);
con.printf("DefaultMsgPort: %08X\n", task.t_DefaultMsgPort);
diff --git a/src/mame/drivers/m24.cpp b/src/mame/drivers/m24.cpp
index 04e87d70c54..7c32d2c18c8 100644
--- a/src/mame/drivers/m24.cpp
+++ b/src/mame/drivers/m24.cpp
@@ -3,14 +3,14 @@
/****************************************************************************
Olivetti M24 emulation
-
- http://olivettim24.hadesnet.org/index.html
- https://sites.google.com/site/att6300shrine/Home
- http://www.ti99.com/exelvision/website/index.php?page=logabax-persona-1600
-
- The AT&T PC6300, the Xerox 6060 and the Logabax Persona 1600 were badge
- engineered Olivetti M24s.
-
+
+ http://olivettim24.hadesnet.org/index.html
+ https://sites.google.com/site/att6300shrine/Home
+ http://www.ti99.com/exelvision/website/index.php?page=logabax-persona-1600
+
+ The AT&T PC6300, the Xerox 6060 and the Logabax Persona 1600 were badge
+ engineered Olivetti M24s.
+
****************************************************************************/
@@ -317,12 +317,12 @@ ROM_START( m24 )
ROM_SYSTEM_BIOS(1,"v1.21","v1.21")
ROMX_LOAD("m24_bios121h.rom",0x4001, 0x2000, CRC(93292715) SHA1(863eccfb3beca6e64c5b0cc070c64394bad7da82), ROM_SKIP(1) | ROM_BIOS(1))
ROMX_LOAD("m24_bios121l.rom", 0x4000, 0x2000, CRC(1acbc9d7) SHA1(d3696e38853cea31e70ffa4e13e127ec7551bf57), ROM_SKIP(1) | ROM_BIOS(1))
-
+
ROM_SYSTEM_BIOS(2,"v1.36","v1.36")
ROMX_LOAD("m24_bios136h.rom",0x4001, 0x2000, CRC(25cbf8ba) SHA1(1ab90985852544d2c12b47bb7f20f9faccabdf88), ROM_SKIP(1) | ROM_BIOS(2))
ROMX_LOAD("m24_bios136l.rom", 0x4000, 0x2000, CRC(e2f738c0) SHA1(da9771325a5021cf9908997e0e0d14e47258125f), ROM_SKIP(1) | ROM_BIOS(2))
-
- ROM_SYSTEM_BIOS(3,"v1.43","v1.43")
+
+ ROM_SYSTEM_BIOS(3,"v1.43","v1.43")
ROMX_LOAD("olivetti_m24_version_1.43_high.bin",0x4001, 0x2000, CRC(04e697ba) SHA1(1066dcc849e6289b5ac6372c84a590e456d497a6), ROM_SKIP(1) | ROM_BIOS(3))
ROMX_LOAD("olivetti_m24_version_1.43_low.bin", 0x4000, 0x2000, CRC(ff7e0f10) SHA1(13423011a9bae3f3193e8c199f98a496cab48c0f), ROM_SKIP(1) | ROM_BIOS(3))
diff --git a/src/mame/drivers/mdisk.cpp b/src/mame/drivers/mdisk.cpp
index 4551c485ac8..53720cc46e9 100644
--- a/src/mame/drivers/mdisk.cpp
+++ b/src/mame/drivers/mdisk.cpp
@@ -5,13 +5,13 @@
mupid M-Disk Comp.-A
Grundig FL-100
- Floppy disk station, usually connected to a mupid C2D2/C2A2 or the
- Grundig PTC-100.
+ Floppy disk station, usually connected to a mupid C2D2/C2A2 or the
+ Grundig PTC-100.
- Everything here is guessed based on the software and a PCB image. You
- can see garbled output when you connect the builtin terminal to the
- first serial port ('ser'). It does boot from floppy too, so presumely
- only needs an emulated main system to work.
+ Everything here is guessed based on the software and a PCB image. You
+ can see garbled output when you connect the builtin terminal to the
+ first serial port ('ser'). It does boot from floppy too, so presumely
+ only needs an emulated main system to work.
***************************************************************************/
diff --git a/src/mame/drivers/megasys1.cpp b/src/mame/drivers/megasys1.cpp
index 234fbfce95c..9236fd0e222 100644
--- a/src/mame/drivers/megasys1.cpp
+++ b/src/mame/drivers/megasys1.cpp
@@ -3070,7 +3070,7 @@ ROM_START( iganinjub )
ROM_LOAD16_BYTE( "19.a12", 0x000000, 0x010000, CRC(6b4c16ac) SHA1(edb5fe3b3e4e94e59348c0a7034df9df6ef157d3) )
ROM_LOAD16_BYTE( "23.13", 0x000001, 0x010000, CRC(03bfda29) SHA1(ced6ddcbb86d3109bcfb8e1982a5f666ca7dc10e) )
ROM_LOAD16_BYTE( "20.a13", 0x020000, 0x010000, CRC(fa0705fb) SHA1(110ebca62a57f9d8e355a339a99819faf1fe57f1) )
- ROM_LOAD16_BYTE( "24.12", 0x020001, 0x010000, CRC(2de40303) SHA1(5c841295c0d804163a7da3c122dd40af7780d1f2) )
+ ROM_LOAD16_BYTE( "24.12", 0x020001, 0x010000, CRC(2de40303) SHA1(5c841295c0d804163a7da3c122dd40af7780d1f2) )
ROM_LOAD16_BYTE( "c", 0x040000, 0x010000, CRC(de5937ad) SHA1(d3039e5391feb925ea10f33a1363bf3ffc1ebb3d) )
ROM_LOAD16_BYTE( "b", 0x040001, 0x010000, CRC(afaf0480) SHA1(b8d0ec859a94941650bdd2b01e98d054d49fef67) )
diff --git a/src/mame/drivers/midtunit.cpp b/src/mame/drivers/midtunit.cpp
index 2b2db8280b7..f170ad24dca 100644
--- a/src/mame/drivers/midtunit.cpp
+++ b/src/mame/drivers/midtunit.cpp
@@ -598,12 +598,12 @@ void midtunit_state::tunit_core(machine_config &config)
/* basic machine hardware */
TMS34010(config, m_maincpu, CPU_CLOCK);
m_maincpu->set_addrmap(AS_PROGRAM, &midtunit_state::main_map);
- m_maincpu->set_halt_on_reset(false); /* halt on reset */
+ m_maincpu->set_halt_on_reset(false); /* halt on reset */
m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
- m_maincpu->set_pixels_per_clock(2); /* pixels per clock */
- m_maincpu->set_scanline_ind16_callback("video", FUNC(midtunit_video_device::scanline_update)); /* scanline updater (indexed16) */
- m_maincpu->set_shiftreg_in_callback("video", FUNC(midtunit_video_device::to_shiftreg)); /* write to shiftreg function */
- m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
+ m_maincpu->set_pixels_per_clock(2); /* pixels per clock */
+ m_maincpu->set_scanline_ind16_callback("video", FUNC(midtunit_video_device::scanline_update)); /* scanline updater (indexed16) */
+ m_maincpu->set_shiftreg_in_callback("video", FUNC(midtunit_video_device::to_shiftreg)); /* write to shiftreg function */
+ m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
m_maincpu->set_screen("screen");
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
diff --git a/src/mame/drivers/midwunit.cpp b/src/mame/drivers/midwunit.cpp
index 60a34efc8fd..c3a49753079 100644
--- a/src/mame/drivers/midwunit.cpp
+++ b/src/mame/drivers/midwunit.cpp
@@ -630,12 +630,12 @@ void midwunit_state::wunit(machine_config &config)
TMS34010(config, m_maincpu, 50000000);
m_maincpu->set_addrmap(AS_PROGRAM, &midwunit_state::main_map);
- m_maincpu->set_halt_on_reset(false); /* halt on reset */
+ m_maincpu->set_halt_on_reset(false); /* halt on reset */
m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
- m_maincpu->set_pixels_per_clock(1); /* pixels per clock */
- m_maincpu->set_scanline_ind16_callback("video", FUNC(midtunit_video_device::scanline_update)); /* scanline updater (indexed16) */
- m_maincpu->set_shiftreg_in_callback("video", FUNC(midtunit_video_device::to_shiftreg)); /* write to shiftreg function */
- m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
+ m_maincpu->set_pixels_per_clock(1); /* pixels per clock */
+ m_maincpu->set_scanline_ind16_callback("video", FUNC(midtunit_video_device::scanline_update)); /* scanline updater (indexed16) */
+ m_maincpu->set_shiftreg_in_callback("video", FUNC(midtunit_video_device::to_shiftreg)); /* write to shiftreg function */
+ m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
m_maincpu->set_screen("screen");
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
diff --git a/src/mame/drivers/midxunit.cpp b/src/mame/drivers/midxunit.cpp
index c6d7ab3fa24..25466619eaf 100644
--- a/src/mame/drivers/midxunit.cpp
+++ b/src/mame/drivers/midxunit.cpp
@@ -248,12 +248,12 @@ void midxunit_state::midxunit(machine_config &config)
/* basic machine hardware */
TMS34020(config, m_maincpu, 40000000);
m_maincpu->set_addrmap(AS_PROGRAM, &midxunit_state::main_map);
- m_maincpu->set_halt_on_reset(false); /* halt on reset */
- m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
- m_maincpu->set_pixels_per_clock(1); /* pixels per clock */
- m_maincpu->set_scanline_ind16_callback("video", FUNC(midxunit_video_device::scanline_update)); /* scanline updater (indexed16) */
- m_maincpu->set_shiftreg_in_callback("video", FUNC(midxunit_video_device::to_shiftreg)); /* write to shiftreg function */
- m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
+ m_maincpu->set_halt_on_reset(false); /* halt on reset */
+ m_maincpu->set_pixel_clock(PIXEL_CLOCK); /* pixel clock */
+ m_maincpu->set_pixels_per_clock(1); /* pixels per clock */
+ m_maincpu->set_scanline_ind16_callback("video", FUNC(midxunit_video_device::scanline_update)); /* scanline updater (indexed16) */
+ m_maincpu->set_shiftreg_in_callback("video", FUNC(midxunit_video_device::to_shiftreg)); /* write to shiftreg function */
+ m_maincpu->set_shiftreg_out_callback("video", FUNC(midtunit_video_device::from_shiftreg)); /* read from shiftreg function */
m_maincpu->set_screen("screen");
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
diff --git a/src/mame/drivers/minivideo.cpp b/src/mame/drivers/minivideo.cpp
index 97e5444fb1c..1447674cd7c 100644
--- a/src/mame/drivers/minivideo.cpp
+++ b/src/mame/drivers/minivideo.cpp
@@ -116,7 +116,7 @@ void minivideo_state::minivideo(machine_config &config)
/*
PCB is marked: "MINIVIDEO 1.3" on component side
PCB is marked: "MINIVIDEO 1.3" and "LS" on solder side ("LS" is the Italian for "Lato Saldature" which translates to "Solders Side")
-PCB is labelled: "LF1.3" on component side
+PCB is labelled: "LF1.3" on component side
*/
ROM_START( fiches )
ROM_REGION(0x8000, "maincpu", 0)
@@ -130,7 +130,7 @@ ROM_END
/*
PCB is marked: "MINIVIDEO 1.2" on component side
-PCB is marked: "MINIVIDEO 1.2" and "LS" on solder side ("LS" is the Italian for "Lato Saldature" which translates to "Solders Side")
+PCB is marked: "MINIVIDEO 1.2" and "LS" on solder side ("LS" is the Italian for "Lato Saldature" which translates to "Solders Side")
*/
ROM_START( fiches12 )
ROM_REGION(0x8000, "maincpu", 0)
diff --git a/src/mame/drivers/monon_color.cpp b/src/mame/drivers/monon_color.cpp
index 8a1eb317936..f805d31d302 100644
--- a/src/mame/drivers/monon_color.cpp
+++ b/src/mame/drivers/monon_color.cpp
@@ -64,29 +64,29 @@ void monon_color_state::machine_start()
memcpy(maincpu, flash+0x200, 0x1e00); // 0x4000-0x5dff fixed code?
// there are a whole bunch of blocks that map at 0x5e00 (boot code jumps straight to 0x5e00)
-
+
memcpy(maincpu+0x1e00, flash+0x2000, 0x1000); // clears RAM, sets up stack etc. but then jumps to 0x9xxx where we have nothing (probably the correct initial block tho)
-// memcpy(maincpu+0x1e00, flash+0x4200, 0x1000); // just set register + a jump (to function that writes to UART)
-// memcpy(maincpu+0x1e00, flash+0x4c00, 0x1000);
-// memcpy(maincpu+0x1e00, flash+0x5600, 0x1000);
-// memcpy(maincpu+0x1e00, flash+0x6000, 0x1000); // ends up reting with nothing on the stack
-// memcpy(maincpu+0x1e00, flash+0x6a00, 0x1000);
+// memcpy(maincpu+0x1e00, flash+0x4200, 0x1000); // just set register + a jump (to function that writes to UART)
+// memcpy(maincpu+0x1e00, flash+0x4c00, 0x1000);
+// memcpy(maincpu+0x1e00, flash+0x5600, 0x1000);
+// memcpy(maincpu+0x1e00, flash+0x6000, 0x1000); // ends up reting with nothing on the stack
+// memcpy(maincpu+0x1e00, flash+0x6a00, 0x1000);
// memcpy(maincpu+0x1e00, flash+0x7e00, 0x1000);
// memcpy(maincpu+0x1e00, flash+0x8800, 0x1000);
// memcpy(maincpu+0x1e00, flash+0x9200, 0x1000);
-
+
/* block starting at e000 in flash is not code? (or encrypted?)
no code to map at 0x9000 in address space (possible BIOS?)
no code in flash ROM past the first 64kb(?) which is basically the same on all games, must be some kind of script interpreter? J2ME maybe?
- there are 4 different 'versions' of the code in the dumped ROMs, where the code is the same the roms match up until 0x50000 after which the game specific data starts
+ there are 4 different 'versions' of the code in the dumped ROMs, where the code is the same the roms match up until 0x50000 after which the game specific data starts
- by game number:
+ by game number:
- 101,102,103,104,105 (1st revision)
- 106,107 (2nd revision)
- 201 (3rd revision)
- 202,203,204,205,301,303,304 (4th revision)
+ 101,102,103,104,105 (1st revision)
+ 106,107 (2nd revision)
+ 201 (3rd revision)
+ 202,203,204,205,301,303,304 (4th revision)
*/
}
diff --git a/src/mame/drivers/mupid2.cpp b/src/mame/drivers/mupid2.cpp
index 979641a045a..d0222f9975e 100644
--- a/src/mame/drivers/mupid2.cpp
+++ b/src/mame/drivers/mupid2.cpp
@@ -3,13 +3,13 @@
/***************************************************************************
mupid/Infonova C2A2
- Grundig PTC-100
+ Grundig PTC-100
- - Z80
- - 128 + 8 KB RAM
- - Z80 SIO/0
- - 8035
- - M58990P-1 ADC
+ - Z80
+ - 128 + 8 KB RAM
+ - Z80 SIO/0
+ - 8035
+ - M58990P-1 ADC
***************************************************************************/
@@ -112,24 +112,24 @@ INPUT_PORTS_END
READ8_MEMBER(mupid2_state::kbd_bus_r)
{
-// logerror("kbd_bus_r\n");
+// logerror("kbd_bus_r\n");
return 0xff;
}
READ8_MEMBER(mupid2_state::kbd_p1_r)
{
-// logerror("kbd_p1_r\n");
+// logerror("kbd_p1_r\n");
return 0xff;
}
WRITE8_MEMBER(mupid2_state::kbd_p1_w)
{
-// logerror("kbd_p1_w: %02x\n", data);
+// logerror("kbd_p1_w: %02x\n", data);
}
WRITE8_MEMBER(mupid2_state::kbd_p2_w)
{
-// logerror("kbd_p2_w: %02x\n", data);
+// logerror("kbd_p2_w: %02x\n", data);
}
diff --git a/src/mame/drivers/nes.cpp b/src/mame/drivers/nes.cpp
index e7113c8cd1b..34acda1dcef 100644
--- a/src/mame/drivers/nes.cpp
+++ b/src/mame/drivers/nes.cpp
@@ -61,7 +61,7 @@ void nes_state::nes(machine_config &config)
// non-rendering scanlines, we compensate. This ends up being 2500 cycles for the non-rendering portion, 2273
// cycles for the actual vblank period.
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(NTSC_APU_CLOCK.dvalue()/1000000)) *
- (ppu2c0x_device::VBLANK_LAST_SCANLINE_NTSC-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
+ (ppu2c0x_device::VBLANK_LAST_SCANLINE_NTSC-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
m_screen->set_size(32*8, 262);
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
m_screen->set_screen_update(FUNC(nes_state::screen_update_nes));
@@ -103,7 +103,7 @@ void nes_state::nespal(machine_config &config)
/* video hardware */
m_screen->set_refresh_hz(50.0070);
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
- (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
+ (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
m_screen->set_size(32*8, 312);
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
}
@@ -136,7 +136,7 @@ void nes_state::nespalc(machine_config &config)
/* video hardware */
m_screen->set_refresh_hz(50.0070);
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(PALC_APU_CLOCK.dvalue()/1000000)) *
- (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE_PALC+1+2)));
+ (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE_PALC+1+2)));
}
void nes_state::famipalc(machine_config &config)
diff --git a/src/mame/drivers/nes_vt.cpp b/src/mame/drivers/nes_vt.cpp
index e15f88bedbe..ba74fe07ae0 100644
--- a/src/mame/drivers/nes_vt.cpp
+++ b/src/mame/drivers/nes_vt.cpp
@@ -1361,7 +1361,7 @@ void nes_vt_state::nes_vt_base(machine_config &config)
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_refresh_hz(60.0988);
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((113.66/(NTSC_APU_CLOCK.dvalue()/1000000)) *
- (ppu2c0x_device::VBLANK_LAST_SCANLINE_NTSC-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
+ (ppu2c0x_device::VBLANK_LAST_SCANLINE_NTSC-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
m_screen->set_size(32*8, 262);
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
m_screen->set_screen_update("ppu", FUNC(ppu2c0x_device::screen_update));
@@ -1454,7 +1454,7 @@ void nes_vt_state::nes_vt_dg(machine_config &config)
m_screen->set_refresh_hz(50.0070);
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
- (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
+ (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
m_screen->set_size(32*8, 312);
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
}
@@ -1477,7 +1477,7 @@ void nes_vt_state::nes_vt_hh(machine_config &config)
/* video hardware */
m_screen->set_refresh_hz(50.0070);
m_screen->set_vblank_time(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) *
- (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
+ (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)));
m_screen->set_size(32*8, 312);
m_screen->set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
}
diff --git a/src/mame/drivers/overdriv.cpp b/src/mame/drivers/overdriv.cpp
index efb35042f87..7e6f1e58ec7 100644
--- a/src/mame/drivers/overdriv.cpp
+++ b/src/mame/drivers/overdriv.cpp
@@ -340,8 +340,8 @@ void overdriv_state::overdriv(machine_config &config)
MC6809E(config, m_audiocpu, XTAL(3'579'545)); /* 1.789 MHz?? This might be the right speed, but ROM testing */
m_audiocpu->set_addrmap(AS_PROGRAM, &overdriv_state::overdriv_sound_map); /* takes a little too much (the counter wraps from 0000 to 9999). */
- /* This might just mean that the video refresh rate is less than */
- /* 60 fps, that's how I fixed it for now. */
+ /* This might just mean that the video refresh rate is less than */
+ /* 60 fps, that's how I fixed it for now. */
config.m_minimum_quantum = attotime::from_hz(12000);
diff --git a/src/mame/drivers/pasopia7.cpp b/src/mame/drivers/pasopia7.cpp
index 3e750193123..08a7a753c8c 100644
--- a/src/mame/drivers/pasopia7.cpp
+++ b/src/mame/drivers/pasopia7.cpp
@@ -16,7 +16,7 @@
Reading fdc has been commented out, until the code can be modified to
work with new upd765 (was causing a hang at boot).
- Schematics: https://archive.org/details/Io19839/page/n331
+ Schematics: https://archive.org/details/Io19839/page/n331
***************************************************************************************************/
diff --git a/src/mame/drivers/pgm2.cpp b/src/mame/drivers/pgm2.cpp
index a3e1ca62cdb..8a23ba68dd5 100644
--- a/src/mame/drivers/pgm2.cpp
+++ b/src/mame/drivers/pgm2.cpp
@@ -1356,7 +1356,7 @@ READ32_MEMBER(pgm2_state::ddpdojt_speedup_r)
/*
else
{
- logerror("pc is %08x\n", pc);
+ logerror("pc is %08x\n", pc);
}
*/
@@ -1375,7 +1375,7 @@ READ32_MEMBER(pgm2_state::ddpdojt_speedup2_r)
/*
else
{
- logerror("pc is %08x\n", pc);
+ logerror("pc is %08x\n", pc);
}
*/
diff --git a/src/mame/drivers/pocketc.cpp b/src/mame/drivers/pocketc.cpp
index 634a3ff7d4b..4ba6701a99e 100644
--- a/src/mame/drivers/pocketc.cpp
+++ b/src/mame/drivers/pocketc.cpp
@@ -1,9 +1,9 @@
// license:GPL-2.0+
// copyright-holders:Peter Trauner
/******************************************************************************
- Sharp pocket computers
- PC1401/PC1403
- PeT mess@utanet.at May 2000
+ Sharp pocket computers
+ PC1401/PC1403
+ PeT mess@utanet.at May 2000
******************************************************************************/
#include "emu.h"
diff --git a/src/mame/drivers/psx.cpp b/src/mame/drivers/psx.cpp
index e66c79b5327..e7f09bb3d00 100644
--- a/src/mame/drivers/psx.cpp
+++ b/src/mame/drivers/psx.cpp
@@ -542,8 +542,8 @@ void psx1_state::psx_base(machine_config &config)
SPEAKER(config, "lspeaker").front_left();
SPEAKER(config, "rspeaker").front_right();
spu_device &spu(SPU(config, "spu", XTAL(67'737'600)/2, m_maincpu.target()));
- spu.add_route(0, "lspeaker", 1.00);
- spu.add_route(1, "rspeaker", 1.00);
+ spu.add_route(0, "lspeaker", 1.00);
+ spu.add_route(1, "rspeaker", 1.00);
quickload_image_device &quickload(QUICKLOAD(config, "quickload", 0));
quickload.set_handler(snapquick_load_delegate(&QUICKLOAD_LOAD_NAME(psx1_state, psx_exe_load), this), "cpe,exe,psf,psx", 0);
diff --git a/src/mame/drivers/rainbow.cpp b/src/mame/drivers/rainbow.cpp
index 3f2951c86c5..90b293771fc 100644
--- a/src/mame/drivers/rainbow.cpp
+++ b/src/mame/drivers/rainbow.cpp
@@ -781,9 +781,9 @@ private:
// THIS MACRO * RESETS * the PATTERN TO DEFAULT.
// NOTE 2: m_patmult MUST BE LOADED BEFORE !!
#define OPTION_RESET_PATTERNS \
- m_vpat = 0xff; \
- if (m_patmult == 0) m_patmult = 0x01; \
- if (m_patcnt == 0) m_patcnt = m_patmult; \
+ m_vpat = 0xff; \
+ if (m_patmult == 0) m_patmult = 0x01; \
+ if (m_patcnt == 0) m_patcnt = m_patmult; \
if (m_patidx == 0) m_patidx = 7;
@@ -793,8 +793,8 @@ private:
m_monitor_suggested = m_inp13->read(); \
m_gdc_indirect_register = 0; \
m_gdc_color_map_index = 0; \
- for (int i = 0; i < 256; i++) \
- m_gdc_scroll_buffer[i] = i; \
+ for (int i = 0; i < 256; i++) \
+ m_gdc_scroll_buffer[i] = i; \
m_gdc_scroll_index = 0; \
m_gdc_write_buffer_index = 0; \
m_gdc_write_mask = 0x00; \
@@ -2175,11 +2175,11 @@ READ8_MEMBER(rainbow_state::system_parameter_r)
return ((m_inp5->read() == 1 ? 0 : 1) |
(m_inp7->read() == 1 ? 0 : 4) | // Floppy is always present (bit 1 zero)
#ifdef OLD_RAM_BOARD_PRESENT
- (m_inp8->read() > MOTHERBOARD_RAM ? 0 : 8) |
+ (m_inp8->read() > MOTHERBOARD_RAM ? 0 : 8) |
#else
- 8 | // unverified
+ 8 | // unverified
#endif
- 16 | 32 | 64 | 128); // unverified
+ 16 | 32 | 64 | 128); // unverified
}
// [02] COMMUNICATIONS STATUS REGISTER - PAGE 154 (**** READ **** )
@@ -2198,7 +2198,7 @@ READ8_MEMBER(rainbow_state::comm_control_r)
is_mhfu_enabled = m_crtc->MHFU(MHFU_IS_ENABLED);
return (m_comm_port->ri_r() ? 0x01 : 0x00) |
- (m_comm_port->si_r() ? 0x02 : 0x00) |
+ (m_comm_port->si_r() ? 0x02 : 0x00) |
(m_comm_port->dsr_r() ? 0x04 : 0x00) |
(m_comm_port->cts_r() ? 0x08 : 0x00) |
(m_comm_port->dcd_r() ? 0x10 : 0x00) |
@@ -2355,13 +2355,13 @@ READ8_MEMBER(rainbow_state::z80_generalstat_r)
}
// logerror(" RDY:%x WG:%d ",fdc_ready,fdc_write_gate);
int data = (fdc_step ? 0x00 : 0x80) |
- (fdc_write_gate ? 0x00 : 0x40) |
- (tk00 ? 0x20 : 0x00) | // ***** ALL LOW ACTIVE - EXCEPT tk00 :
- (last_dir ? 0x00 : 0x10) |
- (fdc_ready ? 0x00 : 0x08) |
- (m_int88 ? 0x00 : 0x04) |
- (m_intz80 ? 0x00 : 0x02) |
- (m_zflip ? 0x00 : 0x01);
+ (fdc_write_gate ? 0x00 : 0x40) |
+ (tk00 ? 0x20 : 0x00) | // ***** ALL LOW ACTIVE - EXCEPT tk00 :
+ (last_dir ? 0x00 : 0x10) |
+ (fdc_ready ? 0x00 : 0x08) |
+ (m_int88 ? 0x00 : 0x04) |
+ (m_intz80 ? 0x00 : 0x02) |
+ (m_zflip ? 0x00 : 0x01);
return data;
}
@@ -3151,7 +3151,7 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
// NEXT: 32 BYTE COLOR MAP, LOADED TO $51
//if (m_gdc_indirect_register & GDC_SELECT_MODE_REGISTER) // 0x40
- // logerror(" *** SELECT MODE REGISTER");
+ // logerror(" *** SELECT MODE REGISTER");
if (m_gdc_indirect_register & GDC_SELECT_SCROLL_MAP) // 0x80
{
diff --git a/src/mame/drivers/rulechan.cpp b/src/mame/drivers/rulechan.cpp
index 08ee4c57b68..c421cf10508 100644
--- a/src/mame/drivers/rulechan.cpp
+++ b/src/mame/drivers/rulechan.cpp
@@ -21,7 +21,7 @@
PCB specs: Hardware not available
-
+
*********************************************************************
Edge Connector:
@@ -72,7 +72,7 @@
+---------------------------------------+-----+-----+-----+-----------------------------+
| Demo No | | | OFF | |
| Si | | | ON | |
- +---------------------------------------+-----+-----+-----+-----+-----------------------+
+ +---------------------------------------+-----+-----+-----+-----+-----------------------+
| Acceso a Pagina No | | OFF | |
| (settings access) Si | | ON | |
+---------------------------------------+-----------------+-----+-----+-----------------+
@@ -96,18 +96,18 @@
-------------------
(You must enable "LAMPS" layout for this procedure)
-
+
When the game runs by the very first time (no nvram yet), it will
complain about "DATA ERROR" in a blue message window. After a few
- seconds, it will bring up another red window with the "HARD ERROR 02"
+ seconds, it will bring up another red window with the "HARD ERROR 02"
message.
-
+
So, we must initialize the game following the next instructions:
-
+
1.- Toggle ON "Operator Key" (turn to green).
- 2.- Press once "Page Key". It will show a green window titled
- "CONTROL ADMINISTRATIVO" and a message with a security token.
+ 2.- Press once "Page Key". It will show a green window titled
+ "CONTROL ADMINISTRATIVO" and a message with a security token.
3.- Press again "Page Key". It will bring up a new window where we
must type a password. At this time, in the layout, under the
@@ -115,25 +115,25 @@
4.- Enter the required paswword using the credits in (IN1....IN6)
and credits out (OUT1...OUT6) buttons following the key assignment
- indications located under the password field.
- Use the "E" button to finish once all numbers were typed.
- Use the "B" button clear last digit typed, in case of mistake.
+ indications located under the password field.
+ Use the "E" button to finish once all numbers were typed.
+ Use the "B" button clear last digit typed, in case of mistake.
5.- Once finished that, the game will reboot and will be ready
to play. Also, password showed on layout will dissapear.
- In case that (by unknown reason) the game asks for
- "CONTROL ADMINISTRATIVO" again, follow the instructions starting
- from step "1". After that, we will can play again.
+ In case that (by unknown reason) the game asks for
+ "CONTROL ADMINISTRATIVO" again, follow the instructions starting
+ from step "1". After that, we will can play again.
*********************************************************************/
-
-
+
+
/*********************************************************************
Dev notes:
-
+
Again, this driver was written based on a couple of ROM dumps and a
lot of reverse engineering, with no harware available, but guessing
that this firmware and hardware are similar to others well known
@@ -141,30 +141,30 @@
The most exciting part of this work was discover that this game runs
with an electromechanical roulette, not a tipical LED roulette. It
- added an extra challenge to the work, wich implies a full develop
+ added an extra challenge to the work, wich implies a full develop
of an electromechanical part simulation, objective that finally
could be reached.
-
- Surprisingly, this game firmware includes a full communications
+
+ Surprisingly, this game firmware includes a full communications
module, accesible via RS232 serial interface, that let the users
some useful things like reconfigure hardware and game options or
- get different kinds of reports, like accounting, statistics and
+ get different kinds of reports, like accounting, statistics and
many other technical items. All this tasks are performed from a
PC running a D.O.S. program provided by the maker and fortunately
still available. Even more, there is another standalone D.O.S.
software provided by the manufacturer (also still available) to
get the passwords needed when hardware fails or administrative
tasks are required.
-
- Another interesting thing found on this game is that it can be
+
+ Another interesting thing found on this game is that it can be
configured for a single or a double zero roulette, depending on
what kind of roulette has attached.
-
+
*********************************************************************/
-#define CPU_CLOCK XTAL(8'000'000) // guess
+#define CPU_CLOCK XTAL(8'000'000) // guess
#define VID_CLOCK XTAL(21'477'272) // guess
#define TMS_CLOCK (CPU_CLOCK / 4) // guess
#define VDP_MEM 0x20000 // 4x 4464 (64K x 4 DRAM)
@@ -311,7 +311,7 @@ void rulechan_state::main_io(address_map &map)
map(0x31, 0x31).rw(FUNC(rulechan_state::port31_r),FUNC(rulechan_state::port31_w)); // wheel control - read: Must be 0x00 at power-up.
map(0x32, 0x32).w(FUNC(rulechan_state::port32_w)); // wheel control.
map(0x40, 0x43).nopr().nopw();
- map(0x60, 0x60).nopw(); // Watchdog.
+ map(0x60, 0x60).nopw(); // Watchdog.
}
@@ -334,7 +334,7 @@ READ8_MEMBER(rulechan_state::port3_r)
return 0xff;
}
-/******************************
+/******************************
Port 30 - Wheel control *
* bit 2 - ball detector *
* bit 3 - step detector *
@@ -397,7 +397,7 @@ WRITE8_MEMBER(rulechan_state::port31_w)
}
if(BIT(m_p31, 7)) // Shoot ball.
- {
+ {
m_p30 &= 0xdf; // ball out....
m_num = machine().rand() % 37; // sort winning number.
@@ -426,7 +426,7 @@ void rulechan_state::sound_off()
{
m_maincpu->space(AS_IO).write_byte(0x10, 0x07);
m_maincpu->space(AS_IO).write_byte(0x11, m_maincpu->space(AS_PROGRAM).read_byte(SND_FLG) | 0x20);
- m_maincpu->space(AS_IO).write_byte(0x10, 0x0e);
+ m_maincpu->space(AS_IO).write_byte(0x10, 0x0e);
}
void rulechan_state::sound_sort()
@@ -436,9 +436,9 @@ void rulechan_state::sound_sort()
m_maincpu->space(AS_IO).write_byte(0x10, m_sndsrt[(2 * i)]);
m_maincpu->space(AS_IO).write_byte(0x11, m_sndsrt[(2 * i) + 1]);
}
- m_maincpu->space(AS_IO).write_byte(0x10, 0x07);
+ m_maincpu->space(AS_IO).write_byte(0x10, 0x07);
m_maincpu->space(AS_IO).write_byte(0x11, m_maincpu->space(AS_PROGRAM).read_byte(SND_FLG) & 0xdf);
- m_maincpu->space(AS_IO).write_byte(0x10, 0x0e);
+ m_maincpu->space(AS_IO).write_byte(0x10, 0x0e);
}
@@ -451,24 +451,24 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
if(m_step == 0)
{
if((BIT4) & (m_updn4 == 0))
- {
+ {
m_p30 &= 0xef;
m_updn4 = 1;
//logerror("1:port_p30:- Reset bit 4 pulse start -%2x cont_pasos:%2d\n",m_p30, m_step);
return;
}
-
+
if((!BIT4) & (m_updn4 == 1))
- {
+ {
m_p30 |= 0x10;
-
+
//logerror("2:port_p30:- Set bit 4 -%2x cont_pasos:%2d\n",m_p30, m_step);
return;
- }
-
+ }
+
if((BIT4) & (m_updn4 == 1))
- {
+ {
m_updn4 = 0;
m_step++;
@@ -485,9 +485,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
//logerror("4:port_p30:-reset bit 3 -%2x cont_pasos:%2d\n",m_p30, m_step);
return;
}
-
+
if(!BIT3 & (m_updn3 == 0))
- {
+ {
if(!BIT2)
{
m_p30 |= 0x04;
@@ -497,13 +497,13 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
}
else
{
- if((m_step - 1 == m_num) & (m_updn2 == 0))
+ if((m_step - 1 == m_num) & (m_updn2 == 0))
{
if(!BIT5) // ball in pocket?...
- {
+ {
m_p30 &= 0xfb;
m_updn2 = 1;
- m_ballin++;
+ m_ballin++;
logerror("Ball In Pocket m_num:%2x\n", m_num);
return;
}
@@ -513,18 +513,18 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
m_updn2 = 0;
m_updn3 = 1;
}
-
+
if(!BIT3 & (m_updn3 == 1))
{
m_p30 |= 0x08;
m_updn3 = 0;
m_step++;
-
+
if (m_step == 39)
{
m_step = 0;
m_p30 |= 0x1c;
- }
+ }
//logerror("6:port_p30:-set bit 3 -%2x cont_pasos:%2d \n",m_p30, m_step);
return;
@@ -540,7 +540,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::wheel_speed)
TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::ball_speed)
{
if(MOTORON)
- {
+ {
if(d_spin == 0)
{
m_tspin++;
@@ -550,18 +550,18 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::ball_speed)
{
m_tspin = 37; // breaking ball once per number step.
}
-
+
if(m_tspin == 37)
{
m_tspin = 0;
m_spin++;
d_spin = m_spin; // breaking ball once per round.
}
-
+
if((!BALLIN) | (LEDNOTNUM & BALLIN ))
{
m_led++;
-
+
if(m_led == 37)
{
m_led = 0;
@@ -596,7 +596,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(rulechan_state::ball_speed)
/* if needed, get pass and shows it on layout*/
m_pass[0] = m_maincpu->space(AS_PROGRAM).read_byte(RAM_PSW);
- if((m_pass[0] <= 0x39) & (m_pass[0] >= 0x30))
+ if((m_pass[0] <= 0x39) & (m_pass[0] >= 0x30))
{
for(int i = 0; i < 6; i++)
{
@@ -687,7 +687,7 @@ static INPUT_PORTS_START( rulechan )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_TOGGLE PORT_CODE(KEYCODE_0)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
- PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_93cxx_device, do_read) // bit 6 is EEPROM data.
+ PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_serial_93cxx_device, do_read) // bit 6 is EEPROM data.
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_CODE(KEYCODE_9)
PORT_START("DSW")
@@ -737,27 +737,27 @@ MACHINE_CONFIG_START(rulechan_state::rulechan)
/* nvram */
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
-
+
/* eeprom */
EEPROM_93C46_8BIT(config, "eeprom");
-
+
MCFG_TIMER_DRIVER_ADD_PERIODIC("ball_speed", rulechan_state, ball_speed, attotime::from_hz(60))
MCFG_TIMER_DRIVER_ADD_PERIODIC("wheel_speed", rulechan_state, wheel_speed, attotime::from_hz(60))
-
+
/* video hardware */
v9938_device &v9938(V9938(config, "v9938", VID_CLOCK));
v9938.set_screen_ntsc("screen");
v9938.set_vram_size(VDP_MEM);
//v9938.int_cb().set_inputline("maincpu", 0);
SCREEN(config, "screen", SCREEN_TYPE_RASTER);
-
+
/* sound hardware */
SPEAKER(config, "mono").front_center();
ay8910_device &ay_re900(AY8910(config, "ay8910", TMS_CLOCK));
ay_re900.port_a_read_callback().set(FUNC(rulechan_state::psg_portA_r));
ay_re900.port_b_read_callback().set(FUNC(rulechan_state::psg_portB_r));
ay_re900.add_route(ALL_OUTPUTS, "mono", 0.5);
-
+
MACHINE_CONFIG_END
@@ -788,7 +788,7 @@ ROM_END
void rulechan_state::rulechan_init()
{
- m_p30 = 0x3c;
+ m_p30 = 0x3c;
m_p32 = 0xf0; // Motor off at startup
m_step = 0;
m_updn2 = 0;
diff --git a/src/mame/drivers/samcoupe.cpp b/src/mame/drivers/samcoupe.cpp
index 2f13fdd8745..372a6d4dde9 100644
--- a/src/mame/drivers/samcoupe.cpp
+++ b/src/mame/drivers/samcoupe.cpp
@@ -515,7 +515,7 @@ void samcoupe_state::samcoupe(machine_config &config)
/* video hardware */
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(SAMCOUPE_XTAL_X1/2, SAM_TOTAL_WIDTH, 0, SAM_BORDER_LEFT + SAM_SCREEN_WIDTH + SAM_BORDER_RIGHT,
- SAM_TOTAL_HEIGHT, 0, SAM_BORDER_TOP + SAM_SCREEN_HEIGHT + SAM_BORDER_BOTTOM);
+ SAM_TOTAL_HEIGHT, 0, SAM_BORDER_TOP + SAM_SCREEN_HEIGHT + SAM_BORDER_BOTTOM);
m_screen->set_screen_update(FUNC(samcoupe_state::screen_update));
m_screen->set_palette("palette");
diff --git a/src/mame/drivers/seta2.cpp b/src/mame/drivers/seta2.cpp
index 33be4d99df0..1262103859f 100644
--- a/src/mame/drivers/seta2.cpp
+++ b/src/mame/drivers/seta2.cpp
@@ -4346,7 +4346,7 @@ ROM_START( telpacfl )
ROM_REGION( 0x800000, "unused", ROMREGION_ERASE00 ) // Sprites
// not decoding the bad ROM is better than loading corrupt gfx data
ROM_LOAD64_WORD( "mp3_cg-2__u21_v1.0.u21", 0x000004, 0x200000, BAD_DUMP CRC(54dc430b) SHA1(a2e55866249d01f6f2f2dd998421baf9fe0c6972) ) // physically damaged eprom
-
+
ROM_REGION( 0x100000, "x1snd", 0 ) // Samples
ROM_LOAD( "mp3_sound0__u111_v1.0.u111", 0x000000, 0x080000, CRC(711c915e) SHA1(d654a0c158cf54aab5faca913583c5620388aa46) )
ROM_LOAD( "mp3_sound1__u112_v1.0.u112", 0x080000, 0x080000, CRC(27fd83cd) SHA1(d0261b2c5354ea17061e71bcea747d70efc18a49) )
diff --git a/src/mame/drivers/snesb.cpp b/src/mame/drivers/snesb.cpp
index ffeff63c862..376ccaa3095 100644
--- a/src/mame/drivers/snesb.cpp
+++ b/src/mame/drivers/snesb.cpp
@@ -1172,66 +1172,66 @@ void snesb_state::init_rushbets()
void snesb_state::init_venom()
{
- uint8_t *src = memregion("user7")->base();
- uint8_t *dst = memregion("user3")->base();
-
- static uint8_t address_tab_high[0x60] = {
- 0x00, 0x11, 0x02, 0x13, 0x04, 0x15, 0x06, 0x17, 0x08, 0x19, 0x0a, 0x1b, 0x0c, 0x1d, 0x0e, 0x1f,
- 0x20, 0x31, 0x22, 0x33, 0x24, 0x35, 0x26, 0x37, 0x28, 0x39, 0x2a, 0x3b, 0x2c, 0x3d, 0x2e, 0x3f,
- 0x10, 0x01, 0x12, 0x03, 0x14, 0x05, 0x16, 0x07, 0x18, 0x09, 0x1a, 0x0b, 0x1c, 0x0d, 0x1e, 0x0f,
- 0x30, 0x21, 0x32, 0x23, 0x34, 0x25, 0x36, 0x27, 0x38, 0x29, 0x3a, 0x2b, 0x3c, 0x2d, 0x3e, 0x2f,
- 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
- 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f
- };
-
- static uint8_t address_tab_low[0x40] = {
- 0x14, 0x1d, 0x11, 0x3c, 0x0a, 0x29, 0x2d, 0x2e, 0x30, 0x32, 0x16, 0x36, 0x05, 0x25, 0x26, 0x37,
- 0x20, 0x21, 0x27, 0x28, 0x33, 0x34, 0x23, 0x12, 0x1e, 0x1f, 0x3b, 0x24, 0x2c, 0x35, 0x38, 0x39,
- 0x3d, 0x0c, 0x2a, 0x0d, 0x22, 0x18, 0x19, 0x1a, 0x03, 0x08, 0x04, 0x3a, 0x0b, 0x0f, 0x15, 0x17,
- 0x1b, 0x13, 0x00, 0x1c, 0x2b, 0x01, 0x06, 0x2f, 0x07, 0x09, 0x02, 0x31, 0x10, 0x0e, 0x3f, 0x3e
- };
-
- static uint8_t data_table[0x100] = {
- 0x6a, 0xf2, 0xe0, 0xea, 0xe8, 0x60, 0x62, 0xe2, 0x70, 0xfa, 0x7a, 0x78, 0xf0, 0x68, 0x72, 0xf8,
- 0x4f, 0xd7, 0xc5, 0xcf, 0xcd, 0x45, 0x47, 0xc7, 0x55, 0xdf, 0x5f, 0x5d, 0xd5, 0x4d, 0x57, 0xdd,
- 0x0e, 0x96, 0x84, 0x8e, 0x8c, 0x04, 0x06, 0x86, 0x14, 0x9e, 0x1e, 0x1c, 0x94, 0x0c, 0x16, 0x9c,
- 0x6e, 0xf6, 0xe4, 0xee, 0xec, 0x64, 0x66, 0xe6, 0x74, 0xfe, 0x7e, 0x7c, 0xf4, 0x6c, 0x76, 0xfc,
- 0x2e, 0xb6, 0xa4, 0xae, 0xac, 0x24, 0x26, 0xa6, 0x34, 0xbe, 0x3e, 0x3c, 0xb4, 0x2c, 0x36, 0xbc,
- 0x0a, 0x92, 0x80, 0x8a, 0x88, 0x00, 0x02, 0x82, 0x10, 0x9a, 0x1a, 0x18, 0x90, 0x08, 0x12, 0x98,
- 0x4a, 0xd2, 0xc0, 0xca, 0xc8, 0x40, 0x42, 0xc2, 0x50, 0xda, 0x5a, 0x58, 0xd0, 0x48, 0x52, 0xd8,
- 0x4e, 0xd6, 0xc4, 0xce, 0xcc, 0x44, 0x46, 0xc6, 0x54, 0xde, 0x5e, 0x5c, 0xd4, 0x4c, 0x56, 0xdc,
- 0x0b, 0x93, 0x81, 0x8b, 0x89, 0x01, 0x03, 0x83, 0x11, 0x9b, 0x1b, 0x19, 0x91, 0x09, 0x13, 0x99,
- 0x6f, 0xf7, 0xe5, 0xef, 0xed, 0x65, 0x67, 0xe7, 0x75, 0xff, 0x7f, 0x7d, 0xf5, 0x6d, 0x77, 0xfd,
- 0x6b, 0xf3, 0xe1, 0xeb, 0xe9, 0x61, 0x63, 0xe3, 0x71, 0xfb, 0x7b, 0x79, 0xf1, 0x69, 0x73, 0xf9,
- 0x2b, 0xb3, 0xa1, 0xab, 0xa9, 0x21, 0x23, 0xa3, 0x31, 0xbb, 0x3b, 0x39, 0xb1, 0x29, 0x33, 0xb9,
- 0x0f, 0x97, 0x85, 0x8f, 0x8d, 0x05, 0x07, 0x87, 0x15, 0x9f, 0x1f, 0x1d, 0x95, 0x0d, 0x17, 0x9d,
- 0x2a, 0xb2, 0xa0, 0xaa, 0xa8, 0x20, 0x22, 0xa2, 0x30, 0xba, 0x3a, 0x38, 0xb0, 0x28, 0x32, 0xb8,
- 0x4b, 0xd3, 0xc1, 0xcb, 0xc9, 0x41, 0x43, 0xc3, 0x51, 0xdb, 0x5b, 0x59, 0xd1, 0x49, 0x53, 0xd9,
- 0x2f, 0xb7, 0xa5, 0xaf, 0xad, 0x25, 0x27, 0xa7, 0x35, 0xbf, 0x3f, 0x3d, 0xb5, 0x2d, 0x37, 0xbd
- };
-
- for (int i = 0; i < 0x300000; i++)
- {
- int j = (address_tab_high[i >> 15] << 15) + (i & 0x7fc0) + address_tab_low[i & 0x3f];
-
- dst[i] = data_table[src[j]];
-
- if (i >= 0x00000 && i < 0x10000) {
- dst[i] = bitswap<8>(dst[i], 6, 7, 0, 3, 1, 4, 2, 5) ^ 0xff;
- }
-
- if (i >= 0x10000 && i < 0x20000) {
- dst[i] = bitswap<8>(dst[i], 0, 1, 4, 5, 3, 7, 6, 2);
- }
-
- if (i >= 0x20000 && i < 0x30000) {
- dst[i] = bitswap<8>(dst[i], 1, 3, 2, 6, 5, 4, 0, 7) ^ 0xff;
- }
-
- if (i >= 0x30000 && i < 0x40000) {
- dst[i] = bitswap<8>(dst[i], 4, 0, 7, 6, 2, 1, 5, 3);
- }
- }
+ uint8_t *src = memregion("user7")->base();
+ uint8_t *dst = memregion("user3")->base();
+
+ static uint8_t address_tab_high[0x60] = {
+ 0x00, 0x11, 0x02, 0x13, 0x04, 0x15, 0x06, 0x17, 0x08, 0x19, 0x0a, 0x1b, 0x0c, 0x1d, 0x0e, 0x1f,
+ 0x20, 0x31, 0x22, 0x33, 0x24, 0x35, 0x26, 0x37, 0x28, 0x39, 0x2a, 0x3b, 0x2c, 0x3d, 0x2e, 0x3f,
+ 0x10, 0x01, 0x12, 0x03, 0x14, 0x05, 0x16, 0x07, 0x18, 0x09, 0x1a, 0x0b, 0x1c, 0x0d, 0x1e, 0x0f,
+ 0x30, 0x21, 0x32, 0x23, 0x34, 0x25, 0x36, 0x27, 0x38, 0x29, 0x3a, 0x2b, 0x3c, 0x2d, 0x3e, 0x2f,
+ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
+ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f
+ };
+
+ static uint8_t address_tab_low[0x40] = {
+ 0x14, 0x1d, 0x11, 0x3c, 0x0a, 0x29, 0x2d, 0x2e, 0x30, 0x32, 0x16, 0x36, 0x05, 0x25, 0x26, 0x37,
+ 0x20, 0x21, 0x27, 0x28, 0x33, 0x34, 0x23, 0x12, 0x1e, 0x1f, 0x3b, 0x24, 0x2c, 0x35, 0x38, 0x39,
+ 0x3d, 0x0c, 0x2a, 0x0d, 0x22, 0x18, 0x19, 0x1a, 0x03, 0x08, 0x04, 0x3a, 0x0b, 0x0f, 0x15, 0x17,
+ 0x1b, 0x13, 0x00, 0x1c, 0x2b, 0x01, 0x06, 0x2f, 0x07, 0x09, 0x02, 0x31, 0x10, 0x0e, 0x3f, 0x3e
+ };
+
+ static uint8_t data_table[0x100] = {
+ 0x6a, 0xf2, 0xe0, 0xea, 0xe8, 0x60, 0x62, 0xe2, 0x70, 0xfa, 0x7a, 0x78, 0xf0, 0x68, 0x72, 0xf8,
+ 0x4f, 0xd7, 0xc5, 0xcf, 0xcd, 0x45, 0x47, 0xc7, 0x55, 0xdf, 0x5f, 0x5d, 0xd5, 0x4d, 0x57, 0xdd,
+ 0x0e, 0x96, 0x84, 0x8e, 0x8c, 0x04, 0x06, 0x86, 0x14, 0x9e, 0x1e, 0x1c, 0x94, 0x0c, 0x16, 0x9c,
+ 0x6e, 0xf6, 0xe4, 0xee, 0xec, 0x64, 0x66, 0xe6, 0x74, 0xfe, 0x7e, 0x7c, 0xf4, 0x6c, 0x76, 0xfc,
+ 0x2e, 0xb6, 0xa4, 0xae, 0xac, 0x24, 0x26, 0xa6, 0x34, 0xbe, 0x3e, 0x3c, 0xb4, 0x2c, 0x36, 0xbc,
+ 0x0a, 0x92, 0x80, 0x8a, 0x88, 0x00, 0x02, 0x82, 0x10, 0x9a, 0x1a, 0x18, 0x90, 0x08, 0x12, 0x98,
+ 0x4a, 0xd2, 0xc0, 0xca, 0xc8, 0x40, 0x42, 0xc2, 0x50, 0xda, 0x5a, 0x58, 0xd0, 0x48, 0x52, 0xd8,
+ 0x4e, 0xd6, 0xc4, 0xce, 0xcc, 0x44, 0x46, 0xc6, 0x54, 0xde, 0x5e, 0x5c, 0xd4, 0x4c, 0x56, 0xdc,
+ 0x0b, 0x93, 0x81, 0x8b, 0x89, 0x01, 0x03, 0x83, 0x11, 0x9b, 0x1b, 0x19, 0x91, 0x09, 0x13, 0x99,
+ 0x6f, 0xf7, 0xe5, 0xef, 0xed, 0x65, 0x67, 0xe7, 0x75, 0xff, 0x7f, 0x7d, 0xf5, 0x6d, 0x77, 0xfd,
+ 0x6b, 0xf3, 0xe1, 0xeb, 0xe9, 0x61, 0x63, 0xe3, 0x71, 0xfb, 0x7b, 0x79, 0xf1, 0x69, 0x73, 0xf9,
+ 0x2b, 0xb3, 0xa1, 0xab, 0xa9, 0x21, 0x23, 0xa3, 0x31, 0xbb, 0x3b, 0x39, 0xb1, 0x29, 0x33, 0xb9,
+ 0x0f, 0x97, 0x85, 0x8f, 0x8d, 0x05, 0x07, 0x87, 0x15, 0x9f, 0x1f, 0x1d, 0x95, 0x0d, 0x17, 0x9d,
+ 0x2a, 0xb2, 0xa0, 0xaa, 0xa8, 0x20, 0x22, 0xa2, 0x30, 0xba, 0x3a, 0x38, 0xb0, 0x28, 0x32, 0xb8,
+ 0x4b, 0xd3, 0xc1, 0xcb, 0xc9, 0x41, 0x43, 0xc3, 0x51, 0xdb, 0x5b, 0x59, 0xd1, 0x49, 0x53, 0xd9,
+ 0x2f, 0xb7, 0xa5, 0xaf, 0xad, 0x25, 0x27, 0xa7, 0x35, 0xbf, 0x3f, 0x3d, 0xb5, 0x2d, 0x37, 0xbd
+ };
+
+ for (int i = 0; i < 0x300000; i++)
+ {
+ int j = (address_tab_high[i >> 15] << 15) + (i & 0x7fc0) + address_tab_low[i & 0x3f];
+
+ dst[i] = data_table[src[j]];
+
+ if (i >= 0x00000 && i < 0x10000) {
+ dst[i] = bitswap<8>(dst[i], 6, 7, 0, 3, 1, 4, 2, 5) ^ 0xff;
+ }
+
+ if (i >= 0x10000 && i < 0x20000) {
+ dst[i] = bitswap<8>(dst[i], 0, 1, 4, 5, 3, 7, 6, 2);
+ }
+
+ if (i >= 0x20000 && i < 0x30000) {
+ dst[i] = bitswap<8>(dst[i], 1, 3, 2, 6, 5, 4, 0, 7) ^ 0xff;
+ }
+
+ if (i >= 0x30000 && i < 0x40000) {
+ dst[i] = bitswap<8>(dst[i], 4, 0, 7, 6, 2, 1, 5, 3);
+ }
+ }
// boot vector
dst[0x7ffc] = 0x98;
@@ -1247,7 +1247,7 @@ void snesb_state::init_venom()
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770073, 0x770073, read8_delegate(FUNC(snesb_state::snesb_dsw2_r),this));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770079, 0x770079, read8_delegate(FUNC(snesb_state::snesb_coin_r),this));
- init_snes();
+ init_snes();
}
ROM_START( kinstb )
@@ -1449,10 +1449,10 @@ ROM_START( venom )
ROM_REGION(0x800, "user6", ROMREGION_ERASEFF)
ROM_REGION( 0x300000, "user7", 0 )
- ROM_LOAD( "u31.bin", 0x000000, 0x0100000, CRC(d1034a76) SHA1(541dd92197ca2e4eb686e426c840aad847d02be8) )
- ROM_LOAD( "u32.bin", 0x100000, 0x0100000, CRC(fbe865b0) SHA1(25467a6faa912bf180c5dd7aecee77c3b5f207f8) )
- ROM_LOAD( "u33.bin", 0x200000, 0x0080000, CRC(ed874ca2) SHA1(cfc90b38ea2eea07e990f0b72d7c1af2a7076beb) )
- ROM_LOAD( "u34.bin", 0x280000, 0x0080000, CRC(7a09c9e0) SHA1(794965d5501ec0e21f1f3a8cb8fd66f913d42760) )
+ ROM_LOAD( "u31.bin", 0x000000, 0x0100000, CRC(d1034a76) SHA1(541dd92197ca2e4eb686e426c840aad847d02be8) )
+ ROM_LOAD( "u32.bin", 0x100000, 0x0100000, CRC(fbe865b0) SHA1(25467a6faa912bf180c5dd7aecee77c3b5f207f8) )
+ ROM_LOAD( "u33.bin", 0x200000, 0x0080000, CRC(ed874ca2) SHA1(cfc90b38ea2eea07e990f0b72d7c1af2a7076beb) )
+ ROM_LOAD( "u34.bin", 0x280000, 0x0080000, CRC(7a09c9e0) SHA1(794965d5501ec0e21f1f3a8cb8fd66f913d42760) )
ROM_END
GAME( 199?, kinstb, 0, kinstb, kinstb, snesb_state, init_kinstb, ROT0, "bootleg", "Killer Instinct (SNES bootleg)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )
diff --git a/src/mame/drivers/vii.cpp b/src/mame/drivers/vii.cpp
index 0fd09f99796..21c557153a2 100644
--- a/src/mame/drivers/vii.cpp
+++ b/src/mame/drivers/vii.cpp
@@ -12,26 +12,26 @@
To-Do:
- Proper driver_device inheritance to untangle the mess of members
-
- Detailed list of bugs:
-
- All systems:
- Various inaccuracies in samples/envelopes.
-
- walle:
- Game seems unhappy with NVRAM, clears contents on each boot.
- rad_skat:
- Palette issues on the High Score screen.
- vii:
- When loading a cart from file manager, sometimes MAME will crash.
- The "MOTOR" option in the diagnostic menu does nothing when selected.
- The "SPEECH IC" option in the diagnostic menu does nothing when selected.
- On 'vii_vc1' & 'vii_vc2' cart, the left-right keys are transposed with the up-down keys.
- - This is not a bug per se, as the games are played with the controller physically rotated 90 degrees.
- When entering a game in Basketball, MAME fatalerrors when starting the game due to jumping to invalid code.
- zone60/wirels60:
- When entering a game in Basketball, MAME fatalerrors when starting the game due to jumping to invalid code.
+ Proper driver_device inheritance to untangle the mess of members
+
+ Detailed list of bugs:
+
+ All systems:
+ Various inaccuracies in samples/envelopes.
+
+ walle:
+ Game seems unhappy with NVRAM, clears contents on each boot.
+ rad_skat:
+ Palette issues on the High Score screen.
+ vii:
+ When loading a cart from file manager, sometimes MAME will crash.
+ The "MOTOR" option in the diagnostic menu does nothing when selected.
+ The "SPEECH IC" option in the diagnostic menu does nothing when selected.
+ On 'vii_vc1' & 'vii_vc2' cart, the left-right keys are transposed with the up-down keys.
+ - This is not a bug per se, as the games are played with the controller physically rotated 90 degrees.
+ When entering a game in Basketball, MAME fatalerrors when starting the game due to jumping to invalid code.
+ zone60/wirels60:
+ When entering a game in Basketball, MAME fatalerrors when starting the game due to jumping to invalid code.
*******************************************************************************/
diff --git a/src/mame/drivers/vsmile.cpp b/src/mame/drivers/vsmile.cpp
index 79a318ec6af..69da8f95d67 100644
--- a/src/mame/drivers/vsmile.cpp
+++ b/src/mame/drivers/vsmile.cpp
@@ -10,18 +10,18 @@
To-Do:
- Proper UART support (SPG2xx) for controller
-
- Similar Systems: ( from http://en.wkikpedia.org/wiki/V.Smile )
-
- V.Smile by VTech, a system designed for children under the age of 10
- V.Smile Pocket (2 versions)
- V.Smile Cyber Pocket
- V.Smile PC Pal
- V-Motion Active Learning System
- Leapster
- V.Smile Baby Infant Development System
- V.Flash
+ Proper UART support (SPG2xx) for controller
+
+ Similar Systems: ( from http://en.wkikpedia.org/wiki/V.Smile )
+
+ V.Smile by VTech, a system designed for children under the age of 10
+ V.Smile Pocket (2 versions)
+ V.Smile Cyber Pocket
+ V.Smile PC Pal
+ V-Motion Active Learning System
+ Leapster
+ V.Smile Baby Infant Development System
+ V.Flash
*******************************************************************************/
diff --git a/src/mame/drivers/ymmu100.cpp b/src/mame/drivers/ymmu100.cpp
index 24cd390da1d..a45442ae3a6 100644
--- a/src/mame/drivers/ymmu100.cpp
+++ b/src/mame/drivers/ymmu100.cpp
@@ -517,7 +517,7 @@ void mu100_state::mu100_map(address_map &map)
u16 mu100_state::adc0_r()
{
- // logerror("adc0_r\n");
+ // logerror("adc0_r\n");
return 0;
}
@@ -615,7 +615,7 @@ void mu100_state::p6_w(u16 data)
u16 mu100_state::p6_r()
{
- // logerror("plug in detect read\n");
+ // logerror("plug in detect read\n");
return 0x00;
}
diff --git a/src/mame/includes/playmark.h b/src/mame/includes/playmark.h
index 8bd73db762e..a2dbede2a02 100644
--- a/src/mame/includes/playmark.h
+++ b/src/mame/includes/playmark.h
@@ -68,7 +68,7 @@ protected:
int m_yoffset;
int m_pri_masks[3];
uint16_t m_scroll[7];
- int m_sprtranspen;
+ int m_sprtranspen;
/* misc */
uint16_t m_snd_command;
diff --git a/src/mame/includes/seta2.h b/src/mame/includes/seta2.h
index bb81b0a0148..a40e22c4cbc 100644
--- a/src/mame/includes/seta2.h
+++ b/src/mame/includes/seta2.h
@@ -124,7 +124,7 @@ protected:
optional_device<eeprom_serial_93cxx_device> m_eeprom;
optional_device<intelfsh16_device> m_flash;
optional_device<ticket_dispenser_device> m_dispenser;
-
+
optional_memory_bank_array<8> m_x1_bank;
optional_shared_ptr<uint16_t> m_nvram;
optional_shared_ptr<uint16_t> m_spriteram;
diff --git a/src/mame/includes/spacefb.h b/src/mame/includes/spacefb.h
index 22deee4b971..81eb75bd6c5 100644
--- a/src/mame/includes/spacefb.h
+++ b/src/mame/includes/spacefb.h
@@ -100,4 +100,4 @@ private:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
};
-#endif // MAME_INCLUDES_SPACEFB \ No newline at end of file
+#endif // MAME_INCLUDES_SPACEFB
diff --git a/src/mame/layout/hp3478a.lay b/src/mame/layout/hp3478a.lay
index ba1960d4a22..ab897c81bc8 100644
--- a/src/mame/layout/hp3478a.lay
+++ b/src/mame/layout/hp3478a.lay
@@ -131,10 +131,10 @@
<!-- to match the schematics, we consider Col.0-3 to be driven by P14-17. The value in "inputmask" is the one read as "p1 & 0x0F", i.e. P13-P10. -->
-<!-- col.0 : (nc)|shift|ACA|DCA
- col.1 : 4W|2W|ACV|DCV
- col.2 : int|dn|up|auto
- col.3 : (nc)|loc|srq|sgl -->
+<!-- col.0 : (nc)|shift|ACA|DCA
+ col.1 : 4W|2W|ACV|DCV
+ col.2 : int|dn|up|auto
+ col.3 : (nc)|loc|srq|sgl -->
<bezel element="hl" inputtag="COL.0" inputmask="0x01"><bounds x="65" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
<bezel element="hl" inputtag="COL.0" inputmask="0x02"><bounds x="80" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
<bezel element="hl" inputtag="COL.0" inputmask="0x04"><bounds x="95" y="35" width="10" height="10" /><color alpha="0.2" /></bezel>
diff --git a/src/mame/layout/rulechan.lay b/src/mame/layout/rulechan.lay
index 8aa58259373..243319aa89a 100644
--- a/src/mame/layout/rulechan.lay
+++ b/src/mame/layout/rulechan.lay
@@ -3,7 +3,7 @@
<element name="DIGIT" defstate="0">
<led7seg><color red="0.0" green="0.45" blue="0.45" /></led7seg>
- </element>
+ </element>
<element name="BALL0">
<disk state = "0">
<color red="0.0" green="0.3" blue="0" />
@@ -203,14 +203,14 @@
<screen index="0">
<bounds left="100" top="0" right="832" bottom="1072" />
</screen>
-
+
<bezel name="lamp10" element="DIGIT"><bounds x="1140" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
<bezel name="lamp11" element="DIGIT"><bounds x="1160" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
<bezel name="lamp12" element="DIGIT"><bounds x="1180" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
<bezel name="lamp13" element="DIGIT"><bounds x="1200" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
<bezel name="lamp14" element="DIGIT"><bounds x="1220" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
<bezel name="lamp15" element="DIGIT"><bounds x="1240" y="550" width="20" height="30" /><orientation rotate="0" /></bezel>
-
+
<bezel element="BBET" inputtag="IN0" inputmask="0x04" >
<bounds x="270" y="50" width="42" height="42" />
</bezel>
diff --git a/src/mame/machine/3dom2.cpp b/src/mame/machine/3dom2.cpp
index 82487d46c9b..42ec38f04e9 100644
--- a/src/mame/machine/3dom2.cpp
+++ b/src/mame/machine/3dom2.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Philip Bennett
/***************************************************************************
- 3DO M2 Bulldog ASIC
+ 3DO M2 Bulldog ASIC
***************************************************************************/
@@ -32,71 +32,71 @@ DEFINE_DEVICE_TYPE(M2_CDE, m2_cde_device, "m2cde", "3DO M2 CDE ASIC")
// VDU REGISTER DEFINITIONS
//**************************************************************************
-#define VDU_VLOC 0x00
-#define VDU_VINT 0x04
-#define VDU_VDC0 0x08
-#define VDU_VDC1 0x0c
-#define VDU_FV0A 0x10
-#define VDU_FV1A 0x14
-#define VDU_AVDI 0x1c
-#define VDU_VDLI 0x20
-#define VDU_VCFG 0x24
-#define VDU_DMT0 0x28
-#define VDU_DMT1 0x2c
-#define VDU_LFSR 0x30
-#define VDU_VRST 0x34
+#define VDU_VLOC 0x00
+#define VDU_VINT 0x04
+#define VDU_VDC0 0x08
+#define VDU_VDC1 0x0c
+#define VDU_FV0A 0x10
+#define VDU_FV1A 0x14
+#define VDU_AVDI 0x1c
+#define VDU_VDLI 0x20
+#define VDU_VCFG 0x24
+#define VDU_DMT0 0x28
+#define VDU_DMT1 0x2c
+#define VDU_LFSR 0x30
+#define VDU_VRST 0x34
//-------------------------------------------------
// VLOC
//-------------------------------------------------
-#define VDU_VLOC_VCOUNT_MASK 0x00003FF8
-#define VDU_VLOC_VCOUNT_SHIFT 3
-#define VDU_VLOC_VIDEOFIELD 0x00004000
-#define VDU_VLOC_RESERVED 0xFFFF8007
+#define VDU_VLOC_VCOUNT_MASK 0x00003FF8
+#define VDU_VLOC_VCOUNT_SHIFT 3
+#define VDU_VLOC_VIDEOFIELD 0x00004000
+#define VDU_VLOC_RESERVED 0xFFFF8007
//-------------------------------------------------
// VINT
//-------------------------------------------------
-#define VDU_VINT_VINT0 0x80000000
-#define VDU_VINT_VLINE0_MASK 0x7FF00000
-#define VDU_VINT_VLINE0_SHIFT 20
-#define VDU_VINT_VINT1 0x00008000
-#define VDU_VINT_VLINE1_MASK 0x00007FF0
-#define VDU_VINT_VLINE1_SHIFT 4
-#define VDU_VINT_RESERVED 0x000F000F
+#define VDU_VINT_VINT0 0x80000000
+#define VDU_VINT_VLINE0_MASK 0x7FF00000
+#define VDU_VINT_VLINE0_SHIFT 20
+#define VDU_VINT_VINT1 0x00008000
+#define VDU_VINT_VLINE1_MASK 0x00007FF0
+#define VDU_VINT_VLINE1_SHIFT 4
+#define VDU_VINT_RESERVED 0x000F000F
//-------------------------------------------------
// VDC0/VDC1
//-------------------------------------------------
-#define VDU_VDC_HINT 0x02000000
-#define VDU_VDC_VINT 0x01000000
-#define VDU_VDC_DITHER 0x00400000
-#define VDU_VDC_MTXBYP 0x00200000
-#define VDU_VDC_RESERVED 0xFC9FFFFF
+#define VDU_VDC_HINT 0x02000000
+#define VDU_VDC_VINT 0x01000000
+#define VDU_VDC_DITHER 0x00400000
+#define VDU_VDC_MTXBYP 0x00200000
+#define VDU_VDC_RESERVED 0xFC9FFFFF
//-------------------------------------------------
// AVDI
//-------------------------------------------------
-#define VDU_AVDI_HSTART_MASK 0xFFE00000
-#define VDU_AVDI_HWIDTH_MASK 0x0003FF80
-#define VDU_AVDI_HDOUBLE 0x00000008
-#define VDU_AVDI_VDOUBLE 0x00000004
-#define VDU_AVDI_RESERVED 0x001C0073
-#define VDU_AVDI_HSTART_SHIFT 21
-#define VDU_AVDI_HWIDTH_SHIFT 7
+#define VDU_AVDI_HSTART_MASK 0xFFE00000
+#define VDU_AVDI_HWIDTH_MASK 0x0003FF80
+#define VDU_AVDI_HDOUBLE 0x00000008
+#define VDU_AVDI_VDOUBLE 0x00000004
+#define VDU_AVDI_RESERVED 0x001C0073
+#define VDU_AVDI_HSTART_SHIFT 21
+#define VDU_AVDI_HWIDTH_SHIFT 7
//-------------------------------------------------
// VDLI
//-------------------------------------------------
-#define VDU_VDLI_BYPASSTYPE 0x10000000
-#define VDU_VDLI_FBFORMAT 0x04000000
-#define VDU_VDLI_ONEVINTDIS 0x00400000
-#define VDU_VDLI_RANDOMDITHER 0x00200000
-#define VDU_VDLI_RESERVED 0xEB9FFFFF
-#define VDU_VDLI_BYPASSTYPE_MSB 0
-#define VDU_VDLI_BYPASSTYPE_LSB 0x10000000
-#define VDU_VDLI_FBFORMAT_16 0
-#define VDU_VDLI_FBFORMAT_32 0x04000000
+#define VDU_VDLI_BYPASSTYPE 0x10000000
+#define VDU_VDLI_FBFORMAT 0x04000000
+#define VDU_VDLI_ONEVINTDIS 0x00400000
+#define VDU_VDLI_RANDOMDITHER 0x00200000
+#define VDU_VDLI_RESERVED 0xEB9FFFFF
+#define VDU_VDLI_BYPASSTYPE_MSB 0
+#define VDU_VDLI_BYPASSTYPE_LSB 0x10000000
+#define VDU_VDLI_FBFORMAT_16 0
+#define VDU_VDLI_FBFORMAT_32 0x04000000
//-------------------------------------------------
// VCFG
@@ -105,82 +105,82 @@ DEFINE_DEVICE_TYPE(M2_CDE, m2_cde_device, "m2cde", "3DO M2 CDE ASIC")
//-------------------------------------------------
// VRST
//-------------------------------------------------
-#define VDU_VRST_DVERESET 0x00000002
-#define VDU_VRST_VIDRESET 0x00000001
-#define VDU_VRST_RESERVED 0xFFFFFFFC
+#define VDU_VRST_DVERESET 0x00000002
+#define VDU_VRST_VIDRESET 0x00000001
+#define VDU_VRST_RESERVED 0xFFFFFFFC
//-------------------------------------------------
// VDL DMA CONTROL WORD
//-------------------------------------------------
-#define VDL_DMA_MOD_MASK 0xFF000000
-#define VDL_DMA_ENABLE 0x00200000
-#define VDL_DMA_NOBUCKET 0x00020000
-#define VDL_DMA_LDLOWER 0x00010000
-#define VDL_DMA_LDUPPER 0x00008000
-#define VDL_DMA_NWORDS_MASK 0x00007E00
-#define VDL_DMA_NLINES_MASK 0x000001FF
-#define VDL_DMA_RESERVED 0x00DC0000
-#define VDL_DMA_NWORDS_SHIFT 9
-#define VDL_DMA_MOD_SHIFT 24
-#define VDL_DMA_NLINES_SHIFT 0
+#define VDL_DMA_MOD_MASK 0xFF000000
+#define VDL_DMA_ENABLE 0x00200000
+#define VDL_DMA_NOBUCKET 0x00020000
+#define VDL_DMA_LDLOWER 0x00010000
+#define VDL_DMA_LDUPPER 0x00008000
+#define VDL_DMA_NWORDS_MASK 0x00007E00
+#define VDL_DMA_NLINES_MASK 0x000001FF
+#define VDL_DMA_RESERVED 0x00DC0000
+#define VDL_DMA_NWORDS_SHIFT 9
+#define VDL_DMA_MOD_SHIFT 24
+#define VDL_DMA_NLINES_SHIFT 0
//-------------------------------------------------
// VDL DC CONTROL WORD
//-------------------------------------------------
-#define VDL_DC 0x80000000
-#define VDL_DC_0 0x00000000
-#define VDL_DC_1 0x10000000
-#define VDL_DC_HINTCTL_MASK 0x00060000
-#define VDL_DC_HINTCTL_SHIFT 17
-#define VDL_DC_VINTCTL_MASK 0x00018000
-#define VDL_DC_VINTCTL_SHIFT 15
-#define VDL_DC_DITHERCTL_MASK 0x00001800
-#define VDL_DC_DITHERCTL_SHIFT 11
-#define VDL_DC_MTXBYPCTL_MASK 0x00000600
-#define VDL_DC_MTXBYPCTL_SHIFT 9
-#define VDL_DC_RESERVED 0x0FF861FF
-#define VDL_CTL_DISABLE 0
-#define VDL_CTL_ENABLE 1
-#define VDL_CTL_NOP 2
+#define VDL_DC 0x80000000
+#define VDL_DC_0 0x00000000
+#define VDL_DC_1 0x10000000
+#define VDL_DC_HINTCTL_MASK 0x00060000
+#define VDL_DC_HINTCTL_SHIFT 17
+#define VDL_DC_VINTCTL_MASK 0x00018000
+#define VDL_DC_VINTCTL_SHIFT 15
+#define VDL_DC_DITHERCTL_MASK 0x00001800
+#define VDL_DC_DITHERCTL_SHIFT 11
+#define VDL_DC_MTXBYPCTL_MASK 0x00000600
+#define VDL_DC_MTXBYPCTL_SHIFT 9
+#define VDL_DC_RESERVED 0x0FF861FF
+#define VDL_CTL_DISABLE 0
+#define VDL_CTL_ENABLE 1
+#define VDL_CTL_NOP 2
//-------------------------------------------------
// VDL AV CONTROL WORD
//-------------------------------------------------
-#define VDL_AV 0xA0000000
-#define VDL_AV_HSTART_MASK 0x1FFC0000
-#define VDL_AV_HSTART_SHIFT 18
-#define VDL_AV_LD_HSTART 0x00020000
-#define VDL_AV_HWIDTH_MASK 0x0001FFC0
-#define VDL_AV_HWIDTH_SHIFT 6
-#define VDL_AV_LD_HWIDTH 0x00000020
-#define VDL_AV_HDOUBLE 0x00000010
-#define VDL_AV_VDOUBLE 0x00000008
-#define VDL_AV_LD_HDOUBLE 0x00000004
-#define VDL_AV_LD_VDOUBLE 0x00000002
-#define VDL_AV_RESERVED 0x00000001
+#define VDL_AV 0xA0000000
+#define VDL_AV_HSTART_MASK 0x1FFC0000
+#define VDL_AV_HSTART_SHIFT 18
+#define VDL_AV_LD_HSTART 0x00020000
+#define VDL_AV_HWIDTH_MASK 0x0001FFC0
+#define VDL_AV_HWIDTH_SHIFT 6
+#define VDL_AV_LD_HWIDTH 0x00000020
+#define VDL_AV_HDOUBLE 0x00000010
+#define VDL_AV_VDOUBLE 0x00000008
+#define VDL_AV_LD_HDOUBLE 0x00000004
+#define VDL_AV_LD_VDOUBLE 0x00000002
+#define VDL_AV_RESERVED 0x00000001
//-------------------------------------------------
// VDL LC CONTROL WORD
//-------------------------------------------------
-#define VDL_LC 0xC0000000
-#define VDL_LC_BYPASSTYPE 0x02000000
-#define VDL_LC_FBFORMAT 0x00800000
-#define VDL_LC_ONEVINTDIS 0x00080000
-#define VDL_LC_RANDOMDITHER 0x00040000
-#define VDL_LC_LD_BYPASSTYPE 0x00002000
-#define VDL_LC_LD_FBFORMAT 0x00001000
-#define VDL_LC_RESERVED 0x1D73CFFF
-#define VDL_LC_BYPASSTYPE_MSB 0x00000000
-#define VDL_LC_BYPASSTYPE_LSB 0x02000000
-#define VDL_LC_FBFORMAT_16 0x00000000
-#define VDL_LC_FBFORMAT_32 0x00800000
+#define VDL_LC 0xC0000000
+#define VDL_LC_BYPASSTYPE 0x02000000
+#define VDL_LC_FBFORMAT 0x00800000
+#define VDL_LC_ONEVINTDIS 0x00080000
+#define VDL_LC_RANDOMDITHER 0x00040000
+#define VDL_LC_LD_BYPASSTYPE 0x00002000
+#define VDL_LC_LD_FBFORMAT 0x00001000
+#define VDL_LC_RESERVED 0x1D73CFFF
+#define VDL_LC_BYPASSTYPE_MSB 0x00000000
+#define VDL_LC_BYPASSTYPE_LSB 0x02000000
+#define VDL_LC_FBFORMAT_16 0x00000000
+#define VDL_LC_FBFORMAT_32 0x00800000
//-------------------------------------------------
// VDL DMA CONTROL WORD
//-------------------------------------------------
-#define VDL_NOP 0xe1000000
+#define VDL_NOP 0xe1000000
@@ -192,9 +192,9 @@ static void write_m2_reg(uint32_t &reg, uint32_t data, reg_wmode mode)
{
switch (mode)
{
- case REG_WRITE: reg = data; break;
- case REG_SET: reg |= data; break;
- case REG_CLEAR: reg &= ~data; break;
+ case REG_WRITE: reg = data; break;
+ case REG_SET: reg |= data; break;
+ case REG_CLEAR: reg &= ~data; break;
default:
assert_always(false, "Bad register write mode");
}
@@ -278,7 +278,7 @@ void m2_bda_device::device_post_load()
//-------------------------------------------------
-// machine_config_fragment - declare sub-devices
+// machine_config_fragment - declare sub-devices
//-------------------------------------------------
void m2_bda_device::device_add_mconfig(machine_config &config)
@@ -294,7 +294,7 @@ void m2_bda_device::device_add_mconfig(machine_config &config)
M2_CTRLPORT(config, m_ctrlport, DERIVED_CLOCK(1, 1));
M2_MPEG(config, m_mpeg, DERIVED_CLOCK(1, 1));
-// m_mpeg->int_handler().set(m_powerbus, FUNC(m2_powerbus_device::int_line<BDAINT_MPEG_LINE>));
+// m_mpeg->int_handler().set(m_powerbus, FUNC(m2_powerbus_device::int_line<BDAINT_MPEG_LINE>));
DSPP(config, m_dspp, DERIVED_CLOCK(1, 1));
m_dspp->int_handler().set(m_powerbus, FUNC(m2_powerbus_device::int_line<BDAINT_DSP_LINE>));
@@ -469,15 +469,15 @@ void m2_bda_device::configure_ppc_address_map(address_space &space)
space.install_ram(TE_TRAM_BASE, TE_TRAM_BASE + TE_TRAM_MASK, m_te->tram_ptr());
// Install BDA sub-devices
- space.install_readwrite_handler(POWERBUS_BASE, POWERBUS_BASE + DEVICE_MASK,read32_delegate(FUNC(m2_powerbus_device::read), &(*m_powerbus)), write32_delegate(FUNC(m2_powerbus_device::write), &(*m_powerbus)), 0xffffffffffffffffULL);
- space.install_readwrite_handler(MEMCTL_BASE, MEMCTL_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_memctl_device::read), &(*m_memctl)), write32_delegate(FUNC(m2_memctl_device::write), &(*m_memctl)), 0xffffffffffffffffULL);
- space.install_readwrite_handler(VDU_BASE, VDU_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_vdu_device::read), &(*m_vdu)), write32_delegate(FUNC(m2_vdu_device::write), &(*m_vdu)), 0xffffffffffffffffULL);
- space.install_readwrite_handler(TE_BASE, TE_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_te_device::read), &(*m_te)), write32_delegate(FUNC(m2_te_device::write), &(*m_te)), 0xffffffffffffffffULL);
- space.install_readwrite_handler(DSP_BASE, DSP_BASE + DEVICE_MASK, read32_delegate(FUNC(dspp_device::read), &(*m_dspp)), write32_delegate(FUNC(dspp_device::write), &(*m_dspp)), 0xffffffffffffffffULL);
- space.install_readwrite_handler(CTRLPORT_BASE, CTRLPORT_BASE + DEVICE_MASK,read32_delegate(FUNC(m2_ctrlport_device::read), &(*m_ctrlport)), write32_delegate(FUNC(m2_ctrlport_device::write), &(*m_ctrlport)), 0xffffffffffffffffULL);
- space.install_readwrite_handler(MPEG_BASE, MPEG_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_mpeg_device::read), &(*m_mpeg)), write32_delegate(FUNC(m2_mpeg_device::write), &(*m_mpeg)), 0xffffffffffffffffULL);
+ space.install_readwrite_handler(POWERBUS_BASE, POWERBUS_BASE + DEVICE_MASK,read32_delegate(FUNC(m2_powerbus_device::read), &(*m_powerbus)), write32_delegate(FUNC(m2_powerbus_device::write), &(*m_powerbus)), 0xffffffffffffffffULL);
+ space.install_readwrite_handler(MEMCTL_BASE, MEMCTL_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_memctl_device::read), &(*m_memctl)), write32_delegate(FUNC(m2_memctl_device::write), &(*m_memctl)), 0xffffffffffffffffULL);
+ space.install_readwrite_handler(VDU_BASE, VDU_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_vdu_device::read), &(*m_vdu)), write32_delegate(FUNC(m2_vdu_device::write), &(*m_vdu)), 0xffffffffffffffffULL);
+ space.install_readwrite_handler(TE_BASE, TE_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_te_device::read), &(*m_te)), write32_delegate(FUNC(m2_te_device::write), &(*m_te)), 0xffffffffffffffffULL);
+ space.install_readwrite_handler(DSP_BASE, DSP_BASE + DEVICE_MASK, read32_delegate(FUNC(dspp_device::read), &(*m_dspp)), write32_delegate(FUNC(dspp_device::write), &(*m_dspp)), 0xffffffffffffffffULL);
+ space.install_readwrite_handler(CTRLPORT_BASE, CTRLPORT_BASE + DEVICE_MASK,read32_delegate(FUNC(m2_ctrlport_device::read), &(*m_ctrlport)), write32_delegate(FUNC(m2_ctrlport_device::write), &(*m_ctrlport)), 0xffffffffffffffffULL);
+ space.install_readwrite_handler(MPEG_BASE, MPEG_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_mpeg_device::read), &(*m_mpeg)), write32_delegate(FUNC(m2_mpeg_device::write), &(*m_mpeg)), 0xffffffffffffffffULL);
- space.install_readwrite_handler(CPUID_BASE, CPUID_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_bda_device::cpu_id_r), this), write32_delegate(FUNC(m2_bda_device::cpu_id_w), this), 0xffffffffffffffffULL);
+ space.install_readwrite_handler(CPUID_BASE, CPUID_BASE + DEVICE_MASK, read32_delegate(FUNC(m2_bda_device::cpu_id_r), this), write32_delegate(FUNC(m2_bda_device::cpu_id_w), this), 0xffffffffffffffffULL);
// Find and install the CDE
@@ -954,7 +954,7 @@ WRITE32_MEMBER( m2_vdu_device::write )
uint32_t byte_offs = offset << 2;
reg_wmode wmode = byte_offs & 0x400 ? REG_CLEAR : REG_WRITE;
-// logerror("%s: VDU WRITE: %03x %08x %x\n", machine().describe_context(), byte_offs, data, mem_mask);
+// logerror("%s: VDU WRITE: %03x %08x %x\n", machine().describe_context(), byte_offs, data, mem_mask);
byte_offs &= ~0x400;
switch (byte_offs)
{
@@ -1132,8 +1132,8 @@ void m2_vdu_device::draw_scanline(uint32_t *dst, uint32_t srclower, uint32_t src
uint32_t hw = (m_avdi & VDU_AVDI_HWIDTH_MASK) >> VDU_AVDI_HWIDTH_SHIFT;
bool is32bpp = m_vdli & VDU_VDLI_FBFORMAT_32 ? true : false;
-// bool bypassmsb = m_vdli & VDU_VDLI_BYPASSTYPE_MSB ? true : false;
-// bool randomdith = m_vdli & VDU_VDLI_RANDOMDITHER ? true : false;
+// bool bypassmsb = m_vdli & VDU_VDLI_BYPASSTYPE_MSB ? true : false;
+// bool randomdith = m_vdli & VDU_VDLI_RANDOMDITHER ? true : false;
uint32_t h = 0;
@@ -1188,8 +1188,8 @@ void m2_vdu_device::draw_scanline_double(uint32_t *dst, uint32_t srclower, uint3
uint32_t hw = (m_avdi & VDU_AVDI_HWIDTH_MASK) >> VDU_AVDI_HWIDTH_SHIFT;
bool is32bpp = m_vdli & VDU_VDLI_FBFORMAT_32 ? true : false;
-// bool bypassmsb = m_vdli & VDU_VDLI_BYPASSTYPE_MSB ? true : false;
-// bool randomdith = m_vdli & VDU_VDLI_RANDOMDITHER ? true : false;
+// bool bypassmsb = m_vdli & VDU_VDLI_BYPASSTYPE_MSB ? true : false;
+// bool randomdith = m_vdli & VDU_VDLI_RANDOMDITHER ? true : false;
uint32_t h = 0;
@@ -1333,7 +1333,7 @@ uint32_t m2_vdu_device::screen_update(screen_device &screen, bitmap_rgb32 &bitma
{
bool hdouble = m_avdi & VDU_AVDI_HDOUBLE ? true : false;
bool vdouble = m_avdi & VDU_AVDI_VDOUBLE ? true : false;
-// bool onevintdis = m_vdli & VDU_VDLI_ONEVINTDIS ? true : false;
+// bool onevintdis = m_vdli & VDU_VDLI_ONEVINTDIS ? true : false;
uint32_t srclower = lower;
uint32_t srcupper = upper;
@@ -1760,7 +1760,7 @@ WRITE32_MEMBER( m2_cde_device::write )
{
case CDE_SDBG_CNTL:
{
- // ........ ........ xxxxxxxx xxxx.... Clock scaler (written with 33MHz/38400 = 868)
+ // ........ ........ xxxxxxxx xxxx.... Clock scaler (written with 33MHz/38400 = 868)
write_m2_reg(m_sdbg_cntl, data, wm_cw);
break;
}
@@ -1844,7 +1844,7 @@ WRITE32_MEMBER( m2_cde_device::write )
break;
}
-// case CDE_SYSTEM_CONF:
+// case CDE_SYSTEM_CONF:
case CDE_VISA_DIS:
{
write_m2_reg(m_visa_dis, data, wm_cw);
@@ -1941,7 +1941,7 @@ void m2_cde_device::start_dma(uint32_t ch)
// TODO: DMA timing is probably inaccurate
attotime delay = attotime::from_nsec(10);// * dma_ch.m_ccnt;
-// attotime delay = clocks_to_attotime(4 * dma_ch.m_ccnt);
+// attotime delay = clocks_to_attotime(4 * dma_ch.m_ccnt);
dma_ch.m_timer->adjust(delay);
if (dma_ch.m_cntl & CDE_DMA_DIRECTION)
diff --git a/src/mame/machine/3dom2.h b/src/mame/machine/3dom2.h
index c96d1f6a816..f0a95aac24d 100644
--- a/src/mame/machine/3dom2.h
+++ b/src/mame/machine/3dom2.h
@@ -2,9 +2,9 @@
// copyright-holders:Philip Bennett
/***************************************************************************
- 3DO M2
+ 3DO M2
- TODO: Move reg defines out of classes and into source
+ TODO: Move reg defines out of classes and into source
***************************************************************************/
@@ -18,7 +18,7 @@
#include "cpu/powerpc/ppc.h"
#include "screen.h"
-#define M2_BAD_TIMING 0 // HACK
+#define M2_BAD_TIMING 0 // HACK
/***************************************************************************
ENUMERATIONS
@@ -26,55 +26,55 @@
enum
{
- SYSCFG_VIDEO_NTSC = 0x00000000,
- SYSCFG_VIDEO_PAL = 0x00000001,
+ SYSCFG_VIDEO_NTSC = 0x00000000,
+ SYSCFG_VIDEO_PAL = 0x00000001,
- SYSCFG_VIDEO_ENCODER_MEIENC = 0x00000000, // NTSC by default
- SYSCFG_VIDEO_ENCODER_VP536 = 0x00000004, // NTSC by default
- SYSCFG_VIDEO_ENCODER_BT9103 = 0x00000008, // PAL by default
- SYSCFG_VIDEO_ENCODER_DENC = 0x0000000C, // PAL by default
+ SYSCFG_VIDEO_ENCODER_MEIENC = 0x00000000, // NTSC by default
+ SYSCFG_VIDEO_ENCODER_VP536 = 0x00000004, // NTSC by default
+ SYSCFG_VIDEO_ENCODER_BT9103 = 0x00000008, // PAL by default
+ SYSCFG_VIDEO_ENCODER_DENC = 0x0000000C, // PAL by default
- SYSCFG_REGION_UK = 0x00000800,
- SYSCFG_REGION_JAPAN = 0x00001000,
- SYSCFG_REGION_US = 0x00001800,
+ SYSCFG_REGION_UK = 0x00000800,
+ SYSCFG_REGION_JAPAN = 0x00001000,
+ SYSCFG_REGION_US = 0x00001800,
#if 0 // Console
- SYSCFG_AUDIO_CS4216 = 0xA0000000,
- SYSCFG_AUDIO_ASASHI = 0xE0000000,
+ SYSCFG_AUDIO_CS4216 = 0xA0000000,
+ SYSCFG_AUDIO_ASASHI = 0xE0000000,
#else
- SYSCFG_AUDIO_CS4216 = 0x20000000,
- SYSCFG_AUDIO_ASASHI = 0x60000000,
+ SYSCFG_AUDIO_CS4216 = 0x20000000,
+ SYSCFG_AUDIO_ASASHI = 0x60000000,
#endif
- SYSCFG_BOARD_AC_DEVCARD = 0x00040000,
- SYSCFG_BOARD_AC_COREBOARD = 0x00058000,
- SYSCFG_BOARD_DEVCARD = 0x00060000,
- SYSCFG_BOARD_UPGRADE = 0x00070000,
- SYSCFG_BOARD_MULTIPLAYER = 0x00078000,
+ SYSCFG_BOARD_AC_DEVCARD = 0x00040000,
+ SYSCFG_BOARD_AC_COREBOARD = 0x00058000,
+ SYSCFG_BOARD_DEVCARD = 0x00060000,
+ SYSCFG_BOARD_UPGRADE = 0x00070000,
+ SYSCFG_BOARD_MULTIPLAYER = 0x00078000,
SYSCONFIG_ARCADE = 0x03600000 | SYSCFG_BOARD_AC_COREBOARD | SYSCFG_AUDIO_ASASHI | SYSCFG_REGION_JAPAN | SYSCFG_VIDEO_ENCODER_MEIENC | SYSCFG_VIDEO_NTSC,
};
enum bdaint_line
{
- BDAINT_EXTD4_LINE = 3,
- BDAINT_EXTD3_LINE = 4,
- BDAINT_EXTD2_LINE = 5,
- BDAINT_EXTD1_LINE = 6,
- BDAINT_PVIOL_LINE = 7,
- BDAINT_WVIOL_LINE = 8,
- BDAINT_TO_LINE = 9,
-
- BDAINT_CEL_LINE = 21,
- BDAINT_MYSTERY_LINE = 22,
- BDAINT_VINT1_LINE = 23,
- BDAINT_VINT0_LINE = 24,
- BDAINT_DSP_LINE = 25,
- BDAINT_MPEG_LINE = 26,
- BDAINT_TRIGEN_LINE = 27,
- BDAINT_TRIDFINST_LINE = 28,
- BDAINT_TRIDMINST_LINE = 29,
- BDAINT_TRILISTEND_LINE = 30,
- BDAINT_TRIWINCLIP_LINE = 31,
+ BDAINT_EXTD4_LINE = 3,
+ BDAINT_EXTD3_LINE = 4,
+ BDAINT_EXTD2_LINE = 5,
+ BDAINT_EXTD1_LINE = 6,
+ BDAINT_PVIOL_LINE = 7,
+ BDAINT_WVIOL_LINE = 8,
+ BDAINT_TO_LINE = 9,
+
+ BDAINT_CEL_LINE = 21,
+ BDAINT_MYSTERY_LINE = 22,
+ BDAINT_VINT1_LINE = 23,
+ BDAINT_VINT0_LINE = 24,
+ BDAINT_DSP_LINE = 25,
+ BDAINT_MPEG_LINE = 26,
+ BDAINT_TRIGEN_LINE = 27,
+ BDAINT_TRIDFINST_LINE = 28,
+ BDAINT_TRIDMINST_LINE = 29,
+ BDAINT_TRILISTEND_LINE = 30,
+ BDAINT_TRIWINCLIP_LINE = 31,
};
enum reg_wmode
@@ -111,10 +111,10 @@ class m2_bda_device : public device_t
public:
enum rambank_size // TODO: REMOVE ME
{
- RAM_2MB = 2,
- RAM_4MB = 4,
- RAM_8MB = 8,
- RAM_16MB = 16
+ RAM_2MB = 2,
+ RAM_4MB = 4,
+ RAM_8MB = 8,
+ RAM_16MB = 16
};
template <typename T, typename U>
@@ -163,7 +163,7 @@ public:
void set_interrupt(uint32_t state);
-// screen_device * get_screen() const { return m_screen; }
+// screen_device * get_screen() const { return m_screen; }
protected:
// Device-level overrides
@@ -176,31 +176,31 @@ protected:
private:
enum base_addr
{
- POWERBUS_BASE = 0x00010000,
- MEMCTL_BASE = 0x00020000,
- VDU_BASE = 0x00030000,
- TE_BASE = 0x00040000,
- DSP_BASE = 0x00060000,
- CTRLPORT_BASE = 0x00070000,
- MPEG_BASE = 0x00080000,
- TE_TRAM_BASE = 0x000c0000,
- SLOT1_BASE = 0x01000000,
- SLOT2_BASE = 0x02000000,
- SLOT3_BASE = 0x03000000,
- SLOT4_BASE = 0x04000000,
- SLOT5_BASE = 0x05000000,
- SLOT6_BASE = 0x06000000,
- SLOT7_BASE = 0x07000000,
- SLOT8_BASE = 0x08000000,
- CPUID_BASE = 0x10000000,
- RAM_BASE = 0x40000000,
+ POWERBUS_BASE = 0x00010000,
+ MEMCTL_BASE = 0x00020000,
+ VDU_BASE = 0x00030000,
+ TE_BASE = 0x00040000,
+ DSP_BASE = 0x00060000,
+ CTRLPORT_BASE = 0x00070000,
+ MPEG_BASE = 0x00080000,
+ TE_TRAM_BASE = 0x000c0000,
+ SLOT1_BASE = 0x01000000,
+ SLOT2_BASE = 0x02000000,
+ SLOT3_BASE = 0x03000000,
+ SLOT4_BASE = 0x04000000,
+ SLOT5_BASE = 0x05000000,
+ SLOT6_BASE = 0x06000000,
+ SLOT7_BASE = 0x07000000,
+ SLOT8_BASE = 0x08000000,
+ CPUID_BASE = 0x10000000,
+ RAM_BASE = 0x40000000,
};
enum dev_mask
{
- DEVICE_MASK = 0x0000ffff,
- SLOT_MASK = 0x00ffffff,
- TE_TRAM_MASK = 0x00003fff,
+ DEVICE_MASK = 0x0000ffff,
+ SLOT_MASK = 0x00ffffff,
+ TE_TRAM_MASK = 0x00003fff,
};
@@ -209,24 +209,24 @@ private:
public: // TODO: THIS SHOULD NOT BE PUBLIC
required_device<ppc_device> m_cpu1;
required_device<ppc_device> m_cpu2;
- devcb_read_line m_videores_in;
+ devcb_read_line m_videores_in;
// Sub-devices
- required_device<m2_memctl_device> m_memctl;
- required_device<m2_powerbus_device> m_powerbus;
- required_device<m2_vdu_device> m_vdu;
- required_device<m2_ctrlport_device> m_ctrlport;
- required_device<dspp_device> m_dspp;
- required_device<m2_mpeg_device> m_mpeg;
- required_device<m2_te_device> m_te;
+ required_device<m2_memctl_device> m_memctl;
+ required_device<m2_powerbus_device> m_powerbus;
+ required_device<m2_vdu_device> m_vdu;
+ required_device<m2_ctrlport_device> m_ctrlport;
+ required_device<dspp_device> m_dspp;
+ required_device<m2_mpeg_device> m_mpeg;
+ required_device<m2_te_device> m_te;
// System RAM
- uint32_t *m_ram;
- uint32_t m_rambank_size[2];
- uint32_t m_ram_mask;
+ uint32_t *m_ram;
+ uint32_t m_rambank_size[2];
+ uint32_t m_ram_mask;
- devcb_write16 m_dac_l;
- devcb_write16 m_dac_r;
+ devcb_write16 m_dac_l;
+ devcb_write16 m_dac_r;
emu_timer *m_dac_timer;
@@ -269,24 +269,24 @@ protected:
private:
enum reg_offs
{
- BDAPCTL_DEVID = 0x00,
- BDAPCTL_PBCONTROL = 0x10,
- BDAPCTL_PBINTENSET = 0x40,
- BDAPCTL_PBINTSTAT = 0x50,
- BDAPCTL_ERRSTAT = 0x60,
- BDAPCTL_ERRADDR = 0x70,
+ BDAPCTL_DEVID = 0x00,
+ BDAPCTL_PBCONTROL = 0x10,
+ BDAPCTL_PBINTENSET = 0x40,
+ BDAPCTL_PBINTSTAT = 0x50,
+ BDAPCTL_ERRSTAT = 0x60,
+ BDAPCTL_ERRADDR = 0x70,
};
void update_interrupts();
- devcb_write_line m_int_handler;
+ devcb_write_line m_int_handler;
// Registers
- uint32_t m_ctrl;
- uint32_t m_int_enable;
- uint32_t m_int_status;
- uint32_t m_err_status;
- uint32_t m_err_address;
+ uint32_t m_ctrl;
+ uint32_t m_int_enable;
+ uint32_t m_int_status;
+ uint32_t m_err_status;
+ uint32_t m_err_address;
};
@@ -313,46 +313,46 @@ protected:
private:
enum reg_offs
{
- MCTL_MCONFIG = 0x0,
- MCTL_MREF = 0x4,
- MCTL_MCNTL = 0x8,
- MCTL_MRESET = 0xc,
+ MCTL_MCONFIG = 0x0,
+ MCTL_MREF = 0x4,
+ MCTL_MCNTL = 0x8,
+ MCTL_MRESET = 0xc,
};
enum mcfg_reg
{
- MCFG_LDIA_MASK = 0x07000000,
- MCFG_LDIA_SHIFT = 24,
- MCFG_LDOA_MASK = 0x00c00000,
- MCFG_LDOA_SHIFT = 22,
- MCFG_RC_MASK = 0x003c0000,
- MCFG_RC_SHIFT = 18,
- MCFG_RCD_MASK = 0x00030000,
- MCFG_RCD_SHIFT = 16,
- MCFG_SS1_MASK = 0x0000e000,
- MCFG_SS1_SHIFT = 13,
- MCFG_SS0_MASK = 0x00001c00,
- MCFG_SS0_SHIFT = 10,
- MCFG_CL_MASK = 0x00000030,
- MCFG_CL_SHIFT = 4,
+ MCFG_LDIA_MASK = 0x07000000,
+ MCFG_LDIA_SHIFT = 24,
+ MCFG_LDOA_MASK = 0x00c00000,
+ MCFG_LDOA_SHIFT = 22,
+ MCFG_RC_MASK = 0x003c0000,
+ MCFG_RC_SHIFT = 18,
+ MCFG_RCD_MASK = 0x00030000,
+ MCFG_RCD_SHIFT = 16,
+ MCFG_SS1_MASK = 0x0000e000,
+ MCFG_SS1_SHIFT = 13,
+ MCFG_SS0_MASK = 0x00001c00,
+ MCFG_SS0_SHIFT = 10,
+ MCFG_CL_MASK = 0x00000030,
+ MCFG_CL_SHIFT = 4,
};
enum mref_reg
{
- MREF_DEBUGADDR = 0x7F000000, /* Selector if GPIOx_GP == 0 */
- MREF_GPIO3_GP = 0x00800000, /* General purpose or debug out */
- MREF_GPIO3_OUT = 0x00400000, /* Output or input */
- MREF_GPIO3_VALUE = 0x00200000, /* Value if GPIOx_GP == 1 */
- MREF_GPIO2_GP = 0x00100000, /* General purpose or debug out */
- MREF_GPIO2_OUT = 0x00080000, /* Output or input */
- MREF_GPIO2_VALUE = 0x00040000, /* Value if GPIOx_GP == 1 */
- MREF_GPIO1_GP = 0x00020000, /* General purpose or debug out */
- MREF_GPIO1_OUT = 0x00010000, /* Output or input */
- MREF_GPIO1_VALUE = 0x00008000, /* Value if GPIOx_GP == 1 */
- MREF_GPIO0_GP = 0x00004000, /* General purpose or debug out */
- MREF_GPIO0_OUT = 0x00002000, /* Output or input */
- MREF_GPIO0_VALUE = 0x00001000, /* Value if GPIOx_GP == 1 */
- MREF_REFRESH = 0x00000FFF, /* Memory refresh count */
+ MREF_DEBUGADDR = 0x7F000000, /* Selector if GPIOx_GP == 0 */
+ MREF_GPIO3_GP = 0x00800000, /* General purpose or debug out */
+ MREF_GPIO3_OUT = 0x00400000, /* Output or input */
+ MREF_GPIO3_VALUE = 0x00200000, /* Value if GPIOx_GP == 1 */
+ MREF_GPIO2_GP = 0x00100000, /* General purpose or debug out */
+ MREF_GPIO2_OUT = 0x00080000, /* Output or input */
+ MREF_GPIO2_VALUE = 0x00040000, /* Value if GPIOx_GP == 1 */
+ MREF_GPIO1_GP = 0x00020000, /* General purpose or debug out */
+ MREF_GPIO1_OUT = 0x00010000, /* Output or input */
+ MREF_GPIO1_VALUE = 0x00008000, /* Value if GPIOx_GP == 1 */
+ MREF_GPIO0_GP = 0x00004000, /* General purpose or debug out */
+ MREF_GPIO0_OUT = 0x00002000, /* Output or input */
+ MREF_GPIO0_VALUE = 0x00001000, /* Value if GPIOx_GP == 1 */
+ MREF_REFRESH = 0x00000FFF, /* Memory refresh count */
};
@@ -361,25 +361,25 @@ private:
// 0:0MB 1:2MB 2:4MB 3:4MB 4:4MB 5:8MB 6:16MB 7:0MB
switch (size)
{
- case 0: return 0;
- case 2: return 1;
- case 4: return 2;
- case 8: return 5;
- case 16: return 6;
+ case 0: return 0;
+ case 2: return 1;
+ case 4: return 2;
+ case 8: return 5;
+ case 16: return 6;
}
return 0;
}
// GPIO
- devcb_read_line m_gpio_in[4];
+ devcb_read_line m_gpio_in[4];
devcb_write_line m_gpio_out[4];
// Registers
- uint32_t m_mcfg;
- uint32_t m_mref;
- uint32_t m_mcntl;
- uint32_t m_reset;
+ uint32_t m_mcfg;
+ uint32_t m_mref;
+ uint32_t m_mcntl;
+ uint32_t m_reset;
};
@@ -425,29 +425,29 @@ private:
// Internal stuff
required_device<screen_device> m_screen;
- emu_timer *m_vint0_timer;
- emu_timer *m_vint1_timer;
- devcb_write_line m_vint0_int_handler;
- devcb_write_line m_vint1_int_handler;
+ emu_timer *m_vint0_timer;
+ emu_timer *m_vint1_timer;
+ devcb_write_line m_vint0_int_handler;
+ devcb_write_line m_vint1_int_handler;
// Registers
- uint32_t m_vint;
- uint32_t m_vdc0;
- uint32_t m_vdc1;
- uint32_t m_fv0a;
- uint32_t m_fv1a;
- uint32_t m_avdi;
- uint32_t m_vdli;
- uint32_t m_vcfg;
- uint32_t m_dmt0;
- uint32_t m_dmt1;
- uint32_t m_vrst;
+ uint32_t m_vint;
+ uint32_t m_vdc0;
+ uint32_t m_vdc1;
+ uint32_t m_fv0a;
+ uint32_t m_fv1a;
+ uint32_t m_avdi;
+ uint32_t m_vdli;
+ uint32_t m_vcfg;
+ uint32_t m_dmt0;
+ uint32_t m_dmt1;
+ uint32_t m_vrst;
// Screen parameters
- uint32_t m_hstart;
- uint32_t m_htotal;
- uint32_t m_vstart;
- uint32_t m_vtotal;
+ uint32_t m_hstart;
+ uint32_t m_htotal;
+ uint32_t m_vstart;
+ uint32_t m_vtotal;
};
@@ -512,28 +512,28 @@ private:
enum misc
{
- PIP_RAM_WORDS = 256,
- TEXTURE_RAM_WORDS = 4096,
- PIP_RAM_BYTEMASK = PIP_RAM_WORDS * 4 - 1,
- TEXTURE_RAM_BYTEMASK = TEXTURE_RAM_WORDS * 4 - 1,
+ PIP_RAM_WORDS = 256,
+ TEXTURE_RAM_WORDS = 4096,
+ PIP_RAM_BYTEMASK = PIP_RAM_WORDS * 4 - 1,
+ TEXTURE_RAM_BYTEMASK = TEXTURE_RAM_WORDS * 4 - 1,
};
enum inst_type
{
- INST_WRITE_REG = 0x10000000,
- INST_VTX_SHORT = 0x20000000,
- INST_VTX_LONG = 0x30000000,
- INST_VTX_POINT = 0x40000000,
- INST_MASK = 0xf0000000,
+ INST_WRITE_REG = 0x10000000,
+ INST_VTX_SHORT = 0x20000000,
+ INST_VTX_LONG = 0x30000000,
+ INST_VTX_POINT = 0x40000000,
+ INST_MASK = 0xf0000000,
};
enum vtx_flag
{
- VTX_FLAG_SHAD = 0x00010000,
- VTX_FLAG_TEXT = 0x00020000,
- VTX_FLAG_PRSP = 0x00040000,
- VTX_FLAG_NEW = 0x00080000,
- VTX_FLAG_RM = 0x00100000,
+ VTX_FLAG_SHAD = 0x00010000,
+ VTX_FLAG_TEXT = 0x00020000,
+ VTX_FLAG_PRSP = 0x00040000,
+ VTX_FLAG_NEW = 0x00080000,
+ VTX_FLAG_RM = 0x00100000,
};
struct se_vtx
@@ -639,14 +639,14 @@ private:
uint32_t readbits_from_ram(uint32_t & src_addr, uint32_t & bit_offs, uint32_t bits);
void load_texture();
- m2_bda_device *m_bda;
+ m2_bda_device *m_bda;
const address_space_config m_space_config; // TODO: Why is this still here?
- devcb_write_line m_general_int_handler;
- devcb_write_line m_dfinstr_int_handler;
- devcb_write_line m_iminstr_int_handler;
- devcb_write_line m_listend_int_handler;
- devcb_write_line m_winclip_int_handler;
+ devcb_write_line m_general_int_handler;
+ devcb_write_line m_dfinstr_int_handler;
+ devcb_write_line m_iminstr_int_handler;
+ devcb_write_line m_listend_int_handler;
+ devcb_write_line m_winclip_int_handler;
// Registers
union
@@ -672,9 +672,9 @@ private:
{
struct
{
- se_vtx vertices[3];
- uint32_t reserved[16];
- uint32_t vertex_state;
+ se_vtx vertices[3];
+ uint32_t reserved[16];
+ uint32_t vertex_state;
};
uint32_t m_regs[65];
} m_se;
@@ -841,26 +841,26 @@ private:
// Destination blender state
struct
{
- uint32_t x;
- uint32_t y;
- uint32_t w;
+ uint32_t x;
+ uint32_t y;
+ uint32_t w;
- rgba ti;
- uint8_t ssb;
+ rgba ti;
+ uint8_t ssb;
- rgba src;
- uint8_t dsb;
+ rgba src;
+ uint8_t dsb;
- rgba srcpath;
- rgba texpath;
- rgba blend;
- rgba dst;
+ rgba srcpath;
+ rgba texpath;
+ rgba blend;
+ rgba dst;
} m_dbstate;
- te_state m_state;
+ te_state m_state;
- uint32_t *m_pipram;
- uint32_t *m_tram;
+ uint32_t *m_pipram;
+ uint32_t *m_tram;
};
@@ -937,141 +937,141 @@ private:
enum reg_offs
{
// Miscellaneous
- CDE_DEVICE_ID = 0x000,
- CDE_VERSION = 0x004,
- CDE_SDBG_CNTL = 0x00C, // Serial debug control register
- CDE_SDBG_RD = 0x010, // Serial debug read data
- CDE_SDBG_WRT = 0x014, // Serial debug write data
- CDE_INT_STS = 0x018, // offset for status reg
- CDE_INT_ENABLE = 0x01C,
- CDE_RESET_CNTL = 0x020,
- CDE_ROM_DISABLE = 0x024,
- CDE_CD_CMD_WRT = 0x028,
- CDE_CD_STS_RD = 0x02C,
- CDE_GPIO1 = 0x030, // GPIO1 control register (UART interrupt)
- CDE_GPIO2 = 0x034, // GPIO1 control register
+ CDE_DEVICE_ID = 0x000,
+ CDE_VERSION = 0x004,
+ CDE_SDBG_CNTL = 0x00C, // Serial debug control register
+ CDE_SDBG_RD = 0x010, // Serial debug read data
+ CDE_SDBG_WRT = 0x014, // Serial debug write data
+ CDE_INT_STS = 0x018, // offset for status reg
+ CDE_INT_ENABLE = 0x01C,
+ CDE_RESET_CNTL = 0x020,
+ CDE_ROM_DISABLE = 0x024,
+ CDE_CD_CMD_WRT = 0x028,
+ CDE_CD_STS_RD = 0x02C,
+ CDE_GPIO1 = 0x030, // GPIO1 control register (UART interrupt)
+ CDE_GPIO2 = 0x034, // GPIO1 control register
// BIO Bus
- CDE_DEV_DETECT = 0x200,
- CDE_BBLOCK = 0x204,
- CDE_BBLOCK_EN = 0x208, // Blocking enable register
- CDE_DEV5_CONF = 0x20C,
- CDE_DEV_STATE = 0x210,
- CDE_DEV6_CONF = 0x214,
- CDE_DEV5_VISA_CONF = 0x218,
- CDE_DEV6_VISA_CONF = 0x21C,
- CDE_UNIQ_ID_CMD = 0x220,
- CDE_UNIQ_ID_RD = 0x224,
- CDE_DEV_ERROR = 0x228,
- CDE_DEV7_CONF = 0x22C,
- CDE_DEV7_VISA_CONF = 0x230,
- CDE_DEV0_SETUP = 0x240,
- CDE_DEV0_CYCLE_TIME = 0x244,
- CDE_DEV1_SETUP = 0x248,
- CDE_DEV1_CYCLE_TIME = 0x24C,
- CDE_DEV2_SETUP = 0x250,
- CDE_DEV2_CYCLE_TIME = 0x254,
- CDE_DEV3_SETUP = 0x258,
- CDE_DEV3_CYCLE_TIME = 0x25C,
- CDE_DEV4_SETUP = 0x260,
- CDE_DEV4_CYCLE_TIME = 0x264,
- CDE_DEV5_SETUP = 0x268,
- CDE_DEV5_CYCLE_TIME = 0x26C,
- CDE_DEV6_SETUP = 0x270,
- CDE_DEV6_CYCLE_TIME = 0x274,
- CDE_DEV7_SETUP = 0x278,
- CDE_DEV7_CYCLE_TIME = 0x27C,
- CDE_SYSTEM_CONF = 0x280,
- CDE_VISA_DIS = 0x284,
- CDE_MICRO_RWS = 0x290,
- CDE_MICRO_WI = 0x294,
- CDE_MICRO_WOB = 0x298,
- CDE_MICRO_WO = 0x29C,
- CDE_MICRO_STATUS = 0x2A0,
+ CDE_DEV_DETECT = 0x200,
+ CDE_BBLOCK = 0x204,
+ CDE_BBLOCK_EN = 0x208, // Blocking enable register
+ CDE_DEV5_CONF = 0x20C,
+ CDE_DEV_STATE = 0x210,
+ CDE_DEV6_CONF = 0x214,
+ CDE_DEV5_VISA_CONF = 0x218,
+ CDE_DEV6_VISA_CONF = 0x21C,
+ CDE_UNIQ_ID_CMD = 0x220,
+ CDE_UNIQ_ID_RD = 0x224,
+ CDE_DEV_ERROR = 0x228,
+ CDE_DEV7_CONF = 0x22C,
+ CDE_DEV7_VISA_CONF = 0x230,
+ CDE_DEV0_SETUP = 0x240,
+ CDE_DEV0_CYCLE_TIME = 0x244,
+ CDE_DEV1_SETUP = 0x248,
+ CDE_DEV1_CYCLE_TIME = 0x24C,
+ CDE_DEV2_SETUP = 0x250,
+ CDE_DEV2_CYCLE_TIME = 0x254,
+ CDE_DEV3_SETUP = 0x258,
+ CDE_DEV3_CYCLE_TIME = 0x25C,
+ CDE_DEV4_SETUP = 0x260,
+ CDE_DEV4_CYCLE_TIME = 0x264,
+ CDE_DEV5_SETUP = 0x268,
+ CDE_DEV5_CYCLE_TIME = 0x26C,
+ CDE_DEV6_SETUP = 0x270,
+ CDE_DEV6_CYCLE_TIME = 0x274,
+ CDE_DEV7_SETUP = 0x278,
+ CDE_DEV7_CYCLE_TIME = 0x27C,
+ CDE_SYSTEM_CONF = 0x280,
+ CDE_VISA_DIS = 0x284,
+ CDE_MICRO_RWS = 0x290,
+ CDE_MICRO_WI = 0x294,
+ CDE_MICRO_WOB = 0x298,
+ CDE_MICRO_WO = 0x29C,
+ CDE_MICRO_STATUS = 0x2A0,
// CD DMA
- CDE_CD_DMA1_CNTL = 0x300,
- CDE_CD_DMA1_CPAD = 0x308,
- CDE_CD_DMA1_CCNT = 0x30C,
- CDE_CD_DMA1_NPAD = 0x318,
- CDE_CD_DMA1_NCNT = 0x31C,
- CDE_CD_DMA2_CNTL = 0x320,
- CDE_CD_DMA2_CPAD = 0x328,
- CDE_CD_DMA2_CCNT = 0x32C,
- CDE_CD_DMA2_NPAD = 0x338,
- CDE_CD_DMA2_NCNT = 0x33C,
+ CDE_CD_DMA1_CNTL = 0x300,
+ CDE_CD_DMA1_CPAD = 0x308,
+ CDE_CD_DMA1_CCNT = 0x30C,
+ CDE_CD_DMA1_NPAD = 0x318,
+ CDE_CD_DMA1_NCNT = 0x31C,
+ CDE_CD_DMA2_CNTL = 0x320,
+ CDE_CD_DMA2_CPAD = 0x328,
+ CDE_CD_DMA2_CCNT = 0x32C,
+ CDE_CD_DMA2_NPAD = 0x338,
+ CDE_CD_DMA2_NCNT = 0x33C,
// BioBus DMA
- CDE_DMA1_CNTL = 0x1000,
- CDE_DMA1_CBAD = 0x1004,
- CDE_DMA1_CPAD = 0x1008,
- CDE_DMA1_CCNT = 0x100C,
- CDE_DMA1_NBAD = 0x1014,
- CDE_DMA1_NPAD = 0x1018,
- CDE_DMA1_NCNT = 0x101C,
- CDE_DMA2_CNTL = 0x1020,
- CDE_DMA2_CBAD = 0x1024,
- CDE_DMA2_CPAD = 0x1028,
- CDE_DMA2_CCNT = 0x102C,
- CDE_DMA2_NBAD = 0x1034,
- CDE_DMA2_NPAD = 0x1038,
- CDE_DMA2_NCNT = 0x103C,
+ CDE_DMA1_CNTL = 0x1000,
+ CDE_DMA1_CBAD = 0x1004,
+ CDE_DMA1_CPAD = 0x1008,
+ CDE_DMA1_CCNT = 0x100C,
+ CDE_DMA1_NBAD = 0x1014,
+ CDE_DMA1_NPAD = 0x1018,
+ CDE_DMA1_NCNT = 0x101C,
+ CDE_DMA2_CNTL = 0x1020,
+ CDE_DMA2_CBAD = 0x1024,
+ CDE_DMA2_CPAD = 0x1028,
+ CDE_DMA2_CCNT = 0x102C,
+ CDE_DMA2_NBAD = 0x1034,
+ CDE_DMA2_NPAD = 0x1038,
+ CDE_DMA2_NCNT = 0x103C,
};
enum cde_int
{
- CDE_INT_SENT = 0x80000000,
- CDE_SDBG_WRT_DONE = 0x10000000,
- CDE_SDBG_RD_DONE = 0x08000000,
- CDE_DIPIR = 0x04000000,
- CDE_ARM_BOUNDS = 0x01000000,
- CDE_DMA2_BLOCKED = 0x00400000,
- CDE_DMA1_BLOCKED = 0x00200000,
- CDE_ID_READY = 0x00100000,
- CDE_ARM_FENCE = 0x00080000,
- CDE_EXT_INT = 0x00040000, // PJB: Used for SIO?
- CDE_3DO_CARD_INT = 0x00020000,
- CDE_ARM_INT = 0x00010000,
- CDE_CD_DMA2_OF = 0x00004000,
- CDE_CD_DMA1_OF = 0x00002000,
- CDE_ARM_ABORT = 0x00001000,
- CDE_CD_DMA2_DONE = 0x00000800,
- CDE_CD_DMA1_DONE = 0x00000400,
- CDE_DMA2_DONE = 0x00000100,
- CDE_DMA1_DONE = 0x00000080,
- CDE_PBUS_ERROR = 0x00000040,
- CDE_CD_CMD_WRT_DONE = 0x00000020,
- CDE_CD_STS_RD_DONE = 0x00000010,
- CDE_CD_STS_FL_DONE = 0x00000008,
- CDE_GPIO1_INT = 0x00000004,
- CDE_GPIO2_INT = 0x00000002,
- CDE_BBUS_ERROR = 0x00000001,
+ CDE_INT_SENT = 0x80000000,
+ CDE_SDBG_WRT_DONE = 0x10000000,
+ CDE_SDBG_RD_DONE = 0x08000000,
+ CDE_DIPIR = 0x04000000,
+ CDE_ARM_BOUNDS = 0x01000000,
+ CDE_DMA2_BLOCKED = 0x00400000,
+ CDE_DMA1_BLOCKED = 0x00200000,
+ CDE_ID_READY = 0x00100000,
+ CDE_ARM_FENCE = 0x00080000,
+ CDE_EXT_INT = 0x00040000, // PJB: Used for SIO?
+ CDE_3DO_CARD_INT = 0x00020000,
+ CDE_ARM_INT = 0x00010000,
+ CDE_CD_DMA2_OF = 0x00004000,
+ CDE_CD_DMA1_OF = 0x00002000,
+ CDE_ARM_ABORT = 0x00001000,
+ CDE_CD_DMA2_DONE = 0x00000800,
+ CDE_CD_DMA1_DONE = 0x00000400,
+ CDE_DMA2_DONE = 0x00000100,
+ CDE_DMA1_DONE = 0x00000080,
+ CDE_PBUS_ERROR = 0x00000040,
+ CDE_CD_CMD_WRT_DONE = 0x00000020,
+ CDE_CD_STS_RD_DONE = 0x00000010,
+ CDE_CD_STS_FL_DONE = 0x00000008,
+ CDE_GPIO1_INT = 0x00000004,
+ CDE_GPIO2_INT = 0x00000002,
+ CDE_BBUS_ERROR = 0x00000001,
};
enum cde_dma_cntl
{
- CDE_DMA_DIRECTION = 0x00000400, /* PowerBus to BioBus if set */
- CDE_DMA_RESET = 0x00000200, /* Reset engine if set */
- CDE_DMA_GLOBAL = 0x00000100, /* snoopable trans if set */
- CDE_DMA_CURR_VALID = 0x00000080, /* current setup valid if set */
- CDE_DMA_NEXT_VALID = 0x00000040, /* next setup valid if set */
- CDE_DMA_GO_FOREVER = 0x00000020, /* copy next to current if set*/
- CDE_PB_CHANNEL_MASK = 0x0000001F, /* powerbus channel to use */
+ CDE_DMA_DIRECTION = 0x00000400, /* PowerBus to BioBus if set */
+ CDE_DMA_RESET = 0x00000200, /* Reset engine if set */
+ CDE_DMA_GLOBAL = 0x00000100, /* snoopable trans if set */
+ CDE_DMA_CURR_VALID = 0x00000080, /* current setup valid if set */
+ CDE_DMA_NEXT_VALID = 0x00000040, /* next setup valid if set */
+ CDE_DMA_GO_FOREVER = 0x00000020, /* copy next to current if set*/
+ CDE_PB_CHANNEL_MASK = 0x0000001F, /* powerbus channel to use */
};
enum cde_dev_setup
{
- CDE_WRITEN_HOLD = 0x00000003,
- CDE_WRITEN_SETUP = 0x0000001C,
- CDE_READ_HOLD = 0x00000060,
- CDE_READ_SETUP = 0x00000380,
- CDE_PAGEMODE = 0x00000400,
- CDE_DATAWIDTH = 0x00001800,
- CDE_DATAWIDTH_8 = 0x00000000,
- CDE_DATAWIDTH_16 = 0x00000800,
- CDE_READ_SETUP_IO = 0x0000E000,
- CDE_MODEA = 0x00010000,
- CDE_HIDEA = 0x00020000,
+ CDE_WRITEN_HOLD = 0x00000003,
+ CDE_WRITEN_SETUP = 0x0000001C,
+ CDE_READ_HOLD = 0x00000060,
+ CDE_READ_SETUP = 0x00000380,
+ CDE_PAGEMODE = 0x00000400,
+ CDE_DATAWIDTH = 0x00001800,
+ CDE_DATAWIDTH_8 = 0x00000000,
+ CDE_DATAWIDTH_16 = 0x00000800,
+ CDE_READ_SETUP_IO = 0x0000E000,
+ CDE_MODEA = 0x00010000,
+ CDE_HIDEA = 0x00020000,
};
void write_reg(uint32_t &reg, uint32_t data, bool clear);
@@ -1089,38 +1089,38 @@ private:
}
required_device<ppc_device> m_cpu1;
- m2_bda_device *m_bda; // todo
+ m2_bda_device *m_bda; // todo
- devcb_write_line m_int_handler;
- devcb_write32 m_sdbg_out_handler;
+ devcb_write_line m_int_handler;
+ devcb_write32 m_sdbg_out_handler;
// Registers
- uint32_t m_sdbg_in;
- uint32_t m_sdbg_out;
- uint32_t m_sdbg_cntl;
- uint32_t m_int_status;
- uint32_t m_int_enable;
- uint32_t m_bblock_en;
- uint32_t m_syscfg;
- uint32_t m_visa_dis;
+ uint32_t m_sdbg_in;
+ uint32_t m_sdbg_out;
+ uint32_t m_sdbg_cntl;
+ uint32_t m_int_status;
+ uint32_t m_int_enable;
+ uint32_t m_bblock_en;
+ uint32_t m_syscfg;
+ uint32_t m_visa_dis;
struct biobus_device
{
- uint32_t m_setup;
- uint32_t m_cycle_time;
+ uint32_t m_setup;
+ uint32_t m_cycle_time;
} m_bio_device[8];
struct dma_channel
{
- uint32_t m_cntl;
- uint32_t m_cbad;
- uint32_t m_cpad;
- uint32_t m_ccnt;
- uint32_t m_nbad;
- uint32_t m_npad;
- uint32_t m_ncnt;
- emu_timer *m_timer;
+ uint32_t m_cntl;
+ uint32_t m_cbad;
+ uint32_t m_cpad;
+ uint32_t m_ccnt;
+ uint32_t m_nbad;
+ uint32_t m_npad;
+ uint32_t m_ncnt;
+ emu_timer *m_timer;
} m_dma[2];
};
diff --git a/src/mame/machine/3dom2_defs.h b/src/mame/machine/3dom2_defs.h
index 95731c58136..4019e5087ce 100644
--- a/src/mame/machine/3dom2_defs.h
+++ b/src/mame/machine/3dom2_defs.h
@@ -2,7 +2,7 @@
// copyright-holders:Philip Bennett
/***************************************************************************
- 3DO M2
+ 3DO M2
***************************************************************************/
@@ -15,245 +15,245 @@
ENUMERATIONS
***************************************************************************/
-#define M2_SYSCFG_VIDEO_NTSC (0x00000000U)
-#define M2_SYSCFG_VIDEO_PAL (0x00000001U)
+#define M2_SYSCFG_VIDEO_NTSC (0x00000000U)
+#define M2_SYSCFG_VIDEO_PAL (0x00000001U)
-#define M2_SYSCFG_VIDEO_ENCODER_MEIENC (0x00000000U) // NTSC by default
-#define M2_SYSCFG_VIDEO_ENCODER_VP536 (0x00000004U) // NTSC by default
-#define M2_SYSCFG_VIDEO_ENCODER_BT9103 (0x00000008U) // PAL by default
-#define M2_SYSCFG_VIDEO_ENCODER_DENC (0x0000000CU) // PAL by default
+#define M2_SYSCFG_VIDEO_ENCODER_MEIENC (0x00000000U) // NTSC by default
+#define M2_SYSCFG_VIDEO_ENCODER_VP536 (0x00000004U) // NTSC by default
+#define M2_SYSCFG_VIDEO_ENCODER_BT9103 (0x00000008U) // PAL by default
+#define M2_SYSCFG_VIDEO_ENCODER_DENC (0x0000000CU) // PAL by default
-#define M2_SYSCFG_REGION_UK (0x00000800U)
-#define M2_SYSCFG_REGION_JAPAN (0x00001000U)
-#define M2_SYSCFG_REGION_US (0x00001800U)
+#define M2_SYSCFG_REGION_UK (0x00000800U)
+#define M2_SYSCFG_REGION_JAPAN (0x00001000U)
+#define M2_SYSCFG_REGION_US (0x00001800U)
#if 0 // Console
-#define M2_SYSCFG_AUDIO_CS4216 (0xA0000000U)
-#define M2_SYSCFG_AUDIO_ASASHI (0xE0000000U)
+#define M2_SYSCFG_AUDIO_CS4216 (0xA0000000U)
+#define M2_SYSCFG_AUDIO_ASASHI (0xE0000000U)
#else
-#define M2_SYSCFG_AUDIO_CS4216 (0x20000000U)
-#define M2_SYSCFG_AUDIO_ASASHI (0x60000000U)
+#define M2_SYSCFG_AUDIO_CS4216 (0x20000000U)
+#define M2_SYSCFG_AUDIO_ASASHI (0x60000000U)
#endif
-#define M2_SYSCFG_BOARD_AC_DEVCARD (0x00040000U)
-#define M2_SYSCFG_BOARD_AC_COREBOARD (0x00058000U)
-#define M2_SYSCFG_BOARD_DEVCARD (0x00060000U)
-#define M2_SYSCFG_BOARD_UPGRADE (0x00070000U)
-#define M2_SYSCFG_BOARD_MULTIPLAYER (0x00078000U)
+#define M2_SYSCFG_BOARD_AC_DEVCARD (0x00040000U)
+#define M2_SYSCFG_BOARD_AC_COREBOARD (0x00058000U)
+#define M2_SYSCFG_BOARD_DEVCARD (0x00060000U)
+#define M2_SYSCFG_BOARD_UPGRADE (0x00070000U)
+#define M2_SYSCFG_BOARD_MULTIPLAYER (0x00078000U)
#define M2_SYSCONFIG_ARCADE (0x03600000 | SYSCFG_BOARD_AC_COREBOARD | SYSCFG_AUDIO_ASASHI | SYSCFG_REGION_JAPAN | SYSCFG_VIDEO_ENCODER_MEIENC | SYSCFG_VIDEO_NTSCU)
-#define M2_MEMBASE_POWERBUS (0x00010000U)
-#define M2_MEMBASE_MEMCTL (0x00020000U)
-#define M2_MEMBASE_VDU (0x00030000U)
-#define M2_MEMBASE_TE (0x00040000U)
-#define M2_MEMBASE_DSP (0x00060000U)
-#define M2_MEMBASE_CTRLPORT (0x00070000U)
-#define M2_MEMBASE_MPEG (0x00080000U)
-#define M2_MEMBASE_TE_TRAM (0x000c0000U)
-#define M2_MEMBASE_SLOT1 (0x01000000U)
-#define M2_MEMBASE_SLOT2 (0x02000000U)
-#define M2_MEMBASE_SLOT3 (0x03000000U)
-#define M2_MEMBASE_SLOT4 (0x04000000U)
-#define M2_MEMBASE_SLOT5 (0x05000000U)
-#define M2_MEMBASE_SLOT6 (0x06000000U)
-#define M2_MEMBASE_SLOT7 (0x07000000U)
-#define M2_MEMBASE_SLOT8 (0x08000000U)
-#define M2_MEMBASE_CPUID (0x10000000U)
-#define M2_MEMBASE_RAM (0x40000000U)
+#define M2_MEMBASE_POWERBUS (0x00010000U)
+#define M2_MEMBASE_MEMCTL (0x00020000U)
+#define M2_MEMBASE_VDU (0x00030000U)
+#define M2_MEMBASE_TE (0x00040000U)
+#define M2_MEMBASE_DSP (0x00060000U)
+#define M2_MEMBASE_CTRLPORT (0x00070000U)
+#define M2_MEMBASE_MPEG (0x00080000U)
+#define M2_MEMBASE_TE_TRAM (0x000c0000U)
+#define M2_MEMBASE_SLOT1 (0x01000000U)
+#define M2_MEMBASE_SLOT2 (0x02000000U)
+#define M2_MEMBASE_SLOT3 (0x03000000U)
+#define M2_MEMBASE_SLOT4 (0x04000000U)
+#define M2_MEMBASE_SLOT5 (0x05000000U)
+#define M2_MEMBASE_SLOT6 (0x06000000U)
+#define M2_MEMBASE_SLOT7 (0x07000000U)
+#define M2_MEMBASE_SLOT8 (0x08000000U)
+#define M2_MEMBASE_CPUID (0x10000000U)
+#define M2_MEMBASE_RAM (0x40000000U)
enum dev_mask
{
- DEVICE_MASK (0x0000ffffU)
- SLOT_MASK (0x00ffffffU)
- TE_TRAM_MASK (0x00003fffU)
+ DEVICE_MASK (0x0000ffffU)
+ SLOT_MASK (0x00ffffffU)
+ TE_TRAM_MASK (0x00003fffU)
};
enum reg_offs
{
-#define M2_BDAPCTL_DEVID (0x00U)
-#define M2_BDAPCTL_PBCONTROL (0x10U)
-#define M2_BDAPCTL_PBINTENSET (0x40U)
-#define M2_BDAPCTL_PBINTSTAT (0x50U)
-#define M2_BDAPCTL_ERRSTAT (0x60U)
-#define M2_BDAPCTL_ERRADDR (0x70U)
+#define M2_BDAPCTL_DEVID (0x00U)
+#define M2_BDAPCTL_PBCONTROL (0x10U)
+#define M2_BDAPCTL_PBINTENSET (0x40U)
+#define M2_BDAPCTL_PBINTSTAT (0x50U)
+#define M2_BDAPCTL_ERRSTAT (0x60U)
+#define M2_BDAPCTL_ERRADDR (0x70U)
enum reg_offs
{
- MCTL_MCONFIG (0x0U)
- MCTL_MREF (0x4U)
- MCTL_MCNTL (0x8U)
- MCTL_MRESET (0xcU)
+ MCTL_MCONFIG (0x0U)
+ MCTL_MREF (0x4U)
+ MCTL_MCNTL (0x8U)
+ MCTL_MRESET (0xcU)
};
-#define M2_MCFG_LDIA_MASK (0x07000000U)
-#define M2_MCFG_LDIA_SHIFT (24U)
-#define M2_MCFG_LDOA_MASK (0x00c00000U)
-#define M2_MCFG_LDOA_SHIFT (22U)
-#define M2_MCFG_RC_MASK (0x003c0000U)
-#define M2_MCFG_RC_SHIFT (18U)
-#define M2_MCFG_RCD_MASK (0x00030000U)
-#define M2_MCFG_RCD_SHIFT (16U)
-#define M2_MCFG_SS1_MASK (0x0000e000U)
-#define M2_MCFG_SS1_SHIFT (13U)
-#define M2_MCFG_SS0_MASK (0x00001c00U)
-#define M2_MCFG_SS0_SHIFT (10U)
-#define M2_MCFG_CL_MASK (0x00000030U)
-#define M2_MCFG_CL_SHIFT (4U)
-
-#define M2_MREF_DEBUGADDR (0x7F000000U) /* Selector if GPIOx_GP =(0 */
-#define M2_MREF_GPIO3_GP (0x00800000U) /* General purpose or debug out */
-#define M2_MREF_GPIO3_OUT (0x00400000U) /* Output or input */
-#define M2_MREF_GPIO3_VALUE (0x00200000U) /* Value if GPIOx_GP =(1 */
-#define M2_MREF_GPIO2_GP (0x00100000U) /* General purpose or debug out */
-#define M2_MREF_GPIO2_OUT (0x00080000U) /* Output or input */
-#define M2_MREF_GPIO2_VALUE (0x00040000U) /* Value if GPIOx_GP =(1 */
-#define M2_MREF_GPIO1_GP (0x00020000U) /* General purpose or debug out */
-#define M2_MREF_GPIO1_OUT (0x00010000U) /* Output or input */
-#define M2_MREF_GPIO1_VALUE (0x00008000U) /* Value if GPIOx_GP =(1 */
-#define M2_MREF_GPIO0_GP (0x00004000U) /* General purpose or debug out */
-#define M2_MREF_GPIO0_OUT (0x00002000U) /* Output or input */
-#define M2_MREF_GPIO0_VALUE (0x00001000U) /* Value if GPIOx_GP =(1 */
-#define M2_MREF_REFRESH (0x00000FFFU) /* Memory refresh count */
+#define M2_MCFG_LDIA_MASK (0x07000000U)
+#define M2_MCFG_LDIA_SHIFT (24U)
+#define M2_MCFG_LDOA_MASK (0x00c00000U)
+#define M2_MCFG_LDOA_SHIFT (22U)
+#define M2_MCFG_RC_MASK (0x003c0000U)
+#define M2_MCFG_RC_SHIFT (18U)
+#define M2_MCFG_RCD_MASK (0x00030000U)
+#define M2_MCFG_RCD_SHIFT (16U)
+#define M2_MCFG_SS1_MASK (0x0000e000U)
+#define M2_MCFG_SS1_SHIFT (13U)
+#define M2_MCFG_SS0_MASK (0x00001c00U)
+#define M2_MCFG_SS0_SHIFT (10U)
+#define M2_MCFG_CL_MASK (0x00000030U)
+#define M2_MCFG_CL_SHIFT (4U)
+
+#define M2_MREF_DEBUGADDR (0x7F000000U) /* Selector if GPIOx_GP =(0 */
+#define M2_MREF_GPIO3_GP (0x00800000U) /* General purpose or debug out */
+#define M2_MREF_GPIO3_OUT (0x00400000U) /* Output or input */
+#define M2_MREF_GPIO3_VALUE (0x00200000U) /* Value if GPIOx_GP =(1 */
+#define M2_MREF_GPIO2_GP (0x00100000U) /* General purpose or debug out */
+#define M2_MREF_GPIO2_OUT (0x00080000U) /* Output or input */
+#define M2_MREF_GPIO2_VALUE (0x00040000U) /* Value if GPIOx_GP =(1 */
+#define M2_MREF_GPIO1_GP (0x00020000U) /* General purpose or debug out */
+#define M2_MREF_GPIO1_OUT (0x00010000U) /* Output or input */
+#define M2_MREF_GPIO1_VALUE (0x00008000U) /* Value if GPIOx_GP =(1 */
+#define M2_MREF_GPIO0_GP (0x00004000U) /* General purpose or debug out */
+#define M2_MREF_GPIO0_OUT (0x00002000U) /* Output or input */
+#define M2_MREF_GPIO0_VALUE (0x00001000U) /* Value if GPIOx_GP =(1 */
+#define M2_MREF_REFRESH (0x00000FFFU) /* Memory refresh count */
enum CDE_REGS
// Miscellaneous
- CDE_DEVICE_ID (0x000U)
- CDE_VERSION (0x004U)
- CDE_SDBG_CNTL (0x00C, // Serial debug control register
- CDE_SDBG_RD (0x010, // Serial debug read data
- CDE_SDBG_WRT (0x014, // Serial debug write data
- CDE_INT_STS (0x018, // offset for status reg
- CDE_INT_ENABLE (0x01CU)
- CDE_RESET_CNTL (0x020U)
- CDE_ROM_DISABLE (0x024U)
- CDE_CD_CMD_WRT (0x028U)
- CDE_CD_STS_RD (0x02CU)
- CDE_GPIO1 (0x030, // GPIO1 control register (UART interrupt)
- CDE_GPIO2 (0x034, // GPIO1 control register
+ CDE_DEVICE_ID (0x000U)
+ CDE_VERSION (0x004U)
+ CDE_SDBG_CNTL (0x00C, // Serial debug control register
+ CDE_SDBG_RD (0x010, // Serial debug read data
+ CDE_SDBG_WRT (0x014, // Serial debug write data
+ CDE_INT_STS (0x018, // offset for status reg
+ CDE_INT_ENABLE (0x01CU)
+ CDE_RESET_CNTL (0x020U)
+ CDE_ROM_DISABLE (0x024U)
+ CDE_CD_CMD_WRT (0x028U)
+ CDE_CD_STS_RD (0x02CU)
+ CDE_GPIO1 (0x030, // GPIO1 control register (UART interrupt)
+ CDE_GPIO2 (0x034, // GPIO1 control register
// BIO Bus
- CDE_DEV_DETECT (0x200U)
- CDE_BBLOCK (0x204U)
- CDE_BBLOCK_EN (0x208, // Blocking enable register
- CDE_DEV5_CONF (0x20CU)
- CDE_DEV_STATE (0x210U)
- CDE_DEV6_CONF (0x214U)
- CDE_DEV5_VISA_CONF (0x218U)
- CDE_DEV6_VISA_CONF (0x21CU)
- CDE_UNIQ_ID_CMD (0x220U)
- CDE_UNIQ_ID_RD (0x224U)
- CDE_DEV_ERROR (0x228U)
- CDE_DEV7_CONF (0x22CU)
- CDE_DEV7_VISA_CONF (0x230U)
- CDE_DEV0_SETUP (0x240U)
- CDE_DEV0_CYCLE_TIME (0x244U)
- CDE_DEV1_SETUP (0x248U)
- CDE_DEV1_CYCLE_TIME (0x24CU)
- CDE_DEV2_SETUP (0x250U)
- CDE_DEV2_CYCLE_TIME (0x254U)
- CDE_DEV3_SETUP (0x258U)
- CDE_DEV3_CYCLE_TIME (0x25CU)
- CDE_DEV4_SETUP (0x260U)
- CDE_DEV4_CYCLE_TIME (0x264U)
- CDE_DEV5_SETUP (0x268U)
- CDE_DEV5_CYCLE_TIME (0x26CU)
- CDE_DEV6_SETUP (0x270U)
- CDE_DEV6_CYCLE_TIME (0x274U)
- CDE_DEV7_SETUP (0x278U)
- CDE_DEV7_CYCLE_TIME (0x27CU)
- CDE_SYSTEM_CONF (0x280U)
- CDE_VISA_DIS (0x284U)
- M2_CDE_MICRO_RWS (0x290U)
- M2_CDE_MICRO_WI (0x294U)
- M2_CDE_MICRO_WOB (0x298U)
- M2_CDE_MICRO_WO (0x29CU)
- M2_CDE_MICRO_STATUS (0x2A0U)
+ CDE_DEV_DETECT (0x200U)
+ CDE_BBLOCK (0x204U)
+ CDE_BBLOCK_EN (0x208, // Blocking enable register
+ CDE_DEV5_CONF (0x20CU)
+ CDE_DEV_STATE (0x210U)
+ CDE_DEV6_CONF (0x214U)
+ CDE_DEV5_VISA_CONF (0x218U)
+ CDE_DEV6_VISA_CONF (0x21CU)
+ CDE_UNIQ_ID_CMD (0x220U)
+ CDE_UNIQ_ID_RD (0x224U)
+ CDE_DEV_ERROR (0x228U)
+ CDE_DEV7_CONF (0x22CU)
+ CDE_DEV7_VISA_CONF (0x230U)
+ CDE_DEV0_SETUP (0x240U)
+ CDE_DEV0_CYCLE_TIME (0x244U)
+ CDE_DEV1_SETUP (0x248U)
+ CDE_DEV1_CYCLE_TIME (0x24CU)
+ CDE_DEV2_SETUP (0x250U)
+ CDE_DEV2_CYCLE_TIME (0x254U)
+ CDE_DEV3_SETUP (0x258U)
+ CDE_DEV3_CYCLE_TIME (0x25CU)
+ CDE_DEV4_SETUP (0x260U)
+ CDE_DEV4_CYCLE_TIME (0x264U)
+ CDE_DEV5_SETUP (0x268U)
+ CDE_DEV5_CYCLE_TIME (0x26CU)
+ CDE_DEV6_SETUP (0x270U)
+ CDE_DEV6_CYCLE_TIME (0x274U)
+ CDE_DEV7_SETUP (0x278U)
+ CDE_DEV7_CYCLE_TIME (0x27CU)
+ CDE_SYSTEM_CONF (0x280U)
+ CDE_VISA_DIS (0x284U)
+ M2_CDE_MICRO_RWS (0x290U)
+ M2_CDE_MICRO_WI (0x294U)
+ M2_CDE_MICRO_WOB (0x298U)
+ M2_CDE_MICRO_WO (0x29CU)
+ M2_CDE_MICRO_STATUS (0x2A0U)
// CD DMA
- M2_CDE_CD_DMA1_CNTL (0x300U)
- M2_CDE_CD_DMA1_CPAD (0x308U)
- M2_CDE_CD_DMA1_CCNT (0x30CU)
- M2_CDE_CD_DMA1_NPAD (0x318U)
- M2_CDE_CD_DMA1_NCNT (0x31CU)
- M2_CDE_CD_DMA2_CNTL (0x320U)
- M2_CDE_CD_DMA2_CPAD (0x328U)
- M2_CDE_CD_DMA2_CCNT (0x32CU)
- M2_CDE_CD_DMA2_NPAD (0x338U)
- M2_CDE_CD_DMA2_NCNT (0x33CU)
+ M2_CDE_CD_DMA1_CNTL (0x300U)
+ M2_CDE_CD_DMA1_CPAD (0x308U)
+ M2_CDE_CD_DMA1_CCNT (0x30CU)
+ M2_CDE_CD_DMA1_NPAD (0x318U)
+ M2_CDE_CD_DMA1_NCNT (0x31CU)
+ M2_CDE_CD_DMA2_CNTL (0x320U)
+ M2_CDE_CD_DMA2_CPAD (0x328U)
+ M2_CDE_CD_DMA2_CCNT (0x32CU)
+ M2_CDE_CD_DMA2_NPAD (0x338U)
+ M2_CDE_CD_DMA2_NCNT (0x33CU)
// BioBus DMA
- M2_CDE_DMA1_CNTL (0x1000U)
- M2_CDE_DMA1_CBAD (0x1004U)
- M2_CDE_DMA1_CPAD (0x1008U)
- M2_CDE_DMA1_CCNT (0x100CU)
- M2_CDE_DMA1_NBAD (0x1014U)
- M2_CDE_DMA1_NPAD (0x1018U)
- M2_CDE_DMA1_NCNT (0x101CU)
- M2_CDE_DMA2_CNTL (0x1020U)
- M2_CDE_DMA2_CBAD (0x1024U)
- M2_CDE_DMA2_CPAD (0x1028U)
- M2_CDE_DMA2_CCNT (0x102CU)
- M2_CDE_DMA2_NBAD (0x1034U)
- M2_CDE_DMA2_NPAD (0x1038U)
- M2_CDE_DMA2_NCNT (0x103CU)
+ M2_CDE_DMA1_CNTL (0x1000U)
+ M2_CDE_DMA1_CBAD (0x1004U)
+ M2_CDE_DMA1_CPAD (0x1008U)
+ M2_CDE_DMA1_CCNT (0x100CU)
+ M2_CDE_DMA1_NBAD (0x1014U)
+ M2_CDE_DMA1_NPAD (0x1018U)
+ M2_CDE_DMA1_NCNT (0x101CU)
+ M2_CDE_DMA2_CNTL (0x1020U)
+ M2_CDE_DMA2_CBAD (0x1024U)
+ M2_CDE_DMA2_CPAD (0x1028U)
+ M2_CDE_DMA2_CCNT (0x102CU)
+ M2_CDE_DMA2_NBAD (0x1034U)
+ M2_CDE_DMA2_NPAD (0x1038U)
+ M2_CDE_DMA2_NCNT (0x103CU)
};
enum cde_int
{
- M2_CDE_INT_SENT (0x80000000U)
- M2_CDE_SDBG_WRT_DONE (0x10000000U)
- M2_CDE_SDBG_RD_DONE (0x08000000U)
- M2_CDE_DIPIR (0x04000000U)
- M2_CDE_ARM_BOUNDS (0x01000000U)
- M2_CDE_DMA2_BLOCKED (0x00400000U)
- M2_CDE_DMA1_BLOCKED (0x00200000U)
- M2_CDE_ID_READY (0x00100000U)
- M2_CDE_ARM_FENCE (0x00080000U)
- M2_CDE_EXT_INT (0x00040000, // Added by Phil
- M2_CDE_3DO_CARD_INT (0x00020000U)
- M2_CDE_ARM_INT (0x00010000U)
- M2_CDE_CD_DMA2_OF (0x00004000U)
- M2_CDE_CD_DMA1_OF (0x00002000U)
- M2_CDE_ARM_ABORT (0x00001000U)
- M2_CDE_CD_DMA2_DONE (0x00000800U)
- M2_CDE_CD_DMA1_DONE (0x00000400U)
- M2_CDE_DMA2_DONE (0x00000100U)
- M2_CDE_DMA1_DONE (0x00000080U)
- M2_CDE_PBUS_ERROR (0x00000040U)
- M2_CDE_CD_CMD_WRT_DONE (0x00000020U)
- M2_CDE_CD_STS_RD_DONE (0x00000010U)
- M2_CDE_CD_STS_FL_DONE (0x00000008U)
- M2_CDE_GPIO1_INT (0x00000004U)
- M2_CDE_GPIO2_INT (0x00000002U)
- M2_CDE_BBUS_ERROR (0x00000001U)
+ M2_CDE_INT_SENT (0x80000000U)
+ M2_CDE_SDBG_WRT_DONE (0x10000000U)
+ M2_CDE_SDBG_RD_DONE (0x08000000U)
+ M2_CDE_DIPIR (0x04000000U)
+ M2_CDE_ARM_BOUNDS (0x01000000U)
+ M2_CDE_DMA2_BLOCKED (0x00400000U)
+ M2_CDE_DMA1_BLOCKED (0x00200000U)
+ M2_CDE_ID_READY (0x00100000U)
+ M2_CDE_ARM_FENCE (0x00080000U)
+ M2_CDE_EXT_INT (0x00040000, // Added by Phil
+ M2_CDE_3DO_CARD_INT (0x00020000U)
+ M2_CDE_ARM_INT (0x00010000U)
+ M2_CDE_CD_DMA2_OF (0x00004000U)
+ M2_CDE_CD_DMA1_OF (0x00002000U)
+ M2_CDE_ARM_ABORT (0x00001000U)
+ M2_CDE_CD_DMA2_DONE (0x00000800U)
+ M2_CDE_CD_DMA1_DONE (0x00000400U)
+ M2_CDE_DMA2_DONE (0x00000100U)
+ M2_CDE_DMA1_DONE (0x00000080U)
+ M2_CDE_PBUS_ERROR (0x00000040U)
+ M2_CDE_CD_CMD_WRT_DONE (0x00000020U)
+ M2_CDE_CD_STS_RD_DONE (0x00000010U)
+ M2_CDE_CD_STS_FL_DONE (0x00000008U)
+ M2_CDE_GPIO1_INT (0x00000004U)
+ M2_CDE_GPIO2_INT (0x00000002U)
+ M2_CDE_BBUS_ERROR (0x00000001U)
};
enum cde_dma_cntl
{
- M2_CDE_DMA_DIRECTION (0x00000400, /* PowerBus to BioBus if set */
- M2_CDE_DMA_RESET (0x00000200, /* Reset engine if set */
- M2_CDE_DMA_GLOBAL (0x00000100, /* snoopable trans if set */
- M2_CDE_DMA_CURR_VALID (0x00000080, /* current setup valid if set */
- M2_CDE_DMA_NEXT_VALID (0x00000040, /* next setup valid if set */
- M2_CDE_DMA_GO_FOREVER (0x00000020, /* copy next to current if set*/
- M2_CDE_PB_CHANNEL_MASK (0x0000001F, /* powerbus channel to use */
+ M2_CDE_DMA_DIRECTION (0x00000400, /* PowerBus to BioBus if set */
+ M2_CDE_DMA_RESET (0x00000200, /* Reset engine if set */
+ M2_CDE_DMA_GLOBAL (0x00000100, /* snoopable trans if set */
+ M2_CDE_DMA_CURR_VALID (0x00000080, /* current setup valid if set */
+ M2_CDE_DMA_NEXT_VALID (0x00000040, /* next setup valid if set */
+ M2_CDE_DMA_GO_FOREVER (0x00000020, /* copy next to current if set*/
+ M2_CDE_PB_CHANNEL_MASK (0x0000001F, /* powerbus channel to use */
};
// CDE
-#define M2_CDE_WRITEN_HOLD (0x00000003U)
-#define M2_CDE_WRITEN_SETUP (0x0000001CU)
-#define M2_CDE_READ_HOLD (0x00000060U)
-#define M2_CDE_READ_SETUP (0x00000380U)
-#define M2_CDE_PAGEMODE (0x00000400U)
-#define M2_CDE_DATAWIDTH (0x00001800U)
-#define M2_CDE_DATAWIDTH_8 (0x00000000U)
-#define M2_CDE_DATAWIDTH_16 (0x00000800U)
-#define M2_CDE_READ_SETUP_IO (0x0000E000U)
-#define M2_CDE_MODEA (0x00010000U)
-#define M2_CDE_HIDEA (0x00020000U)
+#define M2_CDE_WRITEN_HOLD (0x00000003U)
+#define M2_CDE_WRITEN_SETUP (0x0000001CU)
+#define M2_CDE_READ_HOLD (0x00000060U)
+#define M2_CDE_READ_SETUP (0x00000380U)
+#define M2_CDE_PAGEMODE (0x00000400U)
+#define M2_CDE_DATAWIDTH (0x00001800U)
+#define M2_CDE_DATAWIDTH_8 (0x00000000U)
+#define M2_CDE_DATAWIDTH_16 (0x00000800U)
+#define M2_CDE_READ_SETUP_IO (0x0000E000U)
+#define M2_CDE_MODEA (0x00010000U)
+#define M2_CDE_HIDEA (0x00020000U)
// TE
@@ -266,40 +266,40 @@ enum dev_mask
//-------------------------------------------------
// Triangle Engine Master Mode
-#define M2_TE_MASTER_MODE_RESET (0x00000001U)
-#define M2_TE_MASTER_MODE_DTEXT (0x00000002U)
-#define M2_TE_MASTER_MODE_DSHADE (0x00000004U)
-#define M2_TE_MASTER_MODE_DBLEND (0x00000008U)
-#define M2_TE_MASTER_MODE_DZBUF (0x00000010U)
-#define M2_TE_MASTER_MODE_DDITH (0x00000020U)
+#define M2_TE_MASTER_MODE_RESET (0x00000001U)
+#define M2_TE_MASTER_MODE_DTEXT (0x00000002U)
+#define M2_TE_MASTER_MODE_DSHADE (0x00000004U)
+#define M2_TE_MASTER_MODE_DBLEND (0x00000008U)
+#define M2_TE_MASTER_MODE_DZBUF (0x00000010U)
+#define M2_TE_MASTER_MODE_DDITH (0x00000020U)
// Triangle Engine Immediate Control
-#define M2_TE_TEICNTL_INT (0x00000001U)
-#define M2_TE_TEICNTL_STEP (0x00000002U)
-#define M2_TE_TEICNTL_STPL (0x00000004U)
-#define M2_TE_TEICNTL_STPI (0x00000008U)
-#define M2_TE_TEICNTL_RSTRT (0x00000010U)
-#define M2_TE_TEICNTL_STRT (0x00000020U)
-
-#define M2_TE_TEDCNTL_TLD (0x00000001U)
-#define M2_TE_TEDCNTL_JA (0x00000002U)
-#define M2_TE_TEDCNTL_JR (0x00000004U)
-#define M2_TE_TEDCNTL_INT (0x00000008U)
-#define M2_TE_TEDCNTL_PSE (0x00000010U)
-#define M2_TE_TEDCNTL_SYNC (0x00000020U)
-
-#define M2_TE_INTSTAT_DEFERRED_INSTR (0x00000100U)
-#define M2_TE_INTSTAT_IMMEDIATE_INSTR (0x00000200U)
-#define M2_TE_INTSTAT_LIST_END (0x00000400U)
-#define M2_TE_INTSTAT_WINDOW_CLIP (0x00000800U)
-#define M2_TE_INTSTAT_SPECIAL_INSTR (0x00001000U)
-#define M2_TE_INTSTAT_UNIMPLEMENTED_INSTR (0x00002000U)
-#define M2_TE_INTSTAT_SUPERVISOR (0x00004000U)
-#define M2_TE_INTSTAT_ANY_RENDER (0x00008000U)
-#define M2_TE_INTSTAT_Z_FUNC (0x00010000U)
-#define M2_TE_INTSTAT_ALU_STATUS (0x00020000U)
-#define M2_TE_INTSTAT_FB_CLIP (0x00040000U)
-#define M2_TE_INTSTAT_IMMEDIATE (0x00080000U)
+#define M2_TE_TEICNTL_INT (0x00000001U)
+#define M2_TE_TEICNTL_STEP (0x00000002U)
+#define M2_TE_TEICNTL_STPL (0x00000004U)
+#define M2_TE_TEICNTL_STPI (0x00000008U)
+#define M2_TE_TEICNTL_RSTRT (0x00000010U)
+#define M2_TE_TEICNTL_STRT (0x00000020U)
+
+#define M2_TE_TEDCNTL_TLD (0x00000001U)
+#define M2_TE_TEDCNTL_JA (0x00000002U)
+#define M2_TE_TEDCNTL_JR (0x00000004U)
+#define M2_TE_TEDCNTL_INT (0x00000008U)
+#define M2_TE_TEDCNTL_PSE (0x00000010U)
+#define M2_TE_TEDCNTL_SYNC (0x00000020U)
+
+#define M2_TE_INTSTAT_DEFERRED_INSTR (0x00000100U)
+#define M2_TE_INTSTAT_IMMEDIATE_INSTR (0x00000200U)
+#define M2_TE_INTSTAT_LIST_END (0x00000400U)
+#define M2_TE_INTSTAT_WINDOW_CLIP (0x00000800U)
+#define M2_TE_INTSTAT_SPECIAL_INSTR (0x00001000U)
+#define M2_TE_INTSTAT_UNIMPLEMENTED_INSTR (0x00002000U)
+#define M2_TE_INTSTAT_SUPERVISOR (0x00004000U)
+#define M2_TE_INTSTAT_ANY_RENDER (0x00008000U)
+#define M2_TE_INTSTAT_Z_FUNC (0x00010000U)
+#define M2_TE_INTSTAT_ALU_STATUS (0x00020000U)
+#define M2_TE_INTSTAT_FB_CLIP (0x00040000U)
+#define M2_TE_INTSTAT_IMMEDIATE (0x00080000U)
// IWP
// IRP
@@ -314,16 +314,16 @@ enum dev_mask
//-------------------------------------------------
// Vertex State
-#define M2_TE_VERTEXSTATE_TSORT_MASK (0x00000007U)
-#define M2_TE_VERTEXSTATE_TSORT_OMN (0x00000001U)
-#define M2_TE_VERTEXSTATE_TSORT_MNO (0x00000002U)
-#define M2_TE_VERTEXSTATE_TSORT_ONM (0x00000003U)
-#define M2_TE_VERTEXSTATE_TSORT_NOM (0x00000004U)
-#define M2_TE_VERTEXSTATE_TSORT_MON (0x00000005U)
-#define M2_TE_VERTEXSTATE_TSORT_NMO (0x00000006U)
+#define M2_TE_VERTEXSTATE_TSORT_MASK (0x00000007U)
+#define M2_TE_VERTEXSTATE_TSORT_OMN (0x00000001U)
+#define M2_TE_VERTEXSTATE_TSORT_MNO (0x00000002U)
+#define M2_TE_VERTEXSTATE_TSORT_ONM (0x00000003U)
+#define M2_TE_VERTEXSTATE_TSORT_NOM (0x00000004U)
+#define M2_TE_VERTEXSTATE_TSORT_MON (0x00000005U)
+#define M2_TE_VERTEXSTATE_TSORT_NMO (0x00000006U)
-#define M2_TE_VERTEXSTATE_VCNT_SHIFT (3U)
-#define M2_TE_VERTEXSTATE_VCNT_MASK (0x00000018U)
+#define M2_TE_VERTEXSTATE_VCNT_SHIFT (3U)
+#define M2_TE_VERTEXSTATE_VCNT_MASK (0x00000018U)
//-------------------------------------------------
@@ -331,9 +331,9 @@ enum dev_mask
//-------------------------------------------------
// Edge and Span Walker Control
-#define ESCNTL_DSPOFF (0x00000001U)
-#define ESCNTL_DUSCAN (0x00000002U)
-#define ESCNTL_PERSPECTIVEOFF (0x00000004U)
+#define ESCNTL_DSPOFF (0x00000001U)
+#define ESCNTL_DUSCAN (0x00000002U)
+#define ESCNTL_PERSPECTIVEOFF (0x00000004U)
//-------------------------------------------------
@@ -341,148 +341,148 @@ enum dev_mask
//-------------------------------------------------
// Texture Mapper Master Control (0x00046400)
-#define M2_TE_TXTCNTL_MMDMA_TRAM_ON (0x00000004U)
-#define M2_TE_TXTCNTL_MMDMA_PIP_ON (0x00000008U)
-#define M2_TE_TXTCNTL_SNOOP_ON (0x00000020U)
+#define M2_TE_TXTCNTL_MMDMA_TRAM_ON (0x00000004U)
+#define M2_TE_TXTCNTL_MMDMA_PIP_ON (0x00000008U)
+#define M2_TE_TXTCNTL_SNOOP_ON (0x00000020U)
// Texture Load Control (0x00046404)
-#define M2_TE_TXTLDCNTL_SRCBITOFFS (0x00000007U)
-#define M2_TE_TXTLDCNTL_LDMODE_MASK (0x00000300U)
-#define M2_TE_TXTLDCNTL_LDMODE_TEXLOAD (0x00000000U)
-#define M2_TE_TXTLDCNTL_LDMODE_MMDMA (0x00000100U)
-#define M2_TE_TXTLDCNTL_LDMODE_PIPLOAD (0x00000200U)
-#define M2_TE_TXTLDCNTL_LDMODE_RESERVED (0x00000300U)
-#define M2_TE_TXTLDCNTL_COMPRESSED (0x00000400U)
+#define M2_TE_TXTLDCNTL_SRCBITOFFS (0x00000007U)
+#define M2_TE_TXTLDCNTL_LDMODE_MASK (0x00000300U)
+#define M2_TE_TXTLDCNTL_LDMODE_TEXLOAD (0x00000000U)
+#define M2_TE_TXTLDCNTL_LDMODE_MMDMA (0x00000100U)
+#define M2_TE_TXTLDCNTL_LDMODE_PIPLOAD (0x00000200U)
+#define M2_TE_TXTLDCNTL_LDMODE_RESERVED (0x00000300U)
+#define M2_TE_TXTLDCNTL_COMPRESSED (0x00000400U)
// Address Control (0x00046408)
-#define M2_TE_TXTADDRCNTL_LODMAX_MASK (0x0000000fU)
-#define M2_TE_TXTADDRCNTL_FILTERSEL_MASK (0x00000003U)
-#define M2_TE_TXTADDRCNTL_FILTERSEL_POINT (0x00000000U)
-#define M2_TE_TXTADDRCNTL_FILTERSEL_LINEAR (0x00000001U)
-#define M2_TE_TXTADDRCNTL_FILTERSEL_BILINEAR (0x00000002U)
-#define M2_TE_TXTADDRCNTL_FILTERSEL_QUASITRI (0x00000003U)
-#define M2_TE_TXTADDRCNTL_R12FILTERSEL_SHIFT (4U)
-#define M2_TE_TXTADDRCNTL_R3FILTERSEL_SHIFT (7U)
-#define M2_TE_TXTADDRCNTL_R45FILTERSEL_SHIFT (10U)
-#define M2_TE_TXTADDRCNTL_LOOKUP_EN (0x00002000U)
+#define M2_TE_TXTADDRCNTL_LODMAX_MASK (0x0000000fU)
+#define M2_TE_TXTADDRCNTL_FILTERSEL_MASK (0x00000003U)
+#define M2_TE_TXTADDRCNTL_FILTERSEL_POINT (0x00000000U)
+#define M2_TE_TXTADDRCNTL_FILTERSEL_LINEAR (0x00000001U)
+#define M2_TE_TXTADDRCNTL_FILTERSEL_BILINEAR (0x00000002U)
+#define M2_TE_TXTADDRCNTL_FILTERSEL_QUASITRI (0x00000003U)
+#define M2_TE_TXTADDRCNTL_R12FILTERSEL_SHIFT (4U)
+#define M2_TE_TXTADDRCNTL_R3FILTERSEL_SHIFT (7U)
+#define M2_TE_TXTADDRCNTL_R45FILTERSEL_SHIFT (10U)
+#define M2_TE_TXTADDRCNTL_LOOKUP_EN (0x00002000U)
// PIP Control (0x0004640C)
-#define M2_TE_TXTPIPCNTL_INDEX_OFFSET (0x000000ffU)
-#define M2_TE_TXTPIPCNTL_COLORSEL_MASK (0x00000700U)
-#define M2_TE_TXTPIPCNTL_COLORSEL_SHIFT (8U)
-#define M2_TE_TXTPIPCNTL_ALPHASEL_MASK (0x00003800U)
-#define M2_TE_TXTPIPCNTL_ALPHASEL_SHIFT (11U)
-#define M2_TE_TXTPIPCNTL_SSBSEL_MASK (0x0001c000U)
-#define M2_TE_TXTPIPCNTL_SSBSEL_SHIFT (14U)
-
-#define M2_TE_TXTPIPCNTL_SEL_CONSTANT 0
-#define M2_TE_TXTPIPCNTL_SEL_TRAM 1
-#define M2_TE_TXTPIPCNTL_SEL_PIP 2
+#define M2_TE_TXTPIPCNTL_INDEX_OFFSET (0x000000ffU)
+#define M2_TE_TXTPIPCNTL_COLORSEL_MASK (0x00000700U)
+#define M2_TE_TXTPIPCNTL_COLORSEL_SHIFT (8U)
+#define M2_TE_TXTPIPCNTL_ALPHASEL_MASK (0x00003800U)
+#define M2_TE_TXTPIPCNTL_ALPHASEL_SHIFT (11U)
+#define M2_TE_TXTPIPCNTL_SSBSEL_MASK (0x0001c000U)
+#define M2_TE_TXTPIPCNTL_SSBSEL_SHIFT (14U)
+
+#define M2_TE_TXTPIPCNTL_SEL_CONSTANT 0
+#define M2_TE_TXTPIPCNTL_SEL_TRAM 1
+#define M2_TE_TXTPIPCNTL_SEL_PIP 2
// Texture Application Control (0x00046410)
-#define M2_TE_TXTTABCNTL_C_ASEL_MASK 0x00000007
-#define M2_TE_TXTTABCNTL_C_ASEL_SHIFT 0
-#define M2_TE_TXTTABCNTL_C_BSEL_MASK 0x00000038
-#define M2_TE_TXTTABCNTL_C_BSEL_SHIFT 3
-#define M2_TE_TXTTABCNTL_C_TSEL_MASK 0x000001c0
-#define M2_TE_TXTTABCNTL_C_TSEL_SHIFT 6
-
-#define M2_TE_TXTTABCNTL_C_ABTSEL_AITER 0
-#define M2_TE_TXTTABCNTL_C_ABTSEL_CITER 1
-#define M2_TE_TXTTABCNTL_C_ABTSEL_AT 2
-#define M2_TE_TXTTABCNTL_C_ABTSEL_CT 3
-#define M2_TE_TXTTABCNTL_C_ABTSEL_ACONST 4
-#define M2_TE_TXTTABCNTL_C_ABTSEL_CCONST 5
-
-#define M2_TE_TXTTABCNTL_C_OSEL_MASK 0x00000600
-#define M2_TE_TXTTABCNTL_C_OSEL_SHIFT 9
-
-#define M2_TE_TXTTABCNTL_CO_SEL_CITER 0
-#define M2_TE_TXTTABCNTL_CO_SEL_CT 1
-#define M2_TE_TXTTABCNTL_CO_SEL_BLEND 2
-#define M2_TE_TXTTABCNTL_CO_SEL_RESERVED 3
-
-#define M2_TE_TXTTABCNTL_A_ASEL_MASK 0x00001800
-#define M2_TE_TXTTABCNTL_A_ASEL_SHIFT 11
-#define M2_TE_TXTTABCNTL_A_BSEL_MASK 0x00006000
-#define M2_TE_TXTTABCNTL_A_BSEL_SHIFT 13
-
-#define M2_TE_TXTTABCNTL_A_ABSEL_AITER 0
-#define M2_TE_TXTTABCNTL_A_ABSEL_AT 1
-#define M2_TE_TXTTABCNTL_A_ABSEL_ACONST 2
-
-#define M2_TE_TXTTABCNTL_A_OSEL_MASK 0x00018000
-#define M2_TE_TXTTABCNTL_A_OSEL_SHIFT 15
-
-#define M2_TE_TXTTABCNTL_AO_SEL_AITER 0
-#define M2_TE_TXTTABCNTL_AO_SEL_AT 1
-#define M2_TE_TXTTABCNTL_AO_SEL_BLEND 2
-#define M2_TE_TXTTABCNTL_AO_SEL_RESERVED 3
-
-#define M2_TE_TXTTABCNTL_BLENDOP_MASK 0x00010000
-#define M2_TE_TXTTABCNTL_BLENDOP_SHIFT 16
-#define M2_TE_TXTTABCNTL_BLENDOP_LERP 0
-#define M2_TE_TXTTABCNTL_BLENDOP_MULT 1
+#define M2_TE_TXTTABCNTL_C_ASEL_MASK 0x00000007
+#define M2_TE_TXTTABCNTL_C_ASEL_SHIFT 0
+#define M2_TE_TXTTABCNTL_C_BSEL_MASK 0x00000038
+#define M2_TE_TXTTABCNTL_C_BSEL_SHIFT 3
+#define M2_TE_TXTTABCNTL_C_TSEL_MASK 0x000001c0
+#define M2_TE_TXTTABCNTL_C_TSEL_SHIFT 6
+
+#define M2_TE_TXTTABCNTL_C_ABTSEL_AITER 0
+#define M2_TE_TXTTABCNTL_C_ABTSEL_CITER 1
+#define M2_TE_TXTTABCNTL_C_ABTSEL_AT 2
+#define M2_TE_TXTTABCNTL_C_ABTSEL_CT 3
+#define M2_TE_TXTTABCNTL_C_ABTSEL_ACONST 4
+#define M2_TE_TXTTABCNTL_C_ABTSEL_CCONST 5
+
+#define M2_TE_TXTTABCNTL_C_OSEL_MASK 0x00000600
+#define M2_TE_TXTTABCNTL_C_OSEL_SHIFT 9
+
+#define M2_TE_TXTTABCNTL_CO_SEL_CITER 0
+#define M2_TE_TXTTABCNTL_CO_SEL_CT 1
+#define M2_TE_TXTTABCNTL_CO_SEL_BLEND 2
+#define M2_TE_TXTTABCNTL_CO_SEL_RESERVED 3
+
+#define M2_TE_TXTTABCNTL_A_ASEL_MASK 0x00001800
+#define M2_TE_TXTTABCNTL_A_ASEL_SHIFT 11
+#define M2_TE_TXTTABCNTL_A_BSEL_MASK 0x00006000
+#define M2_TE_TXTTABCNTL_A_BSEL_SHIFT 13
+
+#define M2_TE_TXTTABCNTL_A_ABSEL_AITER 0
+#define M2_TE_TXTTABCNTL_A_ABSEL_AT 1
+#define M2_TE_TXTTABCNTL_A_ABSEL_ACONST 2
+
+#define M2_TE_TXTTABCNTL_A_OSEL_MASK 0x00018000
+#define M2_TE_TXTTABCNTL_A_OSEL_SHIFT 15
+
+#define M2_TE_TXTTABCNTL_AO_SEL_AITER 0
+#define M2_TE_TXTTABCNTL_AO_SEL_AT 1
+#define M2_TE_TXTTABCNTL_AO_SEL_BLEND 2
+#define M2_TE_TXTTABCNTL_AO_SEL_RESERVED 3
+
+#define M2_TE_TXTTABCNTL_BLENDOP_MASK 0x00010000
+#define M2_TE_TXTTABCNTL_BLENDOP_SHIFT 16
+#define M2_TE_TXTTABCNTL_BLENDOP_LERP 0
+#define M2_TE_TXTTABCNTL_BLENDOP_MULT 1
// TAB Constants
-#define M2_TE_TXTTABCONST_BLUE 0x000000ff
-#define M2_TE_TXTTABCONST_BLUE_SHIFT 0
-#define M2_TE_TXTTABCONST_GREEN 0x0000ff00
-#define M2_TE_TXTTABCONST_GREEN_SHIFT 8
-#define M2_TE_TXTTABCONST_RED 0x00ff0000
-#define M2_TE_TXTTABCONST_RED_SHIFT 16
-#define M2_TE_TXTTABCONST_ALPHA 0x7f000000
-#define M2_TE_TXTTABCONST_ALPHA_SHIFT 24
-#define M2_TE_TXTTABCONST_SSB 0x80000000
+#define M2_TE_TXTTABCONST_BLUE 0x000000ff
+#define M2_TE_TXTTABCONST_BLUE_SHIFT 0
+#define M2_TE_TXTTABCONST_GREEN 0x0000ff00
+#define M2_TE_TXTTABCONST_GREEN_SHIFT 8
+#define M2_TE_TXTTABCONST_RED 0x00ff0000
+#define M2_TE_TXTTABCONST_RED_SHIFT 16
+#define M2_TE_TXTTABCONST_ALPHA 0x7f000000
+#define M2_TE_TXTTABCONST_ALPHA_SHIFT 24
+#define M2_TE_TXTTABCONST_SSB 0x80000000
// Texture Loader Destination Base (0x00046414)
-#define M2_TE_TXTLDDSTBASE_ADDR 0x00003ffc
+#define M2_TE_TXTLDDSTBASE_ADDR 0x00003ffc
// Texture Lod Base 0 (0x00046414)
// Texture Lod Base 1 (0x00046418)
// Texture Lod Base 2 (0x0004641C)
// Texture Lod Base 3 (0x00046420)
-#define M2_TE_TXTLODBASE_MASK 0x00003ffc
+#define M2_TE_TXTLODBASE_MASK 0x00003ffc
// Texture Loader Source Base (0x00046424)
-#define M2_TE_TXTLDSRCBASE_ADDR 0x00003fff
+#define M2_TE_TXTLDSRCBASE_ADDR 0x00003fff
// Texture Loader Counts (0x00046428)
-#define M2_TE_TXTLDBYTECNT_COUNT 0x0fffffff
-#define M2_TE_TXTLDROWCNT_COUNT 0x0fffffff
-#define M2_TE_TXTLDTEXCNT_COUNT 0x0fffffff
+#define M2_TE_TXTLDBYTECNT_COUNT 0x0fffffff
+#define M2_TE_TXTLDROWCNT_COUNT 0x0fffffff
+#define M2_TE_TXTLDTEXCNT_COUNT 0x0fffffff
// Texture Loader Width (0x00046428)
-#define M2_TE_TxTLDWIDTH_SRCROW 0x0000ffff
-#define M2_TE_TxTLDWIDTH_DSTROW_SHIFT 16
-#define M2_TE_TxTLDWIDTH_DSTROW 0xffff0000
+#define M2_TE_TxTLDWIDTH_SRCROW 0x0000ffff
+#define M2_TE_TxTLDWIDTH_DSTROW_SHIFT 16
+#define M2_TE_TxTLDWIDTH_DSTROW 0xffff0000
// Texture Size (0x0004642C)
-#define M2_TE_TXTUVMAX_VMAX_MASK 0x000003ff
-#define M2_TE_TXTUVMAX_VMAX_SHIFT 0
-#define M2_TE_TXTUVMAX_UMAX_MASK 0x03ff0000
-#define M2_TE_TXTUVMAX_UMAX_SHIFT 16
+#define M2_TE_TXTUVMAX_VMAX_MASK 0x000003ff
+#define M2_TE_TXTUVMAX_VMAX_SHIFT 0
+#define M2_TE_TXTUVMAX_UMAX_MASK 0x03ff0000
+#define M2_TE_TXTUVMAX_UMAX_SHIFT 16
// Texture Mask (0x00046430)
-#define M2_TE_TXTUVMASK_VMASK_MASK 0x000003ff
-#define M2_TE_TXTUVMASK_VMASK_SHIFT 0
-#define M2_TE_TXTUVMASK_UMASK_MASK 0x03ff0000
-#define M2_TE_TXTUVMASK_UMASK_SHIFT 16
+#define M2_TE_TXTUVMASK_VMASK_MASK 0x000003ff
+#define M2_TE_TXTUVMASK_VMASK_SHIFT 0
+#define M2_TE_TXTUVMASK_UMASK_MASK 0x03ff0000
+#define M2_TE_TXTUVMASK_UMASK_SHIFT 16
// TRAM Format (0x0004643C)
// TODO: Expansion formats
-#define M2_TE_TXTEXPFORM_CDEPTH_MASK 0x0000000f
-#define M2_TE_TXTEXPFORM_CDEPTH_SHIFT 0
-#define M2_TE_TXTEXPFORM_IDEPTH_MASK 0x0000000f
-#define M2_TE_TXTEXPFORM_IDEPTH_SHIFT 0
-#define M2_TE_TXTEXPFORM_ADEPTH_MASK 0x000000f0
-#define M2_TE_TXTEXPFORM_ADEPTH_SHIFT 4
-#define M2_TE_TXTEXPFORM_TRANSPARENT 0x00000100
-#define M2_TE_TXTEXPFORM_SSBON 0x00000200
-#define M2_TE_TXTEXPFORM_COLORON 0x00000400
-#define M2_TE_TXTEXPFORM_INDEXON 0x00000400
-#define M2_TE_TXTEXPFORM_ALPHAON 0x00000800
-#define M2_TE_TXTEXPFORM_LITERAL 0x00001000
+#define M2_TE_TXTEXPFORM_CDEPTH_MASK 0x0000000f
+#define M2_TE_TXTEXPFORM_CDEPTH_SHIFT 0
+#define M2_TE_TXTEXPFORM_IDEPTH_MASK 0x0000000f
+#define M2_TE_TXTEXPFORM_IDEPTH_SHIFT 0
+#define M2_TE_TXTEXPFORM_ADEPTH_MASK 0x000000f0
+#define M2_TE_TXTEXPFORM_ADEPTH_SHIFT 4
+#define M2_TE_TXTEXPFORM_TRANSPARENT 0x00000100
+#define M2_TE_TXTEXPFORM_SSBON 0x00000200
+#define M2_TE_TXTEXPFORM_COLORON 0x00000400
+#define M2_TE_TXTEXPFORM_INDEXON 0x00000400
+#define M2_TE_TXTEXPFORM_ALPHAON 0x00000800
+#define M2_TE_TXTEXPFORM_LITERAL 0x00001000
// Format Registers
@@ -493,203 +493,203 @@ enum dev_mask
//-------------------------------------------------
// Snoop (0x0048000)
-#define M2_TE_DBSNOOP_DESTWRSNOOP 0x00000001
-#define M2_TE_DBSNOOP_SRCRDSNOOP 0x00000002
-#define M2_TE_DBSNOOP_ZWRSNOOP 0x00000004
-#define M2_TE_DBSNOOP_ZRDSNOOP 0x00000008
+#define M2_TE_DBSNOOP_DESTWRSNOOP 0x00000001
+#define M2_TE_DBSNOOP_SRCRDSNOOP 0x00000002
+#define M2_TE_DBSNOOP_ZWRSNOOP 0x00000004
+#define M2_TE_DBSNOOP_ZRDSNOOP 0x00000008
// Supervisor General Control (0x0048004)
-#define M2_TE_DBSUPERGENCTL_DESTOUTEN 0x00000001
-#define M2_TE_DBSUPERGENCTL_DESTWR16BEN 0x00000002
-#define M2_TE_DBSUPERGENCTL_ZWR16BEN 0x00000004
+#define M2_TE_DBSUPERGENCTL_DESTOUTEN 0x00000001
+#define M2_TE_DBSUPERGENCTL_DESTWR16BEN 0x00000002
+#define M2_TE_DBSUPERGENCTL_ZWR16BEN 0x00000004
// User General Control (0x0048008)
-#define M2_TE_DBUSERGENCTL_DESTOUT_MASK 0x0000000f
-#define M2_TE_DBUSERGENCTL_DITHEREN 0x00000010
-#define M2_TE_DBUSERGENCTL_SRCINEN 0x00000020
-#define M2_TE_DBUSERGENCTL_BLENDEN 0x00000040
-#define M2_TE_DBUSERGENCTL_WCLIPOUTEN 0x00000080
-#define M2_TE_DBUSERGENCTL_WCLIPINEN 0x00000100
-#define M2_TE_DBUSERGENCTL_ZOUTEN 0x00000200
-#define M2_TE_DBUSERGENCTL_ZBUFEN 0x00000400
+#define M2_TE_DBUSERGENCTL_DESTOUT_MASK 0x0000000f
+#define M2_TE_DBUSERGENCTL_DITHEREN 0x00000010
+#define M2_TE_DBUSERGENCTL_SRCINEN 0x00000020
+#define M2_TE_DBUSERGENCTL_BLENDEN 0x00000040
+#define M2_TE_DBUSERGENCTL_WCLIPOUTEN 0x00000080
+#define M2_TE_DBUSERGENCTL_WCLIPINEN 0x00000100
+#define M2_TE_DBUSERGENCTL_ZOUTEN 0x00000200
+#define M2_TE_DBUSERGENCTL_ZBUFEN 0x00000400
// Discard Control (0x004800C)
-#define M2_TE_DBDISCARDCTL_ADISEN 0x00000001
-#define M2_TE_DBDISCARDCTL_RGBDISEN 0x00000002
-#define M2_TE_DBDISCARDCTL_SSBDISEN 0x00000004
-#define M2_TE_DBDISCARDCTL_ZCLIPDISEN 0x00000008
+#define M2_TE_DBDISCARDCTL_ADISEN 0x00000001
+#define M2_TE_DBDISCARDCTL_RGBDISEN 0x00000002
+#define M2_TE_DBDISCARDCTL_SSBDISEN 0x00000004
+#define M2_TE_DBDISCARDCTL_ZCLIPDISEN 0x00000008
// Status (0x0048010)
-#define M2_TE_DBSTATUS_ANYREND 0x00000001
-#define M2_TE_DBSTATUS_ZFUNC_GT 0x00000002
-#define M2_TE_DBSTATUS_ZFUNC_EQ 0x00000004
-#define M2_TE_DBSTATUS_ZFUNC_LT 0x00000008
-#define DBSTATUS_ALUSTAT_BLUE_GT 0x00000010
-#define DBSTATUS_ALUSTAT_BLUE_EQ 0x00000020
-#define DBSTATUS_ALUSTAT_BLUE_LT 0x00000040
-#define DBSTATUS_ALUSTAT_GREEN_GT 0x00000080
-#define DBSTATUS_ALUSTAT_GREEN_EQ 0x00000100
-#define DBSTATUS_ALUSTAT_GREEN_LT 0x00000200
-#define DBSTATUS_ALUSTAT_RED_GT 0x00000400
-#define DBSTATUS_ALUSTAT_RED_EQ 0x00000800
-#define DBSTATUS_ALUSTAT_RED_LT 0x00001000
-#define M2_TE_DBSTATUS_ZCLIP 0x00002000
-#define M2_TE_DBSTATUS_WINCLIP 0x00004000
-#define M2_TE_DBSTATUS_FBCLIP 0x00008000
+#define M2_TE_DBSTATUS_ANYREND 0x00000001
+#define M2_TE_DBSTATUS_ZFUNC_GT 0x00000002
+#define M2_TE_DBSTATUS_ZFUNC_EQ 0x00000004
+#define M2_TE_DBSTATUS_ZFUNC_LT 0x00000008
+#define DBSTATUS_ALUSTAT_BLUE_GT 0x00000010
+#define DBSTATUS_ALUSTAT_BLUE_EQ 0x00000020
+#define DBSTATUS_ALUSTAT_BLUE_LT 0x00000040
+#define DBSTATUS_ALUSTAT_GREEN_GT 0x00000080
+#define DBSTATUS_ALUSTAT_GREEN_EQ 0x00000100
+#define DBSTATUS_ALUSTAT_GREEN_LT 0x00000200
+#define DBSTATUS_ALUSTAT_RED_GT 0x00000400
+#define DBSTATUS_ALUSTAT_RED_EQ 0x00000800
+#define DBSTATUS_ALUSTAT_RED_LT 0x00001000
+#define M2_TE_DBSTATUS_ZCLIP 0x00002000
+#define M2_TE_DBSTATUS_WINCLIP 0x00004000
+#define M2_TE_DBSTATUS_FBCLIP 0x00008000
// Interrupt Control (0x00048014)
-#define M2_TE_DBINTCNTL_ZFUNCSTATINTEN_MASK 0x00000003
-#define M2_TE_DBINTCNTL_ZFUNCSTATINTEN_MASK 0x00000003
+#define M2_TE_DBINTCNTL_ZFUNCSTATINTEN_MASK 0x00000003
+#define M2_TE_DBINTCNTL_ZFUNCSTATINTEN_MASK 0x00000003
// Framebuffer XY Clip Control (0x00048018)
-#define M2_TE_DBFBCLIP_YFBCLIP_MASK 0x000007ff
-#define M2_TE_DBFBCLIP_YFBCLIP_SHIFT 0
-#define M2_TE_DBFBCLIP_XFBCLIP_MASK 0x07ff0000
-#define M2_TE_DBFBCLIP_XFBCLIP_SHIFT 16
+#define M2_TE_DBFBCLIP_YFBCLIP_MASK 0x000007ff
+#define M2_TE_DBFBCLIP_YFBCLIP_SHIFT 0
+#define M2_TE_DBFBCLIP_XFBCLIP_MASK 0x07ff0000
+#define M2_TE_DBFBCLIP_XFBCLIP_SHIFT 16
// Window X Clip Control (0x0004801C)
-#define M2_TE_DBFBXWINCLIP_XMAX_MASK 0x000007ff
-#define M2_TE_DBFBXWINCLIP_XMAX_SHIFT 0
-#define M2_TE_DBFBXWINCLIP_XMIN_MASK 0x07ff0000
-#define M2_TE_DBFBXWINCLIP_XMIN_SHIFT 16
+#define M2_TE_DBFBXWINCLIP_XMAX_MASK 0x000007ff
+#define M2_TE_DBFBXWINCLIP_XMAX_SHIFT 0
+#define M2_TE_DBFBXWINCLIP_XMIN_MASK 0x07ff0000
+#define M2_TE_DBFBXWINCLIP_XMIN_SHIFT 16
// Window Y Clip Control (0x00048020)
-#define M2_TE_DBFBYWINCLIP_YMAX_MASK 0x000007ff
-#define M2_TE_DBFBYWINCLIP_YMAX_SHIFT 0
-#define M2_TE_DBFBYWINCLIP_YMIN_MASK 0x07ff0000
-#define M2_TE_DBFBYWINCLIP_YMIN_SHIFT 16
+#define M2_TE_DBFBYWINCLIP_YMAX_MASK 0x000007ff
+#define M2_TE_DBFBYWINCLIP_YMAX_SHIFT 0
+#define M2_TE_DBFBYWINCLIP_YMIN_MASK 0x07ff0000
+#define M2_TE_DBFBYWINCLIP_YMIN_SHIFT 16
// Destination Write Control (0x0048024)
-#define M2_TE_DBDESTCNTL_32BPP 0x00000001
+#define M2_TE_DBDESTCNTL_32BPP 0x00000001
// Destination Write Base Address (0x0048028)
// Destination X Stride (0x004802C)
-#define M2_TE_DBDEST_XSTRIDE 0x000007ff
+#define M2_TE_DBDEST_XSTRIDE 0x000007ff
// Source Read Control (0x00048030)
-#define M2_TE_DBSRCCNTL_32BPP 0x00000001
-#define M2_TE_DBSRCCNTL_MSBREP 0x00000002
+#define M2_TE_DBSRCCNTL_32BPP 0x00000001
+#define M2_TE_DBSRCCNTL_MSBREP 0x00000002
// Source Read Base Address (0x00048034)
// Source X Stride (0x00048038)
-#define M2_TE_DBSRCXSTRIDE 0x000007ff
+#define M2_TE_DBSRCXSTRIDE 0x000007ff
// Source XY Offset (0x0004803C)
-#define M2_TE_DBSRCOFFS_YOFFS_MASK 0x00000fff
-#define M2_TE_DBSRCOFFS_YOFFS_SHIFT 0
-#define M2_TE_DBSRCOFFS_XOFFS_MASK 0x0fff0000
-#define M2_TE_DBSRCOFFS_XOFFS_SHIFT 16
+#define M2_TE_DBSRCOFFS_YOFFS_MASK 0x00000fff
+#define M2_TE_DBSRCOFFS_YOFFS_SHIFT 0
+#define M2_TE_DBSRCOFFS_XOFFS_MASK 0x0fff0000
+#define M2_TE_DBSRCOFFS_XOFFS_SHIFT 16
// Z Buffer Control (0x00048040)
-#define M2_TE_DBZCNTL_ZFUNCCNTL_MASK 0x0000003f
-#define M2_TE_DBZCNTL_ZPIXOUT_LT 0x00000001
-#define M2_TE_DBZCNTL_ZBUFOUT_LT 0x00000002
-#define M2_TE_DBZCNTL_ZPIXOUT_EQ 0x00000004
-#define M2_TE_DBZCNTL_ZBUFOUT_EQ 0x00000008
-#define M2_TE_DBZCNTL_ZPIXOUT_GT 0x00000010
-#define M2_TE_DBZCNTL_ZBUFOUT_GT 0x00000020
+#define M2_TE_DBZCNTL_ZFUNCCNTL_MASK 0x0000003f
+#define M2_TE_DBZCNTL_ZPIXOUT_LT 0x00000001
+#define M2_TE_DBZCNTL_ZBUFOUT_LT 0x00000002
+#define M2_TE_DBZCNTL_ZPIXOUT_EQ 0x00000004
+#define M2_TE_DBZCNTL_ZBUFOUT_EQ 0x00000008
+#define M2_TE_DBZCNTL_ZPIXOUT_GT 0x00000010
+#define M2_TE_DBZCNTL_ZBUFOUT_GT 0x00000020
// Z Buffer Base Address (0x00048044)
-#define M2_TE_DBZBASEADDR_MASK 0x00ffffff
+#define M2_TE_DBZBASEADDR_MASK 0x00ffffff
// Z Buffer XY Offset (0x00048048)
-#define M2_TE_DBZOFFS_YOFFS_MASK 0x00000fff
-#define M2_TE_DBZOFFS_YOFFS_SHIFT 0
-#define M2_TE_DBZOFFS_XOFFS_MASK 0x0fff0000
-#define M2_TE_DBZOFFS_XOFFS_SHIFT 16
+#define M2_TE_DBZOFFS_YOFFS_MASK 0x00000fff
+#define M2_TE_DBZOFFS_YOFFS_SHIFT 0
+#define M2_TE_DBZOFFS_XOFFS_MASK 0x0fff0000
+#define M2_TE_DBZOFFS_XOFFS_SHIFT 16
// Z Buffer Clip (0x0004804C)
-#define M2_TE_DBZCLIP_YCLIP_MASK 0x000007ff
-#define M2_TE_DBZCLIP_YCLIP_SHIFT 0
-#define M2_TE_DBZCLIP_XCLIP_MASK 0x07ff0000
-#define M2_TE_DBZCLIP_XCLIP_SHIFT 16
+#define M2_TE_DBZCLIP_YCLIP_MASK 0x000007ff
+#define M2_TE_DBZCLIP_YCLIP_SHIFT 0
+#define M2_TE_DBZCLIP_XCLIP_MASK 0x07ff0000
+#define M2_TE_DBZCLIP_XCLIP_SHIFT 16
// SSB/DSB Control (0x00048050)
-#define M2_TE_DBSSBDSBCNTL_DSBSELECT_MASK 0x00000007
-#define M2_TE_DBSSBDSBCNTL_DSBSELECT_SHIFT 0
-#define M2_TE_DBSSBDSBCNTL_DSBSELECT_SSB 0
-#define M2_TE_DBSSBDSBCNTL_DSBSELECT_CONSTANT 1
-#define M2_TE_DBSSBDSBCNTL_DSBSELECT_SRC 2
+#define M2_TE_DBSSBDSBCNTL_DSBSELECT_MASK 0x00000007
+#define M2_TE_DBSSBDSBCNTL_DSBSELECT_SHIFT 0
+#define M2_TE_DBSSBDSBCNTL_DSBSELECT_SSB 0
+#define M2_TE_DBSSBDSBCNTL_DSBSELECT_CONSTANT 1
+#define M2_TE_DBSSBDSBCNTL_DSBSELECT_SRC 2
-#define M2_TE_DBSSBDSBCNTL_DSBCONST 0x00000004
+#define M2_TE_DBSSBDSBCNTL_DSBCONST 0x00000004
// RGB constants (0x00048054)
-#define M2_TE_DBCONSTIN_B_MASK 0x000000ff
-#define M2_TE_DBCONSTIN_B_SHIFT 0
-#define M2_TE_DBCONSTIN_G_MASK 0x0000ff00
-#define M2_TE_DBCONSTIN_G_SHIFT 8
-#define M2_TE_DBCONSTIN_R_MASK 0x00ff0000
-#define M2_TE_DBCONSTIN_R_SHIFT 16
+#define M2_TE_DBCONSTIN_B_MASK 0x000000ff
+#define M2_TE_DBCONSTIN_B_SHIFT 0
+#define M2_TE_DBCONSTIN_G_MASK 0x0000ff00
+#define M2_TE_DBCONSTIN_G_SHIFT 8
+#define M2_TE_DBCONSTIN_R_MASK 0x00ff0000
+#define M2_TE_DBCONSTIN_R_SHIFT 16
// Texture Multiplication Control (0x00048058)
-#define M2_TE_DBTXTMULTCNTL_TXTRJUST 0x00000001
-#define M2_TE_DBTXTMULTCNTL_TXTCOEFCMP 0x00000002
-
-#define M2_TE_DBTXTMULTCNTL_TXTCONSTCNTL_MASK 0x0000000c
-#define M2_TE_DBTXTMULTCNTL_TXTCONSTCNTL_SHIFT 2
-#define M2_TE_DBTXTMULTCNTL_TXTCONSTCNTL_TEXSSB 0
-#define M2_TE_DBTXTMULTCNTL_TXTCONSTCNTL_SRCDSB 1
-
-#define M2_TE_DBTXTMULTCNTL_COEFSEL_MASK 0x00000030
-#define M2_TE_DBTXTMULTCNTL_COEFSEL_SHIFT 4
-#define M2_TE_DBTXTMULTCNTL_COEFSEL_ATI 0
-#define M2_TE_DBTXTMULTCNTL_COEFSEL_ASRC 1
-#define M2_TE_DBTXTMULTCNTL_COEFSEL_CONSTANT 2
-#define M2_TE_DBTXTMULTCNTL_COEFSEL_CSRC 3
-
-#define M2_TE_DBTXTMULTCNTL_INSEL_MASK 0x000000c0
-#define M2_TE_DBTXTMULTCNTL_INSEL_SHIFT 6
-#define M2_TE_DBTXTMULTCNTL_INSEL_CTI 0
-#define M2_TE_DBTXTMULTCNTL_INSEL_CONSTANT 1
-#define M2_TE_DBTXTMULTCNTL_INSEL_COMPSRC 2
-#define M2_TE_DBTXTMULTCNTL_INSEL_ATI 3
+#define M2_TE_DBTXTMULTCNTL_TXTRJUST 0x00000001
+#define M2_TE_DBTXTMULTCNTL_TXTCOEFCMP 0x00000002
+
+#define M2_TE_DBTXTMULTCNTL_TXTCONSTCNTL_MASK 0x0000000c
+#define M2_TE_DBTXTMULTCNTL_TXTCONSTCNTL_SHIFT 2
+#define M2_TE_DBTXTMULTCNTL_TXTCONSTCNTL_TEXSSB 0
+#define M2_TE_DBTXTMULTCNTL_TXTCONSTCNTL_SRCDSB 1
+
+#define M2_TE_DBTXTMULTCNTL_COEFSEL_MASK 0x00000030
+#define M2_TE_DBTXTMULTCNTL_COEFSEL_SHIFT 4
+#define M2_TE_DBTXTMULTCNTL_COEFSEL_ATI 0
+#define M2_TE_DBTXTMULTCNTL_COEFSEL_ASRC 1
+#define M2_TE_DBTXTMULTCNTL_COEFSEL_CONSTANT 2
+#define M2_TE_DBTXTMULTCNTL_COEFSEL_CSRC 3
+
+#define M2_TE_DBTXTMULTCNTL_INSEL_MASK 0x000000c0
+#define M2_TE_DBTXTMULTCNTL_INSEL_SHIFT 6
+#define M2_TE_DBTXTMULTCNTL_INSEL_CTI 0
+#define M2_TE_DBTXTMULTCNTL_INSEL_CONSTANT 1
+#define M2_TE_DBTXTMULTCNTL_INSEL_COMPSRC 2
+#define M2_TE_DBTXTMULTCNTL_INSEL_ATI 3
// Source Multiplication Control (0x00048058)
-#define M2_TE_DBSRCMULTCNTL_SRCRJUST 0x00000001
-#define M2_TE_DBSRCMULTCNTL_SRCCOEFCMP 0x00000002
-
-#define M2_TE_DBSRCMULTCNTL_SRCCONSTCNTL_MASK 0x0000000c
-#define M2_TE_DBSRCMULTCNTL_SRCCONSTCNTL_SHIFT 2
-#define M2_TE_DBSRCMULTCNTL_SRCCONSTCNTL_TEXSSB 0
-#define M2_TE_DBSRCMULTCNTL_SRCCONSTCNTL_SRCDSB 1
-
-#define M2_TE_DBSRCMULTCNTL_COEFSEL_MASK 0x00000030
-#define M2_TE_DBSRCMULTCNTL_COEFSEL_SHIFT 4
-#define M2_TE_DBSRCMULTCNTL_COEFSEL_ATI 0
-#define M2_TE_DBSRCMULTCNTL_COEFSEL_ASRC 1
-#define M2_TE_DBSRCMULTCNTL_COEFSEL_CONSTANT 2
-#define M2_TE_DBSRCMULTCNTL_COEFSEL_CTI 3
-
-#define M2_TE_DBSRCMULTCNTL_INSEL_MASK 0x000000c0
-#define M2_TE_DBSRCMULTCNTL_INSEL_SHIFT 6
-#define M2_TE_DBSRCMULTCNTL_INSEL_SRC 0
-#define M2_TE_DBSRCMULTCNTL_INSEL_CONSTANT 1
-#define M2_TE_DBSRCMULTCNTL_INSEL_COMPCTI 2
-#define M2_TE_DBSRCMULTCNTL_INSEL_TEXALPHA 3
+#define M2_TE_DBSRCMULTCNTL_SRCRJUST 0x00000001
+#define M2_TE_DBSRCMULTCNTL_SRCCOEFCMP 0x00000002
+
+#define M2_TE_DBSRCMULTCNTL_SRCCONSTCNTL_MASK 0x0000000c
+#define M2_TE_DBSRCMULTCNTL_SRCCONSTCNTL_SHIFT 2
+#define M2_TE_DBSRCMULTCNTL_SRCCONSTCNTL_TEXSSB 0
+#define M2_TE_DBSRCMULTCNTL_SRCCONSTCNTL_SRCDSB 1
+
+#define M2_TE_DBSRCMULTCNTL_COEFSEL_MASK 0x00000030
+#define M2_TE_DBSRCMULTCNTL_COEFSEL_SHIFT 4
+#define M2_TE_DBSRCMULTCNTL_COEFSEL_ATI 0
+#define M2_TE_DBSRCMULTCNTL_COEFSEL_ASRC 1
+#define M2_TE_DBSRCMULTCNTL_COEFSEL_CONSTANT 2
+#define M2_TE_DBSRCMULTCNTL_COEFSEL_CTI 3
+
+#define M2_TE_DBSRCMULTCNTL_INSEL_MASK 0x000000c0
+#define M2_TE_DBSRCMULTCNTL_INSEL_SHIFT 6
+#define M2_TE_DBSRCMULTCNTL_INSEL_SRC 0
+#define M2_TE_DBSRCMULTCNTL_INSEL_CONSTANT 1
+#define M2_TE_DBSRCMULTCNTL_INSEL_COMPCTI 2
+#define M2_TE_DBSRCMULTCNTL_INSEL_TEXALPHA 3
// ALU Control (0x00048070)
-#define M2_TE_DBALUCNTL_FINALDIVIDE_MASK 0x00000007
-#define M2_TE_DBALUCNTL_FINALDIVIDE_SHIFT 0
+#define M2_TE_DBALUCNTL_FINALDIVIDE_MASK 0x00000007
+#define M2_TE_DBALUCNTL_FINALDIVIDE_SHIFT 0
-#define M2_TE_DBALUCNTL_ALUOP_MASK 0x000000f8
-#define M2_TE_DBALUCNTL_ALUOP_SHIFT 5
+#define M2_TE_DBALUCNTL_ALUOP_MASK 0x000000f8
+#define M2_TE_DBALUCNTL_ALUOP_SHIFT 5
// Source Alpha Control (0x00048074)
-#define M2_TE_DBDSTACNTL_ADESTSEL_MASK 0x00000003
-#define M2_TE_DBDSTACNTL_ADESTSEL_SHIFT 0
-#define M2_TE_DBDSTACNTL_ADESTCONSTCNTL_MASK 0x0000000c
-#define M2_TE_DBDSTACNTL_ADESTCONSTCNTL_SHIFT 2
-
-#define M2_TE_DBDSTALPHACONST_CONST1_MASK 0x000000ff
-#define M2_TE_DBDSTALPHACONST_CONST1_SHIFT 0
-#define M2_TE_DBDSTALPHACONST_CONST0_MASK 0x00ff0000
-#define M2_TE_DBDSTALPHACONST_CONST0_SHIFT 16
-
-#define M2_TE_DBSSBDSBCNTL_DSBSEL_MASK 0x00000003
-#define M2_TE_DBSSBDSBCNTL_DSBSEL_SHIFT 0
-#define M2_TE_DBSSBDSBCNTL_DSBCONST_MASK 0x00000004
-#define M2_TE_DBSSBDSBCNTL_DSBCONST_SHIFT 2
-
-#endif // MACHINE_3DOM2_DEFS_H \ No newline at end of file
+#define M2_TE_DBDSTACNTL_ADESTSEL_MASK 0x00000003
+#define M2_TE_DBDSTACNTL_ADESTSEL_SHIFT 0
+#define M2_TE_DBDSTACNTL_ADESTCONSTCNTL_MASK 0x0000000c
+#define M2_TE_DBDSTACNTL_ADESTCONSTCNTL_SHIFT 2
+
+#define M2_TE_DBDSTALPHACONST_CONST1_MASK 0x000000ff
+#define M2_TE_DBDSTALPHACONST_CONST1_SHIFT 0
+#define M2_TE_DBDSTALPHACONST_CONST0_MASK 0x00ff0000
+#define M2_TE_DBDSTALPHACONST_CONST0_SHIFT 16
+
+#define M2_TE_DBSSBDSBCNTL_DSBSEL_MASK 0x00000003
+#define M2_TE_DBSSBDSBCNTL_DSBSEL_SHIFT 0
+#define M2_TE_DBSSBDSBCNTL_DSBCONST_MASK 0x00000004
+#define M2_TE_DBSSBDSBCNTL_DSBCONST_SHIFT 2
+
+#endif // MACHINE_3DOM2_DEFS_H
diff --git a/src/mame/machine/3dom2_te.cpp b/src/mame/machine/3dom2_te.cpp
index 55e430b877e..9757e966da4 100644
--- a/src/mame/machine/3dom2_te.cpp
+++ b/src/mame/machine/3dom2_te.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Philip Bennett
/***************************************************************************
- 3DO M2 BDA Triangle Engine
+ 3DO M2 BDA Triangle Engine
***************************************************************************/
@@ -10,19 +10,19 @@
#include "3dom2.h"
/*
- TODO:
+ TODO:
- VTX_FLAGS do not get passed to the TMAPPER: Should use master control
- bits to disable shading and texturing.
+ VTX_FLAGS do not get passed to the TMAPPER: Should use master control
+ bits to disable shading and texturing.
- - Evil Night attract mode sky is missing. Why?
- - What is 1/w when 0?
- - What do we do about RL flat-topped triangles?
- - Heat of 11 color check has dodgy pixels <- HAS IT?
+ - Evil Night attract mode sky is missing. Why?
+ - What is 1/w when 0?
+ - What do we do about RL flat-topped triangles?
+ - Heat of 11 color check has dodgy pixels <- HAS IT?
- Polystar blending is incorrect (intro)
*/
-#define TEST_TIMING 1
+#define TEST_TIMING 1
#if TEST_TIMING
enum
@@ -51,20 +51,20 @@ DEFINE_DEVICE_TYPE(M2_TE, m2_te_device, "m2te", "BDA Triangle Engine")
-//static const uint32_t fixed_bits = 23;
+//static const uint32_t fixed_bits = 23;
-static const uint32_t xy_bits = 11;
-static const uint32_t color_bits = 8;
-static const uint32_t text_bits[] = { 10, 7, 4, 1 };
-static const int32_t depth_bits[] = { 0, -3, -6, -9 };
+static const uint32_t xy_bits = 11;
+static const uint32_t color_bits = 8;
+static const uint32_t text_bits[] = { 10, 7, 4, 1 };
+static const int32_t depth_bits[] = { 0, -3, -6, -9 };
// For right-aligning
-static const uint32_t xy_rshift = 12;
-static const uint32_t color_rshift = 4;
+static const uint32_t xy_rshift = 12;
+static const uint32_t color_rshift = 4;
// 11.0 format
-static const uint32_t xy_one = 1;
+static const uint32_t xy_one = 1;
/***************************************************************************
@@ -79,40 +79,40 @@ static const uint32_t xy_one = 1;
//-------------------------------------------------
// Triangle Engine Master Mode
-#define TEMASTER_MODE_RESET 0x00000001
-#define TEMASTER_MODE_DTEXT 0x00000002
-#define TEMASTER_MODE_DSHADE 0x00000004
-#define TEMASTER_MODE_DBLEND 0x00000008
-#define TEMASTER_MODE_DZBUF 0x00000010
-#define TEMASTER_MODE_DDITH 0x00000020
+#define TEMASTER_MODE_RESET 0x00000001
+#define TEMASTER_MODE_DTEXT 0x00000002
+#define TEMASTER_MODE_DSHADE 0x00000004
+#define TEMASTER_MODE_DBLEND 0x00000008
+#define TEMASTER_MODE_DZBUF 0x00000010
+#define TEMASTER_MODE_DDITH 0x00000020
// Triangle Engine Immediate Control
-#define TEICNTL_INT 0x00000001
-#define TEICNTL_STEP 0x00000002
-#define TEICNTL_STPL 0x00000004
-#define TEICNTL_STPI 0x00000008
-#define TEICNTL_RSTRT 0x00000010
-#define TEICNTL_STRT 0x00000020
-
-#define TEDCNTL_TLD 0x00000001
-#define TEDCNTL_JA 0x00000002
-#define TEDCNTL_JR 0x00000004
-#define TEDCNTL_INT 0x00000008
-#define TEDCNTL_PSE 0x00000010
-#define TEDCNTL_SYNC 0x00000020
-
-#define INTSTAT_DEFERRED_INSTR 0x00000100
-#define INTSTAT_IMMEDIATE_INSTR 0x00000200
-#define INTSTAT_LIST_END 0x00000400
-#define INTSTAT_WINDOW_CLIP 0x00000800
-#define INTSTAT_SPECIAL_INSTR 0x00001000
-#define INTSTAT_UNIMPLEMENTED_INSTR 0x00002000
-#define INTSTAT_SUPERVISOR 0x00004000
-#define INTSTAT_ANY_RENDER 0x00008000
-#define INTSTAT_Z_FUNC 0x00010000
-#define INTSTAT_ALU_STATUS 0x00020000
-#define INTSTAT_FB_CLIP 0x00040000
-#define INTSTAT_IMMEDIATE 0x00080000
+#define TEICNTL_INT 0x00000001
+#define TEICNTL_STEP 0x00000002
+#define TEICNTL_STPL 0x00000004
+#define TEICNTL_STPI 0x00000008
+#define TEICNTL_RSTRT 0x00000010
+#define TEICNTL_STRT 0x00000020
+
+#define TEDCNTL_TLD 0x00000001
+#define TEDCNTL_JA 0x00000002
+#define TEDCNTL_JR 0x00000004
+#define TEDCNTL_INT 0x00000008
+#define TEDCNTL_PSE 0x00000010
+#define TEDCNTL_SYNC 0x00000020
+
+#define INTSTAT_DEFERRED_INSTR 0x00000100
+#define INTSTAT_IMMEDIATE_INSTR 0x00000200
+#define INTSTAT_LIST_END 0x00000400
+#define INTSTAT_WINDOW_CLIP 0x00000800
+#define INTSTAT_SPECIAL_INSTR 0x00001000
+#define INTSTAT_UNIMPLEMENTED_INSTR 0x00002000
+#define INTSTAT_SUPERVISOR 0x00004000
+#define INTSTAT_ANY_RENDER 0x00008000
+#define INTSTAT_Z_FUNC 0x00010000
+#define INTSTAT_ALU_STATUS 0x00020000
+#define INTSTAT_FB_CLIP 0x00040000
+#define INTSTAT_IMMEDIATE 0x00080000
// IWP
// IRP
@@ -127,16 +127,16 @@ static const uint32_t xy_one = 1;
//-------------------------------------------------
// Vertex State
-#define VERTEXSTATE_TSORT_MASK 0x00000007
-#define VERTEXSTATE_TSORT_OMN 0x00000001
-#define VERTEXSTATE_TSORT_MNO 0x00000002
-#define VERTEXSTATE_TSORT_ONM 0x00000003
-#define VERTEXSTATE_TSORT_NOM 0x00000004
-#define VERTEXSTATE_TSORT_MON 0x00000005
-#define VERTEXSTATE_TSORT_NMO 0x00000006
+#define VERTEXSTATE_TSORT_MASK 0x00000007
+#define VERTEXSTATE_TSORT_OMN 0x00000001
+#define VERTEXSTATE_TSORT_MNO 0x00000002
+#define VERTEXSTATE_TSORT_ONM 0x00000003
+#define VERTEXSTATE_TSORT_NOM 0x00000004
+#define VERTEXSTATE_TSORT_MON 0x00000005
+#define VERTEXSTATE_TSORT_NMO 0x00000006
-#define VERTEXSTATE_VCNT_SHIFT 3
-#define VERTEXSTATE_VCNT_MASK 0x00000018
+#define VERTEXSTATE_VCNT_SHIFT 3
+#define VERTEXSTATE_VCNT_MASK 0x00000018
//-------------------------------------------------
@@ -144,9 +144,9 @@ static const uint32_t xy_one = 1;
//-------------------------------------------------
// Edge and Span Walker Control
-#define ESCNTL_DSPOFF 0x00000001
-#define ESCNTL_DUSCAN 0x00000002
-#define ESCNTL_PERSPECTIVEOFF 0x00000004
+#define ESCNTL_DSPOFF 0x00000001
+#define ESCNTL_DUSCAN 0x00000002
+#define ESCNTL_PERSPECTIVEOFF 0x00000004
//-------------------------------------------------
@@ -154,148 +154,148 @@ static const uint32_t xy_one = 1;
//-------------------------------------------------
// Texture Mapper Master Control (0x00046400)
-#define TXTCNTL_MMDMA_TRAM_ON 0x00000004
-#define TXTCNTL_MMDMA_PIP_ON 0x00000008
-#define TXTCNTL_SNOOP_ON 0x00000020
+#define TXTCNTL_MMDMA_TRAM_ON 0x00000004
+#define TXTCNTL_MMDMA_PIP_ON 0x00000008
+#define TXTCNTL_SNOOP_ON 0x00000020
// Texture Load Control (0x00046404)
-#define TXTLDCNTL_SRCBITOFFS 0x00000007
-#define TXTLDCNTL_LDMODE_MASK 0x00000300
-#define TXTLDCNTL_LDMODE_TEXLOAD 0x00000000
-#define TXTLDCNTL_LDMODE_MMDMA 0x00000100
-#define TXTLDCNTL_LDMODE_PIPLOAD 0x00000200
-#define TXTLDCNTL_LDMODE_RESERVED 0x00000300
-#define TXTLDCNTL_COMPRESSED 0x00000400
+#define TXTLDCNTL_SRCBITOFFS 0x00000007
+#define TXTLDCNTL_LDMODE_MASK 0x00000300
+#define TXTLDCNTL_LDMODE_TEXLOAD 0x00000000
+#define TXTLDCNTL_LDMODE_MMDMA 0x00000100
+#define TXTLDCNTL_LDMODE_PIPLOAD 0x00000200
+#define TXTLDCNTL_LDMODE_RESERVED 0x00000300
+#define TXTLDCNTL_COMPRESSED 0x00000400
// Address Control (0x00046408)
-#define TXTADDRCNTL_LODMAX_MASK 0x0000000f
-#define TXTADDRCNTL_FILTERSEL_MASK 0x00000003
-#define TXTADDRCNTL_FILTERSEL_POINT 0x00000000
-#define TXTADDRCNTL_FILTERSEL_LINEAR 0x00000001
-#define TXTADDRCNTL_FILTERSEL_BILINEAR 0x00000002
-#define TXTADDRCNTL_FILTERSEL_QUASITRI 0x00000003
-#define TXTADDRCNTL_R12FILTERSEL_SHIFT 4
-#define TXTADDRCNTL_R3FILTERSEL_SHIFT 7
-#define TXTADDRCNTL_R45FILTERSEL_SHIFT 10
-#define TXTADDRCNTL_LOOKUP_EN 0x00002000
+#define TXTADDRCNTL_LODMAX_MASK 0x0000000f
+#define TXTADDRCNTL_FILTERSEL_MASK 0x00000003
+#define TXTADDRCNTL_FILTERSEL_POINT 0x00000000
+#define TXTADDRCNTL_FILTERSEL_LINEAR 0x00000001
+#define TXTADDRCNTL_FILTERSEL_BILINEAR 0x00000002
+#define TXTADDRCNTL_FILTERSEL_QUASITRI 0x00000003
+#define TXTADDRCNTL_R12FILTERSEL_SHIFT 4
+#define TXTADDRCNTL_R3FILTERSEL_SHIFT 7
+#define TXTADDRCNTL_R45FILTERSEL_SHIFT 10
+#define TXTADDRCNTL_LOOKUP_EN 0x00002000
// PIP Control (0x0004640C)
-#define TXTPIPCNTL_INDEX_OFFSET 0x000000ff
-#define TXTPIPCNTL_COLORSEL_MASK 0x00000700
-#define TXTPIPCNTL_COLORSEL_SHIFT 8
-#define TXTPIPCNTL_ALPHASEL_MASK 0x00003800
-#define TXTPIPCNTL_ALPHASEL_SHIFT 11
-#define TXTPIPCNTL_SSBSEL_MASK 0x0001c000
-#define TXTPIPCNTL_SSBSEL_SHIFT 14
-
-#define TXTPIPCNTL_SEL_CONSTANT 0
-#define TXTPIPCNTL_SEL_TRAM 1
-#define TXTPIPCNTL_SEL_PIP 2
+#define TXTPIPCNTL_INDEX_OFFSET 0x000000ff
+#define TXTPIPCNTL_COLORSEL_MASK 0x00000700
+#define TXTPIPCNTL_COLORSEL_SHIFT 8
+#define TXTPIPCNTL_ALPHASEL_MASK 0x00003800
+#define TXTPIPCNTL_ALPHASEL_SHIFT 11
+#define TXTPIPCNTL_SSBSEL_MASK 0x0001c000
+#define TXTPIPCNTL_SSBSEL_SHIFT 14
+
+#define TXTPIPCNTL_SEL_CONSTANT 0
+#define TXTPIPCNTL_SEL_TRAM 1
+#define TXTPIPCNTL_SEL_PIP 2
// Texture Application Control (0x00046410)
-#define TXTTABCNTL_C_ASEL_MASK 0x00000007
-#define TXTTABCNTL_C_ASEL_SHIFT 0
-#define TXTTABCNTL_C_BSEL_MASK 0x00000038
-#define TXTTABCNTL_C_BSEL_SHIFT 3
-#define TXTTABCNTL_C_TSEL_MASK 0x000001c0
-#define TXTTABCNTL_C_TSEL_SHIFT 6
-
-#define TXTTABCNTL_C_ABTSEL_AITER 0
-#define TXTTABCNTL_C_ABTSEL_CITER 1
-#define TXTTABCNTL_C_ABTSEL_AT 2
-#define TXTTABCNTL_C_ABTSEL_CT 3
-#define TXTTABCNTL_C_ABTSEL_ACONST 4
-#define TXTTABCNTL_C_ABTSEL_CCONST 5
-
-#define TXTTABCNTL_C_OSEL_MASK 0x00000600
-#define TXTTABCNTL_C_OSEL_SHIFT 9
-
-#define TXTTABCNTL_CO_SEL_CITER 0
-#define TXTTABCNTL_CO_SEL_CT 1
-#define TXTTABCNTL_CO_SEL_BLEND 2
-#define TXTTABCNTL_CO_SEL_RESERVED 3
-
-#define TXTTABCNTL_A_ASEL_MASK 0x00001800
-#define TXTTABCNTL_A_ASEL_SHIFT 11
-#define TXTTABCNTL_A_BSEL_MASK 0x00006000
-#define TXTTABCNTL_A_BSEL_SHIFT 13
-
-#define TXTTABCNTL_A_ABSEL_AITER 0
-#define TXTTABCNTL_A_ABSEL_AT 1
-#define TXTTABCNTL_A_ABSEL_ACONST 2
-
-#define TXTTABCNTL_A_OSEL_MASK 0x00018000
-#define TXTTABCNTL_A_OSEL_SHIFT 15
-
-#define TXTTABCNTL_AO_SEL_AITER 0
-#define TXTTABCNTL_AO_SEL_AT 1
-#define TXTTABCNTL_AO_SEL_BLEND 2
-#define TXTTABCNTL_AO_SEL_RESERVED 3
-
-#define TXTTABCNTL_BLENDOP_MASK 0x00010000
-#define TXTTABCNTL_BLENDOP_SHIFT 16
-#define TXTTABCNTL_BLENDOP_LERP 0
-#define TXTTABCNTL_BLENDOP_MULT 1
+#define TXTTABCNTL_C_ASEL_MASK 0x00000007
+#define TXTTABCNTL_C_ASEL_SHIFT 0
+#define TXTTABCNTL_C_BSEL_MASK 0x00000038
+#define TXTTABCNTL_C_BSEL_SHIFT 3
+#define TXTTABCNTL_C_TSEL_MASK 0x000001c0
+#define TXTTABCNTL_C_TSEL_SHIFT 6
+
+#define TXTTABCNTL_C_ABTSEL_AITER 0
+#define TXTTABCNTL_C_ABTSEL_CITER 1
+#define TXTTABCNTL_C_ABTSEL_AT 2
+#define TXTTABCNTL_C_ABTSEL_CT 3
+#define TXTTABCNTL_C_ABTSEL_ACONST 4
+#define TXTTABCNTL_C_ABTSEL_CCONST 5
+
+#define TXTTABCNTL_C_OSEL_MASK 0x00000600
+#define TXTTABCNTL_C_OSEL_SHIFT 9
+
+#define TXTTABCNTL_CO_SEL_CITER 0
+#define TXTTABCNTL_CO_SEL_CT 1
+#define TXTTABCNTL_CO_SEL_BLEND 2
+#define TXTTABCNTL_CO_SEL_RESERVED 3
+
+#define TXTTABCNTL_A_ASEL_MASK 0x00001800
+#define TXTTABCNTL_A_ASEL_SHIFT 11
+#define TXTTABCNTL_A_BSEL_MASK 0x00006000
+#define TXTTABCNTL_A_BSEL_SHIFT 13
+
+#define TXTTABCNTL_A_ABSEL_AITER 0
+#define TXTTABCNTL_A_ABSEL_AT 1
+#define TXTTABCNTL_A_ABSEL_ACONST 2
+
+#define TXTTABCNTL_A_OSEL_MASK 0x00018000
+#define TXTTABCNTL_A_OSEL_SHIFT 15
+
+#define TXTTABCNTL_AO_SEL_AITER 0
+#define TXTTABCNTL_AO_SEL_AT 1
+#define TXTTABCNTL_AO_SEL_BLEND 2
+#define TXTTABCNTL_AO_SEL_RESERVED 3
+
+#define TXTTABCNTL_BLENDOP_MASK 0x00010000
+#define TXTTABCNTL_BLENDOP_SHIFT 16
+#define TXTTABCNTL_BLENDOP_LERP 0
+#define TXTTABCNTL_BLENDOP_MULT 1
// TAB Constants
-#define TXTTABCONST_BLUE 0x000000ff
-#define TXTTABCONST_BLUE_SHIFT 0
-#define TXTTABCONST_GREEN 0x0000ff00
-#define TXTTABCONST_GREEN_SHIFT 8
-#define TXTTABCONST_RED 0x00ff0000
-#define TXTTABCONST_RED_SHIFT 16
-#define TXTTABCONST_ALPHA 0x7f000000
-#define TXTTABCONST_ALPHA_SHIFT 24
-#define TXTTABCONST_SSB 0x80000000
+#define TXTTABCONST_BLUE 0x000000ff
+#define TXTTABCONST_BLUE_SHIFT 0
+#define TXTTABCONST_GREEN 0x0000ff00
+#define TXTTABCONST_GREEN_SHIFT 8
+#define TXTTABCONST_RED 0x00ff0000
+#define TXTTABCONST_RED_SHIFT 16
+#define TXTTABCONST_ALPHA 0x7f000000
+#define TXTTABCONST_ALPHA_SHIFT 24
+#define TXTTABCONST_SSB 0x80000000
// Texture Loader Destination Base (0x00046414)
-#define TXTLDDSTBASE_ADDR 0x00003ffc
+#define TXTLDDSTBASE_ADDR 0x00003ffc
// Texture Lod Base 0 (0x00046414)
// Texture Lod Base 1 (0x00046418)
// Texture Lod Base 2 (0x0004641C)
// Texture Lod Base 3 (0x00046420)
-#define TXTLODBASE_MASK 0x00003ffc
+#define TXTLODBASE_MASK 0x00003ffc
// Texture Loader Source Base (0x00046424)
-#define TXTLDSRCBASE_ADDR 0x00003fff
+#define TXTLDSRCBASE_ADDR 0x00003fff
// Texture Loader Counts (0x00046428)
-#define TXTLDBYTECNT_COUNT 0x0fffffff
-#define TXTLDROWCNT_COUNT 0x0fffffff
-#define TXTLDTEXCNT_COUNT 0x0fffffff
+#define TXTLDBYTECNT_COUNT 0x0fffffff
+#define TXTLDROWCNT_COUNT 0x0fffffff
+#define TXTLDTEXCNT_COUNT 0x0fffffff
// Texture Loader Width (0x00046428)
-#define TxTLDWIDTH_SRCROW 0x0000ffff
-#define TxTLDWIDTH_DSTROW_SHIFT 16
-#define TxTLDWIDTH_DSTROW 0xffff0000
+#define TxTLDWIDTH_SRCROW 0x0000ffff
+#define TxTLDWIDTH_DSTROW_SHIFT 16
+#define TxTLDWIDTH_DSTROW 0xffff0000
// Texture Size (0x0004642C)
-#define TXTUVMAX_VMAX_MASK 0x000003ff
-#define TXTUVMAX_VMAX_SHIFT 0
-#define TXTUVMAX_UMAX_MASK 0x03ff0000
-#define TXTUVMAX_UMAX_SHIFT 16
+#define TXTUVMAX_VMAX_MASK 0x000003ff
+#define TXTUVMAX_VMAX_SHIFT 0
+#define TXTUVMAX_UMAX_MASK 0x03ff0000
+#define TXTUVMAX_UMAX_SHIFT 16
// Texture Mask (0x00046430)
-#define TXTUVMASK_VMASK_MASK 0x000003ff
-#define TXTUVMASK_VMASK_SHIFT 0
-#define TXTUVMASK_UMASK_MASK 0x03ff0000
-#define TXTUVMASK_UMASK_SHIFT 16
+#define TXTUVMASK_VMASK_MASK 0x000003ff
+#define TXTUVMASK_VMASK_SHIFT 0
+#define TXTUVMASK_UMASK_MASK 0x03ff0000
+#define TXTUVMASK_UMASK_SHIFT 16
// TRAM Format (0x0004643C)
// TODO: Expansion formats
-#define TXTEXPFORM_CDEPTH_MASK 0x0000000f
-#define TXTEXPFORM_CDEPTH_SHIFT 0
-#define TXTEXPFORM_IDEPTH_MASK 0x0000000f
-#define TXTEXPFORM_IDEPTH_SHIFT 0
-#define TXTEXPFORM_ADEPTH_MASK 0x000000f0
-#define TXTEXPFORM_ADEPTH_SHIFT 4
-#define TXTEXPFORM_TRANSPARENT 0x00000100
-#define TXTEXPFORM_SSBON 0x00000200
-#define TXTEXPFORM_COLORON 0x00000400
-#define TXTEXPFORM_INDEXON 0x00000400
-#define TXTEXPFORM_ALPHAON 0x00000800
-#define TXTEXPFORM_LITERAL 0x00001000
+#define TXTEXPFORM_CDEPTH_MASK 0x0000000f
+#define TXTEXPFORM_CDEPTH_SHIFT 0
+#define TXTEXPFORM_IDEPTH_MASK 0x0000000f
+#define TXTEXPFORM_IDEPTH_SHIFT 0
+#define TXTEXPFORM_ADEPTH_MASK 0x000000f0
+#define TXTEXPFORM_ADEPTH_SHIFT 4
+#define TXTEXPFORM_TRANSPARENT 0x00000100
+#define TXTEXPFORM_SSBON 0x00000200
+#define TXTEXPFORM_COLORON 0x00000400
+#define TXTEXPFORM_INDEXON 0x00000400
+#define TXTEXPFORM_ALPHAON 0x00000800
+#define TXTEXPFORM_LITERAL 0x00001000
// Format Registers
@@ -306,204 +306,204 @@ static const uint32_t xy_one = 1;
//-------------------------------------------------
// Snoop (0x0048000)
-#define DBSNOOP_DESTWRSNOOP 0x00000001
-#define DBSNOOP_SRCRDSNOOP 0x00000002
-#define DBSNOOP_ZWRSNOOP 0x00000004
-#define DBSNOOP_ZRDSNOOP 0x00000008
+#define DBSNOOP_DESTWRSNOOP 0x00000001
+#define DBSNOOP_SRCRDSNOOP 0x00000002
+#define DBSNOOP_ZWRSNOOP 0x00000004
+#define DBSNOOP_ZRDSNOOP 0x00000008
// Supervisor General Control (0x0048004)
-#define DBSUPERGENCTL_DESTOUTEN 0x00000001
-#define DBSUPERGENCTL_DESTWR16BEN 0x00000002
-#define DBSUPERGENCTL_ZWR16BEN 0x00000004
+#define DBSUPERGENCTL_DESTOUTEN 0x00000001
+#define DBSUPERGENCTL_DESTWR16BEN 0x00000002
+#define DBSUPERGENCTL_ZWR16BEN 0x00000004
// User General Control (0x0048008)
-#define DBUSERGENCTL_DESTOUT_MASK 0x0000000f
-#define DBUSERGENCTL_DITHEREN 0x00000010
-#define DBUSERGENCTL_SRCINEN 0x00000020
-#define DBUSERGENCTL_BLENDEN 0x00000040
-#define DBUSERGENCTL_WCLIPOUTEN 0x00000080
-#define DBUSERGENCTL_WCLIPINEN 0x00000100
-#define DBUSERGENCTL_ZOUTEN 0x00000200
-#define DBUSERGENCTL_ZBUFEN 0x00000400
+#define DBUSERGENCTL_DESTOUT_MASK 0x0000000f
+#define DBUSERGENCTL_DITHEREN 0x00000010
+#define DBUSERGENCTL_SRCINEN 0x00000020
+#define DBUSERGENCTL_BLENDEN 0x00000040
+#define DBUSERGENCTL_WCLIPOUTEN 0x00000080
+#define DBUSERGENCTL_WCLIPINEN 0x00000100
+#define DBUSERGENCTL_ZOUTEN 0x00000200
+#define DBUSERGENCTL_ZBUFEN 0x00000400
// Discard Control (0x004800C)
-#define DBDISCARDCTL_ADISEN 0x00000001
-#define DBDISCARDCTL_RGBDISEN 0x00000002
-#define DBDISCARDCTL_SSBDISEN 0x00000004
-#define DBDISCARDCTL_ZCLIPDISEN 0x00000008
+#define DBDISCARDCTL_ADISEN 0x00000001
+#define DBDISCARDCTL_RGBDISEN 0x00000002
+#define DBDISCARDCTL_SSBDISEN 0x00000004
+#define DBDISCARDCTL_ZCLIPDISEN 0x00000008
// Status (0x0048010)
-#define DBSTATUS_ANYREND 0x00000001
-#define DBSTATUS_ZFUNC_GT 0x00000002
-#define DBSTATUS_ZFUNC_EQ 0x00000004
-#define DBSTATUS_ZFUNC_LT 0x00000008
-#define DBSTATUS_ALUSTAT_BLUE_GT 0x00000010
-#define DBSTATUS_ALUSTAT_BLUE_EQ 0x00000020
-#define DBSTATUS_ALUSTAT_BLUE_LT 0x00000040
-#define DBSTATUS_ALUSTAT_GREEN_GT 0x00000080
-#define DBSTATUS_ALUSTAT_GREEN_EQ 0x00000100
-#define DBSTATUS_ALUSTAT_GREEN_LT 0x00000200
-#define DBSTATUS_ALUSTAT_RED_GT 0x00000400
-#define DBSTATUS_ALUSTAT_RED_EQ 0x00000800
-#define DBSTATUS_ALUSTAT_RED_LT 0x00001000
-#define DBSTATUS_ZCLIP 0x00002000
-#define DBSTATUS_WINCLIP 0x00004000
-#define DBSTATUS_FBCLIP 0x00008000
+#define DBSTATUS_ANYREND 0x00000001
+#define DBSTATUS_ZFUNC_GT 0x00000002
+#define DBSTATUS_ZFUNC_EQ 0x00000004
+#define DBSTATUS_ZFUNC_LT 0x00000008
+#define DBSTATUS_ALUSTAT_BLUE_GT 0x00000010
+#define DBSTATUS_ALUSTAT_BLUE_EQ 0x00000020
+#define DBSTATUS_ALUSTAT_BLUE_LT 0x00000040
+#define DBSTATUS_ALUSTAT_GREEN_GT 0x00000080
+#define DBSTATUS_ALUSTAT_GREEN_EQ 0x00000100
+#define DBSTATUS_ALUSTAT_GREEN_LT 0x00000200
+#define DBSTATUS_ALUSTAT_RED_GT 0x00000400
+#define DBSTATUS_ALUSTAT_RED_EQ 0x00000800
+#define DBSTATUS_ALUSTAT_RED_LT 0x00001000
+#define DBSTATUS_ZCLIP 0x00002000
+#define DBSTATUS_WINCLIP 0x00004000
+#define DBSTATUS_FBCLIP 0x00008000
// Interrupt Control (0x00048014)
-#define DBINTCNTL_ZFUNCSTATINTEN_MASK 0x00000003
-#define DBINTCNTL_ZFUNCSTATINTEN_MASK 0x00000003
+#define DBINTCNTL_ZFUNCSTATINTEN_MASK 0x00000003
+#define DBINTCNTL_ZFUNCSTATINTEN_MASK 0x00000003
// Framebuffer XY Clip Control (0x00048018)
-#define DBFBCLIP_YFBCLIP_MASK 0x000007ff
-#define DBFBCLIP_YFBCLIP_SHIFT 0
-#define DBFBCLIP_XFBCLIP_MASK 0x07ff0000
-#define DBFBCLIP_XFBCLIP_SHIFT 16
+#define DBFBCLIP_YFBCLIP_MASK 0x000007ff
+#define DBFBCLIP_YFBCLIP_SHIFT 0
+#define DBFBCLIP_XFBCLIP_MASK 0x07ff0000
+#define DBFBCLIP_XFBCLIP_SHIFT 16
// Window X Clip Control (0x0004801C)
-#define DBFBXWINCLIP_XMAX_MASK 0x000007ff
-#define DBFBXWINCLIP_XMAX_SHIFT 0
-#define DBFBXWINCLIP_XMIN_MASK 0x07ff0000
-#define DBFBXWINCLIP_XMIN_SHIFT 16
+#define DBFBXWINCLIP_XMAX_MASK 0x000007ff
+#define DBFBXWINCLIP_XMAX_SHIFT 0
+#define DBFBXWINCLIP_XMIN_MASK 0x07ff0000
+#define DBFBXWINCLIP_XMIN_SHIFT 16
// Window Y Clip Control (0x00048020)
-#define DBFBYWINCLIP_YMAX_MASK 0x000007ff
-#define DBFBYWINCLIP_YMAX_SHIFT 0
-#define DBFBYWINCLIP_YMIN_MASK 0x07ff0000
-#define DBFBYWINCLIP_YMIN_SHIFT 16
+#define DBFBYWINCLIP_YMAX_MASK 0x000007ff
+#define DBFBYWINCLIP_YMAX_SHIFT 0
+#define DBFBYWINCLIP_YMIN_MASK 0x07ff0000
+#define DBFBYWINCLIP_YMIN_SHIFT 16
// Destination Write Control (0x0048024)
-#define DBDESTCNTL_32BPP 0x00000001
+#define DBDESTCNTL_32BPP 0x00000001
// Destination Write Base Address (0x0048028)
// Destination X Stride (0x004802C)
-#define DBDEST_XSTRIDE 0x000007ff
+#define DBDEST_XSTRIDE 0x000007ff
// Source Read Control (0x00048030)
-#define DBSRCCNTL_32BPP 0x00000001
-#define DBSRCCNTL_MSBREP 0x00000002
+#define DBSRCCNTL_32BPP 0x00000001
+#define DBSRCCNTL_MSBREP 0x00000002
// Source Read Base Address (0x00048034)
// Source X Stride (0x00048038)
-#define DBSRCXSTRIDE 0x000007ff
+#define DBSRCXSTRIDE 0x000007ff
// Source XY Offset (0x0004803C)
-#define DBSRCOFFS_YOFFS_MASK 0x00000fff
-#define DBSRCOFFS_YOFFS_SHIFT 0
-#define DBSRCOFFS_XOFFS_MASK 0x0fff0000
-#define DBSRCOFFS_XOFFS_SHIFT 16
+#define DBSRCOFFS_YOFFS_MASK 0x00000fff
+#define DBSRCOFFS_YOFFS_SHIFT 0
+#define DBSRCOFFS_XOFFS_MASK 0x0fff0000
+#define DBSRCOFFS_XOFFS_SHIFT 16
// Z Buffer Control (0x00048040)
-#define DBZCNTL_ZFUNCCNTL_MASK 0x0000003f
-#define DBZCNTL_ZPIXOUT_LT 0x00000001
-#define DBZCNTL_ZBUFOUT_LT 0x00000002
-#define DBZCNTL_ZPIXOUT_EQ 0x00000004
-#define DBZCNTL_ZBUFOUT_EQ 0x00000008
-#define DBZCNTL_ZPIXOUT_GT 0x00000010
-#define DBZCNTL_ZBUFOUT_GT 0x00000020
+#define DBZCNTL_ZFUNCCNTL_MASK 0x0000003f
+#define DBZCNTL_ZPIXOUT_LT 0x00000001
+#define DBZCNTL_ZBUFOUT_LT 0x00000002
+#define DBZCNTL_ZPIXOUT_EQ 0x00000004
+#define DBZCNTL_ZBUFOUT_EQ 0x00000008
+#define DBZCNTL_ZPIXOUT_GT 0x00000010
+#define DBZCNTL_ZBUFOUT_GT 0x00000020
// Z Buffer Base Address (0x00048044)
-#define DBZBASEADDR_MASK 0x00ffffff
+#define DBZBASEADDR_MASK 0x00ffffff
// Z Buffer XY Offset (0x00048048)
-#define DBZOFFS_YOFFS_MASK 0x00000fff
-#define DBZOFFS_YOFFS_SHIFT 0
-#define DBZOFFS_XOFFS_MASK 0x0fff0000
-#define DBZOFFS_XOFFS_SHIFT 16
+#define DBZOFFS_YOFFS_MASK 0x00000fff
+#define DBZOFFS_YOFFS_SHIFT 0
+#define DBZOFFS_XOFFS_MASK 0x0fff0000
+#define DBZOFFS_XOFFS_SHIFT 16
// Z Buffer Clip (0x0004804C)
-#define DBZCLIP_YCLIP_MASK 0x000007ff
-#define DBZCLIP_YCLIP_SHIFT 0
-#define DBZCLIP_XCLIP_MASK 0x07ff0000
-#define DBZCLIP_XCLIP_SHIFT 16
+#define DBZCLIP_YCLIP_MASK 0x000007ff
+#define DBZCLIP_YCLIP_SHIFT 0
+#define DBZCLIP_XCLIP_MASK 0x07ff0000
+#define DBZCLIP_XCLIP_SHIFT 16
// SSB/DSB Control (0x00048050)
-#define DBSSBDSBCNTL_DSBSELECT_MASK 0x00000007
-#define DBSSBDSBCNTL_DSBSELECT_SHIFT 0
-#define DBSSBDSBCNTL_DSBSELECT_SSB 0
-#define DBSSBDSBCNTL_DSBSELECT_CONSTANT 1
-#define DBSSBDSBCNTL_DSBSELECT_SRC 2
+#define DBSSBDSBCNTL_DSBSELECT_MASK 0x00000007
+#define DBSSBDSBCNTL_DSBSELECT_SHIFT 0
+#define DBSSBDSBCNTL_DSBSELECT_SSB 0
+#define DBSSBDSBCNTL_DSBSELECT_CONSTANT 1
+#define DBSSBDSBCNTL_DSBSELECT_SRC 2
-#define DBSSBDSBCNTL_DSBCONST 0x00000004
+#define DBSSBDSBCNTL_DSBCONST 0x00000004
// RGB constants (0x00048054)
-#define DBCONSTIN_B_MASK 0x000000ff
-#define DBCONSTIN_B_SHIFT 0
-#define DBCONSTIN_G_MASK 0x0000ff00
-#define DBCONSTIN_G_SHIFT 8
-#define DBCONSTIN_R_MASK 0x00ff0000
-#define DBCONSTIN_R_SHIFT 16
+#define DBCONSTIN_B_MASK 0x000000ff
+#define DBCONSTIN_B_SHIFT 0
+#define DBCONSTIN_G_MASK 0x0000ff00
+#define DBCONSTIN_G_SHIFT 8
+#define DBCONSTIN_R_MASK 0x00ff0000
+#define DBCONSTIN_R_SHIFT 16
// Texture Multiplication Control (0x00048058)
-#define DBTXTMULTCNTL_TXTRJUST 0x00000001
-#define DBTXTMULTCNTL_TXTCOEFCMP 0x00000002
-
-#define DBTXTMULTCNTL_TXTCONSTCNTL_MASK 0x0000000c
-#define DBTXTMULTCNTL_TXTCONSTCNTL_SHIFT 2
-#define DBTXTMULTCNTL_TXTCONSTCNTL_TEXSSB 0
-#define DBTXTMULTCNTL_TXTCONSTCNTL_SRCDSB 1
-
-#define DBTXTMULTCNTL_COEFSEL_MASK 0x00000030
-#define DBTXTMULTCNTL_COEFSEL_SHIFT 4
-#define DBTXTMULTCNTL_COEFSEL_ATI 0
-#define DBTXTMULTCNTL_COEFSEL_ASRC 1
-#define DBTXTMULTCNTL_COEFSEL_CONSTANT 2
-#define DBTXTMULTCNTL_COEFSEL_CSRC 3
-
-#define DBTXTMULTCNTL_INSEL_MASK 0x000000c0
-#define DBTXTMULTCNTL_INSEL_SHIFT 6
-#define DBTXTMULTCNTL_INSEL_CTI 0
-#define DBTXTMULTCNTL_INSEL_CONSTANT 1
-#define DBTXTMULTCNTL_INSEL_COMPSRC 2
-#define DBTXTMULTCNTL_INSEL_ATI 3
+#define DBTXTMULTCNTL_TXTRJUST 0x00000001
+#define DBTXTMULTCNTL_TXTCOEFCMP 0x00000002
+
+#define DBTXTMULTCNTL_TXTCONSTCNTL_MASK 0x0000000c
+#define DBTXTMULTCNTL_TXTCONSTCNTL_SHIFT 2
+#define DBTXTMULTCNTL_TXTCONSTCNTL_TEXSSB 0
+#define DBTXTMULTCNTL_TXTCONSTCNTL_SRCDSB 1
+
+#define DBTXTMULTCNTL_COEFSEL_MASK 0x00000030
+#define DBTXTMULTCNTL_COEFSEL_SHIFT 4
+#define DBTXTMULTCNTL_COEFSEL_ATI 0
+#define DBTXTMULTCNTL_COEFSEL_ASRC 1
+#define DBTXTMULTCNTL_COEFSEL_CONSTANT 2
+#define DBTXTMULTCNTL_COEFSEL_CSRC 3
+
+#define DBTXTMULTCNTL_INSEL_MASK 0x000000c0
+#define DBTXTMULTCNTL_INSEL_SHIFT 6
+#define DBTXTMULTCNTL_INSEL_CTI 0
+#define DBTXTMULTCNTL_INSEL_CONSTANT 1
+#define DBTXTMULTCNTL_INSEL_COMPSRC 2
+#define DBTXTMULTCNTL_INSEL_ATI 3
// Source Multiplication Control (0x00048058)
-#define DBSRCMULTCNTL_SRCRJUST 0x00000001
-#define DBSRCMULTCNTL_SRCCOEFCMP 0x00000002
-
-#define DBSRCMULTCNTL_SRCCONSTCNTL_MASK 0x0000000c
-#define DBSRCMULTCNTL_SRCCONSTCNTL_SHIFT 2
-#define DBSRCMULTCNTL_SRCCONSTCNTL_TEXSSB 0
-#define DBSRCMULTCNTL_SRCCONSTCNTL_SRCDSB 1
-
-#define DBSRCMULTCNTL_COEFSEL_MASK 0x00000030
-#define DBSRCMULTCNTL_COEFSEL_SHIFT 4
-#define DBSRCMULTCNTL_COEFSEL_ATI 0
-#define DBSRCMULTCNTL_COEFSEL_ASRC 1
-#define DBSRCMULTCNTL_COEFSEL_CONSTANT 2
-#define DBSRCMULTCNTL_COEFSEL_CTI 3
-
-#define DBSRCMULTCNTL_INSEL_MASK 0x000000c0
-#define DBSRCMULTCNTL_INSEL_SHIFT 6
-#define DBSRCMULTCNTL_INSEL_SRC 0
-#define DBSRCMULTCNTL_INSEL_CONSTANT 1
-#define DBSRCMULTCNTL_INSEL_COMPCTI 2
-#define DBSRCMULTCNTL_INSEL_TEXALPHA 3
+#define DBSRCMULTCNTL_SRCRJUST 0x00000001
+#define DBSRCMULTCNTL_SRCCOEFCMP 0x00000002
+
+#define DBSRCMULTCNTL_SRCCONSTCNTL_MASK 0x0000000c
+#define DBSRCMULTCNTL_SRCCONSTCNTL_SHIFT 2
+#define DBSRCMULTCNTL_SRCCONSTCNTL_TEXSSB 0
+#define DBSRCMULTCNTL_SRCCONSTCNTL_SRCDSB 1
+
+#define DBSRCMULTCNTL_COEFSEL_MASK 0x00000030
+#define DBSRCMULTCNTL_COEFSEL_SHIFT 4
+#define DBSRCMULTCNTL_COEFSEL_ATI 0
+#define DBSRCMULTCNTL_COEFSEL_ASRC 1
+#define DBSRCMULTCNTL_COEFSEL_CONSTANT 2
+#define DBSRCMULTCNTL_COEFSEL_CTI 3
+
+#define DBSRCMULTCNTL_INSEL_MASK 0x000000c0
+#define DBSRCMULTCNTL_INSEL_SHIFT 6
+#define DBSRCMULTCNTL_INSEL_SRC 0
+#define DBSRCMULTCNTL_INSEL_CONSTANT 1
+#define DBSRCMULTCNTL_INSEL_COMPCTI 2
+#define DBSRCMULTCNTL_INSEL_TEXALPHA 3
// ALU Control (0x00048070) TODO
-#define DBALUCNTL_FINALDIVIDE_MASK 0x00000007
-#define DBALUCNTL_FINALDIVIDE_SHIFT 0
+#define DBALUCNTL_FINALDIVIDE_MASK 0x00000007
+#define DBALUCNTL_FINALDIVIDE_SHIFT 0
-#define DBALUCNTL_ALUOP_MASK 0x000000f8
-#define DBALUCNTL_ALUOP_SHIFT 5
+#define DBALUCNTL_ALUOP_MASK 0x000000f8
+#define DBALUCNTL_ALUOP_SHIFT 5
// Source Alpha Control (0x00048074)
-#define DBDSTACNTL_ADESTSEL_MASK 0x00000003
-#define DBDSTACNTL_ADESTSEL_SHIFT 0
-#define DBDSTACNTL_ADESTCONSTCNTL_MASK 0x0000000c
-#define DBDSTACNTL_ADESTCONSTCNTL_SHIFT 2
+#define DBDSTACNTL_ADESTSEL_MASK 0x00000003
+#define DBDSTACNTL_ADESTSEL_SHIFT 0
+#define DBDSTACNTL_ADESTCONSTCNTL_MASK 0x0000000c
+#define DBDSTACNTL_ADESTCONSTCNTL_SHIFT 2
-#define DBDSTALPHACONST_CONST1_MASK 0x000000ff
-#define DBDSTALPHACONST_CONST1_SHIFT 0
-#define DBDSTALPHACONST_CONST0_MASK 0x00ff0000
-#define DBDSTALPHACONST_CONST0_SHIFT 16
+#define DBDSTALPHACONST_CONST1_MASK 0x000000ff
+#define DBDSTALPHACONST_CONST1_SHIFT 0
+#define DBDSTALPHACONST_CONST0_MASK 0x00ff0000
+#define DBDSTALPHACONST_CONST0_SHIFT 16
-#define DBSSBDSBCNTL_DSBSEL_MASK 0x00000003
-#define DBSSBDSBCNTL_DSBSEL_SHIFT 0
-#define DBSSBDSBCNTL_DSBCONST_MASK 0x00000004
-#define DBSSBDSBCNTL_DSBCONST_SHIFT 2
+#define DBSSBDSBCNTL_DSBSEL_MASK 0x00000003
+#define DBSSBDSBCNTL_DSBSEL_SHIFT 0
+#define DBSSBDSBCNTL_DSBCONST_MASK 0x00000004
+#define DBSSBDSBCNTL_DSBCONST_SHIFT 2
@@ -665,7 +665,7 @@ static const char *get_reg_name(uint32_t unit, uint32_t reg)
}
case 3:
{
-// if (reg < sizeof(tm_regs))
+// if (reg < sizeof(tm_regs))
{
sprintf(buffer, "TM:????");
return buffer;
@@ -836,7 +836,7 @@ WRITE32_MEMBER( m2_te_device::write )
uint32_t reg = offset & 0x1ff;
reg_wmode wmode = static_cast<reg_wmode>((offset >> 9) & 3);
-// logerror("%s: TE W[%.8x] (%s) %.8x\n", machine().describe_context(), 0x00040000 + (offset << 2), get_reg_name(unit, reg), data);
+// logerror("%s: TE W[%.8x] (%s) %.8x\n", machine().describe_context(), 0x00040000 + (offset << 2), get_reg_name(unit, reg), data);
switch (unit)
{
@@ -1184,7 +1184,7 @@ void m2_te_device::log_triangle(uint32_t flags)
void m2_te_device::setup_triangle(uint32_t flags)
{
-// log_triangle(flags);
+// log_triangle(flags);
se_vtx va = m_se.vertices[0];
se_vtx vb = m_se.vertices[1];
@@ -1362,24 +1362,24 @@ void m2_te_device::setup_triangle(uint32_t flags)
// Convert everything to fixed point and pass to the edge walker
/*
- NOT SURE THESE ARE RIGHT. See P209
+ NOT SURE THESE ARE RIGHT. See P209
- XY 12.0
- SL s12.0
- RGBA 9.0
- RGBA SLOPES = s9.11
- TEX: 11.13
- DEPTH: 1.23
- TEX SLOPES: s11.13
- DEPTH SLOPES: s1.23
- AREA : s23.0
+ XY 12.0
+ SL s12.0
+ RGBA 9.0
+ RGBA SLOPES = s9.11
+ TEX: 11.13
+ DEPTH: 1.23
+ TEX SLOPES: s11.13
+ DEPTH SLOPES: s1.23
+ AREA : s23.0
- Numbers output to the edge walker are 24 bits
+ Numbers output to the edge walker are 24 bits
- IEE: 1.8.23
- BDA: 1.7.24 (includes hidden bit)
+ IEE: 1.8.23
+ BDA: 1.7.24 (includes hidden bit)
- However, we're using 23 bits.
+ However, we're using 23 bits.
*/
@@ -2286,7 +2286,7 @@ void m2_te_device::texture_blend(
}
}
-void m2_te_device::select_lerp( uint32_t sel,
+void m2_te_device::select_lerp( uint32_t sel,
uint32_t ri, uint32_t gi, uint32_t bi, uint32_t ai,
uint32_t rt, uint32_t gt, uint32_t bt, uint32_t at, uint32_t ssbt,
uint32_t & ar, uint32_t & ag, uint32_t & ab )
@@ -2681,17 +2681,17 @@ void m2_te_device::destination_blend(uint32_t x, uint32_t y, uint32_t w, const r
// TODO: Status
/*
- {
- fbClipStat = fbClipDis
- winClipStat = winClipDis
- zClipStat = zClipDis
- alurstat
- alugstat
- alubstat
- zFuncStat
- anyRender
- set_interrupt
- }
+ {
+ fbClipStat = fbClipDis
+ winClipStat = winClipDis
+ zClipStat = zClipDis
+ alurstat
+ alugstat
+ alubstat
+ zFuncStat
+ anyRender
+ set_interrupt
+ }
*/
}
@@ -2710,9 +2710,9 @@ void m2_te_device::select_tex_pixel()
switch (cntl)
{
- case 0: m_dbstate.texpath.a = m_dbstate.ti.a; break;
- case 1: m_dbstate.texpath.a = 255; break;
- case 2: m_dbstate.texpath.a = 0; break;
+ case 0: m_dbstate.texpath.a = m_dbstate.ti.a; break;
+ case 1: m_dbstate.texpath.a = 255; break;
+ case 2: m_dbstate.texpath.a = 0; break;
}
switch ((m_db.txt_mult_cntl & DBTXTMULTCNTL_INSEL_MASK) >> DBTXTMULTCNTL_INSEL_SHIFT)
@@ -2896,18 +2896,18 @@ uint8_t m2_te_device::get_src_coef(uint8_t cti, uint8_t dm2const0, uint8_t dm2co
switch ((m_db.src_mult_cntl & DBSRCMULTCNTL_SRCCONSTCNTL_MASK) >> DBSRCMULTCNTL_SRCCONSTCNTL_SHIFT)
{
- case DBSRCMULTCNTL_SRCCONSTCNTL_TEXSSB: sel = m_dbstate.ssb; break;
- case DBSRCMULTCNTL_SRCCONSTCNTL_SRCDSB: sel = m_dbstate.dsb; break;
+ case DBSRCMULTCNTL_SRCCONSTCNTL_TEXSSB: sel = m_dbstate.ssb; break;
+ case DBSRCMULTCNTL_SRCCONSTCNTL_SRCDSB: sel = m_dbstate.dsb; break;
}
cnst = sel ? dm2const1 : dm2const0;
switch ((m_db.src_mult_cntl & DBSRCMULTCNTL_COEFSEL_MASK) >> DBSRCMULTCNTL_COEFSEL_SHIFT)
{
- case DBSRCMULTCNTL_COEFSEL_ATI: coef = m_dbstate.texpath.a; break;
- case DBSRCMULTCNTL_COEFSEL_ASRC: coef = m_dbstate.srcpath.a; break;
- case DBSRCMULTCNTL_COEFSEL_CONSTANT: coef = cnst; break;
- case DBSRCMULTCNTL_COEFSEL_CTI: coef = cti; break;
+ case DBSRCMULTCNTL_COEFSEL_ATI: coef = m_dbstate.texpath.a; break;
+ case DBSRCMULTCNTL_COEFSEL_ASRC: coef = m_dbstate.srcpath.a; break;
+ case DBSRCMULTCNTL_COEFSEL_CONSTANT: coef = cnst; break;
+ case DBSRCMULTCNTL_COEFSEL_CTI: coef = cti; break;
}
if (m_db.src_mult_cntl & DBSRCMULTCNTL_SRCCOEFCMP)
@@ -2933,10 +2933,10 @@ uint8_t m2_te_device::get_tex_coef(uint8_t cs, uint8_t dm1const0, uint8_t dm1con
switch ((m_db.txt_mult_cntl & DBTXTMULTCNTL_COEFSEL_MASK) >> DBTXTMULTCNTL_COEFSEL_SHIFT)
{
- case DBTXTMULTCNTL_COEFSEL_ATI: coef = m_dbstate.texpath.a; break;
- case DBTXTMULTCNTL_COEFSEL_ASRC: coef = m_dbstate.srcpath.a; break;
- case DBTXTMULTCNTL_COEFSEL_CONSTANT: coef = cnst; break;
- case DBTXTMULTCNTL_COEFSEL_CSRC: coef = cs; break;
+ case DBTXTMULTCNTL_COEFSEL_ATI: coef = m_dbstate.texpath.a; break;
+ case DBTXTMULTCNTL_COEFSEL_ASRC: coef = m_dbstate.srcpath.a; break;
+ case DBTXTMULTCNTL_COEFSEL_CONSTANT: coef = cnst; break;
+ case DBTXTMULTCNTL_COEFSEL_CSRC: coef = cs; break;
}
if (m_db.txt_mult_cntl & DBTXTMULTCNTL_TXTCOEFCMP)
@@ -2954,8 +2954,8 @@ void m2_te_device::select_alpha_dsb()
switch ((m_db.dst_alpha_ctrl & DBDSTACNTL_ADESTCONSTCNTL_MASK) >> DBDSTACNTL_ADESTCONSTCNTL_SHIFT)
{
- case 0: sel = m_dbstate.ssb; break;
- case 1: sel = m_dbstate.dsb; break;
+ case 0: sel = m_dbstate.ssb; break;
+ case 1: sel = m_dbstate.dsb; break;
}
if (sel)
@@ -2965,17 +2965,17 @@ void m2_te_device::select_alpha_dsb()
switch ((m_db.dst_alpha_ctrl & DBDSTACNTL_ADESTSEL_MASK) >> DBDSTACNTL_ADESTSEL_SHIFT)
{
- case 0: m_dbstate.dst.a = m_dbstate.texpath.a; break;
- case 1: m_dbstate.dst.a = aconst; break;
- case 2: m_dbstate.dst.a = m_dbstate.srcpath.a; break;
- case 3: m_dbstate.dst.a = m_dbstate.blend.r; break;
+ case 0: m_dbstate.dst.a = m_dbstate.texpath.a; break;
+ case 1: m_dbstate.dst.a = aconst; break;
+ case 2: m_dbstate.dst.a = m_dbstate.srcpath.a; break;
+ case 3: m_dbstate.dst.a = m_dbstate.blend.r; break;
}
switch ((m_db.ssbdsb_ctrl & DBSSBDSBCNTL_DSBSEL_MASK) >> DBSSBDSBCNTL_DSBSEL_SHIFT)
{
- case 0: m_dbstate.dsb = m_dbstate.ssb; break;
- case 1: m_dbstate.dsb = (m_db.ssbdsb_ctrl & DBSSBDSBCNTL_DSBCONST_MASK) >> DBSSBDSBCNTL_DSBCONST_SHIFT; break;
- case 2: m_dbstate.dsb = m_dbstate.dsb; break;
+ case 0: m_dbstate.dsb = m_dbstate.ssb; break;
+ case 1: m_dbstate.dsb = (m_db.ssbdsb_ctrl & DBSSBDSBCNTL_DSBCONST_MASK) >> DBSSBDSBCNTL_DSBCONST_SHIFT; break;
+ case 2: m_dbstate.dsb = m_dbstate.dsb; break;
}
}
else
@@ -3048,10 +3048,10 @@ uint8_t m2_te_device::alu_calc(uint16_t a, uint16_t b)
switch (j)
{
- case 0: cinv |= (cntl & 1); break;
- case 1: cinv |= (cntl & 2) && 1; break;
- case 2: cinv |= (cntl & 4) && 1; break;
- case 3: cinv |= (cntl & 8) && 1; break;
+ case 0: cinv |= (cntl & 1); break;
+ case 1: cinv |= (cntl & 2) && 1; break;
+ case 2: cinv |= (cntl & 4) && 1; break;
+ case 3: cinv |= (cntl & 8) && 1; break;
}
cinv <<= 1;
@@ -3075,13 +3075,13 @@ uint8_t m2_te_device::alu_calc(uint16_t a, uint16_t b)
switch ((m_db.alu_ctrl & DBALUCNTL_FINALDIVIDE_MASK) >> DBALUCNTL_FINALDIVIDE_SHIFT)
{
- case 1: blendout = result << 1; break;
- case 2: blendout = result << 2; break;
- case 3: blendout = result << 3; break;
- case 7: blendout = result >> 1; break;
- case 6: blendout = result >> 2; break;
- case 5: blendout = result >> 3; break;
- default: blendout = result; break;
+ case 1: blendout = result << 1; break;
+ case 2: blendout = result << 2; break;
+ case 3: blendout = result << 3; break;
+ case 7: blendout = result >> 1; break;
+ case 6: blendout = result >> 2; break;
+ case 5: blendout = result >> 3; break;
+ default: blendout = result; break;
}
if (blendout > 255)
@@ -3139,22 +3139,22 @@ void m2_te_device::walk_span(uint32_t wrange, bool omit_right,
xe = scan_lr ? xe + 1 : xe - 1;
/*
- Edge to Span walker
- X/Y 11.0
- RGBA 8.11
- U/W, V/W 10.13
- 1/W 0.23
- RGBA DDX s8.11
- UV DDX s10.13
- 1/W DDX s0.23
-
- To destination blender:
- X/Y 11.0
- W 0.16
-
- To texture mapper:
- RGBA 8.0
- UV 10.4
+ Edge to Span walker
+ X/Y 11.0
+ RGBA 8.11
+ U/W, V/W 10.13
+ 1/W 0.23
+ RGBA DDX s8.11
+ UV DDX s10.13
+ 1/W DDX s0.23
+
+ To destination blender:
+ X/Y 11.0
+ W 0.16
+
+ To texture mapper:
+ RGBA 8.0
+ UV 10.4
*/
if (omit_right)
@@ -3478,22 +3478,22 @@ void m2_te_device::execute()
#if TEST_TIMING
/*
- TESetup Engine: 600-700 triangles/sec (?)
+ TESetup Engine: 600-700 triangles/sec (?)
- Pixel Rates:
- Point - 132Mpix/s
- Linear - 66Mpix/s
- Bilin - 33Mpix
- QTril - 22M
+ Pixel Rates:
+ Point - 132Mpix/s
+ Linear - 66Mpix/s
+ Bilin - 33Mpix
+ QTril - 22M
- No blend, no Z - 120MPix
- Zbuffer - 66-120M pix
- Bend - 66 M pix
+ No blend, no Z - 120MPix
+ Zbuffer - 66-120M pix
+ Bend - 66 M pix
*/
uint32_t total_cycles = (g_statistics[STAT_TRIANGLES_PROCESSED] * 100) +
(g_statistics[STAT_TEXEL_READS]) +
-// (g_statistics[STAT_PIXELS_PROCESSED]) +
+// (g_statistics[STAT_PIXELS_PROCESSED]) +
(g_statistics[STAT_PIXEL_LOADS]) +
(g_statistics[STAT_PIXEL_STORES]) +
(g_statistics[STAT_TEXEL_BYTES]/4) +
diff --git a/src/mame/machine/genpin.cpp b/src/mame/machine/genpin.cpp
index 877cb1a5d90..1c1ca11a38f 100644
--- a/src/mame/machine/genpin.cpp
+++ b/src/mame/machine/genpin.cpp
@@ -17,4 +17,4 @@ void genpin_class::genpin_audio(machine_config &config)
m_samples->set_channels(6);
m_samples->set_samples_names(genpin_sample_names);
m_samples->add_route(ALL_OUTPUTS, "mechvol", 1.0);
-} \ No newline at end of file
+}
diff --git a/src/mame/machine/midwunit.cpp b/src/mame/machine/midwunit.cpp
index 85203c56d7e..f37dbe5deee 100644
--- a/src/mame/machine/midwunit.cpp
+++ b/src/mame/machine/midwunit.cpp
@@ -13,12 +13,12 @@
#include "includes/midtunit.h"
#include "includes/midwunit.h"
-#define LOG_UNKNOWN (1 << 0)
-#define LOG_CMOS (1 << 1)
-#define LOG_IO (1 << 2)
-#define LOG_SOUND (1 << 3)
+#define LOG_UNKNOWN (1 << 0)
+#define LOG_CMOS (1 << 1)
+#define LOG_IO (1 << 2)
+#define LOG_SOUND (1 << 3)
-#define VERBOSE (0)
+#define VERBOSE (0)
#include "logmacro.h"
/*************************************
diff --git a/src/mame/machine/midxunit.cpp b/src/mame/machine/midxunit.cpp
index fbbdad46380..a597eff9c4e 100644
--- a/src/mame/machine/midxunit.cpp
+++ b/src/mame/machine/midxunit.cpp
@@ -14,12 +14,12 @@
#include "includes/midxunit.h"
#include "midwayic.h"
-#define LOG_IO (1 << 0)
-#define LOG_UART (1 << 1)
-#define LOG_UNKNOWN (1 << 2)
-#define LOG_SOUND (1 << 3)
+#define LOG_IO (1 << 0)
+#define LOG_UART (1 << 1)
+#define LOG_UNKNOWN (1 << 2)
+#define LOG_SOUND (1 << 3)
-#define VERBOSE (0)
+#define VERBOSE (0)
#include "logmacro.h"
/*************************************
diff --git a/src/mame/video/galaxian.cpp b/src/mame/video/galaxian.cpp
index b54d49a5db9..5fd0583c61a 100644
--- a/src/mame/video/galaxian.cpp
+++ b/src/mame/video/galaxian.cpp
@@ -1368,12 +1368,12 @@ void galaxian_state::jumpbug_extend_sprite_info(const uint8_t *base, uint8_t *sx
*
*************************************/
-/* gfxbank[4] is used as a cpu bank number, and gfxbank[0] for graphics banking */
+/* gfxbank[4] is used as a cpu bank number, and gfxbank[0] for graphics banking */
WRITE8_MEMBER( galaxian_state::fourplay_rombank_w )
{
m_gfxbank[4] = (m_gfxbank[4] & (2 - offset)) | (data << offset);
- m_gfxbank[0] = (m_gfxbank[4] == 3); // 1 = true, 0 = false
+ m_gfxbank[0] = (m_gfxbank[4] == 3); // 1 = true, 0 = false
membank("bank1")->set_entry( m_gfxbank[4] );
}
diff --git a/src/mame/video/k054156_k054157_k056832.h b/src/mame/video/k054156_k054157_k056832.h
index 05197cb48ed..982bcd4a7db 100644
--- a/src/mame/video/k054156_k054157_k056832.h
+++ b/src/mame/video/k054156_k054157_k056832.h
@@ -41,7 +41,7 @@ public:
template <typename... T> void set_tile_callback(T &&... args) { m_k056832_cb = k056832_cb_delegate(std::forward<T>(args)...); }
- template <typename T>
+ template <typename T>
void set_config(T &&gfx_reg, int bpp, int big, int djmain_hack)
{
m_rombase.set_tag(std::forward<T>(gfx_reg));
diff --git a/src/mame/video/midtunit.cpp b/src/mame/video/midtunit.cpp
index 465a9616e22..6fcafa2f232 100644
--- a/src/mame/video/midtunit.cpp
+++ b/src/mame/video/midtunit.cpp
@@ -140,8 +140,8 @@ WRITE16_MEMBER(midtunit_video_device::midtunit_vram_w)
offset *= 2;
if (m_videobank_select)
{
- if (ACCESSING_BITS_0_7)
- m_local_videoram[offset] = (data & 0xff) | ((m_dma_register[DMA_PALETTE] & 0xff) << 8);
+ if (ACCESSING_BITS_0_7)
+ m_local_videoram[offset] = (data & 0xff) | ((m_dma_register[DMA_PALETTE] & 0xff) << 8);
if (ACCESSING_BITS_8_15)
m_local_videoram[offset + 1] = ((data >> 8) & 0xff) | (m_dma_register[DMA_PALETTE] & 0xff00);
}
diff --git a/src/mame/video/midtunit.h b/src/mame/video/midtunit.h
index 69cdec0cd3f..baba3687f2e 100644
--- a/src/mame/video/midtunit.h
+++ b/src/mame/video/midtunit.h
@@ -16,7 +16,7 @@
#include "cpu/tms34010/tms34010.h"
#include "emupal.h"
-#define DEBUG_MIDTUNIT_BLITTER (0)
+#define DEBUG_MIDTUNIT_BLITTER (0)
class midtunit_video_device : public device_t
{
@@ -110,16 +110,16 @@ protected:
};
/* graphics-related variables */
- uint16_t m_midtunit_control;
- bool m_gfx_rom_large;
+ uint16_t m_midtunit_control;
+ bool m_gfx_rom_large;
/* videoram-related variables */
- uint32_t m_gfxbank_offset[2];
- std::unique_ptr<uint16_t[]> m_local_videoram;
- uint8_t m_videobank_select;
+ uint32_t m_gfxbank_offset[2];
+ std::unique_ptr<uint16_t[]> m_local_videoram;
+ uint8_t m_videobank_select;
/* DMA-related variables */
- uint16_t m_dma_register[18];
+ uint16_t m_dma_register[18];
struct dma_state
{
uint8_t * gfxrom;
@@ -145,7 +145,7 @@ protected:
uint16_t xstep; /* 8.8 fixed number scale x factor */
uint16_t ystep; /* 8.8 fixed number scale y factor */
};
- dma_state m_dma_state;
+ dma_state m_dma_state;
#if DEBUG_MIDTUNIT_BLITTER
virtual void device_reset() override;
@@ -223,4 +223,4 @@ DECLARE_DEVICE_TYPE(MIDTUNIT_VIDEO, midtunit_video_device)
DECLARE_DEVICE_TYPE(MIDWUNIT_VIDEO, midwunit_video_device)
DECLARE_DEVICE_TYPE(MIDXUNIT_VIDEO, midxunit_video_device)
-#endif // MAME_VIDEO_MIDTUNIT_H \ No newline at end of file
+#endif // MAME_VIDEO_MIDTUNIT_H
diff --git a/src/mame/video/midtunit.ipp b/src/mame/video/midtunit.ipp
index 690afa6646b..1662c706d5d 100644
--- a/src/mame/video/midtunit.ipp
+++ b/src/mame/video/midtunit.ipp
@@ -9,23 +9,23 @@
**************************************************************************/
#define INIT_TEMPLATED_DMA_DRAW(dest, i, xflip, skip, scale, zero, nonzero) \
- dest[i+0] = &midtunit_video_device::dma_draw<8, xflip, skip, scale, zero, nonzero>; \
- dest[i+1] = &midtunit_video_device::dma_draw<1, xflip, skip, scale, zero, nonzero>; \
- dest[i+2] = &midtunit_video_device::dma_draw<2, xflip, skip, scale, zero, nonzero>; \
- dest[i+3] = &midtunit_video_device::dma_draw<3, xflip, skip, scale, zero, nonzero>; \
- dest[i+4] = &midtunit_video_device::dma_draw<4, xflip, skip, scale, zero, nonzero>; \
- dest[i+5] = &midtunit_video_device::dma_draw<5, xflip, skip, scale, zero, nonzero>; \
- dest[i+6] = &midtunit_video_device::dma_draw<6, xflip, skip, scale, zero, nonzero>; \
+ dest[i+0] = &midtunit_video_device::dma_draw<8, xflip, skip, scale, zero, nonzero>; \
+ dest[i+1] = &midtunit_video_device::dma_draw<1, xflip, skip, scale, zero, nonzero>; \
+ dest[i+2] = &midtunit_video_device::dma_draw<2, xflip, skip, scale, zero, nonzero>; \
+ dest[i+3] = &midtunit_video_device::dma_draw<3, xflip, skip, scale, zero, nonzero>; \
+ dest[i+4] = &midtunit_video_device::dma_draw<4, xflip, skip, scale, zero, nonzero>; \
+ dest[i+5] = &midtunit_video_device::dma_draw<5, xflip, skip, scale, zero, nonzero>; \
+ dest[i+6] = &midtunit_video_device::dma_draw<6, xflip, skip, scale, zero, nonzero>; \
dest[i+7] = &midtunit_video_device::dma_draw<7, xflip, skip, scale, zero, nonzero>;
#define TEMPLATED_DMA_DRAW_NONE(dest, i) \
- dest[i+0] = &midtunit_video_device::dma_draw_none; \
- dest[i+1] = &midtunit_video_device::dma_draw_none; \
- dest[i+2] = &midtunit_video_device::dma_draw_none; \
- dest[i+3] = &midtunit_video_device::dma_draw_none; \
- dest[i+4] = &midtunit_video_device::dma_draw_none; \
- dest[i+5] = &midtunit_video_device::dma_draw_none; \
- dest[i+6] = &midtunit_video_device::dma_draw_none; \
+ dest[i+0] = &midtunit_video_device::dma_draw_none; \
+ dest[i+1] = &midtunit_video_device::dma_draw_none; \
+ dest[i+2] = &midtunit_video_device::dma_draw_none; \
+ dest[i+3] = &midtunit_video_device::dma_draw_none; \
+ dest[i+4] = &midtunit_video_device::dma_draw_none; \
+ dest[i+5] = &midtunit_video_device::dma_draw_none; \
+ dest[i+6] = &midtunit_video_device::dma_draw_none; \
dest[i+7] = &midtunit_video_device::dma_draw_none;
#define TEMPLATED_DMA_DRAW_P0(dest, i, skip, scale) INIT_TEMPLATED_DMA_DRAW(dest, i, false, skip, scale, PIXEL_COPY, PIXEL_SKIP)
@@ -47,33 +47,33 @@
#define TEMPLATED_DMA_DRAW_P0C1_XF(dest, i, skip, scale) INIT_TEMPLATED_DMA_DRAW(dest, i, true, skip, scale, PIXEL_COPY, PIXEL_COLOR)
#define INIT_TEMPLATED_DMA_DRAW_GROUP(dest, skip, scale) \
- TEMPLATED_DMA_DRAW_NONE(dest, 0); \
- TEMPLATED_DMA_DRAW_P0(dest, 8, skip, scale); \
- TEMPLATED_DMA_DRAW_P1(dest, 16, skip, scale); \
- TEMPLATED_DMA_DRAW_P0P1(dest, 24, skip, scale); \
- TEMPLATED_DMA_DRAW_C0(dest, 32, skip, scale); \
- TEMPLATED_DMA_DRAW_C0(dest, 40, skip, scale); \
- TEMPLATED_DMA_DRAW_C0P1(dest, 48, skip, scale); \
- TEMPLATED_DMA_DRAW_C0P1(dest, 56, skip, scale); \
- TEMPLATED_DMA_DRAW_C1(dest, 64, skip, scale); \
- TEMPLATED_DMA_DRAW_P0C1(dest, 72, skip, scale); \
- TEMPLATED_DMA_DRAW_C1(dest, 80, skip, scale); \
- TEMPLATED_DMA_DRAW_P0C1(dest, 88, skip, scale); \
- TEMPLATED_DMA_DRAW_C0C1(dest, 96, skip, scale); \
- TEMPLATED_DMA_DRAW_C0C1(dest, 104, skip, scale); \
- TEMPLATED_DMA_DRAW_C0C1(dest, 112, skip, scale); \
- TEMPLATED_DMA_DRAW_C0C1(dest, 120, skip, scale); \
- TEMPLATED_DMA_DRAW_NONE(dest, 128); \
- TEMPLATED_DMA_DRAW_P0_XF(dest, 136, skip, scale); \
- TEMPLATED_DMA_DRAW_P1_XF(dest, 144, skip, scale); \
+ TEMPLATED_DMA_DRAW_NONE(dest, 0); \
+ TEMPLATED_DMA_DRAW_P0(dest, 8, skip, scale); \
+ TEMPLATED_DMA_DRAW_P1(dest, 16, skip, scale); \
+ TEMPLATED_DMA_DRAW_P0P1(dest, 24, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0(dest, 32, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0(dest, 40, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0P1(dest, 48, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0P1(dest, 56, skip, scale); \
+ TEMPLATED_DMA_DRAW_C1(dest, 64, skip, scale); \
+ TEMPLATED_DMA_DRAW_P0C1(dest, 72, skip, scale); \
+ TEMPLATED_DMA_DRAW_C1(dest, 80, skip, scale); \
+ TEMPLATED_DMA_DRAW_P0C1(dest, 88, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0C1(dest, 96, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0C1(dest, 104, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0C1(dest, 112, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0C1(dest, 120, skip, scale); \
+ TEMPLATED_DMA_DRAW_NONE(dest, 128); \
+ TEMPLATED_DMA_DRAW_P0_XF(dest, 136, skip, scale); \
+ TEMPLATED_DMA_DRAW_P1_XF(dest, 144, skip, scale); \
TEMPLATED_DMA_DRAW_P0P1_XF(dest, 152, skip, scale); \
- TEMPLATED_DMA_DRAW_C0_XF(dest, 160, skip, scale); \
- TEMPLATED_DMA_DRAW_C0_XF(dest, 168, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0_XF(dest, 160, skip, scale); \
+ TEMPLATED_DMA_DRAW_C0_XF(dest, 168, skip, scale); \
TEMPLATED_DMA_DRAW_C0P1_XF(dest, 176, skip, scale); \
TEMPLATED_DMA_DRAW_C0P1_XF(dest, 184, skip, scale); \
- TEMPLATED_DMA_DRAW_C1_XF(dest, 192, skip, scale); \
+ TEMPLATED_DMA_DRAW_C1_XF(dest, 192, skip, scale); \
TEMPLATED_DMA_DRAW_P0C1_XF(dest, 200, skip, scale); \
- TEMPLATED_DMA_DRAW_C1_XF(dest, 208, skip, scale); \
+ TEMPLATED_DMA_DRAW_C1_XF(dest, 208, skip, scale); \
TEMPLATED_DMA_DRAW_P0C1_XF(dest, 216, skip, scale); \
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 224, skip, scale); \
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 232, skip, scale); \
@@ -81,13 +81,13 @@
TEMPLATED_DMA_DRAW_C0C1_XF(dest, 248, skip, scale);
#define DEFINE_TEMPLATED_DMA_DRAW(xflip, skip, scale, zero, nonzero) \
- template void midtunit_video_device::dma_draw<8, xflip, skip, scale, zero, nonzero>(); \
- template void midtunit_video_device::dma_draw<1, xflip, skip, scale, zero, nonzero>(); \
- template void midtunit_video_device::dma_draw<2, xflip, skip, scale, zero, nonzero>(); \
- template void midtunit_video_device::dma_draw<3, xflip, skip, scale, zero, nonzero>(); \
- template void midtunit_video_device::dma_draw<4, xflip, skip, scale, zero, nonzero>(); \
- template void midtunit_video_device::dma_draw<5, xflip, skip, scale, zero, nonzero>(); \
- template void midtunit_video_device::dma_draw<6, xflip, skip, scale, zero, nonzero>(); \
+ template void midtunit_video_device::dma_draw<8, xflip, skip, scale, zero, nonzero>(); \
+ template void midtunit_video_device::dma_draw<1, xflip, skip, scale, zero, nonzero>(); \
+ template void midtunit_video_device::dma_draw<2, xflip, skip, scale, zero, nonzero>(); \
+ template void midtunit_video_device::dma_draw<3, xflip, skip, scale, zero, nonzero>(); \
+ template void midtunit_video_device::dma_draw<4, xflip, skip, scale, zero, nonzero>(); \
+ template void midtunit_video_device::dma_draw<5, xflip, skip, scale, zero, nonzero>(); \
+ template void midtunit_video_device::dma_draw<6, xflip, skip, scale, zero, nonzero>(); \
template void midtunit_video_device::dma_draw<7, xflip, skip, scale, zero, nonzero>();
#define DEFINE_TEMPLATED_DMA_DRAW_P0(skip, scale) \
@@ -107,21 +107,21 @@
#define DEFINE_TEMPLATED_DMA_DRAW_P0C1(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(false, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COLOR)
-#define DEFINE_TEMPLATED_DMA_DRAW_P0_XF(skip, scale) \
+#define DEFINE_TEMPLATED_DMA_DRAW_P0_XF(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_SKIP)
-#define DEFINE_TEMPLATED_DMA_DRAW_P1_XF(skip, scale) \
+#define DEFINE_TEMPLATED_DMA_DRAW_P1_XF(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_SKIP, midtunit_video_device::PIXEL_COPY)
-#define DEFINE_TEMPLATED_DMA_DRAW_C0_XF(skip, scale) \
+#define DEFINE_TEMPLATED_DMA_DRAW_C0_XF(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_SKIP)
-#define DEFINE_TEMPLATED_DMA_DRAW_C1_XF(skip, scale) \
+#define DEFINE_TEMPLATED_DMA_DRAW_C1_XF(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_SKIP, midtunit_video_device::PIXEL_COLOR)
-#define DEFINE_TEMPLATED_DMA_DRAW_P0P1_XF(skip, scale) \
+#define DEFINE_TEMPLATED_DMA_DRAW_P0P1_XF(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COPY)
-#define DEFINE_TEMPLATED_DMA_DRAW_C0C1_XF(skip, scale) \
+#define DEFINE_TEMPLATED_DMA_DRAW_C0C1_XF(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_COLOR)
-#define DEFINE_TEMPLATED_DMA_DRAW_C0P1_XF(skip, scale) \
+#define DEFINE_TEMPLATED_DMA_DRAW_C0P1_XF(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COLOR, midtunit_video_device::PIXEL_COPY)
-#define DEFINE_TEMPLATED_DMA_DRAW_P0C1_XF(skip, scale) \
+#define DEFINE_TEMPLATED_DMA_DRAW_P0C1_XF(skip, scale) \
DEFINE_TEMPLATED_DMA_DRAW(true, skip, scale, midtunit_video_device::PIXEL_COPY, midtunit_video_device::PIXEL_COLOR)
#define DEFINE_TEMPLATED_DMA_DRAW_GROUP(skip, scale) \
diff --git a/src/mame/video/pc1251.cpp b/src/mame/video/pc1251.cpp
index 32974c9a677..ee7780d2e3d 100644
--- a/src/mame/video/pc1251.cpp
+++ b/src/mame/video/pc1251.cpp
@@ -9,7 +9,7 @@
#define LOG_LCD (1 << 0)
-#define VERBOSE (0)
+#define VERBOSE (0)
#include "logmacro.h"
const char *const pc1251_state::s_def[5] =
diff --git a/src/mame/video/seta2.cpp b/src/mame/video/seta2.cpp
index e8fadf30e8b..8114ec08b43 100644
--- a/src/mame/video/seta2.cpp
+++ b/src/mame/video/seta2.cpp
@@ -99,68 +99,68 @@
1c Zoom Y? low bits
1e Zoom Y? high bits *
- 24 1->0 in funcube3 and staraudi
+ 24 1->0 in funcube3 and staraudi
26 1->0 during INT0, before writing sprites
- (probably creates a custom format sprite list at 0x0000 by processing the list at 0x3000)
+ (probably creates a custom format sprite list at 0x0000 by processing the list at 0x3000)
30 fedc ba98 7654 321-
---- ---- ---- ---0 Disable video
32..3f ?
- Global X offset values based on penbros
+ Global X offset values based on penbros
- 0x1c0 - when zoom is smallest
- counts up to 0x7ff
- then 0x00 when finished
+ 0x1c0 - when zoom is smallest
+ counts up to 0x7ff
+ then 0x00 when finished
- counts up to 0x089 when zooming in
+ counts up to 0x089 when zooming in
- Zoom values (both x and y) based on penbros and others (x flip/unflip logic is reverse of y logic)
+ Zoom values (both x and y) based on penbros and others (x flip/unflip logic is reverse of y logic)
- (unflipped gfx)
- 0x7f5 00 = smallest
- 0x7ff 00 = normal
- 0x7ff xx = larger
+ (unflipped gfx)
+ 0x7f5 00 = smallest
+ 0x7ff 00 = normal
+ 0x7ff xx = larger
- (flipped gfx, negative zoom factor!, used instead of flipscreen bits in some cases)
- 0x00b 00 = smallest
- 0x001 00 = normal
- 0x001 xx = larger
+ (flipped gfx, negative zoom factor!, used instead of flipscreen bits in some cases)
+ 0x00b 00 = smallest
+ 0x001 00 = normal
+ 0x001 xx = larger
***************************************************************************/
/***************************************************************************
-
+
NON-BUGS
grdians : After the fire rowscroll effect in the intro there is a small artifact
left scrolling at the top of the screen when the next image is displayed
- See 4:24 in https://www.youtube.com/watch?v=cvHGFEsB_cM
-
+ See 4:24 in https://www.youtube.com/watch?v=cvHGFEsB_cM
+
***************************************************************************/
WRITE16_MEMBER(seta2_state::vregs_w)
{
/* 02/04 = horizontal display start/end
- mj4simai = 0065/01E5 (0180 visible area)
- myangel = 005D/01D5 (0178 visible area)
- pzlbowl = 0058/01D8 (0180 visible area)
- penbros = 0065/01A5 (0140 visible area)
- grdians = 0059/0188 (012f visible area)
+ mj4simai = 0065/01E5 (0180 visible area)
+ myangel = 005D/01D5 (0178 visible area)
+ pzlbowl = 0058/01D8 (0180 visible area)
+ penbros = 0065/01A5 (0140 visible area)
+ grdians = 0059/0188 (012f visible area)
06 = horizontal total?
- mj4simai = 0204
- myangel = 0200
- pzlbowl = 0204
- penbros = 01c0
- grdians = 019a
+ mj4simai = 0204
+ myangel = 0200
+ pzlbowl = 0204
+ penbros = 01c0
+ grdians = 019a
*/
uint16_t olddata = m_vregs[offset];
COMBINE_DATA(&m_vregs[offset]);
-// popmessage("%04x %04x", m_vregs[0x1e/2], m_vregs[0x1c/2]);
+// popmessage("%04x %04x", m_vregs[0x1e/2], m_vregs[0x1c/2]);
if (m_vregs[offset] != olddata)
logerror("CPU #0 PC %06X: Video Reg %02X <- %04X\n", m_maincpu->pc(), offset * 2, data);
@@ -233,7 +233,7 @@ WRITE16_MEMBER(seta2_state::vregs_w)
m_private_spriteram[i + 3] |= 0x4000;
}
- break;
+ break;
}
}
@@ -337,7 +337,7 @@ inline void seta2_state::drawgfx_line(bitmap_ind16 &bitmap, const rectangle &cli
int pen_shift = 15 - shadow;
int pen_mask = (1 << pen_shift) - 1;
dest[sx] = ((dest[sx] & pen_mask) | (pen << pen_shift)) & 0x7fff;
- }
+ }
}
}
}
@@ -362,7 +362,7 @@ inline void seta2_state::get_tile(uint16_t* spriteram, int is_16x16, int x, int
if (is_16x16)
{
code &= ~3;
-
+
if (!flipx)
{
if (x & 8)
@@ -419,7 +419,7 @@ void seta2_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
// HACK: this inverts the zoom on all sprites, thus flipping the screen and altering positions as the origin becomes the right hand side, not left, see star audition (by default) or deer hunting when you turn on horizontal flip
// TODO: properly render negative zoom sprites
- if (global_xzoom & 0x400)
+ if (global_xzoom & 0x400)
{
global_xoffset -= 0x14f;
}
@@ -454,7 +454,7 @@ void seta2_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
if (special)
{
use_shadow = 0;
- // which_gfx = 4 << 8;
+ // which_gfx = 4 << 8;
global_yoffset = -0x90;
global_xoffset = 0x80;
}
@@ -590,7 +590,7 @@ void seta2_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
int realfirstline = firstline;
- if (firstline < cliprect.min_y) realfirstline = cliprect.min_y;
+ if (firstline < cliprect.min_y) realfirstline = cliprect.min_y;
if (endline > cliprect.max_y) endline = cliprect.max_y;
for (int realline = realfirstline; realline <= endline; realline++)
@@ -627,7 +627,7 @@ TIMER_CALLBACK_MEMBER(seta2_state::raster_timer_done)
{
m_tmp68301->external_interrupt_1();
logerror("external int (vpos is %d)\n", m_screen->vpos());
- m_screen->update_partial(m_screen->vpos() - 1);
+ m_screen->update_partial(m_screen->vpos() - 1);
}
}
}
diff --git a/src/mame/video/ssv.cpp b/src/mame/video/ssv.cpp
index 8e1e81b2d7c..7d280915cc5 100644
--- a/src/mame/video/ssv.cpp
+++ b/src/mame/video/ssv.cpp
@@ -165,7 +165,7 @@ void ssv_state::drawgfx_line(bitmap_ind16 &bitmap, const rectangle &cliprect, in
{ 0x0f,0 }, // 4: eagle shot 4bpp birdie text
{ 0xf0,4 }, // 5: eagle shot 4bpp Japanese text
{ 0x3f,0 }, // 6: common 6bpp case + keithlcy (logo), drifto94 (wheels) masking
- { 0xff,0 } // 7: common 8bpp case
+ { 0xff,0 } // 7: common 8bpp case
};
const uint8_t gfxbppmask = BPP_MASK_TABLE[gfx & 0x07].gfx_mask;
@@ -829,12 +829,12 @@ void ssv_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
{
// "Normal" Sprite
/*
- hot spots:
- "warning" in hypreac2 has mode & 0x0100 and is not 16x16
- keithlcy high scores has mode & 0x0100 and y & 0x0c00 can be 0x0c00
- drifto94 "you have proved yOur".. has mode & 0x0100 and x & 0x0c00 can be 0x0c00
- ultrax (begin of lev1): 100010: 6b60 4280 0016 00a0
- 121400: 51a0 0042 6800 0c00 needs to be a normal sprite
+ hot spots:
+ "warning" in hypreac2 has mode & 0x0100 and is not 16x16
+ keithlcy high scores has mode & 0x0100 and y & 0x0c00 can be 0x0c00
+ drifto94 "you have proved yOur".. has mode & 0x0100 and x & 0x0c00 can be 0x0c00
+ ultrax (begin of lev1): 100010: 6b60 4280 0016 00a0
+ 121400: 51a0 0042 6800 0c00 needs to be a normal sprite
*/
int code = spritelist_local[0]; // code high bits