diff options
author | Sandro Ronco <sronco@users.noreply.github.com> | 2012-09-10 17:44:55 +0000 |
---|---|---|
committer | Sandro Ronco <sronco@users.noreply.github.com> | 2012-09-10 17:44:55 +0000 |
commit | 573744ba277f1e91df3b86b4091da616a3311428 (patch) | |
tree | 15cfb32988766e9b010696a6fae43cc7f7c7458b /src | |
parent | be3af47f06821ce44fa7ebd16c026ede804d82bf (diff) |
Added asl_ext, bclr_dir, bset_dir opcodes to the HC11 core. (nw)
Diffstat (limited to 'src')
-rw-r--r-- | src/emu/cpu/mc68hc11/hc11ops.c | 47 | ||||
-rw-r--r-- | src/emu/cpu/mc68hc11/hc11ops.h | 6 | ||||
-rw-r--r-- | src/mess/drivers/alphasma.c | 1 |
3 files changed, 51 insertions, 3 deletions
diff --git a/src/emu/cpu/mc68hc11/hc11ops.c b/src/emu/cpu/mc68hc11/hc11ops.c index 55aaab26ce2..cc19d247f57 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.c +++ b/src/emu/cpu/mc68hc11/hc11ops.c @@ -645,6 +645,27 @@ static void HC11OP(aslb)(hc11_state *cpustate) CYCLES(cpustate, 2); } +/* ASL EXT 0x78 */ +static void HC11OP(asl_ext)(hc11_state *cpustate) +{ + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); + UINT16 r = i << 1; + CLEAR_NZVC(cpustate); + SET_C8(r); + WRITE8(cpustate, adr, r); + SET_N8(r); + SET_Z8(r); + + if (((cpustate->ccr & CC_N) && (cpustate->ccr & CC_C) == 0) || + ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C))) + { + cpustate->ccr |= CC_V; + } + + CYCLES(cpustate, 6); +} + /* BITA IMM 0x85 */ static void HC11OP(bita_imm)(hc11_state *cpustate) { @@ -775,6 +796,19 @@ static void HC11OP(bcc)(hc11_state *cpustate) CYCLES(cpustate, 3); } +/* BCLR DIR 0x15 */ +static void HC11OP(bclr_dir)(hc11_state *cpustate) +{ + UINT8 d = FETCH(cpustate); + UINT8 mask = FETCH(cpustate); + UINT8 r = READ8(cpustate, d) & ~mask; + WRITE8(cpustate, d, r); + CLEAR_NZV(cpustate); + SET_N8(r); + SET_Z8(r); + CYCLES(cpustate, 6); +} + /* BCLR INDX 0x1d */ static void HC11OP(bclr_indx)(hc11_state *cpustate) { @@ -967,6 +1001,19 @@ static void HC11OP(brn)(hc11_state *cpustate) CYCLES(cpustate, 3); } +/* BSET DIR 0x14 */ +static void HC11OP(bset_dir)(hc11_state *cpustate) +{ + UINT8 d = FETCH(cpustate); + UINT8 mask = FETCH(cpustate); + UINT8 r = READ8(cpustate, d) | mask; + WRITE8(cpustate, d, r); + CLEAR_NZV(cpustate); + SET_N8(r); + SET_Z8(r); + CYCLES(cpustate, 6); +} + /* BSET INDX 0x1c */ static void HC11OP(bset_indx)(hc11_state *cpustate) { diff --git a/src/emu/cpu/mc68hc11/hc11ops.h b/src/emu/cpu/mc68hc11/hc11ops.h index c9d4b279f20..dea89b70ea9 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.h +++ b/src/emu/cpu/mc68hc11/hc11ops.h @@ -49,7 +49,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] = { 0x18, 0xe4, HC11OP(andb_indy) }, { 0, 0x48, HC11OP(asla) }, { 0, 0x58, HC11OP(aslb) }, -// { 0, 0x78, HC11OP(asl_ext) }, + { 0, 0x78, HC11OP(asl_ext) }, // { 0, 0x68, HC11OP(asl_indx) }, // { 0x18, 0x68, HC11OP(asl_indy) }, // { 0, 0x47, HC11OP(asra) }, @@ -58,7 +58,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] = // { 0, 0x67, HC11OP(asr_indx) }, // { 0x18, 0x67, HC11OP(asr_indy) }, { 0, 0x24, HC11OP(bcc) }, -// { 0, 0x15, HC11OP(bclr_dir) }, + { 0, 0x15, HC11OP(bclr_dir) }, { 0, 0x1d, HC11OP(bclr_indx) }, // { 0x18, 0x1d, HC11OP(bclr_indy) }, { 0, 0x25, HC11OP(bcs) }, @@ -90,7 +90,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] = { 0, 0x12, HC11OP(brset_dir) }, { 0, 0x1e, HC11OP(brset_indx) }, // { 0x18, 0x1e, HC11OP(brset_indy) }, -// { 0, 0x14, HC11OP(bset_dir) }, + { 0, 0x14, HC11OP(bset_dir) }, { 0, 0x1c, HC11OP(bset_indx) }, // { 0x18, 0x1c, HC11OP(bset_indy) }, { 0, 0x8d, HC11OP(bsr) }, diff --git a/src/mess/drivers/alphasma.c b/src/mess/drivers/alphasma.c index 8ce61267fa0..df79481de3d 100644 --- a/src/mess/drivers/alphasma.c +++ b/src/mess/drivers/alphasma.c @@ -66,6 +66,7 @@ static MACHINE_CONFIG_START( alphasmart, alphasmart_state ) MCFG_CPU_PROGRAM_MAP(alphasmart_mem) MCFG_CPU_IO_MAP(alphasmart_io) MCFG_CPU_CONFIG(alphasmart_hc11_config) + MCFG_CPU_PERIODIC_INT(irq0_line_hold, 50) /* video hardware */ MCFG_SCREEN_ADD("screen", LCD) |