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authorGravatarGravatar Miodrag Milanovic <mmicko@gmail.com>2016-07-27 09:26:22 +0200
committerGravatarGravatar Miodrag Milanovic <mmicko@gmail.com>2016-07-27 09:26:22 +0200
commit4887ce18443a51fd2a861da959082ad346ff4ee2 (patch) (github)
treef21e5096b569bff399a6e03c09715502ef859c34 /src
parent385f433cf4f7c3a2fa6012536a479de6ddddc68a (diff)
downloadmame-4887ce18443a51fd2a861da959082ad346ff4ee2.tar.bz2
mame-4887ce18443a51fd2a861da959082ad346ff4ee2.zip
Cleanups and version bump
Diffstat (limited to 'src')
-rw-r--r--src/devices/bus/a7800/a78_slot.cpp2
-rw-r--r--src/devices/bus/bbc/1mhzbus/1mhzbus.cpp22
-rw-r--r--src/devices/bus/bbc/analogue/analogue.cpp4
-rw-r--r--src/devices/bus/bbc/tube/tube.cpp24
-rw-r--r--src/devices/bus/bbc/userport/userport.cpp6
-rw-r--r--src/devices/bus/electron/m2105.cpp2
-rw-r--r--src/devices/bus/isa/p1_sound.cpp18
-rw-r--r--src/devices/bus/isa/p1_sound.h18
-rw-r--r--src/devices/bus/ti99_peb/ti_rs232.h2
-rw-r--r--src/devices/cpu/alto2/alto2cpu.cpp2
-rw-r--r--src/devices/cpu/m6809/hd6309.cpp7
-rw-r--r--src/devices/cpu/m6809/m6809.cpp10
-rw-r--r--src/devices/cpu/m6809/m6809.h4
-rw-r--r--src/devices/cpu/mcs51/mcs51.cpp2
-rw-r--r--src/devices/cpu/sparc/mb86901.cpp20
-rw-r--r--src/devices/cpu/sparc/sparc.h4
-rw-r--r--src/devices/machine/68230pit.cpp148
-rw-r--r--src/devices/machine/68230pit.h46
-rw-r--r--src/devices/machine/fga002.cpp202
-rw-r--r--src/devices/machine/fga002.h231
-rw-r--r--src/devices/machine/hp_taco.cpp4
-rw-r--r--src/devices/machine/input_merger.cpp8
-rw-r--r--src/devices/machine/input_merger.h2
-rw-r--r--src/devices/machine/pdc.cpp1
-rw-r--r--src/devices/machine/scnxx562.cpp494
-rw-r--r--src/devices/machine/scnxx562.h90
-rw-r--r--src/devices/machine/z80scc.cpp48
-rw-r--r--src/devices/sound/qs1000.h2
-rw-r--r--src/devices/sound/ym2151.cpp2
-rw-r--r--src/devices/sound/ym2413.cpp2
-rw-r--r--src/devices/sound/ym2413.h2
-rw-r--r--src/devices/video/ef9365.cpp2
-rw-r--r--src/devices/video/zeus2.cpp12
-rw-r--r--src/devices/video/zeus2.h2
-rw-r--r--src/emu/debug/debugcpu.h2
-rw-r--r--src/emu/debug/dvstate.cpp2
-rw-r--r--src/emu/didisasm.h1
-rw-r--r--src/emu/diimage.cpp96
-rw-r--r--src/emu/diimage.h8
-rw-r--r--src/emu/softlist.h14
-rw-r--r--src/frontend/mame/ui/imgcntrl.h20
-rw-r--r--src/frontend/mame/ui/widgets.cpp6
-rw-r--r--src/frontend/mame/ui/widgets.h4
-rw-r--r--src/lib/formats/acorn_dsk.cpp2
-rw-r--r--src/lib/util/aviio.cpp10
-rw-r--r--src/lib/util/corefile.cpp2
-rw-r--r--src/lib/util/opresolv.cpp65
-rw-r--r--src/lib/util/opresolv.h1
-rw-r--r--src/lib/util/unicode.cpp2
-rw-r--r--src/lib/util/zippath.cpp74
-rw-r--r--src/mame/drivers/bfm_sc4.cpp2
-rw-r--r--src/mame/drivers/chihiro.cpp8
-rw-r--r--src/mame/drivers/ddenlovr.cpp16
-rw-r--r--src/mame/drivers/dynax.cpp66
-rw-r--r--src/mame/drivers/epos.cpp10
-rw-r--r--src/mame/drivers/esh.cpp4
-rw-r--r--src/mame/drivers/expro02.cpp2
-rw-r--r--src/mame/drivers/fccpu30.cpp16
-rw-r--r--src/mame/drivers/fcisio.cpp54
-rw-r--r--src/mame/drivers/fromance.cpp118
-rw-r--r--src/mame/drivers/galaxian.cpp4
-rw-r--r--src/mame/drivers/goldstar.cpp10
-rw-r--r--src/mame/drivers/hk68v10.cpp6
-rw-r--r--src/mame/drivers/hnayayoi.cpp2
-rw-r--r--src/mame/drivers/homedata.cpp64
-rw-r--r--src/mame/drivers/ibmpcjr.cpp2
-rw-r--r--src/mame/drivers/itech32.cpp2
-rw-r--r--src/mame/drivers/legionna.cpp12
-rw-r--r--src/mame/drivers/nbmj8688.cpp44
-rw-r--r--src/mame/drivers/nbmj8891.cpp34
-rw-r--r--src/mame/drivers/nbmj8991.cpp26
-rw-r--r--src/mame/drivers/nbmj9195.cpp38
-rw-r--r--src/mame/drivers/ohmygod.cpp2
-rw-r--r--src/mame/drivers/poisk1.cpp2
-rw-r--r--src/mame/drivers/rainbow.cpp204
-rw-r--r--src/mame/drivers/seibuspi.cpp4
-rw-r--r--src/mame/drivers/seicupbl.cpp32
-rw-r--r--src/mame/drivers/sliver.cpp4
-rw-r--r--src/mame/drivers/sm7238.cpp26
-rw-r--r--src/mame/drivers/sun4.cpp182
-rw-r--r--src/mame/drivers/tiamc1.cpp32
-rw-r--r--src/mame/drivers/tv990.cpp46
-rw-r--r--src/mame/includes/bfm_sc4.h14
-rw-r--r--src/mame/includes/legionna.h1
-rw-r--r--src/mame/includes/vendetta.h2
-rw-r--r--src/mame/machine/archimds.cpp2
-rw-r--r--src/mame/machine/opwolf.cpp28
-rw-r--r--src/mame/machine/seibucop/seibucop.cpp64
-rw-r--r--src/mame/machine/seibucop/seibucop.h2
-rw-r--r--src/mame/machine/seicop.cpp56
-rw-r--r--src/mame/machine/seicop.h4
-rw-r--r--src/mame/mame.lst12
-rw-r--r--src/mame/video/epos.cpp2
-rw-r--r--src/mame/video/gime.cpp4
-rw-r--r--src/mame/video/itech32.cpp2
-rw-r--r--src/mame/video/legionna.cpp32
-rw-r--r--src/mame/video/pcd.cpp2
-rw-r--r--src/mame/video/vtvideo.cpp28
-rw-r--r--src/osd/modules/file/windir.cpp2
-rw-r--r--src/osd/modules/input/input_common.cpp2
-rw-r--r--src/osd/modules/input/input_x11.cpp2
-rw-r--r--src/osd/modules/render/d3d/d3dhlsl.cpp6
-rw-r--r--src/osd/modules/render/drawbgfx.cpp4
-rw-r--r--src/osd/modules/render/drawd3d.cpp4
-rw-r--r--src/osd/osdcore.h20
-rw-r--r--src/osd/windows/video.cpp2
106 files changed, 1558 insertions, 1567 deletions
diff --git a/src/devices/bus/a7800/a78_slot.cpp b/src/devices/bus/a7800/a78_slot.cpp
index c5170169ce4..9e028502170 100644
--- a/src/devices/bus/a7800/a78_slot.cpp
+++ b/src/devices/bus/a7800/a78_slot.cpp
@@ -22,7 +22,7 @@
even if not all carts use all of them (in particular no cart type
seems to use access to the ranges $0500 to $0fff and $2800 to $2fff)
-
+
***********************************************************************************************************/
diff --git a/src/devices/bus/bbc/1mhzbus/1mhzbus.cpp b/src/devices/bus/bbc/1mhzbus/1mhzbus.cpp
index 0c5c01f965f..11e97624e54 100644
--- a/src/devices/bus/bbc/1mhzbus/1mhzbus.cpp
+++ b/src/devices/bus/bbc/1mhzbus/1mhzbus.cpp
@@ -98,15 +98,15 @@ void bbc_1mhzbus_slot_device::device_reset()
SLOT_INTERFACE_START( bbc_1mhzbus_devices )
-// SLOT_INTERFACE("teletext", BBC_TELETEXT) /* Acorn ANE01 Teletext Adapter */
-// SLOT_INTERFACE("ieee488", BBC_IEEE488) /* Acorn ANK01 IEEE488 Interface */
-// SLOT_INTERFACE("music500", BBC_MUSIC500) /* Acorn ANV02 Music500 */
-// SLOT_INTERFACE("music2000", BBC_MUSIC2000) /* Hybrid Music 2000 MIDI Interface */
-// SLOT_INTERFACE("music3000", BBC_MUSIC3000) /* Hybrid Music 3000 Expander */
-// SLOT_INTERFACE("music5000", BBC_MUSIC5000) /* Hybrid Music 5000 Synthesiser */
-// SLOT_INTERFACE("opus3", BBC_OPUS3) /* Opus Challenger 3 */
-// SLOT_INTERFACE("torchg400", BBC_TORCHG400) /* Torch Graduate G400 */
-// SLOT_INTERFACE("torchg800", BBC_TORCHG800) /* Torch Graduate G800 */
-// SLOT_INTERFACE("beebsid", BBC_BEEBSID) /* BeebSID */
-// SLOT_INTERFACE("prisma3", BBC_PRISMA3) /* Prisma 3 - Millipede 1989 */
+// SLOT_INTERFACE("teletext", BBC_TELETEXT) /* Acorn ANE01 Teletext Adapter */
+// SLOT_INTERFACE("ieee488", BBC_IEEE488) /* Acorn ANK01 IEEE488 Interface */
+// SLOT_INTERFACE("music500", BBC_MUSIC500) /* Acorn ANV02 Music500 */
+// SLOT_INTERFACE("music2000", BBC_MUSIC2000) /* Hybrid Music 2000 MIDI Interface */
+// SLOT_INTERFACE("music3000", BBC_MUSIC3000) /* Hybrid Music 3000 Expander */
+// SLOT_INTERFACE("music5000", BBC_MUSIC5000) /* Hybrid Music 5000 Synthesiser */
+// SLOT_INTERFACE("opus3", BBC_OPUS3) /* Opus Challenger 3 */
+// SLOT_INTERFACE("torchg400", BBC_TORCHG400) /* Torch Graduate G400 */
+// SLOT_INTERFACE("torchg800", BBC_TORCHG800) /* Torch Graduate G800 */
+// SLOT_INTERFACE("beebsid", BBC_BEEBSID) /* BeebSID */
+// SLOT_INTERFACE("prisma3", BBC_PRISMA3) /* Prisma 3 - Millipede 1989 */
SLOT_INTERFACE_END
diff --git a/src/devices/bus/bbc/analogue/analogue.cpp b/src/devices/bus/bbc/analogue/analogue.cpp
index 2ab1c4b8344..954e7a7e958 100644
--- a/src/devices/bus/bbc/analogue/analogue.cpp
+++ b/src/devices/bus/bbc/analogue/analogue.cpp
@@ -91,6 +91,6 @@ void bbc_analogue_slot_device::device_reset()
SLOT_INTERFACE_START( bbc_analogue_devices )
-// SLOT_INTERFACE("joystick", BBC_JOYSTICKS) /* Acorn ANH01 BBC Micro Joysticks */
-// SLOT_INTERFACE("quinkey", BBC_QUINKEY) /* Microwriter Quinkey */
+// SLOT_INTERFACE("joystick", BBC_JOYSTICKS) /* Acorn ANH01 BBC Micro Joysticks */
+// SLOT_INTERFACE("quinkey", BBC_QUINKEY) /* Microwriter Quinkey */
SLOT_INTERFACE_END
diff --git a/src/devices/bus/bbc/tube/tube.cpp b/src/devices/bus/bbc/tube/tube.cpp
index d0d473def07..8ce07531fcc 100644
--- a/src/devices/bus/bbc/tube/tube.cpp
+++ b/src/devices/bus/bbc/tube/tube.cpp
@@ -96,13 +96,13 @@ void bbc_tube_slot_device::device_reset()
SLOT_INTERFACE_START( bbc_tube_ext_devices )
-// SLOT_INTERFACE("6502copro", BBC_6502_COPRO) /* Acorn ANC01 6502 2nd processor */
-// SLOT_INTERFACE("z80copro", BBC_Z80_COPRO) /* Acorn ANC04 Z80 2nd processor */
-// SLOT_INTERFACE("32016copro", BBC_32016_COPRO) /* Acorn ANC05 32016 2nd processor */
-// SLOT_INTERFACE("cambcopro", BBC_CAMB_COPRO) /* Acorn ANC06 Cambridge Co-Processor */
-// SLOT_INTERFACE("armcopro", BBC_ARM_COPRO) /* Acorn ANC13 ARM Evaluation System */
-// SLOT_INTERFACE("unicopro", BBC_UNIVERSAL) /* Acorn ANC21 Universal 2nd Processor Unit */
-// SLOT_INTERFACE("a500copro", BBC_A500_COPRO) /* Acorn A500 2nd Processor */
+// SLOT_INTERFACE("6502copro", BBC_6502_COPRO) /* Acorn ANC01 6502 2nd processor */
+// SLOT_INTERFACE("z80copro", BBC_Z80_COPRO) /* Acorn ANC04 Z80 2nd processor */
+// SLOT_INTERFACE("32016copro", BBC_32016_COPRO) /* Acorn ANC05 32016 2nd processor */
+// SLOT_INTERFACE("cambcopro", BBC_CAMB_COPRO) /* Acorn ANC06 Cambridge Co-Processor */
+// SLOT_INTERFACE("armcopro", BBC_ARM_COPRO) /* Acorn ANC13 ARM Evaluation System */
+// SLOT_INTERFACE("unicopro", BBC_UNIVERSAL) /* Acorn ANC21 Universal 2nd Processor Unit */
+// SLOT_INTERFACE("a500copro", BBC_A500_COPRO) /* Acorn A500 2nd Processor */
SLOT_INTERFACE_END
@@ -118,8 +118,8 @@ SLOT_INTERFACE_END
SLOT_INTERFACE_START( bbc_tube_int_devices )
-// SLOT_INTERFACE("65c102copro", BBC_65C102_COPRO) /* Acorn ADC06 6502 co-processor */
-// SLOT_INTERFACE("80186copro", BBC_80186_COPRO) /* Acorn ADC08 80186 co-processor */
-// SLOT_INTERFACE("80286copro", BBC_80286_COPRO) /* Acorn ADC08 80286 co-processor */
-// SLOT_INTERFACE("arm7copro", BBC_ARM7_COPRO) /* Sprow ARM7 co-processor */
-SLOT_INTERFACE_END \ No newline at end of file
+// SLOT_INTERFACE("65c102copro", BBC_65C102_COPRO) /* Acorn ADC06 6502 co-processor */
+// SLOT_INTERFACE("80186copro", BBC_80186_COPRO) /* Acorn ADC08 80186 co-processor */
+// SLOT_INTERFACE("80286copro", BBC_80286_COPRO) /* Acorn ADC08 80286 co-processor */
+// SLOT_INTERFACE("arm7copro", BBC_ARM7_COPRO) /* Sprow ARM7 co-processor */
+SLOT_INTERFACE_END
diff --git a/src/devices/bus/bbc/userport/userport.cpp b/src/devices/bus/bbc/userport/userport.cpp
index b866348678b..e044e0177d4 100644
--- a/src/devices/bus/bbc/userport/userport.cpp
+++ b/src/devices/bus/bbc/userport/userport.cpp
@@ -96,7 +96,7 @@ UINT8 bbc_userport_device::read_portb()
SLOT_INTERFACE_START( bbc_userport_devices )
-// SLOT_INTERFACE("amxmouse", BBC_AMXMOUSE) /* AMX Mouse */
-// SLOT_INTERFACE("tracker", BBC_TRACKER) /* Acorn Tracker Ball */
-// SLOT_INTERFACE("music4000", BBC_MUSIC4000) /* Hybrid Music 4000 Keyboard */
+// SLOT_INTERFACE("amxmouse", BBC_AMXMOUSE) /* AMX Mouse */
+// SLOT_INTERFACE("tracker", BBC_TRACKER) /* Acorn Tracker Ball */
+// SLOT_INTERFACE("music4000", BBC_MUSIC4000) /* Hybrid Music 4000 Keyboard */
SLOT_INTERFACE_END
diff --git a/src/devices/bus/electron/m2105.cpp b/src/devices/bus/electron/m2105.cpp
index 8632d1ad154..6b6a701f7b5 100644
--- a/src/devices/bus/electron/m2105.cpp
+++ b/src/devices/bus/electron/m2105.cpp
@@ -50,7 +50,7 @@ ROM_END
//-------------------------------------------------
//static ADDRESS_MAP_START( m2105_mem, AS_IO, 8, electron_m2105_device )
-// AM_RANGE(0x30000, 0x3ffff) AM_MIRROR(0x4000) AM_ROM AM_REGION("m2105_rom", 0)
+// AM_RANGE(0x30000, 0x3ffff) AM_MIRROR(0x4000) AM_ROM AM_REGION("m2105_rom", 0)
//ADDRESS_MAP_END
diff --git a/src/devices/bus/isa/p1_sound.cpp b/src/devices/bus/isa/p1_sound.cpp
index 7629ee6fb7d..03499c77643 100644
--- a/src/devices/bus/isa/p1_sound.cpp
+++ b/src/devices/bus/isa/p1_sound.cpp
@@ -4,7 +4,7 @@
Poisk-1 sound card. DAC, ADC, MIDI in/out and 6 music channels.
- Memory-mapped, uses IRQ3 and IRQ7, no DMA.
+ Memory-mapped, uses IRQ3 and IRQ7, no DMA.
Copyright MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
@@ -36,7 +36,7 @@ static MACHINE_CONFIG_FRAGMENT( p1_sound )
MCFG_DEVICE_ADD("d14", PIT8253, 0)
MCFG_PIT8253_CLK0(XTAL_12_5MHz/10)
-// sampler at 10 KHz
+// sampler at 10 KHz
MCFG_PIT8253_OUT0_HANDLER(WRITELINE(p1_sound_device, sampler_sync))
MCFG_PIT8253_CLK1(XTAL_12_5MHz/10)
MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("midi", i8251_device, write_txc))
@@ -45,19 +45,19 @@ static MACHINE_CONFIG_FRAGMENT( p1_sound )
MCFG_DEVICE_ADD("d16", PIT8253, 0)
MCFG_PIT8253_CLK0(XTAL_12_5MHz/10)
-// MCFG_PIT8253_OUT0_HANDLER(XXX)
+// MCFG_PIT8253_OUT0_HANDLER(XXX)
MCFG_PIT8253_CLK1(XTAL_12_5MHz/10)
-// MCFG_PIT8253_OUT1_HANDLER(XXX)
+// MCFG_PIT8253_OUT1_HANDLER(XXX)
MCFG_PIT8253_CLK2(XTAL_12_5MHz/10)
-// MCFG_PIT8253_OUT2_HANDLER(XXX)
+// MCFG_PIT8253_OUT2_HANDLER(XXX)
MCFG_DEVICE_ADD("d17", PIT8253, 0)
MCFG_PIT8253_CLK0(XTAL_12_5MHz/10)
-// MCFG_PIT8253_OUT0_HANDLER(XXX)
+// MCFG_PIT8253_OUT0_HANDLER(XXX)
MCFG_PIT8253_CLK1(XTAL_12_5MHz/10)
-// MCFG_PIT8253_OUT1_HANDLER(XXX)
+// MCFG_PIT8253_OUT1_HANDLER(XXX)
MCFG_PIT8253_CLK2(XTAL_12_5MHz/10)
-// MCFG_PIT8253_OUT2_HANDLER(XXX)
+// MCFG_PIT8253_OUT2_HANDLER(XXX)
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_DAC_ADD("dac")
@@ -135,7 +135,7 @@ READ8_MEMBER( p1_sound_device::adc_r )
WRITE8_MEMBER( p1_sound_device::dac_w )
{
-// logerror("DAC write: %02x <- %02x\n", offset>>1, data);
+// logerror("DAC write: %02x <- %02x\n", offset>>1, data);
m_dac_data[offset>>1] = data;
m_isa->irq7_w(CLEAR_LINE);
}
diff --git a/src/devices/bus/isa/p1_sound.h b/src/devices/bus/isa/p1_sound.h
index d99669294c9..95a6878f395 100644
--- a/src/devices/bus/isa/p1_sound.h
+++ b/src/devices/bus/isa/p1_sound.h
@@ -54,15 +54,15 @@ protected:
virtual void device_reset() override;
private:
- UINT8 m_dac_data[16];
- int m_dac_ptr;
-
- required_device<dac_device> m_dac;
- optional_device<filter_rc_device> m_filter;
- required_device<i8251_device> m_midi;
- required_device<pit8253_device> m_d14;
- required_device<pit8253_device> m_d16;
- required_device<pit8253_device> m_d17;
+ UINT8 m_dac_data[16];
+ int m_dac_ptr;
+
+ required_device<dac_device> m_dac;
+ optional_device<filter_rc_device> m_filter;
+ required_device<i8251_device> m_midi;
+ required_device<pit8253_device> m_d14;
+ required_device<pit8253_device> m_d16;
+ required_device<pit8253_device> m_d17;
};
diff --git a/src/devices/bus/ti99_peb/ti_rs232.h b/src/devices/bus/ti99_peb/ti_rs232.h
index 129561d9bf5..f244843fc09 100644
--- a/src/devices/bus/ti99_peb/ti_rs232.h
+++ b/src/devices/bus/ti99_peb/ti_rs232.h
@@ -127,7 +127,7 @@ public:
bool is_reset_on_load() const override { return false; }
const char *image_interface() const override { return ""; }
const char *file_extensions() const override { return ""; }
-
+
protected:
virtual void device_start(void) override;
bool call_load() override;
diff --git a/src/devices/cpu/alto2/alto2cpu.cpp b/src/devices/cpu/alto2/alto2cpu.cpp
index 85e87765cf7..28db09474ef 100644
--- a/src/devices/cpu/alto2/alto2cpu.cpp
+++ b/src/devices/cpu/alto2/alto2cpu.cpp
@@ -832,7 +832,7 @@ void alto2_cpu_device::device_start()
m_madr_a91 = prom_load(machine(), &pl_madr_a91, memregion("madr_a91")->base());
#if DEBUG_ALU_A10_PROM
- // dump ALU a10 PROM after loading
+ // dump ALU a10 PROM after loading
for (UINT8 i = 0; i < 32; i++) {
UINT8 a = m_alu_a10[i];
printf("%03o: S3-S0:%u%u%u%u M:%u CI:%u T:%u ?:%u\n",
diff --git a/src/devices/cpu/m6809/hd6309.cpp b/src/devices/cpu/m6809/hd6309.cpp
index caba599adef..213464d90dc 100644
--- a/src/devices/cpu/m6809/hd6309.cpp
+++ b/src/devices/cpu/m6809/hd6309.cpp
@@ -26,11 +26,11 @@
machine must be twos complement
History:
-
-July 2016 ErikGav:
+
+July 2016 ErikGav:
Unify with 6809 pairs and quads (A+B=D, E+F=W, D+W=Q)
Initialize V register to $FFFF at startup
-
+
March 2013 NPW:
Rewrite of 6809/6309/Konami CPU; attempted to make cycle exact.
@@ -795,4 +795,3 @@ void hd6309_device::execute_run()
execute_one();
} while(m_icount > 0);
}
-
diff --git a/src/devices/cpu/m6809/m6809.cpp b/src/devices/cpu/m6809/m6809.cpp
index aa380c14e0f..c02450c1ea2 100644
--- a/src/devices/cpu/m6809/m6809.cpp
+++ b/src/devices/cpu/m6809/m6809.cpp
@@ -21,10 +21,10 @@
machine must be twos complement
History:
-
-July 2016 ErikGav:
- Unify with 6309 pairs and quads (A+B=D, E+F=W, D+W=Q)
-
+
+July 2016 ErikGav:
+ Unify with 6309 pairs and quads (A+B=D, E+F=W, D+W=Q)
+
March 2013 NPW:
Rewrite of 6809/6309/Konami CPU; attempted to make cycle exact.
@@ -147,7 +147,7 @@ void m6809_base_device::device_start()
state_add(M6809_CC, "CC", m_cc).mask(0xff);
state_add(M6809_DP, "DP", m_dp).mask(0xff);
- if (is_6809())
+ if (is_6809())
{
state_add(M6809_A, "A", m_q.r.a).mask(0xff);
state_add(M6809_B, "B", m_q.r.b).mask(0xff);
diff --git a/src/devices/cpu/m6809/m6809.h b/src/devices/cpu/m6809/m6809.h
index ebcde8f554d..8a2f5f9e400 100644
--- a/src/devices/cpu/m6809/m6809.h
+++ b/src/devices/cpu/m6809/m6809.h
@@ -141,14 +141,14 @@ protected:
union M6809Q
{
#ifdef LSB_FIRST
- union
+ union
{
struct { UINT8 f, e, b, a; };
struct { UINT16 w, d; };
} r;
struct { PAIR16 w, d; } p;
#else
- union
+ union
{
struct { UINT8 a, b, e, f; };
struct { UINT16 d, w; };
diff --git a/src/devices/cpu/mcs51/mcs51.cpp b/src/devices/cpu/mcs51/mcs51.cpp
index cb680438e96..48674fdb6b8 100644
--- a/src/devices/cpu/mcs51/mcs51.cpp
+++ b/src/devices/cpu/mcs51/mcs51.cpp
@@ -2101,7 +2101,7 @@ void mcs51_cpu_device::device_start()
/* ensure these pointers are set before get_info is called */
update_ptrs();
-
+
m_serial_rx_cb.resolve_safe(0);
m_serial_tx_cb.resolve_safe();
diff --git a/src/devices/cpu/sparc/mb86901.cpp b/src/devices/cpu/sparc/mb86901.cpp
index 8ed13db2778..1e9eafebcb1 100644
--- a/src/devices/cpu/sparc/mb86901.cpp
+++ b/src/devices/cpu/sparc/mb86901.cpp
@@ -695,9 +695,9 @@ void mb86901_device::execute_add(UINT32 op)
PSR |= (BIT31(result)) ? PSR_N_MASK : 0;
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= ((BIT31(rs1) && BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(rs1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
+ (!BIT31(rs1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
PSR |= ((BIT31(rs1) && BIT31(operand2)) ||
- (!BIT31(result) && (BIT31(rs1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (!BIT31(result) && (BIT31(rs1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
}
}
@@ -740,8 +740,8 @@ void mb86901_device::execute_taddcc(UINT32 op)
UINT32 result = rs1 + operand2;
bool temp_v = (BIT31(rs1) && BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(rs1) && !BIT31(operand2) && BIT31(result)) ||
- ((rs1 & 3) != 0 || (operand2 & 3) != 0) ? true : false;
+ (!BIT31(rs1) && !BIT31(operand2) && BIT31(result)) ||
+ ((rs1 & 3) != 0 || (operand2 & 3) != 0) ? true : false;
if (TADDCCTV && temp_v)
{
@@ -755,7 +755,7 @@ void mb86901_device::execute_taddcc(UINT32 op)
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= temp_v ? PSR_V_MASK : 0;
PSR |= ((BIT31(rs1) && BIT31(operand2)) ||
- (!BIT31(result) && (BIT31(rs1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (!BIT31(result) && (BIT31(rs1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
if (RD != 0)
RDREG = result;
@@ -810,9 +810,9 @@ void mb86901_device::execute_sub(UINT32 op)
PSR |= (BIT31(result)) ? PSR_N_MASK : 0;
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= ((BIT31(rs1) && !BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(rs1) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
+ (!BIT31(rs1) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0;
PSR |= ((!BIT31(rs1) && BIT31(operand2)) ||
- (BIT31(result) && (!BIT31(rs1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (BIT31(result) && (!BIT31(rs1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
}
}
@@ -856,8 +856,8 @@ void mb86901_device::execute_tsubcc(UINT32 op)
UINT32 result = rs1 - operand2;
bool temp_v = (BIT31(rs1) && !BIT31(operand2) && !BIT31(result)) ||
- (!BIT31(rs1) && BIT31(operand2) && BIT31(result)) ||
- ((rs1 & 3) != 0 || (operand2 & 3) != 0) ? true : false;
+ (!BIT31(rs1) && BIT31(operand2) && BIT31(result)) ||
+ ((rs1 & 3) != 0 || (operand2 & 3) != 0) ? true : false;
if (TSUBCCTV && temp_v)
{
@@ -871,7 +871,7 @@ void mb86901_device::execute_tsubcc(UINT32 op)
PSR |= (result == 0) ? PSR_Z_MASK : 0;
PSR |= temp_v ? PSR_V_MASK : 0;
PSR |= ((!BIT31(rs1) && BIT31(operand2)) ||
- (BIT31(result) && (!BIT31(rs1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
+ (BIT31(result) && (!BIT31(rs1) || BIT31(operand2)))) ? PSR_C_MASK : 0;
if (RD != 0)
RDREG = result;
diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h
index fa8b9dd234b..424305a1924 100644
--- a/src/devices/cpu/sparc/sparc.h
+++ b/src/devices/cpu/sparc/sparc.h
@@ -11,8 +11,8 @@
#include "sparcdasm.h"
-#define SPARCV8 (0)
-#define LOG_FCODES (0)
+#define SPARCV8 (0)
+#define LOG_FCODES (0)
#if LOG_FCODES
#include <map>
diff --git a/src/devices/machine/68230pit.cpp b/src/devices/machine/68230pit.cpp
index 3354738f954..fa7142c2306 100644
--- a/src/devices/machine/68230pit.cpp
+++ b/src/devices/machine/68230pit.cpp
@@ -5,13 +5,13 @@
* Motorola MC68230 PI/T Parallell Interface and Timer
*
* PORT MODES INCLUDE :
-* - BIT I/O
+* - BIT I/O
* - UNIDIRECTIONAL 8 BIT AND 16 BIT
-* - BIDIRECTIONAL 8 BIT AND 16 BIT
-* PROGRAMMABLE HANDSHAKING OPTIONS
-* 24-BIT PROGRAMMABLE TIMER MODES
-* FIVE SEPARATE INTERRUPT VECTORS SEPARATE PORT AND TIMER INTERRUPT SERVICE REQUESTS
-* REGISTERS AREREAD/WRITEAND DIRECTLY ADDRESSABLE
+* - BIDIRECTIONAL 8 BIT AND 16 BIT
+* PROGRAMMABLE HANDSHAKING OPTIONS
+* 24-BIT PROGRAMMABLE TIMER MODES
+* FIVE SEPARATE INTERRUPT VECTORS SEPARATE PORT AND TIMER INTERRUPT SERVICE REQUESTS
+* REGISTERS AREREAD/WRITEAND DIRECTLY ADDRESSABLE
* REGISTERS ARE ADDRESSED FOR MOVEP (Move Peripheral) AND DMAC COMPATIBILITY
*
* Revisions: 2015-07-15 JLE initial
@@ -77,9 +77,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
, m_tcr(0)
, m_tivr(0)
, m_cpr(0)
- // , m_cprh(0) // Collectivelly handled by m_cpr
- // , m_cprm(0) // Collectivelly handled by m_cpr
- // , m_cprl(0) // Collectivelly handled by m_cpr
+ // , m_cprh(0) // Collectivelly handled by m_cpr
+ // , m_cprm(0) // Collectivelly handled by m_cpr
+ // , m_cprl(0) // Collectivelly handled by m_cpr
, m_cntr(0)
, m_tsr(0)
{
@@ -113,9 +113,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
, m_tcr(0)
, m_tivr(0)
, m_cpr(0)
- // , m_cprh(0) // Collectivelly handled by m_cpr
- // , m_cprm(0) // Collectivelly handled by m_cpr
- // , m_cprl(0) // Collectivelly handled by m_cpr
+ // , m_cprh(0) // Collectivelly handled by m_cpr
+ // , m_cprm(0) // Collectivelly handled by m_cpr
+ // , m_cprl(0) // Collectivelly handled by m_cpr
, m_cntr(0)
, m_tsr(0)
{
@@ -193,9 +193,9 @@ void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32
{
switch(id)
{
- case TIMER_ID_PIT:
+ case TIMER_ID_PIT:
if (m_cntr-- == 0) // Zero detect
- {
+ {
/* TODO: Check mode and use preload value if required or just rollover 24 bit */
if ((m_tcr & REG_TCR_ZD) == 0)
m_cntr = m_cpr;
@@ -203,9 +203,9 @@ void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32
m_cntr &= 0xffffff;
}
break;
- default:
- LOG(("Unhandled Timer ID %d\n", id));
- break;
+ default:
+ LOG(("Unhandled Timer ID %d\n", id));
+ break;
}
}
@@ -400,21 +400,21 @@ void pit68230_device::wr_pitreg_tcr(UINT8 data)
switch (m_tcr & REG_TCR_TOUT_TIACK_MASK)
{
case REG_TCR_PC3_PC7:
- case REG_TCR_PC3_PC7_DC: LOG(("- PC3 and PC7 used as I/O pins\n")); break;
+ case REG_TCR_PC3_PC7_DC: LOG(("- PC3 and PC7 used as I/O pins\n")); break;
case REG_TCR_TOUT_PC7_SQ:
- case REG_TCR_TOUT_PC7_SQ_DC: LOG(("- PC3 used as SQuare wave TOUT and PC7 used as I/O pin - not supported yet\n")); sqr = 1; break;
- case REG_TCR_TOUT_TIACK: LOG(("- PC3 used as TOUT and PC7 used as TIACK - not supported yet\n")); tout = 1; tiack = 1; break;
- case REG_TCR_TOUT_TIACK_INT: LOG(("- PC3 used as TOUT and PC7 used as TIACK, Interrupts enabled - not supported yet\n")); tout = 1; tiack = 1; irq = 1; break;
- case REG_TCR_TOUT_PC7: LOG(("- PC3 used as TOUT and PC7 used as I/O pin - not supported yet\n")); break;
- case REG_TCR_TOUT_PC7_INT: LOG(("- PC3 used as TOUT and PC7 used as I/O pin, Interrupts enabled - not supported yet\n")); break;
+ case REG_TCR_TOUT_PC7_SQ_DC: LOG(("- PC3 used as SQuare wave TOUT and PC7 used as I/O pin - not supported yet\n")); sqr = 1; break;
+ case REG_TCR_TOUT_TIACK: LOG(("- PC3 used as TOUT and PC7 used as TIACK - not supported yet\n")); tout = 1; tiack = 1; break;
+ case REG_TCR_TOUT_TIACK_INT: LOG(("- PC3 used as TOUT and PC7 used as TIACK, Interrupts enabled - not supported yet\n")); tout = 1; tiack = 1; irq = 1; break;
+ case REG_TCR_TOUT_PC7: LOG(("- PC3 used as TOUT and PC7 used as I/O pin - not supported yet\n")); break;
+ case REG_TCR_TOUT_PC7_INT: LOG(("- PC3 used as TOUT and PC7 used as I/O pin, Interrupts enabled - not supported yet\n")); break;
}
switch (m_tcr & REG_TCR_CC_MASK)
{
- case REG_TCR_CC_PC2_CLK_PSC: LOG(("- PC2 used as I/O pin,CLK and x32 prescaler are used\n")); clk = 1; psc = 1; break;
- case REG_TCR_CC_TEN_CLK_PSC: LOG(("- PC2 used as Timer enable/disable, CLK and presacaler are used\n")); pen = 1; clk = 1; psc = 1; break;
- case REG_TCR_CC_TIN_PSC: LOG(("- PC2 used as Timer clock and the presacaler is used - not supported yet\n")); psc = 1; break;
- case REG_TCR_CC_TIN_RAW: LOG(("- PC2 used as Timer clock and the presacaler is NOT used - not supported yet\n")); break;
+ case REG_TCR_CC_PC2_CLK_PSC: LOG(("- PC2 used as I/O pin,CLK and x32 prescaler are used\n")); clk = 1; psc = 1; break;
+ case REG_TCR_CC_TEN_CLK_PSC: LOG(("- PC2 used as Timer enable/disable, CLK and presacaler are used\n")); pen = 1; clk = 1; psc = 1; break;
+ case REG_TCR_CC_TIN_PSC: LOG(("- PC2 used as Timer clock and the presacaler is used - not supported yet\n")); psc = 1; break;
+ case REG_TCR_CC_TIN_RAW: LOG(("- PC2 used as Timer clock and the presacaler is NOT used - not supported yet\n")); break;
}
LOG(("%s", m_tcr & REG_TCR_ZR ? "- Spec violation, should always be 0!\n" : ""));
LOG(("- Timer %s when reaching 0 (zero)\n", m_tcr & REG_TCR_ZD ? "rolls over" : "reload the preload values"));
@@ -475,29 +475,29 @@ WRITE8_MEMBER (pit68230_device::write)
{
LOG(("%s %s \n",tag(), FUNCNAME));
switch (offset) {
- case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
- case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
- case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
- case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
- case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
- case PIT_68230_PIVR: wr_pitreg_pivr(data); break;
- case PIT_68230_PACR: wr_pitreg_pacr(data); break;
- case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
- case PIT_68230_PADR: wr_pitreg_padr(data); break;
- case PIT_68230_PBDR: wr_pitreg_pbdr(data); break;
- case PIT_68230_PAAR: break; // Ignores write per spec, read only register
- case PIT_68230_PBAR: break; // Ignores write per spec, read only register
- case PIT_68230_PCDR: wr_pitreg_pcdr(data); break;
- case PIT_68230_PSR: wr_pitreg_psr(data); break;
- case PIT_68230_TCR: wr_pitreg_tcr(data); break;
- case PIT_68230_TIVR: wr_pitreg_tivr(data); break;
- case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
- case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
- case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
- case PIT_68230_CNTRH: break; // Ignores write per spec, read only register
- case PIT_68230_CNTRM: break; // Ignores write per spec, read only register
- case PIT_68230_CNTRL: break; // Ignores write per spec, read only register
- case PIT_68230_TSR: wr_pitreg_tsr(data); break;
+ case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
+ case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
+ case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
+ case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
+ case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
+ case PIT_68230_PIVR: wr_pitreg_pivr(data); break;
+ case PIT_68230_PACR: wr_pitreg_pacr(data); break;
+ case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
+ case PIT_68230_PADR: wr_pitreg_padr(data); break;
+ case PIT_68230_PBDR: wr_pitreg_pbdr(data); break;
+ case PIT_68230_PAAR: break; // Ignores write per spec, read only register
+ case PIT_68230_PBAR: break; // Ignores write per spec, read only register
+ case PIT_68230_PCDR: wr_pitreg_pcdr(data); break;
+ case PIT_68230_PSR: wr_pitreg_psr(data); break;
+ case PIT_68230_TCR: wr_pitreg_tcr(data); break;
+ case PIT_68230_TIVR: wr_pitreg_tivr(data); break;
+ case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
+ case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
+ case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
+ case PIT_68230_CNTRH: break; // Ignores write per spec, read only register
+ case PIT_68230_CNTRM: break; // Ignores write per spec, read only register
+ case PIT_68230_CNTRL: break; // Ignores write per spec, read only register
+ case PIT_68230_TSR: wr_pitreg_tsr(data); break;
default:
LOG (("Unhandled Write of %02x to register %02x", data, offset));
}
@@ -601,7 +601,7 @@ UINT8 pit68230_device::rr_pitreg_pcdr()
return m_pcdr;
}
-/* The port A alternate register is an alternate register for reading the port A pins.
+/* The port A alternate register is an alternate register for reading the port A pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
the instantaneous pin level is read and no input latching is performed except at the
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
@@ -697,29 +697,29 @@ READ8_MEMBER (pit68230_device::read){
UINT8 data;
switch (offset) {
- case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
- case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
- case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
- case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
- case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
- case PIT_68230_PIVR: data = rr_pitreg_pivr(); break;
- case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
- case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
- case PIT_68230_PADR: data = rr_pitreg_padr(); break;
- case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
- case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
- case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
- case PIT_68230_PCDR: data = rr_pitreg_pcdr(); break;
- case PIT_68230_PSR: data = rr_pitreg_psr(); break;
- case PIT_68230_TCR: data = rr_pitreg_tcr(); break;
- case PIT_68230_TIVR: data = rr_pitreg_tivr(); break;
- case PIT_68230_CPRH: data = rr_pitreg_cprh(); break;
- case PIT_68230_CPRM: data = rr_pitreg_cprm(); break;
- case PIT_68230_CPRL: data = rr_pitreg_cprl(); break;
- case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
- case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
- case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
- case PIT_68230_TSR: data = rr_pitreg_tsr(); break;
+ case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
+ case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
+ case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
+ case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
+ case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
+ case PIT_68230_PIVR: data = rr_pitreg_pivr(); break;
+ case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
+ case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
+ case PIT_68230_PADR: data = rr_pitreg_padr(); break;
+ case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
+ case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
+ case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
+ case PIT_68230_PCDR: data = rr_pitreg_pcdr(); break;
+ case PIT_68230_PSR: data = rr_pitreg_psr(); break;
+ case PIT_68230_TCR: data = rr_pitreg_tcr(); break;
+ case PIT_68230_TIVR: data = rr_pitreg_tivr(); break;
+ case PIT_68230_CPRH: data = rr_pitreg_cprh(); break;
+ case PIT_68230_CPRM: data = rr_pitreg_cprm(); break;
+ case PIT_68230_CPRL: data = rr_pitreg_cprl(); break;
+ case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
+ case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
+ case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
+ case PIT_68230_TSR: data = rr_pitreg_tsr(); break;
default:
LOG (("Unhandled read register %02x\n", offset));
data = 0;
diff --git a/src/devices/machine/68230pit.h b/src/devices/machine/68230pit.h
index 0c304bd1970..06736741867 100644
--- a/src/devices/machine/68230pit.h
+++ b/src/devices/machine/68230pit.h
@@ -174,23 +174,23 @@ class pit68230_device : public device_t//, public device_execute_interface
protected:
enum {
- REG_TCR_ENABLE = 0x01,
- REG_TCR_CC_MASK = 0x06,
- REG_TCR_CC_PC2_CLK_PSC = 0x00,
- REG_TCR_CC_TEN_CLK_PSC = 0x02,
- REG_TCR_CC_TIN_PSC = 0x04,
- REG_TCR_CC_TIN_RAW = 0x06,
- REG_TCR_ZR = 0x08,
- REG_TCR_ZD = 0x10,
- REG_TCR_TOUT_TIACK_MASK = 0xe0, // 1 1 1
- REG_TCR_PC3_PC7 = 0x00, // 0 0 0
- REG_TCR_PC3_PC7_DC = 0x20, // 0 0 1
- REG_TCR_TOUT_PC7_SQ = 0x40, // 0 1 0
- REG_TCR_TOUT_PC7_SQ_DC = 0x60, // 0 1 1
- REG_TCR_TOUT_TIACK = 0x80, // 1 0 0
- REG_TCR_TOUT_TIACK_INT = 0xa0, // 1 0 1
- REG_TCR_TOUT_PC7 = 0xc0, // 1 1 0
- REG_TCR_TOUT_PC7_INT = 0xe0, // 1 1 1
+ REG_TCR_ENABLE = 0x01,
+ REG_TCR_CC_MASK = 0x06,
+ REG_TCR_CC_PC2_CLK_PSC = 0x00,
+ REG_TCR_CC_TEN_CLK_PSC = 0x02,
+ REG_TCR_CC_TIN_PSC = 0x04,
+ REG_TCR_CC_TIN_RAW = 0x06,
+ REG_TCR_ZR = 0x08,
+ REG_TCR_ZD = 0x10,
+ REG_TCR_TOUT_TIACK_MASK = 0xe0, // 1 1 1
+ REG_TCR_PC3_PC7 = 0x00, // 0 0 0
+ REG_TCR_PC3_PC7_DC = 0x20, // 0 0 1
+ REG_TCR_TOUT_PC7_SQ = 0x40, // 0 1 0
+ REG_TCR_TOUT_PC7_SQ_DC = 0x60, // 0 1 1
+ REG_TCR_TOUT_TIACK = 0x80, // 1 0 0
+ REG_TCR_TOUT_TIACK_INT = 0xa0, // 1 0 1
+ REG_TCR_TOUT_PC7 = 0xc0, // 1 1 0
+ REG_TCR_TOUT_PC7_INT = 0xe0, // 1 1 1
};
// device-level overrides
@@ -217,18 +217,18 @@ protected:
UINT8 m_paddr; // Port A Data Direction register
UINT8 m_pbddr; // Port B Data Direction register
UINT8 m_pcddr; // Port C Data Direction register
- UINT8 m_pivr; // Ports Interrupt vector
+ UINT8 m_pivr; // Ports Interrupt vector
UINT8 m_pacr; // Port A Control register
UINT8 m_pbcr; // Port B Control register
UINT8 m_padr; // Port A Data register
UINT8 m_pbdr; // Port B Data register
UINT8 m_pcdr; // Port C Data register
UINT8 m_psr; // Port Status Register
- UINT8 m_tcr; // Timer Control Register
- UINT8 m_tivr; // Timer Interrupt Vector register
- int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
- int m_cntr; // - The 24 bit Counter
- UINT8 m_tsr; // Timer Status Register
+ UINT8 m_tcr; // Timer Control Register
+ UINT8 m_tivr; // Timer Interrupt Vector register
+ int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
+ int m_cntr; // - The 24 bit Counter
+ UINT8 m_tsr; // Timer Status Register
// Timers
emu_timer *pit_timer;
diff --git a/src/devices/machine/fga002.cpp b/src/devices/machine/fga002.cpp
index 4cd77414612..ceb54043211 100644
--- a/src/devices/machine/fga002.cpp
+++ b/src/devices/machine/fga002.cpp
@@ -4,31 +4,31 @@
*
* Force Computer FGA-002 Force Gate Array
*
-* Documetation: http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/201559_FGA-002_Nov96.pdf
+* Documetation: http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/201559_FGA-002_Nov96.pdf
*
-* The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and containing 24,000 gates in a 281 pin PGA
-* package. It provides interfaces to the 68020/30 microprocessor as well as a VMEbus compatible interface.
-* The auxilary interface of the gate array is a high speed data channel used by the internal 32 bit DMA controller. The interface
-* allows data transfer rates of up to 6 MByte/second. The timing of the local I/O interface is programmable and provides
-* easy interfacing of local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly connected or
-* connected via buffers to the gate array allowing easy implementation and usage. The gate array registers are programmed by the local CPU.
+* The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and containing 24,000 gates in a 281 pin PGA
+* package. It provides interfaces to the 68020/30 microprocessor as well as a VMEbus compatible interface.
+* The auxilary interface of the gate array is a high speed data channel used by the internal 32 bit DMA controller. The interface
+* allows data transfer rates of up to 6 MByte/second. The timing of the local I/O interface is programmable and provides
+* easy interfacing of local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly connected or
+* connected via buffers to the gate array allowing easy implementation and usage. The gate array registers are programmed by the local CPU.
*
-* FEATURES:
-* - Programmable decoding for CPU and VME access to the local main memory
-* - Interrupt management for internal and external interrupt sources
-* - 32 bit multi-port DMA Controller
-* - FORCE Message Broadcast slave interface with 2 message channels
-* - 8 interrupt capable MAILBOXES
-* - 8 bit TIMER with 16 selectable internal source clocks
+* FEATURES:
+* - Programmable decoding for CPU and VME access to the local main memory
+* - Interrupt management for internal and external interrupt sources
+* - 32 bit multi-port DMA Controller
+* - FORCE Message Broadcast slave interface with 2 message channels
+* - 8 interrupt capable MAILBOXES
+* - 8 bit TIMER with 16 selectable internal source clocks
*
*
-* CAUTION (from the documentation - no unducumented registers are currently emulated )
-* The FGA-002 gate array contains registers, which are used to configure the gate array for special external hardware
-* requirements. These registers are reserved and will be setup by the boot software according to the hardware environment in which the gate array is
-* implemented. These registers must not be changed by the user. Some of these hardware configuration registers also contain user selectable bits.
-* Programming the contents of these registers has to be done carefully without changing the bits initialized by the boot software.
-* Registers not described must not be programmed. Unqualified changes of register bits may have unpredictable consequences for the gate array and
-* external hardware. It is expressly forbidden to change register bits, except those defined for the user.
+* CAUTION (from the documentation - no unducumented registers are currently emulated )
+* The FGA-002 gate array contains registers, which are used to configure the gate array for special external hardware
+* requirements. These registers are reserved and will be setup by the boot software according to the hardware environment in which the gate array is
+* implemented. These registers must not be changed by the user. Some of these hardware configuration registers also contain user selectable bits.
+* Programming the contents of these registers has to be done carefully without changing the bits initialized by the boot software.
+* Registers not described must not be programmed. Unqualified changes of register bits may have unpredictable consequences for the gate array and
+* external hardware. It is expressly forbidden to change register bits, except those defined for the user.
*
*/
#include "fga002.h"
@@ -112,14 +112,14 @@ void fga002_device::device_timer (emu_timer &timer, device_timer_id id, INT32 pa
{
switch(id)
{
- case TIMER_ID_FGA:
+ case TIMER_ID_FGA:
if (m_tim0count-- == 0) // Zero detect
- {
+ {
if ((m_fga002[FGA_TIM0CTL] & REG_TIM0CTL_ZERO_STOP) == 0)
{
fga_timer->adjust(attotime::never, TIMER_ID_FGA, attotime::never);
}
- else
+ else
{
if ((m_fga002[FGA_TIM0CTL] & REG_TIM0CTL_AUTOPRELOAD) == 0)
m_tim0count &= 0xff;
@@ -128,34 +128,34 @@ void fga002_device::device_timer (emu_timer &timer, device_timer_id id, INT32 pa
}
}
break;
- default:
- LOG(("Unhandled Timer ID %d\n", id));
- break;
+ default:
+ LOG(("Unhandled Timer ID %d\n", id));
+ break;
}
}
-/* The FGA002 Timer
+/* The FGA002 Timer
- FEATURES
- - 8 bit Synchronous Counter
- - 16 selectable clocks with frequencies from 1MHz to 0.5 Hz
- - Autopreload and Zerostop operating modes
- - Watchdog Timer operation
- - SYSFAIL and/or interrupt generation
- - Vectored interrupt
- - Interrupt levels selectable by software
+ FEATURES
+ - 8 bit Synchronous Counter
+ - 16 selectable clocks with frequencies from 1MHz to 0.5 Hz
+ - Autopreload and Zerostop operating modes
+ - Watchdog Timer operation
+ - SYSFAIL and/or interrupt generation
+ - Vectored interrupt
+ - Interrupt levels selectable by software
*/
-/* Timer Preload Register TIM0PRELOAD
- The Timer Preload Register TIM0PRELOAD contains the preset value which can be loaded into the counter circuit. The default
- value of this register after reset is $00. The TIM0PRELOAD register can be read at any time but must not be altered if the
- timer is running.
- [7:0] The Timer Preload register contains the 8 bit value that is loaded into the counter if the
- Autopreload option in the TIM0CTL register is selected and the counter reaches the value zero.
- Also, if a write access to the TIM0COUNT register is performed, the counter is loaded with the value
- stored in the Timer Preload Register.
+/* Timer Preload Register TIM0PRELOAD
+ The Timer Preload Register TIM0PRELOAD contains the preset value which can be loaded into the counter circuit. The default
+ value of this register after reset is $00. The TIM0PRELOAD register can be read at any time but must not be altered if the
+ timer is running.
+ [7:0] The Timer Preload register contains the 8 bit value that is loaded into the counter if the
+ Autopreload option in the TIM0CTL register is selected and the counter reaches the value zero.
+ Also, if a write access to the TIM0COUNT register is performed, the counter is loaded with the value
+ stored in the Timer Preload Register.
*/
void fga002_device::do_fga002reg_tim0preload_w(UINT8 data)
{
@@ -169,44 +169,44 @@ UINT8 fga002_device::do_fga002reg_tim0preload_r()
return m_fga002[FGA_TIM0PRELOAD];
}
-/* Timer Control Register TIM0CTL
- In the Timer Control Register TIM0CTL the operating mode and the clock source of the timer can be selected. The Timer
- Control Register is grouped into two major fields. Bits 7-4 define the operating mode of the timer and the sysfail option.
- Bits 3-0 select the source clock applied to the timer. The TIM0CTL register is cleared to $00 after any reset operation.
- [7] Zerostop This bit selects whether the counter stops when reaching zero count or continues counting down. The value the
- counter will decrement to next depends on the setting of bit 6 of this register, which is the Autopreload bit.
- 1 = The counter continues counting down.
- 0 = The counter stops on zero count.
- [6] Autopreload This bit selects whether the counter rolls over from $00 to the value $FF and continues counting down or is
- preset by the contents of the timer preload register after reaching the zero count. The Autopreload option may be
- ignored if the counter is programmed to stop on zero count.
- 1 The Autopreload option is enabled. When the counter has passed from $01 to $00, the value stored in the Preload
- register will be transferred to the counter on the first clock edge following the zero count clock. After
- that transfer the counter continues decrementing from the new value.
- 0 The Autopreload option is disabled. After the counter has reached zero it will roll over to the value $FF and
- continue counting down.
- [5] Sysfail This bit enables/disables the sysfail generation by the timer. If this option is enabled, the SFAILO output pin of the FGA-002
- gate array will be asserted low when the timer triggers the timer interrupt. The sysfail signal is negated when the timer
- interrupt is cleared. 1 = enabled 0 = disabled
- [4] Start/Stop: This bit controls the timer start and stop operation. 1 = start 0 = stop
- [3:0] Clock select This bitfield provides selection of the source clock for timer operation.
- 3..0 source clock period
- 0000 1 microsecond
- 0001 2 microseconds
- 0010 4 microseconds
- 0011 8 microseconds
- 0100 16 microseconds
- 0101 32 microseconds
- 0110 64 microseconds
- 0111 128 microseconds
- 1000 256 microseconds
- 1001 512 microseconds
- 1010 2 milliseconds
- 1011 8 milliseconds
- 1100 32 milliseconds
- 1101 125 milliseconds
- 1110 500 milliseconds
- 1111 2 seconds
+/* Timer Control Register TIM0CTL
+ In the Timer Control Register TIM0CTL the operating mode and the clock source of the timer can be selected. The Timer
+ Control Register is grouped into two major fields. Bits 7-4 define the operating mode of the timer and the sysfail option.
+ Bits 3-0 select the source clock applied to the timer. The TIM0CTL register is cleared to $00 after any reset operation.
+ [7] Zerostop This bit selects whether the counter stops when reaching zero count or continues counting down. The value the
+ counter will decrement to next depends on the setting of bit 6 of this register, which is the Autopreload bit.
+ 1 = The counter continues counting down.
+ 0 = The counter stops on zero count.
+ [6] Autopreload This bit selects whether the counter rolls over from $00 to the value $FF and continues counting down or is
+ preset by the contents of the timer preload register after reaching the zero count. The Autopreload option may be
+ ignored if the counter is programmed to stop on zero count.
+ 1 The Autopreload option is enabled. When the counter has passed from $01 to $00, the value stored in the Preload
+ register will be transferred to the counter on the first clock edge following the zero count clock. After
+ that transfer the counter continues decrementing from the new value.
+ 0 The Autopreload option is disabled. After the counter has reached zero it will roll over to the value $FF and
+ continue counting down.
+ [5] Sysfail This bit enables/disables the sysfail generation by the timer. If this option is enabled, the SFAILO output pin of the FGA-002
+ gate array will be asserted low when the timer triggers the timer interrupt. The sysfail signal is negated when the timer
+ interrupt is cleared. 1 = enabled 0 = disabled
+ [4] Start/Stop: This bit controls the timer start and stop operation. 1 = start 0 = stop
+ [3:0] Clock select This bitfield provides selection of the source clock for timer operation.
+ 3..0 source clock period
+ 0000 1 microsecond
+ 0001 2 microseconds
+ 0010 4 microseconds
+ 0011 8 microseconds
+ 0100 16 microseconds
+ 0101 32 microseconds
+ 0110 64 microseconds
+ 0111 128 microseconds
+ 1000 256 microseconds
+ 1001 512 microseconds
+ 1010 2 milliseconds
+ 1011 8 milliseconds
+ 1100 32 milliseconds
+ 1101 125 milliseconds
+ 1110 500 milliseconds
+ 1111 2 seconds
*/
void fga002_device::do_fga002reg_tim0ctl_w(UINT8 data)
@@ -250,12 +250,12 @@ UINT8 fga002_device::do_fga002reg_tim0ctl_r()
return m_fga002[FGA_TIM0CTL];
}
-/* Timer Count Register TIM0COUNT
- The Timer Count Register TIM0COUNT contains the current value of the timer/counter. A write access to this register will
- load the counter with the value stored in the Timer Preload Register. The written data will be ignored.
- It is permitted to perform read/write accesses to the Timer Count Register when the timer is running.
- The Timer Count Register is initialized to the value $FF after reset.
- [7:0] Timer Count Value
+/* Timer Count Register TIM0COUNT
+ The Timer Count Register TIM0COUNT contains the current value of the timer/counter. A write access to this register will
+ load the counter with the value stored in the Timer Preload Register. The written data will be ignored.
+ It is permitted to perform read/write accesses to the Timer Count Register when the timer is running.
+ The Timer Count Register is initialized to the value $FF after reset.
+ [7:0] Timer Count Value
*/
void fga002_device::do_fga002reg_tim0count_w(UINT8 data)
{
@@ -269,11 +269,11 @@ UINT8 fga002_device::do_fga002reg_tim0count_r()
return m_tim0count;
}
-/* Timer Interrupt Control Register ICRTIM0
- Timer Interrupt Control is performed by the Timer Interrupt Control Register ICRTIM0 which enables/disables the interrupt
- and selects the interrupt level.
- [3] IRQ enable, 1 = timer interrupt channel enabled, 0 = disabled
- [2:0] IRQ level 000 = interrupt disabled 001-111 = Level 1 to 7 interrupt
+/* Timer Interrupt Control Register ICRTIM0
+ Timer Interrupt Control is performed by the Timer Interrupt Control Register ICRTIM0 which enables/disables the interrupt
+ and selects the interrupt level.
+ [3] IRQ enable, 1 = timer interrupt channel enabled, 0 = disabled
+ [2:0] IRQ level 000 = interrupt disabled 001-111 = Level 1 to 7 interrupt
*/
void fga002_device::do_fga002reg_icrtim0_w(UINT8 data)
{
@@ -287,10 +287,10 @@ UINT8 fga002_device::do_fga002reg_icrtim0_r()
return m_fga002[FGA_ICRTIM0];
}
-/* Timer Interrupt Status Register ISTIM0
- ISTIM0 displays a pending timer interrupt. This bit is always readable and indicates 0 if the timer interrupt has been triggered. A write access to the
- ISTIM0 register clears the timer interrupt. The data written to this register will be ignored.
- [7] The IRQ Status register bit displays if a timer interrupt request is pending. 1 = no interrupt is pending. 0 = interrupt is pending
+/* Timer Interrupt Status Register ISTIM0
+ ISTIM0 displays a pending timer interrupt. This bit is always readable and indicates 0 if the timer interrupt has been triggered. A write access to the
+ ISTIM0 register clears the timer interrupt. The data written to this register will be ignored.
+ [7] The IRQ Status register bit displays if a timer interrupt request is pending. 1 = no interrupt is pending. 0 = interrupt is pending
[6:0] not used
*/
void fga002_device::do_fga002reg_istim0_w(UINT8 data)
@@ -390,7 +390,7 @@ WRITE8_MEMBER (fga002_device::write){
case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break;
case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break;
case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break;
- case FGA_ISTIM0 : do_fga002reg_istim0_w(data); break;
+ case FGA_ISTIM0 : do_fga002reg_istim0_w(data); break;
case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break;
case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break;
case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break;
@@ -401,7 +401,7 @@ WRITE8_MEMBER (fga002_device::write){
case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break;
case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break;
case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break;
- case FGA_TIM0COUNT : do_fga002reg_tim0count_w(data); break;
+ case FGA_TIM0COUNT : do_fga002reg_tim0count_w(data); break;
default:
LOG(("Unsupported register %04x\n", offset));
}
@@ -493,7 +493,7 @@ READ8_MEMBER (fga002_device::read){
case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break;
case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break;
case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break;
- case FGA_ISTIM0 : ret = do_fga002reg_istim0_r(); break;
+ case FGA_ISTIM0 : ret = do_fga002reg_istim0_r(); break;
case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break;
case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break;
case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break;
@@ -504,7 +504,7 @@ READ8_MEMBER (fga002_device::read){
case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break;
case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break;
case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break;
- case FGA_TIM0COUNT : ret = do_fga002reg_tim0count_r(); break;
+ case FGA_TIM0COUNT : ret = do_fga002reg_tim0count_r(); break;
default:
LOG(("Unsupported register %04x\n", offset));
}
diff --git a/src/devices/machine/fga002.h b/src/devices/machine/fga002.h
index 80401da5b84..86b7ffc7b4c 100644
--- a/src/devices/machine/fga002.h
+++ b/src/devices/machine/fga002.h
@@ -5,7 +5,7 @@
#include "emu.h"
-#define MCFG_FGA002_ADD(_tag, _clock) MCFG_DEVICE_ADD(_tag, FGA002, _clock)
+#define MCFG_FGA002_ADD(_tag, _clock) MCFG_DEVICE_ADD(_tag, FGA002, _clock)
//**************************************************************************
// TYPE DEFINITIONS
@@ -15,19 +15,19 @@
class fga002_device : public device_t
{
- public:
+ public:
// construction/destruction
fga002_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
fga002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_WRITE8_MEMBER (write);
DECLARE_READ8_MEMBER (read);
- protected:
+ protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr) override;
- private:
+ private:
UINT8 m_tim0count;
UINT8 m_fga002[0x500];
@@ -48,128 +48,128 @@ class fga002_device : public device_t
TIMER_ID_FGA
};
enum {
- REG_TIM0CTL_ZERO_STOP = 0x80,
- REG_TIM0CTL_AUTOPRELOAD = 0x40,
- REG_TIM0CTL_SYSFAIL = 0x20,
- REG_TIM0CTL_START_STOP = 0x10,
- REG_TIM0CTL_CLK_MSK = 0x0f,
- REG_TIM0CTL_CLK_1_MIC = 0x00,
- REG_TIM0CTL_CLK_2_MIC = 0x01,
- REG_TIM0CTL_CLK_4_MIC = 0x02,
- REG_TIM0CTL_CLK_8_MIC = 0x03,
- REG_TIM0CTL_CLK_16_MIC = 0x04,
- REG_TIM0CTL_CLK_32_MIC = 0x05,
- REG_TIM0CTL_CLK_64_MIC = 0x06,
- REG_TIM0CTL_CLK_128_MIC = 0x07,
- REG_TIM0CTL_CLK_256_MIC = 0x08,
- REG_TIM0CTL_CLK_512_MIC = 0x09,
- REG_TIM0CTL_CLK_2_MIL = 0x0a,
- REG_TIM0CTL_CLK_8_MIL = 0x0b,
- REG_TIM0CTL_CLK_32_MIL = 0x0c,
- REG_TIM0CTL_CLK_125_MIL = 0x0d,
- REG_TIM0CTL_CLK_500_MIL = 0x0e,
- REG_TIM0CTL_CLK_2_SEC = 0x0f,
+ REG_TIM0CTL_ZERO_STOP = 0x80,
+ REG_TIM0CTL_AUTOPRELOAD = 0x40,
+ REG_TIM0CTL_SYSFAIL = 0x20,
+ REG_TIM0CTL_START_STOP = 0x10,
+ REG_TIM0CTL_CLK_MSK = 0x0f,
+ REG_TIM0CTL_CLK_1_MIC = 0x00,
+ REG_TIM0CTL_CLK_2_MIC = 0x01,
+ REG_TIM0CTL_CLK_4_MIC = 0x02,
+ REG_TIM0CTL_CLK_8_MIC = 0x03,
+ REG_TIM0CTL_CLK_16_MIC = 0x04,
+ REG_TIM0CTL_CLK_32_MIC = 0x05,
+ REG_TIM0CTL_CLK_64_MIC = 0x06,
+ REG_TIM0CTL_CLK_128_MIC = 0x07,
+ REG_TIM0CTL_CLK_256_MIC = 0x08,
+ REG_TIM0CTL_CLK_512_MIC = 0x09,
+ REG_TIM0CTL_CLK_2_MIL = 0x0a,
+ REG_TIM0CTL_CLK_8_MIL = 0x0b,
+ REG_TIM0CTL_CLK_32_MIL = 0x0c,
+ REG_TIM0CTL_CLK_125_MIL = 0x0d,
+ REG_TIM0CTL_CLK_500_MIL = 0x0e,
+ REG_TIM0CTL_CLK_2_SEC = 0x0f,
};
enum {
- REG_ISTIM0_TIM_INT = 0x80,
+ REG_ISTIM0_TIM_INT = 0x80,
};
/* Register offsets */
enum {
- FGA_ICRMBOX0 = 0x0000,
- FGA_ICRMBOX1 = 0x0004,
- FGA_ICRMBOX2 = 0x0008,
- FGA_ICRMBOX3 = 0x000c,
- FGA_ICRMBOX4 = 0x0010,
- FGA_ICRMBOX5 = 0x0014,
- FGA_ICRMBOX6 = 0x0018,
- FGA_ICRMBOX7 = 0x001C,
- FGA_VMEPAGE = 0x0200,
- FGA_ICRVME1 = 0x0204,
- FGA_ICRVME2 = 0x0208,
- FGA_ICRVME3 = 0x020c,
- FGA_ICRVME4 = 0x0210,
- FGA_ICRVME5 = 0x0214,
- FGA_ICRVME6 = 0x0218,
- FGA_ICRVME7 = 0x021c,
- FGA_ICRTIM0 = 0x0220,
- FGA_ICRDMANORM = 0x0230,
- FGA_ICRDMAERR = 0x0234,
- FGA_CTL1 = 0x0238,
- FGA_CTL2 = 0x023c,
- FGA_ICRFMB0REF = 0x0240,
- FGA_ICRFMB1REF = 0x0244,
- FGA_ICRFMB0MES = 0x0248,
- FGA_ICRFMB1MES = 0x024c,
- FGA_CTL3 = 0x0250,
- FGA_CTL4 = 0x0254,
- FGA_ICRPARITY = 0x0258,
- FGA_AUXPINCTL = 0x0260,
- FGA_CTL5 = 0x0264,
- FGA_AUXFIFWEX = 0x0268,
- FGA_AUXFIFREX = 0x026c,
- FGA_CTL6 = 0x0270,
- FGA_CTL7 = 0x0274,
- FGA_CTL8 = 0x0278,
- FGA_CTL9 = 0x027c,
- FGA_ICRABORT = 0x0280,
- FGA_ICRACFAIL = 0x0284,
- FGA_ICRSYSFAIL = 0x0288,
- FGA_ICRLOCAL0 = 0x028c,
- FGA_ICRLOCAL1 = 0x0290,
- FGA_ICRLOCAL2 = 0x0294,
- FGA_ICRLOCAL3 = 0x0298,
- FGA_ICRLOCAL4 = 0x029c,
- FGA_ICRLOCAL5 = 0x02a0,
- FGA_ICRLOCAL6 = 0x02a4,
- FGA_ICRLOCAL7 = 0x02a8,
- FGA_ENAMCODE = 0x02b4,
- FGA_CTL10 = 0x02c0,
- FGA_CTL11 = 0x02c4,
- FGA_MAINUM = 0x02c8,
- FGA_MAINUU = 0x02cc,
+ FGA_ICRMBOX0 = 0x0000,
+ FGA_ICRMBOX1 = 0x0004,
+ FGA_ICRMBOX2 = 0x0008,
+ FGA_ICRMBOX3 = 0x000c,
+ FGA_ICRMBOX4 = 0x0010,
+ FGA_ICRMBOX5 = 0x0014,
+ FGA_ICRMBOX6 = 0x0018,
+ FGA_ICRMBOX7 = 0x001C,
+ FGA_VMEPAGE = 0x0200,
+ FGA_ICRVME1 = 0x0204,
+ FGA_ICRVME2 = 0x0208,
+ FGA_ICRVME3 = 0x020c,
+ FGA_ICRVME4 = 0x0210,
+ FGA_ICRVME5 = 0x0214,
+ FGA_ICRVME6 = 0x0218,
+ FGA_ICRVME7 = 0x021c,
+ FGA_ICRTIM0 = 0x0220,
+ FGA_ICRDMANORM = 0x0230,
+ FGA_ICRDMAERR = 0x0234,
+ FGA_CTL1 = 0x0238,
+ FGA_CTL2 = 0x023c,
+ FGA_ICRFMB0REF = 0x0240,
+ FGA_ICRFMB1REF = 0x0244,
+ FGA_ICRFMB0MES = 0x0248,
+ FGA_ICRFMB1MES = 0x024c,
+ FGA_CTL3 = 0x0250,
+ FGA_CTL4 = 0x0254,
+ FGA_ICRPARITY = 0x0258,
+ FGA_AUXPINCTL = 0x0260,
+ FGA_CTL5 = 0x0264,
+ FGA_AUXFIFWEX = 0x0268,
+ FGA_AUXFIFREX = 0x026c,
+ FGA_CTL6 = 0x0270,
+ FGA_CTL7 = 0x0274,
+ FGA_CTL8 = 0x0278,
+ FGA_CTL9 = 0x027c,
+ FGA_ICRABORT = 0x0280,
+ FGA_ICRACFAIL = 0x0284,
+ FGA_ICRSYSFAIL = 0x0288,
+ FGA_ICRLOCAL0 = 0x028c,
+ FGA_ICRLOCAL1 = 0x0290,
+ FGA_ICRLOCAL2 = 0x0294,
+ FGA_ICRLOCAL3 = 0x0298,
+ FGA_ICRLOCAL4 = 0x029c,
+ FGA_ICRLOCAL5 = 0x02a0,
+ FGA_ICRLOCAL6 = 0x02a4,
+ FGA_ICRLOCAL7 = 0x02a8,
+ FGA_ENAMCODE = 0x02b4,
+ FGA_CTL10 = 0x02c0,
+ FGA_CTL11 = 0x02c4,
+ FGA_MAINUM = 0x02c8,
+ FGA_MAINUU = 0x02cc,
FGA_BOTTOMPAGEU = 0x02d0,
FGA_BOTTOMPAGEL = 0x02d4,
- FGA_TOPPAGEU = 0x02d8,
- FGA_TOPPAGEL = 0x02dc,
- FGA_MYVMEPAGE = 0x02fc,
+ FGA_TOPPAGEU = 0x02d8,
+ FGA_TOPPAGEL = 0x02dc,
+ FGA_MYVMEPAGE = 0x02fc,
FGA_TIM0PRELOAD = 0x0300,
- FGA_TIM0CTL = 0x0310,
- FGA_DMASRCATT = 0x0320,
- FGA_DMADSTATT = 0x0324,
- FGA_DMA_GENERAL = 0x0328,
- FGA_CTL12 = 0x032c,
- FGA_LIOTIMING = 0x0330,
- FGA_LOCALIACK = 0x0334,
- FGA_FMBCTL = 0x0338,
- FGA_FMBAREA = 0x033c,
+ FGA_TIM0CTL = 0x0310,
+ FGA_DMASRCATT = 0x0320,
+ FGA_DMADSTATT = 0x0324,
+ FGA_DMA_GENERAL = 0x0328,
+ FGA_CTL12 = 0x032c,
+ FGA_LIOTIMING = 0x0330,
+ FGA_LOCALIACK = 0x0334,
+ FGA_FMBCTL = 0x0338,
+ FGA_FMBAREA = 0x033c,
FGA_AUXSRCSTART = 0x0340,
FGA_AUXDSTSTART = 0x0344,
- FGA_AUXSRCTERM = 0x0348,
- FGA_AUXDSTTERM = 0x034c,
- FGA_CTL13 = 0x0350,
- FGA_CTL14 = 0x0354,
- FGA_CTL15 = 0x0358,
- FGA_CTL16 = 0x035c,
- FGA_SPECIALENA = 0x0424,
- FGA_ISTIM0 = 0x04a0,
- FGA_ISDMANORM = 0x04b0,
- FGA_ISDMAERR = 0x04b4,
- FGA_ISFMB0REF = 0x04b8,
- FGA_ISFMB1REF = 0x04bc,
- FGA_ISPARITY = 0x04c0,
- FGA_DMARUNCTL = 0x04c4,
- FGA_ISABORT = 0x04c8,
- FGA_ISACFAIL = 0x04cc,
- FGA_ISFMB0MES = 0x04e0,
- FGA_ISFMB1MES = 0x04e4,
- FGA_ISSYSFAIL = 0x04d0,
- FGA_ABORTPIN = 0x04d4,
- FGA_RSVMECALL = 0x04f0,
- FGA_RSKEYRES = 0x04f4,
- FGA_RSCPUCALL = 0x04f8,
- FGA_RSLOCSW = 0x04fc,
- FGA_TIM0COUNT = 0x0c00,
+ FGA_AUXSRCTERM = 0x0348,
+ FGA_AUXDSTTERM = 0x034c,
+ FGA_CTL13 = 0x0350,
+ FGA_CTL14 = 0x0354,
+ FGA_CTL15 = 0x0358,
+ FGA_CTL16 = 0x035c,
+ FGA_SPECIALENA = 0x0424,
+ FGA_ISTIM0 = 0x04a0,
+ FGA_ISDMANORM = 0x04b0,
+ FGA_ISDMAERR = 0x04b4,
+ FGA_ISFMB0REF = 0x04b8,
+ FGA_ISFMB1REF = 0x04bc,
+ FGA_ISPARITY = 0x04c0,
+ FGA_DMARUNCTL = 0x04c4,
+ FGA_ISABORT = 0x04c8,
+ FGA_ISACFAIL = 0x04cc,
+ FGA_ISFMB0MES = 0x04e0,
+ FGA_ISFMB1MES = 0x04e4,
+ FGA_ISSYSFAIL = 0x04d0,
+ FGA_ABORTPIN = 0x04d4,
+ FGA_RSVMECALL = 0x04f0,
+ FGA_RSKEYRES = 0x04f4,
+ FGA_RSCPUCALL = 0x04f8,
+ FGA_RSLOCSW = 0x04fc,
+ FGA_TIM0COUNT = 0x0c00,
};
};
@@ -178,4 +178,3 @@ class fga002_device : public device_t
// device type definition
extern const device_type FGA002;
#endif // __FGA002_H__
-
diff --git a/src/devices/machine/hp_taco.cpp b/src/devices/machine/hp_taco.cpp
index 4938d2f4c4b..adb369c59f2 100644
--- a/src/devices/machine/hp_taco.cpp
+++ b/src/devices/machine/hp_taco.cpp
@@ -183,8 +183,8 @@ enum {
#define SHORT_GAP_LENGTH ((tape_pos_t)(0.066 * ONE_INCH_POS)) // Minimum length of short gaps: 0.066" ([1], pg 8-10)
#define LONG_GAP_LENGTH ((tape_pos_t)(1.5 * ONE_INCH_POS)) // Minimum length of long gaps: 1.5" ([1], pg 8-10)
#define NULL_TAPE_POS ((tape_pos_t)-1) // Special value for invalid/unknown tape position
-#define PREAMBLE_TIMEOUT ((tape_pos_t)(2.6 * ONE_INCH_POS)) // Min. length of gap making preamble search time out (totally made up)
-#define DATA_TIMEOUT ((tape_pos_t)(0.066 * ONE_INCH_POS)) // Min. length of gap that will cause data reading to time out (totally made up)
+#define PREAMBLE_TIMEOUT ((tape_pos_t)(2.6 * ONE_INCH_POS)) // Min. length of gap making preamble search time out (totally made up)
+#define DATA_TIMEOUT ((tape_pos_t)(0.066 * ONE_INCH_POS)) // Min. length of gap that will cause data reading to time out (totally made up)
#define FILE_MAGIC 0x4f434154 // Magic value at start of image file: "TACO"
// Parts of command register
diff --git a/src/devices/machine/input_merger.cpp b/src/devices/machine/input_merger.cpp
index d75a3f994d2..ceedca5d556 100644
--- a/src/devices/machine/input_merger.cpp
+++ b/src/devices/machine/input_merger.cpp
@@ -64,8 +64,8 @@ void input_merger_device::device_start()
// input_merger_active_high_device - constructor
//-------------------------------------------------
-input_merger_active_high_device::input_merger_active_high_device(machine_config const &mconfig, char const *tag, device_t *owner, UINT32 clock)
- : input_merger_device(mconfig, INPUT_MERGER_ACTIVE_HIGH, "Input Merger (Active High)", tag, owner, clock, "input_merger_hi", __FILE__)
+input_merger_active_high_device::input_merger_active_high_device(machine_config const &mconfig, char const *tag, device_t *owner, UINT32 clock)
+ : input_merger_device(mconfig, INPUT_MERGER_ACTIVE_HIGH, "Input Merger (Active High)", tag, owner, clock, "input_merger_hi", __FILE__)
{
}
@@ -97,8 +97,8 @@ void input_merger_active_high_device::update_state()
// input_merger_active_low_device - constructor
//-------------------------------------------------
-input_merger_active_low_device::input_merger_active_low_device(machine_config const &mconfig, char const *tag, device_t *owner, UINT32 clock)
- : input_merger_device(mconfig, INPUT_MERGER_ACTIVE_LOW, "Input Merger (Active Low)", tag, owner, clock, "input_merger_lo", __FILE__)
+input_merger_active_low_device::input_merger_active_low_device(machine_config const &mconfig, char const *tag, device_t *owner, UINT32 clock)
+ : input_merger_device(mconfig, INPUT_MERGER_ACTIVE_LOW, "Input Merger (Active Low)", tag, owner, clock, "input_merger_lo", __FILE__)
{
}
diff --git a/src/devices/machine/input_merger.h b/src/devices/machine/input_merger.h
index 9ede71f2ab8..c649d723b55 100644
--- a/src/devices/machine/input_merger.h
+++ b/src/devices/machine/input_merger.h
@@ -2,7 +2,7 @@
// copyright-holders:Dirk Best
/***************************************************************************
- Input Merger
+ Input Merger
Used to connect multiple lines to a single device input while
keeping it pulled high or low
diff --git a/src/devices/machine/pdc.cpp b/src/devices/machine/pdc.cpp
index b993531a14b..f5a75d87f72 100644
--- a/src/devices/machine/pdc.cpp
+++ b/src/devices/machine/pdc.cpp
@@ -324,7 +324,6 @@ pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t
void pdc_device::device_start()
{
-
/* Save States */
save_item(NAME(reg_p0));
save_item(NAME(reg_p1));
diff --git a/src/devices/machine/scnxx562.cpp b/src/devices/machine/scnxx562.cpp
index cbd3f67a861..491e00ccdca 100644
--- a/src/devices/machine/scnxx562.cpp
+++ b/src/devices/machine/scnxx562.cpp
@@ -37,12 +37,12 @@ DONE (x) (p=partly) NMOS CMOS
Synch data rates 4Mbps 10Mbps
----- asynchrounous features ------------------
x 5-8 bit per char Y Y
- p 1-2 stop bits Y Y TODO: 1/16 bit increments
- p odd/even parity Y Y TODO: parity generation on Tx
+ p 1-2 stop bits Y Y TODO: 1/16 bit increments
+ p odd/even parity Y Y TODO: parity generation on Tx
x1,x16 Y Y
break det/gen Y Y
- p parity, framing & Y Y TODO: parity check on Rx
- overrun error det
+ p parity, framing & Y Y TODO: parity check on Rx
+ overrun error det
-- byte oriented synchrounous features --
Int/ext char sync Y Y
1/2 synch chars ? ?
@@ -58,7 +58,7 @@ DONE (x) (p=partly) NMOS CMOS
--
x Receiver FIFO 4 16
x Transmitter FIFO 4 16
- NRZ, NRZI, FM1 or Y Y
+ NRZ, NRZI, FM1 or Y Y
FM2 enc/dec
Manchester dec Y Y
x Baud gen per chan Y Y
@@ -88,7 +88,7 @@ DONE (x) (p=partly) NMOS CMOS
#define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#define LOGR(x)
+#define LOGR(x)
#if VERBOSE > 1
#define logerror printf
#endif
@@ -276,13 +276,13 @@ void duscc_device::device_reset()
Each of the above conditions occupies a bit in the General Status Register (GSR). If ICR[2] is set, the eight conditions are encoded
into three bits which are inserted into bits [2:0] or [4:2] of the interrupt vector register. This forms the content of the IVRM during
an interrupt acknowledge cycle. Unmodified and modified vectors can read directly through specified registers. Two of the conditions
- are the inclusive OR of several other maskable conditions:
+ are the inclusive OR of several other maskable conditions:
- Extemal or CIT special condition: Delta DCD, Delta CTS or CIT zero count (ICTSR[6:4j).
- Rxrrx error or special condition: any condition in the Receiver Status Register (RSR[7:0J) or a transmitter or DPLL condition in
the Transmitter and Receiver Status Register (TRSR[7:3J).
The TxRDY and RxRDY conditions are defined by OMR[4] and OMR[3], respectively. Also associated with the interrupt system are
the Interrupt Enable Register (IER), one bit in the Countermmer Control Register (CTCR), and the Interrupt Control Register (lCR).
-
+
The IER is programmed to enable specified conditions or groups of conditions to cause an interrupt by asserting the corresponding bit.
A negated bit prevents an interrupt from occurring when the condition is active and hence masks the interrupt. In addition to the
IER, CTCR[?] could be programmed to enable or disable an interrupt upon the CfT zero count condition. The interrupt priorities
@@ -292,7 +292,7 @@ void duscc_device::device_reset()
is to cause an interrupt. The CPU vector mode is specified by ICR[5:4] which selects either vectored or non-vectored operation. If
vectored mode is selected, the content of the IVR or IVRM is placed on the data bus when lACK is activated. If ICR[2] is set, the content
of IVRM is output which contains the content of IVR and the encoded status of the interrupting condition.
- Upon receiving an interrupt acknowledge, the DUSCC locks its current interrupt status until the end of the acknowledge cycle.
+ Upon receiving an interrupt acknowledge, the DUSCC locks its current interrupt status until the end of the acknowledge cycle.
If it has an active interrupt pending, it responds with the appropriate vector and then asserts DTACKN. If it does not have an interrupt, it
propagates the acknowledge through its X2/1DCN output if this function is programmed in PCRA[7]; otherwise, the IACKN is
ignored. Locking the interrupt status at the leading edge of IACKN prevents a device at a High position in the interrupt daisy chain from
@@ -306,8 +306,8 @@ int duscc_device::z80daisy_irq_state()
int state = 0;
LOG(("%s %s A:[%02x][%02x][%02x][%02x] B:[%02x][%02x][%02x][%02x] ",tag(), FUNCNAME,
- m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3],
- m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7]));
+ m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3],
+ m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7]));
// loop over all interrupt sources
for (auto & elem : m_int_state)
@@ -333,7 +333,6 @@ int duscc_device::z80daisy_irq_state()
int duscc_device::z80daisy_irq_ack()
{
-
LOG(("%s %s()\n",tag(), FUNCNAME));
// loop over all interrupt sources
@@ -360,7 +359,6 @@ int duscc_device::z80daisy_irq_ack()
void duscc_device::z80daisy_irq_reti()
{
-
LOG(("%s %s \n",tag(), FUNCNAME));
// loop over all interrupt sources
@@ -381,7 +379,7 @@ void duscc_device::z80daisy_irq_reti()
void duscc_device::check_interrupts()
{
LOG(("%s %s()\n",tag(), FUNCNAME));
- int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE;
+ int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE;
// "If no interrupt is pending, an H'FF' is output when reading the IVRM."
if (state == 0)
@@ -431,8 +429,8 @@ UINT8 duscc_device::modify_vector(UINT8 vec, int i, UINT8 src)
if ((m_icr & REG_ICR_VEC_MOD) != 0) // Affect vector?
{
// Modify vector according to "Vector Include Status" bit (REG_ICR_V2V4_MOD)
- if ((m_icr & REG_ICR_V2V4_MOD) != 0)
- { // Affect V2-V4
+ if ((m_icr & REG_ICR_V2V4_MOD) != 0)
+ { // Affect V2-V4
vec &= 0x07 << 3;
vec |= src << 3;
}
@@ -447,7 +445,7 @@ UINT8 duscc_device::modify_vector(UINT8 vec, int i, UINT8 src)
/* Interrupt Control and Status Registers
- This group of registers define mechanisms for communications between the DUSCC and the processor and contain the device status
+ This group of registers define mechanisms for communications between the DUSCC and the processor and contain the device status
information. Four registers, available for each channel, and four common device registers comprise this group which consists of
the following:
1. Interrupt Enable Register (IERA/B).
@@ -538,11 +536,11 @@ duscc_channel::duscc_channel(const machine_config &mconfig, const char *tag, dev
LOG(("%s\n",FUNCNAME));
// Reset all registers
- m_cmr1 = m_cmr2 = m_s1r = m_s2r = m_tpr = m_ttr = m_rpr = m_rtr
- = /* m_ctprh = m_ctprl = */ m_ctpr = m_ctcr = m_omr
- = /* m_cth = m_ctl = */ m_ct = m_pcr
+ m_cmr1 = m_cmr2 = m_s1r = m_s2r = m_tpr = m_ttr = m_rpr = m_rtr
+ = /* m_ctprh = m_ctprl = */ m_ctpr = m_ctcr = m_omr
+ = /* m_cth = m_ctl = */ m_ct = m_pcr
= m_ccr = m_rsr = m_trsr = m_ictsr /*= m_gsr*/ = m_ier /*= m_rea*/
- = m_cid = /*m_ivr = m_icr = m_sea = m_ivrm = */ m_mrr = m_ier1
+ = m_cid = /*m_ivr = m_icr = m_sea = m_ivrm = */ m_mrr = m_ier1
= m_ier2 = m_ier3 = m_trcr = m_rflr = m_ftlr = m_trmsr = m_telr = 0;
// Reset all states
@@ -591,13 +589,13 @@ void duscc_channel::device_start()
save_item(NAME(m_ttr));
save_item(NAME(m_rpr));
save_item(NAME(m_rtr));
- // save_item(NAME(m_ctprh));
- // save_item(NAME(m_ctprl));
+ // save_item(NAME(m_ctprh));
+ // save_item(NAME(m_ctprl));
save_item(NAME(m_ctpr));
save_item(NAME(m_ctcr));
save_item(NAME(m_omr));
- // save_item(NAME(m_cth));
- // save_item(NAME(m_ctl));
+ // save_item(NAME(m_cth));
+ // save_item(NAME(m_ctl));
save_item(NAME(m_ct));
save_item(NAME(m_pcr));
save_item(NAME(m_ccr));
@@ -606,14 +604,14 @@ void duscc_channel::device_start()
save_item(NAME(m_rsr));
save_item(NAME(m_trsr));
save_item(NAME(m_ictsr));
- // save_item(NAME(m_gsr)); // Moved this to the device instead, it is a global register
+ // save_item(NAME(m_gsr)); // Moved this to the device instead, it is a global register
save_item(NAME(m_ier));
- // save_item(NAME(m_rea));
+ // save_item(NAME(m_rea));
save_item(NAME(m_cid));
- // save_item(NAME(m_ivr)); // Moved this to the device instead, it is a global register
- // save_item(NAME(m_icr)); // Moved this to the device instead, it is a global register
- // save_item(NAME(m_sea));
- // save_item(NAME(m_ivrm)); // Moved this to the device instead, it is a global register
+ // save_item(NAME(m_ivr)); // Moved this to the device instead, it is a global register
+ // save_item(NAME(m_icr)); // Moved this to the device instead, it is a global register
+ // save_item(NAME(m_sea));
+ // save_item(NAME(m_ivrm)); // Moved this to the device instead, it is a global register
save_item(NAME(m_mrr));
save_item(NAME(m_ier1));
save_item(NAME(m_ier2));
@@ -642,7 +640,7 @@ void duscc_channel::device_start()
save_item(NAME(m_rts));
save_item(NAME(m_sync));
- // device_serial_interface::register_save_state(machine().save(), this);
+ // device_serial_interface::register_save_state(machine().save(), this);
}
@@ -659,39 +657,39 @@ void duscc_channel::device_reset()
transmit_register_reset();
// Soft/Channel Reset values according to DUSCC users guide
- m_cmr1 =0x00;
- m_cmr2 =0x00;
- m_s1r =0x00;
- m_s2r =0x00;
- m_tpr =0x00;
- m_ttr =0x00;
- m_rpr =0x00;
- m_rtr =0x00;
- m_ctcr =0x00;
- m_omr =0x00;
- m_pcr =0x00;
- m_ccr =0x00;
- m_rsr =0x00;
- m_trsr =0x00;
- m_ictsr =0x00;
- // m_gsr =0x00;
- m_ier =0x00;
- // m_rea =0x00;
- // m_ivr =0x0f;
- // m_icr =0x00;
- // m_sea =0x00;
- // m_ivrm =0x00;
- m_mrr =0x00; // TODO: Need a read after reset to enable CMOS features
- m_ier1 =0x00;
- m_ier2 =0x00;
- m_ier3 =0x00;
- m_trcr =0x00;
- m_rflr =0x00;
- m_ftlr =0x33;
- m_trmsr =0x00;
- m_telr =0x10;
- m_rtxc =0x00;
- m_trxc =0x00;
+ m_cmr1 =0x00;
+ m_cmr2 =0x00;
+ m_s1r =0x00;
+ m_s2r =0x00;
+ m_tpr =0x00;
+ m_ttr =0x00;
+ m_rpr =0x00;
+ m_rtr =0x00;
+ m_ctcr =0x00;
+ m_omr =0x00;
+ m_pcr =0x00;
+ m_ccr =0x00;
+ m_rsr =0x00;
+ m_trsr =0x00;
+ m_ictsr =0x00;
+ // m_gsr =0x00;
+ m_ier =0x00;
+ // m_rea =0x00;
+ // m_ivr =0x0f;
+ // m_icr =0x00;
+ // m_sea =0x00;
+ // m_ivrm =0x00;
+ m_mrr =0x00; // TODO: Need a read after reset to enable CMOS features
+ m_ier1 =0x00;
+ m_ier2 =0x00;
+ m_ier3 =0x00;
+ m_trcr =0x00;
+ m_rflr =0x00;
+ m_ftlr =0x33;
+ m_trmsr =0x00;
+ m_telr =0x10;
+ m_rtxc =0x00;
+ m_trxc =0x00;
// reset external lines TODO: check relation to control bits and reset
@@ -711,14 +709,14 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
{
switch(id)
{
- case TIMER_ID:
- if (m_ct-- == 0) // Zero detect
- {
+ case TIMER_ID:
+ if (m_ct-- == 0) // Zero detect
+ {
m_ictsr |= REG_ICTSR_ZERO_DET; // set zero detection bit
// Generate interrupt?
- if ( ( (m_ctcr & REG_CTCR_ZERO_DET_INT) == 1 ) &&
- ( (m_uart->m_icr & (m_index == duscc_device::CHANNEL_A ? duscc_device::REG_ICR_CHA : duscc_device::REG_ICR_CHB) ) != 0) )
+ if ( ( (m_ctcr & REG_CTCR_ZERO_DET_INT) == 1 ) &&
+ ( (m_uart->m_icr & (m_index == duscc_device::CHANNEL_A ? duscc_device::REG_ICR_CHA : duscc_device::REG_ICR_CHB) ) != 0) )
{
//trigger_interrupt();
}
@@ -728,7 +726,7 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
{
m_ct = m_ctpr;
}
- else
+ else
{
m_ct = 0xffff;
}
@@ -774,7 +772,7 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
m_ictsr &= ~REG_ICTSR_ZERO_DET;
}
break;
- case TIMER_ID_RTXC: // Terminate zero detection pulse
+ case TIMER_ID_RTXC: // Terminate zero detection pulse
m_rtxc = 0;
rtxc_timer->adjust(attotime::never);
if (m_index == duscc_device::CHANNEL_A)
@@ -782,7 +780,7 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
else
m_uart->m_out_rtxcb_cb(m_rtxc);
break;
- case TIMER_ID_TRXC: // Terminate zero detection pulse
+ case TIMER_ID_TRXC: // Terminate zero detection pulse
m_trxc = 0;
trxc_timer->adjust(attotime::never);
if (m_index == duscc_device::CHANNEL_A)
@@ -790,53 +788,53 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
else
m_uart->m_out_trxcb_cb(m_trxc);
break;
- default:
- LOGR(("Unhandled Timer ID %d\n", id));
- break;
+ default:
+ LOGR(("Unhandled Timer ID %d\n", id));
+ break;
}
// LOG(("%s %d\n", FUNCNAME, id));
device_serial_interface::device_timer(timer, id, param, ptr);
}
-/* The DUSCC 16 bit Timer
- Counter/Timer Control and Value Registers
- There are five registers in this set consisting of the following:
- 1. Counterltimer control register (CTCRAlB).
- 2. Counterltimer preset Highland Low registers (CTPRHAlB, CTPRLAlB).
- 3. Counter/bmer (current value) High and Low registers (CTHAlB, CTLAlB)
- The control register contains the operational information for the counterltimer. The preset registers contain the count which is
- loaded into the counterltimer circuits. The third group contains the current value of the counterltimer as it operates.
+/* The DUSCC 16 bit Timer
+ Counter/Timer Control and Value Registers
+ There are five registers in this set consisting of the following:
+ 1. Counterltimer control register (CTCRAlB).
+ 2. Counterltimer preset Highland Low registers (CTPRHAlB, CTPRLAlB).
+ 3. Counter/bmer (current value) High and Low registers (CTHAlB, CTLAlB)
+ The control register contains the operational information for the counterltimer. The preset registers contain the count which is
+ loaded into the counterltimer circuits. The third group contains the current value of the counterltimer as it operates.
*/
/* Counter/Timer Control Register (CTCRA/CTCRB)
- [7] Zero Detect Interrupt - This bit determines whether the assertion of the CIT ZERO COUNT status bit (ICTSR[6)) causes an
- interrupt to be generated if set to 1 and the Master interrupt control bit (ICR[0:1]) is set
- [6] Zero Detect Control - his bit determines the action of the counter upon reaching zero count
- 0 - The counter/timer is preset to the value contained in the counterltimer preset registers (CTPRL, CTPRH) at the next clock edge.
- 1 - The counterltimer continues counting without preset. The value at the next clock edge will be H'FFFF'.
- [5] CounterlTimer Output Control - This bit selects the output waveform when the counterltimer is selected to be output on TRxC or RTxC.
- 0 - The output toggles each time the CIT reaches zero count. The output is cleared to Low by either of the preset counterltimer commands.
- 1 - The output is a single clock positive width pulse each time the CIT reaches zero count. (The duration of this pulse is one clock period.)
- [4:3] Clock Select - This field selects whether the clock selected by [2:0J is prescaled prior to being applied to the input of the CIT.
- 0 0 No prescaling.
- 0 1 Divide clock by 16.
- 1 0 Divide clock by 32.
- 1 1 Divide clock by 64.
- [2:0] Clock Source - This field selects the clock source for the counterltimer.
- 000 RTxC pin. Pin must be programmed as input.
- 001 TRxC pin. Pin must be programmed as input.
- 010 Source is the crystal oscillator or system clock input divided by four.
- 011 This selects a special mode of operation. In this mode the counter, after receiving the 'start CIT' command, delays the
- start of counting until the RxD input goes Low. It continues counting until the RxD input goes High, then stops and sets
- the CIT zero count status bit. The CPU can use the value in the CIT to determine the bit rate of the incoming data.
- The clock is the crystal oscillator or system clock input divided by four.
- 100 Source is the 32X BRG output selected by RTR[3:0J of own channel.
- 101 Source is the 32X BRG output selected by TTR[3:0J of own channel.
- 110 Source is the internal signal which loads received characters from the receive shift register into the receiver
- FIFO. When operating in this mode, the FIFOed EOM status bit (RSR[7)) shall be set when the character which
- causes the count to go to zero is loaded into the receive FIFO.
- 111 Source is the internal signal which transfers characters from the data bus into the transmit FIFO. When operating in this
- mode, and if the TEOM on zero count or done control bit (TPR[4)) is asserted, the FIFOed send EOM command will
- be automatically asserted when the character which causes the count to go to zero is loaded into the transmit FIFO.
+ [7] Zero Detect Interrupt - This bit determines whether the assertion of the CIT ZERO COUNT status bit (ICTSR[6)) causes an
+ interrupt to be generated if set to 1 and the Master interrupt control bit (ICR[0:1]) is set
+ [6] Zero Detect Control - his bit determines the action of the counter upon reaching zero count
+ 0 - The counter/timer is preset to the value contained in the counterltimer preset registers (CTPRL, CTPRH) at the next clock edge.
+ 1 - The counterltimer continues counting without preset. The value at the next clock edge will be H'FFFF'.
+ [5] CounterlTimer Output Control - This bit selects the output waveform when the counterltimer is selected to be output on TRxC or RTxC.
+ 0 - The output toggles each time the CIT reaches zero count. The output is cleared to Low by either of the preset counterltimer commands.
+ 1 - The output is a single clock positive width pulse each time the CIT reaches zero count. (The duration of this pulse is one clock period.)
+ [4:3] Clock Select - This field selects whether the clock selected by [2:0J is prescaled prior to being applied to the input of the CIT.
+ 0 0 No prescaling.
+ 0 1 Divide clock by 16.
+ 1 0 Divide clock by 32.
+ 1 1 Divide clock by 64.
+ [2:0] Clock Source - This field selects the clock source for the counterltimer.
+ 000 RTxC pin. Pin must be programmed as input.
+ 001 TRxC pin. Pin must be programmed as input.
+ 010 Source is the crystal oscillator or system clock input divided by four.
+ 011 This selects a special mode of operation. In this mode the counter, after receiving the 'start CIT' command, delays the
+ start of counting until the RxD input goes Low. It continues counting until the RxD input goes High, then stops and sets
+ the CIT zero count status bit. The CPU can use the value in the CIT to determine the bit rate of the incoming data.
+ The clock is the crystal oscillator or system clock input divided by four.
+ 100 Source is the 32X BRG output selected by RTR[3:0J of own channel.
+ 101 Source is the 32X BRG output selected by TTR[3:0J of own channel.
+ 110 Source is the internal signal which loads received characters from the receive shift register into the receiver
+ FIFO. When operating in this mode, the FIFOed EOM status bit (RSR[7)) shall be set when the character which
+ causes the count to go to zero is loaded into the receive FIFO.
+ 111 Source is the internal signal which transfers characters from the data bus into the transmit FIFO. When operating in this
+ mode, and if the TEOM on zero count or done control bit (TPR[4)) is asserted, the FIFOed send EOM command will
+ be automatically asserted when the character which causes the count to go to zero is loaded into the transmit FIFO.
*/
UINT8 duscc_channel::do_dusccreg_ctcr_r()
{
@@ -852,54 +850,54 @@ void duscc_channel::do_dusccreg_ctcr_w(UINT8 data)
}
/* Counterrrimer Preset High Register (CTPRHA, CTPRHB)
- [7:0) MSB - This register contains the eight most significant bits of the value loaded into the counter/timer upon receipt of the load CIT
- from preset regsiter command or when.the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated.
- The minimum 16-bit counter/timer preset value is H'0002'.
+ [7:0) MSB - This register contains the eight most significant bits of the value loaded into the counter/timer upon receipt of the load CIT
+ from preset regsiter command or when.the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated.
+ The minimum 16-bit counter/timer preset value is H'0002'.
*/
UINT8 duscc_channel::do_dusccreg_ctprh_r()
{
UINT8 ret = ((m_ctpr >> 8) & 0xff );
LOG(("%s(%02x)\n", FUNCNAME, ret));
- // return m_ctprh;
+ // return m_ctprh;
return ret;
}
void duscc_channel::do_dusccreg_ctprh_w(UINT8 data)
-{
+{
LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data));
- // m_ctprh = data;
+ // m_ctprh = data;
m_ctpr &= ~0x0000ff00;
m_ctpr |= ((data << 8) & 0x0000ff00);
- return;
+ return;
}
/* CounterfTimer Preset Low Register (CTPRLA, CTPRLB)
- [7:0) lSB - This register contains the eight least significant bits of the value loaded into the counter/timer upon receipt of the load CIT
- from preset register command or when the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated.
- The minimum 16-bit counter/timer preset value is H'0002'.
+ [7:0) lSB - This register contains the eight least significant bits of the value loaded into the counter/timer upon receipt of the load CIT
+ from preset register command or when the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated.
+ The minimum 16-bit counter/timer preset value is H'0002'.
*/
UINT8 duscc_channel::do_dusccreg_ctprl_r()
{
UINT8 ret = (m_ctpr & 0xff);
LOG(("%s(%02x)\n", FUNCNAME, ret));
- // return m_ctprl;
+ // return m_ctprl;
return ret;
}
void duscc_channel::do_dusccreg_ctprl_w(UINT8 data)
-{
+{
LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data));
- // m_ctprl = data;
+ // m_ctprl = data;
m_ctpr &= ~0x000000ff;
m_ctpr |= (data & 0x000000ff);
- return;
+ return;
}
/* Counter/Timer High Register (CTHA, CTHB) Read only
- [7:0] MSB - A read of this 'register' provides the eight most significant bits of the current value of the counter/timer. it is
- recommended that the CIT be stopped via a stop counter command before it is read in order to prevent errors which may occur due to
- the read being performed while the CIT is changing. This count may be continued after the register is read.
+ [7:0] MSB - A read of this 'register' provides the eight most significant bits of the current value of the counter/timer. it is
+ recommended that the CIT be stopped via a stop counter command before it is read in order to prevent errors which may occur due to
+ the read being performed while the CIT is changing. This count may be continued after the register is read.
*/
UINT8 duscc_channel::do_dusccreg_cth_r()
@@ -912,15 +910,15 @@ UINT8 duscc_channel::do_dusccreg_cth_r()
/* Counter/Timer Low Register (CTLA, CTLB) Read only
- [7:0] lSB - A read of this 'register' provides the eight least significant bits of the current value of the counter/timer. It is
- recommended that the CIT be stopped via a stop counter command before it is read, in order to prevent errors which may occur due to
- the read being performed while the CIT is changing. This count may be continued after the register is read.
+ [7:0] lSB - A read of this 'register' provides the eight least significant bits of the current value of the counter/timer. It is
+ recommended that the CIT be stopped via a stop counter command before it is read, in order to prevent errors which may occur due to
+ the read being performed while the CIT is changing. This count may be continued after the register is read.
*/
UINT8 duscc_channel::do_dusccreg_ctl_r()
{
UINT8 ret = (m_ct & 0xff);
LOG(("%s(%02x)\n", FUNCNAME, ret));
- // return m_ctl;
+ // return m_ctl;
return ret;
}
@@ -1134,31 +1132,31 @@ int duscc_channel::get_tx_word_length()
// register read methods - see correspondning write method for details on each register
UINT8 duscc_channel::do_dusccreg_cmr1_r()
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, m_cmr1));
- return m_cmr1;
+ return m_cmr1;
}
UINT8 duscc_channel::do_dusccreg_cmr2_r()
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, m_cmr2));
- return m_cmr2;
+ return m_cmr2;
}
UINT8 duscc_channel::do_dusccreg_s1r_r()
{
LOG(("%s(%02x)\n", FUNCNAME, m_s1r));
- return m_s1r;
+ return m_s1r;
}
UINT8 duscc_channel::do_dusccreg_s2r_r()
{
LOG(("%s(%02x)\n", FUNCNAME, m_s2r));
- return m_s2r;
+ return m_s2r;
}
UINT8 duscc_channel::do_dusccreg_tpr_r()
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, m_tpr));
return m_tpr;
}
@@ -1227,9 +1225,9 @@ UINT8 duscc_channel::do_dusccreg_rxfifo_r()
}
UINT8 duscc_channel::do_dusccreg_rsr_r()
-{
+{
LOG(("%s: %02x\n", FUNCNAME, m_rsr));
- return (UINT8) m_rsr;
+ return (UINT8) m_rsr;
}
UINT8 duscc_channel::do_dusccreg_trsr_r()
@@ -1239,9 +1237,9 @@ UINT8 duscc_channel::do_dusccreg_trsr_r()
}
UINT8 duscc_channel::do_dusccreg_ictsr_r()
-{
- logerror("%s is not implemented yet\n", FUNCNAME);
- return (UINT8) m_ictsr;
+{
+ logerror("%s is not implemented yet\n", FUNCNAME);
+ return (UINT8) m_ictsr;
}
/* General Status Register (GSR)
@@ -1266,15 +1264,15 @@ UINT8 duscc_channel::do_dusccreg_ictsr_r()
receiver' command is invoked.
*/
UINT8 duscc_channel::do_dusccreg_gsr_r()
-{
+{
LOGR(("%s <- %02x\n", FUNCNAME, m_uart->m_gsr));
- return (UINT8) m_uart->m_gsr;
+ return (UINT8) m_uart->m_gsr;
}
UINT8 duscc_channel::do_dusccreg_ier_r()
-{
+{
LOGR(("%s <- %02x\n", FUNCNAME, m_uart->m_ier));
- return (UINT8) 0;
+ return (UINT8) 0;
}
UINT8 duscc_channel::do_dusccreg_cid_r()
@@ -1310,7 +1308,7 @@ UINT8 duscc_channel::do_dusccreg_ivr_ivrm_r()
}
UINT8 duscc_channel::do_dusccreg_icr_r()
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, m_uart->m_icr));
return m_uart->m_icr;
}
@@ -1376,9 +1374,9 @@ UINT8 duscc_channel::do_dusccreg_telr_r()
primary function of these registers is to define configuration of the channels and the function of the programmable pins. A channel
cannot be dynamically reconfigured. Do not write to CMRI or CMR2 if the receiver or transmitter is enabled.
*/
-/* CMR1 register -
- [7:6] Data Encoding - These bits select the data encoding for the received and transmitted data:
- 00 If the DPLL is set to NRZI mode (see DPLL commands), it selects positive logic (1 = high, 0 = low).
+/* CMR1 register -
+ [7:6] Data Encoding - These bits select the data encoding for the received and transmitted data:
+ 00 If the DPLL is set to NRZI mode (see DPLL commands), it selects positive logic (1 = high, 0 = low).
If the DPLL is set to FM mode (see DPLL commands), Manchester (bi-phase level) encoding is selected.
01 NRZI. Non-return-to-zero inverted.
10 FMO. Bi-phase space.
@@ -1514,7 +1512,7 @@ void duscc_channel::do_dusccreg_cmr2_w(UINT8 data)
}
/* SYN1/Secondary Address 1 Register (S1RA, S1RB)
- [7:O} Character Compare
+ [7:O} Character Compare
- In ASYNC mode this register holds a 5 to 8-bit long bit pattern which is ocmpared with received
characters. if a match occurs, the character compare status bit (RSR[7]) is set. This field is ignored if the receivEII is in a break
condition.
@@ -1526,10 +1524,10 @@ void duscc_channel::do_dusccreg_cmr2_w(UINT8 data)
TODO: Add check in receive_data and set status bits accordingly
*/
void duscc_channel::do_dusccreg_s1r_w(UINT8 data)
-{
+{
LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data));
m_s1r = data;
- return;
+ return;
}
/* SYN2ISecondary Address 2 Register (S2RA, S2RB)
@@ -1540,10 +1538,10 @@ void duscc_channel::do_dusccreg_s1r_w(UINT8 data)
match. If parity Is specified, then any unused bits in this register must be programmed to zeros. In BOP secondary mode using two
address octets, it contains the partial address used to compare the second received address octet.*/
void duscc_channel::do_dusccreg_s2r_w(UINT8 data)
-{
+{
LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data));
m_s2r = data;
- return;
+ return;
}
/* Transmitter Parameter Register (TPRA, TPRB)
@@ -1907,7 +1905,7 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
default: LOG(("Wrong programming\n")); break; // Should never happen
}
- return;
+ return;
}
/*
@@ -1941,7 +1939,7 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
/* Enable transmitter. Enables transmitter operation, conditioned by the state of
the CTS ENABLE Tx bit, TPR[2]. Has no effect if invoked when the transmitter has
previously been enabled.*/
- case REG_CCR_ENABLE_TX: LOG(("- Enable Tx\n"));
+ case REG_CCR_ENABLE_TX: LOG(("- Enable Tx\n"));
m_uart->m_gsr |= (m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
m_tra = 1;
set_tra_rate(m_brg_tx_rate);
@@ -1995,7 +1993,7 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
duscc_timer->adjust(attotime::from_hz(rate), TIMER_ID_RTXC, attotime::from_hz(rate));
break;
- /* Stop. Stops the counter/timer and prescaler. Since the command may be asynchronous with the selected clock source,
+ /* Stop. Stops the counter/timer and prescaler. Since the command may be asynchronous with the selected clock source,
the counter/timer and/or prescaler may count one or more additional cycles before stopping.. */
case REG_CCR_STOP_TIMER: LOG(("- Stop Counter/Timer\n"));
duscc_timer->adjust(attotime::never);
@@ -2073,21 +2071,21 @@ void duscc_channel::do_dusccreg_txfifo_w(UINT8 data)
before reading the character data from RxFIFO. For block status, the status register is initially cleared and then read after the
message is received. Asserted status bits can be programmed to generate an interrupt (see Interrupt Enable Register).*/
void duscc_channel::do_dusccreg_rsr_w(UINT8 data)
-{
+{
LOG(("%s: %02x\n", FUNCNAME, data));
m_rsr &= ~data; // Clear only bits which are 1:s
- return;
+ return;
}
void duscc_channel::do_dusccreg_trsr_w(UINT8 data)
-{
+{
LOG(("%s: %02x - not supported yet\n", FUNCNAME, data));
m_trsr = data;
return;
}
void duscc_channel::do_dusccreg_ictsr_w(UINT8 data)
-{
+{
LOG(("%s: %02x - not supported yet\n", FUNCNAME, data));
m_ictsr = data;
return;
@@ -2095,57 +2093,57 @@ void duscc_channel::do_dusccreg_ictsr_w(UINT8 data)
/* This register provides a 'quick look' at the overall status of both channels of the DUSCC. A write to this register with ls at the
corresponding bit pOSitions causes TxRDY (bits 5 and 1) and/or RxRDY (bits 4 and 0) to be reset. The other status bits can be reset
- only by resetting the individual status bits that they point to.
+ only by resetting the individual status bits that they point to.
[7] Channel 8 External or Coutnerrrimer Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4].
[6] Channel B Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: RSRB[7:0], TRSRB[7:3].
- [5] Channel 8 Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B
+ [5] Channel 8 Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B
transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4j. This bit can be asserted only
- when the transmitter is enabled. Reselling the transmitter negates TxRDY.
+ when the transmitter is enabled. Reselling the transmitter negates TxRDY.
[4] Channel 8 Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel B receiver
FIFO to be read by the CPU. See deSCription of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel B
- receiver' command is invoked.
+ receiver' command is invoked.
[3] Channel A External or Countermmer Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
[2] Channel A Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: RSRA(7:0], TRSRA(7:3].
- [1) Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
+ [1) Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4]. This bit can be asserted only
when the transmitter is enabled. Resetting the transmitter negates TxRDY.
[0) Channel A Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel A receiver
FIFO to be read by the CPU. See description of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel A
- receiver' command is invoked.*/
+ receiver' command is invoked.*/
void duscc_channel::do_dusccreg_gsr_w(UINT8 data)
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, data));
m_uart->m_gsr &= (data & REG_GSR_XXREADY_MASK); // Reset only XXREADY bits, the rest needs to be reset by the source
- return; // TODO: Check of the XXREADY source bits should be reset too
+ return; // TODO: Check of the XXREADY source bits should be reset too
}
/* Interrupt Enable Register (IERA, IERB)
This register controls whether the assertion of bits in the channel's status registers causes an interrupt to be generated. An additional
condition for an interrupt to be generated is that the channel's master interrupt enabled bit, ICR[O] or ICR[1], be asserted.*/
void duscc_channel::do_dusccreg_ier_w(UINT8 data)
-{
+{
m_ier = data;
LOG(("%s(%02x)\n", FUNCNAME, data));
m_uart->check_interrupts();
- return;
+ return;
}
void duscc_channel::do_dusccreg_ivr_w(UINT8 data)
-{
+{
m_uart->m_ivr = data;
LOG(("%s(%02x)\n", FUNCNAME, data));
return;
}
void duscc_channel::do_dusccreg_icr_w(UINT8 data)
-{
+{
m_uart->m_icr = data;
LOG(("%s(%02x)\n", FUNCNAME, data));
return;
}
void duscc_channel::do_dusccreg_sea_rea_w(UINT8 data)
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, data));
if ( m_uart->m_variant != SET_CMOS )
{
@@ -2157,7 +2155,7 @@ void duscc_channel::do_dusccreg_sea_rea_w(UINT8 data)
m_a7 = (m_index == duscc_device::CHANNEL_A ? 0x40 : 0); // Set or Reset depending in channel
}
- return;
+ return;
}
void duscc_channel::do_dusccreg_mrr_w(UINT8 data){ logerror("%s is not implemented yet\n", FUNCNAME); return; }
@@ -2178,36 +2176,36 @@ UINT8 duscc_channel::read(offs_t &offset)
switch (reg)
{
- case REG_CMR1: data = do_dusccreg_cmr1_r(); break;
- case REG_CMR2: data = do_dusccreg_cmr2_r(); break;
- case REG_S1R: data = do_dusccreg_s1r_r(); break;
- case REG_S2R: data = do_dusccreg_s2r_r(); break;
- case REG_TPR: data = do_dusccreg_tpr_r(); break;
- case REG_TTR: data = do_dusccreg_ttr_r(); break;
- case REG_RPR: data = do_dusccreg_rpr_r(); break;
- case REG_RTR: data = do_dusccreg_rtr_r(); break;
- case REG_CTPRH: data = do_dusccreg_ctprh_r(); break;
- case REG_CTPRL: data = do_dusccreg_ctprl_r(); break;
- case REG_CTCR: data = do_dusccreg_ctcr_r(); break;
- case REG_OMR: data = do_dusccreg_omr_r(); break;
- case REG_CTH: data = do_dusccreg_cth_r(); break;
- case REG_CTL: data = do_dusccreg_ctl_r(); break;
- case REG_PCR: data = do_dusccreg_pcr_r(); break;
- case REG_CCR: data = do_dusccreg_ccr_r(); break;
- case REG_RXFIFO_0: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_1: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_2: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_3: data = do_dusccreg_rxfifo_r(); break;
- case REG_RSR: data = do_dusccreg_rsr_r(); break;
- case REG_TRSR: data = do_dusccreg_trsr_r(); break;
- case REG_ICTSR: data = do_dusccreg_ictsr_r(); break;
- case REG_GSR: data = do_dusccreg_gsr_r(); break;
- case REG_IER: data = do_dusccreg_ier_r(); break;
- // case REG_IVR: data = do_dusccreg_ivr_r(); break; // Chan A = IVR, B = IVRM
- case REG_IVRM: data = do_dusccreg_ivr_ivrm_r(); break;
- case REG_ICR: data = do_dusccreg_icr_r(); break;
+ case REG_CMR1: data = do_dusccreg_cmr1_r(); break;
+ case REG_CMR2: data = do_dusccreg_cmr2_r(); break;
+ case REG_S1R: data = do_dusccreg_s1r_r(); break;
+ case REG_S2R: data = do_dusccreg_s2r_r(); break;
+ case REG_TPR: data = do_dusccreg_tpr_r(); break;
+ case REG_TTR: data = do_dusccreg_ttr_r(); break;
+ case REG_RPR: data = do_dusccreg_rpr_r(); break;
+ case REG_RTR: data = do_dusccreg_rtr_r(); break;
+ case REG_CTPRH: data = do_dusccreg_ctprh_r(); break;
+ case REG_CTPRL: data = do_dusccreg_ctprl_r(); break;
+ case REG_CTCR: data = do_dusccreg_ctcr_r(); break;
+ case REG_OMR: data = do_dusccreg_omr_r(); break;
+ case REG_CTH: data = do_dusccreg_cth_r(); break;
+ case REG_CTL: data = do_dusccreg_ctl_r(); break;
+ case REG_PCR: data = do_dusccreg_pcr_r(); break;
+ case REG_CCR: data = do_dusccreg_ccr_r(); break;
+ case REG_RXFIFO_0: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_1: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_2: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_3: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RSR: data = do_dusccreg_rsr_r(); break;
+ case REG_TRSR: data = do_dusccreg_trsr_r(); break;
+ case REG_ICTSR: data = do_dusccreg_ictsr_r(); break;
+ case REG_GSR: data = do_dusccreg_gsr_r(); break;
+ case REG_IER: data = do_dusccreg_ier_r(); break;
+ // case REG_IVR: data = do_dusccreg_ivr_r(); break; // Chan A = IVR, B = IVRM
+ case REG_IVRM: data = do_dusccreg_ivr_ivrm_r(); break;
+ case REG_ICR: data = do_dusccreg_icr_r(); break;
// CDUSCC Extended registers - requires A7 to be set through REG_SEA
- case REG_CID: data = do_dusccreg_cid_r(); break;
+ case REG_CID: data = do_dusccreg_cid_r(); break;
default:
logerror(" \"%s\" %s: %c : Unsupported RRx register:%02x\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg);
}
@@ -2228,44 +2226,44 @@ void duscc_channel::write(UINT8 data, offs_t &offset)
LOG(("\"%s\" %s: %c : Register write '%02x' -> [%02x]", m_owner->tag(), FUNCNAME, 'A' + m_index, data, reg ));
switch (reg)
{
- case REG_CMR1: do_dusccreg_cmr1_w(data); break;
- case REG_CMR2: do_dusccreg_cmr2_w(data); break;
- case REG_S1R: do_dusccreg_s1r_w(data); break;
- case REG_S2R: do_dusccreg_s2r_w(data); break;
- case REG_TPR: do_dusccreg_tpr_w(data); break;
- case REG_TTR: do_dusccreg_ttr_w(data); break;
- case REG_RPR: do_dusccreg_rpr_w(data); break;
- case REG_RTR: do_dusccreg_rtr_w(data); break;
- case REG_CTPRH: do_dusccreg_ctprh_w(data); break;
- case REG_CTPRL: do_dusccreg_ctprl_w(data); break;
- case REG_CTCR: do_dusccreg_ctcr_w(data); break;
- case REG_OMR: do_dusccreg_omr_w(data); break;
-// case REG_CTH: LOG(("REG_CTH \n")); break; // Read only register
-// case REG_CTL: LOG(("REG_CTL \n")); break; // Read only register
- case REG_PCR: do_dusccreg_pcr_w(data); break;
- case REG_CCR: do_dusccreg_ccr_w(data); break;
- case REG_TXFIFO_0: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_1: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_2: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_3: do_dusccreg_txfifo_w(data); break;
- case REG_RSR: do_dusccreg_rsr_w(data); break;
- case REG_TRSR: do_dusccreg_trsr_w(data); break;
- case REG_ICTSR: do_dusccreg_ictsr_w(data); break;
- case REG_GSR: do_dusccreg_gsr_w(data); break;
- case REG_IER: do_dusccreg_ier_w(data); break;
- case REG_IVR: do_dusccreg_ivr_w(data); break;
- case REG_ICR: do_dusccreg_icr_w(data); break;
+ case REG_CMR1: do_dusccreg_cmr1_w(data); break;
+ case REG_CMR2: do_dusccreg_cmr2_w(data); break;
+ case REG_S1R: do_dusccreg_s1r_w(data); break;
+ case REG_S2R: do_dusccreg_s2r_w(data); break;
+ case REG_TPR: do_dusccreg_tpr_w(data); break;
+ case REG_TTR: do_dusccreg_ttr_w(data); break;
+ case REG_RPR: do_dusccreg_rpr_w(data); break;
+ case REG_RTR: do_dusccreg_rtr_w(data); break;
+ case REG_CTPRH: do_dusccreg_ctprh_w(data); break;
+ case REG_CTPRL: do_dusccreg_ctprl_w(data); break;
+ case REG_CTCR: do_dusccreg_ctcr_w(data); break;
+ case REG_OMR: do_dusccreg_omr_w(data); break;
+// case REG_CTH: LOG(("REG_CTH \n")); break; // Read only register
+// case REG_CTL: LOG(("REG_CTL \n")); break; // Read only register
+ case REG_PCR: do_dusccreg_pcr_w(data); break;
+ case REG_CCR: do_dusccreg_ccr_w(data); break;
+ case REG_TXFIFO_0: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_1: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_2: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_3: do_dusccreg_txfifo_w(data); break;
+ case REG_RSR: do_dusccreg_rsr_w(data); break;
+ case REG_TRSR: do_dusccreg_trsr_w(data); break;
+ case REG_ICTSR: do_dusccreg_ictsr_w(data); break;
+ case REG_GSR: do_dusccreg_gsr_w(data); break;
+ case REG_IER: do_dusccreg_ier_w(data); break;
+ case REG_IVR: do_dusccreg_ivr_w(data); break;
+ case REG_ICR: do_dusccreg_icr_w(data); break;
// CDUSCC Extended registers - requires A7 to be set through REG_SEA
-// case REG_MRR: LOG(("REG_MRR \n")); break;
- case REG_SEA: do_dusccreg_sea_rea_w(data); break; /* Also supports REG_REA depending on which channel is written to */
- case REG_IER1: LOG(("REG_IER1\n")); break;
- case REG_IER2: LOG(("REG_IER2\n")); break;
- case REG_IER3: LOG(("REG_IER3\n")); break;
- case REG_TRCR: LOG(("REG_TRCR\n")); break;
- case REG_RFLR: LOG(("REG_RFLR\n")); break;
- case REG_FTLR: LOG(("REG_FTLR\n")); break;
- case REG_TRMSR: LOG(("REG_TRMSR\n")); break;
- case REG_TELR: LOG(("REG_TELR\n")); break;
+// case REG_MRR: LOG(("REG_MRR \n")); break;
+ case REG_SEA: do_dusccreg_sea_rea_w(data); break; /* Also supports REG_REA depending on which channel is written to */
+ case REG_IER1: LOG(("REG_IER1\n")); break;
+ case REG_IER2: LOG(("REG_IER2\n")); break;
+ case REG_IER3: LOG(("REG_IER3\n")); break;
+ case REG_TRCR: LOG(("REG_TRCR\n")); break;
+ case REG_RFLR: LOG(("REG_RFLR\n")); break;
+ case REG_FTLR: LOG(("REG_FTLR\n")); break;
+ case REG_TRMSR: LOG(("REG_TRMSR\n")); break;
+ case REG_TELR: LOG(("REG_TELR\n")); break;
default:
logerror(" \"%s\" %s: %c : Unsupported WRx register:%02x(%02x)\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg, data);
@@ -2323,7 +2321,7 @@ void duscc_channel::receive_data(UINT8 data)
{
// receive overrun error detected
m_rsr |= REG_RSR_OVERRUN_ERROR;
- // m_rx_error_fifo[m_rx_fifo_wp] &= ~REG_RSR_OVERRUN_ERROR; // The overrun error is NOT fifoed obviously...
+ // m_rx_error_fifo[m_rx_fifo_wp] &= ~REG_RSR_OVERRUN_ERROR; // The overrun error is NOT fifoed obviously...
logerror("Receive_data() Error %02x\n", m_rsr);
}
else
@@ -2338,7 +2336,7 @@ void duscc_channel::receive_data(UINT8 data)
m_rx_fifo_wp = 0;
}
- // if (m_eir & REG_IER_)
+ // if (m_eir & REG_IER_)
}
}
diff --git a/src/devices/machine/scnxx562.h b/src/devices/machine/scnxx562.h
index ee07df1b124..5365f5f70ac 100644
--- a/src/devices/machine/scnxx562.h
+++ b/src/devices/machine/scnxx562.h
@@ -241,13 +241,13 @@ public:
UINT8 m_ttr;
UINT8 m_rpr;
UINT8 m_rtr;
- // UINT8 m_ctprh;
- // UINT8 m_ctprl;
+ // UINT8 m_ctprh;
+ // UINT8 m_ctprl;
unsigned int m_ctpr;
UINT8 m_ctcr;
UINT8 m_omr;
- // UINT8 m_cth;
- // UINT8 m_ctl;
+ // UINT8 m_cth;
+ // UINT8 m_ctl;
unsigned int m_ct;
UINT8 m_pcr;
UINT8 m_ccr;
@@ -256,13 +256,13 @@ public:
UINT8 m_rsr;
UINT8 m_trsr;
UINT8 m_ictsr;
- // UINT8 m_gsr; // moved to the device since it is global
+ // UINT8 m_gsr; // moved to the device since it is global
UINT8 m_ier;
// UINT8 m_rea;
UINT8 m_cid;
//UINT8 m_ivr;
//UINT8 m_icr;
- // UINT8 m_sea;
+ // UINT8 m_sea;
//UINT8 m_ivrm;
UINT8 m_mrr;
UINT8 m_ier1;
@@ -275,12 +275,12 @@ public:
UINT8 m_telr;
protected:
- enum // Needs to be 0-3 in unmodified prio level
+ enum // Needs to be 0-3 in unmodified prio level
{
- INT_RXREADY = 0,
- INT_TXREADY = 1,
- INT_RXTXSTAT = 2,
- INT_EXTCTSTAT = 3
+ INT_RXREADY = 0,
+ INT_TXREADY = 1,
+ INT_RXTXSTAT = 2,
+ INT_EXTCTSTAT = 3
};
enum
@@ -292,9 +292,9 @@ protected:
REG_CCR_ENABLE_RX = 0x42,
REG_CCR_DISABLE_RX = 0x43,
REG_CCR_START_TIMER = 0x80,
- REG_CCR_STOP_TIMER = 0x81,
- REG_CCR_PRST_FFFF = 0x82,
- REG_CCR_PRST_CTPR = 0x83,
+ REG_CCR_STOP_TIMER = 0x81,
+ REG_CCR_PRST_FFFF = 0x82,
+ REG_CCR_PRST_CTPR = 0x83,
};
enum
@@ -403,24 +403,24 @@ protected:
enum
{
- REG_RSR_CHAR_COMPARE = 0x80,
- REG_RSR_OVERRUN_ERROR = 0x20,
- REG_RSR_FRAMING_ERROR = 0x02,
- REG_RSR_PARITY_ERROR = 0x01,
+ REG_RSR_CHAR_COMPARE = 0x80,
+ REG_RSR_OVERRUN_ERROR = 0x20,
+ REG_RSR_FRAMING_ERROR = 0x02,
+ REG_RSR_PARITY_ERROR = 0x01,
};
enum
{
- REG_GSR_CHAN_A_RXREADY = 0x01,
- REG_GSR_CHAN_B_RXREADY = 0x10,
- REG_GSR_CHAN_A_TXREADY = 0x02,
- REG_GSR_CHAN_B_TXREADY = 0x20,
- REG_GSR_XXREADY_MASK = 0x33
+ REG_GSR_CHAN_A_RXREADY = 0x01,
+ REG_GSR_CHAN_B_RXREADY = 0x10,
+ REG_GSR_CHAN_A_TXREADY = 0x02,
+ REG_GSR_CHAN_B_TXREADY = 0x20,
+ REG_GSR_XXREADY_MASK = 0x33
};
enum
{
- REG_ICTSR_ZERO_DET = 0x40,
+ REG_ICTSR_ZERO_DET = 0x40,
REG_ICTSR_DELTA_CTS = 0x10,
REG_ICTSR_DCD = 0x08,
REG_ICTSR_CTS = 0x04,
@@ -428,14 +428,14 @@ protected:
enum
{
- REG_IER_DCD_CTS = 0x80,
- REG_IER_TXRDY = 0x40,
- REG_IER_TRSR73 = 0x20,
- REG_IER_RXRDY = 0x10,
- REG_IER_RSR76 = 0x08,
- REG_IER_RSR54 = 0x04,
- REG_IER_RSR32 = 0x02,
- REG_IER_RSR10 = 0x01,
+ REG_IER_DCD_CTS = 0x80,
+ REG_IER_TXRDY = 0x40,
+ REG_IER_TRSR73 = 0x20,
+ REG_IER_RXRDY = 0x10,
+ REG_IER_RSR76 = 0x08,
+ REG_IER_RSR54 = 0x04,
+ REG_IER_RSR32 = 0x02,
+ REG_IER_RSR10 = 0x01,
};
// Register offsets, stripped from channel bit 0x20 but including A7 bit
@@ -494,13 +494,13 @@ protected:
UINT8 m_rtxc;
UINT8 m_trxc;
-
+
enum
{
- REG_CTCR_ZERO_DET_INT = 0x80,
- REG_CTCR_ZERO_DET_CTL = 0x40,
- REG_CTCR_TIM_OC = 0x20,
+ REG_CTCR_ZERO_DET_INT = 0x80,
+ REG_CTCR_ZERO_DET_CTL = 0x40,
+ REG_CTCR_TIM_OC = 0x20,
};
enum
@@ -731,15 +731,15 @@ protected:
enum
{
- REG_ICR_CHB = 0x01,
- REG_ICR_CHA = 0x02,
- REG_ICR_VEC_MOD = 0x04,
- REG_ICR_V2V4_MOD = 0x08,
- REG_ICR_PRIO_MASK = 0xC0,
- REG_ICR_PRIO_AHI = 0x00,
- REG_ICR_PRIO_BHI = 0x40,
- REG_ICR_PRIO_AINT = 0x80,
- REG_ICR_PRIO_BINT = 0xC0,
+ REG_ICR_CHB = 0x01,
+ REG_ICR_CHA = 0x02,
+ REG_ICR_VEC_MOD = 0x04,
+ REG_ICR_V2V4_MOD = 0x08,
+ REG_ICR_PRIO_MASK = 0xC0,
+ REG_ICR_PRIO_AHI = 0x00,
+ REG_ICR_PRIO_BHI = 0x40,
+ REG_ICR_PRIO_AINT = 0x80,
+ REG_ICR_PRIO_BINT = 0xC0,
};
};
diff --git a/src/devices/machine/z80scc.cpp b/src/devices/machine/z80scc.cpp
index 5e1e7f984f9..04a197d0e1a 100644
--- a/src/devices/machine/z80scc.cpp
+++ b/src/devices/machine/z80scc.cpp
@@ -79,7 +79,7 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
// printf("TAG %lld %s%s Data:%d\n", machine().firstcpu->total_cycles(), __PRETTY_FUNCTION__, m_owner->tag(), data);
#define VERBOSE 0
-#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
+#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
#define LOG(x) LOGPRINT(x)
#define LOGR(x)
#define LOGSETUP(x) LOGPRINT(x)
@@ -1602,7 +1602,7 @@ void z80scc_channel::do_sccreg_wr4(UINT8 data)
if (data == m_wr4)
{
logerror("- supressing reinit of Tx as write to wr4 is identical to previous value\n");
- }
+ }
else
{
m_wr4 = data;
@@ -1622,7 +1622,7 @@ void z80scc_channel::do_sccreg_wr5(UINT8 data)
if (data == m_wr5)
{
logerror("- supressing reinit of Tx as write to wr5 is identical to previous value\n");
- }
+ }
else
{
m_wr5 = data;
@@ -1962,22 +1962,22 @@ void z80scc_channel::control_write(UINT8 data)
/* TODO. Sort out 80X30 & other SCC variants limitations in register access */
switch (reg)
{
- case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); break;
- case REG_WR1_INT_DMA_ENABLE: do_sccreg_wr1(data); m_uart->check_interrupts(); break;
- case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break;
- case REG_WR3_RX_CONTROL: do_sccreg_wr3(data); break;
- case REG_WR4_RX_TX_MODES: do_sccreg_wr4(data); break;
- case REG_WR5_TX_CONTROL: do_sccreg_wr5(data); break;
- case REG_WR6_SYNC_OR_SDLC_A: do_sccreg_wr6(data); break;
- case REG_WR7_SYNC_OR_SDLC_F: do_sccreg_wr7(data); break;
- case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break;
- case REG_WR9_MASTER_INT_CTRL: do_sccreg_wr9(data); break;
- case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break;
- case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break;
- case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break;
- case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break;
- case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break;
- case REG_WR15_EXT_ST_INT_CTRL: do_sccreg_wr15(data); break;
+ case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); break;
+ case REG_WR1_INT_DMA_ENABLE: do_sccreg_wr1(data); m_uart->check_interrupts(); break;
+ case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break;
+ case REG_WR3_RX_CONTROL: do_sccreg_wr3(data); break;
+ case REG_WR4_RX_TX_MODES: do_sccreg_wr4(data); break;
+ case REG_WR5_TX_CONTROL: do_sccreg_wr5(data); break;
+ case REG_WR6_SYNC_OR_SDLC_A: do_sccreg_wr6(data); break;
+ case REG_WR7_SYNC_OR_SDLC_F: do_sccreg_wr7(data); break;
+ case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break;
+ case REG_WR9_MASTER_INT_CTRL: do_sccreg_wr9(data); break;
+ case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break;
+ case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break;
+ case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break;
+ case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break;
+ case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break;
+ case REG_WR15_EXT_ST_INT_CTRL: do_sccreg_wr15(data); break;
default:
logerror("\"%s\": %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
}
@@ -2361,14 +2361,14 @@ WRITE_LINE_MEMBER( z80scc_channel::txc_w )
}
//--------------------------------------------------------------------------------------------------------
-// safe_transmit_register_reset - wait for the transmitter shift register to be
-// emptied before apply the new value of wr5 and/or wr4. In the case of a Tx FIFO
+// safe_transmit_register_reset - wait for the transmitter shift register to be
+// emptied before apply the new value of wr5 and/or wr4. In the case of a Tx FIFO
// the change will occur before next character is started. From the specification:
//
// "The character length may be changed on the fly, but the desired length must be selected before the
// character is loaded into the Transmit Shift register from the transmit data FIFO. The easiest way to
// ensure this is to write to WR5 to change the character length before writing the data to the transmit
-// buffer."
+// buffer."
//
// Right now we only detect the problem and log an error
//---------------------------------------------------------------------------------------------------------
@@ -2424,11 +2424,11 @@ void z80scc_channel::update_serial()
if (m_brg_rate != 0 || m_wr14 & WR14_BRG_ENABLE)
{
- if (m_brg_rate == 1)
+ if (m_brg_rate == 1)
{
m_brg_rate = 0; // BRG beeing disabled
}
- else // or enabled
+ else // or enabled
{
m_brg_const = 2 + (m_wr13 << 8 | m_wr12);
int rate = m_owner->clock() / (m_brg_const == 0 ? 1 : m_brg_const);
diff --git a/src/devices/sound/qs1000.h b/src/devices/sound/qs1000.h
index 6894164fb38..d94d964ed19 100644
--- a/src/devices/sound/qs1000.h
+++ b/src/devices/sound/qs1000.h
@@ -102,7 +102,7 @@ public:
DECLARE_READ8_MEMBER( p3_r );
DECLARE_WRITE8_MEMBER( p3_w );
-
+
DECLARE_READ8_MEMBER( data_to_i8052 );
enum
diff --git a/src/devices/sound/ym2151.cpp b/src/devices/sound/ym2151.cpp
index 3f149267900..a753e6ede27 100644
--- a/src/devices/sound/ym2151.cpp
+++ b/src/devices/sound/ym2151.cpp
@@ -1103,7 +1103,7 @@ void ym2151_device::chan_calc(unsigned int chan)
env = volume_calc(op+3); /* C2 */
if (env < ENV_QUIET)
chanout[chan] += op_calc(op+3, env, c2);
- // if(chan==3) printf("%d\n", chanout[chan]);
+ // if(chan==3) printf("%d\n", chanout[chan]);
/* M1 */
op->mem_value = mem;
diff --git a/src/devices/sound/ym2413.cpp b/src/devices/sound/ym2413.cpp
index 78206bca856..5fd92f9946f 100644
--- a/src/devices/sound/ym2413.cpp
+++ b/src/devices/sound/ym2413.cpp
@@ -1679,6 +1679,6 @@ const device_type YM2413 = &device_creator<ym2413_device>;
ym2413_device::ym2413_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, YM2413, "YM2413", tag, owner, clock, "ym2413", __FILE__),
- device_sound_interface(mconfig, *this)
+ device_sound_interface(mconfig, *this)
{
}
diff --git a/src/devices/sound/ym2413.h b/src/devices/sound/ym2413.h
index 371066cdfa4..5a7164faec9 100644
--- a/src/devices/sound/ym2413.h
+++ b/src/devices/sound/ym2413.h
@@ -8,7 +8,7 @@
#include "emu.h"
class ym2413_device : public device_t,
- public device_sound_interface
+ public device_sound_interface
{
public:
ym2413_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
diff --git a/src/devices/video/ef9365.cpp b/src/devices/video/ef9365.cpp
index f2a69d053ab..d7277e82604 100644
--- a/src/devices/video/ef9365.cpp
+++ b/src/devices/video/ef9365.cpp
@@ -123,7 +123,7 @@ const char * commands_names[]=
// devices
const device_type EF9365 = &device_creator<ef9365_device>;
-
+
ROM_START( ef9365 )
ROM_REGION( 0x1E0, "ef9365", 0 )
ROM_LOAD( "charset_ef9365.rom", 0x0000, 0x01E0, CRC(8d3053be) SHA1(0f9a64d217a0f7f04ee0720d49c5b680ad0ae359) )
diff --git a/src/devices/video/zeus2.cpp b/src/devices/video/zeus2.cpp
index 655df3f3084..0f885af9b3e 100644
--- a/src/devices/video/zeus2.cpp
+++ b/src/devices/video/zeus2.cpp
@@ -967,7 +967,7 @@ void zeus2_device::zeus2_draw_model(UINT32 baseaddr, UINT16 count, int logit)
if (logit)
{
//if ((cmd == 0x38) || (cmd == 0x2d))
- // log_render_info();
+ // log_render_info();
int offs;
logerror("\t");
for (offs = 0; offs < databufcount; offs++)
@@ -1014,8 +1014,8 @@ void zeus2_device::zeus2_draw_model(UINT32 baseaddr, UINT16 count, int logit)
default:
//if (quadsize == 10)
//{
- // logerror("Correcting quad size\n");
- // quadsize = 14;
+ // logerror("Correcting quad size\n");
+ // quadsize = 14;
//}
if (logit)
logerror("unknown model data\n");
@@ -1212,9 +1212,9 @@ void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texdata, i
float y = vert[i].y;
float z = vert[i].p[0];
//if (0) {
- // x *= xScale;
- // y *= yScale;
- // z *= zScale;
+ // x *= xScale;
+ // y *= yScale;
+ // z *= zScale;
//}
vert[i].x = x * m_state->zeus_matrix[0][0] + y * m_state->zeus_matrix[0][1] + z * m_state->zeus_matrix[0][2];
diff --git a/src/devices/video/zeus2.h b/src/devices/video/zeus2.h
index 135d900f86c..d90a7b33c07 100644
--- a/src/devices/video/zeus2.h
+++ b/src/devices/video/zeus2.h
@@ -227,7 +227,7 @@ public:
// Convert 0xRRRRCCCC to frame buffer addresss
//inline UINT32 frame_addr_from_expanded_addr(UINT32 addr)
//{
- // return (((addr & 0x3ff0000) >> (16 - 9 + 1)) | (addr & 0x1ff)) << 1;
+ // return (((addr & 0x3ff0000) >> (16 - 9 + 1)) | (addr & 0x1ff)) << 1;
//}
// Convert Physical 0xRRRRCCCC to frame buffer addresss
diff --git a/src/emu/debug/debugcpu.h b/src/emu/debug/debugcpu.h
index aa2018201dd..66bbe48e1f2 100644
--- a/src/emu/debug/debugcpu.h
+++ b/src/emu/debug/debugcpu.h
@@ -350,7 +350,7 @@ private:
FILE & m_file; // tracing file for this CPU
std::string m_action; // action to perform during a trace
offs_t m_history[TRACE_LOOPS]; // history of recent PCs
- bool m_detect_loops; // whether or not we should detect loops
+ bool m_detect_loops; // whether or not we should detect loops
int m_loops; // number of instructions in a loop
int m_nextdex; // next index
bool m_trace_over; // true if we're tracing over
diff --git a/src/emu/debug/dvstate.cpp b/src/emu/debug/dvstate.cpp
index 55dc0593a86..62d792cc9a7 100644
--- a/src/emu/debug/dvstate.cpp
+++ b/src/emu/debug/dvstate.cpp
@@ -285,7 +285,7 @@ void debug_view_state::view_update()
}
}
}
-
+
// fill the rest with blanks
while (visible && (col < m_visible.x))
{
diff --git a/src/emu/didisasm.h b/src/emu/didisasm.h
index 474cc2b5079..d92c90acc3b 100644
--- a/src/emu/didisasm.h
+++ b/src/emu/didisasm.h
@@ -60,7 +60,6 @@ typedef device_delegate<offs_t (device_t &device, char *buffer, offs_t pc, const
// class representing interface-specific live disasm
class device_disasm_interface : public device_interface
{
-
public:
// construction/destruction
device_disasm_interface(const machine_config &mconfig, device_t &device);
diff --git a/src/emu/diimage.cpp b/src/emu/diimage.cpp
index 72f40e9f758..c71d506f4b3 100644
--- a/src/emu/diimage.cpp
+++ b/src/emu/diimage.cpp
@@ -56,7 +56,7 @@ const image_device_type_info device_image_interface::m_device_info_array[] =
//-------------------------------------------------
image_device_format::image_device_format(const std::string &name, const std::string &description, const std::string &extensions, const std::string &optspec)
- : m_name(name), m_description(description), m_optspec(optspec)
+ : m_name(name), m_description(description), m_optspec(optspec)
{
std::regex comma_regex("\\,");
std::copy(
@@ -180,7 +180,7 @@ void device_image_interface::device_compute_hash(util::hash_collection &hashes,
}
//-------------------------------------------------
-// set_image_filename - specifies the filename of
+// set_image_filename - specifies the filename of
// an image
//-------------------------------------------------
@@ -221,7 +221,7 @@ image_error_t device_image_interface::set_image_filename(const char *filename)
****************************************************************************/
//-------------------------------------------------
-// device_get_named_creatable_format -
+// device_get_named_creatable_format -
// accesses a specific image format available for
// image creation by name
//-------------------------------------------------
@@ -240,8 +240,8 @@ const image_device_format *device_image_interface::device_get_named_creatable_fo
****************************************************************************/
//-------------------------------------------------
-// image_clear_error - clear out any specified
-// error
+// image_clear_error - clear out any specified
+// error
//-------------------------------------------------
void device_image_interface::clear_error()
@@ -256,8 +256,8 @@ void device_image_interface::clear_error()
//-------------------------------------------------
-// error - returns the error text for an image
-// error
+// error - returns the error text for an image
+// error
//-------------------------------------------------
static const char *const messages[] =
@@ -280,7 +280,7 @@ const char *device_image_interface::error()
//-------------------------------------------------
-// seterror - specifies an error on an image
+// seterror - specifies an error on an image
//-------------------------------------------------
void device_image_interface::seterror(image_error_t err, const char *message)
@@ -296,8 +296,8 @@ void device_image_interface::seterror(image_error_t err, const char *message)
//-------------------------------------------------
-// message - used to display a message while
-// loading
+// message - used to display a message while
+// loading
//-------------------------------------------------
void device_image_interface::message(const char *format, ...)
@@ -322,9 +322,9 @@ void device_image_interface::message(const char *format, ...)
***************************************************************************/
//-------------------------------------------------
-// try_change_working_directory - tries to change
-// the working directory, but only if the directory
-// actually exists
+// try_change_working_directory - tries to change
+// the working directory, but only if the directory
+// actually exists
//-------------------------------------------------
bool device_image_interface::try_change_working_directory(const char *subdir)
@@ -357,8 +357,8 @@ bool device_image_interface::try_change_working_directory(const char *subdir)
//-------------------------------------------------
-// setup_working_directory - sets up the working
-// directory according to a few defaults
+// setup_working_directory - sets up the working
+// directory according to a few defaults
//-------------------------------------------------
void device_image_interface::setup_working_directory()
@@ -396,7 +396,7 @@ const char * device_image_interface::working_directory()
//-------------------------------------------------
-// get_software_region
+// get_software_region
//-------------------------------------------------
UINT8 *device_image_interface::get_software_region(const char *tag)
@@ -413,7 +413,7 @@ UINT8 *device_image_interface::get_software_region(const char *tag)
//-------------------------------------------------
-// image_get_software_region_length
+// image_get_software_region_length
//-------------------------------------------------
UINT32 device_image_interface::get_software_region_length(const char *tag)
@@ -428,7 +428,7 @@ UINT32 device_image_interface::get_software_region_length(const char *tag)
//-------------------------------------------------
-// image_get_feature
+// image_get_feature
//-------------------------------------------------
const char *device_image_interface::get_feature(const char *feature_name)
@@ -534,10 +534,10 @@ UINT32 device_image_interface::crc()
//-------------------------------------------------
-// battery_load - retrieves the battery
-// backed RAM for an image. The file name is
-// created from the machine driver name and the
-// image name.
+// battery_load - retrieves the battery
+// backed RAM for an image. The file name is
+// created from the machine driver name and the
+// image name.
//-------------------------------------------------
void device_image_interface::battery_load(void *buffer, int length, int fill)
@@ -579,10 +579,10 @@ void device_image_interface::battery_load(void *buffer, int length, void *def_bu
//-------------------------------------------------
-// battery_save - stores the battery
-// backed RAM for an image. The file name is
-// created from the machine driver name and the
-// image name.
+// battery_save - stores the battery
+// backed RAM for an image. The file name is
+// created from the machine driver name and the
+// image name.
//-------------------------------------------------
void device_image_interface::battery_save(const void *buffer, int length)
@@ -631,8 +631,8 @@ bool device_image_interface::uses_file_extension(const char *file_extension) con
// ***************************************************************************
//-------------------------------------------------
-// is_loaded - quick check to determine whether an
-// image is loaded
+// is_loaded - quick check to determine whether an
+// image is loaded
//-------------------------------------------------
bool device_image_interface::is_loaded()
@@ -642,8 +642,8 @@ bool device_image_interface::is_loaded()
//-------------------------------------------------
-// load_image_by_path - loads an image with a
-// specific path
+// load_image_by_path - loads an image with a
+// specific path
//-------------------------------------------------
image_error_t device_image_interface::load_image_by_path(UINT32 open_flags, const char *path)
@@ -750,8 +750,8 @@ int device_image_interface::reopen_for_write(const char *path)
//-------------------------------------------------
-// determine_open_plan - determines which open
-// flags to use, and in what order
+// determine_open_plan - determines which open
+// flags to use, and in what order
//-------------------------------------------------
void device_image_interface::determine_open_plan(int is_create, UINT32 *open_plan)
@@ -772,9 +772,9 @@ void device_image_interface::determine_open_plan(int is_create, UINT32 *open_pla
//-------------------------------------------------
-// dump_wrong_and_correct_checksums - dump an
-// error message containing the wrong and the
-// correct checksums for a given software item
+// dump_wrong_and_correct_checksums - dump an
+// error message containing the wrong and the
+// correct checksums for a given software item
//-------------------------------------------------
static void dump_wrong_and_correct_checksums(const util::hash_collection &hashes, const util::hash_collection &acthashes)
@@ -785,8 +785,8 @@ static void dump_wrong_and_correct_checksums(const util::hash_collection &hashes
//-------------------------------------------------
-// verify_length_and_hash - verify the length
-// and hash signatures of a file
+// verify_length_and_hash - verify the length
+// and hash signatures of a file
//-------------------------------------------------
static int verify_length_and_hash(emu_file *file, const char *name, UINT32 explength, const util::hash_collection &hashes)
@@ -826,7 +826,7 @@ static int verify_length_and_hash(emu_file *file, const char *name, UINT32 exple
//-------------------------------------------------
-// load_software - software image loading
+// load_software - software image loading
//-------------------------------------------------
bool device_image_interface::load_software(software_list_device &swlist, const char *swname, const rom_entry *start)
@@ -931,7 +931,7 @@ bool device_image_interface::load_software(software_list_device &swlist, const c
//-------------------------------------------------
-// load_internal - core image loading
+// load_internal - core image loading
//-------------------------------------------------
bool device_image_interface::load_internal(const char *path, bool is_create, int create_format, util::option_resolution *create_args, bool just_load)
@@ -1068,7 +1068,7 @@ done:
//-------------------------------------------------
-// load - load an image into MAME
+// load - load an image into MAME
//-------------------------------------------------
bool device_image_interface::load(const char *path)
@@ -1078,7 +1078,7 @@ bool device_image_interface::load(const char *path)
//-------------------------------------------------
-// open_image_file - opening plain image file
+// open_image_file - opening plain image file
//-------------------------------------------------
bool device_image_interface::open_image_file(emu_options &options)
@@ -1097,8 +1097,8 @@ bool device_image_interface::open_image_file(emu_options &options)
//-------------------------------------------------
-// image_finish_load - special call - only use
-// from core
+// image_finish_load - special call - only use
+// from core
//-------------------------------------------------
bool device_image_interface::finish_load()
@@ -1138,7 +1138,7 @@ bool device_image_interface::finish_load()
//-------------------------------------------------
-// create - create a image
+// create - create a image
//-------------------------------------------------
bool device_image_interface::create(const char *path, const image_device_format *create_format, util::option_resolution *create_args)
@@ -1158,8 +1158,8 @@ bool device_image_interface::create(const char *path, const image_device_format
//-------------------------------------------------
-// clear - clear all internal data pertaining
-// to an image
+// clear - clear all internal data pertaining
+// to an image
//-------------------------------------------------
void device_image_interface::clear()
@@ -1186,7 +1186,7 @@ void device_image_interface::clear()
//-------------------------------------------------
-// unload - main call to unload an image
+// unload - main call to unload an image
//-------------------------------------------------
void device_image_interface::unload()
@@ -1201,7 +1201,7 @@ void device_image_interface::unload()
//-------------------------------------------------
-// update_names - update brief and instance names
+// update_names - update brief and instance names
//-------------------------------------------------
void device_image_interface::update_names(const device_type device_type, const char *inst, const char *brief)
diff --git a/src/emu/diimage.h b/src/emu/diimage.h
index 34d6532eedc..51ad3f2da70 100644
--- a/src/emu/diimage.h
+++ b/src/emu/diimage.h
@@ -88,10 +88,10 @@ public:
const std::string &optspec() const { return m_optspec; }
private:
- std::string m_name;
- std::string m_description;
- std::vector<std::string> m_extensions;
- std::string m_optspec;
+ std::string m_name;
+ std::string m_description;
+ std::vector<std::string> m_extensions;
+ std::string m_optspec;
};
diff --git a/src/emu/softlist.h b/src/emu/softlist.h
index 72a8381f929..98e858d96d5 100644
--- a/src/emu/softlist.h
+++ b/src/emu/softlist.h
@@ -184,12 +184,12 @@ public:
private:
// internal state
- software_part * m_next;
- software_info & m_info;
- std::string m_name;
- std::string m_interface;
- std::list<feature_list_item> m_featurelist;
- std::vector<rom_entry> m_romdata;
+ software_part * m_next;
+ software_info & m_info;
+ std::string m_name;
+ std::string m_interface;
+ std::list<feature_list_item> m_featurelist;
+ std::vector<rom_entry> m_romdata;
};
@@ -300,7 +300,7 @@ protected:
emu_file m_file;
std::string m_description;
std::string m_errors;
- std::list<software_info> m_infolist;
+ std::list<software_info> m_infolist;
const_string_pool m_stringpool;
};
diff --git a/src/frontend/mame/ui/imgcntrl.h b/src/frontend/mame/ui/imgcntrl.h
index 510d167ac14..e93d09ccc2e 100644
--- a/src/frontend/mame/ui/imgcntrl.h
+++ b/src/frontend/mame/ui/imgcntrl.h
@@ -46,11 +46,11 @@ protected:
} m_submenu_result;
// instance variables - made protected so they can be shared with floppycntrl.cpp
- int m_state;
- device_image_interface & m_image;
- std::string m_current_directory;
- std::string m_current_file;
- bool m_create_ok;
+ int m_state;
+ device_image_interface & m_image;
+ std::string m_current_directory;
+ std::string m_current_file;
+ bool m_create_ok;
// methods
virtual void hook_load(std::string filename, bool softlist);
@@ -58,11 +58,11 @@ protected:
private:
// instance variables
- bool m_create_confirmed;
- const software_info * m_swi;
- const software_part * m_swp;
- class software_list_device * m_sld;
- std::string m_software_info_name;
+ bool m_create_confirmed;
+ const software_info * m_swi;
+ const software_part * m_swp;
+ class software_list_device * m_sld;
+ std::string m_software_info_name;
// methods
virtual void populate() override;
diff --git a/src/frontend/mame/ui/widgets.cpp b/src/frontend/mame/ui/widgets.cpp
index 7a82310879e..956e251dba6 100644
--- a/src/frontend/mame/ui/widgets.cpp
+++ b/src/frontend/mame/ui/widgets.cpp
@@ -2,9 +2,9 @@
// copyright-holders:Nicola Salmoria, Aaron Giles, Nathan Woods
/*********************************************************************
- ui/widgets.cpp
+ ui/widgets.cpp
- Internal MAME widgets for the user interface.
+ Internal MAME widgets for the user interface.
*********************************************************************/
@@ -15,7 +15,7 @@
namespace ui {
/***************************************************************************
- WIDGETS
+ WIDGETS
***************************************************************************/
//-------------------------------------------------
diff --git a/src/frontend/mame/ui/widgets.h b/src/frontend/mame/ui/widgets.h
index a18c3a80cc9..45f1725d7ec 100644
--- a/src/frontend/mame/ui/widgets.h
+++ b/src/frontend/mame/ui/widgets.h
@@ -2,9 +2,9 @@
// copyright-holders:Nicola Salmoria, Aaron Giles, Nathan Woods
/***************************************************************************
- ui/widgets.h
+ ui/widgets.h
- Internal MAME widgets for the user interface.
+ Internal MAME widgets for the user interface.
***************************************************************************/
diff --git a/src/lib/formats/acorn_dsk.cpp b/src/lib/formats/acorn_dsk.cpp
index 5321cc00ea9..e8e0289ead1 100644
--- a/src/lib/formats/acorn_dsk.cpp
+++ b/src/lib/formats/acorn_dsk.cpp
@@ -506,7 +506,7 @@ int acorn_dos_format::find_size(io_generic *io, UINT32 form_factor)
if (cat[0] == 0xfd) return i;
break;
}
-
+
}
}
LOG_FORMATS("dos: no match\n");
diff --git a/src/lib/util/aviio.cpp b/src/lib/util/aviio.cpp
index 93f5bac1a1c..08fa138a177 100644
--- a/src/lib/util/aviio.cpp
+++ b/src/lib/util/aviio.cpp
@@ -189,11 +189,11 @@
#define AVI_INDEX_2FIELD 0x01
- /**
- * @def AVI_INTEGRAL_MULTIPLE
- *
- * @brief Ensures the integral multiple of the video dimension, because most video players are not capable to playback a video stream with a lower multiple.
- */
+ /**
+ * @def AVI_INTEGRAL_MULTIPLE
+ *
+ * @brief Ensures the integral multiple of the video dimension, because most video players are not capable to playback a video stream with a lower multiple.
+ */
#define AVI_INTEGRAL_MULTIPLE 4
diff --git a/src/lib/util/corefile.cpp b/src/lib/util/corefile.cpp
index 7a34406cf02..8e52b942d2f 100644
--- a/src/lib/util/corefile.cpp
+++ b/src/lib/util/corefile.cpp
@@ -1302,7 +1302,7 @@ bool core_filename_ends_with(const std::string &filename, const std::string &ext
// first if the extension is bigger than the name, we definitely don't match
bool matches = namelen >= extlen;
-
+
// work backwards checking for a match
while (matches && extlen > 0 && namelen > 0)
{
diff --git a/src/lib/util/opresolv.cpp b/src/lib/util/opresolv.cpp
index 7abe600cd65..baf66580d26 100644
--- a/src/lib/util/opresolv.cpp
+++ b/src/lib/util/opresolv.cpp
@@ -19,13 +19,12 @@
namespace util {
-
/***************************************************************************
- option_resolution
+ option_resolution
***************************************************************************/
// -------------------------------------------------
-// entry::int_value
+// entry::int_value
// -------------------------------------------------
int option_resolution::entry::int_value() const
@@ -35,7 +34,7 @@ int option_resolution::entry::int_value() const
// -------------------------------------------------
-// entry::set_int_value
+// entry::set_int_value
// -------------------------------------------------
void option_resolution::entry::set_int_value(int i)
@@ -45,7 +44,7 @@ void option_resolution::entry::set_int_value(int i)
// -------------------------------------------------
-// resolve_single_param
+// resolve_single_param
// -------------------------------------------------
option_resolution::error option_resolution::resolve_single_param(const char *specification, option_resolution::entry *param_value,
@@ -181,7 +180,7 @@ option_resolution::error option_resolution::resolve_single_param(const char *spe
// -------------------------------------------------
-// lookup_in_specification
+// lookup_in_specification
// -------------------------------------------------
const char *option_resolution::lookup_in_specification(const char *specification, const option_guide *option)
@@ -193,7 +192,7 @@ const char *option_resolution::lookup_in_specification(const char *specification
// -------------------------------------------------
-// ctor
+// ctor
// -------------------------------------------------
option_resolution::option_resolution(const option_guide *guide, const char *specification)
@@ -204,14 +203,14 @@ option_resolution::option_resolution(const option_guide *guide, const char *spec
assert(guide);
- // first count the number of options specified in the guide
+ // first count the number of options specified in the guide
option_count = count_options(guide, specification);
// set up the entries list
m_specification = specification;
m_entries.resize(option_count);
- // initialize each of the entries
+ // initialize each of the entries
opt = 0;
guide_entry = guide;
while(guide_entry->option_type != OPTIONTYPE_END)
@@ -239,7 +238,7 @@ option_resolution::option_resolution(const option_guide *guide, const char *spec
// -------------------------------------------------
-// dtor
+// dtor
// -------------------------------------------------
option_resolution::~option_resolution()
@@ -248,7 +247,7 @@ option_resolution::~option_resolution()
// -------------------------------------------------
-// add_param
+// add_param
// -------------------------------------------------
option_resolution::error option_resolution::add_param(const char *param, const std::string &value)
@@ -325,7 +324,7 @@ option_resolution::error option_resolution::add_param(const char *param, const s
// -------------------------------------------------
-// finish
+// finish
// -------------------------------------------------
option_resolution::error option_resolution::finish()
@@ -364,7 +363,7 @@ option_resolution::error option_resolution::finish()
// -------------------------------------------------
-// lookup_entry
+// lookup_entry
// -------------------------------------------------
const option_resolution::entry *option_resolution::lookup_entry(int option_char) const
@@ -389,7 +388,7 @@ const option_resolution::entry *option_resolution::lookup_entry(int option_char)
// -------------------------------------------------
-// lookup_int
+// lookup_int
// -------------------------------------------------
int option_resolution::lookup_int(int option_char) const
@@ -400,7 +399,7 @@ int option_resolution::lookup_int(int option_char) const
// -------------------------------------------------
-// lookup_string
+// lookup_string
// -------------------------------------------------
const char *option_resolution::lookup_string(int option_char) const
@@ -411,7 +410,7 @@ const char *option_resolution::lookup_string(int option_char) const
// -------------------------------------------------
-// find_option
+// find_option
// -------------------------------------------------
const option_guide *option_resolution::find_option(int option_char) const
@@ -422,7 +421,7 @@ const option_guide *option_resolution::find_option(int option_char) const
// -------------------------------------------------
-// index_option
+// index_option
// -------------------------------------------------
const option_guide *option_resolution::index_option(int indx) const
@@ -434,7 +433,7 @@ const option_guide *option_resolution::index_option(int indx) const
// -------------------------------------------------
-// count_options
+// count_options
// -------------------------------------------------
size_t option_resolution::count_options(const option_guide *guide, const char *specification)
@@ -463,7 +462,7 @@ size_t option_resolution::count_options(const option_guide *guide, const char *s
// -------------------------------------------------
-// list_ranges
+// list_ranges
// -------------------------------------------------
option_resolution::error option_resolution::list_ranges(const char *specification, int option_char, range *range, size_t range_count)
@@ -485,7 +484,7 @@ option_resolution::error option_resolution::list_ranges(const char *specificatio
// -------------------------------------------------
-// get_default
+// get_default
// -------------------------------------------------
option_resolution::error option_resolution::get_default(const char *specification, int option_char, int *val)
@@ -509,7 +508,7 @@ option_resolution::error option_resolution::get_default(const char *specificatio
// -------------------------------------------------
-// list_ranges
+// list_ranges
// -------------------------------------------------
option_resolution::error option_resolution::is_valid_value(const char *specification, int option_char, int val)
@@ -532,7 +531,7 @@ option_resolution::error option_resolution::is_valid_value(const char *specifica
// -------------------------------------------------
-// contains
+// contains
// -------------------------------------------------
bool option_resolution::contains(const char *specification, int option_char)
@@ -542,24 +541,24 @@ bool option_resolution::contains(const char *specification, int option_char)
// -------------------------------------------------
-// error_string
+// error_string
// -------------------------------------------------
const char *option_resolution::error_string(option_resolution::error err)
{
switch (err)
{
- case error::SUCCESS: return "The operation completed successfully";
- case error::OUTOFMEMORY: return "Out of memory";
- case error::PARAMOUTOFRANGE: return "Parameter out of range";
- case error::PARAMNOTSPECIFIED: return "Parameter not specified";
- case error::PARAMNOTFOUND: return "Unknown parameter";
- case error::PARAMALREADYSPECIFIED: return "Parameter specified multiple times";
- case error::BADPARAM: return "Invalid parameter";
- case error::SYNTAX: return "Syntax error";
- case error::INTERNAL: return "Internal error";
+ case error::SUCCESS: return "The operation completed successfully";
+ case error::OUTOFMEMORY: return "Out of memory";
+ case error::PARAMOUTOFRANGE: return "Parameter out of range";
+ case error::PARAMNOTSPECIFIED: return "Parameter not specified";
+ case error::PARAMNOTFOUND: return "Unknown parameter";
+ case error::PARAMALREADYSPECIFIED: return "Parameter specified multiple times";
+ case error::BADPARAM: return "Invalid parameter";
+ case error::SYNTAX: return "Syntax error";
+ case error::INTERNAL: return "Internal error";
}
return nullptr;
}
-} // namespace util \ No newline at end of file
+} // namespace util
diff --git a/src/lib/util/opresolv.h b/src/lib/util/opresolv.h
index 5faf615b30b..097d6e303ac 100644
--- a/src/lib/util/opresolv.h
+++ b/src/lib/util/opresolv.h
@@ -86,7 +86,6 @@ struct option_guide
#define OPTION_ENUM_END
namespace util {
-
class option_resolution
{
public:
diff --git a/src/lib/util/unicode.cpp b/src/lib/util/unicode.cpp
index 0390576ae9a..0ddee038eee 100644
--- a/src/lib/util/unicode.cpp
+++ b/src/lib/util/unicode.cpp
@@ -100,7 +100,7 @@ int uchar_from_utf8(unicode_char *uchar, const char *utf8char, size_t count)
{
auxchar = utf8char[i];
- // all auxillary chars must be between 0x80-0xbf
+ // all auxillary chars must be between 0x80-0xbf
if ((auxchar & 0xc0) != 0x80)
return -1;
diff --git a/src/lib/util/zippath.cpp b/src/lib/util/zippath.cpp
index 1a13bfe7784..0494a96def5 100644
--- a/src/lib/util/zippath.cpp
+++ b/src/lib/util/zippath.cpp
@@ -98,7 +98,7 @@ int is_path_separator(char c)
}
// -------------------------------------------------
-// parse_parent_path - parses out the parent path
+// parse_parent_path - parses out the parent path
// -------------------------------------------------
/**
@@ -137,7 +137,7 @@ static void parse_parent_path(const char *path, int *beginpos, int *endpos)
// -------------------------------------------------
-// zippath_parent - retrieves the parent directory
+// zippath_parent - retrieves the parent directory
// -------------------------------------------------
std::string &zippath_parent(std::string &dst, const char *path)
@@ -155,7 +155,7 @@ std::string &zippath_parent(std::string &dst, const char *path)
// -------------------------------------------------
-// zippath_parent - retrieves the parent directory
+// zippath_parent - retrieves the parent directory
// -------------------------------------------------
std::string zippath_parent(const char *path)
@@ -168,8 +168,8 @@ std::string zippath_parent(const char *path)
// -------------------------------------------------
-// zippath_parent_basename - retrieves the parent
-// directory basename
+// zippath_parent_basename - retrieves the parent
+// directory basename
// -------------------------------------------------
/**
@@ -194,8 +194,8 @@ std::string &zippath_parent_basename(std::string &dst, const char *path)
// -------------------------------------------------
-// zippath_parent_basename - retrieves the parent
-// directory basename
+// zippath_parent_basename - retrieves the parent
+// directory basename
// -------------------------------------------------
std::string zippath_parent_basename(const char *path)
@@ -208,7 +208,7 @@ std::string zippath_parent_basename(const char *path)
// -------------------------------------------------
-// zippath_combine - combines two paths
+// zippath_combine - combines two paths
// -------------------------------------------------
/**
@@ -251,7 +251,7 @@ std::string &zippath_combine(std::string &dst, const char *path1, const char *pa
// -------------------------------------------------
-// zippath_combine - combines two paths
+// zippath_combine - combines two paths
// -------------------------------------------------
std::string zippath_combine(const char *path1, const char *path2)
@@ -268,8 +268,8 @@ std::string zippath_combine(const char *path1, const char *path2)
***************************************************************************/
// -------------------------------------------------
-// file_error_from_zip_error - translates a
-// osd_file::error to a zip_error
+// file_error_from_zip_error - translates a
+// osd_file::error to a zip_error
// -------------------------------------------------
/**
@@ -311,8 +311,8 @@ static osd_file::error file_error_from_zip_error(archive_file::error ziperr)
// -------------------------------------------------
-// create_core_file_from_zip - creates a core_file
-// from a zip file entry
+// create_core_file_from_zip - creates a core_file
+// from a zip file entry
// -------------------------------------------------
/**
@@ -359,7 +359,7 @@ done:
// -------------------------------------------------
-// zippath_fopen - opens a zip path file
+// zippath_fopen - opens a zip path file
// -------------------------------------------------
/**
@@ -490,7 +490,7 @@ done:
***************************************************************************/
// -------------------------------------------------
-// is_root - tests to see if this path is the root
+// is_root - tests to see if this path is the root
// -------------------------------------------------
/**
@@ -521,8 +521,8 @@ static int is_root(const char *path)
// -------------------------------------------------
-// is_7z_file - tests to see if this file is a
-// 7-zip file
+// is_7z_file - tests to see if this file is a
+// 7-zip file
// -------------------------------------------------
/**
@@ -543,8 +543,8 @@ static bool is_7z_file(std::string const &path)
// -------------------------------------------------
-// is_zip_file - tests to see if this file is a
-// ZIP file
+// is_zip_file - tests to see if this file is a
+// ZIP file
// -------------------------------------------------
static bool is_zip_file(std::string const &path)
@@ -556,8 +556,8 @@ static bool is_zip_file(std::string const &path)
// -------------------------------------------------
-// is_zip_file_separator - returns whether this
-// character is a path separator within a ZIP file
+// is_zip_file_separator - returns whether this
+// character is a path separator within a ZIP file
// -------------------------------------------------
/**
@@ -578,8 +578,8 @@ static bool is_zip_file_separator(char c)
// -------------------------------------------------
-// is_zip_path_separator - returns whether this
-// character is a path separator within a ZIP path
+// is_zip_path_separator - returns whether this
+// character is a path separator within a ZIP path
// -------------------------------------------------
/**
@@ -600,8 +600,8 @@ static bool is_zip_path_separator(char c)
// -------------------------------------------------
-// next_path_char - lexes out the next path
-// character, normalizing separators as '/'
+// next_path_char - lexes out the next path
+// character, normalizing separators as '/'
// -------------------------------------------------
/**
@@ -650,8 +650,8 @@ static char next_path_char(std::string const &s, std::string::size_type &pos)
// -------------------------------------------------
-// zippath_find_sub_path - attempts to identify the
-// type of a sub path in a zip file
+// zippath_find_sub_path - attempts to identify the
+// type of a sub path in a zip file
// -------------------------------------------------
/**
@@ -701,8 +701,8 @@ static int zippath_find_sub_path(archive_file &zipfile, std::string const &subpa
// -------------------------------------------------
-// zippath_resolve - separates a ZIP path out into
-// true path and ZIP entry components
+// zippath_resolve - separates a ZIP path out into
+// true path and ZIP entry components
// -------------------------------------------------
/**
@@ -793,7 +793,7 @@ static osd_file::error zippath_resolve(const char *path, osd::directory::entry::
// -------------------------------------------------
-// zippath_opendir - opens a directory
+// zippath_opendir - opens a directory
// -------------------------------------------------
/**
@@ -864,7 +864,7 @@ done:
// -------------------------------------------------
-// zippath_closedir - closes a directory
+// zippath_closedir - closes a directory
// -------------------------------------------------
/**
@@ -890,9 +890,9 @@ void zippath_closedir(zippath_directory *directory)
// -------------------------------------------------
-// get_relative_path - checks to see if a specified
-// header is in the zippath_directory, and if so
-// returns the relative path
+// get_relative_path - checks to see if a specified
+// header is in the zippath_directory, and if so
+// returns the relative path
// -------------------------------------------------
/**
@@ -935,7 +935,7 @@ static const char *get_relative_path(zippath_directory const &directory)
// -------------------------------------------------
-// zippath_readdir - reads a directory
+// zippath_readdir - reads a directory
// -------------------------------------------------
/**
@@ -1048,8 +1048,8 @@ const osd::directory::entry *zippath_readdir(zippath_directory *directory)
// -------------------------------------------------
-// zippath_is_zip - returns TRUE if this path is
-// a ZIP path or FALSE if not
+// zippath_is_zip - returns TRUE if this path is
+// a ZIP path or FALSE if not
// -------------------------------------------------
/**
diff --git a/src/mame/drivers/bfm_sc4.cpp b/src/mame/drivers/bfm_sc4.cpp
index 309c3f905d6..df5852c9410 100644
--- a/src/mame/drivers/bfm_sc4.cpp
+++ b/src/mame/drivers/bfm_sc4.cpp
@@ -326,7 +326,7 @@ WRITE8_MEMBER(bfm_sc45_state::mux_output2_w)
UINT16 short_data;
UINT8 byte_data_first_segment;
UINT8 byte_data_second_segment;
- for (int digit = 0; digit < 32; digit += 2)
+ for (int digit = 0; digit < 32; digit += 2)
{
short_data = (m_segment_34_cache[digit + 1] << 8) | m_segment_34_cache[digit];
byte_data_first_segment = (short_data >> 1) & 15;
diff --git a/src/mame/drivers/chihiro.cpp b/src/mame/drivers/chihiro.cpp
index 054aa568a76..002a2a07568 100644
--- a/src/mame/drivers/chihiro.cpp
+++ b/src/mame/drivers/chihiro.cpp
@@ -720,7 +720,7 @@ static const struct {
} hacks[3] = { { "chihiro", false, { { 0x6a79f/*3f79f*/, 0x01 }, { 0x6a7a0/*3f7a0*/, 0x00 }, { 0x6b575/*40575*/, 0x00 }, { 0x6b576/*40576*/, 0x00 }, { 0x6b5af/*405af*/, 0x75 }, { 0x6b78a/*4078a*/, 0x75 }, { 0x6b7ca/*407ca*/, 0x00 }, { 0x6b7b8/*407b8*/, 0x00 }, { 0x8f5b2, 0x75 }, { 0x79a9e/*2ea9e*/, 0x74 }, { 0x79b80/*2eb80*/, 0xeb }, { 0x79b97/*2eb97*/, 0x74 }, { 0, 0 } } },
{ "outr2", true, { { 0x12e4cf, 0x01 }, { 0x12e4d0, 0x00 }, { 0x4793e, 0x01 }, { 0x4793f, 0x00 }, { 0x47aa3, 0x01 }, { 0x47aa4, 0x00 }, { 0x14f2b6, 0x84 }, { 0x14f2d1, 0x75 }, { 0x8732f, 0x7d }, { 0x87384, 0x7d }, { 0x87388, 0xeb }, { 0, 0 } } },
{ "crtaxihr", false, { { 0x14ada5/*11fda5*/, 0x90 },{ 0x14ada6/*11fda6*/, 0x90 }, { 0, 0 } } },
- };
+ };
void chihiro_state::hack_usb()
{
@@ -899,7 +899,7 @@ int ohci_hlean2131qc_device::handle_nonstandard_request(int endpoint, USBSetupPa
// setup->wIndex = number of bytes to write
// data will be transferred from the host using endpoint 2 (OUT)
endpoints[endpoint].buffer[0] = 0;
- }
+ }
else if (setup->bRequest == 0x1f)
{
// this command is used to write data to external memory (with respect to the internal 8051 cpu)
@@ -907,7 +907,7 @@ int ohci_hlean2131qc_device::handle_nonstandard_request(int endpoint, USBSetupPa
// setup->wIndex = number of bytes to write
// data will be transferred from the host using endpoint 3 (OUT)
endpoints[endpoint].buffer[0] = 0;
- }
+ }
else if (setup->bRequest == 0x20)
{
// this command is used to send a set of jvs packets, each to a different node
@@ -942,7 +942,7 @@ int ohci_hlean2131qc_device::handle_nonstandard_request(int endpoint, USBSetupPa
}
else if (setup->bRequest == 0x30)
{
- // this command first disables external interrupt 0 if the lower 8 bits of setup->wValue are 0
+ // this command first disables external interrupt 0 if the lower 8 bits of setup->wValue are 0
// or enables it if those bits, seen as a signed 8 bit value, represent a number greater than 0
// then it will return in byte 4 of the data stage the value 0 if external interrupt 0 has been disabled or value 1 if it has been enabled
// and in byte 5 the value of an 8 bit counter that is incremented at every external interrupt 0
diff --git a/src/mame/drivers/ddenlovr.cpp b/src/mame/drivers/ddenlovr.cpp
index adc86a9e39a..ec87b4ac442 100644
--- a/src/mame/drivers/ddenlovr.cpp
+++ b/src/mame/drivers/ddenlovr.cpp
@@ -8198,12 +8198,12 @@ static INPUT_PORTS_START( mjflove )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
PORT_START("DSW2") /* IN12 - DSW2 */
- PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
+ PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
- PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:3,4,5")
+ PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:3,4,5")
PORT_DIPSETTING( 0x18, "1" )
PORT_DIPSETTING( 0x14, "2" )
PORT_DIPSETTING( 0x10, "3" )
@@ -8212,17 +8212,17 @@ static INPUT_PORTS_START( mjflove )
PORT_DIPSETTING( 0x08, "6" )
PORT_DIPSETTING( 0x04, "7" )
PORT_DIPSETTING( 0x00, "8" )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_SERVICE( 0x80, IP_ACTIVE_LOW ) PORT_DIPLOCATION("SW1:8")
+ PORT_SERVICE( 0x80, IP_ACTIVE_LOW ) PORT_DIPLOCATION("SW1:8")
/*
- PORT_DIPNAME( 0x80, 0x80, DEF_STR( Test ) ) PORT_DIPLOCATION("SW1:8")
- PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x00, DEF_STR( On ) )*/
+ PORT_DIPNAME( 0x80, 0x80, DEF_STR( Test ) ) PORT_DIPLOCATION("SW1:8")
+ PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x00, DEF_STR( On ) )*/
PORT_START("DSW1") /* IN11 - DSW1 */
PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW2:1" )
diff --git a/src/mame/drivers/dynax.cpp b/src/mame/drivers/dynax.cpp
index 02036eb868a..f183ebdd0cd 100644
--- a/src/mame/drivers/dynax.cpp
+++ b/src/mame/drivers/dynax.cpp
@@ -2612,33 +2612,33 @@ INPUT_PORTS_END
static INPUT_PORTS_START( mjdialq2 )
PORT_START("DSW0")
- PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
+ PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x04, 0x00, "PINFU with TSUMO" ) PORT_DIPLOCATION("SW1:3")
+ PORT_DIPNAME( 0x04, 0x00, "PINFU with TSUMO" ) PORT_DIPLOCATION("SW1:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x38, 0x20, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:4,5,6")
- PORT_DIPSETTING( 0x38, "1 (Easy)" )
- PORT_DIPSETTING( 0x30, "2" )
- PORT_DIPSETTING( 0x28, "3" )
- PORT_DIPSETTING( 0x20, "4" )
- PORT_DIPSETTING( 0x18, "5" )
- PORT_DIPSETTING( 0x10, "6" )
- PORT_DIPSETTING( 0x08, "7" )
- PORT_DIPSETTING( 0x00, "8 (Hard)" )
-
- PORT_DIPNAME( 0x40, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:7")
+ PORT_DIPNAME( 0x38, 0x20, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:4,5,6")
+ PORT_DIPSETTING( 0x38, "1 (Easy)" )
+ PORT_DIPSETTING( 0x30, "2" )
+ PORT_DIPSETTING( 0x28, "3" )
+ PORT_DIPSETTING( 0x20, "4" )
+ PORT_DIPSETTING( 0x18, "5" )
+ PORT_DIPSETTING( 0x10, "6" )
+ PORT_DIPSETTING( 0x08, "7" )
+ PORT_DIPSETTING( 0x00, "8 (Hard)" )
+
+ PORT_DIPNAME( 0x40, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
+ PORT_DIPNAME( 0x80, 0x80, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW1")
- PORT_DIPNAME( 0x07, 0x07, "Time Setting" ) PORT_DIPLOCATION("SW2:1,2,3")
+ PORT_DIPNAME( 0x07, 0x07, "Time Setting" ) PORT_DIPLOCATION("SW2:1,2,3")
PORT_DIPSETTING( 0x07, "08:30" )
PORT_DIPSETTING( 0x06, "09:00" )
PORT_DIPSETTING( 0x05, "09:30" )
@@ -2647,19 +2647,19 @@ static INPUT_PORTS_START( mjdialq2 )
PORT_DIPSETTING( 0x02, "11:00" )
PORT_DIPSETTING( 0x01, "11:30" )
PORT_DIPSETTING( 0x00, "12:00" )
- PORT_DIPNAME( 0x08, 0x00, "Time Service" ) PORT_DIPLOCATION("SW2:4") // "secret moves" happen at certain time stamps
+ PORT_DIPNAME( 0x08, 0x00, "Time Service" ) PORT_DIPLOCATION("SW2:4") // "secret moves" happen at certain time stamps
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, "TEL Display" ) PORT_DIPLOCATION("SW2:5")
+ PORT_DIPNAME( 0x10, 0x10, "TEL Display" ) PORT_DIPLOCATION("SW2:5")
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
- PORT_DIPNAME( 0x20, 0x20, "GAL mode" ) PORT_DIPLOCATION("SW2:6") // unknown what this does
+ PORT_DIPNAME( 0x20, 0x20, "GAL mode" ) PORT_DIPLOCATION("SW2:6") // unknown what this does
PORT_DIPSETTING( 0x20, "1" )
PORT_DIPSETTING( 0x00, "2" )
- PORT_DIPNAME( 0x40, 0x40, "Select Special Item" ) PORT_DIPLOCATION("SW2:7")/* Allows to select which one of the nine special items you want. */
+ PORT_DIPNAME( 0x40, 0x40, "Select Special Item" ) PORT_DIPLOCATION("SW2:7")/* Allows to select which one of the nine special items you want. */
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, "Debug" ) PORT_DIPLOCATION("SW2:8")
+ PORT_DIPNAME( 0x80, 0x80, "Debug" ) PORT_DIPLOCATION("SW2:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@@ -6381,24 +6381,24 @@ ROM_END
/*
Intergirl by Barko
-1x GM68A45S uj11 CRT Controller (CRTC)
-1x Z8400ADSD-Z80ACPU ug8 8-bit Microprocessor - main
-1x GL324 u14 Quad Operational Amplifier - sound
-1x YM2203C uj5 FM Operator Type-N (OPM) - sound
-1x YM3014B u13 D/A Converter (DAC) - sound
-1x oscillator 22.1184MHz xt1
+1x GM68A45S uj11 CRT Controller (CRTC)
+1x Z8400ADSD-Z80ACPU ug8 8-bit Microprocessor - main
+1x GL324 u14 Quad Operational Amplifier - sound
+1x YM2203C uj5 FM Operator Type-N (OPM) - sound
+1x YM3014B u13 D/A Converter (DAC) - sound
+1x oscillator 22.1184MHz xt1
ROMs
-2x TMS27C512 1,2 dumped
-3x TMS27C020 3,4,5 dumped
+2x TMS27C512 1,2 dumped
+3x TMS27C020 3,4,5 dumped
RAMs
-1x GM76C88AL-15 ug1
-6x KM424C64P-10 uf13,uf13a,uf14,uf15,uf16,uf17
+1x GM76C88AL-15 ug1
+6x KM424C64P-10 uf13,uf13a,uf14,uf15,uf16,uf17
PLDs
-1x PAL16L8ACN ug6 read protected
-1x CY7C381-0JC read protected
+1x PAL16L8ACN ug6 read protected
+1x CY7C381-0JC read protected
*/
ROM_START( intrgirl )
@@ -6415,7 +6415,7 @@ ROM_START( intrgirl )
ROM_LOAD( "n82s147n.uk15", 0x000, 0x200, NO_DUMP )
ROM_LOAD( "n82s147n.uk16", 0x200, 0x200, NO_DUMP )
- ROM_REGION( 0x104, "pals", ROMREGION_ERASE00 )
+ ROM_REGION( 0x104, "pals", ROMREGION_ERASE00 )
ROM_LOAD( "pal16l8acn.ug6", 0x000, 0x104, NO_DUMP ) //read protected
ROM_END
diff --git a/src/mame/drivers/epos.cpp b/src/mame/drivers/epos.cpp
index 538799158f1..2afbd439cdd 100644
--- a/src/mame/drivers/epos.cpp
+++ b/src/mame/drivers/epos.cpp
@@ -27,10 +27,10 @@
between the two palettes. This effect is not emulated, but since both
halfs of the palette are identical, this is not an issue. See $039c.
The other games have a different color test, not using the busy loop.
-
- - Find out how Beastie Feastie's 2nd player inputs work.
-
- - Fix flip screen support for The Dealer and Beastie Feastie.
+
+ - Find out how Beastie Feastie's 2nd player inputs work.
+
+ - Fix flip screen support for The Dealer and Beastie Feastie.
***************************************************************************/
@@ -355,7 +355,7 @@ INPUT_PORTS_END
static INPUT_PORTS_START( beastf )
PORT_INCLUDE(dealer)
-
+
PORT_MODIFY("INPUTS")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
diff --git a/src/mame/drivers/esh.cpp b/src/mame/drivers/esh.cpp
index b3bcfd51cd9..588782f3394 100644
--- a/src/mame/drivers/esh.cpp
+++ b/src/mame/drivers/esh.cpp
@@ -150,8 +150,8 @@ WRITE8_MEMBER(esh_state::misc_write)
{
/* Bit 0 unknown */
-// if (data & 0x02)
-// logerror("BEEP!\n");
+// if (data & 0x02)
+// logerror("BEEP!\n");
m_beep->set_state(BIT(data, 1)); // polarity unknown
/* Bit 2 unknown */
m_ld_video_visible = bool(!((data & 0x08) >> 3));
diff --git a/src/mame/drivers/expro02.cpp b/src/mame/drivers/expro02.cpp
index b1bbf6448fc..cf39a1db0a7 100644
--- a/src/mame/drivers/expro02.cpp
+++ b/src/mame/drivers/expro02.cpp
@@ -228,7 +228,7 @@ public:
m_kaneko_spr(*this, "kan_spr"),
m_spriteram(*this, "spriteram")
{ }
-
+
required_device<cpu_device> m_maincpu;
required_device<palette_device> m_palette;
required_device<screen_device> m_screen;
diff --git a/src/mame/drivers/fccpu30.cpp b/src/mame/drivers/fccpu30.cpp
index cfef6508309..3687f4f81a0 100644
--- a/src/mame/drivers/fccpu30.cpp
+++ b/src/mame/drivers/fccpu30.cpp
@@ -352,11 +352,11 @@ READ8_MEMBER (fccpu30_state::rotary_rd){
*/
READ8_MEMBER (fccpu30_state::board_mem_id_rd){
LOG(("%s\n", FUNCNAME));
- // return 0x6A; // CPU-30 R4 with 4Mb of shared RAM. TODO: make this configurable from commandline or artwork
- // return 0x57; // blankt 53 56
- // return 0x36; // CPU-26 1Mb 36 MHz
- // return 0x35; // CPU-26 1Mb 36 MHz
- return 0x36; // CPU-26 1Mb 36 MHz
+ // return 0x6A; // CPU-30 R4 with 4Mb of shared RAM. TODO: make this configurable from commandline or artwork
+ // return 0x57; // blankt 53 56
+ // return 0x36; // CPU-26 1Mb 36 MHz
+ // return 0x35; // CPU-26 1Mb 36 MHz
+ return 0x36; // CPU-26 1Mb 36 MHz
}
#if 0
@@ -415,7 +415,7 @@ MACHINE_CONFIG_END
ROM_START (fccpu30)
ROM_REGION32_BE(0x900000, "roms", 0)
-// Boots with Board ID set to: 0x36
+// Boots with Board ID set to: 0x36
ROM_LOAD16_BYTE("CPU33LO.BIN", 0x000001, 0x40000, CRC (49895fdf) SHA1 (733abd144c95225a2faf920490e31df2a27f8e03))
ROM_LOAD16_BYTE("CPU33UP.BIN", 0x000000, 0x40000, CRC (cfe75e94) SHA1 (d40e0635a48607be25f7c58c74b53b7e58fe735d))
@@ -425,9 +425,9 @@ ROM_START (fccpu30)
ROM_LOAD32_BYTE("CPU30LO.BIN", 0x000002, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9))
ROM_LOAD32_BYTE("CPU30UP.BIN", 0x000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8))
ROM_LOAD32_BYTE("CPU30UU.BIN", 0x000000, 0x20000, CRC (66e95cc2) SHA1 (acdb468a3a5974295b81271d617de7f101098891))
-#endif
+#endif
-// Same binary for many boards, attempts to detect CPU speed etc, currently failing detection but boots system roms anyway
+// Same binary for many boards, attempts to detect CPU speed etc, currently failing detection but boots system roms anyway
ROM_LOAD ("PGA-002.bin", 0x800000, 0x10000, CRC(faa38972) SHA1(651dfc2f9a865fc6adf49dad90f9e705f2889919) )
ROM_END
diff --git a/src/mame/drivers/fcisio.cpp b/src/mame/drivers/fcisio.cpp
index 4e33d41c8a8..6b068f4c9e7 100644
--- a/src/mame/drivers/fcisio.cpp
+++ b/src/mame/drivers/fcisio.cpp
@@ -118,7 +118,7 @@ static ADDRESS_MAP_START (fcisio1_mem, AS_PROGRAM, 16, fcisio1_state)
AM_RANGE (0xe60000, 0xe601ff) AM_DEVREADWRITE8("duscc3", duscc68562_device, read, write, 0x00ff)
AM_RANGE (0xe80000, 0xe80dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0x00ff)
AM_RANGE (0xf00000, 0xf7ffff) AM_ROM /* System EPROM Area 32Kb DEBUGGER supplied */
-// AM_RANGE (0xc40000, 0xc800ff) AM_READWRITE8 (not_implemented_r, not_implemented_w, 0xffff) /* Dummy mapping af address area to display message */
+// AM_RANGE (0xc40000, 0xc800ff) AM_READWRITE8 (not_implemented_r, not_implemented_w, 0xffff) /* Dummy mapping af address area to display message */
ADDRESS_MAP_END
/* Start it up */
@@ -155,14 +155,14 @@ WRITE8_MEMBER (fcisio1_state::not_implemented_w){
// TODO: Get a manual to understand the config options for real
READ8_MEMBER (fcisio1_state::config_rd){
- UINT8 ret = 0;
+ UINT8 ret = 0;
LOG(("%s\n", FUNCNAME));
// Port B bit #7, 0x80 Self test bit, choose either of these two lines
ret &= ~0x80; // 0 = selftest
- // ret |= 0x80; // 1 = no selftest
+ // ret |= 0x80; // 1 = no selftest
- return ret;
+ return ret;
}
/* Input ports */
@@ -211,7 +211,7 @@ ROM_START (fcisio1)
/* ISIO ROM:s v2.1 information
* PIT setup sequence
* 00 -> REG_PGCR
- * 18 -> REG_PSRR
+ * 18 -> REG_PSRR
* 0f -> Reg PADDR
* 0f -> REG_PBDDR
* fa -> REG_PACR
@@ -225,7 +225,7 @@ ROM_START (fcisio1)
* 40 -> Reg PIVR
* 00 -> REG_TCR - timer disabled, all C pins, use preload, CLK and prescaler are used
* a0 -> REG_TCR - timer disabled, The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- * output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
+ * output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
* pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge input.
* 00 -> Reg 0x12
* 00 -> REG_CPRH
@@ -263,39 +263,39 @@ ROM_START (fcisio1)
* 00 -> REG_PCDR
* ------- repeated 16 times -------------------
* a1 -> REG_TCR - timer enabled, The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- * output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
+ * output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
* pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge input.
* ?? <- Reg 0x0c
* ---------------------------------------------
*
* DUSCC0 channel A setup sequence
- * 0f 00 -> REG_CCR - Reset Tx
- * 0f 40 -> REG_CCR - Reset Rx
- * 00 07 -> REG_CMR1 - Async mode
- * 01 38 -> REG_CMR2 - Normal polled or interrupt mode, no DMA
- * 02 00 -> REG_S1R - SYN1, Secondary Address 1 Register, 0 = no sync
- * 03 00 -> REG_S2R - SYN2, only used in COP dual Sync mode but alao 0 = no sync
+ * 0f 00 -> REG_CCR - Reset Tx
+ * 0f 40 -> REG_CCR - Reset Rx
+ * 00 07 -> REG_CMR1 - Async mode
+ * 01 38 -> REG_CMR2 - Normal polled or interrupt mode, no DMA
+ * 02 00 -> REG_S1R - SYN1, Secondary Address 1 Register, 0 = no sync
+ * 03 00 -> REG_S2R - SYN2, only used in COP dual Sync mode but alao 0 = no sync
* 04 7F -> REG_TPR - Tx 8 bits, CTS and RTS, 1 STOP bit
* 05 3d -> REG_TTR - Tx BRG 9600 (assuming a 14.7456 crystal)
* 06 1b -> REG_RPR - Rx RTS, 8 bits, no DCD, no parity
* 07 2d -> REG_RTR - Rx BRG 9600 (assuming a 14.7456 crystal)
- * 0b e1 -> REG_OMR - RTS high, OUT1 = OUT2 = high, RxRdy asserted for each character,
- * TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
- * 0a 00 -> REG_CTCR - Counter/Timer control register 00 = Zero Det Int: disabled, Zero Det Control: preset,
- * Output Control: square, Prescaler: 1, Clock Source: RTxC pin
- * 09 00 -> REG_CTPRL - Counter/Timer Prescaler Register Low = 0
- * 08 00 -> REG_CTPRH - Counter/Timer Prescaler Register High = 0
- * 0f 00 -> REG_CCR - Reset Tx
- * 0f 02 -> REG_CCR - Enable Tx
- * 0f 40 -> REG_CCR - Reset Rx
- * 0f 42 -> REG_CCR - Enable Rx
- * 0f 02 -> REG_CCR - Enable Tx
- * 0f 42 -> REG_CCR - Enable Rx
+ * 0b e1 -> REG_OMR - RTS high, OUT1 = OUT2 = high, RxRdy asserted for each character,
+ * TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
+ * 0a 00 -> REG_CTCR - Counter/Timer control register 00 = Zero Det Int: disabled, Zero Det Control: preset,
+ * Output Control: square, Prescaler: 1, Clock Source: RTxC pin
+ * 09 00 -> REG_CTPRL - Counter/Timer Prescaler Register Low = 0
+ * 08 00 -> REG_CTPRH - Counter/Timer Prescaler Register High = 0
+ * 0f 00 -> REG_CCR - Reset Tx
+ * 0f 02 -> REG_CCR - Enable Tx
+ * 0f 40 -> REG_CCR - Reset Rx
+ * 0f 42 -> REG_CCR - Enable Rx
+ * 0f 02 -> REG_CCR - Enable Tx
+ * 0f 42 -> REG_CCR - Enable Rx
* 0e 27 -> REG_PCR - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
- * 1c 10 -> REG_IER - Interrupt Enable Register: RxRdy generates interrupt
+ * 1c 10 -> REG_IER - Interrupt Enable Register: RxRdy generates interrupt
* ... chan B setup with same data....
* ---- DUSCC0 to DUSCC3, setup with same data except at the end of each setup:
- * 1e 1c -> DUSCC0 REG_IVR -
+ * 1e 1c -> DUSCC0 REG_IVR -
* 1e 1b -> DUSCC1 REG_IVR
* 1e 1a -> DUSCC2 REG_IVR
* 1e 19 -> DUSCC3 REG_IVR
diff --git a/src/mame/drivers/fromance.cpp b/src/mame/drivers/fromance.cpp
index c9729606561..33a5cb017ce 100644
--- a/src/mame/drivers/fromance.cpp
+++ b/src/mame/drivers/fromance.cpp
@@ -722,49 +722,49 @@ static INPUT_PORTS_START( daiyogen )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("DSW1")
- PORT_DIPNAME( 0x01, 0x00, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("SW1:!1")
+ PORT_DIPNAME( 0x01, 0x00, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("SW1:!1")
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
- PORT_DIPNAME( 0x06, 0x00, "Player Initial Score" ) PORT_DIPLOCATION("SW1:!2,!3")
+ PORT_DIPNAME( 0x06, 0x00, "Player Initial Score" ) PORT_DIPLOCATION("SW1:!2,!3")
PORT_DIPSETTING( 0x00, "1,000" )
- PORT_DIPSETTING( 0x04, "1,500" )
+ PORT_DIPSETTING( 0x04, "1,500" )
PORT_DIPSETTING( 0x02, "2,000" )
PORT_DIPSETTING( 0x06, "3,000" )
- PORT_DIPNAME( 0x18, 0x00, "Computer Difficulty" ) PORT_DIPLOCATION("SW1:!4,!5")
+ PORT_DIPNAME( 0x18, 0x00, "Computer Difficulty" ) PORT_DIPLOCATION("SW1:!4,!5")
PORT_DIPSETTING( 0x10, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x00, DEF_STR( Normal ) )
PORT_DIPSETTING( 0x08, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x18, DEF_STR( Very_Hard ) )
- PORT_DIPNAME( 0x20, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:!6")
+ PORT_DIPNAME( 0x20, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:!6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW1:!7" )
- PORT_DIPNAME( 0x80, 0x00, "YAKUMAN STOP" ) PORT_DIPLOCATION("SW1:!8") // not sure what this is supposed to mean
+ PORT_DIPNAME( 0x80, 0x00, "YAKUMAN STOP" ) PORT_DIPLOCATION("SW1:!8") // not sure what this is supposed to mean
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
PORT_START("DSW2")
- PORT_DIPNAME( 0x07, 0x00, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:!1,!2,!3")
+ PORT_DIPNAME( 0x07, 0x00, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:!1,!2,!3")
PORT_DIPSETTING( 0x00, "1" )
- PORT_DIPSETTING( 0x04, "2" )
+ PORT_DIPSETTING( 0x04, "2" )
PORT_DIPSETTING( 0x02, "3" )
- PORT_DIPSETTING( 0x06, "4" )
- PORT_DIPSETTING( 0x01, "5" )
+ PORT_DIPSETTING( 0x06, "4" )
+ PORT_DIPSETTING( 0x01, "5" )
PORT_DIPSETTING( 0x05, "6" )
- PORT_DIPSETTING( 0x03, "7" )
+ PORT_DIPSETTING( 0x03, "7" )
PORT_DIPSETTING( 0x07, "8" )
- PORT_DIPNAME( 0x18, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW2:!4,!5")
+ PORT_DIPNAME( 0x18, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW2:!4,!5")
PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x18, DEF_STR( 3C_1C ) )
- PORT_DIPNAME( 0x20, 0x00, "Ignore FURITEN" ) PORT_DIPLOCATION("SW2:!6")
+ PORT_DIPNAME( 0x20, 0x00, "Ignore FURITEN" ) PORT_DIPLOCATION("SW2:!6")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x00, "PINFU with TSUMO" ) PORT_DIPLOCATION("SW2:!7")
+ PORT_DIPNAME( 0x40, 0x00, "PINFU with TSUMO" ) PORT_DIPLOCATION("SW2:!7")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x40, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x00, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:!8")
+ PORT_DIPNAME( 0x80, 0x00, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:!8")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
@@ -793,50 +793,50 @@ static INPUT_PORTS_START( mjnatsu )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) // COIN1
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
- PORT_START("DSW2")
- PORT_DIPNAME( 0x07, 0x00, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:!1,!2,!3")
- PORT_DIPSETTING( 0x00, "1" )
- PORT_DIPSETTING( 0x04, "2" )
- PORT_DIPSETTING( 0x02, "3" )
- PORT_DIPSETTING( 0x06, "4" )
- PORT_DIPSETTING( 0x01, "5" )
- PORT_DIPSETTING( 0x05, "6" )
- PORT_DIPSETTING( 0x03, "7" )
- PORT_DIPSETTING( 0x07, "8" )
- PORT_DIPNAME( 0x18, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:!4,!5")
- PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
- PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
- PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
- PORT_DIPSETTING( 0x18, DEF_STR( 3C_1C ) )
- PORT_DIPNAME( 0x20, 0x00, "Ignore FURITEN" ) PORT_DIPLOCATION("SW1:!6")
- PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x20, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x00, "PINFU with TSUMO" ) PORT_DIPLOCATION("SW1:!7")
- PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x40, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x00, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:!8")
- PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x80, DEF_STR( On ) )
-
- PORT_START("DSW1")
- PORT_DIPNAME( 0x01, 0x00, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("SW2:!1")
- PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
- PORT_DIPNAME( 0x06, 0x00, "Player Initial Score" ) PORT_DIPLOCATION("SW2:!2,!3")
- PORT_DIPSETTING( 0x00, "1,000" )
- PORT_DIPSETTING( 0x04, "2,000" )
- PORT_DIPSETTING( 0x02, "3,000" )
- PORT_DIPSETTING( 0x06, "5,000" )
- PORT_DIPNAME( 0x08, 0x00, "Start GOLD" ) PORT_DIPLOCATION("SW2:!4")
- PORT_DIPSETTING( 0x00, "1,000" )
- PORT_DIPSETTING( 0x08, "6,000" )
- PORT_DIPNAME( 0x10, 0x00, "Item Shop Voice" ) PORT_DIPLOCATION("SW2:!5")
- PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x00, "Stop Button (N)" ) PORT_DIPLOCATION("SW2:!6")
- PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPUNUSED_DIPLOC( 0x40, 0x00, "SW2:!7" )
+ PORT_START("DSW2")
+ PORT_DIPNAME( 0x07, 0x00, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:!1,!2,!3")
+ PORT_DIPSETTING( 0x00, "1" )
+ PORT_DIPSETTING( 0x04, "2" )
+ PORT_DIPSETTING( 0x02, "3" )
+ PORT_DIPSETTING( 0x06, "4" )
+ PORT_DIPSETTING( 0x01, "5" )
+ PORT_DIPSETTING( 0x05, "6" )
+ PORT_DIPSETTING( 0x03, "7" )
+ PORT_DIPSETTING( 0x07, "8" )
+ PORT_DIPNAME( 0x18, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:!4,!5")
+ PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
+ PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
+ PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
+ PORT_DIPSETTING( 0x18, DEF_STR( 3C_1C ) )
+ PORT_DIPNAME( 0x20, 0x00, "Ignore FURITEN" ) PORT_DIPLOCATION("SW1:!6")
+ PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x20, DEF_STR( On ) )
+ PORT_DIPNAME( 0x40, 0x00, "PINFU with TSUMO" ) PORT_DIPLOCATION("SW1:!7")
+ PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x40, DEF_STR( On ) )
+ PORT_DIPNAME( 0x80, 0x00, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:!8")
+ PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x80, DEF_STR( On ) )
+
+ PORT_START("DSW1")
+ PORT_DIPNAME( 0x01, 0x00, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("SW2:!1")
+ PORT_DIPSETTING( 0x00, DEF_STR( On ) )
+ PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
+ PORT_DIPNAME( 0x06, 0x00, "Player Initial Score" ) PORT_DIPLOCATION("SW2:!2,!3")
+ PORT_DIPSETTING( 0x00, "1,000" )
+ PORT_DIPSETTING( 0x04, "2,000" )
+ PORT_DIPSETTING( 0x02, "3,000" )
+ PORT_DIPSETTING( 0x06, "5,000" )
+ PORT_DIPNAME( 0x08, 0x00, "Start GOLD" ) PORT_DIPLOCATION("SW2:!4")
+ PORT_DIPSETTING( 0x00, "1,000" )
+ PORT_DIPSETTING( 0x08, "6,000" )
+ PORT_DIPNAME( 0x10, 0x00, "Item Shop Voice" ) PORT_DIPLOCATION("SW2:!5")
+ PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x00, DEF_STR( On ) )
+ PORT_DIPNAME( 0x20, 0x00, "Stop Button (N)" ) PORT_DIPLOCATION("SW2:!6")
+ PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x00, DEF_STR( On ) )
+ PORT_DIPUNUSED_DIPLOC( 0x40, 0x00, "SW2:!7" )
PORT_DIPUNUSED_DIPLOC( 0x80, 0x00, "SW2:!8" )
PORT_INCLUDE( mahjong_panel )
diff --git a/src/mame/drivers/galaxian.cpp b/src/mame/drivers/galaxian.cpp
index dc6807fc286..816b2206e66 100644
--- a/src/mame/drivers/galaxian.cpp
+++ b/src/mame/drivers/galaxian.cpp
@@ -5862,11 +5862,11 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( turpins, turtles )
// the ROMs came from a blister, so there aren't PCB infos available. Chip types and clocks are guessed.
-
+
/* alternate memory map */
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(turpins_map)
-
+
MCFG_CPU_MODIFY("audiocpu")
MCFG_CPU_PROGRAM_MAP(turpins_sound_map)
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/goldstar.cpp b/src/mame/drivers/goldstar.cpp
index b3d2011f7c8..01636756c80 100644
--- a/src/mame/drivers/goldstar.cpp
+++ b/src/mame/drivers/goldstar.cpp
@@ -14680,7 +14680,7 @@ ROM_END
The taiwanese hardware needs better decoded reels graphics ROMs,
The chars/text graphics are properly decodes, but texts strings
look bad in the game.
-
+
*******************************************************************************************/
/*
@@ -15567,8 +15567,8 @@ DRIVER_INIT_MEMBER(wingco_state, flaming7)
/* Patch to bypass the iButton electronic serial number check.
5D79: jumps to $5D83 for the demo game.
- just patched to jump to $5D80 (jmp $6115)
- where the check is succesfull.
+ just patched to jump to $5D80 (jmp $6115)
+ where the check is succesfull.
*/
UINT8 *ROM = memregion("maincpu")->base();
ROM[0x5d7a] = 0x05;
@@ -15586,8 +15586,8 @@ DRIVER_INIT_MEMBER(wingco_state, flam7_tw)
/* Patch to bypass the iButton electronic serial number check.
60B2: After last compare, code jumps to $60BC for the demo game.
- Just patched to jump to $60B9 (jmp $644E) where the check
- is succesfull.
+ Just patched to jump to $60B9 (jmp $644E) where the check
+ is succesfull.
*/
UINT8 *ROM = memregion("maincpu")->base();
ROM[0x60b3] = 0x05;
diff --git a/src/mame/drivers/hk68v10.cpp b/src/mame/drivers/hk68v10.cpp
index cab10d05ac0..0020375ea63 100644
--- a/src/mame/drivers/hk68v10.cpp
+++ b/src/mame/drivers/hk68v10.cpp
@@ -370,15 +370,15 @@ ROM_LOAD16_BYTE ("hk68kv10U12.bin", 0xFC0000, 0x2000, CRC (f2d688e9) SHA1 (e6869
* :scc B Reg 05 <- ea Setting up the transmitter, Transmitter Enable 1, Transmitter Bits/Character 8, Send Break 0, RTS=1, DTR=1
* :scc B Reg 03 <- e1 Setting up the receiver, Receiver Enable 1, Auto Enables 1, Receiver Bits/Character 8
* :scc B Reg 09 <- 00 Master Interrupt Control - No reset 02 A&B: RTS=1 DTR=1 INT=0 Vector generated
- * :scc B Reg 01 <- 00 Ext INT:0 Tx INT:0 Parity SC:0 Wait/Ready Enable:0 as Wait on Transmit, Rx INT:0
+ * :scc B Reg 01 <- 00 Ext INT:0 Tx INT:0 Parity SC:0 Wait/Ready Enable:0 as Wait on Transmit, Rx INT:0
* :scc B Reg 0b <- 56 Clock Mode Control 55 Clock type TTL level on RTxC pin, RCV CLK=BRG, TRA CLK=BRG, TRxC pin is Output, TRxC CLK=BRG - not_implemented
* :scc B Reg 0c <- 0b Low byte of Time Constant for Baudrate generator -> 38400 baud
* :scc B Reg 0d <- 00 High byte of Time Constant for Baudrate generator
* :scc B Reg 0e <- 03 Misc Control Bits DPLL NULL Command, BRG enabled SRC=PCLK, BRG SRC bps=307200=PCLK 4915200/16, BRG OUT 9600=307200/16(32)
- * Repeated for :scc A
+ * Repeated for :scc A
* :scc B Reg 0c <- 0e Low byte of Time Constant for Baudrate generator -> 9600 baud
* :scc B Reg 0d <- 00 High byte of Time Constant for Baudrate generator
- * Repeated for :scc A
+ * Repeated for :scc A
*/
ROM_END
diff --git a/src/mame/drivers/hnayayoi.cpp b/src/mame/drivers/hnayayoi.cpp
index ad8fc057afc..3afc8c0def9 100644
--- a/src/mame/drivers/hnayayoi.cpp
+++ b/src/mame/drivers/hnayayoi.cpp
@@ -424,7 +424,7 @@ static INPUT_PORTS_START( untoucha )
PORT_DIPNAME( 0x40, 0x40, "Speech" ) PORT_DIPLOCATION("SW2:2")
PORT_DIPSETTING( 0x40, DEF_STR( On ) )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
- PORT_DIPNAME( 0x20, 0x20, "Unknown (Aumit?)" ) PORT_DIPLOCATION("SW2:3")
+ PORT_DIPNAME( 0x20, 0x20, "Unknown (Aumit?)" ) PORT_DIPLOCATION("SW2:3")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) /* DIPSW sheet says 'AUMIT CUT WHEN ON' */
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) /* Maybe it is Audit, but where/what? */
PORT_DIPNAME( 0x10, 0x10, "Auto Hold" ) PORT_DIPLOCATION("SW2:4")
diff --git a/src/mame/drivers/homedata.cpp b/src/mame/drivers/homedata.cpp
index f5d2a6181b1..b19ab6dd652 100644
--- a/src/mame/drivers/homedata.cpp
+++ b/src/mame/drivers/homedata.cpp
@@ -639,19 +639,19 @@ ADDRESS_MAP_END
static INPUT_PORTS_START( mjhokite )
PORT_START("DSW1")
- PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:8")
+ PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:8")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW1:7" )
- PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:6,5")
+ PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW1:7" )
+ PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:6,5")
PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x10, 0x10, "Initial Score" ) PORT_DIPLOCATION("SW1:4")
+ PORT_DIPNAME( 0x10, 0x10, "Initial Score" ) PORT_DIPLOCATION("SW1:4")
PORT_DIPSETTING( 0x10, "1000" )
PORT_DIPSETTING( 0x00, "2000" )
- PORT_DIPNAME( 0xe0, 0x80, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:3,2,1")
+ PORT_DIPNAME( 0xe0, 0x80, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:3,2,1")
PORT_DIPSETTING( 0xe0, "1 (easiest)" )
PORT_DIPSETTING( 0xc0, "2" )
PORT_DIPSETTING( 0xa0, "3" )
@@ -662,18 +662,18 @@ static INPUT_PORTS_START( mjhokite )
PORT_DIPSETTING( 0x00, "8 (hardest)" )
PORT_START("DSW2")
- PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:8")
+ PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:8")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x02, 0x00, "Girl Voice" ) PORT_DIPLOCATION("SW2:7")
+ PORT_DIPNAME( 0x02, 0x00, "Girl Voice" ) PORT_DIPLOCATION("SW2:7")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW2:6" )
- PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW2:5" )
+ PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW2:5" )
PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW2:4" )
- PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW2:3" )
+ PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW2:3" )
PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:2" )
- PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:1" )
+ PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:1" )
PORT_START("IN0")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
@@ -913,30 +913,30 @@ INPUT_PORTS_END
static INPUT_PORTS_START( pteacher )
PORT_START("DSW") /* dip switches (handled by pteacher_keyboard_r) */
- PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:1")
+ PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:1")
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
- PORT_DIPNAME( 0x0002, 0x0000, "In-Game BGM") PORT_DIPLOCATION("SW1:2")
+ PORT_DIPNAME( 0x0002, 0x0000, "In-Game BGM") PORT_DIPLOCATION("SW1:2")
PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
- PORT_DIPNAME( 0x000c, 0x000c, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:3,4")
- PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
- PORT_DIPSETTING( 0x0004, DEF_STR( 2C_1C ) )
- PORT_DIPSETTING( 0x000c, DEF_STR( 1C_1C ) )
- PORT_DIPSETTING( 0x0008, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x0010, 0x0010, "Female Voices" ) PORT_DIPLOCATION("SW1:5")
- PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0010, DEF_STR( On ) )
- PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW1:6" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW1:7" )
- PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
- PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
-
- PORT_SERVICE_DIPLOC(0x0100, IP_ACTIVE_LOW, "SW2:1" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW2:2" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW2:3" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW2:4" )
+ PORT_DIPNAME( 0x000c, 0x000c, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:3,4")
+ PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
+ PORT_DIPSETTING( 0x0004, DEF_STR( 2C_1C ) )
+ PORT_DIPSETTING( 0x000c, DEF_STR( 1C_1C ) )
+ PORT_DIPSETTING( 0x0008, DEF_STR( 1C_2C ) )
+ PORT_DIPNAME( 0x0010, 0x0010, "Female Voices" ) PORT_DIPLOCATION("SW1:5")
+ PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0010, DEF_STR( On ) )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW1:6" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW1:7" )
+ PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
+ PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+
+ PORT_SERVICE_DIPLOC(0x0100, IP_ACTIVE_LOW, "SW2:1" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW2:2" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW2:3" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW2:4" )
PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("COIN")
@@ -950,8 +950,8 @@ INPUT_PORTS_END
static INPUT_PORTS_START( mjjoship )
PORT_INCLUDE( pteacher )
- // Manual wrong for this game - it's an incomplete version of the
- // pteacher set, with no service mode and start score instead of
+ // Manual wrong for this game - it's an incomplete version of the
+ // pteacher set, with no service mode and start score instead of
// girl voices. Coins stated in manual in same place but do nothing
PORT_MODIFY("DSW")
diff --git a/src/mame/drivers/ibmpcjr.cpp b/src/mame/drivers/ibmpcjr.cpp
index 6d3859f7183..878b6ff29dd 100644
--- a/src/mame/drivers/ibmpcjr.cpp
+++ b/src/mame/drivers/ibmpcjr.cpp
@@ -613,7 +613,7 @@ static MACHINE_CONFIG_START( ibmpcjr, pcjr_state)
/* video hardware */
MCFG_PCVIDEO_PCJR_ADD("pcvideo_pcjr")
MCFG_VIDEO_SET_SCREEN("pcvideo_pcjr:screen")
-
+
MCFG_GFXDECODE_ADD("gfxdecode", "pcvideo_pcjr:palette", pcjr)
/* sound hardware */
diff --git a/src/mame/drivers/itech32.cpp b/src/mame/drivers/itech32.cpp
index af9304a915d..1b0ef8b6137 100644
--- a/src/mame/drivers/itech32.cpp
+++ b/src/mame/drivers/itech32.cpp
@@ -443,7 +443,7 @@ WRITE16_MEMBER(itech32_state::int1_ack_w)
void itech32_state::machine_start()
{
membank("soundbank")->configure_entries(0, 256, memregion("soundcpu")->base() + 0x10000, 0x4000);
-
+
save_item(NAME(m_vint_state));
save_item(NAME(m_xint_state));
save_item(NAME(m_qint_state));
diff --git a/src/mame/drivers/legionna.cpp b/src/mame/drivers/legionna.cpp
index 87d29f816e9..08c4480e40b 100644
--- a/src/mame/drivers/legionna.cpp
+++ b/src/mame/drivers/legionna.cpp
@@ -904,13 +904,13 @@ static INPUT_PORTS_START( cupsoc )
// TODO: dip-conditional with coin slots
// SEIBU_COIN_INPUTS override
PORT_START("COIN")
- PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
+ PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
- PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
+ PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
+ PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNUSED )
+ PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )
+ PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_START("SYSTEM")
@@ -931,7 +931,7 @@ static INPUT_PORTS_START( cupsoc )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
- PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED )
+ PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
diff --git a/src/mame/drivers/nbmj8688.cpp b/src/mame/drivers/nbmj8688.cpp
index 455f67c5dbf..314a62da37f 100644
--- a/src/mame/drivers/nbmj8688.cpp
+++ b/src/mame/drivers/nbmj8688.cpp
@@ -2210,7 +2210,7 @@ INPUT_PORTS_END
static INPUT_PORTS_START( ojousan )
PORT_START("DSWA")
- PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2,3")
+ PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2,3")
PORT_DIPSETTING( 0x07, "1 (Easy)" )
PORT_DIPSETTING( 0x06, "2" )
PORT_DIPSETTING( 0x05, "3" )
@@ -2219,10 +2219,10 @@ static INPUT_PORTS_START( ojousan )
PORT_DIPSETTING( 0x02, "6" )
PORT_DIPSETTING( 0x01, "7" )
PORT_DIPSETTING( 0x00, "8 (Hard)" )
- PORT_DIPNAME( 0x08, 0x00, "RENCHAN after TENPAIed RYUKYOKU" ) PORT_DIPLOCATION("SWA:4")
+ PORT_DIPNAME( 0x08, 0x00, "RENCHAN after TENPAIed RYUKYOKU" ) PORT_DIPLOCATION("SWA:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, "Character Display Test" ) PORT_DIPLOCATION("SWA:5")
+ PORT_DIPNAME( 0x10, 0x10, "Character Display Test" ) PORT_DIPLOCATION("SWA:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SWA:6" )
@@ -3029,7 +3029,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( swinggal, ojousan )
- MCFG_CPU_MODIFY("maincpu")
+ MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(secolove_map)
MCFG_CPU_IO_MAP(iemoto_io_map)
MACHINE_CONFIG_END
@@ -3560,23 +3560,23 @@ ROM_START( ojousanm )
ROM_END
ROM_START( swinggal )
- ROM_REGION( 0x10000, "maincpu", 0 ) /* program */
- ROM_LOAD( "1.4G", 0x00000, 0x08000, CRC(e0e94bb9) SHA1(f514993614376c2175e906eab2776567e0c32f67) )
- ROM_LOAD( "2.3G", 0x08000, 0x08000, CRC(577d786e) SHA1(e47e78d8607be0e41c2b220eb367f67e5e19c481) )
-
- ROM_REGION( 0x30000, "voice", 0 ) /* voice */
- ROM_LOAD( "3I", 0x00000, 0x10000, CRC(b15ac0c4) SHA1(88c7a0be533465fc9c6833e52bcb1729c2307d06) )
- ROM_LOAD( "2I", 0x10000, 0x10000, CRC(ff44d460) SHA1(cd070b6b48cfafa67e9fe778a2a31e623caa3ddd) )
- ROM_LOAD( "1I", 0x20000, 0x10000, CRC(05294295) SHA1(bb2114dccc94545664c10a9e32ebd87eed59865c) )
-
- ROM_REGION( 0x1c0000, "gfx1", 0 ) /* gfx */
- /* 000000-0fffff empty */
- ROM_LOAD( "3.5A", 0x100000, 0x20000, CRC(c1f49332) SHA1(35e4db593ab54b0ab6734a377cc2ed1c8670314c) )
- ROM_LOAD( "4.6A", 0x120000, 0x20000, CRC(f9bac001) SHA1(3aa707c75c27b968303bb8bc007e5da872a807f5) )
- ROM_LOAD( "5.7A", 0x140000, 0x20000, CRC(d9ec3418) SHA1(0d29d800a821b6806dc6b9d5a7aaa0939346ddc4) )
- ROM_LOAD( "6.8A", 0x160000, 0x20000, CRC(5a966741) SHA1(c122ada315f09b0851947e9efd67e0a11663cf66) )
- ROM_LOAD( "7.9A", 0x180000, 0x20000, CRC(93abe5c5) SHA1(d71da2ded70726af0aa1ee751fbab758326447ab) )
- ROM_LOAD( "8.10A", 0x1a0000, 0x20000, CRC(010d353d) SHA1(5ea7fd6f26f6ad484bb6e07e66e8c25d178ac037) )
+ ROM_REGION( 0x10000, "maincpu", 0 ) /* program */
+ ROM_LOAD( "1.4G", 0x00000, 0x08000, CRC(e0e94bb9) SHA1(f514993614376c2175e906eab2776567e0c32f67) )
+ ROM_LOAD( "2.3G", 0x08000, 0x08000, CRC(577d786e) SHA1(e47e78d8607be0e41c2b220eb367f67e5e19c481) )
+
+ ROM_REGION( 0x30000, "voice", 0 ) /* voice */
+ ROM_LOAD( "3I", 0x00000, 0x10000, CRC(b15ac0c4) SHA1(88c7a0be533465fc9c6833e52bcb1729c2307d06) )
+ ROM_LOAD( "2I", 0x10000, 0x10000, CRC(ff44d460) SHA1(cd070b6b48cfafa67e9fe778a2a31e623caa3ddd) )
+ ROM_LOAD( "1I", 0x20000, 0x10000, CRC(05294295) SHA1(bb2114dccc94545664c10a9e32ebd87eed59865c) )
+
+ ROM_REGION( 0x1c0000, "gfx1", 0 ) /* gfx */
+ /* 000000-0fffff empty */
+ ROM_LOAD( "3.5A", 0x100000, 0x20000, CRC(c1f49332) SHA1(35e4db593ab54b0ab6734a377cc2ed1c8670314c) )
+ ROM_LOAD( "4.6A", 0x120000, 0x20000, CRC(f9bac001) SHA1(3aa707c75c27b968303bb8bc007e5da872a807f5) )
+ ROM_LOAD( "5.7A", 0x140000, 0x20000, CRC(d9ec3418) SHA1(0d29d800a821b6806dc6b9d5a7aaa0939346ddc4) )
+ ROM_LOAD( "6.8A", 0x160000, 0x20000, CRC(5a966741) SHA1(c122ada315f09b0851947e9efd67e0a11663cf66) )
+ ROM_LOAD( "7.9A", 0x180000, 0x20000, CRC(93abe5c5) SHA1(d71da2ded70726af0aa1ee751fbab758326447ab) )
+ ROM_LOAD( "8.10A", 0x1a0000, 0x20000, CRC(010d353d) SHA1(5ea7fd6f26f6ad484bb6e07e66e8c25d178ac037) )
ROM_END
ROM_START( bijokkog )
@@ -4060,7 +4060,7 @@ GAME( 1987, iemotom, iemoto, iemotom, iemotom, driver_device, 0,
GAME( 1987, ryuuha, iemoto, ryuuha, ryuuha, driver_device, 0, ROT0, "Central Denshi", "Ryuuha [BET] (Japan 871027)", MACHINE_SUPPORTS_SAVE )
GAME( 1987, ojousan, 0, ojousan, ojousan, driver_device, 0, ROT0, "Nichibutsu", "Ojousan (Japan 871204)", MACHINE_SUPPORTS_SAVE )
GAME( 1987, ojousanm, ojousan, ojousanm, ojousanm, driver_device, 0, ROT0, "Nichibutsu", "Ojousan [BET] (Japan 870108)", MACHINE_SUPPORTS_SAVE )
-GAME( 1987, swinggal, 0, swinggal, ryuuha, driver_device, 0, ROT0, "Digital Denshi", "Swing Gal [BET] (Japan 871221)", MACHINE_SUPPORTS_SAVE )
+GAME( 1987, swinggal, 0, swinggal, ryuuha, driver_device, 0, ROT0, "Digital Denshi", "Swing Gal [BET] (Japan 871221)", MACHINE_SUPPORTS_SAVE )
GAME( 1988, korinai, 0, korinai, korinai, driver_device, 0, ROT0, "Nichibutsu", "Mahjong-zukino Korinai Menmen (Japan 880425)", MACHINE_SUPPORTS_SAVE )
GAME( 1988, korinaim, korinai, korinaim, korinaim, driver_device, 0, ROT0, "Nichibutsu", "Mahjong-zukino Korinai Menmen [BET] (Japan 880920)", MACHINE_SUPPORTS_SAVE )
diff --git a/src/mame/drivers/nbmj8891.cpp b/src/mame/drivers/nbmj8891.cpp
index 0ef8e6879e3..25c4fdbb1bd 100644
--- a/src/mame/drivers/nbmj8891.cpp
+++ b/src/mame/drivers/nbmj8891.cpp
@@ -767,7 +767,7 @@ INPUT_PORTS_END
static INPUT_PORTS_START( msjiken )
PORT_START("DSWA")
- PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:1,2,3")
+ PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:1,2,3")
PORT_DIPSETTING( 0x07, "1 (Easy)" )
PORT_DIPSETTING( 0x06, "2" )
PORT_DIPSETTING( 0x05, "3" )
@@ -776,19 +776,19 @@ static INPUT_PORTS_START( msjiken )
PORT_DIPSETTING( 0x02, "6" )
PORT_DIPSETTING( 0x01, "7" )
PORT_DIPSETTING( 0x00, "8 (Hard)" )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:4")
PORT_DIPSETTING( 0x08, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x10, 0x10, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:5")
+ PORT_DIPNAME( 0x10, 0x10, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
+ PORT_DIPNAME( 0x20, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x00, "Game Sounds" ) PORT_DIPLOCATION("SW1:7")
+ PORT_DIPNAME( 0x40, 0x00, "Game Sounds" ) PORT_DIPLOCATION("SW1:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, "Control Type" ) PORT_DIPLOCATION("SW1:8")
+ PORT_DIPNAME( 0x80, 0x80, "Control Type" ) PORT_DIPLOCATION("SW1:8")
PORT_DIPSETTING( 0x80, "ROYAL" )
PORT_DIPSETTING( 0x00, "JAMMA" )
@@ -1161,7 +1161,7 @@ static INPUT_PORTS_START( mjfocus )
// I don't have manual for this game.
PORT_START("DSWA")
- PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2,3")
+ PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2,3")
PORT_DIPSETTING( 0x07, "1 (Easy)" )
PORT_DIPSETTING( 0x06, "2" )
PORT_DIPSETTING( 0x05, "3" )
@@ -1170,13 +1170,13 @@ static INPUT_PORTS_START( mjfocus )
PORT_DIPSETTING( 0x02, "6" )
PORT_DIPSETTING( 0x01, "7" )
PORT_DIPSETTING( 0x00, "8 (Hard)" )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:4")
PORT_DIPSETTING( 0x08, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x10, 0x10, "Character Display Test" ) PORT_DIPLOCATION("SWA:5")
+ PORT_DIPNAME( 0x10, 0x10, "Character Display Test" ) PORT_DIPLOCATION("SWA:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SWA:7" )
@@ -1738,27 +1738,27 @@ INPUT_PORTS_END
static INPUT_PORTS_START( mladyhtr )
PORT_START("DSWA")
- PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2")
+ PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2")
PORT_DIPSETTING( 0x03, "1" )
PORT_DIPSETTING( 0x02, "2" )
PORT_DIPSETTING( 0x01, "3" )
PORT_DIPSETTING( 0x00, "4" )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:3")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:3")
PORT_DIPSETTING( 0x04, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:5")
+ PORT_DIPNAME( 0x10, 0x10, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:5")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, "Game Sounds" ) PORT_DIPLOCATION("SWA:6")
+ PORT_DIPNAME( 0x20, 0x20, "Game Sounds" ) PORT_DIPLOCATION("SWA:6")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, "Game Mode" ) PORT_DIPLOCATION("SWA:7")
+ PORT_DIPNAME( 0x40, 0x40, "Game Mode" ) PORT_DIPLOCATION("SWA:7")
PORT_DIPSETTING( 0x40, "Beginner" )
PORT_DIPSETTING( 0x00, "Expert" )
- PORT_DIPNAME( 0x80, 0x80, "Graphic ROM Test" ) PORT_DIPLOCATION("SWA:8")
+ PORT_DIPNAME( 0x80, 0x80, "Graphic ROM Test" ) PORT_DIPLOCATION("SWA:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
diff --git a/src/mame/drivers/nbmj8991.cpp b/src/mame/drivers/nbmj8991.cpp
index 24a49727239..50900d54b80 100644
--- a/src/mame/drivers/nbmj8991.cpp
+++ b/src/mame/drivers/nbmj8991.cpp
@@ -300,27 +300,27 @@ INPUT_PORTS_END
static INPUT_PORTS_START( triplew1 )
PORT_START("DSWA")
- PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2")
+ PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2")
PORT_DIPSETTING( 0x03, "1 (Easy)" )
PORT_DIPSETTING( 0x02, "2" )
PORT_DIPSETTING( 0x01, "3" )
PORT_DIPSETTING( 0x00, "4 (Hard)" )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:3")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:3")
PORT_DIPSETTING( 0x04, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:4")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, "Game Sounds" ) PORT_DIPLOCATION("SWA:5")
+ PORT_DIPNAME( 0x10, 0x10, "Game Sounds" ) PORT_DIPLOCATION("SWA:5")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, "Character Display Test" ) PORT_DIPLOCATION("SWA:7")
+ PORT_DIPNAME( 0x40, 0x40, "Character Display Test" ) PORT_DIPLOCATION("SWA:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, "Graphic ROM Test" ) PORT_DIPLOCATION("SWA:8")
+ PORT_DIPNAME( 0x80, 0x80, "Graphic ROM Test" ) PORT_DIPLOCATION("SWA:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@@ -669,7 +669,7 @@ INPUT_PORTS_END
static INPUT_PORTS_START( galkoku )
PORT_START("DSWA")
- PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2,3")
+ PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:1,2,3")
PORT_DIPSETTING( 0x07, "1 (Easy)" )
PORT_DIPSETTING( 0x06, "2" )
PORT_DIPSETTING( 0x05, "3" )
@@ -678,19 +678,19 @@ static INPUT_PORTS_START( galkoku )
PORT_DIPSETTING( 0x02, "6" )
PORT_DIPSETTING( 0x01, "7" )
PORT_DIPSETTING( 0x00, "8 (Hard)" )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:4")
PORT_DIPSETTING( 0x08, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x10, 0x10, "Character Display Test" ) PORT_DIPLOCATION("SWA:5")
+ PORT_DIPNAME( 0x10, 0x10, "Character Display Test" ) PORT_DIPLOCATION("SWA:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unused ) ) PORT_DIPLOCATION("SWA:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unused ) ) PORT_DIPLOCATION("SWA:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) ) PORT_DIPLOCATION("SWA:8")
+ PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) ) PORT_DIPLOCATION("SWA:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
diff --git a/src/mame/drivers/nbmj9195.cpp b/src/mame/drivers/nbmj9195.cpp
index 06eddd16b8c..c0874236844 100644
--- a/src/mame/drivers/nbmj9195.cpp
+++ b/src/mame/drivers/nbmj9195.cpp
@@ -817,53 +817,53 @@ static INPUT_PORTS_START( patimono )
// Interesting note - manual states switch A:8 is always off/unused
PORT_START("DSWA")
- PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("DSWA:1,2")
- PORT_DIPSETTING( 0x03, "1" )
- PORT_DIPSETTING( 0x02, "2" )
- PORT_DIPSETTING( 0x01, "3" )
- PORT_DIPSETTING( 0x00, "4" )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Coinage ) ) PORT_DIPLOCATION("DSWA:3")
+ PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("DSWA:1,2")
+ PORT_DIPSETTING( 0x03, "1" )
+ PORT_DIPSETTING( 0x02, "2" )
+ PORT_DIPSETTING( 0x01, "3" )
+ PORT_DIPSETTING( 0x00, "4" )
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Coinage ) ) PORT_DIPLOCATION("DSWA:3")
PORT_DIPSETTING( 0x04, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("DSWA:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("DSWA:4")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x08, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, "Music" ) PORT_DIPLOCATION("DSWA:5")
+ PORT_DIPNAME( 0x10, 0x10, "Music" ) PORT_DIPLOCATION("DSWA:5")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x00, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("DSWA:6")
+ PORT_DIPNAME( 0x20, 0x00, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("DSWA:6")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, "Character Display Test" ) PORT_DIPLOCATION("DSWA:7")
+ PORT_DIPNAME( 0x40, 0x40, "Character Display Test" ) PORT_DIPLOCATION("DSWA:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, "Graphic ROM Test" ) PORT_DIPLOCATION("DSWA:8")
+ PORT_DIPNAME( 0x80, 0x80, "Graphic ROM Test" ) PORT_DIPLOCATION("DSWA:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSWB")
- PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:1")
+ PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:1")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:2")
+ PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:2")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:3")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:4")
+ PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:5")
+ PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:6")
+ PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:8")
+ PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSWB:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
diff --git a/src/mame/drivers/ohmygod.cpp b/src/mame/drivers/ohmygod.cpp
index a77393d241a..19432ad7651 100644
--- a/src/mame/drivers/ohmygod.cpp
+++ b/src/mame/drivers/ohmygod.cpp
@@ -300,7 +300,7 @@ GFXDECODE_END
void ohmygod_state::machine_start()
{
membank("okibank")->configure_entries(0, 16, memregion("oki")->base(), 0x20000);
-
+
save_item(NAME(m_spritebank));
save_item(NAME(m_scrollx));
save_item(NAME(m_scrolly));
diff --git a/src/mame/drivers/poisk1.cpp b/src/mame/drivers/poisk1.cpp
index 85f3c024706..8e7408060f1 100644
--- a/src/mame/drivers/poisk1.cpp
+++ b/src/mame/drivers/poisk1.cpp
@@ -644,7 +644,7 @@ static MACHINE_CONFIG_START( poisk1, p1_state )
MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_PLAY | CASSETTE_MOTOR_DISABLED | CASSETTE_SPEAKER_ENABLED)
MCFG_SOFTWARE_LIST_ADD("flop_list","poisk1_flop")
-// MCFG_SOFTWARE_LIST_ADD("cass_list","poisk1_cass")
+// MCFG_SOFTWARE_LIST_ADD("cass_list","poisk1_cass")
MCFG_SPEAKER_STANDARD_MONO( "mono" )
MCFG_SOUND_ADD( "speaker", SPEAKER_SOUND, 0 )
diff --git a/src/mame/drivers/rainbow.cpp b/src/mame/drivers/rainbow.cpp
index c9bbafeea8b..de3c7e9ea08 100644
--- a/src/mame/drivers/rainbow.cpp
+++ b/src/mame/drivers/rainbow.cpp
@@ -36,11 +36,11 @@ NVRAM files from -A and -B machines are not interchangeable. If problems arise,
CPM 2.1 / DOS2.11 / DOS 3.x and UCSD systems (fort_sys, pas_sys) + diag disks boot.
It is possible to boot DOS 3.10 from floppy A: and later use a hard disk attached to E:.
-NB.: a single hard disk (5 - 67 MB, 512 byte sectors) may be attached before startup. It should remain there
+NB.: a single hard disk (5 - 67 MB, 512 byte sectors) may be attached before startup. It should remain there
until shutdown. "Hot swapping" wasn't possible on the original system (our GUI just doesn't forbid it).
To create a RD50/ST506 compatible image (153 cylinders, 4 heads, 16 sectors, standard 512 byte sectors) enter
->chdman64 createhd - c none - chs 153, 4, 16 - ss 512 - o RD50_ST506.chd
+>chdman64 createhd - c none - chs 153, 4, 16 - ss 512 - o RD50_ST506.chd
NOTE: use -c none parameter for no compression. No more than 8 heads or 1024 cylinders.
Some BUGS remain: BIOS autoboot doesnt work at all. It is not possible to boot from a properly formatted
@@ -58,7 +58,7 @@ CURRENTY UNEMULATED
(b1) LOOPBACK circuit not emulated, NMI from RAM card also unemulated (NMI vector 02).
The former is used in startup tests, the latter seems less relevant (must use menu self test "S"
- or memory diagnostic test. TODO: mem.test causes a CPU crash when reaching higher RAM regions.
+ or memory diagnostic test. TODO: mem.test causes a CPU crash when reaching higher RAM regions.
(b2) system interaction tests HALT Z80 CPU at location $0211 (forever). Boot the RX50 diag.disk
to see what happens (key 3 - individual tests, then 12 - system interaction). Uses LOOPBACK too?
@@ -84,7 +84,7 @@ SH10 BDL REQ (L) -> Pin 1 (A0) BUNDLE OPTION wishes to use shared memory
HARDWARE UPGRADES WORTH EMULATING (should be implemented as SLOT DEVICES):
* Color graphics option (uses NEC upd7220 GDC). REFERENCE: Programmer's Reference: AA-AE36A-TV.
-Either 240 X 380 x 16 or 240 x 800 x 4 colors (out of 4096). 8 x 64 K video RAM.
+Either 240 X 380 x 16 or 240 x 800 x 4 colors (out of 4096). 8 x 64 K video RAM.
On a 100-A, pallette limited to 4 shades (LSB 2 bits; applies to medium resolution mode 240 X 380 pixels only).
Graphics output independent from monochrome output. Single and dual monitor configurations possible.
@@ -242,10 +242,10 @@ W17 pulls J1 serial port pin 1 to GND when set (chassis to logical GND).
#define RTC_BASE 0xFC000
// Do not pretend to emulate newer RAM board; stick with the old one:
-// (only affects presence bit in 'system_parameter_r')
+// (only affects presence bit in 'system_parameter_r')
#define OLD_RAM_BOARD_PRESENT
-#ifdef ASSUME_MODEL_A_HARDWARE
+#ifdef ASSUME_MODEL_A_HARDWARE
// Define standard and maximum RAM sizes (A model):
#define MOTHERBOARD_RAM 0x0ffff // 64 K base RAM (100-A)
#define END_OF_RAM 0xcffff // Very last byte (theretical; on 100-A) DO NOT CHANGE.
@@ -268,8 +268,8 @@ W17 pulls J1 serial port pin 1 to GND when set (chassis to logical GND).
// DEC says that MHFU is also re-enabled 'automatically after STI' (when under BIOS control?)
// Schematics show "VERT FREQ INT" (= DC012 output, pin 2) and MHFU ENBL L are evaluated,
-// as well as the power good signal from the PSU (AC_OK). MS_TO_POWER_GOOD is a guess:
-#define MS_TO_POWER_GOOD 350
+// as well as the power good signal from the PSU (AC_OK). MS_TO_POWER_GOOD is a guess:
+#define MS_TO_POWER_GOOD 350
// Reset duration of 108 ms from documentation -
#define RESET_DURATION_MS 108
@@ -290,13 +290,13 @@ W17 pulls J1 serial port pin 1 to GND when set (chassis to logical GND).
#include "machine/wd_fdc.h"
#include "formats/rx50_dsk.h"
-#include "formats/pc_dsk.h" // PC Formats
+#include "formats/pc_dsk.h" // PC Formats
#include "imagedev/flopdrv.h"
#include "imagedev/harddriv.h"
#include "machine/wd2010.h"
-#include "machine/z80dart.h"
+#include "machine/z80dart.h"
#include "bus/rs232/rs232.h"
#include "imagedev/bitbngr.h"
#include "machine/com8116.h"
@@ -422,7 +422,7 @@ public:
DECLARE_WRITE8_MEMBER(printer_bitrate_w);
DECLARE_WRITE_LINE_MEMBER( com8116_a_fr_w );
DECLARE_WRITE_LINE_MEMBER( com8116_a_ft_w );
-
+
UINT32 screen_update_rainbow(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
INTERRUPT_GEN_MEMBER(vblank_irq);
IRQ_CALLBACK_MEMBER(irq_callback);
@@ -485,7 +485,7 @@ private:
void lower_8088_irq(int ref);
void update_mpsc_irq();
- int m_mpsc_irq;
+ int m_mpsc_irq;
void update_8088_irqs();
void update_bundle_irq(); // RD51 or COMM.OPTION!
@@ -552,7 +552,7 @@ FLOPPY_FORMATS_END
static SLOT_INTERFACE_START(rainbow_floppies)
SLOT_INTERFACE("525qd0", FLOPPY_525_QD) // QD means 80 tracks with DD data rate (single or double sided).
SLOT_INTERFACE("525qd1", FLOPPY_525_QD)
-SLOT_INTERFACE("525dd", FLOPPY_525_DD) // mimic a 5.25" PC (40 track) drive. Requires IDrive5.SYS.
+SLOT_INTERFACE("525dd", FLOPPY_525_DD) // mimic a 5.25" PC (40 track) drive. Requires IDrive5.SYS.
SLOT_INTERFACE("35dd", FLOPPY_35_DD) // mimic 3.5" PC drive (720K, double density). Use Impdrv3.SYS.
SLOT_INTERFACE_END
@@ -560,8 +560,8 @@ void rainbow_state::machine_start()
{
m_POWER_GOOD = false; // Simulate AC_OK signal from power supply.
cmd_timer = timer_alloc(0);
- cmd_timer->adjust(attotime::from_msec(MS_TO_POWER_GOOD));
-
+ cmd_timer->adjust(attotime::from_msec(MS_TO_POWER_GOOD));
+
MOTOR_DISABLE_counter = 2; // soon resets drv.LEDs
m_SCREEN_BLANK = false;
@@ -585,7 +585,7 @@ void rainbow_state::machine_start()
rom[0xf4000 + 0x0303] = 0x00; // disable CRC check
rom[0xf4000 + 0x135e] = 0x00; // FLOPPY / RX-50 WORKAROUND: in case of Z80 RESPONSE FAILURE ($80 bit set in AL), do not block floppy access.
- rom[0xf4000 + 0x198F] = 0xeb; // cond.JMP to uncond.JMP (disables error message 60...)
+ rom[0xf4000 + 0x198F] = 0xeb; // cond.JMP to uncond.JMP (disables error message 60...)
}
#endif
}
@@ -719,7 +719,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(rainbowz80_io, AS_IO, 8, rainbow_state)
ADDRESS_MAP_UNMAP_HIGH
-ADDRESS_MAP_GLOBAL_MASK(0xff)
+ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x00) AM_READWRITE(z80_latch_r, z80_latch_w)
AM_RANGE(0x20, 0x20) AM_READWRITE(z80_generalstat_r, z80_diskdiag_read_w) // read to port 0x20 used by MS-DOS 2.x diskette loader.
AM_RANGE(0x21, 0x21) AM_READWRITE(z80_generalstat_r, z80_diskdiag_write_w)
@@ -836,31 +836,31 @@ void rainbow_state::machine_reset()
printf("\nWARNING: 896 K is not a valid memory configuration on Rainbow 100 A!\n");
}
-// check = (unmap_start >> 16)-1; // guess.
-// NVRAM_LOCATION = nv[0xed084]; // location not verified yet. DMT RAM check tests offset $84 !
+// check = (unmap_start >> 16)-1; // guess.
+// NVRAM_LOCATION = nv[0xed084]; // location not verified yet. DMT RAM check tests offset $84 !
#else
printf("\n*** RAINBOW B MODEL ASSUMED (128 - 896 K RAM)\n");
if (unmap_start < 0x20000)
{
- unmap_start = 0x20000; // 128 K minimum
+ unmap_start = 0x20000; // 128 K minimum
printf("\nWARNING: 64 K is not a valid memory size on Rainbow 100-B!\n");
}
check = (unmap_start >> 16) - 2;
- NVRAM_LOCATION = nv[0xed0db];
+ NVRAM_LOCATION = nv[0xed0db];
#endif
if (check != NVRAM_LOCATION)
printf("\nNOTE: RAM configuration does not match NVRAM.\nUNMAP_START = %05x NVRAM VALUE = %02x SHOULD BE: %02x\n", unmap_start, NVRAM_LOCATION, check);
if(END_OF_RAM > unmap_start)
program.unmap_readwrite(unmap_start, END_OF_RAM);
-
- m_crtc->MHFU(MHFU_RESET_and_DISABLE);
+
+ m_crtc->MHFU(MHFU_RESET_and_DISABLE);
#ifdef RTC_ENABLED
// *********************************** / DS1315 'PHANTOM CLOCK' IMPLEMENTATION FOR 'DEC-100-B' ***************************************
// No address space needed ( -> IRQs must be disabled to block ROM accesses during reads ).
- program.install_read_handler(RTC_BASE, RTC_BASE + 0x2104, read8_delegate(FUNC(rainbow_state::rtc_r), this));
+ program.install_read_handler(RTC_BASE, RTC_BASE + 0x2104, read8_delegate(FUNC(rainbow_state::rtc_r), this));
// *********************************** / DS1315 'PHANTOM CLOCK' IMPLEMENTATION FOR 'DEC-100-B' ***************************************
#endif
@@ -908,7 +908,7 @@ void rainbow_state::machine_reset()
m_z80->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
m_z80_halted = true;
- m_zflip = true; // ZRESET high on startup
+ m_zflip = true; // ZRESET high on startup
m_diagnostic = 0; // DIAGNOSTIC_R/W registers (shouldn't it be 1?)
INTZ80 = false;
@@ -1022,7 +1022,7 @@ void rainbow_state::update_mpsc_irq()
else
raise_8088_irq(IRQ_COMM_PTR_INTR_L);
- m_mpsc->m1_r(); // interrupt acknowledge
+ m_mpsc->m1_r(); // interrupt acknowledge
}
WRITE_LINE_MEMBER(rainbow_state::mpsc_irq)
@@ -1031,18 +1031,18 @@ WRITE_LINE_MEMBER(rainbow_state::mpsc_irq)
update_mpsc_irq();
}
-// PORT 0x0e : Printer bit rates
+// PORT 0x0e : Printer bit rates
WRITE8_MEMBER(rainbow_state::printer_bitrate_w)
-{
+{
printf("\nPRINTER bitrate = %02x HEX\n",data & 7);
// "bit 3 controls the communications port clock (RxC,TxC). External clock when 1, internal when 0"
- printf(" - CLOCK BIT: %02x", data & 8);
+ printf(" - CLOCK BIT: %02x", data & 8);
}
// PORT 0x06 : Communication bit rates (see page 21 of PC 100 SPEC)
WRITE8_MEMBER(rainbow_state::comm_bitrate_w)
-{
+{
m_dbrg->str_w(data & 0x0f); // PDF is wrong, low nibble is RECEIVE clock (verified in SETUP).
printf("\nRECEIVE bitrate = %02x HEX\n",data & 0x0f);
@@ -1126,9 +1126,9 @@ WRITE8_MEMBER(rainbow_state::share_z80_w)
// DRIVERS: (a) DOS and CP/M binaries plus source from DEC employee (rbclik); Reads & displays times. Y2K READY!
// (b) Suitable Solutions ClikClok distribution disk; Uses $FE000 and up. 2 digit year. Needed to set time & date.
-//
-// TODO: obtain hardware / check address decoders.
-// RTC accesses here were derived from Vincent Esser's published source.
+//
+// TODO: obtain hardware / check address decoders.
+// RTC accesses here were derived from Vincent Esser's published source.
READ8_MEMBER(rainbow_state::rtc_r)
{
if((m_inp11->read() == 0x01)) // if enabled...
@@ -1136,34 +1136,34 @@ READ8_MEMBER(rainbow_state::rtc_r)
switch (offset)
{
// Transfer data to DS1315 (data = offset):
- case 0x0000: // RTC_WRITE_DATA_0 0xFC000
+ case 0x0000: // RTC_WRITE_DATA_0 0xFC000
case 0x2000: // RTC_WRITE_DATA_0 0xFE000 (MIRROR)
- case 0x0001: // RTC_WRITE_DATA_1 0xFC001
+ case 0x0001: // RTC_WRITE_DATA_1 0xFC001
case 0x2001: // RTC_WRITE_DATA_1 0xFE001 (MIRROR)
- m_rtc->write_data(space, offset & 0x01);
+ m_rtc->write_data(space, offset & 0x01);
break;
// Read actual time/date from ClikClok:
case 0x0004: // 0xFC004
case 0x2004: // 0xFE004 (MIRROR)
- if (m_rtc->chip_enable())
- return (m_rtc->read_data(space, 0) & 0x01);
+ if (m_rtc->chip_enable())
+ return (m_rtc->read_data(space, 0) & 0x01);
- // (RTC ACTIVATION) READ MAGIC PATTERN 0
- case 0x0100: // 0xFC100
+ // (RTC ACTIVATION) READ MAGIC PATTERN 0
+ case 0x0100: // 0xFC100
case 0x2100: // 0xFE100 (MIRROR)
- m_rtc->read_0(space, 0);
+ m_rtc->read_0(space, 0);
break;
- // (RTC ACTIVATION) READ MAGIC PATTERN 1
- case 0x0101: // 0xFC101
+ // (RTC ACTIVATION) READ MAGIC PATTERN 1
+ case 0x0101: // 0xFC101
case 0x2101: // 0xFE101 (MIRROR)
- m_rtc->read_1(space, 0);
+ m_rtc->read_1(space, 0);
break;
// RESET
- case 0x0104: // 0xFC104
+ case 0x0104: // 0xFC104
case 0x2104: // 0xFE104 (MIRROR)
m_rtc->chip_reset();
break;
@@ -1171,7 +1171,7 @@ READ8_MEMBER(rainbow_state::rtc_r)
}
UINT8 *rom = memregion("maincpu")->base();
- return rom[RTC_BASE + offset]; // Return ROM to prevent crashes
+ return rom[RTC_BASE + offset]; // Return ROM to prevent crashes
}
// ------------------------/ ClikClok (for model B; DS1315) ---------------------------------
@@ -1185,8 +1185,8 @@ static const int SECTOR_SIZES[4] = { 256, 512, 1024, 128 };
void rainbow_state::hdc_reset()
{
-// logerror(">> HARD DISC CONTROLLER RESET <<\n");
- m_hdc->reset();
+// logerror(">> HARD DISC CONTROLLER RESET <<\n");
+ m_hdc->reset();
m_bdl_irq = 0;
update_bundle_irq(); // reset INTRQ
@@ -1260,7 +1260,7 @@ static UINT32 get_and_print_lbasector(device_t *device, hard_disk_info *info, UI
lbasector *= info->sectors; // LBA : ( x 16 )
lbasector += (sector_number - 1); // + (sector number - 1)
-// device->logerror(" CYLINDER %u - HEAD %u - SECTOR NUMBER %u (LBA-SECTOR %u) ", cylinder, head, sector_number, lbasector);
+// device->logerror(" CYLINDER %u - HEAD %u - SECTOR NUMBER %u (LBA-SECTOR %u) ", cylinder, head, sector_number, lbasector);
return lbasector;
}
@@ -1279,7 +1279,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
{
read_status = 2;
-// logerror("\nTRYING TO READ");
+// logerror("\nTRYING TO READ");
output().set_value("led1", 0);
int hi = (m_hdc->read(generic_space(), 0x05)) & 0x07;
@@ -1310,7 +1310,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
if (hard_disk_read(local_hard_disk, lbasector, m_hdc_buffer)) // accepts LBA sector (UINT32) !
{
read_status = 0;
-// logerror("...success!\n");
+// logerror("...success!\n");
}
}
}
@@ -1401,7 +1401,7 @@ int rainbow_state::do_write_sector()
if ((info = hard_disk_get_info(local_hard_disk)))
{
feedback = 10;
-// logerror("\n* TRYING TO WRITE * ");
+// logerror("\n* TRYING TO WRITE * ");
output().set_value("led1", 1); // OFF
UINT8 SDH = (m_hdc->read(generic_space(), 0x06));
@@ -1483,7 +1483,7 @@ READ8_MEMBER(rainbow_state::hd_status_68_r)
int my_offset = 0x07;
int stat = m_hdc->read(space, my_offset);
-// logerror("(x68) WD1010 register %04x (STATUS) read, result : %04x\n", my_offset, stat);
+// logerror("(x68) WD1010 register %04x (STATUS) read, result : %04x\n", my_offset, stat);
// NOTE: SEEK COMPLETE IS CURRENTLY HARD WIRED / NOT FULLY EMULATED -
// Bit 4 : SEEK COMPLETE: This status bit indicates that the disk drive positioned the R/W heads over the desired track on the disk surface.
@@ -1546,7 +1546,7 @@ WRITE8_MEMBER(rainbow_state::hd_status_68_w)
// 1 : see @ 088D after 'READ_SECTOR_OK'
if (data & 0x01)
{
-// logerror(">> HARD DISC * SET BUFFER READY * <<\n");
+// logerror(">> HARD DISC * SET BUFFER READY * <<\n");
output().set_value("led1", 0); // 1 = OFF (One of the CPU LEDs as DRIVE LED) = HARD DISK ACTIVITY =
MOTOR_DISABLE_counter = 20;
@@ -1585,7 +1585,7 @@ positioned over cylinder 0 (the data track furthest away from the spindle).
READ8_MEMBER(rainbow_state::hd_status_69_r)
{
int HS = m_hdc->read(space, 0x06) & (1 + 2 + 4); // SDH bits 0-2 = HEAD #
-// logerror("(x69 READ) %i = HEAD SELECT WD1010\n", HS);
+// logerror("(x69 READ) %i = HEAD SELECT WD1010\n", HS);
UINT8 data = (HS << 1);
@@ -1594,7 +1594,7 @@ READ8_MEMBER(rainbow_state::hd_status_69_r)
int DRV = ((m_hdc->read(space, 0x06) >> 3) & 0x01); // 0x03 gives error R6 with DIAG.DISK
if (DRV == 0)
{
-// logerror("(x69 READ) %i = _DRIVE # 0_ SELECT! \n", DRV);
+// logerror("(x69 READ) %i = _DRIVE # 0_ SELECT! \n", DRV);
data |= 1;
}
@@ -1607,7 +1607,7 @@ READ8_MEMBER(rainbow_state::hd_status_69_r)
if (m_hdc_drive_ready)
data |= 64;
- m_hdc_track0 = false; // Fake TRACK 0 signal (normally FROM DRIVE)
+ m_hdc_track0 = false; // Fake TRACK 0 signal (normally FROM DRIVE)
int stat1 = m_hdc->read(space, 0x04); // CYL LO
int stat2 = m_hdc->read(space, 0x05); // CYL HI
@@ -1617,7 +1617,7 @@ READ8_MEMBER(rainbow_state::hd_status_69_r)
if (m_hdc_track0)
{
data |= 128;
-// logerror("(x69 READ) TRACK 00 detected\n");
+// logerror("(x69 READ) TRACK 00 detected\n");
}
return data;
@@ -1672,7 +1672,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_bdrq)
{
static int old_state;
-// logerror("BDRQ - BUFFER DATA REQUEST OBTAINED: %u\n", state);
+// logerror("BDRQ - BUFFER DATA REQUEST OBTAINED: %u\n", state);
if ((state == 1) && (old_state == 0))
{
hdc_buffer_counter_reset();
@@ -1725,35 +1725,35 @@ READ8_MEMBER(rainbow_state::system_parameter_r)
return (((m_inp5->read() == 1) ? 0 : 1) |
((m_inp6->read() == 1) ? 0 : 2) |
((m_inp7->read() == 1) ? 0 : 4) |
-#ifdef OLD_RAM_BOARD_PRESENT
- ((m_inp8->read() > MOTHERBOARD_RAM) ? 0 : 8) |
+#ifdef OLD_RAM_BOARD_PRESENT
+ ((m_inp8->read() > MOTHERBOARD_RAM) ? 0 : 8) |
#else
8 |
#endif
- 16 | 32 | 64 | 128 // to be verified.
+ 16 | 32 | 64 | 128 // to be verified.
);
}
-// [02] COMMUNICATIONS STATUS REGISTER - PAGE 154 (**** READ **** )
-// Used to read status of SERIAL port, IRQ line of each CPU, and MHFU logic enable signal.
+// [02] COMMUNICATIONS STATUS REGISTER - PAGE 154 (**** READ **** )
+// Used to read status of SERIAL port, IRQ line of each CPU, and MHFU logic enable signal.
// ******* TODO: 5 status bits * MISSING * ********************************************************
// 0 COMM RI (reflects status of RI line at COMM port)
// 1 COMM SI / SCF(reflects status of speed indicator line or
-// the secondary receive line signal detect at COMM port)
+// the secondary receive line signal detect at COMM port)
// 2 COMM DSR (reflects status of DSR at COMM)
// 3 COMM CTS (reflects status of CTS at COMM)
// 4 COMM RLSD (receive line signal detect at COMM)
READ8_MEMBER(rainbow_state::comm_control_r)
{
- bool is_mhfu_enabled = false;
- if (m_POWER_GOOD)
- is_mhfu_enabled = m_crtc->MHFU(MHFU_IS_ENABLED);
-
- return (
- (is_mhfu_enabled ? 0x00 : 0x20) | // (L) status of MHFU flag => bit pos.5
- ((INT88) ? 0x00 : 0x40) | // (L)
- ((INTZ80) ? 0x00 : 0x80) // (L)
+ bool is_mhfu_enabled = false;
+ if (m_POWER_GOOD)
+ is_mhfu_enabled = m_crtc->MHFU(MHFU_IS_ENABLED);
+
+ return (
+ (is_mhfu_enabled ? 0x00 : 0x20) | // (L) status of MHFU flag => bit pos.5
+ ((INT88) ? 0x00 : 0x40) | // (L)
+ ((INTZ80) ? 0x00 : 0x80) // (L)
);
}
@@ -1763,7 +1763,7 @@ READ8_MEMBER(rainbow_state::comm_control_r)
// 0 COMM SPD SEL H (controls speed select line of COMM port)
// 1 COMM SRTS H (controls secondary request to send line of COMM)
// 2 COMM DTR L (controls terminal ready line of COMM)
-// 3 COMM RTS (controls request to send line of COMM)
+// 3 COMM RTS (controls request to send line of COMM)
WRITE8_MEMBER(rainbow_state::comm_control_w)
{
printf("%02x to COMM.CONTROL REGISTER ", data);
@@ -1894,7 +1894,7 @@ READ8_MEMBER(rainbow_state::z80_generalstat_r)
if (!m_floppy->ready_r()) // weird (see wd_fdc)
fdc_ready = 1;
- if ((fdc_ready) && (m_floppy->wpt_r() != 1) && m_POWER_GOOD)
+ if ((fdc_ready) && (m_floppy->wpt_r() != 1) && m_POWER_GOOD)
fdc_write_gate = 1; // * FAKE * WRITE GATE !
// "valid only when drive is selected" !
@@ -1922,7 +1922,7 @@ READ8_MEMBER(rainbow_state::z80_generalstat_r)
READ8_MEMBER(rainbow_state::z80_diskstatus_r)
{
int track = 0;
- int data = m_z80_diskcontrol & (255 - 0x80 - 0x40 - 0x20 - 4);
+ int data = m_z80_diskcontrol & (255 - 0x80 - 0x40 - 0x20 - 4);
// D7: DRQ: reflects status of DATA REQUEST signal from FDC.
// '1' indicates that FDC has read data OR requires new write data.
@@ -1938,7 +1938,7 @@ READ8_MEMBER(rainbow_state::z80_diskstatus_r)
// D5: SIDE 0 * HIGH ACTIVE *: status of side select signal at J2 + J3 of RX50 controller.
// For 1 sided drives, this bit will always read low (0).
if (m_floppy)
- data |= m_floppy->ss_r() ? 0x20 : 0x00;
+ data |= m_floppy->ss_r() ? 0x20 : 0x00;
// *LOW ACTIVE *
// D4: MOTOR 1 ON L: 0 = indicates MOTOR 1 ON bit is set in drive control reg.
@@ -1955,7 +1955,7 @@ READ8_MEMBER(rainbow_state::z80_diskstatus_r)
// D2: TG43 * LOW ACTIVE * : 0 = INDICATES TRACK > 43 SIGNAL FROM FDC TO DISK DRIVE.
// (asserted when writing data to tracks 44 through 79)
- data |= (track > 43) ? 0x00 : 0x04; // ! LOW ACTIVE !
+ data |= (track > 43) ? 0x00 : 0x04; // ! LOW ACTIVE !
// D1: DS1 H: reflect status of bits 0 and 1 from disk.control reg.
// D0: DS0 H: "
@@ -2090,14 +2090,14 @@ READ8_MEMBER(rainbow_state::read_video_ram_r)
// CPU acknowledge of VBL IRQ resets counter
IRQ_CALLBACK_MEMBER(rainbow_state::irq_callback)
-{
- int intnum = -1;
+{
+ int intnum = -1;
for (int i = IRQ_8088_VBL; i >= 0; i--)
{
if (m_irq_mask & (1 << i))
{
- if (i == IRQ_8088_VBL) // If VBL IRQ acknowledged...
- m_crtc->MHFU(MHFU_RESET); // ...reset counter (also: DC012_W)
+ if (i == IRQ_8088_VBL) // If VBL IRQ acknowledged...
+ m_crtc->MHFU(MHFU_RESET); // ...reset counter (also: DC012_W)
intnum = vectors[i] | m_irq_high;
break;
@@ -2111,7 +2111,7 @@ INTERRUPT_GEN_MEMBER(rainbow_state::vblank_irq)
raise_8088_irq(IRQ_8088_VBL);
m_crtc->notify_vblank(true);
- if (m_POWER_GOOD && m_crtc->MHFU(MHFU_IS_ENABLED)) // If enabled...
+ if (m_POWER_GOOD && m_crtc->MHFU(MHFU_IS_ENABLED)) // If enabled...
{
if (m_crtc->MHFU(MHFU_VALUE) > 7) // + more than (7 * 16.666) msecs gone (108 ms would be by the book)
{
@@ -2130,7 +2130,7 @@ WRITE_LINE_MEMBER(rainbow_state::clear_video_interrupt)
m_crtc->notify_vblank(false);
}
-// Reflects bits from 'diagnostic_w' (1:1), except test jumpers
+// Reflects bits from 'diagnostic_w' (1:1), except test jumpers
READ8_MEMBER(rainbow_state::diagnostic_r) // 8088 (port 0A READ). Fig.4-29 + table 4-15
{
return ((m_diagnostic & (0xf1)) |
@@ -2144,7 +2144,7 @@ WRITE8_MEMBER(rainbow_state::diagnostic_w) // 8088 (port 0A WRITTEN). Fig.4-28 +
{
// printf("%02x to diag port (PC=%x)\n", data, space.device().safe_pc());
m_SCREEN_BLANK = (data & 2) ? false : true;
-
+
// ZRESET from 8088 to Z80 - - HIGH at powerup!
if (!(data & 1))
{
@@ -2173,15 +2173,15 @@ WRITE8_MEMBER(rainbow_state::diagnostic_w) // 8088 (port 0A WRITTEN). Fig.4-28 +
m_fdc->reset(); // See formatter description p.197 or 5-13
}
- if (data & 0x04) // GRF_VID_SEL
+ if (data & 0x04) // GRF_VID_SEL
printf("\n*** UNEMULATED GRAPHICS [on GRAPHICS OPTION]. (bit 2 in diagnostic_w) = %i (0 = system module; else graphics option) ",data & 4);
// BIT 3: PARITY TEST (1 = enables parity test on memory option board).
- // FIXME: parity test = NMI? When should NMI fire? Whole bank tested?
+ // FIXME: parity test = NMI? When should NMI fire? Whole bank tested?
if (data & 0x08)
printf("\n*** UNEMULATED PARITY TEST [on RAM EXTENSION] - (bit 3 in diagnostic_w) ");
- // m_i8088->set_input_line_and_vector(INPUT_LINE_NMI, ASSERT_LINE, 0x02);
-
+ // m_i8088->set_input_line_and_vector(INPUT_LINE_NMI, ASSERT_LINE, 0x02);
+
// MISSING BITS (* not vital for normal operation, see diag.disk) -
// * BIT 4: DIAG LOOPBACK (0 at power-up; 1 directs RX50 and DC12 output to printer port)
// * BIT 5: PORT LOOPBACK (1 enables loopback for COMM, PRINTER, KEYBOARD ports)
@@ -2277,7 +2277,7 @@ WRITE_LINE_MEMBER(rainbow_state::write_keyboard_clock)
TIMER_DEVICE_CALLBACK_MEMBER(rainbow_state::motor_tick)
{
if (m_POWER_GOOD)
- m_crtc->MHFU(MHFU_COUNT); // // Increment IF ENABLED and POWER_GOOD, return count
+ m_crtc->MHFU(MHFU_COUNT); // // Increment IF ENABLED and POWER_GOOD, return count
m_hdc_index_latch = true; // HDC drive index signal (not working ?)
@@ -2298,7 +2298,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(rainbow_state::motor_tick)
// on 100-B, DTR from the keyboard 8051 controls bit 7 of IRQ vectors
WRITE_LINE_MEMBER(rainbow_state::irq_hi_w)
{
-#ifdef ASSUME_MODEL_A_HARDWARE
+#ifdef ASSUME_MODEL_A_HARDWARE
m_irq_high = 0;
#else
m_irq_high = (state == ASSERT_LINE) ? 0x80 : 0;
@@ -2316,7 +2316,7 @@ static const gfx_layout rainbow_charlayout =
{ 0, 1, 2, 3, 4, 5, 6, 7 },
/* y offsets */
{ 15 * 8, 0 * 8, 1 * 8, 2 * 8, 3 * 8, 4 * 8, 5 * 8, 6 * 8, 7 * 8, 8 * 8 },
- 8 * 16 /* every char takes 16 bytes */
+ 8 * 16 /* every char takes 16 bytes */
};
static GFXDECODE_START(rainbow)
@@ -2386,28 +2386,28 @@ MCFG_HARDDISK_ADD("harddisk1")
MCFG_DS1315_ADD("rtc") // DS1315 (ClikClok for DEC-100 B) * OPTIONAL *
-MCFG_DEVICE_ADD("com8116", COM8116, XTAL_5_0688MHz) // Baud rate generator
+MCFG_DEVICE_ADD("com8116", COM8116, XTAL_5_0688MHz) // Baud rate generator
MCFG_COM8116_FR_HANDLER(WRITELINE(rainbow_state, com8116_a_fr_w))
MCFG_COM8116_FT_HANDLER(WRITELINE(rainbow_state, com8116_a_ft_w))
-MCFG_UPD7201_ADD("upd7201", XTAL_2_5MHz, 0, 0, 0, 0) // 2.5 Mhz from schematics
+MCFG_UPD7201_ADD("upd7201", XTAL_2_5MHz, 0, 0, 0, 0) // 2.5 Mhz from schematics
MCFG_Z80DART_OUT_INT_CB(WRITELINE(rainbow_state, mpsc_irq))
-MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd))
-MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_dtr))
+MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd))
+MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_dtr))
MCFG_Z80DART_OUT_RTSA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_rts))
-MCFG_Z80DART_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd))
-MCFG_Z80DART_OUT_DTRB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_dtr))
+MCFG_Z80DART_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd))
+MCFG_Z80DART_OUT_DTRB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_dtr))
MCFG_Z80DART_OUT_RTSB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_rts))
MCFG_RS232_PORT_ADD("rs232_a", default_rs232_devices, nullptr)
-MCFG_RS232_RXD_HANDLER(DEVWRITELINE("upd7201", upd7201_device, rxa_w))
-MCFG_RS232_CTS_HANDLER(DEVWRITELINE("upd7201", upd7201_device, ctsa_w))
-MCFG_RS232_DCD_HANDLER(DEVWRITELINE("upd7201", upd7201_device, dcda_w))
+MCFG_RS232_RXD_HANDLER(DEVWRITELINE("upd7201", upd7201_device, rxa_w))
+MCFG_RS232_CTS_HANDLER(DEVWRITELINE("upd7201", upd7201_device, ctsa_w))
+MCFG_RS232_DCD_HANDLER(DEVWRITELINE("upd7201", upd7201_device, dcda_w))
MCFG_RS232_PORT_ADD("rs232_b", default_rs232_devices, nullptr)
-MCFG_RS232_RXD_HANDLER(DEVWRITELINE("upd7201", upd7201_device, rxb_w))
+MCFG_RS232_RXD_HANDLER(DEVWRITELINE("upd7201", upd7201_device, rxb_w))
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("upd7201", upd7201_device, ctsb_w))
MCFG_RS232_DCD_HANDLER(DEVWRITELINE("upd7201", upd7201_device, dcdb_w))
diff --git a/src/mame/drivers/seibuspi.cpp b/src/mame/drivers/seibuspi.cpp
index fac077ac3f9..262e549c51b 100644
--- a/src/mame/drivers/seibuspi.cpp
+++ b/src/mame/drivers/seibuspi.cpp
@@ -947,12 +947,12 @@ READ32_MEMBER(seibuspi_state::ejsakura_keyboard_r)
{
// coins/eeprom data
UINT32 ret = m_special->read();
-
+
// multiplexed inputs
for (int i = 0; i < 5; i++)
if (m_ejsakura_input_port >> i & 1)
ret &= m_key[i]->read();
-
+
return ret;
}
diff --git a/src/mame/drivers/seicupbl.cpp b/src/mame/drivers/seicupbl.cpp
index 32d5bb4ebbe..27ed8f82f4e 100644
--- a/src/mame/drivers/seicupbl.cpp
+++ b/src/mame/drivers/seicupbl.cpp
@@ -2,15 +2,15 @@
// copyright-holders:Angelo Salese
/***************************************************************************
- Seibu Cup Soccer bootlegs
-
- Splitted since it definitely doesn't use neither real COP nor CRTC
-
-
- TODO:
- - tilemap chip drawings might be merged between this and other
- Seibu implementations.
-
+ Seibu Cup Soccer bootlegs
+
+ Splitted since it definitely doesn't use neither real COP nor CRTC
+
+
+ TODO:
+ - tilemap chip drawings might be merged between this and other
+ Seibu implementations.
+
***************************************************************************/
@@ -55,9 +55,9 @@ public:
required_device<generic_latch_8_device> m_soundlatch;
required_device<gfxdecode_device> m_gfxdecode;
required_device<palette_device> m_palette;
-
+
tilemap_t *m_sc_layer[4];
-
+
// screen updates
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
DECLARE_WRITE8_MEMBER(okim_rombank_w);
@@ -70,14 +70,14 @@ public:
TILE_GET_INFO_MEMBER(get_sc1_tileinfo);
TILE_GET_INFO_MEMBER(get_sc2_tileinfo);
TILE_GET_INFO_MEMBER(get_sc3_tileinfo);
-
+
protected:
// driver_device overrides
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
-
+
private:
void draw_sprites(screen_device &screen, bitmap_ind16 &bitmap,const rectangle &cliprect);
};
@@ -281,7 +281,7 @@ UINT32 seicupbl_state::screen_update( screen_device &screen, bitmap_ind16 &bitma
m_sc_layer[i]->set_scrollx(0, m_vregs[i*2+0] - 0x1f0);
m_sc_layer[i]->set_scrolly(0, m_vregs[i*2+1]);
}
-
+
/*if (!(m_layer_disable&0x0001)) */m_sc_layer[0]->draw(screen, bitmap, cliprect, 0, 0);
/*if (!(m_layer_disable&0x0002)) */m_sc_layer[1]->draw(screen, bitmap, cliprect, 0, 1);
/*if (!(m_layer_disable&0x0004)) */m_sc_layer[2]->draw(screen, bitmap, cliprect, 0, 2);
@@ -323,7 +323,7 @@ WRITE16_MEMBER(seicupbl_state::vram_sc3_w)
}
static ADDRESS_MAP_START( cupsocbl_mem, AS_PROGRAM, 16, seicupbl_state )
-// AM_IMPORT_FROM( legionna_cop_mem )
+// AM_IMPORT_FROM( legionna_cop_mem )
AM_RANGE(0x000000, 0x0fffff) AM_ROM
AM_RANGE(0x100400, 0x1005ff) AM_DEVREADWRITE("seibucop_boot", seibu_cop_bootleg_device, copdxbl_0_r,copdxbl_0_w) AM_SHARE("cop_mcu_ram")
AM_RANGE(0x100660, 0x10066f) AM_RAM AM_SHARE("vregs")
@@ -570,7 +570,7 @@ static MACHINE_CONFIG_START( cupsocbl, seicupbl_state )
MCFG_PALETTE_ADD_INIT_BLACK("palette", 128*16)
MCFG_PALETTE_FORMAT(xBBBBBGGGGGRRRRR)
-// MCFG_VIDEO_START_OVERRIDE(seicupbl_state,cupsoc)
+// MCFG_VIDEO_START_OVERRIDE(seicupbl_state,cupsoc)
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
diff --git a/src/mame/drivers/sliver.cpp b/src/mame/drivers/sliver.cpp
index 5faa1adb0f4..0762736ac24 100644
--- a/src/mame/drivers/sliver.cpp
+++ b/src/mame/drivers/sliver.cpp
@@ -138,7 +138,7 @@ public:
void sliver_state::machine_start()
{
membank("okibank")->configure_entries(0, 4, memregion("oki")->base() + 0x20000, 0x20000);
-
+
save_item(NAME(m_io_offset));
save_item(NAME(m_io_reg));
save_item(NAME(m_fifo));
@@ -401,7 +401,7 @@ void sliver_state::video_start()
save_item(NAME(m_jpeg2));
save_item(NAME(m_jpeg_x));
save_item(NAME(m_jpeg_y));
-
+
machine().save().register_postload(save_prepost_delegate(FUNC(sliver_state::postload), this));
}
diff --git a/src/mame/drivers/sm7238.cpp b/src/mame/drivers/sm7238.cpp
index 8d29c6baa3e..912a521d3ea 100644
--- a/src/mame/drivers/sm7238.cpp
+++ b/src/mame/drivers/sm7238.cpp
@@ -2,19 +2,19 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
- SM 7238 (aka T3300) color/mono text terminal, compatible with DEC VT 240.
- Graphics option adds Tek 401x and DEC ReGIS support on a 512x250 bitmap.
+ SM 7238 (aka T3300) color/mono text terminal, compatible with DEC VT 240.
+ Graphics option adds Tek 401x and DEC ReGIS support on a 512x250 bitmap.
- Technical manual and schematics: http://doc.pdp-11.org.ru/Terminals/CM7238/
+ Technical manual and schematics: http://doc.pdp-11.org.ru/Terminals/CM7238/
To do:
- - handle more text_control_w bits
- - more character attributes incl. double width and height, color
- - 80/132 columns switching on the fly, reverse video
+ - handle more text_control_w bits
+ - more character attributes incl. double width and height, color
+ - 80/132 columns switching on the fly, reverse video
- smooth scroll
- - graphics option
- - run vblank from timer output?
- - document hardware and ROM variants, verify if pixel stretching is done
+ - graphics option
+ - run vblank from timer output?
+ - document hardware and ROM variants, verify if pixel stretching is done
****************************************************************************/
@@ -29,7 +29,7 @@
#include "machine/km035.h"
#include "machine/nvram.h"
-#define KSM_COLUMNS 80 // or 132
+#define KSM_COLUMNS 80 // or 132
#define KSM_TOTAL_HORZ KSM_COLUMNS*10
#define KSM_DISP_HORZ KSM_COLUMNS*8
@@ -133,7 +133,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sm7238_io, AS_IO, 8, sm7238_state )
ADDRESS_MAP_UNMAP_HIGH
-// AM_RANGE (0x40, 0x4f) AM_RAM // LUT
+// AM_RANGE (0x40, 0x4f) AM_RAM // LUT
AM_RANGE (0xa0, 0xa0) AM_DEVREADWRITE("i8251line", i8251_device, data_r, data_w)
AM_RANGE (0xa1, 0xa1) AM_DEVREADWRITE("i8251line", i8251_device, status_r, control_w)
AM_RANGE (0xa4, 0xa4) AM_DEVREADWRITE("i8251kbd", i8251_device, data_r, data_w)
@@ -177,7 +177,7 @@ WRITE8_MEMBER(sm7238_state::text_control_w)
if (BIT((data ^ m_video.control), 0)) {
m_video.stride = BIT(data, 0) ? 80 : 132;
-// recompute_parameters();
+// recompute_parameters();
}
m_video.control = data;
@@ -295,7 +295,7 @@ void sm7238_state::recompute_parameters()
int horiz_pix_total = m_video.stride * 8;
visarea.set(0, horiz_pix_total - 1, 0, KSM_DISP_VERT - 1);
- machine().first_screen()->configure(horiz_pix_total, KSM_DISP_VERT, visarea,
+ machine().first_screen()->configure(horiz_pix_total, KSM_DISP_VERT, visarea,
HZ_TO_ATTOSECONDS((m_video.stride == 80) ? 60 : 57.1 ));
}
diff --git a/src/mame/drivers/sun4.cpp b/src/mame/drivers/sun4.cpp
index ecb44cc56f7..2fe04e67b6e 100644
--- a/src/mame/drivers/sun4.cpp
+++ b/src/mame/drivers/sun4.cpp
@@ -383,28 +383,28 @@
20/06/2016 Much less skeletony.
// sun4: 16 contexts, 4096 segments, each PMEG is 32 PTEs, each PTE is 8K
- // VA lower 13 bits in page, next 5 bits select PTE in PMEG, next 12 bits select PMEG, top 2 must be 00 or 11.
+ // VA lower 13 bits in page, next 5 bits select PTE in PMEG, next 12 bits select PMEG, top 2 must be 00 or 11.
4/60 ROM notes:
ffe809fc: call to print "Sizing Memory" to the UART
- ffe80a70: call to "Setting up RAM for monitor" that goes wrong
- ffe80210: testing memory
- ffe80274: loop that goes wobbly and fails
- ffe80dc4: switch off boot mode, MMU maps ROM to copy in RAM from here on
- ffe82000: start of FORTH (?) interpreter once decompressed
+ ffe80a70: call to "Setting up RAM for monitor" that goes wrong
+ ffe80210: testing memory
+ ffe80274: loop that goes wobbly and fails
+ ffe80dc4: switch off boot mode, MMU maps ROM to copy in RAM from here on
+ ffe82000: start of FORTH (?) interpreter once decompressed
text in decompressed area claims to be FORTH-83 FCode, but the opcodes
do not match the documented OpenFirmware FCode ones at all.
- 4/3xx ROM notes:
- sun4: CPU LEDs to 00 (PC=ffe92398) => ........
- sun4: CPU LEDs to 01 (PC=ffe92450) => *.......
- sun4: CPU LEDs to 02 (PC=ffe9246c) => .*......
- sun4: CPU LEDs to 03 (PC=ffe9aa54) => **......
- sun4: CPU LEDs to 04 (PC=ffe9aa54) => ..*.....
- sun4: CPU LEDs to 05 (PC=ffe9aa54) => *.*.....
- sun4: CPU LEDs to 06 (PC=ffe9aa54) => .**.....
- sun4: CPU LEDs to 07 (PC=ffe9aa54) => ***.....
+ 4/3xx ROM notes:
+ sun4: CPU LEDs to 00 (PC=ffe92398) => ........
+ sun4: CPU LEDs to 01 (PC=ffe92450) => *.......
+ sun4: CPU LEDs to 02 (PC=ffe9246c) => .*......
+ sun4: CPU LEDs to 03 (PC=ffe9aa54) => **......
+ sun4: CPU LEDs to 04 (PC=ffe9aa54) => ..*.....
+ sun4: CPU LEDs to 05 (PC=ffe9aa54) => *.*.....
+ sun4: CPU LEDs to 06 (PC=ffe9aa54) => .**.....
+ sun4: CPU LEDs to 07 (PC=ffe9aa54) => ***.....
****************************************************************************/
@@ -431,7 +431,7 @@
#include "debug/debugcmd.h"
#include "debugger.h"
-#define SUN4_LOG_FCODES (0)
+#define SUN4_LOG_FCODES (0)
#define TIMEKEEPER_TAG "timekpr"
#define SCC1_TAG "scc1"
@@ -439,56 +439,56 @@
#define KEYBOARD_TAG "keyboard"
#define RS232A_TAG "rs232a"
#define RS232B_TAG "rs232b"
-#define FDC_TAG "fdc"
+#define FDC_TAG "fdc"
-#define ENA_NOTBOOT (0x80)
-#define ENA_SDVMA (0x20)
-#define ENA_CACHE (0x10)
-#define ENA_RESET (0x04)
-#define ENA_DIAG (0x01)
+#define ENA_NOTBOOT (0x80)
+#define ENA_SDVMA (0x20)
+#define ENA_CACHE (0x10)
+#define ENA_RESET (0x04)
+#define ENA_DIAG (0x01)
// page table entry constants
-#define PM_VALID (0x80000000) // page is valid
-#define PM_WRITEMASK (0x40000000) // writable?
-#define PM_SYSMASK (0x20000000) // system use only?
-#define PM_CACHE (0x10000000) // cachable?
-#define PM_TYPEMASK (0x0c000000) // type mask
-#define PM_ACCESSED (0x02000000) // accessed flag
-#define PM_MODIFIED (0x01000000) // modified flag
+#define PM_VALID (0x80000000) // page is valid
+#define PM_WRITEMASK (0x40000000) // writable?
+#define PM_SYSMASK (0x20000000) // system use only?
+#define PM_CACHE (0x10000000) // cachable?
+#define PM_TYPEMASK (0x0c000000) // type mask
+#define PM_ACCESSED (0x02000000) // accessed flag
+#define PM_MODIFIED (0x01000000) // modified flag
-#define PAGE_SIZE (0x00000400)
+#define PAGE_SIZE (0x00000400)
// DMA controller constants
-#define DMA_DEV_ID (0x80000000)
-#define DMA_L (0x00008000) // use ILACC
-#define DMA_TC (0x00004000) // terminal count
-#define DMA_EN_CNT (0x00002000) // enable count
-#define DMA_BYTE_ADDR (0x00001800) // next byte number to be accessed
-#define DMA_BYTE_ADDR_SHIFT (11)
-#define DMA_REQ_PEND (0x00000400) // request pending
-#define DMA_EN_DMA (0x00000200) // enable DMA
-#define DMA_WRITE (0x00000100) // DMA device->mem if 1, otherwise mem->device
-#define DMA_RESET (0x00000080) // DMA hardware reset
-#define DMA_DRAIN (0x00000040) // force remaining pack bytes to memory
-#define DMA_FLUSH (0x00000020) // force PACK_CNT and ERR_PEND to 0
-#define DMA_INT_EN (0x00000010) // interrupt enable
-#define DMA_PACK_CNT (0x0000000c) // number of bytes in pack register
-#define DMA_PACK_CNT_SHIFT (2)
-#define DMA_ERR_PEND (0x00000002) // error pending, set when memory exception occurs
-#define DMA_INT_PEND (0x00000001) // interrupt pending, set when TC=1
-#define DMA_READ_ONLY (DMA_TC | DMA_BYTE_ADDR | DMA_REQ_PEND | DMA_PACK_CNT | DMA_ERR_PEND | DMA_INT_PEND)
-#define DMA_WRITE_ONLY (DMA_FLUSH)
-#define DMA_READ_WRITE (DMA_EN_CNT | DMA_EN_DMA | DMA_WRITE | DMA_RESET | DMA_INT_EN)
-#define DMA_CTRL (0)
-#define DMA_ADDR (1)
-#define DMA_BYTE_COUNT (2)
-#define DMA_XTAL (XTAL_25MHz)
+#define DMA_DEV_ID (0x80000000)
+#define DMA_L (0x00008000) // use ILACC
+#define DMA_TC (0x00004000) // terminal count
+#define DMA_EN_CNT (0x00002000) // enable count
+#define DMA_BYTE_ADDR (0x00001800) // next byte number to be accessed
+#define DMA_BYTE_ADDR_SHIFT (11)
+#define DMA_REQ_PEND (0x00000400) // request pending
+#define DMA_EN_DMA (0x00000200) // enable DMA
+#define DMA_WRITE (0x00000100) // DMA device->mem if 1, otherwise mem->device
+#define DMA_RESET (0x00000080) // DMA hardware reset
+#define DMA_DRAIN (0x00000040) // force remaining pack bytes to memory
+#define DMA_FLUSH (0x00000020) // force PACK_CNT and ERR_PEND to 0
+#define DMA_INT_EN (0x00000010) // interrupt enable
+#define DMA_PACK_CNT (0x0000000c) // number of bytes in pack register
+#define DMA_PACK_CNT_SHIFT (2)
+#define DMA_ERR_PEND (0x00000002) // error pending, set when memory exception occurs
+#define DMA_INT_PEND (0x00000001) // interrupt pending, set when TC=1
+#define DMA_READ_ONLY (DMA_TC | DMA_BYTE_ADDR | DMA_REQ_PEND | DMA_PACK_CNT | DMA_ERR_PEND | DMA_INT_PEND)
+#define DMA_WRITE_ONLY (DMA_FLUSH)
+#define DMA_READ_WRITE (DMA_EN_CNT | DMA_EN_DMA | DMA_WRITE | DMA_RESET | DMA_INT_EN)
+#define DMA_CTRL (0)
+#define DMA_ADDR (1)
+#define DMA_BYTE_COUNT (2)
+#define DMA_XTAL (XTAL_25MHz)
namespace
{
const sparc_disassembler::asi_desc_map::value_type sun4_asi_desc[] = {
- { 0x10, { nullptr, "Flush I-Cache (Segment)" } },
- { 0x11, { nullptr, "Flush I-Cache (Page)" } },
+ { 0x10, { nullptr, "Flush I-Cache (Segment)" } },
+ { 0x11, { nullptr, "Flush I-Cache (Page)" } },
{ 0x02, { nullptr, "System Space" } }, { 0x12, { nullptr, "Flush I-Cache (Context)" } },
{ 0x03, { nullptr, "Segment Map" } }, { 0x13, { nullptr, "Flush I-Cache (User)" } },
{ 0x04, { nullptr, "Page Map" } }, { 0x14, { nullptr, "Flush D-Cache (Segment)" } },
@@ -621,9 +621,9 @@ private:
UINT32 m_cachetags[0x4000];
UINT32 m_cachedata[0x4000];
UINT32 m_ram_size, m_ram_size_words;
- UINT8 m_ctx_mask; // SS2 is sun4c but has 16 contexts; most have 8
- UINT8 m_pmeg_mask; // SS2 is sun4c but has 16384 PTEs; most have 8192
- UINT8 m_irq_reg; // IRQ control
+ UINT8 m_ctx_mask; // SS2 is sun4c but has 16 contexts; most have 8
+ UINT8 m_pmeg_mask; // SS2 is sun4c but has 16384 PTEs; most have 8192
+ UINT8 m_irq_reg; // IRQ control
UINT8 m_scc1_int, m_scc2_int;
UINT8 m_diag;
int m_arch;
@@ -694,7 +694,7 @@ UINT32 sun4_state::read_insn_data_4c(UINT8 asi, address_space &space, UINT32 off
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read32(space, tmp, mem_mask);
case 1: // type 1 space
@@ -717,7 +717,7 @@ UINT32 sun4_state::read_insn_data_4c(UINT8 asi, address_space &space, UINT32 off
{
printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
- //m_buserr[0] = 0x88; // read, invalid PTE
+ //m_buserr[0] = 0x88; // read, invalid PTE
//m_buserr[1] = offset<<2;
}
return 0;
@@ -735,7 +735,7 @@ void sun4_state::write_insn_data_4c(UINT8 asi, address_space &space, UINT32 offs
if ((!(m_pagemap[entry] & PM_WRITEMASK)) || ((m_pagemap[entry] & PM_SYSMASK) && !(asi & 1)))
{
printf("sun4c: write protect MMU error (PC=%x)\n", m_maincpu->pc());
- m_buserr[0] = 0x8040; // write, protection error
+ m_buserr[0] = 0x8040; // write, protection error
m_buserr[1] = offset<<2;
m_maincpu->set_input_line(SPARC_MAE, ASSERT_LINE);
return;
@@ -750,7 +750,7 @@ void sun4_state::write_insn_data_4c(UINT8 asi, address_space &space, UINT32 offs
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write32(space, tmp, data, mem_mask);
return;
@@ -767,7 +767,7 @@ void sun4_state::write_insn_data_4c(UINT8 asi, address_space &space, UINT32 offs
{
printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
- //m_buserr[0] = 0x8; // invalid PTE
+ //m_buserr[0] = 0x8; // invalid PTE
//m_buserr[1] = offset<<2;
}
}
@@ -790,7 +790,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
switch (asi)
{
- case 2: // system space
+ case 2: // system space
switch (offset >> 26)
{
case 3: // context reg
@@ -804,7 +804,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
printf("sun4c: read buserror, PC=%x (mask %08x)\n", m_maincpu->pc(), mem_mask);
m_maincpu->set_input_line(SPARC_MAE, CLEAR_LINE);
retval = m_buserr[offset & 0xf];
- m_buserr[offset & 0xf] = 0; // clear on reading
+ m_buserr[offset & 0xf] = 0; // clear on reading
return retval;
case 8: // (d-)cache tags
@@ -815,7 +815,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
//logerror("sun4c: read dcache data @ %x, PC = %x\n", offset, m_maincpu->pc());
return m_cachedata[offset&0x3fff];
- case 0xf: // UART bypass
+ case 0xf: // UART bypass
//printf("read UART bypass @ %x mask %08x\n", offset<<2, mem_mask);
switch (offset & 3)
{
@@ -830,7 +830,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
return 0;
}
break;
- case 3: // segment map
+ case 3: // segment map
//printf("sun4: read segment map @ %x (ctx %d entry %d, mem_mask %08x, PC=%x)\n", offset << 2, m_context & m_ctx_mask, (offset>>16) & 0xfff, mem_mask, m_maincpu->pc());
if (mem_mask == 0xffff0000)
{
@@ -842,7 +842,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
}
else
{
- // printf("sun4: read segment map w/unk mask %08x\n", mem_mask);
+ // printf("sun4: read segment map w/unk mask %08x\n", mem_mask);
}
return 0x0;
@@ -918,7 +918,7 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w )
m_cachedata[offset&0x3fff] = data;
return;
- case 0xf: // UART bypass
+ case 0xf: // UART bypass
//printf("%08x to UART bypass @ %x, mask %08x\n", data, offset<<2, mem_mask);
switch (offset & 3)
{
@@ -942,16 +942,16 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w )
else logerror("sun4c: writing segment map with unknown mask %08x, PC=%x\n", mem_mask, m_maincpu->pc());
//printf("sun4: %08x to segment map @ %x (ctx %d entry %d, mem_mask %08x, PC=%x)\n", segdata, offset << 2, m_context, (offset>>16) & 0xfff, mem_mask, m_maincpu->pc());
- m_segmap[m_context & m_ctx_mask][(offset>>16) & 0xfff] = segdata; // only 7 bits of the segment are necessary
+ m_segmap[m_context & m_ctx_mask][(offset>>16) & 0xfff] = segdata; // only 7 bits of the segment are necessary
}
return;
case 4: // page map
- page = (m_segmap[m_context & m_ctx_mask][(offset >> 16) & 0xfff] & m_pmeg_mask) << 6; // get the PMEG
- page += (offset >> 10) & 0x3f; // add the offset
+ page = (m_segmap[m_context & m_ctx_mask][(offset >> 16) & 0xfff] & m_pmeg_mask) << 6; // get the PMEG
+ page += (offset >> 10) & 0x3f; // add the offset
//printf("sun4: %08x to page map @ %x (entry %d, mem_mask %08x, PC=%x)\n", data, offset << 2, page, mem_mask, m_maincpu->pc());
COMBINE_DATA(&m_pagemap[page]);
- m_pagemap[page] &= 0xff00ffff; // these 8 bits are cleared when written and tested as such
+ m_pagemap[page] &= 0xff00ffff; // these 8 bits are cleared when written and tested as such
return;
case 8:
@@ -985,7 +985,7 @@ UINT32 sun4_state::read_insn_data(UINT8 asi, address_space &space, UINT32 offset
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read32(space, tmp, mem_mask);
case 1: // type 1 space
@@ -1008,7 +1008,7 @@ UINT32 sun4_state::read_insn_data(UINT8 asi, address_space &space, UINT32 offset
{
printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
- //m_buserr[0] = 0x88; // read, invalid PTE
+ //m_buserr[0] = 0x88; // read, invalid PTE
//m_buserr[1] = offset<<2;
}
return 0;
@@ -1032,7 +1032,7 @@ void sun4_state::write_insn_data(UINT8 asi, address_space &space, UINT32 offset,
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write32(space, tmp, data, mem_mask);
return;
@@ -1050,7 +1050,7 @@ void sun4_state::write_insn_data(UINT8 asi, address_space &space, UINT32 offset,
{
printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
- //m_buserr[0] = 0x8; // invalid PTE
+ //m_buserr[0] = 0x8; // invalid PTE
//m_buserr[1] = offset<<2;
}
}
@@ -1071,7 +1071,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
switch (asi)
{
- case 2: // system space
+ case 2: // system space
switch (offset >> 26)
{
case 3: // context reg
@@ -1093,7 +1093,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
logerror("sun4: read dcache data @ %x, PC = %x\n", offset, m_maincpu->pc());
return 0xffffffff;
- case 0xf: // UART bypass
+ case 0xf: // UART bypass
//printf("read UART bypass @ %x mask %08x (PC=%x)\n", offset<<2, mem_mask, m_maincpu->pc());
switch (offset & 3)
{
@@ -1108,7 +1108,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
return 0;
}
break;
- case 3: // segment map
+ case 3: // segment map
//printf("sun4: read segment map @ %x (ctx %d entry %d, mem_mask %08x, PC=%x)\n", offset << 2, m_context & m_ctx_mask, (offset>>16) & 0xfff, mem_mask, m_maincpu->pc());
if (mem_mask == 0xffff0000)
{
@@ -1120,7 +1120,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
}
else
{
- // printf("sun4: read segment map w/unk mask %08x\n", mem_mask);
+ // printf("sun4: read segment map w/unk mask %08x\n", mem_mask);
}
return 0x0;
@@ -1130,7 +1130,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
//printf("sun4: read page map @ %x (entry %d, seg %d, PMEG %d, mem_mask %08x, PC=%x)\n", offset << 2, page, (offset >> 16) & 0xfff, m_segmap[m_context & m_ctx_mask][(offset >> 16) & 0xfff] & m_pmeg_mask, mem_mask, m_maincpu->pc());
return m_pagemap[page];
- case 6: // region map used in 4/4xx, I don't know anything about this
+ case 6: // region map used in 4/4xx, I don't know anything about this
return 0;
case 8:
@@ -1183,7 +1183,7 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
}
return;
- case 7: // diag reg
+ case 7: // diag reg
m_diag = data >> 24;
#if 1
printf("sun4: CPU LEDs to %02x (PC=%x) => ", ((data>>24) & 0xff) ^ 0xff, m_maincpu->pc());
@@ -1211,7 +1211,7 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
logerror("sun4: %08x to cache data @ %x, PC = %x\n", data, offset, m_maincpu->pc());
return;
- case 0xf: // UART bypass
+ case 0xf: // UART bypass
//printf("%08x to UART bypass @ %x, mask %08x\n", data, offset<<2, mem_mask);
switch (offset & 3)
{
@@ -1240,11 +1240,11 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
return;
case 4: // page map
- page = (m_segmap[m_context][(offset >> 16) & 0xfff]) << 5; // get the PMEG
- page += (offset >> 11) & 0x1f; // add the offset
+ page = (m_segmap[m_context][(offset >> 16) & 0xfff]) << 5; // get the PMEG
+ page += (offset >> 11) & 0x1f; // add the offset
//printf("sun4: %08x to page map @ %x (entry %d, mem_mask %08x, PC=%x)\n", data, offset << 2, page, mem_mask, m_maincpu->pc());
COMBINE_DATA(&m_pagemap[page]);
- m_pagemap[page] &= 0xff07ffff; // these bits are cleared when written and tested as such
+ m_pagemap[page] &= 0xff07ffff; // these bits are cleared when written and tested as such
return;
case 6: // region map, used in 4/4xx
@@ -1464,10 +1464,10 @@ static ADDRESS_MAP_START(type1space_map, AS_PROGRAM, 32, sun4_state)
AM_RANGE(0x05000000, 0x05000003) AM_READWRITE8(irq_r, irq_w, 0xffffffff)
AM_RANGE(0x06000000, 0x0607ffff) AM_ROM AM_REGION("user1", 0)
AM_RANGE(0x07200000, 0x07200003) AM_READWRITE8(fdc_r, fdc_w, 0xffffffff)
- AM_RANGE(0x08000000, 0x08000003) AM_READ(ss1_sl0_id) // slot 0 contains SCSI/DMA/Ethernet
+ AM_RANGE(0x08000000, 0x08000003) AM_READ(ss1_sl0_id) // slot 0 contains SCSI/DMA/Ethernet
AM_RANGE(0x08400000, 0x0840000f) AM_READWRITE(dma_r, dma_w)
AM_RANGE(0x08800000, 0x0880001f) AM_DEVICE8("scsibus:7:ncr5390", ncr5390_device, map, 0xff0000)
- AM_RANGE(0x0e000000, 0x0e000003) AM_READ(ss1_sl3_id) // slot 3 contains video board
+ AM_RANGE(0x0e000000, 0x0e000003) AM_READ(ss1_sl3_id) // slot 3 contains video board
AM_RANGE(0x0e800000, 0x0e8fffff) AM_RAM AM_SHARE("bw2_vram")
ADDRESS_MAP_END
@@ -2350,7 +2350,7 @@ COMP( 1991, sun4_50, sun4_300,0, sun4c, sun4, sun4_state, ss2,
COMP( 199?, sun4_20, sun4_300,0, sun4c, sun4, sun4_state, sun4c, "Sun Microsystems", "SPARCstation SLC (Sun 4/20)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)
COMP( 1989, sun4_60, sun4_300,0, sun4c, sun4, sun4_state, sun4c, "Sun Microsystems", "SPARCstation 1 (Sun 4/60)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)
COMP( 1990, sun4_65, sun4_300,0, sun4c, sun4, sun4_state, sun4c, "Sun Microsystems", "SPARCstation 1+ (Sun 4/65)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)
-COMP( 1990, sun4_75, sun4_300,0, sun4c, sun4, sun4_state, ss2, "Sun Microsystems", "SPARCstation 2 (Sun 4/75)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)
+COMP( 1990, sun4_75, sun4_300,0, sun4c, sun4, sun4_state, ss2, "Sun Microsystems", "SPARCstation 2 (Sun 4/75)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)
// sun4m (using the SPARC "reference MMU", probably will go to a separate driver)
COMP( 1992, sun_s10, sun4_300,0, sun4c, sun4, sun4_state, sun4c, "Sun Microsystems", "SPARCstation 10 (Sun S10)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)
diff --git a/src/mame/drivers/tiamc1.cpp b/src/mame/drivers/tiamc1.cpp
index 77449e61fc1..7b59b5be424 100644
--- a/src/mame/drivers/tiamc1.cpp
+++ b/src/mame/drivers/tiamc1.cpp
@@ -12,8 +12,8 @@
* Konek-Gorbunok (Little Humpbacked Horse)
* Snezhnaja Koroleva (Snow Queen)
* S.O.S.
- * Gorodki
- * Kot-Rybolov
+ * Gorodki
+ * Kot-Rybolov
Other games known to exist on this hardware (interchangeable by the ROM swap):
* Avtogonki
@@ -114,7 +114,7 @@
- Check sprites priorities on the real hardware
- Check vertical background scrolling on the real hardware
- What charset control is used for?
- - Kot Rybolov viewable area size likely controlled by pit8253 timers 0 and 1, used in test mode only
+ - Kot Rybolov viewable area size likely controlled by pit8253 timers 0 and 1, used in test mode only
*/
@@ -177,14 +177,14 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( kotrybolov_io_map, AS_IO, 8, tiamc1_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
- AM_RANGE(0x00, 0x0f) AM_WRITE(tiamc1_sprite_y_w) // sprites Y
- AM_RANGE(0x10, 0x1f) AM_WRITE(tiamc1_sprite_x_w) // sprites X
- AM_RANGE(0x20, 0x2f) AM_WRITE(tiamc1_sprite_n_w) // sprites #
- AM_RANGE(0x30, 0x3f) AM_WRITE(tiamc1_sprite_a_w) // sprites attributes
- AM_RANGE(0xe0, 0xef) AM_WRITE(tiamc1_palette_w) // color ram
- AM_RANGE(0xf0, 0xf0) AM_WRITE(tiamc1_bg_vshift_w) // background V scroll
- AM_RANGE(0xf4, 0xf4) AM_WRITE(tiamc1_bg_hshift_w) // background H scroll
- AM_RANGE(0xf8, 0xf8) AM_WRITE(kot_bankswitch_w) // character rom offset
+ AM_RANGE(0x00, 0x0f) AM_WRITE(tiamc1_sprite_y_w) // sprites Y
+ AM_RANGE(0x10, 0x1f) AM_WRITE(tiamc1_sprite_x_w) // sprites X
+ AM_RANGE(0x20, 0x2f) AM_WRITE(tiamc1_sprite_n_w) // sprites #
+ AM_RANGE(0x30, 0x3f) AM_WRITE(tiamc1_sprite_a_w) // sprites attributes
+ AM_RANGE(0xe0, 0xef) AM_WRITE(tiamc1_palette_w) // color ram
+ AM_RANGE(0xf0, 0xf0) AM_WRITE(tiamc1_bg_vshift_w) // background V scroll
+ AM_RANGE(0xf4, 0xf4) AM_WRITE(tiamc1_bg_hshift_w) // background H scroll
+ AM_RANGE(0xf8, 0xf8) AM_WRITE(kot_bankswitch_w) // character rom offset
AM_RANGE(0xc0, 0xc3) AM_DEVREADWRITE("pit8253", pit8253_device, read, write)
AM_RANGE(0xd0, 0xd3) AM_DEVREADWRITE("kr580vv55a", i8255_device, read, write) /* input ports + coin counters & lockout */
ADDRESS_MAP_END
@@ -269,7 +269,7 @@ static INPUT_PORTS_START( kot )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* RAZR ??? */
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) // Punch / Right
- PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) // Kick / Left
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) // Kick / Left
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen")
INPUT_PORTS_END
@@ -332,7 +332,7 @@ static MACHINE_CONFIG_START( tiamc1, tiamc1_state )
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
- MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, 336, 0, 256, 312, 0, 256) // pixel clock and htotal comes from docs/schematics, the rest is guess (determined by undumped PROM)
+ MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, 336, 0, 256, 312, 0, 256) // pixel clock and htotal comes from docs/schematics, the rest is guess (determined by undumped PROM)
MCFG_SCREEN_UPDATE_DRIVER(tiamc1_state, screen_update_tiamc1)
MCFG_SCREEN_PALETTE("palette")
@@ -364,7 +364,7 @@ static MACHINE_CONFIG_DERIVED(kot, tiamc1)
MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
MCFG_PIT8253_CLK0(PIXEL_CLOCK / 4)
- MCFG_PIT8253_CLK2(SND_CLOCK) // guess
+ MCFG_PIT8253_CLK2(SND_CLOCK) // guess
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tiamc1_state, pit8253_2_w))
MACHINE_CONFIG_END
@@ -526,13 +526,13 @@ ROM_START( kot )
ROM_LOAD( "856.8", 0x04000, 0x2000, CRC(9180c98f) SHA1(4085180b9e9772e965c487e7b02d88fcae973e87) )
ROM_REGION( 0x8000, "gfx1", 0 )
- ROM_LOAD( "850.5", 0x00000, 0x2000, CRC(5dc3a102) SHA1(e97d219f7004291438b991435b7fe5d5be01d468) ) // sprite gfx
+ ROM_LOAD( "850.5", 0x00000, 0x2000, CRC(5dc3a102) SHA1(e97d219f7004291438b991435b7fe5d5be01d468) ) // sprite gfx
ROM_LOAD( "851.6", 0x02000, 0x2000, CRC(7db239a0) SHA1(af5772afff9009f63e2ab95c1cb00e047f3ed7e4) )
ROM_LOAD( "852.7", 0x04000, 0x2000, CRC(c7700f88) SHA1(1a20cc60b083259070e4f1687b09a31fc763d47e) )
ROM_LOAD( "853.8", 0x06000, 0x2000, CRC(b94bf1af) SHA1(da403c51fd78f99b82304c67f2197078f4ea0bf5) )
ROM_REGION( 0x8000, "gfx2", 0 )
- ROM_LOAD( "846.1", 0x00000, 0x2000, CRC(42447f4a) SHA1(bd35f2f5e468f9191680bf2c1800e09bb9ae1691) ) // tile gfx
+ ROM_LOAD( "846.1", 0x00000, 0x2000, CRC(42447f4a) SHA1(bd35f2f5e468f9191680bf2c1800e09bb9ae1691) ) // tile gfx
ROM_LOAD( "847.2", 0x02000, 0x2000, CRC(99ada5e8) SHA1(9425a515105ec9e9989aae736645b270e39420be) )
ROM_LOAD( "848.3", 0x04000, 0x2000, CRC(a124cff4) SHA1(d1d8e6f725a6f30058d52cdbe80b598149cd6052) )
ROM_LOAD( "849.4", 0x06000, 0x2000, CRC(5d27fda6) SHA1(f1afb39c7422caaa5eff53388f1b7241dd7c1cd7) )
diff --git a/src/mame/drivers/tv990.cpp b/src/mame/drivers/tv990.cpp
index 544765f2086..4f1b7b163c9 100644
--- a/src/mame/drivers/tv990.cpp
+++ b/src/mame/drivers/tv990.cpp
@@ -3,10 +3,10 @@
/***************************************************************************
TeleVideo 990/995 terminal
-
+
Driver by Carl and R. Belmont
Thanks to Al Kossow.
-
+
H/W:
68000-P16 CPU (clock unknown, above 10 MHz it outruns the AT keyboard controller)
16C452 dual 16450 (PC/AT standard) UART + PC-compatible Centronics (integrated into
@@ -14,7 +14,7 @@
AMI MEGA-KBD-H-Q PS/2 keyboard interface on 990, PS/2 8042 on 995
Televideo ASIC marked "134446-00 TVI1111-0 427"
3x AS7C256 (32K x 8 SRAM)
-
+
IRQs:
2 = PS/2 keyboard
3 = Centronics
@@ -24,7 +24,7 @@
Video modes include 80 or 132 wide by 24, 25, 42, 43, 48, or 49 lines high plus an
optional status bar
- Modes include TeleVideo 990, 950, and 955, Wyse WY-60, WY-150/120/50+/50, ANSI,
+ Modes include TeleVideo 990, 950, and 955, Wyse WY-60, WY-150/120/50+/50, ANSI,
DEC VT320/220, VT100/52, SCO Console, and PC TERM.
****************************************************************************/
@@ -37,8 +37,8 @@
#include "machine/nvram.h"
#include "sound/beep.h"
-#define UART0_TAG "ns16450_0"
-#define UART1_TAG "ns16450_1"
+#define UART0_TAG "ns16450_0"
+#define UART1_TAG "ns16450_1"
#define RS232A_TAG "rs232a"
#define RS232B_TAG "rs232b"
@@ -71,14 +71,14 @@ public:
virtual void machine_reset() override;
virtual void machine_start() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
-
+
UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
-
+
DECLARE_READ16_MEMBER(tvi1111_r);
DECLARE_WRITE16_MEMBER(tvi1111_w);
DECLARE_READ8_MEMBER(kbdc_r);
DECLARE_WRITE8_MEMBER(kbdc_w);
-
+
WRITE_LINE_MEMBER(uart0_irq);
WRITE_LINE_MEMBER(uart1_irq);
@@ -100,7 +100,7 @@ INTERRUPT_GEN_MEMBER(tv990_state::vblank)
void tv990_state::machine_start()
{
m_rowtimer = timer_alloc();
-
+
save_item(NAME(tvi1111_regs));
save_item(NAME(m_rowh));
save_item(NAME(m_width));
@@ -128,7 +128,7 @@ READ16_MEMBER(tv990_state::tvi1111_r)
{
if (offset == (0x32/2))
{
- tvi1111_regs[offset] |= 8; // loop at 109ca wants this set
+ tvi1111_regs[offset] |= 8; // loop at 109ca wants this set
}
else if(offset == 0x1d)
{
@@ -230,7 +230,7 @@ UINT32 tv990_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, c
attr ^= attrchg;
}
- if (attr & 0x4) // inverse video?
+ if (attr & 0x4) // inverse video?
{
palette[1] = m_palette->pen(0);
palette[0] = (attr & 0x10) ? m_palette->pen(1) : m_palette->pen(2);
@@ -295,13 +295,13 @@ WRITE8_MEMBER(tv990_state::kbdc_w)
static ADDRESS_MAP_START(tv990_mem, AS_PROGRAM, 16, tv990_state)
AM_RANGE(0x000000, 0x03ffff) AM_ROM AM_REGION("maincpu", 0)
- AM_RANGE(0x060000, 0x06ffff) AM_RAM AM_SHARE("vram") // character/attribute RAM
- AM_RANGE(0X080000, 0X087fff) AM_RAM AM_SHARE("fontram") // font RAM
+ AM_RANGE(0x060000, 0x06ffff) AM_RAM AM_SHARE("vram") // character/attribute RAM
+ AM_RANGE(0X080000, 0X087fff) AM_RAM AM_SHARE("fontram") // font RAM
AM_RANGE(0x090000, 0x0900ff) AM_READWRITE(tvi1111_r, tvi1111_w)
AM_RANGE(0x0a0000, 0x0a000f) AM_DEVREADWRITE8(UART0_TAG, ns16450_device, ins8250_r, ins8250_w, 0x00ff)
AM_RANGE(0x0a0010, 0x0a001f) AM_DEVREADWRITE8(UART1_TAG, ns16450_device, ins8250_r, ins8250_w, 0x00ff)
AM_RANGE(0x0b0000, 0x0b0003) AM_READWRITE8(kbdc_r, kbdc_w, 0x00ff)
- AM_RANGE(0x0c0000, 0x0c7fff) AM_RAM AM_SHARE("nvram")// work RAM
+ AM_RANGE(0x0c0000, 0x0c7fff) AM_RAM AM_SHARE("nvram")// work RAM
ADDRESS_MAP_END
/* Input ports */
@@ -339,7 +339,7 @@ INPUT_CHANGED_MEMBER(tv990_state::color)
void tv990_state::machine_reset()
{
m_rowtimer->adjust(m_screen->time_until_pos(0));
-
+
memset(tvi1111_regs, 0, sizeof(tvi1111_regs));
m_rowh = 16;
m_width = 80;
@@ -348,10 +348,10 @@ void tv990_state::machine_reset()
static MACHINE_CONFIG_START( tv990, tv990_state )
/* basic machine hardware */
- MCFG_CPU_ADD("maincpu", M68000, 14967500) // verified (59.86992/4)
+ MCFG_CPU_ADD("maincpu", M68000, 14967500) // verified (59.86992/4)
MCFG_CPU_PROGRAM_MAP(tv990_mem)
MCFG_CPU_VBLANK_INT_DRIVER("screen", tv990_state, vblank)
-
+
MCFG_SCREEN_ADD_MONOCHROME("screen", RASTER, rgb_t::green)
MCFG_SCREEN_UPDATE_DRIVER(tv990_state, screen_update)
MCFG_SCREEN_SIZE(132*16, 50*16)
@@ -380,7 +380,7 @@ static MACHINE_CONFIG_START( tv990, tv990_state )
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(UART1_TAG, ns16450_device, rx_w))
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(UART1_TAG, ns16450_device, dcd_w))
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(UART1_TAG, ns16450_device, cts_w))
-
+
MCFG_DEVICE_ADD("pc_kbdc", KBDC8042, 0)
MCFG_KBDC8042_KEYBOARD_TYPE(KBDC8042_AT386)
MCFG_KBDC8042_INPUT_BUFFER_FULL_CB(INPUTLINE("maincpu", M68K_IRQ_2))
@@ -395,14 +395,14 @@ MACHINE_CONFIG_END
/* ROM definition */
ROM_START( tv990 )
ROM_REGION( 0x40000, "maincpu", 0 )
- ROM_LOAD16_BYTE( "180003-89_u3.bin", 0x000000, 0x010000, CRC(0465fc55) SHA1(b8874ce54bf2bf4f77664194d2f23c0e4e6ccbe9) )
- ROM_LOAD16_BYTE( "180003-90_u4.bin", 0x000001, 0x010000, CRC(fad7d77d) SHA1(f1114a4a07c8b4ffa0323a2e7ce03d82a386f7d3) )
+ ROM_LOAD16_BYTE( "180003-89_u3.bin", 0x000000, 0x010000, CRC(0465fc55) SHA1(b8874ce54bf2bf4f77664194d2f23c0e4e6ccbe9) )
+ ROM_LOAD16_BYTE( "180003-90_u4.bin", 0x000001, 0x010000, CRC(fad7d77d) SHA1(f1114a4a07c8b4ffa0323a2e7ce03d82a386f7d3) )
ROM_END
ROM_START( tv995 )
ROM_REGION( 0x40000, "maincpu", 0 )
- ROM_LOAD16_BYTE( "995-65_u3.bin", 0x000000, 0x020000, CRC(2d71b6fe) SHA1(a2a3406c19308eb9232db319ea8f151949b2ac74) )
- ROM_LOAD16_BYTE( "995-65_u4.bin", 0x000001, 0x020000, CRC(dc002af2) SHA1(9608e7a729c5ac0fc58f673eaf441d2f4f591ec6) )
+ ROM_LOAD16_BYTE( "995-65_u3.bin", 0x000000, 0x020000, CRC(2d71b6fe) SHA1(a2a3406c19308eb9232db319ea8f151949b2ac74) )
+ ROM_LOAD16_BYTE( "995-65_u4.bin", 0x000001, 0x020000, CRC(dc002af2) SHA1(9608e7a729c5ac0fc58f673eaf441d2f4f591ec6) )
ROM_END
/* Driver */
diff --git a/src/mame/includes/bfm_sc4.h b/src/mame/includes/bfm_sc4.h
index 909325ea1ed..def6c17254a 100644
--- a/src/mame/includes/bfm_sc4.h
+++ b/src/mame/includes/bfm_sc4.h
@@ -59,19 +59,19 @@
#define SC45_BUTTON_MATRIX_20_0 IPT_SERVICE1 // green / test
-static const UINT8 SEGMENT_34_ENCODING_LOOKUP[16] =
+static const UINT8 SEGMENT_34_ENCODING_LOOKUP[16] =
{
- 63, // 0
- 6, // 1
- 91, // 2
- 79, // 3
+ 63, // 0
+ 6, // 1
+ 91, // 2
+ 79, // 3
102,// 4
109,// 5
125,// 6
- 7, // 7
+ 7, // 7
127,// 8
103,// 9
- 0, // 10
+ 0, // 10
121,// 11
121,// 12
121,// 13
diff --git a/src/mame/includes/legionna.h b/src/mame/includes/legionna.h
index 78c95cc17c8..068571f2a72 100644
--- a/src/mame/includes/legionna.h
+++ b/src/mame/includes/legionna.h
@@ -96,4 +96,3 @@ public:
required_device<palette_device> m_palette;
optional_device<raiden2cop_device> m_raiden2cop;
};
-
diff --git a/src/mame/includes/vendetta.h b/src/mame/includes/vendetta.h
index 497db3c2886..b68c15c214b 100644
--- a/src/mame/includes/vendetta.h
+++ b/src/mame/includes/vendetta.h
@@ -34,7 +34,7 @@ public:
m_videobank0(*this, "videobank0"),
m_videobank1(*this, "videobank1") { }
-
+
/* video-related */
int m_layer_colorbase[3];
int m_sprite_colorbase;
diff --git a/src/mame/machine/archimds.cpp b/src/mame/machine/archimds.cpp
index f451db8993e..b22ef889e37 100644
--- a/src/mame/machine/archimds.cpp
+++ b/src/mame/machine/archimds.cpp
@@ -71,7 +71,7 @@ void archimedes_state::archimedes_request_fiq(int mask)
m_ioc_regs[FIQ_STATUS] |= mask;
//printf("STATUS:%02x IRQ:%02x MASK:%02x\n",m_ioc_regs[FIQ_STATUS],mask,m_ioc_regs[FIQ_MASK]);
-
+
if (m_ioc_regs[FIQ_STATUS] & m_ioc_regs[FIQ_MASK])
{
generic_pulse_irq_line(m_maincpu, ARM_FIRQ_LINE, 1);
diff --git a/src/mame/machine/opwolf.cpp b/src/mame/machine/opwolf.cpp
index 9bb86e05f0c..5f738556857 100644
--- a/src/mame/machine/opwolf.cpp
+++ b/src/mame/machine/opwolf.cpp
@@ -95,11 +95,11 @@
Bootleg doesn't support service switch
If you die after round 6 then the bootleg fails to reset the difficulty
for the next game.
- The bootleg does not contain data for the 3 mini-levels ('Enemy has located you'),
- instead it prevents them running by writing 0 to location 70 in the shared memory.
- The bootleg does not play the special powder magazine (level 4) animation.
- The bootleg does not vertically scroll the screen when all men killed in level 5
- The bootleg does not update the enemy spawn tables at various points.
+ The bootleg does not contain data for the 3 mini-levels ('Enemy has located you'),
+ instead it prevents them running by writing 0 to location 70 in the shared memory.
+ The bootleg does not play the special powder magazine (level 4) animation.
+ The bootleg does not vertically scroll the screen when all men killed in level 5
+ The bootleg does not update the enemy spawn tables at various points.
Notes by bmcphail@vcmame.net
@@ -645,11 +645,11 @@ WRITE16_MEMBER(opwolf_state::opwolf_cchip_data_w)
{
//int logValue=1;
//if (offset==0x1c && offset==0x1d && offset==0x1e && offset==0x1f && offset==0x20) // Enemies, tanks, choppers, boats
- // logValue=0;
+ // logValue=0;
//if (offset==0x50 && offset==0x51 && offset==0x52 && offset==0x53) // Coins
- // logValue=0;
+ // logValue=0;
//if (logValue)
- // logerror("%08x: opwolf 68K writes c-chip %02x at %04x/%04x (bank %04x)\n", space.device().safe_pc(), data & 0xff, offset*2, offset, m_current_bank);
+ // logerror("%08x: opwolf 68K writes c-chip %02x at %04x/%04x (bank %04x)\n", space.device().safe_pc(), data & 0xff, offset*2, offset, m_current_bank);
m_cchip_ram[(m_current_bank * 0x400) + offset] = data & 0xff;
@@ -756,13 +756,13 @@ READ16_MEMBER(opwolf_state::opwolf_cchip_data_r)
//int logValue=1;
//if (offset==0x1c || offset==0x1d || offset==0x1e || offset==0x1f || offset==0x20) // Enemies, tanks, choppers, boats
- // logValue=0;
+ // logValue=0;
//if (offset==0x50 || offset==0x51 || offset==0x52 || offset==0x53) // Coins
- // logValue=0;
+ // logValue=0;
//if (space.device().safe_pc()==0xc18 && space.device().safe_pc()!=0xc2e && space.device().safe_pc()!=0xc9e)
- // logValue=0;
+ // logValue=0;
//if (logValue)
- // logerror("%08x: opwolf 68K reads c-chip at %04x/%04x (bank %04x)\n", space.device().safe_pc(), offset*2, offset, m_current_bank);
+ // logerror("%08x: opwolf 68K reads c-chip at %04x/%04x (bank %04x)\n", space.device().safe_pc(), offset*2, offset, m_current_bank);
return m_cchip_ram[(m_current_bank * 0x400) + offset];
}
@@ -782,7 +782,7 @@ TIMER_CALLBACK_MEMBER(opwolf_state::cchip_timer)
// Dev Cheat - kill all enemeies
//if ((ioport("IN1")->read()&0x10)!=0x10)
//{
- // m_cchip_ram[0x1c] = m_cchip_ram[0x1d] = m_cchip_ram[0x1e] = m_cchip_ram[0x1f] = m_cchip_ram[0x20] = 0;
+ // m_cchip_ram[0x1c] = m_cchip_ram[0x1d] = m_cchip_ram[0x1e] = m_cchip_ram[0x1f] = m_cchip_ram[0x20] = 0;
//}
// Coin slots
@@ -888,7 +888,7 @@ TIMER_CALLBACK_MEMBER(opwolf_state::cchip_timer)
// When level 4 (powder magazine) is complete the c-chip triggers an explosion animation.
if (m_triggeredLevel4==0 && m_cchip_ram[0x5f]==0) // Don't write unless 68K is ready (0 at 0x5f))
- {
+ {
m_cchip_ram[0x5f]=10;
m_triggeredLevel4=1;
}
diff --git a/src/mame/machine/seibucop/seibucop.cpp b/src/mame/machine/seibucop/seibucop.cpp
index 72594e43513..280093b0835 100644
--- a/src/mame/machine/seibucop/seibucop.cpp
+++ b/src/mame/machine/seibucop/seibucop.cpp
@@ -49,18 +49,18 @@
- stage 4: has sprite stuck on bottom-left of screen;
- palette dims too much on attract / continue screen.
It's known that the DMA data arrangement gives same results on a real Legionnaire board, so shrug?
- Seibu Cup Soccer
- - Handles collision detection via the 130e/3bb0 macros
- 130e version in this makes a sub instead of an add as last opcode, which in turn reflects with
- the distance (which we do know that is internally loaded somehow).
+ Seibu Cup Soccer
+ - Handles collision detection via the 130e/3bb0 macros
+ 130e version in this makes a sub instead of an add as last opcode, which in turn reflects with
+ the distance (which we do know that is internally loaded somehow).
d104 macro is called before this, it likely sets the range for the 130e snippets.
Example snippet (note: there are multiple calls to 130e)
013F3C: 3D7C 130E 0100 move.w #$130e, ($100,A6) // angle macro
013F42: 302E 01B4 move.w ($1b4,A6), D0 // take the angle
013F46: 082E 000F 01B0 btst #$f, ($1b0,A6) // is status exception flag raised?
013F4C: 6712 beq $13f60
-013F4E: 2228 0004 move.l ($4,A0), D1
-013F52: B2A8 0044 cmp.l ($44,A0), D1 // compares Y value against the next object (yes, cop_regs[1] + 0x40 = cop_regs[0])
+013F4E: 2228 0004 move.l ($4,A0), D1
+013F52: B2A8 0044 cmp.l ($44,A0), D1 // compares Y value against the next object (yes, cop_regs[1] + 0x40 = cop_regs[0])
013F56: 6708 beq $13f60 // if equal then check the distance
013F58: 6E04 bgt $13f5e
013F5A: 7040 moveq #$40, D0 // set angle direction left ...
@@ -69,12 +69,12 @@
013F60: 3D7C 3BB0 0100 move.w #$3bb0, ($100,A6) // dist macro
013F66: 1140 003D move.b D0, ($3d,A0) // move angle value to [0x3d]
013F6A: 4E75 rts
- Zero Team
- - Some faulty collision detection, e.g. crate in front of aquarium in stage 1
- - Bird Boss jumps to wrong direction
- the sequence called is:
- write to reg 4 then execute 0xfc84 and 0xf790, finally reads the distance.
-
+ Zero Team
+ - Some faulty collision detection, e.g. crate in front of aquarium in stage 1
+ - Bird Boss jumps to wrong direction
+ the sequence called is:
+ write to reg 4 then execute 0xfc84 and 0xf790, finally reads the distance.
+
Tech notes (to move into own file with doxy mainpage):
-----------
[0x6fc] DMA mode bit scheme:
@@ -83,16 +83,16 @@
---- ---- ---x ---- internal buffer selector
---- ---- ---- x--- size modifier? Bus transfer size actually?
---- ---- ---- -xxx select channel
-
- work RAM object structure (in seibu cup soccer)
- all object have a [0x40] boundary
- [0x04-0x07] Y position
- [0x08-0x0b] X position
- [0x10-0x13] Y offset (a.k.a. calculated sine)
- [0x14-0x17] X offset (a.k.a. calculated cosine)
- [0x37] angle direction
- TOC
- [0x11381c] ball object
+
+ work RAM object structure (in seibu cup soccer)
+ all object have a [0x40] boundary
+ [0x04-0x07] Y position
+ [0x08-0x0b] X position
+ [0x10-0x13] Y offset (a.k.a. calculated sine)
+ [0x14-0x17] X offset (a.k.a. calculated cosine)
+ [0x37] angle direction
+ TOC
+ [0x11381c] ball object
***************************************************************************/
@@ -316,7 +316,7 @@ WRITE16_MEMBER(raiden2cop_device::cop_pgm_data_w)
cop_func_value[idx] = cop_latch_value;
cop_func_mask[idx] = cop_latch_mask;
bool upper_regs = ((cop_latch_trigger >> 10) & 1) == 1; // f1
-
+
if(data) {
int off = data & 31;
int reg = ((data >> 5) & 3) + (upper_regs == true ? 4 : 0);
@@ -325,7 +325,7 @@ WRITE16_MEMBER(raiden2cop_device::cop_pgm_data_w)
logerror("COPDIS: %04x s=%02x f1=%x l=%x f2=%02x %x %04x %02x %03x %02x.%x.%02x ", cop_latch_trigger, (cop_latch_trigger >> 11) << 3, (cop_latch_trigger >> 10) & 1, ((cop_latch_trigger >> 7) & 7)+1, cop_latch_trigger & 0x7f, cop_latch_value, cop_latch_mask, cop_latch_addr, data, op, reg, off);
off *= 2;
-
+
// COPDIS: 0205 s=00 f1=0 l=5 f2=05 6 ffeb 00 188 03.0.08 read32 10(r0)
// COPDIS: 0205 s=00 f1=0 l=5 f2=05 6 ffeb 01 282 05.0.02 add32 4(r0)
// COPDIS: 0205 s=00 f1=0 l=5 f2=05 6 ffeb 02 082 01.0.02 write32 4(r0)
@@ -763,13 +763,13 @@ WRITE16_MEMBER(raiden2cop_device::cop_dma_trigger_w)
case 0x85:
case 0x86:
case 0x87:
- {
+ {
dma_palette_brightness();
break;
}
/********************************************************************************************************************/
- case 0x09:
+ case 0x09:
{
UINT32 src, dst, size;
int i;
@@ -1145,7 +1145,7 @@ WRITE16_MEMBER( raiden2cop_device::cop_cmd_w)
case 0x7e05:
execute_7e05(offset, data);
break;
-
+
case 0xa100:
case 0xa180:
execute_a100(offset, data); // collisions
@@ -1585,9 +1585,9 @@ WRITE16_MEMBER(raiden2cop_device::LEGACY_cop_cmd_w)
return;
}
/*
- [:raiden2cop] COPDIS: 5105 s=50 f1=0 l=3 f2=05 5 fefb 50 a80 15.0.00 [:raiden2cop] sub32 (r0)
- [:raiden2cop] COPDIS: 5105 s=50 f1=0 l=3 f2=05 5 fefb 51 984 13.0.04 [:raiden2cop] write16h 8(r0)
- [:raiden2cop] COPDIS: 5105 s=50 f1=0 l=3 f2=05 5 fefb 52 082 01.0.02 [:raiden2cop] addmem32 4(r0)
+ [:raiden2cop] COPDIS: 5105 s=50 f1=0 l=3 f2=05 5 fefb 50 a80 15.0.00 [:raiden2cop] sub32 (r0)
+ [:raiden2cop] COPDIS: 5105 s=50 f1=0 l=3 f2=05 5 fefb 51 984 13.0.04 [:raiden2cop] write16h 8(r0)
+ [:raiden2cop] COPDIS: 5105 s=50 f1=0 l=3 f2=05 5 fefb 52 082 01.0.02 [:raiden2cop] addmem32 4(r0)
*/
if (check_command_matches(command, 0xa80, 0x984, 0x082, 0x000, 0x000, 0x000, 0x000, 0x000, 5, 0xfefb))
@@ -1608,14 +1608,14 @@ WRITE16_MEMBER(raiden2cop_device::LEGACY_cop_cmd_w)
printf("5905\n");
return;
}
-
+
// player to ball collision
if (check_command_matches(command, 0xa88, 0x994, 0x088, 0x000, 0x000, 0x000, 0x000, 0x000, 5, 0xfefb))
{
execute_f105(offset,data);
return;
}
-
+
if (executed == 0)
{
printf("did not execute %04x\n", data); // cup soccer triggers this a lot (and others)
diff --git a/src/mame/machine/seibucop/seibucop.h b/src/mame/machine/seibucop/seibucop.h
index 88599840fc4..7802f791f3a 100644
--- a/src/mame/machine/seibucop/seibucop.h
+++ b/src/mame/machine/seibucop/seibucop.h
@@ -258,7 +258,7 @@ private:
void LEGACY_execute_d104(int offset, UINT16 data);
void LEGACY_execute_6980(int offset, UINT16 data);
void LEGACY_execute_c480(int offset, UINT16 data);
-
+
void cop_collision_update_hitbox(UINT16 data, int slot, UINT32 hitadr);
void bcd_update();
diff --git a/src/mame/machine/seicop.cpp b/src/mame/machine/seicop.cpp
index 5b1ba2b44a4..99e0a97daef 100644
--- a/src/mame/machine/seicop.cpp
+++ b/src/mame/machine/seicop.cpp
@@ -5,10 +5,10 @@
COPDX bootleg simulation
- Seibu Cup Soccer (bootleg)
- Notice that only the bare minimum is supported, which is what the bootleg device actually
+ Notice that only the bare minimum is supported, which is what the bootleg device actually
provides. Unlike the original device and many other Seibu customs, it has no DMA.
- Apparently it's an Actel PL84c FPGA programmed to be a Seibu COP clone.
- The internal operations are actually loaded via the ROMs, we use the original algorithm
+ Apparently it's an Actel PL84c FPGA programmed to be a Seibu COP clone.
+ The internal operations are actually loaded via the ROMs, we use the original algorithm
for the trigger until we find the proper hookup.
********************************************************************************************/
@@ -46,7 +46,7 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
UINT8 offs;
offs = (offset & 3) * 4;
-
+
switch(data)
{
default:
@@ -54,7 +54,7 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
break;
case 0x0000:
break;
-
+
case 0xf105:
break;
@@ -89,7 +89,7 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
int target_reg = data & 0x200 ? 2 : 1;
int dy = (m_host_space->read_dword(m_reg[target_reg]+4) >> 16) - (m_host_space->read_dword(m_reg[0]+4) >> 16);
int dx = (m_host_space->read_dword(m_reg[target_reg]+8) >> 16) - (m_host_space->read_dword(m_reg[0]+8) >> 16);
-
+
//m_status = 7;
if(!dy) {
m_status = 0x8000;
@@ -112,7 +112,7 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
break;
}
-
+
case 0x3bb0:
{
int dy = m_dy;
@@ -121,13 +121,13 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
dx >>= 16;
dy >>= 16;
m_dist = sqrt((double)(dx*dx+dy*dy));
-
+
// TODO: is this right?
m_host_space->write_word(m_reg[0]+(0x38), m_dist);
break;
}
-
+
// TODO: wrong
case 0x42c2:
{
@@ -143,18 +143,18 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
m_host_space->write_dword(m_reg[0] + (0x38), (m_dist << (5 - 1)) / div);
break;
}
-
+
/*
- 00000-0ffff:
- amp = x/256
- ang = x & 255
- s = sin(ang*2*pi/256)
- val = trunc(s*amp)
- if(s<0)
- val--
- if(s == 192)
- val = -2*amp
- */
+ 00000-0ffff:
+ amp = x/256
+ ang = x & 255
+ s = sin(ang*2*pi/256)
+ val = trunc(s*amp)
+ if(s<0)
+ val--
+ if(s == 192)
+ val = -2*amp
+ */
case 0x8100:
{
UINT16 sin_offs; //= m_host_space->read_dword(m_reg[0]+(0x34));
@@ -164,7 +164,7 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
double angle = raw_angle * M_PI / 128;
double amp = (65536 >> 5)*(m_host_space->read_word(m_reg[0]+(0x36^2)) & 0xff);
int res;
-
+
/* TODO: up direction, why? */
if(raw_angle == 0xc0)
@@ -176,7 +176,7 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
break;
}
-
+
case 0x8900:
{
int raw_angle = (m_host_space->read_word(m_reg[0]+(0x34^2)) & 0xff);
@@ -201,7 +201,7 @@ WRITE16_MEMBER(seibu_cop_bootleg_device::cmd_trigger_w)
break;
}
}
-
+
}
READ16_MEMBER(seibu_cop_bootleg_device::status_r)
@@ -227,9 +227,9 @@ READ16_MEMBER(seibu_cop_bootleg_device::d104_move_r)
WRITE16_MEMBER(seibu_cop_bootleg_device::d104_move_w)
{
if(offset == 1)
- m_d104_move_offset = (m_d104_move_offset & 0xffff0000) | (data & 0xffff);
+ m_d104_move_offset = (m_d104_move_offset & 0xffff0000) | (data & 0xffff);
else
- m_d104_move_offset = (m_d104_move_offset & 0xffff) | (data << 16);
+ m_d104_move_offset = (m_d104_move_offset & 0xffff) | (data << 16);
}
// anything that is read thru ROM range 0xc**** is replacement code, therefore on this HW they are latches.
@@ -247,8 +247,8 @@ ADDRESS_MAP_END
seibu_cop_bootleg_device::seibu_cop_bootleg_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, SEIBU_COP_BOOTLEG, "Seibu COP (Bootleg)", tag, owner, clock, "seibu_cop_boot", __FILE__),
- device_memory_interface(mconfig, *this),
- m_space_config("regs", ENDIANNESS_LITTLE, 16, 9, 0, nullptr, *ADDRESS_MAP_NAME(seibucopbl_map))
+ device_memory_interface(mconfig, *this),
+ m_space_config("regs", ENDIANNESS_LITTLE, 16, 9, 0, nullptr, *ADDRESS_MAP_NAME(seibucopbl_map))
{
}
@@ -275,7 +275,7 @@ void seibu_cop_bootleg_device::device_config_complete()
void seibu_cop_bootleg_device::device_start()
{
-// m_cop_mcu_ram = reinterpret_cast<UINT16 *>(machine().root_device().memshare("cop_mcu_ram")->ptr());
+// m_cop_mcu_ram = reinterpret_cast<UINT16 *>(machine().root_device().memshare("cop_mcu_ram")->ptr());
}
diff --git a/src/mame/machine/seicop.h b/src/mame/machine/seicop.h
index eb15b497572..ec771f96edf 100644
--- a/src/mame/machine/seicop.h
+++ b/src/mame/machine/seicop.h
@@ -6,7 +6,7 @@
class seibu_cop_bootleg_device : public device_t,
- public device_memory_interface
+ public device_memory_interface
{
public:
seibu_cop_bootleg_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
@@ -34,7 +34,7 @@ protected:
private:
cpu_device *m_host_cpu; /**< reference to the host cpu */
- address_space *m_host_space; /**< reference to the host cpu space */
+ address_space *m_host_space; /**< reference to the host cpu space */
const address_space_config m_space_config;
inline UINT16 read_word(offs_t address);
inline void write_word(offs_t address, UINT16 data);
diff --git a/src/mame/mame.lst b/src/mame/mame.lst
index 2bcc0310c3d..8d4621155f7 100644
--- a/src/mame/mame.lst
+++ b/src/mame/mame.lst
@@ -28269,7 +28269,7 @@ ryuuha // (c) 1987
secolove // (c) 1986
seiha // (c) 1987
seiham // (c) 1987
-swinggal // (c) 1987 Digital Denshi
+swinggal // (c) 1987 Digital Denshi
vipclub // (c) 1988 Daiichi Denshi
@source:nbmj8891.cpp
@@ -34059,13 +34059,13 @@ sun3_460 //
sun_s10 //
sun_s20 //
sun4_20 //
-sun4_110 //
+sun4_110 //
sun4_300 //
-sun4_400 //
+sun4_400 //
sun4_40 //
sun4_50 //
sun4_60 //
-sun4_65 //
+sun4_65 //
sun4_75 //
@source:suna16.cpp
@@ -35736,8 +35736,8 @@ tutor // 1983? Tomy Tutor
tv950 //
@source:tv990.cpp
-tv990 // 1992? TeleVideo
-tv995 // 1994 TeleVideo
+tv990 // 1992? TeleVideo
+tv995 // 1994 TeleVideo
@source:tvc.cpp
tvc64 //
diff --git a/src/mame/video/epos.cpp b/src/mame/video/epos.cpp
index ecc350afd0a..d0096b4dd45 100644
--- a/src/mame/video/epos.cpp
+++ b/src/mame/video/epos.cpp
@@ -90,7 +90,7 @@ UINT32 epos_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, co
int x = (offs % 136) * 2;
int y = (offs / 136);
-
+
if (flip_screen())
{
x = 270 - x; // wrong
diff --git a/src/mame/video/gime.cpp b/src/mame/video/gime.cpp
index 38fcbfd76f3..8a1c2debae5 100644
--- a/src/mame/video/gime.cpp
+++ b/src/mame/video/gime.cpp
@@ -240,7 +240,7 @@ inline gime_base_device::pixel_t gime_base_device::get_composite_color(int color
0xfd8ef1, 0xef8eff, 0xd895ff, 0xb9a1ff, 0x86c4ff, 0x78d4f2, 0x71e2b6, 0xffffff,
};
- // composite output with phase inverted
+ // composite output with phase inverted
static pixel_t composite_palette_180[64] = {
0x000000, 0x5a0e5a, 0x4f0c4f, 0x360f40, 0x0d213c, 0x003334, 0x004141, 0x004943,
0x005409, 0x005600, 0x114c00, 0x263700, 0x392500, 0x491d00, 0x4f0f3e, 0x590e59,
@@ -897,7 +897,7 @@ inline void gime_base_device::write_gime_register(offs_t offset, UINT8 data)
// Bits 0-2 LPR Lines per row
if (xorval & 0x20)
{
- // on phase invert re-load the alternate composite palette
+ // on phase invert re-load the alternate composite palette
m_composite_phase_invert = (data & 0x20);
update_composite_palette();
}
diff --git a/src/mame/video/itech32.cpp b/src/mame/video/itech32.cpp
index 712ff41a32c..da6a84f3f06 100644
--- a/src/mame/video/itech32.cpp
+++ b/src/mame/video/itech32.cpp
@@ -198,7 +198,7 @@ void itech32_state::video_start()
m_scanline_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(itech32_state::scanline_interrupt),this));
m_enable_latch[0] = 1;
m_enable_latch[1] = (m_planes > 1) ? 1 : 0;
-
+
save_item(NAME(m_xfer_xcount));
save_item(NAME(m_xfer_ycount));
save_item(NAME(m_xfer_xcur));
diff --git a/src/mame/video/legionna.cpp b/src/mame/video/legionna.cpp
index 95d6182e445..07b8cce83af 100644
--- a/src/mame/video/legionna.cpp
+++ b/src/mame/video/legionna.cpp
@@ -13,8 +13,8 @@
- MBK
- OBJ 3
- LBK
- TODO: Anything else doesn't match this scheme (most notably Denjin Makai),
- guess it's selectable by PROM, CRTC or COP ...
+ TODO: Anything else doesn't match this scheme (most notably Denjin Makai),
+ guess it's selectable by PROM, CRTC or COP ...
***************************************************************************/
@@ -224,13 +224,13 @@ void legionna_state::common_video_allocate_ptr()
m_scrollram16 = std::make_unique<UINT16[]>(0x60/2);
m_sprite_xoffs = 0;
m_sprite_yoffs = 0;
-
+
save_pointer(NAME(m_back_data.get()), 0x800/2);
save_pointer(NAME(m_fore_data.get()), 0x800/2);
save_pointer(NAME(m_mid_data.get()), 0x800/2);
save_pointer(NAME(m_textram.get()), 0x1000/2);
save_pointer(NAME(m_scrollram16.get()), 0x60/2);
-
+
save_item(NAME(m_back_gfx_bank));
save_item(NAME(m_mid_gfx_bank));
save_item(NAME(m_fore_gfx_bank));
@@ -258,7 +258,7 @@ void legionna_state::common_video_start()
VIDEO_START_MEMBER(legionna_state,legionna)
{
common_video_start();
-
+
m_sprite_pri_mask[0] = 0x0000;
m_sprite_pri_mask[1] = 0xfff0;
m_sprite_pri_mask[2] = 0xfffc;
@@ -282,7 +282,7 @@ VIDEO_START_MEMBER(legionna_state,godzilla)
m_has_extended_banking = 1;
m_has_extended_priority = 0;
-
+
m_sprite_pri_mask[0] = 0xfff0;
m_sprite_pri_mask[1] = 0xfffc;
m_sprite_pri_mask[2] = 0xfffe;
@@ -293,7 +293,7 @@ VIDEO_START_MEMBER(legionna_state,godzilla)
VIDEO_START_MEMBER(legionna_state,denjinmk)
{
common_video_allocate_ptr();
-
+
m_background_layer = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(legionna_state::get_back_tile_info),this),TILEMAP_SCAN_ROWS,16,16,32,32);
m_midground_layer = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(legionna_state::get_mid_tile_info_denji),this), TILEMAP_SCAN_ROWS,16,16,32,32);
m_foreground_layer = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(legionna_state::get_fore_tile_info_denji),this),TILEMAP_SCAN_ROWS,16,16,32,32);
@@ -301,13 +301,13 @@ VIDEO_START_MEMBER(legionna_state,denjinmk)
m_has_extended_banking = 1;
m_has_extended_priority = 0;
-
+
m_sprite_pri_mask[0] = 0xfff0; // normal sprites
m_sprite_pri_mask[1] = 0xfffc; // luna park horse rides
m_sprite_pri_mask[2] = 0xfffe; // door at the end of sewers part in level 1
m_sprite_pri_mask[3] = 0x0000; // briefing guy in pre-stage and portraits before a boss fight
-
-// m_background_layer->set_transparent_pen(15);
+
+// m_background_layer->set_transparent_pen(15);
m_midground_layer->set_transparent_pen(15);
m_foreground_layer->set_transparent_pen(15);
m_text_layer->set_transparent_pen(7);//?
@@ -420,21 +420,21 @@ void legionna_state::draw_sprites(screen_device &screen, bitmap_ind16 &bitmap,co
pri_mask = m_sprite_pri_mask[cur_pri];
#if 0
static UINT8 pri_test;
-
+
if(machine().input().code_pressed_once(KEYCODE_A))
pri_test++;
-
+
if(machine().input().code_pressed_once(KEYCODE_A))
pri_test--;
pri_test&=3;
popmessage("%02x",pri_test);
-
+
// quick and dirty priority tester
if(cur_pri == pri_test)
{
static UINT16 test = 0xffff;
-
+
if(machine().input().code_pressed_once(KEYCODE_Q))
test^=1;
@@ -457,7 +457,7 @@ void legionna_state::draw_sprites(screen_device &screen, bitmap_ind16 &bitmap,co
test^=0x40;
if(machine().input().code_pressed_once(KEYCODE_I))
- test^=0x80;
+ test^=0x80;
pri_mask = 0xffff & test;
data = (data & 0xffc0) | (machine().rand() & 0x3f);
@@ -592,7 +592,7 @@ UINT32 legionna_state::screen_update_heatbrl(screen_device &screen, bitmap_ind16
/* Setup the tilemaps */
screen.priority().fill(0, cliprect);
bitmap.fill(m_palette->black_pen(), cliprect); /* wrong color? */
-
+
// TODO: priority order is different than anything else?
if (!(m_layer_disable&0x0004)) m_foreground_layer->draw(screen, bitmap, cliprect, 0, 0);
if (!(m_layer_disable&0x0002)) m_midground_layer->draw(screen, bitmap, cliprect, 0, 1);
diff --git a/src/mame/video/pcd.cpp b/src/mame/video/pcd.cpp
index b8c868ac074..b192fd62ad2 100644
--- a/src/mame/video/pcd.cpp
+++ b/src/mame/video/pcd.cpp
@@ -149,7 +149,7 @@ static MACHINE_CONFIG_FRAGMENT( pcx_video )
MCFG_CPU_ADD("graphics", I8031, XTAL_24MHz/2)
MCFG_CPU_PROGRAM_MAP(pcx_vid_map)
MCFG_CPU_IO_MAP(pcx_vid_io)
-
+
MCFG_MCS51_SERIAL_TX_CB(WRITE8(pcx_video_device, tx_callback))
MCFG_MCS51_SERIAL_RX_CB(READ8(pcx_video_device, rx_callback))
diff --git a/src/mame/video/vtvideo.cpp b/src/mame/video/vtvideo.cpp
index 61e7f601c8e..cd08b30b6ef 100644
--- a/src/mame/video/vtvideo.cpp
+++ b/src/mame/video/vtvideo.cpp
@@ -238,16 +238,16 @@ WRITE8_MEMBER(vt100_video_device::dc012_w)
// - see 3.1.3.9.5 DC012 Programming Information (PC-100 spec)
if ((offset & 0x100) ) // MHFU is disabled by writing a value to port 010C.
{
-// if (MHFU_FLAG == true)
-// printf("MHFU *** DISABLED *** \n");
+// if (MHFU_FLAG == true)
+// printf("MHFU *** DISABLED *** \n");
MHFU_FLAG = false;
}
else
{
-// if (MHFU_FLAG == false)
-// printf("MHFU ___ENABLED___ %05x \n", space.device().safe_pc());
+// if (MHFU_FLAG == false)
+// printf("MHFU ___ENABLED___ %05x \n", space.device().safe_pc());
MHFU_FLAG = true;
- MHFU_counter = 0;
+ MHFU_counter = 0;
}
if (!(data & 0x08))
@@ -279,10 +279,10 @@ WRITE8_MEMBER(vt100_video_device::dc012_w)
// PDF: reverse field ON
m_reverse_field = 0;
break;
- case 0x0b:
- // PDF: reverse field OFF
- // SETUP: dark screen selected
- m_reverse_field = 1;
+ case 0x0b:
+ // PDF: reverse field OFF
+ // SETUP: dark screen selected
+ m_reverse_field = 1;
break;
// Writing a 11XX bit combination clears the blink-flip flop (valid for 0x0C - 0x0F):
@@ -845,10 +845,10 @@ int rainbow_video_device::MHFU(int ASK)
{
switch (ASK)
{
- case MHFU_IS_ENABLED: // "true": RETURN BOOLEAN (MHFU disabled or enabled?)
+ case MHFU_IS_ENABLED: // "true": RETURN BOOLEAN (MHFU disabled or enabled?)
return MHFU_FLAG;
- case MHFU_COUNT: // -1: increment IF ENABLED, return counter value (=> Rainbow.c)
+ case MHFU_COUNT: // -1: increment IF ENABLED, return counter value (=> Rainbow.c)
if (MHFU_FLAG == true)
if (MHFU_counter < 254)
MHFU_counter++;
@@ -856,17 +856,17 @@ int rainbow_video_device::MHFU(int ASK)
case MHFU_VALUE:
return MHFU_counter;
- case MHFU_RESET: // -250 : RESET counter (NOTHING ELSE!)
+ case MHFU_RESET: // -250 : RESET counter (NOTHING ELSE!)
MHFU_counter = 0;
return MHFU_FLAG;
- case MHFU_RESET_and_ENABLE: // -100 : RESET and ENABLE MHFU counter
+ case MHFU_RESET_and_ENABLE: // -100 : RESET and ENABLE MHFU counter
MHFU_counter = 0;
MHFU_FLAG = true;
return -100;
- case MHFU_RESET_and_DISABLE: // -200 : RESET and DISABLE MHFU
+ case MHFU_RESET_and_DISABLE: // -200 : RESET and DISABLE MHFU
MHFU_counter = 0;
MHFU_FLAG = false;
diff --git a/src/osd/modules/file/windir.cpp b/src/osd/modules/file/windir.cpp
index 9b67e163652..522e0e297a1 100644
--- a/src/osd/modules/file/windir.cpp
+++ b/src/osd/modules/file/windir.cpp
@@ -48,7 +48,7 @@ private:
bool m_is_first; // true if this is the first entry
entry m_entry; // current entry's data
WIN32_FIND_DATA m_data; // current raw data
- std::string m_name; // converted name of directory
+ std::string m_name; // converted name of directory
};
//============================================================
diff --git a/src/osd/modules/input/input_common.cpp b/src/osd/modules/input/input_common.cpp
index 65b1ce144a6..73af2e9e9e1 100644
--- a/src/osd/modules/input/input_common.cpp
+++ b/src/osd/modules/input/input_common.cpp
@@ -87,7 +87,7 @@ key_trans_entry keyboard_trans_table::s_default_table[] =
KEY_TRANS_ENTRY1(TILDE, GRAVE, BACKQUOTE, GRAVE, VK_OEM_3, '`'),
KEY_TRANS_ENTRY1(LSHIFT, LSHIFT, LSHIFT, LSHIFT, VK_LSHIFT, 0),
KEY_TRANS_ENTRY1(BACKSLASH, BACKSLASH, BACKSLASH, BACKSLASH, VK_OEM_5, '\\'),
-// KEY_TRANS_ENTRY1(BACKSLASH2, NONUSHASH, UNKNOWN, OEM_102, VK_OEM_102, '<'),
+// KEY_TRANS_ENTRY1(BACKSLASH2, NONUSHASH, UNKNOWN, OEM_102, VK_OEM_102, '<'),
// This is the additional key that ISO keyboards have over ANSI ones, located between left shift and Y.
KEY_TRANS_ENTRY1(BACKSLASH2, NONUSBACKSLASH, UNKNOWN, OEM_102, VK_OEM_102, '<'),
KEY_TRANS_ENTRY1(Z, Z, z, Z, 'Z', 'Z'),
diff --git a/src/osd/modules/input/input_x11.cpp b/src/osd/modules/input/input_x11.cpp
index 108b565012a..a3a7021c0a6 100644
--- a/src/osd/modules/input/input_x11.cpp
+++ b/src/osd/modules/input/input_x11.cpp
@@ -489,7 +489,7 @@ public:
x11_event_manager::instance().subscribe(event_types, ARRAY_LENGTH(event_types), this);
}
- osd_printf_verbose("Lightgun: End initialization\n");
+ osd_printf_verbose("Lightgun: End initialization\n");
}
bool should_poll_devices(running_machine &machine) override
diff --git a/src/osd/modules/render/d3d/d3dhlsl.cpp b/src/osd/modules/render/d3d/d3dhlsl.cpp
index 8daea6c0c33..241f4b2a7f6 100644
--- a/src/osd/modules/render/d3d/d3dhlsl.cpp
+++ b/src/osd/modules/render/d3d/d3dhlsl.cpp
@@ -48,12 +48,12 @@ public:
{
HRESULT result;
- m_avi_writer = std::make_unique<avi_write>(machine, width, height);
+ m_avi_writer = std::make_unique<avi_write>(machine, width, height);
m_frame.allocate(width, height);
if (!m_frame.valid())
return;
-
+
result = d3d->get_device()->CreateTexture(width, height, 1, D3DUSAGE_DYNAMIC, D3DFMT_A8R8G8B8, D3DPOOL_SYSTEMMEM, &m_sys_texture, nullptr);
if (FAILED(result))
{
@@ -69,7 +69,7 @@ public:
return;
}
m_vid_texture->GetSurfaceLevel(0, &m_vid_surface);
-
+
m_initialized = true;
}
diff --git a/src/osd/modules/render/drawbgfx.cpp b/src/osd/modules/render/drawbgfx.cpp
index 4a3d6711c7c..29721c65b77 100644
--- a/src/osd/modules/render/drawbgfx.cpp
+++ b/src/osd/modules/render/drawbgfx.cpp
@@ -292,14 +292,14 @@ void renderer_bgfx::record()
bool renderer_bgfx::init(running_machine &machine)
{
const char *bgfx_path = downcast<osd_options &>(machine.options()).bgfx_path();
-
+
osd::directory::ptr directory = osd::directory::open(bgfx_path);
if (directory == nullptr)
{
osd_printf_verbose("Unable to find the %s folder. Please reinstall it to use the BGFX renderer\n", bgfx_path);
return true;
}
-
+
return false;
}
diff --git a/src/osd/modules/render/drawd3d.cpp b/src/osd/modules/render/drawd3d.cpp
index 122c8758f05..102abf35413 100644
--- a/src/osd/modules/render/drawd3d.cpp
+++ b/src/osd/modules/render/drawd3d.cpp
@@ -330,7 +330,7 @@ void renderer_d3d9::set_blendmode(int blendmode)
blendop = D3DBLENDOP_ADD;
blendsrc = D3DBLEND_SRCALPHA;
blenddst = D3DBLEND_ONE;
- break;
+ break;
}
// adjust the bits that changed
@@ -479,7 +479,7 @@ texture_info *d3d_texture_manager::find_texinfo(const render_texinfo *texinfo, U
UINT32 prim_page = (UINT32)texinfo->osddata & 1;
if (test_screen != prim_screen || test_page != prim_page)
continue;
-
+
if ((*it)->get_hash() == hash &&
(*it)->get_texinfo().base == texinfo->base &&
(*it)->get_texinfo().width == texinfo->width &&
diff --git a/src/osd/osdcore.h b/src/osd/osdcore.h
index 7b12a51422c..7464e076141 100644
--- a/src/osd/osdcore.h
+++ b/src/osd/osdcore.h
@@ -294,30 +294,30 @@ int osd_uchar_from_osdchar(unicode_char *uchar, const char *osdchar, size_t coun
/*-----------------------------------------------------------------------------
- osd_is_valid_filename_char: is the given character legal for filenames?
+ osd_is_valid_filename_char: is the given character legal for filenames?
- Parameters:
+ Parameters:
- uchar - the character to check
+ uchar - the character to check
- Return value:
+ Return value:
- Whether this character is legal in a filename
+ Whether this character is legal in a filename
-----------------------------------------------------------------------------*/
bool osd_is_valid_filename_char(unicode_char uchar);
/*-----------------------------------------------------------------------------
- osd_is_valid_filepath_char: is the given character legal for paths?
+ osd_is_valid_filepath_char: is the given character legal for paths?
- Parameters:
+ Parameters:
- uchar - the character to check
+ uchar - the character to check
- Return value:
+ Return value:
- Whether this character is legal in a file path
+ Whether this character is legal in a file path
-----------------------------------------------------------------------------*/
bool osd_is_valid_filepath_char(unicode_char uchar);
diff --git a/src/osd/windows/video.cpp b/src/osd/windows/video.cpp
index c38770ad719..0d4232fcd1c 100644
--- a/src/osd/windows/video.cpp
+++ b/src/osd/windows/video.cpp
@@ -145,7 +145,7 @@ std::shared_ptr<osd_monitor_info> win_monitor_info::monitor_from_handle(HMONITOR
for (auto monitor : osd_monitor_info::list)
if (*((HMONITOR*)monitor->oshandle()) == hmonitor)
return monitor;
-
+
return nullptr;
}