diff options
author | Curt Coder <curtcoder@mail.com> | 2012-09-09 20:04:57 +0000 |
---|---|---|
committer | Curt Coder <curtcoder@mail.com> | 2012-09-09 20:04:57 +0000 |
commit | 3cabf176bb95d6ed1a5b8bf23f243c7b269f4c53 (patch) | |
tree | b38a457de278f353ccfef3f352506ddd66a8a998 /src | |
parent | 0bb82250978b228a1e87730f7440d1250292244a (diff) |
(MESS) c128: MMU WIP. (nw)
Diffstat (limited to 'src')
-rw-r--r-- | src/mess/drivers/c128.c | 244 | ||||
-rw-r--r-- | src/mess/includes/c128.h | 25 | ||||
-rw-r--r-- | src/mess/machine/c128.c | 80 |
3 files changed, 308 insertions, 41 deletions
diff --git a/src/mess/drivers/c128.c b/src/mess/drivers/c128.c index d9874bf0d8c..7ae413918ed 100644 --- a/src/mess/drivers/c128.c +++ b/src/mess/drivers/c128.c @@ -211,6 +211,209 @@ to use an EEPROM reader, in order to obtain a dump of the whole content. * 0x0000-0xedff ram (dram bank 1?) * 0xe000-0xffff ram as bank 0 */ + +void c128_state::bankswitch_pla(offs_t offset, int ba, int rw, int aec, int z80io, int ma5, int ma4, int ms3, int ms2, int ms1, int ms0, + int *cas, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic, int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb) +{ + //int game = m_exp->game_r(offset, ba, rw, m_hiram); + //int exrom = m_exp->exrom_r(offset, ba, rw, m_hiram); + //int vicfix = 0; + //int _128_256 = 1; +} + +UINT8 c128_state::read_memory(offs_t offset, int ba, int aec, int z80io) +{ + int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1; + //offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3); + int cas, gwe, rom1, rom2, rom3, rom4, charom, colorram, vic, from1, romh, roml, dwe, ioacc, clrbank, iocs, casenb; + //int io1 = 1, io2 = 1; + + bankswitch_pla(offset, ba, rw, aec, z80io, 0, 0, ms3, ms2, ms1, ms0, + &cas, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb); + + UINT8 data = 0xff; + + if (ba) + { + data = m_vic->bus_r(); + } + + if (!cas) + { + + } + else if (!rom1) + { + + } + else if (!rom2) + { + + } + else if (!rom3) + { + + } + else if (!rom4) + { + + } + else if (!charom) + { + + } + else if (!colorram) + { + + } + else if (!vic) + { + + } + else if (!from1) + { + + } + else if (!iocs) + { + switch (offset) + { + case 0: // SID + break; + + case 2: // CS8563 + break; + + case 4: // CIA1 + break; + + case 5: // CIA2 + break; + + case 6: // I/O1 + break; + + case 7: // I/O2 + break; + } + } + + return data;//m_exp->cd_r(space, offset, data, ba, roml, romh, io1, io2); +} + +void c128_state::write_memory(offs_t offset, UINT8 data, int ba, int aec, int z80io) +{ + int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1; + //offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3); + int cas, gwe, rom1, rom2, rom3, rom4, charom, colorram, vic, from1, romh, roml, dwe, ioacc, clrbank, iocs, casenb; + //int io1 = 1, io2 = 1; + + bankswitch_pla(offset, ba, rw, aec, z80io, 0, 0, ms3, ms2, ms1, ms0, + &cas, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb); + + if (!cas) + { + + } + else if (!gwe) + { + + } + else if (!rom1) + { + + } + else if (!rom2) + { + + } + else if (!rom3) + { + + } + else if (!rom4) + { + + } + else if (!charom) + { + + } + else if (!colorram) + { + + } + else if (!vic) + { + + } + else if (!from1) + { + + } + else if (!dwe) + { + + } + else if (!iocs) + { + + } + + //m_exp->cd_w(space, offset, data, ba, roml, romh, io1, io2); +} + +READ8_MEMBER( c128_state::z80_r ) +{ + int ba = 1, aec = 1, z80io = 1; + + return read_memory(offset, ba, aec, z80io); +} + +WRITE8_MEMBER( c128_state::z80_w ) +{ + int ba = 1, aec = 1, z80io = 1; + + write_memory(offset, data, ba, aec, z80io); +} + +READ8_MEMBER( c128_state::z80_io_r ) +{ + int ba = 1, aec = 1, z80io = 0; + + return read_memory(offset, ba, aec, z80io); +} + +WRITE8_MEMBER( c128_state::z80_io_w ) +{ + int ba = 1, aec = 1, z80io = 0; + + write_memory(offset, data, ba, aec, z80io); +} + +READ8_MEMBER( c128_state::read ) +{ + int ba = 1, aec = 1, z80io = 1; + + return read_memory(offset, ba, aec, z80io); +} + +WRITE8_MEMBER( c128_state::write ) +{ + int ba = 1, aec = 1, z80io = 1; + + write_memory(offset, data, ba, aec, z80io); +} + +READ8_MEMBER( c128_state::vic_videoram_r ) +{ + int ba = 0, aec = 0, z80io = 1; + + return read_memory(offset, ba, aec, z80io); +} + + + //************************************************************************** // ADDRESS MAPS //************************************************************************** @@ -541,6 +744,45 @@ INPUT_PORTS_END //************************************************************************** //------------------------------------------------- +// MOS8722_INTERFACE( mmu_intf ) +//------------------------------------------------- + +WRITE_LINE_MEMBER( c128_state::mmu_z80en_w ) +{ + +} + +WRITE_LINE_MEMBER( c128_state::mmu_fsdir_w ) +{ + +} + +READ_LINE_MEMBER( c128_state::mmu_game_r ) +{ + return 1; +} + +READ_LINE_MEMBER( c128_state::mmu_exrom_r ) +{ + return 1; +} + +READ_LINE_MEMBER( c128_state::mmu_sense40_r ) +{ + return 1; +} + +static MOS8722_INTERFACE( mmu_intf ) +{ + DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_z80en_w), + DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_fsdir_w), + DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_game_r), + DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_exrom_r), + DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_sense40_r) +}; + + +//------------------------------------------------- // MOS8564_INTERFACE( vic_intf ) //------------------------------------------------- @@ -686,6 +928,7 @@ static MACHINE_CONFIG_START( ntsc, c128_state ) // MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6567_HRETRACERATE) /* video hardware */ + MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf) MCFG_MOS8564_ADD(MOS8564_TAG, SCREEN_VIC_TAG, VIC6567_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map) MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, 2000000, vdc_intf, vdc_videoram_map) @@ -777,6 +1020,7 @@ static MACHINE_CONFIG_START( pal, c128_state ) // MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6569_HRETRACERATE) /* video hardware */ + MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf) MCFG_MOS8566_ADD(MOS8566_TAG, SCREEN_VIC_TAG, VIC6569_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map) MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, 2000000, vdc_intf, vdc_videoram_map) diff --git a/src/mess/includes/c128.h b/src/mess/includes/c128.h index 2c9351f462b..4570fd369b3 100644 --- a/src/mess/includes/c128.h +++ b/src/mess/includes/c128.h @@ -22,6 +22,7 @@ #include "machine/c64user.h" #include "machine/cbmiec.h" #include "machine/cbmipt.h" +#include "machine/mos8722.h" #include "machine/petcass.h" #include "machine/ram.h" #include "machine/vcsctrl.h" @@ -55,6 +56,7 @@ public: : legacy_c64_state(mconfig, type, tag), m_maincpu(*this, Z80A_TAG), m_subcpu(*this, M8502_TAG), + m_mmu(*this, MOS8722_TAG), m_vdc(*this, MOS8563_TAG), m_vic(*this, MOS8564_TAG), m_sid(*this, MOS6581_TAG), @@ -71,6 +73,7 @@ public: required_device<legacy_cpu_device> m_maincpu; required_device<legacy_cpu_device> m_subcpu; + required_device<mos8722_device> m_mmu; required_device<mos8563_device> m_vdc; required_device<mos6566_device> m_vic; required_device<sid6581_device> m_sid; @@ -87,6 +90,19 @@ public: virtual void machine_start(); virtual void machine_reset(); + void bankswitch_pla(offs_t offset, int ba, int rw, int aec, int z80io, int ma5, int ma4, int ms3, int ms2, int ms1, int ms0, + int *cas, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic, int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb); + UINT8 read_memory(offs_t offset, int ba, int aec, int z80io); + void write_memory(offs_t offset, UINT8 data, int ba, int aec, int z80io); + + DECLARE_READ8_MEMBER( z80_r ); + DECLARE_WRITE8_MEMBER( z80_w ); + DECLARE_READ8_MEMBER( z80_io_r ); + DECLARE_WRITE8_MEMBER( z80_io_w ); + DECLARE_READ8_MEMBER( read ); + DECLARE_WRITE8_MEMBER( write ); + DECLARE_READ8_MEMBER( vic_videoram_r ); + DECLARE_READ8_MEMBER( read_io ); DECLARE_READ8_MEMBER( mmu8722_port_r ); DECLARE_WRITE8_MEMBER( mmu8722_port_w ); @@ -105,6 +121,12 @@ public: DECLARE_WRITE8_MEMBER( write_ff00 ); DECLARE_WRITE8_MEMBER( write_ff05 ); + DECLARE_WRITE_LINE_MEMBER( mmu_z80en_w ); + DECLARE_WRITE_LINE_MEMBER( mmu_fsdir_w ); + DECLARE_READ_LINE_MEMBER( mmu_game_r ); + DECLARE_READ_LINE_MEMBER( mmu_exrom_r ); + DECLARE_READ_LINE_MEMBER( mmu_sense40_r ); + DECLARE_READ8_MEMBER( vic_lightpen_x_cb ); DECLARE_READ8_MEMBER( vic_lightpen_y_cb ); DECLARE_READ8_MEMBER( vic_lightpen_button_cb ); @@ -151,7 +173,7 @@ public: UINT8 *m_internal_function; UINT8 *m_external_function; UINT8 *m_vdcram; - UINT8 m_mmu[0x0b]; + UINT8 m_mmu_reg[0x0b]; int m_mmu_cpu; int m_mmu_page0; int m_mmu_page1; @@ -167,6 +189,7 @@ public: int m_data_out; int m_va1617; int m_nmilevel; + int m_z80en; DECLARE_DRIVER_INIT(c128pal); DECLARE_DRIVER_INIT(c128dcrp); DECLARE_DRIVER_INIT(c128dcr); diff --git a/src/mess/machine/c128.c b/src/mess/machine/c128.c index 0bb4eee5e75..db45795400d 100644 --- a/src/mess/machine/c128.c +++ b/src/mess/machine/c128.c @@ -21,33 +21,33 @@ #include "video/mos6566.h" #include "video/mc6845.h" -#define MMU_PAGE1 ((((m_mmu[10]&0xf)<<8)|m_mmu[9])<<8) -#define MMU_PAGE0 ((((m_mmu[8]&0xf)<<8)|m_mmu[7])<<8) -#define MMU_VIC_ADDR ((m_mmu[6]&0xc0)<<10) -#define MMU_RAM_RCR_ADDR ((m_mmu[6]&0x30)<<14) -#define MMU_SIZE (c128_mmu_helper[m_mmu[6]&3]) -#define MMU_BOTTOM (m_mmu[6]&4) -#define MMU_TOP (m_mmu[6]&8) -#define MMU_CPU8502 (m_mmu[5]&1) /* else z80 */ +#define MMU_PAGE1 ((((m_mmu_reg[10]&0xf)<<8)|m_mmu_reg[9])<<8) +#define MMU_PAGE0 ((((m_mmu_reg[8]&0xf)<<8)|m_mmu_reg[7])<<8) +#define MMU_VIC_ADDR ((m_mmu_reg[6]&0xc0)<<10) +#define MMU_RAM_RCR_ADDR ((m_mmu_reg[6]&0x30)<<14) +#define MMU_SIZE (c128_mmu_helper[m_mmu_reg[6]&3]) +#define MMU_BOTTOM (m_mmu_reg[6]&4) +#define MMU_TOP (m_mmu_reg[6]&8) +#define MMU_CPU8502 (m_mmu_reg[5]&1) /* else z80 */ /* fastio output (c128_mmu[5]&8) else input */ -#define MMU_FSDIR (m_mmu[5]&0x08) -#define MMU_GAME_IN (m_mmu[5]&0x10) -#define MMU_EXROM_IN (m_mmu[5]&0x20) -#define MMU_64MODE (m_mmu[5]&0x40) -#define MMU_40_IN (m_mmu[5]&0x80) - -#define MMU_RAM_CR_ADDR ((m_mmu[0]&0xc0)<<10) -#define MMU_RAM_LO (m_mmu[0]&2) /* else rom at 0x4000 */ -#define MMU_RAM_MID ((m_mmu[0]&0xc)==0xc) /* 0x8000 - 0xbfff */ -#define MMU_ROM_MID ((m_mmu[0]&0xc)==0) -#define MMU_EXTERNAL_ROM_MID ((m_mmu[0]&0xc)==8) -#define MMU_INTERNAL_ROM_MID ((m_mmu[0]&0xc)==4) - -#define MMU_IO_ON (!(m_mmu[0]&1)) /* io window at 0xd000 */ -#define MMU_ROM_HI ((m_mmu[0]&0x30)==0) /* rom at 0xc000 */ -#define MMU_EXTERNAL_ROM_HI ((m_mmu[0]&0x30)==0x20) -#define MMU_INTERNAL_ROM_HI ((m_mmu[0]&0x30)==0x10) -#define MMU_RAM_HI ((m_mmu[0]&0x30)==0x30) +#define MMU_FSDIR (m_mmu_reg[5]&0x08) +#define MMU_GAME_IN (m_mmu_reg[5]&0x10) +#define MMU_EXROM_IN (m_mmu_reg[5]&0x20) +#define MMU_64MODE (m_mmu_reg[5]&0x40) +#define MMU_40_IN (m_mmu_reg[5]&0x80) + +#define MMU_RAM_CR_ADDR ((m_mmu_reg[0]&0xc0)<<10) +#define MMU_RAM_LO (m_mmu_reg[0]&2) /* else rom at 0x4000 */ +#define MMU_RAM_MID ((m_mmu_reg[0]&0xc)==0xc) /* 0x8000 - 0xbfff */ +#define MMU_ROM_MID ((m_mmu_reg[0]&0xc)==0) +#define MMU_EXTERNAL_ROM_MID ((m_mmu_reg[0]&0xc)==8) +#define MMU_INTERNAL_ROM_MID ((m_mmu_reg[0]&0xc)==4) + +#define MMU_IO_ON (!(m_mmu_reg[0]&1)) /* io window at 0xd000 */ +#define MMU_ROM_HI ((m_mmu_reg[0]&0x30)==0) /* rom at 0xc000 */ +#define MMU_EXTERNAL_ROM_HI ((m_mmu_reg[0]&0x30)==0x20) +#define MMU_INTERNAL_ROM_HI ((m_mmu_reg[0]&0x30)==0x10) +#define MMU_RAM_HI ((m_mmu_reg[0]&0x30)==0x30) #define MMU_RAM_ADDR (MMU_RAM_RCR_ADDR|MMU_RAM_CR_ADDR) @@ -796,9 +796,9 @@ void c128_state::bankswitch(int reset) void c128_state::mmu8722_reset() { - memset(m_mmu, 0, sizeof (m_mmu)); - m_mmu[5] |= 0x38; - m_mmu[10] = 1; + memset(m_mmu_reg, 0, sizeof (m_mmu_reg)); + m_mmu_reg[5] |= 0x38; + m_mmu_reg[10] = 1; m_mmu_cpu = 0; m_mmu_page0 = 0; m_mmu_page1 = 0x0100; @@ -816,10 +816,10 @@ WRITE8_MEMBER( c128_state::mmu8722_port_w ) case 4: case 8: case 10: - m_mmu[offset] = data; + m_mmu_reg[offset] = data; break; case 5: - m_mmu[offset] = data; + m_mmu_reg[offset] = data; bankswitch(0); iec_srq_out_w(); iec_data_out_w(); @@ -828,15 +828,15 @@ WRITE8_MEMBER( c128_state::mmu8722_port_w ) break; case 0: case 6: - m_mmu[offset] = data; + m_mmu_reg[offset] = data; bankswitch(0); break; case 7: - m_mmu[offset] = data; + m_mmu_reg[offset] = data; m_mmu_page0=MMU_PAGE0; break; case 9: - m_mmu[offset] = data; + m_mmu_reg[offset] = data; m_mmu_page1=MMU_PAGE1; bankswitch(0); break; @@ -858,7 +858,7 @@ READ8_MEMBER( c128_state::mmu8722_port_r ) switch (offset) { case 5: - data = m_mmu[offset] | 6; + data = m_mmu_reg[offset] | 6; if ( /*disk enable signal */ 0) data &= ~8; if (!m_game) @@ -884,7 +884,7 @@ READ8_MEMBER( c128_state::mmu8722_port_r ) data=0xff; break; default: - data=m_mmu[offset]; + data=m_mmu_reg[offset]; } return data; } @@ -894,7 +894,7 @@ WRITE8_MEMBER( c128_state::mmu8722_ff00_w ) switch (offset) { case 0: - m_mmu[offset] = data; + m_mmu_reg[offset] = data; bankswitch(0); break; case 1: @@ -902,9 +902,9 @@ WRITE8_MEMBER( c128_state::mmu8722_ff00_w ) case 3: case 4: #if 1 - m_mmu[0]= m_mmu[offset]; + m_mmu_reg[0]= m_mmu_reg[offset]; #else - m_mmu[0]|= m_mmu[offset]; + m_mmu_reg[0]|= m_mmu_reg[offset]; #endif bankswitch(0); break; @@ -913,7 +913,7 @@ WRITE8_MEMBER( c128_state::mmu8722_ff00_w ) READ8_MEMBER( c128_state::mmu8722_ff00_r ) { - return m_mmu[offset]; + return m_mmu_reg[offset]; } WRITE8_MEMBER( c128_state::write_0000 ) |