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author Joakim Larsson Edström <joakimlarsson42@gmail.com>2017-01-05 17:37:59 +0100
committer GitHub <noreply@github.com>2017-01-05 17:37:59 +0100
commit34c3e7866bc3e173a0cfb272286aaf8f774c01f4 (patch)
tree88f5eaf46bfd2c9838b5a6478285dac5b04366ab /src
parentea87606550db588f1a1a126382e9e0e818d3b804 (diff)
parent52906f6edeb741b89c28e8753e7a3bfb1d5e4c2f (diff)
Merge pull request #1927 from JoakimLarsson/vme_1
Converted fcisio1 and fcscsi1 boards to VME slot devices
Diffstat (limited to 'src')
-rw-r--r--src/devices/bus/vme/vme.cpp183
-rw-r--r--src/devices/bus/vme/vme.h287
-rw-r--r--src/devices/bus/vme/vme_fcisio.cpp409
-rw-r--r--src/devices/bus/vme/vme_fcisio.h49
-rw-r--r--src/devices/bus/vme/vme_fcscsi.cpp539
-rw-r--r--src/devices/bus/vme/vme_fcscsi.h73
-rw-r--r--src/devices/bus/vme/vme_mvme350.cpp10
-rw-r--r--src/devices/bus/vme/vme_mvme350.h2
-rw-r--r--src/devices/bus/vme/vme_mzr8105.cpp4
-rw-r--r--src/devices/bus/vme/vme_mzr8105.h2
-rw-r--r--src/devices/bus/vme/vme_mzr8300.cpp14
-rw-r--r--src/devices/bus/vme/vme_mzr8300.h2
-rw-r--r--src/devices/machine/hd63450.h4
-rw-r--r--src/mame/drivers/fccpu30.cpp112
-rw-r--r--src/mame/drivers/fcisio.cpp309
-rw-r--r--src/mame/drivers/fcscsi.cpp435
-rw-r--r--src/mame/drivers/mvme147.cpp239
-rw-r--r--src/mame/drivers/mzr8105.cpp5
-rw-r--r--src/mame/mame.lst9
-rw-r--r--src/mame/mess.flt2
20 files changed, 1387 insertions, 1302 deletions
diff --git a/src/devices/bus/vme/vme.cpp b/src/devices/bus/vme/vme.cpp
index a28e0e45b52..79e6d5a8687 100644
--- a/src/devices/bus/vme/vme.cpp
+++ b/src/devices/bus/vme/vme.cpp
@@ -68,9 +68,11 @@
#include "emu.h"
#include "vme.h"
-#include "bus/vme/vme_mzr8105.h"
+//#include "bus/vme/vme_mzr8105.h"
#include "bus/vme/vme_mzr8300.h"
#include "bus/vme/vme_mvme350.h"
+#include "bus/vme/vme_fcisio.h"
+#include "bus/vme/vme_fcscsi.h"
#define LOG_GENERAL 0x01
#define LOG_SETUP 0x02
@@ -96,25 +98,25 @@
// GLOBAL VARIABLES
//**************************************************************************
-const device_type VME_P1_SLOT = &device_creator<vme_p1_slot_device>;
+const device_type VME_SLOT = &device_creator<vme_slot_device>;
//-------------------------------------------------
-// vme_p1_slot_device - constructor
+// vme_slot_device - constructor
//-------------------------------------------------
-vme_p1_slot_device::vme_p1_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
- device_t(mconfig, VME_P1_SLOT, "VME_P1_SLOT", tag, owner, clock, "vme_p1_slot", __FILE__)
+vme_slot_device::vme_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ device_t(mconfig, VME_SLOT, "VME_SLOT", tag, owner, clock, "vme_slot", __FILE__)
,device_slot_interface(mconfig, *this)
- ,m_vme_p1_tag(nullptr)
- ,m_vme_p1_slottag(nullptr)
+ ,m_vme_tag(nullptr)
+ ,m_vme_slottag(nullptr)
,m_vme_j1_callback(*this)
{
}
-vme_p1_slot_device::vme_p1_slot_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
+vme_slot_device::vme_slot_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
device_t(mconfig, type, name, tag, owner, clock, shortname, source),
device_slot_interface(mconfig, *this)
- ,m_vme_p1_tag(nullptr)
- ,m_vme_p1_slottag(nullptr)
+ ,m_vme_tag(nullptr)
+ ,m_vme_slottag(nullptr)
,m_vme_j1_callback(*this)
{
}
@@ -122,27 +124,27 @@ vme_p1_slot_device::vme_p1_slot_device(const machine_config &mconfig, device_typ
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
-void vme_p1_slot_device::static_set_vme_p1_slot(device_t &device, const char *tag, const char *slottag)
+void vme_slot_device::static_set_vme_slot(device_t &device, const char *tag, const char *slottag)
{
LOG("%s %s - %s\n", FUNCNAME, tag, slottag);
- vme_p1_slot_device &vme_card = dynamic_cast<vme_p1_slot_device&>(device);
- vme_card.m_vme_p1_tag = tag;
- vme_card.m_vme_p1_slottag = slottag;
+ vme_slot_device &vme_card = dynamic_cast<vme_slot_device&>(device);
+ vme_card.m_vme_tag = tag;
+ vme_card.m_vme_slottag = slottag;
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
-void vme_p1_slot_device::device_start()
+void vme_slot_device::device_start()
{
- device_vme_p1_card_interface *dev = dynamic_cast<device_vme_p1_card_interface *>(get_card_device());
- LOG("%s %s - %s:%s\n", tag(), FUNCNAME, m_vme_p1_tag, m_vme_p1_slottag);
+ device_vme_card_interface *dev = dynamic_cast<device_vme_card_interface *>(get_card_device());
+ LOG("%s %s - %s:%s\n", tag(), FUNCNAME, m_vme_tag, m_vme_slottag);
if (dev)
{
- device_vme_p1_card_interface::static_set_vme_p1_tag(*dev, m_vme_p1_tag, m_vme_p1_slottag);
+ device_vme_card_interface::static_set_vme_tag(*dev, m_vme_tag, m_vme_slottag);
}
- // m_card = dynamic_cast<device_vme_p1_card_interface *>(get_card_device());
+ // m_card = dynamic_cast<device_vme_card_interface *>(get_card_device());
}
//-------------------------------------------------
@@ -150,7 +152,7 @@ void vme_p1_slot_device::device_start()
// operations now that the configuration is
// complete
//-------------------------------------------------
-void vme_p1_slot_device::device_config_complete()
+void vme_slot_device::device_config_complete()
{
LOG("%s %s\n", tag(), FUNCNAME);
}
@@ -158,7 +160,7 @@ void vme_p1_slot_device::device_config_complete()
//-------------------------------------------------
// P1 D8 read
//-------------------------------------------------
-READ8_MEMBER(vme_p1_slot_device::read8)
+READ8_MEMBER(vme_slot_device::read8)
{
uint16_t result = 0x00;
LOG("%s %s\n", tag(), FUNCNAME);
@@ -170,62 +172,65 @@ READ8_MEMBER(vme_p1_slot_device::read8)
//-------------------------------------------------
// P1 D8 write
//-------------------------------------------------
-WRITE8_MEMBER(vme_p1_slot_device::write8)
+WRITE8_MEMBER(vme_slot_device::write8)
{
LOG("%s %s\n", tag(), FUNCNAME);
// printf("%s %s\n", tag(), FUNCNAME);
// if (m_card) m_card->write8(space, offset, data);
}
+#if 0 // Disabled until we know how to make a board driver also a slot device
/* The following two slot collections be combined once we intriduce capabilities for each board */
-/* Usually a VME formware supports only a few boards so it will have its own slot collection defined */
+/* Usually a VME firmware supports only a few boards so it will have its own slot collection defined */
// Controller capable boards that can go into slot1 ( or has an embedded VME bus )
-SLOT_INTERFACE_START( vme_p1_slot1 )
- SLOT_INTERFACE("mzr8105", VME_MZR8105)
+SLOT_INTERFACE_START( vme_slot1 )
+// SLOT_INTERFACE("mzr8105", VME_MZR8105)
SLOT_INTERFACE_END
+#endif
// All boards that can be non-controller boards, eg not driving the VME CLK etc
-SLOT_INTERFACE_START( vme_p1_slots )
- SLOT_INTERFACE("mzr8105", VME_MZR8105)
+SLOT_INTERFACE_START( vme_slots )
SLOT_INTERFACE("mzr8300", VME_MZR8300)
SLOT_INTERFACE("mvme350", VME_MVME350)
+ SLOT_INTERFACE("fcisio1", VME_FCISIO1)
+ SLOT_INTERFACE("fcscsi1", VME_FCSCSI1)
SLOT_INTERFACE_END
//
// VME device P1
//
-const device_type VME_P1 = &device_creator<vme_p1_device>;
+const device_type VME = &device_creator<vme_device>;
-vme_p1_device::vme_p1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
- device_t(mconfig, VME_P1, "VME_P1", tag, owner, clock, "vme_p1", __FILE__)
+vme_device::vme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ device_t(mconfig, VME, "VME", tag, owner, clock, "vme", __FILE__)
{
}
-vme_p1_device::vme_p1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
+vme_device::vme_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
device_t(mconfig, type, name, tag, owner, clock, shortname, source)
{
}
-vme_p1_device::~vme_p1_device()
+vme_device::~vme_device()
{
m_device_list.detach_all();
}
-void vme_p1_device::device_start()
+void vme_device::device_start()
{
}
-void vme_p1_device::device_reset()
+void vme_device::device_reset()
{
}
-void vme_p1_device::add_vme_p1_card(device_vme_p1_card_interface *card)
+void vme_device::add_vme_card(device_vme_card_interface *card)
{
m_device_list.append(*card);
}
-void vme_p1_device::install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, uint32_t mask)
+void vme_device::install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, uint32_t mask)
{
cpu_device *m_maincpu = machine().device<cpu_device>("maincpu");
@@ -234,7 +239,7 @@ void vme_p1_device::install_device(offs_t start, offs_t end, read8_delegate rhan
switch(buswidth)
{
case 32:
- logerror("A32:D8 handler requires a P2 connector - not implemented yet\n");
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
case 24:
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask);
@@ -243,11 +248,11 @@ void vme_p1_device::install_device(offs_t start, offs_t end, read8_delegate rhan
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0xffff));
break;
default:
- fatalerror("VME_P1 D8: Bus width %d not supported\n", buswidth);
+ fatalerror("VME D8: Bus width %d not supported\n", buswidth);
}
}
-void vme_p1_device::install_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, uint32_t mask)
+void vme_device::install_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, uint32_t mask)
{
cpu_device *m_maincpu = machine().device<cpu_device>("maincpu");
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
@@ -255,7 +260,7 @@ void vme_p1_device::install_device(offs_t start, offs_t end, read16_delegate rha
switch(buswidth)
{
case 32:
- logerror("A32:D16 handler requires a P2 connector - not implemented yet\n");
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
case 24:
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask);
@@ -264,11 +269,11 @@ void vme_p1_device::install_device(offs_t start, offs_t end, read16_delegate rha
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0xffff));
break;
default:
- fatalerror("VME_P1 D16: Bus width %d not supported\n", buswidth);
+ fatalerror("VME D16: Bus width %d not supported\n", buswidth);
}
}
-void vme_p1_device::install_device(offs_t start, offs_t end, read32_delegate rhandler, write32_delegate whandler, uint32_t mask)
+void vme_device::install_device(offs_t start, offs_t end, read32_delegate rhandler, write32_delegate whandler, uint32_t mask)
{
cpu_device *m_maincpu = machine().device<cpu_device>("maincpu");
int buswidth = m_maincpu->space_config(AS_PROGRAM)->m_databus_width;
@@ -276,29 +281,27 @@ void vme_p1_device::install_device(offs_t start, offs_t end, read32_delegate rha
switch(buswidth)
{
case 32:
- logerror("A32:D32 handler requires a P2 connector - not implemented yet\n");
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
case 24:
- logerror("A24:D32 handler requires a P2 connector - not implemented yet\n");
- // m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask);
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, mask);
break;
case 16:
- logerror("A16:D32 handler requires a P2 connector - not implemented yet\n");
- // m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0xffff));
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(start, end, rhandler, whandler, (uint16_t)(mask & 0xffff));
break;
default:
- fatalerror("VME_P1 D32: Bus width %d not supported\n", buswidth);
+ fatalerror("VME D32: Bus width %d not supported\n", buswidth);
}
}
//
// Card interface
//
-device_vme_p1_card_interface::device_vme_p1_card_interface(const machine_config &mconfig, device_t &device)
+device_vme_card_interface::device_vme_card_interface(const machine_config &mconfig, device_t &device)
: device_slot_card_interface(mconfig, device)
- ,m_vme_p1(nullptr)
- ,m_vme_p1_tag(nullptr)
- ,m_vme_p1_slottag(nullptr)
+ ,m_vme(nullptr)
+ ,m_vme_tag(nullptr)
+ ,m_vme_slottag(nullptr)
,m_slot(0)
,m_next(nullptr)
{
@@ -306,41 +309,40 @@ device_vme_p1_card_interface::device_vme_p1_card_interface(const machine_config
LOG("%s %s\n", m_device->tag(), FUNCNAME);
}
-device_vme_p1_card_interface::~device_vme_p1_card_interface()
+device_vme_card_interface::~device_vme_card_interface()
{
LOG("%s %s\n", m_device->tag(), FUNCNAME);
}
-void device_vme_p1_card_interface::static_set_vme_p1_tag(device_t &device, const char *tag, const char *slottag)
+void device_vme_card_interface::static_set_vme_tag(device_t &device, const char *tag, const char *slottag)
{
- device_vme_p1_card_interface &vme_p1_card = dynamic_cast<device_vme_p1_card_interface &>(device);
- vme_p1_card.m_vme_p1_tag = tag;
- vme_p1_card.m_vme_p1_slottag = slottag;
+ device_vme_card_interface &vme_card = dynamic_cast<device_vme_card_interface &>(device);
+ vme_card.m_vme_tag = tag;
+ vme_card.m_vme_slottag = slottag;
}
-void device_vme_p1_card_interface::set_vme_p1_device()
+void device_vme_card_interface::set_vme_device()
{
LOG("%s %s\n", m_device->tag(), FUNCNAME);
- m_vme_p1 = dynamic_cast<vme_p1_device *>(device().machine().device(m_vme_p1_tag));
- // printf("*** %s %sfound\n", m_vme_p1_tag, m_vme_p1 ? "" : "not ");
- if (m_vme_p1) m_vme_p1->add_vme_p1_card(this);
+ m_vme = dynamic_cast<vme_device *>(device().machine().device(m_vme_tag));
+ // printf("*** %s %sfound\n", m_vme_tag, m_vme ? "" : "not ");
+ if (m_vme) m_vme->add_vme_card(this);
}
/* VME D8 accesses */
-READ8_MEMBER(device_vme_p1_card_interface::read8)
+READ8_MEMBER(device_vme_card_interface::read8)
{
uint8_t result = 0x00;
LOG("%s %s Offset:%08x\n", m_device->tag(), FUNCNAME, offset);
return result;
}
-WRITE8_MEMBER(device_vme_p1_card_interface::write8)
+WRITE8_MEMBER(device_vme_card_interface::write8)
{
LOG("%s %s Offset:%08x\n", m_device->tag(), FUNCNAME, offset);
}
//--------------- P2 connector below--------------------------
-#if 0
/*
The VME P2 connector only specifies the mid row B of the connector
and leaves row A and C to be system specific. This has resulted in
@@ -364,56 +366,3 @@ http://www.interfacebus.com/Design_Connector_VME_P2_Buses.html
TODO: Figure out a good way to let all these variants coexist and interconnect in a VME system
*/
-//**************************************************************************
-// GLOBAL VARIABLES
-//**************************************************************************
-
-const device_type VME_P2_SLOT = &device_creator<vme_p2_slot_device>;
-
-//-------------------------------------------------
-// vme_p2_slot_device - constructor
-//-------------------------------------------------
-vme_p2_slot_device::vme_p2_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
- device_t(mconfig, VME_P2_SLOT, "VME P2 connector", tag, owner, clock, "vme_p2_connector", __FILE__),
- device_slot_interface(mconfig, *this),
- m_vme_j2_callback(*this)
-{
-}
-
-void vme_p2_slot_device::device_start()
-{
- m_vme_p2 = dynamic_cast<device_vme_p2_interface *>(get_card_device());
-}
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void vme_p2_slot_device::device_config_complete()
-{
- // set brief and instance name
- update_names();
-}
-
-//-------------------------------------------------
-// P2 read
-//-------------------------------------------------
-READ32_MEMBER(vme_p2_slot_device::write32)
-{
- uint8_t result = 0x00;
- if (m_vme_p2)
- result = m_vme_p2->read32(space, offset);
- return result;
-}
-
-//-------------------------------------------------
-// P2 write
-//-------------------------------------------------
-WRITE32_MEMBER(vme_p2_slot_device::read32)
-{
- if (m_vme_p2)
- m_vme_p2->write32(space, offset, data);
-}
-#endif
diff --git a/src/devices/bus/vme/vme.h b/src/devices/bus/vme/vme.h
index 8c22c828ae5..6103379a4ac 100644
--- a/src/devices/bus/vme/vme.h
+++ b/src/devices/bus/vme/vme.h
@@ -60,14 +60,14 @@
// Callbacks to the board from the VME bus comes through here
#define MCFG_VME_J1_CB(_devcb) \
- devcb = &vme_p1_slot_device::static_set_vme_j1_callback(*device, DEVCB_##_devcb);
+ devcb = &vme_slot_device::static_set_vme_j1_callback(*device, DEVCB_##_devcb);
-SLOT_INTERFACE_EXTERN(vme_p1_slot1);
-SLOT_INTERFACE_EXTERN(vme_p1_slots);
+//SLOT_INTERFACE_EXTERN(vme_slot1); // Disabled until we know how to combine a board driver and a slot device.
+SLOT_INTERFACE_EXTERN(vme_slots);
-class device_vme_p1_card_interface; // This interface is standardized
+class device_vme_card_interface; // This interface is standardized
-class vme_p1_slot_device : public device_t,
+class vme_slot_device : public device_t,
public device_slot_interface
{
public:
@@ -90,44 +90,44 @@ public:
};
// construction/destruction
- vme_p1_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ vme_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- vme_p1_slot_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
+ vme_slot_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
- template<class _Object> static devcb_base &static_set_vme_j1_callback(device_t &device, _Object object) { return downcast<vme_p1_slot_device &>(device).m_vme_j1_callback.set_callback(object); }
+ template<class _Object> static devcb_base &static_set_vme_j1_callback(device_t &device, _Object object) { return downcast<vme_slot_device &>(device).m_vme_j1_callback.set_callback(object); }
// device-level overrides
virtual void device_start() override;
virtual void device_config_complete() override;
- static void static_set_vme_p1_slot(device_t &device, const char *tag, const char *slottag);
+ static void static_set_vme_slot(device_t &device, const char *tag, const char *slottag);
// configuration
- const char *m_vme_p1_tag, *m_vme_p1_slottag;
+ const char *m_vme_tag, *m_vme_slottag;
virtual DECLARE_READ8_MEMBER(read8);
virtual DECLARE_WRITE8_MEMBER(write8);
// callbacks
devcb_write_line m_vme_j1_callback;
- device_vme_p1_card_interface *m_card;
+ device_vme_card_interface *m_card;
private:
};
-extern const device_type VME_P1;
+extern const device_type VME;
-#define MCFG_VME_P1_DEVICE_ADD(_tag) \
- MCFG_DEVICE_ADD(_tag, VME_P1, 0)
+#define MCFG_VME_DEVICE_ADD(_tag) \
+ MCFG_DEVICE_ADD(_tag, VME, 0)
-class vme_p1_card_interface;
+class vme_card_interface;
-class vme_p1_device : public device_t
+class vme_device : public device_t
{
public:
- vme_p1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- vme_p1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
- ~vme_p1_device();
+ vme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ vme_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
+ ~vme_device();
- void add_vme_p1_card(device_vme_p1_card_interface *card);
+ void add_vme_card(device_vme_card_interface *card);
void install_device(offs_t start, offs_t end, read8_delegate rhandler, write8_delegate whandler, uint32_t mask);
void install_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler, uint32_t mask);
void install_device(offs_t start, offs_t end, read32_delegate rhandler, write32_delegate whandler, uint32_t mask);
@@ -135,32 +135,32 @@ protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
- simple_list<device_vme_p1_card_interface> m_device_list;
+ simple_list<device_vme_card_interface> m_device_list;
};
// device type definition
-extern const device_type VME_P1_SLOT;
+extern const device_type VME_SLOT;
-class device_vme_p1_card_interface : public device_slot_card_interface
+class device_vme_card_interface : public device_slot_card_interface
{
public:
// construction/destruction
- device_vme_p1_card_interface(const machine_config &mconfig, device_t &device);
- virtual ~device_vme_p1_card_interface();
- void set_vme_p1_device();
+ device_vme_card_interface(const machine_config &mconfig, device_t &device);
+ virtual ~device_vme_card_interface();
+ void set_vme_device();
virtual DECLARE_READ8_MEMBER(read8);
virtual DECLARE_WRITE8_MEMBER(write8);
device_t *m_device;
// inline configuration
- static void static_set_vme_p1_tag(device_t &device, const char *tag, const char *slottag);
- vme_p1_device *m_vme_p1;
- const char *m_vme_p1_tag, *m_vme_p1_slottag;
+ static void static_set_vme_tag(device_t &device, const char *tag, const char *slottag);
+ vme_device *m_vme;
+ const char *m_vme_tag, *m_vme_slottag;
int m_slot;
- device_vme_p1_card_interface *m_next;
+ device_vme_card_interface *m_next;
//
// Address Modifiers
@@ -196,231 +196,12 @@ public:
};
};
-SLOT_INTERFACE_EXTERN(vme_p1_slot1);
-
-#define MCFG_VME_P1_SLOT_ADD(_tag, _slot_tag, _slot_intf,_def_slot) \
- MCFG_DEVICE_ADD(_slot_tag, VME_P1_SLOT, 0) \
+#define MCFG_VME_SLOT_ADD(_tag, _slot_tag, _slot_intf,_def_slot) \
+ MCFG_DEVICE_ADD(_slot_tag, VME_SLOT, 0) \
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
- vme_p1_slot_device::static_set_vme_p1_slot(*device, _tag, _slot_tag);
-
-#define MCFG_VME_P1_SLOT_REMOVE(_tag) \
- MCFG_DEVICE_REMOVE(_tag)
-
-
-#if 0
-// Callbacks to the board from the VME bus comes through here
-#define MCFG_VME_J2_CB(_devcb) \
- devcb = &vme_p2_slot_device::static_set_j2_callback(*device, DEVCB_##_devcb);
-
-class device_vme_p2_interface; // This interface often has custom/propritary A and C rows
-
-class vme_p2_slot_device : public device_t,
- public device_slot_interface
-{
-public:
-
- // construction/destruction
- vme_p2_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-
- template<class _Object> static devcb_base &static_set_vme_j2_callback(device_t &device, _Object object) { return downcast<vme_p2_slot_device &>(device).m_vme_j2_callback.set_callback(object); }
-
- // device-level overrides
- virtual void device_start() override;
-
- // callbacks
- devcb_write_line m_vme_j2_callback;
-private:
- device_vme_p2_interface *m_vme_p2;
-};
-
-// device type definition
-extern const device_type VME_P2_SLOT;
-
-class device_vme_p2_interface : public device_slot_card_interface
-{
-public:
- // construction/destruction
- device_vme_p2_interface(const machine_config &mconfig, device_t &device);
- virtual ~device_vme_p2_interface();
+ vme_slot_device::static_set_vme_slot(*device, _tag, _slot_tag);
- virtual DECLARE_READ32_MEMBER(read32);
- virtual DECLARE_WRITE32_MEMBER(write32);
-};
-
-#define MCFG_VME_P2_ADD(_tag,_slot_intf,_def_slot) \
- MCFG_DEVICE_ADD(_tag, VME_P2_SLOT, 0) \
- MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
-
-#define MCFG_VME_P2_REMOVE(_tag) \
+#define MCFG_VME_SLOT_REMOVE(_tag) \
MCFG_DEVICE_REMOVE(_tag)
-#endif
-#if 0
-//**************************************************************************
-// INTERFACE CONFIGURATION MACROS
-//**************************************************************************
-
-#define MCFG_VME16_SLOT_ADD(_vmetag, _tag, _slot_intf, _def_slot, _fixed) \
- MCFG_DEVICE_ADD(_tag, VME16_SLOT, 0) \
- MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _fixed) \
- vme16_slot_device::static_set_vme16_slot(*device, _vmetag, _tag);
-
-//**************************************************************************
-// TYPE DEFINITIONS
-//**************************************************************************
-
-class device_vme16_card_interface;
-
-//
-// The VME device
-//
-class vme_device : public device_t
-,public device_memory_interface
-{
-public:
- // construction/destruction
- vme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- vme_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
-
- // inline configuration
- static void static_set_cputag(device_t &device, const char *tag);
-
- void install_device(offs_t start, offs_t end, offs_t mask, offs_t mirror, read8_delegate rhandler, write8_delegate whandler);
- void install_device(offs_t start, offs_t end, offs_t mask, offs_t mirror, read16_delegate rhandler, write16_delegate whandler);
- void install_device(offs_t start, offs_t end, offs_t mask, offs_t mirror, read32_delegate rhandler, write32_delegate whandler);
- void install_bank(offs_t start, offs_t end, offs_t mask, offs_t mirror, const char *tag, uint8_t *data);
- void unmap_bank(offs_t start, offs_t end, offs_t mask, offs_t mirror);
- void install_rom(device_t *dev, offs_t start, offs_t end, offs_t mask, offs_t mirror, const char *tag, const char *region);
- void install_memory(offs_t start, offs_t end, offs_t mask, offs_t mirror, read8_delegate rhandler, write8_delegate whandler);
- void set_irq_line(int slot, int state);
-protected:
- void install_space(address_spacenum spacenum, offs_t start, offs_t end, offs_t mask, offs_t mirror, read8_delegate rhandler, write8_delegate whandler);
-
- // address spaces
- address_space *m_prgspace;
- int m_prgwidth;
- bool m_allocspaces;
-
- // device-level overrides
- virtual void device_start() override;
- virtual void device_reset() override;
-
- // internal state
- cpu_device *m_maincpu;
- const address_space_config m_program16_config;
- const address_space_config m_program24_config;
- const address_space_config m_program32_config;
-};
-
-class vme16_device : public vme_device
-{
- public:
- vme16_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- vme16_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
-
- virtual const address_space_config *memory_space_config(address_spacenum spacenum) const override;
-
- DECLARE_READ16_MEMBER ( vme_r );
- DECLARE_WRITE16_MEMBER( vme_w );
-
- void add_vme16_card(device_vme16_card_interface *card);
-};
-
-class vme24_device : public vme_device
-{
- public:
- vme24_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- vme24_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
-
- virtual const address_space_config *memory_space_config(address_spacenum spacenum) const override;
-
- DECLARE_READ16_MEMBER ( vme_r );
- DECLARE_WRITE16_MEMBER( vme_w );
-
- void add_vme24_card(device_vme16_card_interface *card);
-};
-
-class vme32_device : public vme_device
-{
- public:
- vme32_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- vme32_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
-
- virtual const address_space_config *memory_space_config(address_spacenum spacenum) const override;
-
- DECLARE_READ32_MEMBER ( vme_r );
- DECLARE_WRITE32_MEMBER( vme_w );
-
- // void add_vme32_card(device_vme16_card_interface *card);
-};
-
-//
-// The SLOT device
-//
-class vme16_slot_device : public device_t,
- public device_slot_interface
-{
-public:
- // construction/destruction
- vme16_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- vme16_slot_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
- virtual ~vme16_slot_device();
-
- //template<class _Object> static devcb_base &set_out_irq2_callback(device_t &device, _Object object) { return downcast<vme16_slot_device &>(device).m_out_irq2_cb.set_callback(object); }
-
- //DECLARE_WRITE_LINE_MEMBER( irq2_w );
-
- // inline configuration
- static void static_set_vme16_slot(device_t &device, const char *tag, const char *slottag);
-
- // device-level overrides
- virtual void device_start() override;
- virtual void device_reset() override;
-
-protected:
-
- // configuration
- const char *m_vme16_tag, *m_vme16_slottag;
-
- device_vme16_card_interface *m_slot;
-};
-
-
-// device type definition
-extern const device_type VME16_SLOT;
-extern const device_type VME16;
-extern const device_type VME24;
-extern const device_type VME32;
-
-//
-// The CARD device
-//
-class device_vme16_card_interface : public device_slot_card_interface
-{
- friend class vme16_device;
-public:
- // construction/destruction
- device_vme16_card_interface(const machine_config &mconfig, device_t &device);
- virtual ~device_vme16_card_interface();
-
- device_vme16_card_interface *next() const { return m_next; }
-
- void set_vme_device();
-
- // inline configuration
- static void static_set_vmebus(device_t &device, device_t *vme_device);
-public:
- vme16_device *m_vme;
- device_t *m_vme_dev;
- device_vme16_card_interface *m_next;
-};
-
-#if 0
- // reset
- virtual void vme16_reset_w() { };
-
-};
-#endif
-#endif
-
#endif /* VME_H_ */
diff --git a/src/devices/bus/vme/vme_fcisio.cpp b/src/devices/bus/vme/vme_fcisio.cpp
new file mode 100644
index 00000000000..cdbcf13908c
--- /dev/null
+++ b/src/devices/bus/vme/vme_fcisio.cpp
@@ -0,0 +1,409 @@
+// license:BSD-3-Clause
+// copyright-holders:Joakim Larsson Edstrom
+/***************************************************************************
+ *
+ * 10/06/2016
+ * The ISIO board is a VME slave board that reads command and returns results through dual ported RAM to the VME bus.
+ *
+ * ISIO-1: page 385 http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
+ * ISIO-2: page 395 http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
+ *
+ * ||
+ * || ||
+ * ||||--||
+ * ||||--||
+ * || ||__________________________________________________________ ___
+ * || |_| |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | |VME|
+ * || | | |
+ * || | |P1 |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || |_| |
+ * || |___|
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |___
+ * || _| |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | |VME|
+ * || | | |
+ * || | |P2 |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || |_| |
+ * || |___|
+ * || ||------------------------------------------------------------+-+
+ * ||||--||
+ * ||||--||
+ * ||
+ *
+ * History of Force Computers
+ *------------------------------------------------------------------------
+ * See fccpu30.cpp
+ *
+ * Description from datasheet etc
+ * ------------------------------
+ * ISIO-1/1A ISIO-2/2A Intelligent Serial I/O Boards
+ * - 68010 for local handling and control
+ * - 8 Channel, multi-protocol serial I/O controller board
+ * - Onboard RS-232 tranceiver. ISIO-2x: optional RS-422 transiever
+ * - ISIO-x: 128Kb ISIO-xA: 512Kb - No Wait State Dual Ported RAM
+ * - 4 fully software programmable VME bus interrupt channels
+ * - Powerful handling firmware(!)
+ * - VMEbus IEEE 1014 compatibility: A24:D16, D8, SYSFAIL (jumper)
+ * - Local watchdog timer
+ *
+ * Local address map - guessed/rev-enged
+ * ----------------------------------------------------------
+ * Address Range Description
+ * ----------------------------------------------------------
+ * 000000 - 000007 Initialisation vectors from system EPROM
+ * 000008 - 01FFFF Local SRAM
+ * E00000 - E001FF DUSCC0
+ * E20000 - E001FF DUSCC0
+ * E40000 - E001FF DUSCC0
+ * E60000 - E001FF DUSCC0
+ * E80000 - E80DFF PI/T
+ * f00000 - F70000 EPROMs
+ * ----------------------------------------------------------
+ *
+ * VME side A24 address map - Dual ported RAM
+ * ----------------------------------------------------------
+ * Offset Range Description
+ * ----------------------------------------------------------
+ * 000000 - 0007FF BIM
+ * 000800 - 000FFF Status registers
+ * 001000 - 0017FF Read generates local interrupt
+ * 001800 - 001FFF Read generates local reset
+ * 002000 - 007FFF Reserved for local CPU
+ * 008000 - 0080FF 16 command channels for 4 x DUSCC Rx/Tx (A/B)
+ * 008100 - 01FFFF 16 data arrays for the I/O channels
+ * ----------------------------------------------------------
+ *
+ * Interrupt sources
+ * ----------------------------------------------------------
+ * Description Device Lvl IRQ VME board
+ * /Board Vector Address
+ * ----------------------------------------------------------
+ * On board Sources
+ * ----------------------------------------------------------
+ *
+ * TODO:
+ * - add PIT and DUSCC interrupts
+ * - add port mapping to self test jumper
+ * - add VME bus driver
+ * - write and map a 68153 device (accessable from VME side)
+ *
+ * Status: passes Self test and get stuck on no ticks for the scheduler.
+ * Schematics of the IRQ routing needed or a good trace of how the
+ * PIT and DUSCCs are hooked up to the BIM to get further.
+ *
+ ****************************************************************************/
+#define TODO "Driver for 68153 BIM device needed\n"
+
+#include "emu.h"
+#include "cpu/m68000/m68000.h"
+#include "machine/scnxx562.h"
+#include "machine/68230pit.h"
+#include "bus/rs232/rs232.h"
+#include "machine/clock.h"
+#include "vme_fcisio.h"
+
+#define LOG_GENERAL 0x01
+#define LOG_SETUP 0x02
+#define LOG_PRINTF 0x04
+
+#define VERBOSE 0 //(LOG_PRINTF | LOG_SETUP | LOG_GENERAL)
+
+#define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0)
+#define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0)
+
+#define LOG(...) LOGMASK(LOG_GENERAL, __VA_ARGS__)
+#define LOGSETUP(...) LOGMASK(LOG_SETUP, __VA_ARGS__)
+
+#if VERBOSE & LOG_PRINTF
+#define logerror printf
+#endif
+
+#ifdef _MSC_VER
+#define FUNCNAME __func__
+#else
+#define FUNCNAME __PRETTY_FUNCTION__
+#endif
+
+//**************************************************************************
+// GLOBAL VARIABLES
+//**************************************************************************
+
+const device_type VME_FCISIO1 = &device_creator<vme_fcisio1_card_device>;
+
+#define CPU_CLOCK XTAL_20MHz /* HCJ */
+#define DUSCC_CLOCK XTAL_14_7456MHz /* HCJ */
+
+static ADDRESS_MAP_START (fcisio1_mem, AS_PROGRAM, 16, vme_fcisio1_card_device)
+ ADDRESS_MAP_UNMAP_HIGH
+ AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* Vectors mapped from System EPROM */
+ AM_RANGE (0x000000, 0x01ffff) AM_RAM /* SRAM */
+ AM_RANGE (0xe00000, 0xe001ff) AM_DEVREADWRITE8("duscc0", duscc68562_device, read, write, 0x00ff)
+ AM_RANGE (0xe20000, 0xe201ff) AM_DEVREADWRITE8("duscc1", duscc68562_device, read, write, 0x00ff)
+ AM_RANGE (0xe40000, 0xe401ff) AM_DEVREADWRITE8("duscc2", duscc68562_device, read, write, 0x00ff)
+ AM_RANGE (0xe60000, 0xe601ff) AM_DEVREADWRITE8("duscc3", duscc68562_device, read, write, 0x00ff)
+ AM_RANGE (0xe80000, 0xe80dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0x00ff)
+ AM_RANGE (0xf00000, 0xf7ffff) AM_ROM /* System EPROM Area 32Kb DEBUGGER supplied */
+// AM_RANGE (0xc40000, 0xc800ff) AM_READWRITE8 (not_implemented_r, not_implemented_w, 0xffff) /* Dummy mapping af address area to display message */
+ADDRESS_MAP_END
+
+/*
+ * Machine configuration
+ */
+static MACHINE_CONFIG_FRAGMENT (fcisio1)
+ /* basic machine hardware */
+ MCFG_CPU_ADD ("maincpu", M68010, CPU_CLOCK / 2)
+ MCFG_CPU_PROGRAM_MAP (fcisio1_mem)
+
+ MCFG_DUSCC68562_ADD("duscc0", DUSCC_CLOCK, 0, 0, 0, 0 )
+ MCFG_DUSCC_OUT_TXDA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
+ MCFG_DUSCC_OUT_DTRA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_dtr))
+ MCFG_DUSCC_OUT_RTSA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_rts))
+
+ MCFG_RS232_PORT_ADD ("rs232trm", default_rs232_devices, "terminal")
+ MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc0", duscc68562_device, rxa_w))
+ MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("duscc0", duscc68562_device, ctsa_w))
+// MCFG_DEVICE_CARD_DEVICE_INPUT_DEFAULTS("terminal", fcisio_terminal)
+
+ MCFG_DUSCC68562_ADD("duscc1", DUSCC_CLOCK, 0, 0, 0, 0 )
+ MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
+ MCFG_DUSCC68562_ADD("duscc3", DUSCC_CLOCK, 0, 0, 0, 0 )
+
+ MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_20MHz / 2)
+ MCFG_PIT68230_PB_INPUT_CB(READ8(vme_fcisio1_card_device, config_rd))
+MACHINE_CONFIG_END
+
+/* ROM definitions */
+ROM_START (fcisio1)
+ ROM_REGION (0x1000000, "maincpu", 0)
+
+/* ISIO ROM:s v2.1 information
+ * PIT setup sequence
+ * 00 -> REG_PGCR
+ * 18 -> REG_PSRR
+ * 0f -> Reg PADDR
+ * 0f -> REG_PBDDR
+ * fa -> REG_PACR
+ * 0f -> REG_PADDR
+ * fa -> REG_PBCR
+ * ff -> REG_PBDR
+ * 0f -> REG_PBDDR
+ * 10 -> REG_PGCR
+ * ff -> REG_PCDR
+ * 17 -> REG_PCDDR
+ * 40 -> Reg PIVR
+ * 00 -> REG_TCR - timer disabled, all C pins, use preload, CLK and prescaler are used
+ * a0 -> REG_TCR - timer disabled, The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
+ * output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
+ * pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge input.
+ * 00 -> Reg 0x12
+ * 00 -> REG_CPRH
+ * 09 -> REG_CPRM
+ * 00 -> REG_CPRL
+ * 00 -> Reg 0x16
+ * 00 -> Reg 0x17
+ * 09 -> Reg 0x18
+ * 00 -> Reg 0x19
+ * 1d -> Reg TIVR
+ * 0f <- REG_PBDR
+ * 0e -> REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0d -> REG_PDBR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f -> REG_PBDR
+ * 0f <- REG_PBDR
+ * 0b -> REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f -> REG_PBDR
+ * 0f <- REG_PBDR
+ * 0f -> REG_PBDR
+ * 0f <- REG_PBDR
+ * 00 <- REG_PCDR
+ * 00 -> REG_PCDR
+ * ------- repeated 16 times -------------------
+ * a1 -> REG_TCR - timer enabled, The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
+ * output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
+ * pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge input.
+ * ?? <- Reg 0x0c
+ * ---------------------------------------------
+ *
+ * DUSCC0 channel A setup sequence
+ * 0f 00 -> REG_CCR - Reset Tx
+ * 0f 40 -> REG_CCR - Reset Rx
+ * 00 07 -> REG_CMR1 - Async mode
+ * 01 38 -> REG_CMR2 - Normal polled or interrupt mode, no DMA
+ * 02 00 -> REG_S1R - SYN1, Secondary Address 1 Register, 0 = no sync
+ * 03 00 -> REG_S2R - SYN2, only used in COP dual Sync mode but alao 0 = no sync
+ * 04 7F -> REG_TPR - Tx 8 bits, CTS and RTS, 1 STOP bit
+ * 05 3d -> REG_TTR - Tx BRG 9600 (assuming a 14.7456 crystal)
+ * 06 1b -> REG_RPR - Rx RTS, 8 bits, no DCD, no parity
+ * 07 2d -> REG_RTR - Rx BRG 9600 (assuming a 14.7456 crystal)
+ * 0b e1 -> REG_OMR - RTS high, OUT1 = OUT2 = high, RxRdy asserted for each character,
+ * TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
+ * 0a 00 -> REG_CTCR - Counter/Timer control register 00 = Zero Det Int: disabled, Zero Det Control: preset,
+ * Output Control: square, Prescaler: 1, Clock Source: RTxC pin
+ * 09 00 -> REG_CTPRL - Counter/Timer Prescaler Register Low = 0
+ * 08 00 -> REG_CTPRH - Counter/Timer Prescaler Register High = 0
+ * 0f 00 -> REG_CCR - Reset Tx
+ * 0f 02 -> REG_CCR - Enable Tx
+ * 0f 40 -> REG_CCR - Reset Rx
+ * 0f 42 -> REG_CCR - Enable Rx
+ * 0f 02 -> REG_CCR - Enable Tx
+ * 0f 42 -> REG_CCR - Enable Rx
+ * 0e 27 -> REG_PCR - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
+ * 1c 10 -> REG_IER - Interrupt Enable Register: RxRdy generates interrupt
+ * ... chan B setup with same data....
+ * ---- DUSCC0 to DUSCC3, setup with same data except at the end of each setup:
+ * 1e 1c -> DUSCC0 REG_IVR -
+ * 1e 1b -> DUSCC1 REG_IVR
+ * 1e 1a -> DUSCC2 REG_IVR
+ * 1e 19 -> DUSCC3 REG_IVR
+ */
+ ROM_LOAD16_BYTE ("ISIO-1_V2.1_L.BIN", 0xf00001, 0x4000, CRC (0d47d80f) SHA1 (541b55966f464c1cf686e36998650720950a2242))
+ ROM_LOAD16_BYTE ("ISIO-1_V2.1_U.BIN", 0xf00000, 0x4000, CRC (67986768) SHA1 (215f7ff90d9dbe2bea54510e3722fb33d4e54193))
+ROM_END
+
+machine_config_constructor vme_fcisio1_card_device::device_mconfig_additions() const
+{
+ LOG("%s %s\n", tag(), FUNCNAME);
+ return MACHINE_CONFIG_NAME( fcisio1 );
+}
+
+const tiny_rom_entry *vme_fcisio1_card_device::device_rom_region() const
+{
+ LOG("%s\n", FUNCNAME);
+ return ROM_NAME( fcisio1 );
+}
+
+//**************************************************************************
+// LIVE DEVICE
+//**************************************************************************
+vme_fcisio1_card_device::vme_fcisio1_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
+ device_t(mconfig, type, name, tag, owner, clock, shortname, source)
+ ,device_vme_card_interface(mconfig, *this)
+ ,m_maincpu (*this, "maincpu")
+ ,m_duscc0(*this, "duscc0")
+ ,m_duscc1(*this, "duscc1")
+ ,m_duscc2(*this, "duscc2")
+ ,m_duscc3(*this, "duscc3")
+ ,m_pit (*this, "pit")
+{
+ LOG("%s\n", FUNCNAME);
+}
+
+vme_fcisio1_card_device::vme_fcisio1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ device_t(mconfig, VME_FCISIO1, "Force Computer SYS68K/ISIO-1/2 Intelligent Serial I/O Board", tag, owner, clock, "fcisio1", __FILE__)
+ ,device_vme_card_interface(mconfig, *this)
+ ,m_maincpu(*this, "maincpu")
+ ,m_duscc0(*this, "duscc0")
+ ,m_duscc1(*this, "duscc1")
+ ,m_duscc2(*this, "duscc2")
+ ,m_duscc3(*this, "duscc3")
+ ,m_pit (*this, "pit")
+{
+ LOG("%s %s\n", tag, FUNCNAME);
+}
+
+/* Start it up */
+void vme_fcisio1_card_device::device_start()
+{
+ LOG("%s\n", FUNCNAME);
+ set_vme_device();
+
+ /* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
+ m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0xf00000);
+
+#if 0 // TODO: Setup VME access handlers for shared memory area
+ uint32_t base = 0xFFFF5000;
+ m_vme->install_device(base + 0, base + 1, // Channel B - Data
+ read8_delegate(FUNC(z80sio_device::db_r), subdevice<z80sio_device>("pit")), write8_delegate(FUNC(z80sio_device::db_w), subdevice<z80sio_device>("pit")), 0x00ff);
+ m_vme->install_device(base + 2, base + 3, // Channel B - Control
+ read8_delegate(FUNC(z80sio_device::cb_r), subdevice<z80sio_device>("pit")), write8_delegate(FUNC(z80sio_device::cb_w), subdevice<z80sio_device>("pit")), 0x00ff);
+#endif
+
+}
+
+void vme_fcisio1_card_device::device_reset()
+{
+ LOG("%s\n", FUNCNAME);
+}
+
+/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
+READ16_MEMBER (vme_fcisio1_card_device::bootvect_r){
+ return m_sysrom [offset];
+}
+
+READ8_MEMBER (vme_fcisio1_card_device::not_implemented_r){
+ static int been_here = 0;
+ if (!been_here++){
+ logerror(TODO);
+ printf(TODO);
+ }
+ return (uint8_t) 0;
+}
+
+WRITE8_MEMBER (vme_fcisio1_card_device::not_implemented_w){
+ static int been_here = 0;
+ if (!been_here++){
+ logerror(TODO);
+ printf(TODO);
+ }
+ return;
+}
+
+// TODO: Get a manual to understand the config options for real
+READ8_MEMBER (vme_fcisio1_card_device::config_rd){
+ uint8_t ret = 0;
+ LOG("%s\n", FUNCNAME);
+
+ // Port B bit #7, 0x80 Self test bit, choose either of these two lines
+ ret &= ~0x80; // 0 = selftest
+ // ret |= 0x80; // 1 = no selftest
+
+ return ret;
+}
+
+// This info isn't kept in a card driver atm so storing it as a comment for later use
+// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
+//COMP( 1986, fcisio1, 0, 0, fcisio1, fcisio1, driver_device, 0, "Force Computers Gmbh", "SYS68K/ISIO-1", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
diff --git a/src/devices/bus/vme/vme_fcisio.h b/src/devices/bus/vme/vme_fcisio.h
new file mode 100644
index 00000000000..1a29283a860
--- /dev/null
+++ b/src/devices/bus/vme/vme_fcisio.h
@@ -0,0 +1,49 @@
+// license:BSD-3-Clause
+// copyright-holders:Joakim Larsson Edstrom
+#ifndef VME_FCISIO_H
+#define VME_FCISIO_H
+#pragma once
+
+#include "machine/scnxx562.h"
+#include "machine/68230pit.h"
+#include "bus/vme/vme.h"
+
+extern const device_type VME_FCISIO1;
+
+class vme_fcisio1_card_device :
+ public device_t
+ ,public device_vme_card_interface
+{
+public:
+ vme_fcisio1_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
+ vme_fcisio1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ // optional information overrides
+ virtual machine_config_constructor device_mconfig_additions() const override;
+ virtual const tiny_rom_entry *device_rom_region() const override;
+
+ DECLARE_READ16_MEMBER (bootvect_r);
+ DECLARE_READ8_MEMBER (config_rd);
+
+ /* Dummy driver routines */
+ DECLARE_READ8_MEMBER (not_implemented_r);
+ DECLARE_WRITE8_MEMBER (not_implemented_w);
+
+protected:
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+private:
+ required_device<cpu_device> m_maincpu;
+ required_device<duscc68562_device> m_duscc0;
+ required_device<duscc68562_device> m_duscc1;
+ required_device<duscc68562_device> m_duscc2;
+ required_device<duscc68562_device> m_duscc3;
+
+ required_device<pit68230_device> m_pit;
+
+ // Pointer to System ROMs needed by bootvect_r
+ uint16_t *m_sysrom;
+};
+
+#endif // VME_FCISIO_H
diff --git a/src/devices/bus/vme/vme_fcscsi.cpp b/src/devices/bus/vme/vme_fcscsi.cpp
new file mode 100644
index 00000000000..3dcf7c17117
--- /dev/null
+++ b/src/devices/bus/vme/vme_fcscsi.cpp
@@ -0,0 +1,539 @@
+// license:BSD-3-Clause
+// copyright-holders:Joakim Larsson Edstrom
+/***************************************************************************
+ * Interrupt scheme and dmac hookup shamelessly based on esq5505.cpp
+ *
+ * 11/04/2016
+ * Force SYS68K ISCSI-1 driver - This driver will be converted into a slot device once the VME bus driver exists.
+ * The ISCSI-1 board is a VME slave board that reads command and returns results through dual ported RAM to the VME bus.
+ *
+ * http://bitsavers.trailing-edge.com/pdf/forceComputers/800114_Force_Introduction_to_the_SYS68K_ISCSI-1_Oct86.pdf
+ *
+ * ||
+ * || ||
+ * ||||--||
+ * ||||--||
+ * || ||__________________________________________________________ ___
+ * || |_| |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | |VME|
+ * || | | |
+ * || | |P1 |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || |_| |
+ * || |___|
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |
+ * || |___
+ * || _| |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | |VME|
+ * || | | |
+ * || | |P2 |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || | | |
+ * || |_| |
+ * || |___|
+ * || ||------------------------------------------------------------+-+
+ * ||||--||
+ * ||||--||
+ * ||
+ *
+ * History of Force Computers
+ *------------------------------------------------------------------------
+ * See fccpu30.cpp
+ *
+ * Description from datasheet etc
+ * ------------------------------
+ * - 68010 CPU for local control (10MHz)
+ * - 68450 DMA Controller for local transfers (10MHz)
+ * - Dual Ported l28Kbyte 0 wait state static RAM between the VMEbus and the local CPU
+ * - SCSlbus interface built with the NCR 5386S SCSlbus controller.
+ * o Programmable as an initiator or target
+ * o Transfer rate up to 1.5Mbyte/s
+ * - SHUGART compatible floppy interface with the WD1772 FDC. Up to 4 floppy drives can be
+ * controlled independent of the SCSlbus
+ * - All I/O signals available on P2 connector 4 different interrupt request signals to the VMEbus. Each
+ * channel contains a software programmable IRQ level (1 to 7) and vector
+ * - Local parallel interface for controlling and monitoring board functions
+ * - VMEbus Rev.C/IEEE P10l4 compatible interface A24:D16, D8, SYSFAIL (jumper)
+ * - Watchdog timer controlling correct functions of on-board hard and software
+ * - Status and control LEDs for monitoring local activities
+ * - High level handling firmware for communication, self test, data caching/hashing and control
+ *
+ * Address Map
+ * ----------------------------------------------------------
+ * Address Range Description
+ * ----------------------------------------------------------
+ * 000000 - 000007 Initialisation vectors from system EPROM
+ * 000008 - 001FFF Local SRAM
+ * 002000 - 01FFFF Dynamic Dual Port RAM VME bus accessable
+ * C40000 - C4001F SCSIbus controller
+ * C80000 - C800FF DMAC
+ * CC0000 - CC0007 FDC
+ * CC0009 - CC0009 Control Register
+ * D00000 - D0003F PI/T
+ * E00000 - E70000 EPROMs
+ * ----------------------------------------------------------
+ *
+ * VME side A24 address map - Dual ported RAM
+ * ----------------------------------------------------------
+ * Default Range Description
+ * ----------------------------------------------------------
+ * A00000 - A00000 Status word Bits 8:RESET 9:HALT 10:WD
+ * A00001 - A0000F BIM - See below
+ * A01001 - A01001 Read generates local interrupt
+ * A01801 - A01801 Read generates local reset
+ * A02000 - A1FFFF Dynamic Dual Port RAM
+ * ----------------------------------------------------------
+ *
+ * BIM Ctrl Vect Req Toggle PI/T Status PI/T
+ * ch adr adr pin write pin rea
+ * ----------------------------------------------------------
+ * 0 A00001 A00009 PA0 PA4
+ * 1 A00003 A0000B PA1 PA5
+ * 2 A00005 A0000D PA2 PA6
+ * 3 A00007 A0000F PA3 PA7
+ * ----------------------------------------------------------
+ *
+ * Interrupt sources
+ * ----------------------------------------------------------
+ * Description Device Lvl IRQ VME board
+ * /Board Vector Address
+ * ----------------------------------------------------------
+ * On board Sources
+ * ABORT P3 p13 1 AV1
+ * DMA controller 68450 2 DMAC/AV2
+ * SCSI bus controller NCR 5386S 3 AV3
+ * Floppy Disk controller WD 1772 4 AV4
+ * Parallel interface and timer 68230 5 PIT timer
+ * --- 6 ---
+ * Parallel interface and timer 68230 7 PIT port
+ * ----------------------------------------------------------
+ *
+ * TODO:
+ * - Write and attach a NCR5386S SCSI device
+ * - Find a floppy image and present it to the WD1772 floppy controller
+ * - Add VME bus driver
+ * - Let a controller CPU board (eg CPU-1 or CPU-30) boot from floppy or SCSI disk
+ *
+ ****************************************************************************/
+#define TODO "Driver for SCSI NCR5386s device needed\n"
+
+#include "emu.h"
+#include "cpu/m68000/m68000.h"
+#include "machine/68230pit.h"
+#include "machine/wd_fdc.h"
+#include "machine/hd63450.h" // compatible with MC68450
+#include "machine/clock.h"
+#include "formats/pc_dsk.h"
+#include "vme_fcscsi.h"
+
+#define LOG_GENERAL 0x01
+#define LOG_SETUP 0x02
+#define LOG_PRINTF 0x04
+
+#define VERBOSE 0 //(LOG_PRINTF | LOG_SETUP | LOG_GENERAL)
+
+#define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0)
+#define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0)
+
+#define LOG(...) LOGMASK(LOG_GENERAL, __VA_ARGS__)
+#define LOGSETUP(...) LOGMASK(LOG_SETUP, __VA_ARGS__)
+
+#if VERBOSE & LOG_PRINTF
+#define logerror printf
+#endif
+
+#ifdef _MSC_VER
+#define FUNCNAME __func__
+#else
+#define FUNCNAME __PRETTY_FUNCTION__
+#endif
+
+//**************************************************************************
+// GLOBAL VARIABLES
+//**************************************************************************
+
+const device_type VME_FCSCSI1 = &device_creator<vme_fcscsi1_card_device>;
+
+#define CPU_CRYSTAL XTAL_20MHz /* Jauch */
+#define PIT_CRYSTAL XTAL_16MHz /* Jauch */
+
+static ADDRESS_MAP_START (fcscsi1_mem, AS_PROGRAM, 16, vme_fcscsi1_card_device)
+ ADDRESS_MAP_UNMAP_HIGH
+ AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* Vectors mapped from System EPROM */
+ AM_RANGE (0x000008, 0x001fff) AM_RAM /* SRAM */
+ AM_RANGE (0x002000, 0x01ffff) AM_RAM /* Dual Ported RAM */
+ AM_RANGE (0xe00000, 0xe7ffff) AM_ROM /* System EPROM Area 32Kb DEBUGGER supplied */
+ AM_RANGE (0xd00000, 0xd0003f) AM_DEVREADWRITE8 ("pit", pit68230_device, read, write, 0x00ff)
+// AM_RANGE (0xc40000, 0xc4001f) AM_DEVREADWRITE8("scsi", ncr5386_device, read, write, 0x00ff) /* SCSI Controller interface - device support not yet available*/
+ AM_RANGE (0xc40000, 0xc4001f) AM_READWRITE8 (scsi_r, scsi_w, 0x00ff)
+ AM_RANGE (0xc80000, 0xc800ff) AM_DEVREADWRITE("mc68450", hd63450_device, read, write) /* DMA Controller interface */
+ AM_RANGE (0xcc0000, 0xcc0007) AM_DEVREADWRITE8("fdc", wd1772_t, read, write, 0x00ff) /* Floppy Controller interface */
+ AM_RANGE (0xcc0008, 0xcc0009) AM_READWRITE8 (tcr_r, tcr_w, 0x00ff) /* The Control Register, SCSI ID and FD drive select bits */
+ADDRESS_MAP_END
+
+
+FLOPPY_FORMATS_MEMBER( vme_fcscsi1_card_device::floppy_formats )
+ FLOPPY_PC_FORMAT
+FLOPPY_FORMATS_END
+
+static SLOT_INTERFACE_START( fcscsi_floppies )
+ SLOT_INTERFACE( "525qd", FLOPPY_525_QD )
+SLOT_INTERFACE_END
+
+/*
+ * Machine configuration
+ */
+static MACHINE_CONFIG_FRAGMENT (fcscsi1)
+ /* basic machine hardware */
+ MCFG_CPU_ADD ("maincpu", M68010, CPU_CRYSTAL / 2) /* 7474 based frequency divide by 2 */
+ MCFG_CPU_PROGRAM_MAP (fcscsi1_mem)
+ MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(vme_fcscsi1_card_device, maincpu_irq_acknowledge_callback)
+
+ /* FDC */
+ MCFG_WD1772_ADD("fdc", PIT_CRYSTAL / 2)
+ MCFG_WD_FDC_INTRQ_CALLBACK(WRITE8(vme_fcscsi1_card_device, fdc_irq))
+ MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("mc68450", hd63450_device, drq1_w))
+ MCFG_FLOPPY_DRIVE_ADD("fdc:0", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:1", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:2", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD("fdc:3", fcscsi_floppies, "525qd", vme_fcscsi1_card_device::floppy_formats)
+
+ /* PIT Parallel Interface and Timer device */
+ MCFG_DEVICE_ADD ("pit", PIT68230, PIT_CRYSTAL / 2) /* 7474 based frequency divide by 2 */
+ MCFG_PIT68230_PB_OUTPUT_CB(WRITE8(vme_fcscsi1_card_device, led_w))
+
+ /* DMAC it is really a M68450 but the HD63850 is upwards compatible */
+ MCFG_DEVICE_ADD("mc68450", HD63450, 0) // MC68450 compatible
+ MCFG_HD63450_CPU("maincpu") // CPU - 68010
+ MCFG_HD63450_CLOCKS(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2))
+ MCFG_HD63450_BURST_CLOCKS(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50))
+ MCFG_HD63450_DMA_END_CB(WRITE8(vme_fcscsi1_card_device, dma_end))
+ MCFG_HD63450_DMA_ERROR_CB(WRITE8(vme_fcscsi1_card_device, dma_error))
+ //MCFG_HD63450_DMA_READ_0_CB(READ8(vme_fcscsi1_card_device, scsi_read_byte)) // ch 0 = SCSI
+ //MCFG_HD63450_DMA_WRITE_0_CB(WRITE8(vme_fcscsi1_card_device, scsi_write_byte))
+ MCFG_HD63450_DMA_READ_1_CB(READ8(vme_fcscsi1_card_device, fdc_read_byte)) // ch 1 = fdc
+ MCFG_HD63450_DMA_WRITE_1_CB(WRITE8(vme_fcscsi1_card_device, fdc_write_byte))
+MACHINE_CONFIG_END
+
+/* ROM definitions */
+ROM_START (fcscsi1)
+ ROM_REGION (0x1000000, "maincpu", 0)
+
+ /* Besta ROM:s - apparantly patched Force ROM:s */
+ ROM_SYSTEM_BIOS(0, "Besta 88", "Besta 88")
+ ROMX_LOAD ("besta88_scsi_lower.ROM", 0xe00001, 0x4000, CRC (fb3ab364) SHA1 (d79112100f1c4beaf358e006efd4dde5e300b0ba), ROM_SKIP(1) | ROM_BIOS(1))
+ ROMX_LOAD ("besta88_scsi_upper.ROM", 0xe00000, 0x4000, CRC (41f9cdf4) SHA1 (66b998bbf9459f0a613718260e05e97749532073), ROM_SKIP(1) | ROM_BIOS(1))
+
+ /* Force ROM:s */
+ ROM_SYSTEM_BIOS(1, "ISCSI-1 v3.7", "Force Computer SYS68K/ISCSI-1 firmware v3.7")
+ ROMX_LOAD ("ISCSI-1_V3.7_L.BIN", 0xe00001, 0x4000, CRC (83d95ab7) SHA1 (bf249910bcb6cb0b04dda2a95a38a0f90b553352), ROM_SKIP(1) | ROM_BIOS(2))
+ ROMX_LOAD ("ISCSI-1_V3.7_U.BIN", 0xe00000, 0x4000, CRC (58815831) SHA1 (074085ef96e1fe2a551938bdeee6a9cab40ff09c), ROM_SKIP(1) | ROM_BIOS(2))
+
+ROM_END
+
+
+machine_config_constructor vme_fcscsi1_card_device::device_mconfig_additions() const
+{
+ LOG("%s %s\n", tag(), FUNCNAME);
+ return MACHINE_CONFIG_NAME( fcscsi1 );
+}
+
+const tiny_rom_entry *vme_fcscsi1_card_device::device_rom_region() const
+{
+ LOG("%s\n", FUNCNAME);
+ return ROM_NAME( fcscsi1 );
+}
+
+//**************************************************************************
+// LIVE DEVICE
+//**************************************************************************
+vme_fcscsi1_card_device::vme_fcscsi1_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
+ device_t(mconfig, type, name, tag, owner, clock, shortname, source)
+ ,device_vme_card_interface(mconfig, *this)
+ ,m_maincpu (*this, "maincpu")
+ ,m_fdc (*this, "fdc")
+ ,m_pit (*this, "pit")
+ ,m_dmac(*this, "mc68450")
+ ,m_tcr (0)
+{
+ LOG("%s\n", FUNCNAME);
+}
+
+vme_fcscsi1_card_device::vme_fcscsi1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ device_t(mconfig, VME_FCSCSI1, "Force Computer SYS68K/ISCSI-1 Intelligent Mass Storage Controller Board", tag, owner, clock, "fcscsi1", __FILE__)
+ ,device_vme_card_interface(mconfig, *this)
+ ,m_maincpu(*this, "maincpu")
+ ,m_fdc(*this, "fdc")
+ ,m_pit(*this, "pit")
+ ,m_dmac(*this, "mc68450")
+ ,m_tcr(0)
+{
+ LOG("%s\n", FUNCNAME);
+}
+
+/* Start it up */
+void vme_fcscsi1_card_device::device_start()
+{
+ LOG("%s\n", FUNCNAME);
+ set_vme_device();
+
+ /* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
+ m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0xe00000);
+
+#if 0 // TODO: Setup VME access handlers for shared memory area
+ uint32_t base = 0x00A00000;
+ m_vme->install_device(base + 0, base + 1, // Channel B - Data
+ read8_delegate(FUNC(z80sio_device::db_r), subdevice<z80sio_device>("pit")), write8_delegate(FUNC(z80sio_device::db_w), subdevice<z80sio_device>("pit")), 0x00ff);
+ m_vme->install_device(base + 2, base + 3, // Channel B - Control
+ read8_delegate(FUNC(z80sio_device::cb_r), subdevice<z80sio_device>("pit")), write8_delegate(FUNC(z80sio_device::cb_w), subdevice<z80sio_device>("pit")), 0x00ff);
+#endif
+
+}
+
+void vme_fcscsi1_card_device::device_reset()
+{
+ LOG("%s\n", FUNCNAME);
+}
+
+/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
+READ16_MEMBER (vme_fcscsi1_card_device::bootvect_r){
+ return m_sysrom [offset];
+}
+
+/* The Control Register - discretely implemented on the PCB
+Bit #: 7 6 5 4 3 2 1 0
+ \ \ \ \ \ \ \ \ Floppy Disk Side Select
+ \ \ \ \ \ \ \ Floppy Disk Drive Select 0
+ \ \ \ \ \ \ Floppy Disk Drive Select 1
+ \ \ \ \ \ Floppy Disk Drive Select 2
+ \ \ \ \ Floppy Disk Drive Select 3
+ \ \ \ ISCSI-l I.D. Bit #0
+ \ \ ISCSI-l I.D. Bit #1
+ \ ISCSI-l 1.D. Bit #2
+*/
+
+READ8_MEMBER (vme_fcscsi1_card_device::tcr_r){
+ LOG("%s\n", FUNCNAME);
+ return (uint8_t) m_tcr;
+}
+
+WRITE8_MEMBER (vme_fcscsi1_card_device::tcr_w){
+ floppy_image_device *floppy0 = m_fdc->subdevice<floppy_connector>("0")->get_device();
+ floppy_image_device *floppy1 = m_fdc->subdevice<floppy_connector>("1")->get_device();
+ floppy_image_device *floppy2 = m_fdc->subdevice<floppy_connector>("2")->get_device();
+ floppy_image_device *floppy3 = m_fdc->subdevice<floppy_connector>("3")->get_device();
+ floppy_image_device *floppy = nullptr;
+
+ if (!BIT(data, 1)) floppy = floppy0;
+ else
+ if (!BIT(data, 2)) floppy = floppy1;
+ else
+ if (!BIT(data, 3)) floppy = floppy2;
+ else
+ if (!BIT(data, 4)) floppy = floppy3;
+
+ if (floppy) {
+ m_fdc->set_floppy(floppy);
+ floppy->ss_w(!BIT(data, 0));
+ floppy->mon_w(0);
+ } else {
+ floppy0->mon_w(1);
+ floppy1->mon_w(1);
+ floppy2->mon_w(1);
+ floppy3->mon_w(1);
+ }
+
+ LOG("%s [%02x]\n", FUNCNAME, data);
+ m_tcr = data;
+ return;
+}
+
+WRITE8_MEMBER (vme_fcscsi1_card_device::led_w){
+ LOG("%s [%02x]\n", FUNCNAME, data);
+
+ m_fdc->dden_w(BIT(data, 7));
+
+ return;
+}
+
+WRITE8_MEMBER(vme_fcscsi1_card_device::dma_end)
+{
+ if (data != 0)
+ {
+ dmac_irq_state = 1;
+ dmac_irq_vector = m_dmac->get_vector(offset);
+ }
+ else
+ {
+ dmac_irq_state = 0;
+ }
+
+ update_irq_to_maincpu();
+}
+
+WRITE8_MEMBER(vme_fcscsi1_card_device::dma_error)
+{
+ if(data != 0)
+ {
+ logerror("DMAC error, vector = %x\n", m_dmac->get_error_vector(offset));
+ dmac_irq_state = 1;
+ dmac_irq_vector = m_dmac->get_vector(offset);
+ }
+ else
+ {
+ dmac_irq_state = 0;
+ }
+
+ update_irq_to_maincpu();
+}
+
+WRITE8_MEMBER(vme_fcscsi1_card_device::fdc_irq)
+{
+ if (data != 0)
+ {
+ fdc_irq_state = 1;
+ }
+ else
+ {
+ fdc_irq_state = 0;
+ }
+ update_irq_to_maincpu();
+}
+
+READ8_MEMBER(vme_fcscsi1_card_device::fdc_read_byte)
+{
+ return m_fdc->data_r();
+}
+
+WRITE8_MEMBER(vme_fcscsi1_card_device::fdc_write_byte)
+{
+ m_fdc->data_w(data & 0xff);
+}
+
+READ8_MEMBER(vme_fcscsi1_card_device::scsi_r)
+{
+ uint8_t data = 0;
+
+ // fake diag status
+ if (offset == 9)
+ data = 0x80;
+
+ LOG("scsi R %02x == %02x\n", offset, data);
+
+ return data;
+}
+
+WRITE8_MEMBER(vme_fcscsi1_card_device::scsi_w)
+{
+ LOG("scsi W %02x <- %02x\n", offset, data);
+}
+
+READ8_MEMBER (vme_fcscsi1_card_device::not_implemented_r){
+ static int been_here = 0;
+ if (!been_here++){
+ logerror(TODO);
+ printf(TODO);
+ }
+ return (uint8_t) 0;
+}
+
+WRITE8_MEMBER (vme_fcscsi1_card_device::not_implemented_w){
+ static int been_here = 0;
+ if (!been_here++){
+ logerror(TODO);
+ printf(TODO);
+ }
+ return;
+}
+
+/*
+----------------------------------------------------
+ IRQ IRQ
+Level Source B4l inserted B4l removed (Def)
+-----------------------------------------------------
+ 1 P3 Pin #13 AV1 Autovector AV1 Autovector
+ 2 DMAC DMAC AV2 Autovector
+ 3 SCSIBC AV3 Autovector AV3 Autovector
+ 4 FDC AV4 Autovector AV4 Autovector
+ 5 PI/T Timer PI/T Timer Vect PI/T Timer Vect
+ 6 -- -- --
+ 7 PI/T Port PI/T Port Vect PI/T Port Vect
+------------------------------------------------------
+Default configuration: B41 jumper removed
+
+The PI/T port interrupt can be used under software control to
+cause non-maskable (Level 7) interrupts if the watchdog timer
+elapses and/or if the VMEbus interrupt trigger call occurs.
+*/
+
+/* TODO: Add configurable B41 jumper */
+#define B41 0
+
+void vme_fcscsi1_card_device::update_irq_to_maincpu() {
+ if (fdc_irq_state) {
+ m_maincpu->set_input_line(M68K_IRQ_3, ASSERT_LINE);
+ m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
+ m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
+ } else if (dmac_irq_state) {
+ m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
+ m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
+#if B41 == 1
+ m_maincpu->set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, dmac_irq_vector);
+#else
+ m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
+#endif
+ } else {
+ m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
+ m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
+ m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
+ }
+}
+
+IRQ_CALLBACK_MEMBER(vme_fcscsi1_card_device::maincpu_irq_acknowledge_callback)
+{
+ // We immediately update the interrupt presented to the CPU, so that it doesn't
+ // end up retrying the same interrupt over and over. We then return the appropriate vector.
+ int vector = 0;
+ switch(irqline) {
+ case 2:
+ dmac_irq_state = 0;
+ vector = dmac_irq_vector;
+ break;
+ default:
+ logerror("\nUnexpected IRQ ACK Callback: IRQ %d\n", irqline);
+ return 0;
+ }
+ update_irq_to_maincpu();
+ return vector;
+}
+
+// This info isn't kept in a card driver atm so storing it as a comment for later use
+// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
+//COMP( 1986, fcscsi1, 0, 0, fcscsi1, fcscsi1, driver_device, 0, "Force Computers Gmbh", "SYS68K/SCSI-1", MACHINE_IS_SKELETON )
diff --git a/src/devices/bus/vme/vme_fcscsi.h b/src/devices/bus/vme/vme_fcscsi.h
new file mode 100644
index 00000000000..719f12df5b6
--- /dev/null
+++ b/src/devices/bus/vme/vme_fcscsi.h
@@ -0,0 +1,73 @@
+// license:BSD-3-Clause
+// copyright-holders:Joakim Larsson Edstrom
+#ifndef VME_FCSCSI_H
+#define VME_FCSCSI_H
+#pragma once
+
+#include "machine/68230pit.h"
+#include "machine/wd_fdc.h"
+#include "machine/hd63450.h" // compatible with MC68450
+#include "bus/vme/vme.h"
+
+extern const device_type VME_FCSCSI1;
+
+class vme_fcscsi1_card_device :
+ public device_t
+ ,public device_vme_card_interface
+{
+public:
+ vme_fcscsi1_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
+ vme_fcscsi1_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ // optional information overrides
+ virtual machine_config_constructor device_mconfig_additions() const override;
+ virtual const tiny_rom_entry *device_rom_region() const override;
+
+ DECLARE_READ16_MEMBER (bootvect_r);
+ DECLARE_READ8_MEMBER (tcr_r);
+ DECLARE_WRITE8_MEMBER (tcr_w);
+ DECLARE_WRITE8_MEMBER (led_w);
+
+ IRQ_CALLBACK_MEMBER(maincpu_irq_acknowledge_callback);
+
+ //dmac
+ DECLARE_WRITE8_MEMBER(dma_end);
+ DECLARE_WRITE8_MEMBER(dma_error);
+
+ //fdc
+ DECLARE_WRITE8_MEMBER(fdc_irq);
+ DECLARE_READ8_MEMBER(fdc_read_byte);
+ DECLARE_WRITE8_MEMBER(fdc_write_byte);
+ DECLARE_FLOPPY_FORMATS(floppy_formats);
+
+ /* Dummy driver routines */
+ DECLARE_READ8_MEMBER (not_implemented_r);
+ DECLARE_WRITE8_MEMBER (not_implemented_w);
+
+ DECLARE_READ8_MEMBER (scsi_r);
+ DECLARE_WRITE8_MEMBER (scsi_w);
+
+ uint8_t fdc_irq_state;
+ uint8_t dmac_irq_state;
+ int dmac_irq_vector;
+
+ void update_irq_to_maincpu();
+
+protected:
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+private:
+ required_device<cpu_device> m_maincpu;
+ required_device<wd1772_t> m_fdc;
+ required_device<pit68230_device> m_pit;
+ required_device<hd63450_device> m_dmac;
+
+ uint8_t m_tcr;
+
+ // Pointer to System ROMs needed by bootvect_r
+ uint16_t *m_sysrom;
+};
+
+#endif // VME_FCSCSI_H
+
diff --git a/src/devices/bus/vme/vme_mvme350.cpp b/src/devices/bus/vme/vme_mvme350.cpp
index 1c1b0df9d44..69afff9490a 100644
--- a/src/devices/bus/vme/vme_mvme350.cpp
+++ b/src/devices/bus/vme/vme_mvme350.cpp
@@ -214,14 +214,14 @@ const tiny_rom_entry *vme_mvme350_card_device::device_rom_region() const
vme_mvme350_card_device::vme_mvme350_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
device_t(mconfig, type, name, tag, owner, clock, shortname, source),
- device_vme_p1_card_interface(mconfig, *this)
+ device_vme_card_interface(mconfig, *this)
{
LOG("%s %s\n", tag, FUNCNAME);
}
vme_mvme350_card_device::vme_mvme350_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, VME_MVME350, "Motorola MVME-350 Intelligent Tape Controller", tag, owner, clock, "mvme350", __FILE__),
- device_vme_p1_card_interface(mconfig, *this)
+ device_vme_card_interface(mconfig, *this)
{
LOG("%s %s\n", tag, FUNCNAME);
}
@@ -229,7 +229,7 @@ vme_mvme350_card_device::vme_mvme350_card_device(const machine_config &mconfig,
void vme_mvme350_card_device::device_start()
{
LOG("%s %s\n", tag(), FUNCNAME);
- set_vme_p1_device();
+ set_vme_device();
/* Setup r/w handlers for shared memory area */
#if 0
@@ -243,9 +243,9 @@ void vme_mvme350_card_device::device_start()
---------------------------------------------------
*/
uint32_t base = 0xFFFF5000;
- m_vme_p1->install_device(base + 0, base + 1, // Channel B - Data
+ m_vme->install_device(base + 0, base + 1, // Channel B - Data
read8_delegate(FUNC(z80sio_device::db_r), subdevice<z80sio_device>("pit")), write8_delegate(FUNC(z80sio_device::db_w), subdevice<z80sio_device>("pit")), 0x00ff);
- m_vme_p1->install_device(base + 2, base + 3, // Channel B - Control
+ m_vme->install_device(base + 2, base + 3, // Channel B - Control
read8_delegate(FUNC(z80sio_device::cb_r), subdevice<z80sio_device>("pit")), write8_delegate(FUNC(z80sio_device::cb_w), subdevice<z80sio_device>("pit")), 0x00ff);
#endif
diff --git a/src/devices/bus/vme/vme_mvme350.h b/src/devices/bus/vme/vme_mvme350.h
index b7cfbdb98f2..5d79fa3d306 100644
--- a/src/devices/bus/vme/vme_mvme350.h
+++ b/src/devices/bus/vme/vme_mvme350.h
@@ -10,7 +10,7 @@ extern const device_type VME_MVME350;
class vme_mvme350_card_device :
public device_t
- ,public device_vme_p1_card_interface
+ ,public device_vme_card_interface
{
public:
vme_mvme350_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
diff --git a/src/devices/bus/vme/vme_mzr8105.cpp b/src/devices/bus/vme/vme_mzr8105.cpp
index 017255ba9e1..8239c0992f1 100644
--- a/src/devices/bus/vme/vme_mzr8105.cpp
+++ b/src/devices/bus/vme/vme_mzr8105.cpp
@@ -47,7 +47,7 @@ machine_config_constructor vme_mzr8105_card_device::device_mconfig_additions() c
vme_mzr8105_card_device::vme_mzr8105_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, VME_MZR8105, "Mizar 8105 68K CPU board", tag, owner, clock, "mzr8105", __FILE__),
- device_vme_p1_card_interface(mconfig, *this)
+ device_vme_card_interface(mconfig, *this)
{
m_slot = 1;
LOG("%s %s\n", tag, FUNCNAME);
@@ -55,7 +55,7 @@ vme_mzr8105_card_device::vme_mzr8105_card_device(const machine_config &mconfig,
vme_mzr8105_card_device::vme_mzr8105_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
device_t(mconfig, type, name, tag, owner, clock, shortname, source),
- device_vme_p1_card_interface(mconfig, *this)
+ device_vme_card_interface(mconfig, *this)
{
LOG("%s %s\n", tag, FUNCNAME);
}
diff --git a/src/devices/bus/vme/vme_mzr8105.h b/src/devices/bus/vme/vme_mzr8105.h
index 55aa77d25c5..525cf691408 100644
--- a/src/devices/bus/vme/vme_mzr8105.h
+++ b/src/devices/bus/vme/vme_mzr8105.h
@@ -9,7 +9,7 @@
extern const device_type VME_MZR8105;
class vme_mzr8105_card_device : public device_t
- ,public device_vme_p1_card_interface
+ ,public device_vme_card_interface
{
public:
vme_mzr8105_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
diff --git a/src/devices/bus/vme/vme_mzr8300.cpp b/src/devices/bus/vme/vme_mzr8300.cpp
index 2ff7b605c95..04ddd02636e 100644
--- a/src/devices/bus/vme/vme_mzr8300.cpp
+++ b/src/devices/bus/vme/vme_mzr8300.cpp
@@ -152,14 +152,14 @@ machine_config_constructor vme_mzr8300_card_device::device_mconfig_additions() c
vme_mzr8300_card_device::vme_mzr8300_card_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source) :
device_t(mconfig, type, name, tag, owner, clock, shortname, source),
- device_vme_p1_card_interface(mconfig, *this)
+ device_vme_card_interface(mconfig, *this)
{
LOG("%s %s\n", tag, FUNCNAME);
}
vme_mzr8300_card_device::vme_mzr8300_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, VME_MZR8300, "Mizar 8300 SIO serial board", tag, owner, clock, "mzr8300", __FILE__),
- device_vme_p1_card_interface(mconfig, *this)
+ device_vme_card_interface(mconfig, *this)
{
LOG("%s %s\n", tag, FUNCNAME);
}
@@ -167,17 +167,17 @@ vme_mzr8300_card_device::vme_mzr8300_card_device(const machine_config &mconfig,
void vme_mzr8300_card_device::device_start()
{
LOG("%s %s\n", tag(), FUNCNAME);
- set_vme_p1_device();
+ set_vme_device();
/* Setup r/w handlers for first SIO in A16 */
uint32_t base = 0xFF0000;
- m_vme_p1->install_device(base + 0, base + 1, // Channel B - Data
+ m_vme->install_device(base + 0, base + 1, // Channel B - Data
read8_delegate(FUNC(z80sio_device::db_r), subdevice<z80sio_device>("sio0")), write8_delegate(FUNC(z80sio_device::db_w), subdevice<z80sio_device>("sio0")), 0x00ff);
- m_vme_p1->install_device(base + 2, base + 3, // Channel B - Control
+ m_vme->install_device(base + 2, base + 3, // Channel B - Control
read8_delegate(FUNC(z80sio_device::cb_r), subdevice<z80sio_device>("sio0")), write8_delegate(FUNC(z80sio_device::cb_w), subdevice<z80sio_device>("sio0")), 0x00ff);
- m_vme_p1->install_device(base + 4, base + 5, // Channel A - Data
+ m_vme->install_device(base + 4, base + 5, // Channel A - Data
read8_delegate(FUNC(z80sio_device::da_r), subdevice<z80sio_device>("sio0")), write8_delegate(FUNC(z80sio_device::da_w), subdevice<z80sio_device>("sio0")), 0x00ff);
- m_vme_p1->install_device(base + 6, base + 7, // Channel A - Control
+ m_vme->install_device(base + 6, base + 7, // Channel A - Control
read8_delegate(FUNC(z80sio_device::ca_r), subdevice<z80sio_device>("sio0")), write8_delegate(FUNC(z80sio_device::ca_w), subdevice<z80sio_device>("sio0")), 0x00ff);
}
diff --git a/src/devices/bus/vme/vme_mzr8300.h b/src/devices/bus/vme/vme_mzr8300.h
index 8cb59348de0..73482cb5b77 100644
--- a/src/devices/bus/vme/vme_mzr8300.h
+++ b/src/devices/bus/vme/vme_mzr8300.h
@@ -10,7 +10,7 @@ extern const device_type VME_MZR8300;
class vme_mzr8300_card_device :
public device_t
- ,public device_vme_p1_card_interface
+ ,public device_vme_card_interface
{
public:
vme_mzr8300_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
diff --git a/src/devices/machine/hd63450.h b/src/devices/machine/hd63450.h
index 5cee35500fc..76e9da87b66 100644
--- a/src/devices/machine/hd63450.h
+++ b/src/devices/machine/hd63450.h
@@ -3,6 +3,9 @@
/*
Hitachi HD63450 DMA Controller
*/
+#ifndef HD63450_H
+#define HD63450_H
+#pragma once
#include "emu.h"
@@ -153,3 +156,4 @@ private:
};
extern const device_type HD63450;
+#endif // HD63450_H
diff --git a/src/mame/drivers/fccpu30.cpp b/src/mame/drivers/fccpu30.cpp
index f07e9e0a5b9..33ea2d70ce7 100644
--- a/src/mame/drivers/fccpu30.cpp
+++ b/src/mame/drivers/fccpu30.cpp
@@ -188,6 +188,9 @@
#include "emu.h"
#include "cpu/m68000/m68000.h"
+#include "bus/vme/vme.h"
+#include "bus/vme/vme_fcisio.h"
+#include "bus/vme/vme_fcscsi.h"
#include "machine/msm6242.h"
#include "machine/ram.h" // For variants that only differs in amount of RAM
#include "machine/scnxx562.h"
@@ -198,15 +201,25 @@
#include "machine/clock.h"
//#include "machine/timekpr.h"
-#define VERBOSE 0
+#define LOG_GENERAL 0x01
+#define LOG_SETUP 0x02
+#define LOG_PRINTF 0x04
+#define LOG_INIT 0x08
+#define LOG_READ 0x10
+#define LOG_INT 0x20
-#define LOGPRINT(x) { do { if (VERBOSE) logerror x; } while (0); }
-#define LOG(x) {} LOGPRINT(x)
-#define LOGINIT(x) {} LOGPRINT(x)
-#define LOGR(x) {}
-#define LOGSETUP(x) {}
-#define LOGINT(x) {}
-#if VERBOSE >= 2
+#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP | LOG_GENERAL)
+
+#define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0)
+#define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0)
+
+#define LOG(...) LOGMASK(LOG_GENERAL, __VA_ARGS__)
+#define LOGSETUP(...) LOGMASK(LOG_SETUP, __VA_ARGS__)
+#define LOGINIT(...) LOGMASK(LOG_INIT, __VA_ARGS__)
+#define LOGR(...) LOGMASK(LOG_READ, __VA_ARGS__)
+#define LOGINT(...) LOGMASK(LOG_INT, __VA_ARGS__)
+
+#if VERBOSE & LOG_PRINTF
#define logerror printf
#endif
@@ -333,7 +346,7 @@ INPUT_PORTS_END
/* Start it up */
void cpu30_state::machine_start ()
{
- LOGINIT(("%s\n", FUNCNAME));
+ LOGINIT("%s\n", FUNCNAME);
save_pointer (NAME (m_sysrom), sizeof(m_sysrom));
save_pointer (NAME (m_sysram), sizeof(m_sysram));
@@ -347,7 +360,7 @@ void cpu30_state::machine_start ()
void cpu30_state::machine_reset ()
{
- LOGINIT(("%s\n", FUNCNAME));
+ LOGINIT("%s\n", FUNCNAME);
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
@@ -355,50 +368,50 @@ void cpu30_state::machine_reset ()
}
/* setup board ID */
-DRIVER_INIT_MEMBER( cpu30_state, cpu30x ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
-DRIVER_INIT_MEMBER( cpu30_state, cpu30xa ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
-DRIVER_INIT_MEMBER( cpu30_state, cpu30za ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
-DRIVER_INIT_MEMBER( cpu30_state, cpu30zbe ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
-DRIVER_INIT_MEMBER( cpu30_state, cpu30be8 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
-DRIVER_INIT_MEMBER( cpu30_state, cpu30be16 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
-DRIVER_INIT_MEMBER( cpu30_state, cpu30lite4 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
-DRIVER_INIT_MEMBER( cpu30_state, cpu30lite8 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x50; }
-DRIVER_INIT_MEMBER( cpu30_state, cpu33 ) { LOGINIT(("%s\n", FUNCNAME)); m_board_id = 0x68; } // 0x60 skips FGA prompt
+DRIVER_INIT_MEMBER( cpu30_state, cpu30x ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
+DRIVER_INIT_MEMBER( cpu30_state, cpu30xa ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
+DRIVER_INIT_MEMBER( cpu30_state, cpu30za ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
+DRIVER_INIT_MEMBER( cpu30_state, cpu30zbe ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
+DRIVER_INIT_MEMBER( cpu30_state, cpu30be8 ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
+DRIVER_INIT_MEMBER( cpu30_state, cpu30be16 ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
+DRIVER_INIT_MEMBER( cpu30_state, cpu30lite4 ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
+DRIVER_INIT_MEMBER( cpu30_state, cpu30lite8 ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x50; }
+DRIVER_INIT_MEMBER( cpu30_state, cpu33 ) { LOGINIT("%s\n", FUNCNAME); m_board_id = 0x68; } // 0x60 skips FGA prompt
/* Mock FDC driver */
READ8_MEMBER (cpu30_state::fdc_r){
- LOG(("%s\n * FDC read Offset: %04x\n", FUNCNAME, offset));
+ LOG("%s\n * FDC read Offset: %04x\n", FUNCNAME, offset);
return 1;
}
WRITE8_MEMBER (cpu30_state::fdc_w){
- LOG(("%s\n * FDC write Offset: %04x Data: %02x\n", FUNCNAME, offset, data));
+ LOG("%s\n * FDC write Offset: %04x Data: %02x\n", FUNCNAME, offset, data);
}
/* Mock SCSI driver */
READ8_MEMBER (cpu30_state::scsi_r){
- LOG(("%s\n * SCSI read Offset: %04x\n", FUNCNAME, offset));
+ LOG("%s\n * SCSI read Offset: %04x\n", FUNCNAME, offset);
return 1;
}
WRITE8_MEMBER (cpu30_state::scsi_w){
- LOG(("%s\n * SCSI write Offset: %04x Data: %02x\n", FUNCNAME, offset, data));
+ LOG("%s\n * SCSI write Offset: %04x Data: %02x\n", FUNCNAME, offset, data);
}
/* 1 = board is in slot 1, 0 = board is NOT in slot 1 */
READ8_MEMBER (cpu30_state::slot1_status_r){
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
return 1;
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
READ32_MEMBER (cpu30_state::bootvect_r){
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
return m_sysrom[offset];
}
WRITE32_MEMBER (cpu30_state::bootvect_w){
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask;
m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
@@ -459,42 +472,42 @@ WRITE32_MEMBER (cpu30_state::bootvect_w){
* "To start VMEPROM, the rotary switches must both be set to 'F':" Hmm...
*/
READ8_MEMBER (cpu30_state::rotary_rd){
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
return 0xff; // TODO: make this configurable from commandline or artwork
}
// PIT#1 Port B TODO: implement floppy and dma control
READ8_MEMBER (cpu30_state::flop_dmac_r){
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
return 0xff;
}
WRITE8_MEMBER (cpu30_state::flop_dmac_w){
- LOG(("%s(%02x)\n", FUNCNAME, data));
+ LOG("%s(%02x)\n", FUNCNAME, data);
}
#define FPCP_SENSE 0x40 /* Port C bit 6 is low if a Floating Point Co Processor is installed */
// PIT#1 Port C TODO: implement timer+port interrupts
// TODO: Connect PC0, PC1, PC4 and PC7 to B5 and/or P2 connector
READ8_MEMBER (cpu30_state::pit1c_r){
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
m_maincpu->set_fpu_enable(1); // Lets assume the FPCP is always installed ( which is default for 68030 atm )
return 0xff & ~FPCP_SENSE; // Should really be command line for the edge cases...
}
WRITE8_MEMBER (cpu30_state::pit1c_w){
- LOG(("%s(%02x)\n", FUNCNAME, data));
+ LOG("%s(%02x)\n", FUNCNAME, data);
}
// PIT#2 Port A TODO: Connect to B5 and /or P2 connector
READ8_MEMBER (cpu30_state::pit2a_r){
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
logerror("Unsupported user i/o on PIT2 port A detected\n");
return 0xff;
}
WRITE8_MEMBER (cpu30_state::pit2a_w){
- LOG(("%s(%02x)\n", FUNCNAME, data));
+ LOG("%s(%02x)\n", FUNCNAME, data);
logerror("Unsupported user i/o on PIT2 port A detected\n");
}
@@ -519,7 +532,7 @@ WRITE8_MEMBER (cpu30_state::pit2a_w){
READ8_MEMBER (cpu30_state::board_mem_id_rd)
{
int sz;
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
switch (m_ram->size())
{
case (1024 * 1024 * 32): sz = 0; break;
@@ -557,56 +570,56 @@ READ8_MEMBER (cpu30_state::board_mem_id_rd)
// return 0x10 + sz;// CPU-22 p4
// return 0x20 + sz;// p1: Wait until hard disk is up to speed
// printf("SIZE:%02x\n", sz);
- LOG(("- Board ID:%02x Size:%02x\n", m_board_id, sz));
+ LOG("- Board ID:%02x Size:%02x\n", m_board_id, sz);
return m_board_id + sz;
}
// PIT#2 Port C TODO: implement timer interrupt, DMA i/o, memory control and Hardware ID
READ8_MEMBER (cpu30_state::pit2c_r){
- LOG(("%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
return 0xfe;
}
WRITE8_MEMBER (cpu30_state::pit2c_w){
- LOG(("%s(%02x)\n", FUNCNAME, data));
+ LOG("%s(%02x)\n", FUNCNAME, data);
}
#if 0
/* Dummy VME access methods until the VME bus device is ready for use */
READ16_MEMBER (cpu30_state::vme_a24_r){
- LOG (logerror ("vme_a24_r\n"));
+ LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
WRITE16_MEMBER (cpu30_state::vme_a24_w){
- LOG (logerror ("vme_a24_w\n"));
+ LOG("%s(%02x)\n", FUNCNAME, data);
}
READ16_MEMBER (cpu30_state::vme_a16_r){
- LOG (logerror ("vme_16_r\n"));
+ LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
WRITE16_MEMBER (cpu30_state::vme_a16_w){
- LOG (logerror ("vme_a16_w\n"));
+ LOG("%s(%02x)\n", FUNCNAME, data);
}
#endif
WRITE_LINE_MEMBER(cpu30_state::fga_irq_callback)
{
- LOGINT(("%s(%02x)\n", FUNCNAME, state));
+ LOGINT("%s(%02x)\n", FUNCNAME, state);
fga_irq_state = state;
fga_irq_level = m_fga002->get_irq_level();
- LOGINT((" - FGA irq level %02x\n", fga_irq_level));
+ LOGINT(" - FGA irq level %02x\n", fga_irq_level);
update_irq_to_maincpu();
}
void cpu30_state::update_irq_to_maincpu()
{
- LOGINT(("%s()\n", FUNCNAME));
- LOGINT((" - fga_irq_level: %02x\n", fga_irq_level));
- LOGINT((" - fga_irq_state: %02x\n", fga_irq_state));
+ LOGINT("%s()\n", FUNCNAME);
+ LOGINT(" - fga_irq_level: %02x\n", fga_irq_level);
+ LOGINT(" - fga_irq_state: %02x\n", fga_irq_state);
switch (fga_irq_level & 0x07)
{
case 1: m_maincpu->set_input_line(M68K_IRQ_1, fga_irq_state); break;
@@ -620,6 +633,11 @@ void cpu30_state::update_irq_to_maincpu()
}
}
+static SLOT_INTERFACE_START(fccpu30_vme_cards)
+ SLOT_INTERFACE("fcisio", VME_FCISIO1)
+ SLOT_INTERFACE("fcscsi", VME_FCSCSI1)
+SLOT_INTERFACE_END
+
/*
* Machine configuration
*/
@@ -630,6 +648,8 @@ static MACHINE_CONFIG_START (cpu30, cpu30_state)
MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("fga002", fga002_device, iack)
MCFG_NVRAM_ADD_0FILL("nvram")
+ MCFG_VME_DEVICE_ADD("vme")
+ MCFG_VME_SLOT_ADD ("vme", "slot1", fccpu30_vme_cards, nullptr)
/* Terminal Port config */
/* Force CPU30 series of boards has up to four serial ports, p1-p4, the FGA boot uses p4 as console and subsequent
firmware uses p1 as console and in an operating system environment there may be user login shells on the other.
diff --git a/src/mame/drivers/fcisio.cpp b/src/mame/drivers/fcisio.cpp
deleted file mode 100644
index 150eba2fe0c..00000000000
--- a/src/mame/drivers/fcisio.cpp
+++ /dev/null
@@ -1,309 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Joakim Larsson Edstrom
-/***************************************************************************
- *
- * 10/06/2016
- * Force SYS68K ISIO-1/2 driver - This driver will be converted into a slot device once the VME bus driver exists.
- * The ISIO board is a VME slave board that reads command and returns results through dual ported RAM to the VME bus.
- *
- * ISIO-1: page 385 http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
- * ISIO-2: page 395 http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
- *
- * Address Map - guessed/revenged no tech doc available
- * ----------------------------------------------------------
- * Address Range Description LOCAL
- * ----------------------------------------------------------
- * 00 0000 - 00 0007 Initialisation vectors from system EPROM
- * 00 0008 - 01 FFFF Local SRAM
- * E0 0000 - E0 01FF DUSCC0
- * E2 0000 - E0 01FF DUSCC0
- * E4 0000 - E0 01FF DUSCC0
- * E6 0000 - E0 01FF DUSCC0
- * E8 0000 - E8 0DFF PI/T
- * f0 0000 - F7 0000 EPROMs
- * ----------------------------------------------------------
- * Address Range Description LOCAL
- * ----------------------------------------------------------
- *
- * Interrupt sources
- * ----------------------------------------------------------
- * Description Device Lvl IRQ VME board
- * /Board Vector Address
- * ----------------------------------------------------------
- * On board Sources
- * ----------------------------------------------------------
- *
- * TODO:
- * - add PIT and DUSCC interrupts
- * - add port mapping to self test jumper
- * - add VME bus driver
- * - write and map a 68153 device (accessable from VME side)
- *
- * Status: passes Self test and get stuck on no ticks for the scheduler.
- * Schematics of the IRQ routing needed or a good trace of how the
- * PIT and DUSCCs are hooked up to the BIM to get further.
- *
- ****************************************************************************/
-#define TODO "Driver for 68153 BIM device needed\n"
-
-#include "emu.h"
-#include "cpu/m68000/m68000.h"
-#include "machine/scnxx562.h"
-#include "machine/68230pit.h"
-#include "bus/rs232/rs232.h"
-#include "machine/clock.h"
-
-#define VERBOSE 0
-
-#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#if VERBOSE == 2
-#define logerror printf
-#endif
-
-#ifdef _MSC_VER
-#define FUNCNAME __func__
-#define LLFORMAT "%I64%"
-#else
-#define FUNCNAME __PRETTY_FUNCTION__
-#define LLFORMAT "%lld"
-#endif
-
-#define CPU_CLOCK XTAL_20MHz /* HCJ */
-#define DUSCC_CLOCK XTAL_14_7456MHz /* HCJ */
-
-class fcisio1_state : public driver_device
-{
-public:
-fcisio1_state(const machine_config &mconfig, device_type type, const char *tag) :
- driver_device (mconfig, type, tag),
- m_maincpu (*this, "maincpu")
- ,m_duscc0(*this, "duscc0")
- ,m_duscc1(*this, "duscc1")
- ,m_duscc2(*this, "duscc2")
- ,m_duscc3(*this, "duscc3")
- ,m_pit (*this, "pit")
-{
-}
- DECLARE_READ16_MEMBER (bootvect_r);
- DECLARE_READ8_MEMBER (config_rd);
-
- /* Dummy driver routines */
- DECLARE_READ8_MEMBER (not_implemented_r);
- DECLARE_WRITE8_MEMBER (not_implemented_w);
-
- virtual void machine_start () override;
-
-protected:
-
-private:
- required_device<cpu_device> m_maincpu;
- required_device<duscc68562_device> m_duscc0;
- required_device<duscc68562_device> m_duscc1;
- required_device<duscc68562_device> m_duscc2;
- required_device<duscc68562_device> m_duscc3;
-
- required_device<pit68230_device> m_pit;
-
- // Pointer to System ROMs needed by bootvect_r
- uint16_t *m_sysrom;
-};
-
-static ADDRESS_MAP_START (fcisio1_mem, AS_PROGRAM, 16, fcisio1_state)
- ADDRESS_MAP_UNMAP_HIGH
- AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* Vectors mapped from System EPROM */
- AM_RANGE (0x000000, 0x01ffff) AM_RAM /* SRAM */
- AM_RANGE (0xe00000, 0xe001ff) AM_DEVREADWRITE8("duscc0", duscc68562_device, read, write, 0x00ff)
- AM_RANGE (0xe20000, 0xe201ff) AM_DEVREADWRITE8("duscc1", duscc68562_device, read, write, 0x00ff)
- AM_RANGE (0xe40000, 0xe401ff) AM_DEVREADWRITE8("duscc2", duscc68562_device, read, write, 0x00ff)
- AM_RANGE (0xe60000, 0xe601ff) AM_DEVREADWRITE8("duscc3", duscc68562_device, read, write, 0x00ff)
- AM_RANGE (0xe80000, 0xe80dff) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0x00ff)
- AM_RANGE (0xf00000, 0xf7ffff) AM_ROM /* System EPROM Area 32Kb DEBUGGER supplied */
-// AM_RANGE (0xc40000, 0xc800ff) AM_READWRITE8 (not_implemented_r, not_implemented_w, 0xffff) /* Dummy mapping af address area to display message */
-ADDRESS_MAP_END
-
-/* Start it up */
-void fcisio1_state::machine_start ()
-{
- LOG (("machine_start\n"));
-
- /* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
- m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0xf00000);
-}
-
-/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
-READ16_MEMBER (fcisio1_state::bootvect_r){
- return m_sysrom [offset];
-}
-
-READ8_MEMBER (fcisio1_state::not_implemented_r){
- static int been_here = 0;
- if (!been_here++){
- logerror(TODO);
- printf(TODO);
- }
- return (uint8_t) 0;
-}
-
-WRITE8_MEMBER (fcisio1_state::not_implemented_w){
- static int been_here = 0;
- if (!been_here++){
- logerror(TODO);
- printf(TODO);
- }
- return;
-}
-
-// TODO: Get a manual to understand the config options for real
-READ8_MEMBER (fcisio1_state::config_rd){
- uint8_t ret = 0;
- LOG(("%s\n", FUNCNAME));
-
- // Port B bit #7, 0x80 Self test bit, choose either of these two lines
- ret &= ~0x80; // 0 = selftest
- // ret |= 0x80; // 1 = no selftest
-
- return ret;
-}
-
-/* Input ports */
-static INPUT_PORTS_START (fcisio1)
-INPUT_PORTS_END
-
-static DEVICE_INPUT_DEFAULTS_START( fcisio_terminal )
- DEVICE_INPUT_DEFAULTS( "RS232_TXBAUD", 0xff, RS232_BAUD_9600 )
- DEVICE_INPUT_DEFAULTS( "RS232_RXBAUD", 0xff, RS232_BAUD_9600 )
- DEVICE_INPUT_DEFAULTS( "RS232_STARTBITS", 0xff, RS232_STARTBITS_1 )
- DEVICE_INPUT_DEFAULTS( "RS232_DATABITS", 0xff, RS232_DATABITS_8 )
- DEVICE_INPUT_DEFAULTS( "RS232_PARITY", 0xff, RS232_PARITY_NONE )
- DEVICE_INPUT_DEFAULTS( "RS232_STOPBITS", 0xff, RS232_STOPBITS_1 )
-DEVICE_INPUT_DEFAULTS_END
-
-/*
- * Machine configuration
- */
-static MACHINE_CONFIG_START (fcisio1, fcisio1_state)
- /* basic machine hardware */
- MCFG_CPU_ADD ("maincpu", M68010, CPU_CLOCK / 2)
- MCFG_CPU_PROGRAM_MAP (fcisio1_mem)
-
- MCFG_DUSCC68562_ADD("duscc0", DUSCC_CLOCK, 0, 0, 0, 0 )
- MCFG_DUSCC_OUT_TXDA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
- MCFG_DUSCC_OUT_DTRA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_dtr))
- MCFG_DUSCC_OUT_RTSA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_rts))
-
- MCFG_RS232_PORT_ADD ("rs232trm", default_rs232_devices, "terminal")
- MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc0", duscc68562_device, rxa_w))
- MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("duscc0", duscc68562_device, ctsa_w))
- MCFG_DEVICE_CARD_DEVICE_INPUT_DEFAULTS("terminal", fcisio_terminal)
-
- MCFG_DUSCC68562_ADD("duscc1", DUSCC_CLOCK, 0, 0, 0, 0 )
- MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
- MCFG_DUSCC68562_ADD("duscc3", DUSCC_CLOCK, 0, 0, 0, 0 )
-
- MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_20MHz / 2)
- MCFG_PIT68230_PB_INPUT_CB(READ8(fcisio1_state, config_rd))
-MACHINE_CONFIG_END
-
-/* ROM definitions */
-ROM_START (fcisio1)
- ROM_REGION (0x1000000, "maincpu", 0)
-
-/* ISIO ROM:s v2.1 information
- * PIT setup sequence
- * 00 -> REG_PGCR
- * 18 -> REG_PSRR
- * 0f -> Reg PADDR
- * 0f -> REG_PBDDR
- * fa -> REG_PACR
- * 0f -> REG_PADDR
- * fa -> REG_PBCR
- * ff -> REG_PBDR
- * 0f -> REG_PBDDR
- * 10 -> REG_PGCR
- * ff -> REG_PCDR
- * 17 -> REG_PCDDR
- * 40 -> Reg PIVR
- * 00 -> REG_TCR - timer disabled, all C pins, use preload, CLK and prescaler are used
- * a0 -> REG_TCR - timer disabled, The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- * output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
- * pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge input.
- * 00 -> Reg 0x12
- * 00 -> REG_CPRH
- * 09 -> REG_CPRM
- * 00 -> REG_CPRL
- * 00 -> Reg 0x16
- * 00 -> Reg 0x17
- * 09 -> Reg 0x18
- * 00 -> Reg 0x19
- * 1d -> Reg TIVR
- * 0f <- REG_PBDR
- * 0e -> REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0d -> REG_PDBR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f -> REG_PBDR
- * 0f <- REG_PBDR
- * 0b -> REG_PBDR
- * 0f <- REG_PBDR
- * 0f <- REG_PBDR
- * 0f -> REG_PBDR
- * 0f <- REG_PBDR
- * 0f -> REG_PBDR
- * 0f <- REG_PBDR
- * 00 <- REG_PCDR
- * 00 -> REG_PCDR
- * ------- repeated 16 times -------------------
- * a1 -> REG_TCR - timer enabled, The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
- * output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one. The dual-function
- * pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge input.
- * ?? <- Reg 0x0c
- * ---------------------------------------------
- *
- * DUSCC0 channel A setup sequence
- * 0f 00 -> REG_CCR - Reset Tx
- * 0f 40 -> REG_CCR - Reset Rx
- * 00 07 -> REG_CMR1 - Async mode
- * 01 38 -> REG_CMR2 - Normal polled or interrupt mode, no DMA
- * 02 00 -> REG_S1R - SYN1, Secondary Address 1 Register, 0 = no sync
- * 03 00 -> REG_S2R - SYN2, only used in COP dual Sync mode but alao 0 = no sync
- * 04 7F -> REG_TPR - Tx 8 bits, CTS and RTS, 1 STOP bit
- * 05 3d -> REG_TTR - Tx BRG 9600 (assuming a 14.7456 crystal)
- * 06 1b -> REG_RPR - Rx RTS, 8 bits, no DCD, no parity
- * 07 2d -> REG_RTR - Rx BRG 9600 (assuming a 14.7456 crystal)
- * 0b e1 -> REG_OMR - RTS high, OUT1 = OUT2 = high, RxRdy asserted for each character,
- * TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
- * 0a 00 -> REG_CTCR - Counter/Timer control register 00 = Zero Det Int: disabled, Zero Det Control: preset,
- * Output Control: square, Prescaler: 1, Clock Source: RTxC pin
- * 09 00 -> REG_CTPRL - Counter/Timer Prescaler Register Low = 0
- * 08 00 -> REG_CTPRH - Counter/Timer Prescaler Register High = 0
- * 0f 00 -> REG_CCR - Reset Tx
- * 0f 02 -> REG_CCR - Enable Tx
- * 0f 40 -> REG_CCR - Reset Rx
- * 0f 42 -> REG_CCR - Enable Rx
- * 0f 02 -> REG_CCR - Enable Tx
- * 0f 42 -> REG_CCR - Enable Rx
- * 0e 27 -> REG_PCR - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
- * 1c 10 -> REG_IER - Interrupt Enable Register: RxRdy generates interrupt
- * ... chan B setup with same data....
- * ---- DUSCC0 to DUSCC3, setup with same data except at the end of each setup:
- * 1e 1c -> DUSCC0 REG_IVR -
- * 1e 1b -> DUSCC1 REG_IVR
- * 1e 1a -> DUSCC2 REG_IVR
- * 1e 19 -> DUSCC3 REG_IVR
- */
- ROM_LOAD16_BYTE ("ISIO-1_V2.1_L.BIN", 0xf00001, 0x4000, CRC (0d47d80f) SHA1 (541b55966f464c1cf686e36998650720950a2242))
- ROM_LOAD16_BYTE ("ISIO-1_V2.1_U.BIN", 0xf00000, 0x4000, CRC (67986768) SHA1 (215f7ff90d9dbe2bea54510e3722fb33d4e54193))
-ROM_END
-
-/* Driver */
-/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
-COMP( 1986, fcisio1, 0, 0, fcisio1, fcisio1, driver_device, 0, "Force Computers Gmbh", "SYS68K/ISIO-1", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
diff --git a/src/mame/drivers/fcscsi.cpp b/src/mame/drivers/fcscsi.cpp
deleted file mode 100644
index 580911f9962..00000000000
--- a/src/mame/drivers/fcscsi.cpp
+++ /dev/null
@@ -1,435 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Joakim Larsson Edstrom
-/***************************************************************************
- * Interrupt scheme and dmac hookup shamelessly based on esq5505.cpp
- *
- * 11/04/2016
- * Force SYS68K ISCSI-1 driver - This driver will be converted into a slot device once the VME bus driver exists.
- * The ISCSI-1 board is a VME slave board that reads command and returns results through dual ported RAM to the VME bus.
- *
- * http://bitsavers.trailing-edge.com/pdf/forceComputers/800114_Force_Introduction_to_the_SYS68K_ISCSI-1_Oct86.pdf
- *
- * Address Map
- * ----------------------------------------------------------
- * Address Range Description
- * ----------------------------------------------------------
- * 00 0000 - 00 0007 Initialisation vectors from system EPROM
- * 00 0008 - 00 1FFF Local SRAM
- * 00 2000 - 01 FFFF Dynamic Dual Port RAM
- * C4 0000 - C4 001F SCSIbus controller
- * C8 0000 - C8 00FF DMAC
- * CC 0000 - CC 0007 FDC
- * CC 0009 - CC 0009 Control Register
- * D0 0000 - D0 003F PI/T
- * E0 0000 - E7 0000 EPROMs
- * ----------------------------------------------------------
- *
- * Interrupt sources
- * ----------------------------------------------------------
- * Description Device Lvl IRQ VME board
- * /Board Vector Address
- * ----------------------------------------------------------
- * On board Sources
- * ABORT P3 p13 1 AV1
- * DMA controller 68450 2 DMAC/AV2
- * SCSI bus controller NCR 5386S 3 AV3
- * Floppy Disk controller WD 1772 4 AV4
- * Parallel interface and timer 68230 5 PIT timer
- * --- 6 ---
- * Parallel interface and timer 65230 7 PIT port
- * ----------------------------------------------------------
- *
- * TODO:
- * - Write and attach a NCR5386S SCSI device
- * - Find a floppy image and present it to the WD1772 floppy controller
- * - Add VME bus driver
- * - Let a controller CPU board (eg CPU-1 or CPU-30) boot from floppy or SCSI disk
- *
- ****************************************************************************/
-#define TODO "Driver for SCSI NCR5386s device needed\n"
-
-#include "emu.h"
-#include "cpu/m68000/m68000.h"
-#include "machine/68230pit.h"
-#include "machine/wd_fdc.h"
-#include "machine/hd63450.h" // compatible with MC68450
-#include "machine/clock.h"
-#include "formats/pc_dsk.h"
-
-#define VERBOSE 0
-
-#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#if VERBOSE == 2
-#define logerror printf
-#endif
-
-#ifdef _MSC_VER
-#define FUNCNAME __func__
-#define LLFORMAT "%I64%"
-#else
-#define FUNCNAME __PRETTY_FUNCTION__
-#define LLFORMAT "%lld"
-#endif
-
-#define CPU_CRYSTAL XTAL_20MHz /* Jauch */
-#define PIT_CRYSTAL XTAL_16MHz /* Jauch */
-
-class fcscsi1_state : public driver_device
-{
-public:
-fcscsi1_state(const machine_config &mconfig, device_type type, const char *tag) :
- driver_device (mconfig, type, tag),
- m_maincpu (*this, "maincpu")
- ,m_fdc (*this, "fdc")
- ,m_pit (*this, "pit")
- ,m_dmac(*this, "mc68450")
- ,m_tcr (0)
-{
-}
- DECLARE_READ16_MEMBER (bootvect_r);
- DECLARE_READ8_MEMBER (tcr_r);
- DECLARE_WRITE8_MEMBER (tcr_w);
- DECLARE_WRITE8_MEMBER (led_w);
-
- IRQ_CALLBACK_MEMBER(maincpu_irq_acknowledge_callback);
-
- //dmac
- DECLARE_WRITE8_MEMBER(dma_end);
- DECLARE_WRITE8_MEMBER(dma_error);
-
- //fdc
- DECLARE_WRITE8_MEMBER(fdc_irq);
- DECLARE_READ8_MEMBER(fdc_read_byte);
- DECLARE_WRITE8_MEMBER(fdc_write_byte);
- DECLARE_FLOPPY_FORMATS(floppy_formats);
-
- /* Dummy driver routines */
- DECLARE_READ8_MEMBER (not_implemented_r);
- DECLARE_WRITE8_MEMBER (not_implemented_w);
-
- DECLARE_READ8_MEMBER (scsi_r);
- DECLARE_WRITE8_MEMBER (scsi_w);
-
- uint8_t fdc_irq_state;
- uint8_t dmac_irq_state;
- int dmac_irq_vector;
-
- virtual void machine_start () override;
- void update_irq_to_maincpu();
-
-protected:
-
-private:
- required_device<cpu_device> m_maincpu;
- required_device<wd1772_t> m_fdc;
- required_device<pit68230_device> m_pit;
- required_device<hd63450_device> m_dmac;
-
- uint8_t m_tcr;
-
- // Pointer to System ROMs needed by bootvect_r
- uint16_t *m_sysrom;
-};
-
-static ADDRESS_MAP_START (fcscsi1_mem, AS_PROGRAM, 16, fcscsi1_state)
- ADDRESS_MAP_UNMAP_HIGH
- AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* Vectors mapped from System EPROM */
- AM_RANGE (0x000008, 0x001fff) AM_RAM /* SRAM */
- AM_RANGE (0x002000, 0x01ffff) AM_RAM /* Dual Ported RAM */
- AM_RANGE (0xe00000, 0xe7ffff) AM_ROM /* System EPROM Area 32Kb DEBUGGER supplied */
- AM_RANGE (0xd00000, 0xd0003f) AM_DEVREADWRITE8 ("pit", pit68230_device, read, write, 0x00ff)
-// AM_RANGE (0xc40000, 0xc4001f) AM_DEVREADWRITE8("scsi", ncr5386_device, read, write, 0x00ff) /* SCSI Controller interface - device support not yet available*/
- AM_RANGE (0xc40000, 0xc4001f) AM_READWRITE8 (scsi_r, scsi_w, 0x00ff)
- AM_RANGE (0xc80000, 0xc800ff) AM_DEVREADWRITE("mc68450", hd63450_device, read, write) /* DMA Controller interface */
- AM_RANGE (0xcc0000, 0xcc0007) AM_DEVREADWRITE8("fdc", wd1772_t, read, write, 0x00ff) /* Floppy Controller interface */
- AM_RANGE (0xcc0008, 0xcc0009) AM_READWRITE8 (tcr_r, tcr_w, 0x00ff) /* The Control Register, SCSI ID and FD drive select bits */
-ADDRESS_MAP_END
-
-/* Input ports */
-static INPUT_PORTS_START (fcscsi1)
-INPUT_PORTS_END
-
-/* Start it up */
-void fcscsi1_state::machine_start ()
-{
- LOG (("machine_start\n"));
-
- /* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
- m_sysrom = (uint16_t*)(memregion ("maincpu")->base () + 0xe00000);
-
-}
-
-/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
-READ16_MEMBER (fcscsi1_state::bootvect_r){
- return m_sysrom [offset];
-}
-
-/* The Control Register - discretely implemented on the PCB
-Bit #: 7 6 5 4 3 2 1 0
- \ \ \ \ \ \ \ \ Floppy Disk Side Select
- \ \ \ \ \ \ \ Floppy Disk Drive Select 0
- \ \ \ \ \ \ Floppy Disk Drive Select 1
- \ \ \ \ \ Floppy Disk Drive Select 2
- \ \ \ \ Floppy Disk Drive Select 3
- \ \ \ ISCSI-l I.D. Bit #0
- \ \ ISCSI-l I.D. Bit #1
- \ ISCSI-l 1.D. Bit #2
-*/
-
-READ8_MEMBER (fcscsi1_state::tcr_r){
- LOG(("%s\n", FUNCNAME));
- return (uint8_t) m_tcr;
-}
-
-WRITE8_MEMBER (fcscsi1_state::tcr_w){
- floppy_image_device *floppy0 = m_fdc->subdevice<floppy_connector>("0")->get_device();
- floppy_image_device *floppy1 = m_fdc->subdevice<floppy_connector>("1")->get_device();
- floppy_image_device *floppy2 = m_fdc->subdevice<floppy_connector>("2")->get_device();
- floppy_image_device *floppy3 = m_fdc->subdevice<floppy_connector>("3")->get_device();
- floppy_image_device *floppy = nullptr;
-
- if (!BIT(data, 1)) floppy = floppy0;
- else
- if (!BIT(data, 2)) floppy = floppy1;
- else
- if (!BIT(data, 3)) floppy = floppy2;
- else
- if (!BIT(data, 4)) floppy = floppy3;
-
- if (floppy) {
- m_fdc->set_floppy(floppy);
- floppy->ss_w(!BIT(data, 0));
- floppy->mon_w(0);
- } else {
- floppy0->mon_w(1);
- floppy1->mon_w(1);
- floppy2->mon_w(1);
- floppy3->mon_w(1);
- }
-
- LOG(("%s [%02x]\n", FUNCNAME, data));
- m_tcr = data;
- return;
-}
-
-WRITE8_MEMBER (fcscsi1_state::led_w){
- LOG(("%s [%02x]\n", FUNCNAME, data));
-
- m_fdc->dden_w(BIT(data, 7));
-
- return;
-}
-
-WRITE8_MEMBER(fcscsi1_state::dma_end)
-{
- if (data != 0)
- {
- dmac_irq_state = 1;
- dmac_irq_vector = m_dmac->get_vector(offset);
- }
- else
- {
- dmac_irq_state = 0;
- }
-
- update_irq_to_maincpu();
-}
-
-WRITE8_MEMBER(fcscsi1_state::dma_error)
-{
- if(data != 0)
- {
- logerror("DMAC error, vector = %x\n", m_dmac->get_error_vector(offset));
- dmac_irq_state = 1;
- dmac_irq_vector = m_dmac->get_vector(offset);
- }
- else
- {
- dmac_irq_state = 0;
- }
-
- update_irq_to_maincpu();
-}
-
-WRITE8_MEMBER(fcscsi1_state::fdc_irq)
-{
- if (data != 0)
- {
- fdc_irq_state = 1;
- }
- else
- {
- fdc_irq_state = 0;
- }
- update_irq_to_maincpu();
-}
-
-READ8_MEMBER(fcscsi1_state::fdc_read_byte)
-{
- return m_fdc->data_r();
-}
-
-WRITE8_MEMBER(fcscsi1_state::fdc_write_byte)
-{
- m_fdc->data_w(data & 0xff);
-}
-
-READ8_MEMBER(fcscsi1_state::scsi_r)
-{
- uint8_t data = 0;
-
- // fake diag status
- if (offset == 9)
- data = 0x80;
-
- LOG(("scsi R %02x == %02x\n", offset, data));
-
- return data;
-}
-
-WRITE8_MEMBER(fcscsi1_state::scsi_w)
-{
- LOG(("scsi W %02x <- %02x\n", offset, data));
-}
-
-READ8_MEMBER (fcscsi1_state::not_implemented_r){
- static int been_here = 0;
- if (!been_here++){
- logerror(TODO);
- printf(TODO);
- }
- return (uint8_t) 0;
-}
-
-WRITE8_MEMBER (fcscsi1_state::not_implemented_w){
- static int been_here = 0;
- if (!been_here++){
- logerror(TODO);
- printf(TODO);
- }
- return;
-}
-
-/*
-----------------------------------------------------
- IRQ IRQ
-Level Source B4l inserted B4l removed (Def)
------------------------------------------------------
- 1 P3 Pin #13 AV1 Autovector AV1 Autovector
- 2 DMAC DMAC AV2 Autovector
- 3 SCSIBC AV3 Autovector AV3 Autovector
- 4 FDC AV4 Autovector AV4 Autovector
- 5 PI/T Timer PI/T Timer Vect PI/T Timer Vect
- 6 -- -- --
- 7 PI/T Port PI/T Port Vect PI/T Port Vect
-------------------------------------------------------
-Default configuration: B41 jumper removed
-
-The PI/T port interrupt can be used under software control to
-cause non-maskable (Level 7) interrupts if the watchdog timer
-elapses and/or if the VMEbus interrupt trigger call occurs.
-*/
-
-/* TODO: Add configurable B41 jumper */
-#define B41 0
-
-void fcscsi1_state::update_irq_to_maincpu() {
- if (fdc_irq_state) {
- m_maincpu->set_input_line(M68K_IRQ_3, ASSERT_LINE);
- m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
- m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
- } else if (dmac_irq_state) {
- m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
- m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
-#if B41 == 1
- m_maincpu->set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, dmac_irq_vector);
-#else
- m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
-#endif
- } else {
- m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
- m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
- m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
- }
-}
-
-IRQ_CALLBACK_MEMBER(fcscsi1_state::maincpu_irq_acknowledge_callback)
-{
- // We immediately update the interrupt presented to the CPU, so that it doesn't
- // end up retrying the same interrupt over and over. We then return the appropriate vector.
- int vector = 0;
- switch(irqline) {
- case 2:
- dmac_irq_state = 0;
- vector = dmac_irq_vector;
- break;
- default:
- logerror("\nUnexpected IRQ ACK Callback: IRQ %d\n", irqline);
- return 0;
- }
- update_irq_to_maincpu();
- return vector;
-}
-
-FLOPPY_FORMATS_MEMBER( fcscsi1_state::floppy_formats )
- FLOPPY_PC_FORMAT
-FLOPPY_FORMATS_END
-
-static SLOT_INTERFACE_START( fcscsi_floppies )
- SLOT_INTERFACE( "525qd", FLOPPY_525_QD )
-SLOT_INTERFACE_END
-
-/*
- * Machine configuration
- */
-static MACHINE_CONFIG_START (fcscsi1, fcscsi1_state)
- /* basic machine hardware */
- MCFG_CPU_ADD ("maincpu", M68010, CPU_CRYSTAL / 2) /* 7474 based frequency divide by 2 */
- MCFG_CPU_PROGRAM_MAP (fcscsi1_mem)
- MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(fcscsi1_state, maincpu_irq_acknowledge_callback)
-
- /* FDC */
- MCFG_WD1772_ADD("fdc", PIT_CRYSTAL / 2)
- MCFG_WD_FDC_INTRQ_CALLBACK(WRITE8(fcscsi1_state, fdc_irq))
- MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("mc68450", hd63450_device, drq1_w))
- MCFG_FLOPPY_DRIVE_ADD("fdc:0", fcscsi_floppies, "525qd", fcscsi1_state::floppy_formats)
- MCFG_FLOPPY_DRIVE_ADD("fdc:1", fcscsi_floppies, "525qd", fcscsi1_state::floppy_formats)
- MCFG_FLOPPY_DRIVE_ADD("fdc:2", fcscsi_floppies, "525qd", fcscsi1_state::floppy_formats)
- MCFG_FLOPPY_DRIVE_ADD("fdc:3", fcscsi_floppies, "525qd", fcscsi1_state::floppy_formats)
-
- /* PIT Parallel Interface and Timer device */
- MCFG_DEVICE_ADD ("pit", PIT68230, PIT_CRYSTAL / 2) /* 7474 based frequency divide by 2 */
- MCFG_PIT68230_PB_OUTPUT_CB(WRITE8(fcscsi1_state, led_w))
-
- /* DMAC it is really a M68450 but the HD63850 is upwards compatible */
- MCFG_DEVICE_ADD("mc68450", HD63450, 0) // MC68450 compatible
- MCFG_HD63450_CPU("maincpu") // CPU - 68010
- MCFG_HD63450_CLOCKS(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2))
- MCFG_HD63450_BURST_CLOCKS(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50))
- MCFG_HD63450_DMA_END_CB(WRITE8(fcscsi1_state, dma_end))
- MCFG_HD63450_DMA_ERROR_CB(WRITE8(fcscsi1_state, dma_error))
- //MCFG_HD63450_DMA_READ_0_CB(READ8(fcscsi1_state, scsi_read_byte)) // ch 0 = SCSI
- //MCFG_HD63450_DMA_WRITE_0_CB(WRITE8(fcscsi1_state, scsi_write_byte))
- MCFG_HD63450_DMA_READ_1_CB(READ8(fcscsi1_state, fdc_read_byte)) // ch 1 = fdc
- MCFG_HD63450_DMA_WRITE_1_CB(WRITE8(fcscsi1_state, fdc_write_byte))
-MACHINE_CONFIG_END
-
-/* ROM definitions */
-ROM_START (fcscsi1)
- ROM_REGION (0x1000000, "maincpu", 0)
-
- /* Besta ROM:s - apparantly patched Force ROM:s */
- ROM_SYSTEM_BIOS(0, "Besta 88", "Besta 88")
- ROMX_LOAD ("besta88_scsi_lower.ROM", 0xe00001, 0x4000, CRC (fb3ab364) SHA1 (d79112100f1c4beaf358e006efd4dde5e300b0ba), ROM_SKIP(1) | ROM_BIOS(1))
- ROMX_LOAD ("besta88_scsi_upper.ROM", 0xe00000, 0x4000, CRC (41f9cdf4) SHA1 (66b998bbf9459f0a613718260e05e97749532073), ROM_SKIP(1) | ROM_BIOS(1))
-
- /* Force ROM:s */
- ROM_SYSTEM_BIOS(1, "ISCSI-1 v3.7", "Force Computer SYS68K/ISCSI-1 firmware v3.7")
- ROMX_LOAD ("ISCSI-1_V3.7_L.BIN", 0xe00001, 0x4000, CRC (83d95ab7) SHA1 (bf249910bcb6cb0b04dda2a95a38a0f90b553352), ROM_SKIP(1) | ROM_BIOS(2))
- ROMX_LOAD ("ISCSI-1_V3.7_U.BIN", 0xe00000, 0x4000, CRC (58815831) SHA1 (074085ef96e1fe2a551938bdeee6a9cab40ff09c), ROM_SKIP(1) | ROM_BIOS(2))
-
-ROM_END
-
-/* Driver */
-/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
-COMP( 1986, fcscsi1, 0, 0, fcscsi1, fcscsi1, driver_device, 0, "Force Computers Gmbh", "SYS68K/SCSI-1", MACHINE_IS_SKELETON )
diff --git a/src/mame/drivers/mvme147.cpp b/src/mame/drivers/mvme147.cpp
index c513572f57c..9f3568104b2 100644
--- a/src/mame/drivers/mvme147.cpp
+++ b/src/mame/drivers/mvme147.cpp
@@ -154,15 +154,26 @@
#include "emu.h"
#include "cpu/m68000/m68000.h"
+#include "bus/vme/vme.h"
+#include "bus/vme/vme_mvme350.h"
#include "machine/z80scc.h"
#include "bus/rs232/rs232.h"
#include "machine/clock.h"
#include "machine/timekpr.h"
-#define VERBOSE 1
+#define LOG_GENERAL 0x01
+#define LOG_SETUP 0x02
+#define LOG_PRINTF 0x04
-#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#if VERBOSE >= 2
+#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP | LOG_GENERAL)
+
+#define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0)
+#define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0)
+
+#define LOG(...) LOGMASK(LOG_GENERAL, __VA_ARGS__)
+#define LOGSETUP(...) LOGMASK(LOG_SETUP, __VA_ARGS__)
+
+#if VERBOSE & LOG_PRINTF
#define logerror printf
#endif
@@ -252,7 +263,7 @@ INPUT_PORTS_END
/* Start it up */
void mvme147_state::machine_start ()
{
- LOG(("--->%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint32_t*)(memregion ("roms")->base () + 0x800000);
@@ -262,7 +273,7 @@ void mvme147_state::machine_start ()
void mvme147_state::machine_reset ()
{
- LOG(("--->%s\n", FUNCNAME));
+ LOG("%s\n", FUNCNAME);
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
@@ -286,21 +297,21 @@ WRITE32_MEMBER (mvme147_state::bootvect_w){
*/
#if 0 /* Doesn't compile atm */
READ32_MEMBER (mvme147_state::pcc32_r){
- LOG(("--->%s[%04x]", FUNCNAME, offset));
+ LOG("%s[%04x]", FUNCNAME, offset);
switch(offset)
{
default:
- LOG(("unsupported register\n"));
+ LOG(" - unsupported register\n");
}
return 0x00;
}
WRITE32_MEMBER (mvme147_state::pcc32_w){
- LOG(("--->%s[%04x]= %08lx", FUNCNAME, offset, data));
+ LOG("%s[%04x]= %08lx", FUNCNAME, offset, data);
switch(offset)
{
default:
- LOG(("unsupported register\n"));
+ LOG("- unsupported register\n");
}
}
#endif
@@ -314,29 +325,29 @@ WRITE32_MEMBER (mvme147_state::pcc32_w){
READ16_MEMBER (mvme147_state::pcc16_r){
uint16_t ret = 0;
- LOG(("Call to %s[%04x]", FUNCNAME, offset));
+ LOG("Call to %s[%04x]", FUNCNAME, offset);
switch(offset)
{
- case P16_TIMER1_PRELOAD - P16BASE : LOG((" -> %02x Timer 1 preload - not implemented\n", ret)); break;
- case P16_TIMER1_COUNT - P16BASE : LOG((" -> %02x Timer 1 count - not implemented\n", ret)); break;
- case P16_TIMER2_PRELOAD - P16BASE : LOG((" -> %02x Timer 2 preload - not implemented\n", ret)); break;
- case P16_TIMER2_COUNT - P16BASE : LOG((" -> %02x Timer 2 count - not implemented\n", ret)); break;
+ case P16_TIMER1_PRELOAD - P16BASE : LOG(" -> %02x Timer 1 preload - not implemented\n", ret); break;
+ case P16_TIMER1_COUNT - P16BASE : LOG(" -> %02x Timer 1 count - not implemented\n", ret); break;
+ case P16_TIMER2_PRELOAD - P16BASE : LOG(" -> %02x Timer 2 preload - not implemented\n", ret); break;
+ case P16_TIMER2_COUNT - P16BASE : LOG(" -> %02x Timer 2 count - not implemented\n", ret); break;
default:
- LOG((" -> %02x unsupported register\n", ret));
+ LOG(" -> %02x unsupported register\n", ret);
}
return ret;
}
WRITE16_MEMBER (mvme147_state::pcc16_w){
- LOG(("Call to %s[%04x] <- %04x - ", FUNCNAME, offset, data));
+ LOG("Call to %s[%04x] <- %04x - ", FUNCNAME, offset, data);
switch(offset)
{
- case P16_TIMER1_PRELOAD - P16BASE : LOG(("Timer 1 preload - not implemented\n")); break;
- case P16_TIMER1_COUNT - P16BASE : LOG(("Timer 1 count - not implemented\n")); break;
- case P16_TIMER2_PRELOAD - P16BASE : LOG(("Timer 2 preload - not implemented\n")); break;
- case P16_TIMER2_COUNT - P16BASE : LOG(("Timer 2 count - not implemented\n")); break;
+ case P16_TIMER1_PRELOAD - P16BASE : LOG("Timer 1 preload - not implemented\n"); break;
+ case P16_TIMER1_COUNT - P16BASE : LOG("Timer 1 count - not implemented\n"); break;
+ case P16_TIMER2_PRELOAD - P16BASE : LOG("Timer 2 preload - not implemented\n"); break;
+ case P16_TIMER2_COUNT - P16BASE : LOG("Timer 2 count - not implemented\n"); break;
default:
- LOG(("unsupported register\n"));
+ LOG("unsupported register\n");
}
}
@@ -371,22 +382,22 @@ WRITE16_MEMBER (mvme147_state::pcc16_w){
READ8_MEMBER (mvme147_state::pcc8_r){
uint8_t ret = 0;
- LOG(("Call to %s[%04x] ", FUNCNAME, offset));
+ LOG("Call to %s[%04x] ", FUNCNAME, offset);
switch(offset + P8BASE)
{
- case P8_TIMER1_INT_CNTL : LOG((" -> %02x - Timer 1 Interrupt Control - not implemented\n", ret)); break;
- case P8_TIMER1_CNTL : LOG((" -> %02x - Timer 1 Control - not implemented\n", ret)); break;
- case P8_TIMER2_INT_CNTL : LOG((" -> %02x - Timer 2 Interrupt Control - not implemented\n", ret)); break;
- case P8_TIMER2_CNTL : LOG((" -> %02x - Timer 2 Control - not implemented\n", ret)); break;
- case P8_ACFAIL_INT_CNTL : LOG((" -> %02x - AC Fail Interrupt Control Register - not implemented\n", ret)); break;
- case P8_WDOG_TIMER_CNTL : LOG((" -> %02x - Watchdog Timer Control Register - not implemented\n", ret)); break;
- case P8_PRINTER_INT_CNTL : LOG((" -> %02x - Printer Interrupt Control Register - not implemented\n", ret)); break;
- case P8_PRINTER_CNTL : LOG((" -> %02x - Printer Control Register - not implemented\n", ret)); break;
- case P8_DMA_INT_CNTL : LOG((" -> %02x - DMA Interrupt Control Register - not implemented\n", ret)); break;
- case P8_DMA_CNTL_STAT : LOG((" -> %02x - DMA Control and Status Register - not implemented\n", ret)); break;
- case P8_BUSERR_CNTL : LOG((" -> %02x - Bus Error Interrupt Control Register - not implemented\n", ret)); break;
- case P8_DMA_STATUS : LOG((" -> %02x - DMA Status Register - not implemented\n", ret)); break;
- case P8_ABORT_INT_CNTL : LOG((" -> %02x - Abort Interrupt Control Register - not fully implemented\n", ret));
+ case P8_TIMER1_INT_CNTL : LOG(" -> %02x - Timer 1 Interrupt Control - not implemented\n", ret); break;
+ case P8_TIMER1_CNTL : LOG(" -> %02x - Timer 1 Control - not implemented\n", ret); break;
+ case P8_TIMER2_INT_CNTL : LOG(" -> %02x - Timer 2 Interrupt Control - not implemented\n", ret); break;
+ case P8_TIMER2_CNTL : LOG(" -> %02x - Timer 2 Control - not implemented\n", ret); break;
+ case P8_ACFAIL_INT_CNTL : LOG(" -> %02x - AC Fail Interrupt Control Register - not implemented\n", ret); break;
+ case P8_WDOG_TIMER_CNTL : LOG(" -> %02x - Watchdog Timer Control Register - not implemented\n", ret); break;
+ case P8_PRINTER_INT_CNTL : LOG(" -> %02x - Printer Interrupt Control Register - not implemented\n", ret); break;
+ case P8_PRINTER_CNTL : LOG(" -> %02x - Printer Control Register - not implemented\n", ret); break;
+ case P8_DMA_INT_CNTL : LOG(" -> %02x - DMA Interrupt Control Register - not implemented\n", ret); break;
+ case P8_DMA_CNTL_STAT : LOG(" -> %02x - DMA Control and Status Register - not implemented\n", ret); break;
+ case P8_BUSERR_CNTL : LOG(" -> %02x - Bus Error Interrupt Control Register - not implemented\n", ret); break;
+ case P8_DMA_STATUS : LOG(" -> %02x - DMA Status Register - not implemented\n", ret); break;
+ case P8_ABORT_INT_CNTL : LOG(" -> %02x - Abort Interrupt Control Register - not fully implemented\n", ret);
/* Bit 3 When this bit is high, the interrupt is enabled. The interrupt is disabled when this bit is low. This bit is cleared by reset.
Bit 6 This bit indicates the current state of the ABORT switch. When this bit is low, the ABORT switch is not pressed. When this bit is
high, the ABORT switch is pressed.
@@ -395,46 +406,46 @@ READ8_MEMBER (mvme147_state::pcc8_r){
it remains cleared until the next leading edge of interrupt enable and abort. This bit is cleared by reset. */
ret = 0; /* Always return reset values for now */
break;
- case P8_TABADD_FC_CNTL : LOG((" -> %02x - Table Address Function Code Register - not implemented\n", ret)); break;
- case P8_SERIAL_INT_CNTL : LOG((" -> %02x - Serial Port Interrupt Control Register - not implemented\n", ret)); break;
- case P8_GEN_PURP_CNTL : LOG((" -> %02x - General Purpose Control Register - not implemented\n", ret)); break;
- case P8_LAN_INT_CNTL : LOG((" -> %02x - LAN Interrupt Control Register - not implemented\n", ret)); break;
- case P8_GEN_PURP_STAT : LOG((" -> %02x - General Purpose Status Register\n", ret));
+ case P8_TABADD_FC_CNTL : LOG(" -> %02x - Table Address Function Code Register - not implemented\n", ret); break;
+ case P8_SERIAL_INT_CNTL : LOG(" -> %02x - Serial Port Interrupt Control Register - not implemented\n", ret); break;
+ case P8_GEN_PURP_CNTL : LOG(" -> %02x - General Purpose Control Register - not implemented\n", ret); break;
+ case P8_LAN_INT_CNTL : LOG(" -> %02x - LAN Interrupt Control Register - not implemented\n", ret); break;
+ case P8_GEN_PURP_STAT : LOG(" -> %02x - General Purpose Status Register\n", ret);
ret = m_genpurp_stat;
break;
- case P8_SCSI_INT_CNTL : LOG((" -> %02x - SCSI Port Interrupt Control Register - not implemented\n", ret)); break;
- case P8_SLAVE_BASE_ADDR : LOG((" -> %02x - Slave Base Address Register - not implemented\n", ret)); break;
- case P8_SWI_1_CNTL : LOG((" -> %02x - Software Interrupt 1 Control Register - not implemented\n", ret)); break;
- case P8_INT_VECT_BASE : LOG((" -> %02x - Interrupt Vector Base - not implemented\n", ret)); break;
- case P8_SWI_2_CNTL : LOG((" -> %02x - Software Interrupt 2 Control Register - not implemented\n", ret)); break;
- case P8_REVISION_LEVEL : LOG((" -> %02x - PCC Revision Level Register - not implemented\n", ret)); break;
- case P8_PRINTER_STATUS : LOG((" -> %02x - Printer Status Register - not implemented\n", ret)); break;
+ case P8_SCSI_INT_CNTL : LOG(" -> %02x - SCSI Port Interrupt Control Register - not implemented\n", ret); break;
+ case P8_SLAVE_BASE_ADDR : LOG(" -> %02x - Slave Base Address Register - not implemented\n", ret); break;
+ case P8_SWI_1_CNTL : LOG(" -> %02x - Software Interrupt 1 Control Register - not implemented\n", ret); break;
+ case P8_INT_VECT_BASE : LOG(" -> %02x - Interrupt Vector Base - not implemented\n", ret); break;
+ case P8_SWI_2_CNTL : LOG(" -> %02x - Software Interrupt 2 Control Register - not implemented\n", ret); break;
+ case P8_REVISION_LEVEL : LOG(" -> %02x - PCC Revision Level Register - not implemented\n", ret); break;
+ case P8_PRINTER_STATUS : LOG(" -> %02x - Printer Status Register - not implemented\n", ret); break;
default:
- LOG((" -> %02x - unsupported register\n", ret));
+ LOG(" -> %02x - unsupported register\n", ret);
}
return ret;
}
WRITE8_MEMBER (mvme147_state::pcc8_w){
- LOG(("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data));
+ LOG("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data);
switch(offset + P8BASE)
{
- case P8_TIMER1_INT_CNTL : LOG(("Timer 1 Interrupt Control - not implemented\n")); break;
- case P8_TIMER1_CNTL : LOG(("Timer 1 Control - not implemented\n")); break;
- case P8_TIMER2_INT_CNTL : LOG(("Timer 2 Interrupt Control - not implemented\n")); break;
- case P8_TIMER2_CNTL : LOG(("Timer 2 Control - not implemented\n")); break;
- case P8_ACFAIL_INT_CNTL : LOG(("AC Fail Interrupt Control Register - not implemented\n")); break;
- case P8_WDOG_TIMER_CNTL : LOG(("Watchdog Timer Control Register - not implemented\n")); break;
- case P8_PRINTER_INT_CNTL : LOG(("Printer Interrupt Control Register - not implemented\n")); break;
- case P8_PRINTER_CNTL : LOG(("Printer Control Register - not implemented\n")); break;
- case P8_DMA_INT_CNTL : LOG(("DMA Interrupt Control Register - not implemented\n")); break;
- case P8_DMA_CNTL_STAT : LOG(("DMA Control and Status Register - not implemented\n")); break;
- case P8_BUSERR_CNTL : LOG(("Bus Error Interrupt Control Register - not implemented\n")); break;
- case P8_DMA_STATUS : LOG(("DMA Status Register - not implemented\n")); break;
- case P8_ABORT_INT_CNTL : LOG(("Abort Interrupt Control Register - not implemented\n")); break;
- case P8_TABADD_FC_CNTL : LOG(("Table Address Function Code Register - not implemented\n")); break;
- case P8_SERIAL_INT_CNTL : LOG(("Serial Port Interrupt Control Register - not implemented\n")); break;
- case P8_GEN_PURP_CNTL : LOG(("General Purpose Control Register - not implemented\n"));
+ case P8_TIMER1_INT_CNTL : LOG("Timer 1 Interrupt Control - not implemented\n"); break;
+ case P8_TIMER1_CNTL : LOG("Timer 1 Control - not implemented\n"); break;
+ case P8_TIMER2_INT_CNTL : LOG("Timer 2 Interrupt Control - not implemented\n"); break;
+ case P8_TIMER2_CNTL : LOG("Timer 2 Control - not implemented\n"); break;
+ case P8_ACFAIL_INT_CNTL : LOG("AC Fail Interrupt Control Register - not implemented\n"); break;
+ case P8_WDOG_TIMER_CNTL : LOG("Watchdog Timer Control Register - not implemented\n"); break;
+ case P8_PRINTER_INT_CNTL: LOG("Printer Interrupt Control Register - not implemented\n"); break;
+ case P8_PRINTER_CNTL : LOG("Printer Control Register - not implemented\n"); break;
+ case P8_DMA_INT_CNTL : LOG("DMA Interrupt Control Register - not implemented\n"); break;
+ case P8_DMA_CNTL_STAT : LOG("DMA Control and Status Register - not implemented\n"); break;
+ case P8_BUSERR_CNTL : LOG("Bus Error Interrupt Control Register - not implemented\n"); break;
+ case P8_DMA_STATUS : LOG("DMA Status Register - not implemented\n"); break;
+ case P8_ABORT_INT_CNTL : LOG("Abort Interrupt Control Register - not implemented\n"); break;
+ case P8_TABADD_FC_CNTL : LOG("Table Address Function Code Register - not implemented\n"); break;
+ case P8_SERIAL_INT_CNTL : LOG("Serial Port Interrupt Control Register - not implemented\n"); break;
+ case P8_GEN_PURP_CNTL : LOG("General Purpose Control Register - not implemented\n");
/*Bits 0-1 These bits control local RAM parity checking. These bits should not be enabled on the MVME147-010.
These bits are cleared by reset. x0 = parity disabled, x1 = parity enabled
Bit 2 This bit is used to test the parity generating and checking logic. When this bit is low, correct parity is written to the DRAM;
@@ -449,8 +460,8 @@ WRITE8_MEMBER (mvme147_state::pcc8_w){
TODO: Bit 4-7 needs to be implemented
*/
break;
- case P8_LAN_INT_CNTL : LOG(("LAN Interrupt Control Register - not implemented\n")); break;
- case P8_GEN_PURP_STAT : LOG(("General Purpose Status Register\n"));
+ case P8_LAN_INT_CNTL : LOG("LAN Interrupt Control Register - not implemented\n"); break;
+ case P8_GEN_PURP_STAT : LOG("General Purpose Status Register\n");
/* Bit 0 This bit is set when a parity error occurs while the local processor is accessing RAM. This bit is cleared by writing a 1 to it.
This bit is cleared by reset.
Bit 1 This bit is set when a power-up reset occurs. It is cleared by writing a 1 to it.
@@ -459,15 +470,15 @@ WRITE8_MEMBER (mvme147_state::pcc8_w){
m_genpurp_stat &= ((data & 1) ? ~1 : 0xff); // Check if parity error bit needs to be cleared
m_genpurp_stat &= ((data & 2) ? ~2 : 0xff); // Check if power up reset bit needs to be cleared
break;
- case P8_SCSI_INT_CNTL : LOG(("SCSI Port Interrupt Control Register - not implemented\n")); break;
- case P8_SLAVE_BASE_ADDR : LOG(("Slave Base Address Register - not implemented\n")); break;
- case P8_SWI_1_CNTL : LOG(("Software Interrupt 1 Control Register - not implemented\n")); break;
- case P8_INT_VECT_BASE : LOG(("Interrupt Vector Base - not implemented\n")); break;
- case P8_SWI_2_CNTL : LOG(("Software Interrupt 2 Control Register - not implemented\n")); break;
- case P8_REVISION_LEVEL : LOG(("PCC Revision Level Register - not implemented\n")); break;
- case P8_PRINTER_DATA : LOG(("Printer Data Register - not implemented\n")); break;
+ case P8_SCSI_INT_CNTL : LOG("SCSI Port Interrupt Control Register - not implemented\n"); break;
+ case P8_SLAVE_BASE_ADDR : LOG("Slave Base Address Register - not implemented\n"); break;
+ case P8_SWI_1_CNTL : LOG("Software Interrupt 1 Control Register - not implemented\n"); break;
+ case P8_INT_VECT_BASE : LOG("Interrupt Vector Base - not implemented\n"); break;
+ case P8_SWI_2_CNTL : LOG("Software Interrupt 2 Control Register - not implemented\n"); break;
+ case P8_REVISION_LEVEL : LOG("PCC Revision Level Register - not implemented\n"); break;
+ case P8_PRINTER_DATA : LOG("Printer Data Register - not implemented\n"); break;
default:
- LOG(("unsupported register\n"));
+ LOG("unsupported register\n");
}
}
@@ -494,11 +505,11 @@ WRITE8_MEMBER (mvme147_state::pcc8_w){
READ8_MEMBER (mvme147_state::vmechip_r){
uint8_t ret = 0;
- LOG(("Call to %s[%04x] ", FUNCNAME, offset));
+ LOG("Call to %s[%04x] ", FUNCNAME, offset);
switch(offset * 2 + VCBASE)
{
case VC_SYS_CNTL_CONF :
- LOG((" -> %02x - System Controller Configuration Register - not implemented\n", ret));
+ LOG(" -> %02x - System Controller Configuration Register - not implemented\n", ret);
ret = m_vc_cntl_conf;
break;
case VC_VMEBUS_REQ_CONF :
@@ -531,11 +542,11 @@ READ8_MEMBER (mvme147_state::vmechip_r){
This bit is cleared by any reset.
*/
ret = 1 << 6; /* Let BUG147 think we are bus master. TODO: Implement proper VME bus signalling */
- LOG((" -> %02x - VMEbus Requester Configuration Register - not implemented\n", ret));
+ LOG(" -> %02x - VMEbus Requester Configuration Register - not implemented\n", ret);
break;
- case VC_MASTER_CONF : LOG((" -> %02x - Master Configuration Register - not implemented\n", ret)); break;
- case VC_SLAVE_CONF : LOG((" -> %02x - Slave Configuration Register - not implemented\n", ret)); break;
- case VC_TIMER_CONF : LOG((" -> %02x - Timer Configuration Register - not implemented\n", ret));
+ case VC_MASTER_CONF : LOG(" -> %02x - Master Configuration Register - not implemented\n", ret); break;
+ case VC_SLAVE_CONF : LOG(" -> %02x - Slave Configuration Register - not implemented\n", ret); break;
+ case VC_TIMER_CONF : LOG(" -> %02x - Timer Configuration Register - not implemented\n", ret);
/*Bits 0-1 These two bits configure the local time-out period. They are set to 1 by any reset.
LBTO1 LBTO0 Time-Out Period
0 0 102 microseconds
@@ -563,44 +574,44 @@ READ8_MEMBER (mvme147_state::vmechip_r){
This causes the arbiter to arbitrate any pending requests for the bus. This bit is set to 1 by SYSRESET.
*/
break;
- case VC_SLAVE_ADR_MOD : LOG((" -> %02x - Slave Address Modifier Register - not implemented\n", ret)); break;
- case VC_MASTER_ADR_MOD : LOG((" -> %02x - Master Address Modifier Register - not implemented\n", ret)); break;
- case VC_INT_HNDL_MASK : LOG((" -> %02x - Interrupt Handler Mask Register - not implemented\n", ret)); break;
- case VC_UTIL_INT_MASK : LOG((" -> %02x - Utility Interrupt Mask Register - not implemented\n", ret)); break;
- case VC_UTIL_INT_VECT : LOG((" -> %02x - Utility Interrupt Vector Register - not implemented\n", ret)); break;
- case VC_INT_REQUEST : LOG((" -> %02x - Interrupt Request Register - not implemented\n", ret)); break;
- case VC_VMEBUS_STAT_ID : LOG((" -> %02x - VMEbus Status/ID Register - not implemented\n", ret)); break;
- case VC_BUS_ERR_STATUS : LOG((" -> %02x - Bus Error Status Register - not implemented\n", ret)); break;
- case VC_GCSR_BASE_ADR : LOG((" -> %02x - GCSR Base Address Configuration Register - not implemented\n", ret)); break;
+ case VC_SLAVE_ADR_MOD : LOG(" -> %02x - Slave Address Modifier Register - not implemented\n", ret); break;
+ case VC_MASTER_ADR_MOD : LOG(" -> %02x - Master Address Modifier Register - not implemented\n", ret); break;
+ case VC_INT_HNDL_MASK : LOG(" -> %02x - Interrupt Handler Mask Register - not implemented\n", ret); break;
+ case VC_UTIL_INT_MASK : LOG(" -> %02x - Utility Interrupt Mask Register - not implemented\n", ret); break;
+ case VC_UTIL_INT_VECT : LOG(" -> %02x - Utility Interrupt Vector Register - not implemented\n", ret); break;
+ case VC_INT_REQUEST : LOG(" -> %02x - Interrupt Request Register - not implemented\n", ret); break;
+ case VC_VMEBUS_STAT_ID : LOG(" -> %02x - VMEbus Status/ID Register - not implemented\n", ret); break;
+ case VC_BUS_ERR_STATUS : LOG(" -> %02x - Bus Error Status Register - not implemented\n", ret); break;
+ case VC_GCSR_BASE_ADR : LOG(" -> %02x - GCSR Base Address Configuration Register - not implemented\n", ret); break;
default:
- LOG(("unsupported register"));
+ LOG("unsupported register");
}
return ret;
}
WRITE8_MEMBER (mvme147_state::vmechip_w){
- LOG(("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data));
+ LOG("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data);
switch(offset * 2 + VCBASE)
{
case VC_SYS_CNTL_CONF :
- LOG(("System Controller Configuration Register - not implemented\n"));
+ LOG("System Controller Configuration Register - not implemented\n");
m_vc_cntl_conf = data & 0xff;
break;
- case VC_VMEBUS_REQ_CONF : LOG(("VMEbus Requester Configuration Register - not implemented\n")); break;
- case VC_MASTER_CONF : LOG(("Master Configuration Register - not implemented\n")); break;
- case VC_SLAVE_CONF : LOG(("Slave Configuration Register - not implemented\n")); break;
- case VC_TIMER_CONF : LOG(("Timer Configuration Register - not implemented\n")); break;
- case VC_SLAVE_ADR_MOD : LOG(("Slave Address Modifier Register - not implemented\n")); break;
- case VC_MASTER_ADR_MOD : LOG(("Master Address Modifier Register - not implemented\n")); break;
- case VC_INT_HNDL_MASK : LOG(("Interrupt Handler Mask Register - not implemented\n")); break;
- case VC_UTIL_INT_MASK : LOG(("Utility Interrupt Mask Register - not implemented\n")); break;
- case VC_UTIL_INT_VECT : LOG(("Utility Interrupt Vector Register - not implemented\n")); break;
- case VC_INT_REQUEST : LOG(("Interrupt Request Register - not implemented\n")); break;
- case VC_VMEBUS_STAT_ID : LOG(("VMEbus Status/ID Register - not implemented\n")); break;
- case VC_BUS_ERR_STATUS : LOG(("Bus Error Status Register - not implemented\n")); break;
- case VC_GCSR_BASE_ADR : LOG(("GCSR Base Address Configuration Register - not implemented\n")); break;
+ case VC_VMEBUS_REQ_CONF : LOG("VMEbus Requester Configuration Register - not implemented\n"); break;
+ case VC_MASTER_CONF : LOG("Master Configuration Register - not implemented\n"); break;
+ case VC_SLAVE_CONF : LOG("Slave Configuration Register - not implemented\n"); break;
+ case VC_TIMER_CONF : LOG("Timer Configuration Register - not implemented\n"); break;
+ case VC_SLAVE_ADR_MOD : LOG("Slave Address Modifier Register - not implemented\n"); break;
+ case VC_MASTER_ADR_MOD : LOG("Master Address Modifier Register - not implemented\n"); break;
+ case VC_INT_HNDL_MASK : LOG("Interrupt Handler Mask Register - not implemented\n"); break;
+ case VC_UTIL_INT_MASK : LOG("Utility Interrupt Mask Register - not implemented\n"); break;
+ case VC_UTIL_INT_VECT : LOG("Utility Interrupt Vector Register - not implemented\n"); break;
+ case VC_INT_REQUEST : LOG("Interrupt Request Register - not implemented\n"); break;
+ case VC_VMEBUS_STAT_ID : LOG("VMEbus Status/ID Register - not implemented\n"); break;
+ case VC_BUS_ERR_STATUS : LOG("Bus Error Status Register - not implemented\n"); break;
+ case VC_GCSR_BASE_ADR : LOG("GCSR Base Address Configuration Register - not implemented\n"); break;
default:
- LOG(("unsupported register\n"));
+ LOG("unsupported register\n");
}
}
@@ -608,24 +619,28 @@ WRITE8_MEMBER (mvme147_state::vmechip_w){
#if 0
/* Dummy VME access methods until the VME bus device is ready for use */
READ16_MEMBER (mvme147_state::vme_a24_r){
- LOG (logerror ("vme_a24_r\n"));
+ LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
WRITE16_MEMBER (mvme147_state::vme_a24_w){
- LOG (logerror ("vme_a24_w\n"));
+ LOG("%s\n", FUNCNAME);
}
READ16_MEMBER (mvme147_state::vme_a16_r){
- LOG (logerror ("vme_16_r\n"));
+ LOG("%s\n", FUNCNAME);
return (uint16_t) 0;
}
WRITE16_MEMBER (mvme147_state::vme_a16_w){
- LOG (logerror ("vme_a16_w\n"));
+ LOG("%s\n", FUNCNAME);
}
#endif
+static SLOT_INTERFACE_START(mvme147_vme_cards)
+ SLOT_INTERFACE("mvme350", VME_MVME350)
+SLOT_INTERFACE_END
+
/*
* Machine configuration
*/
@@ -633,6 +648,8 @@ static MACHINE_CONFIG_START (mvme147, mvme147_state)
/* basic machine hardware */
MCFG_CPU_ADD ("maincpu", M68030, XTAL_16MHz)
MCFG_CPU_PROGRAM_MAP (mvme147_mem)
+ MCFG_VME_DEVICE_ADD("vme")
+ MCFG_VME_SLOT_ADD ("vme", "slot1", mvme147_vme_cards, nullptr)
MCFG_M48T02_ADD("m48t18") /* t08 differs only in accepted voltage levels compared to t18 */
diff --git a/src/mame/drivers/mzr8105.cpp b/src/mame/drivers/mzr8105.cpp
index 5d1a9e0fb55..3eeb35ca1e9 100644
--- a/src/mame/drivers/mzr8105.cpp
+++ b/src/mame/drivers/mzr8105.cpp
@@ -198,7 +198,6 @@ INPUT_PORTS_END
static SLOT_INTERFACE_START(mzr8105_vme_cards)
SLOT_INTERFACE("mzr8300", VME_MZR8300)
- SLOT_INTERFACE("mvme350", VME_MVME350)
SLOT_INTERFACE_END
/*
@@ -207,8 +206,8 @@ SLOT_INTERFACE_END
MACHINE_CONFIG_START (mzr8105, mzr8105_state)
MCFG_CPU_ADD ("maincpu", M68000, XTAL_10MHz)
MCFG_CPU_PROGRAM_MAP (mzr8105_mem)
- MCFG_VME_P1_DEVICE_ADD("vme")
- MCFG_VME_P1_SLOT_ADD ("vme", "slot1", mzr8105_vme_cards, nullptr)
+ MCFG_VME_DEVICE_ADD("vme")
+ MCFG_VME_SLOT_ADD ("vme", "slot1", mzr8105_vme_cards, nullptr)
MACHINE_CONFIG_END
/* ROM definitions */
diff --git a/src/mame/mame.lst b/src/mame/mame.lst
index a5830a51964..3b07e490b23 100644
--- a/src/mame/mame.lst
+++ b/src/mame/mame.lst
@@ -12229,15 +12229,6 @@ fccpu30senr
fccpu30senr501
fccpu33
-//@source:fccpu40.cpp
-//fccpu40 //
-
-@source:fcscsi.cpp
-fcscsi1 //
-
-@source:fcisio.cpp
-fcisio1 //
-
@source:fcombat.cpp
fcombat // (c) 1985 Jaleco
diff --git a/src/mame/mess.flt b/src/mame/mess.flt
index d839ed106ff..f939b7aa86b 100644
--- a/src/mame/mess.flt
+++ b/src/mame/mess.flt
@@ -189,8 +189,6 @@ fb01.cpp
fc100.cpp
fccpu20.cpp
fccpu30.cpp
-fcisio.cpp
-fcscsi.cpp
fidel6502.cpp
fidel68k.cpp
fidelz80.cpp