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author Wilbert Pol <wilbert@jdg.info>2014-03-03 21:52:39 +0000
committer Wilbert Pol <wilbert@jdg.info>2014-03-03 21:52:39 +0000
commit1df0e37933389015408a65a29ab3f63526de2f21 (patch)
tree76e695decbc7e3b6c309bc82ddf5c503095a699c /src
parent41b721e88b5cd9a0e18e91c573b7298d840c70fe (diff)
i386.c: Modernised cpu core. [Wilbert Pol]
Diffstat (limited to 'src')
-rw-r--r--src/emu/cpu/i386/i386.c3724
-rw-r--r--src/emu/cpu/i386/i386.h1354
-rw-r--r--src/emu/cpu/i386/i386op16.c2908
-rw-r--r--src/emu/cpu/i386/i386op32.c2798
-rw-r--r--src/emu/cpu/i386/i386ops.c2078
-rw-r--r--src/emu/cpu/i386/i386ops.h1016
-rw-r--r--src/emu/cpu/i386/i386priv.h841
-rw-r--r--src/emu/cpu/i386/i486ops.c370
-rw-r--r--src/emu/cpu/i386/pentops.c2370
-rw-r--r--src/emu/cpu/i386/x87ops.c2570
10 files changed, 10394 insertions, 9635 deletions
diff --git a/src/emu/cpu/i386/i386.c b/src/emu/cpu/i386/i386.c
index 7c6f4280b2f..e40df6b5e28 100644
--- a/src/emu/cpu/i386/i386.c
+++ b/src/emu/cpu/i386/i386.c
@@ -25,20 +25,99 @@
/* seems to be defined on mingw-gcc */
#undef i386
+const device_type I386 = &device_creator<i386_device>;
+const device_type I386SX = &device_creator<i386SX_device>;
+const device_type I486 = &device_creator<i486_device>;
+const device_type PENTIUM = &device_creator<pentium_device>;
+const device_type MEDIAGX = &device_creator<mediagx_device>;
+const device_type PENTIUM_PRO = &device_creator<pentium_pro_device>;
+const device_type PENTIUM_MMX = &device_creator<pentium_mmx_device>;
+const device_type PENTIUM2 = &device_creator<pentium2_device>;
+const device_type PENTIUM3 = &device_creator<pentium3_device>;
+const device_type PENTIUM4 = &device_creator<pentium4_device>;
+
+
+i386_device::i386_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : cpu_device(mconfig, I386, "I386", tag, owner, clock, "i386", __FILE__)
+ , m_program_config("program", ENDIANNESS_LITTLE, 32, 32, 0)
+ , m_io_config("io", ENDIANNESS_LITTLE, 32, 16, 0)
+ , m_smiact(*this)
+{
+ m_program_config.m_logaddr_width = 32;
+ m_program_config.m_page_shift = 12;
+}
+
+
+i386_device::i386_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int program_data_width, int program_addr_width, int io_data_width)
+ : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
+ , m_program_config("program", ENDIANNESS_LITTLE, program_data_width, program_addr_width, 0)
+ , m_io_config("io", ENDIANNESS_LITTLE, io_data_width, 16, 0)
+ , m_smiact(*this)
+{
+ m_program_config.m_logaddr_width = 32;
+ m_program_config.m_page_shift = 12;
+}
+
+i386SX_device::i386SX_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : i386_device(mconfig, I386SX, "I386SX", tag, owner, clock, "i386sx", __FILE__, 16, 24, 16)
+{
+}
+
+i486_device::i486_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : i386_device(mconfig, I486, "I486", tag, owner, clock, "i486", __FILE__)
+{
+}
+
+pentium_device::pentium_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : i386_device(mconfig, PENTIUM, "PENTIUM", tag, owner, clock, "pentium", __FILE__)
+{
+}
+
+pentium_device::pentium_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
+ : i386_device(mconfig, type, name, tag, owner, clock, shortname, source)
+{
+}
+
+mediagx_device::mediagx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : i386_device(mconfig, MEDIAGX, "MEDIAGX", tag, owner, clock, "mediagx", __FILE__)
+{
+}
+
+pentium_pro_device::pentium_pro_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : pentium_device(mconfig, PENTIUM_PRO, "Pentium Pro", tag, owner, clock, "pentium_pro", __FILE__)
+{
+}
+
+pentium_mmx_device::pentium_mmx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : pentium_device(mconfig, PENTIUM_MMX, "Pentium MMX", tag, owner, clock, "pentium_mmx", __FILE__)
+{
+}
+
+pentium2_device::pentium2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : pentium_device(mconfig, PENTIUM2, "Pentium II", tag, owner, clock, "pentium2", __FILE__)
+{
+}
+
+pentium3_device::pentium3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : pentium_device(mconfig, PENTIUM3, "Pentium III", tag, owner, clock, "pentium3", __FILE__)
+{
+}
+
+pentium4_device::pentium4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : pentium_device(mconfig, PENTIUM4, "Pentium 4", tag, owner, clock, "pentium4", __FILE__)
+{
+}
+
+
int i386_parity_table[256];
MODRM_TABLE i386_MODRM_table[256];
-static void i386_trap_with_error(i386_state* cpustate, int irq, int irq_gate, int trap_level, UINT32 err);
-static void i286_task_switch(i386_state* cpustate, UINT16 selector, UINT8 nested);
-static void i386_task_switch(i386_state* cpustate, UINT16 selector, UINT8 nested);
-static void pentium_smi(i386_state* cpustate);
-
-#define FAULT(fault,error) {cpustate->ext = 1; i386_trap_with_error(cpustate,fault,0,0,error); return;}
-#define FAULT_EXP(fault,error) {cpustate->ext = 1; i386_trap_with_error(cpustate,fault,0,trap_level+1,error); return;}
+#define FAULT(fault,error) {m_ext = 1; i386_trap_with_error(fault,0,0,error); return;}
+#define FAULT_EXP(fault,error) {m_ext = 1; i386_trap_with_error(fault,0,trap_level+1,error); return;}
/*************************************************************************/
-static UINT32 i386_load_protected_mode_segment(i386_state *cpustate, I386_SREG *seg, UINT64 *desc )
+UINT32 i386_device::i386_load_protected_mode_segment(I386_SREG *seg, UINT64 *desc )
{
UINT32 v1,v2;
UINT32 base, limit;
@@ -46,19 +125,19 @@ static UINT32 i386_load_protected_mode_segment(i386_state *cpustate, I386_SREG *
if ( seg->selector & 0x4 )
{
- base = cpustate->ldtr.base;
- limit = cpustate->ldtr.limit;
+ base = m_ldtr.base;
+ limit = m_ldtr.limit;
} else {
- base = cpustate->gdtr.base;
- limit = cpustate->gdtr.limit;
+ base = m_gdtr.base;
+ limit = m_gdtr.limit;
}
entry = seg->selector & ~0x7;
if (limit == 0 || entry + 7 > limit)
return 0;
- v1 = READ32PL0(cpustate, base + entry );
- v2 = READ32PL0(cpustate, base + entry + 4 );
+ v1 = READ32PL0(base + entry );
+ v2 = READ32PL0(base + entry + 4 );
seg->flags = (v2 >> 8) & 0xf0ff;
seg->base = (v2 & 0xff000000) | ((v2 & 0xff) << 16) | ((v1 >> 16) & 0xffff);
@@ -73,7 +152,7 @@ static UINT32 i386_load_protected_mode_segment(i386_state *cpustate, I386_SREG *
return 1;
}
-static void i386_load_call_gate(i386_state* cpustate, I386_CALL_GATE *gate)
+void i386_device::i386_load_call_gate(I386_CALL_GATE *gate)
{
UINT32 v1,v2;
UINT32 base,limit;
@@ -81,19 +160,19 @@ static void i386_load_call_gate(i386_state* cpustate, I386_CALL_GATE *gate)
if ( gate->segment & 0x4 )
{
- base = cpustate->ldtr.base;
- limit = cpustate->ldtr.limit;
+ base = m_ldtr.base;
+ limit = m_ldtr.limit;
} else {
- base = cpustate->gdtr.base;
- limit = cpustate->gdtr.limit;
+ base = m_gdtr.base;
+ limit = m_gdtr.limit;
}
entry = gate->segment & ~0x7;
if (limit == 0 || entry + 7 > limit)
return;
- v1 = READ32PL0(cpustate, base + entry );
- v2 = READ32PL0(cpustate, base + entry + 4 );
+ v1 = READ32PL0(base + entry );
+ v2 = READ32PL0(base + entry + 4 );
/* Note that for task gates, offset and dword_count are not used */
gate->selector = (v1 >> 16) & 0xffff;
@@ -104,7 +183,7 @@ static void i386_load_call_gate(i386_state* cpustate, I386_CALL_GATE *gate)
gate->dpl = (gate->ar >> 5) & 0x03;
}
-static void i386_set_descriptor_accessed(i386_state *cpustate, UINT16 selector)
+void i386_device::i386_set_descriptor_accessed(UINT16 selector)
{
// assume the selector is valid, we don't need to check it again
UINT32 base, addr;
@@ -113,129 +192,129 @@ static void i386_set_descriptor_accessed(i386_state *cpustate, UINT16 selector)
return;
if ( selector & 0x4 )
- base = cpustate->ldtr.base;
+ base = m_ldtr.base;
else
- base = cpustate->gdtr.base;
+ base = m_gdtr.base;
addr = base + (selector & ~7) + 5;
- i386_translate_address(cpustate, TRANSLATE_READ, &addr, NULL);
- rights = cpustate->program->read_byte(addr);
+ i386_translate_address(TRANSLATE_READ, &addr, NULL);
+ rights = m_program->read_byte(addr);
// Should a fault be thrown if the table is read only?
- cpustate->program->write_byte(addr, rights | 1);
+ m_program->write_byte(addr, rights | 1);
}
-static void i386_load_segment_descriptor(i386_state *cpustate, int segment )
+void i386_device::i386_load_segment_descriptor(int segment )
{
if (PROTECTED_MODE)
{
if (!V8086_MODE)
{
- i386_load_protected_mode_segment(cpustate, &cpustate->sreg[segment], NULL );
- i386_set_descriptor_accessed(cpustate, cpustate->sreg[segment].selector);
+ i386_load_protected_mode_segment(&m_sreg[segment], NULL );
+ i386_set_descriptor_accessed(m_sreg[segment].selector);
}
else
{
- cpustate->sreg[segment].base = cpustate->sreg[segment].selector << 4;
- cpustate->sreg[segment].limit = 0xffff;
- cpustate->sreg[segment].flags = (segment == CS) ? 0x00fb : 0x00f3;
- cpustate->sreg[segment].d = 0;
- cpustate->sreg[segment].valid = true;
+ m_sreg[segment].base = m_sreg[segment].selector << 4;
+ m_sreg[segment].limit = 0xffff;
+ m_sreg[segment].flags = (segment == CS) ? 0x00fb : 0x00f3;
+ m_sreg[segment].d = 0;
+ m_sreg[segment].valid = true;
}
}
else
{
- cpustate->sreg[segment].base = cpustate->sreg[segment].selector << 4;
- cpustate->sreg[segment].d = 0;
- cpustate->sreg[segment].valid = true;
+ m_sreg[segment].base = m_sreg[segment].selector << 4;
+ m_sreg[segment].d = 0;
+ m_sreg[segment].valid = true;
- if( segment == CS && !cpustate->performed_intersegment_jump )
- cpustate->sreg[segment].base |= 0xfff00000;
+ if( segment == CS && !m_performed_intersegment_jump )
+ m_sreg[segment].base |= 0xfff00000;
}
}
/* Retrieves the stack selector located in the current TSS */
-static UINT32 i386_get_stack_segment(i386_state* cpustate, UINT8 privilege)
+UINT32 i386_device::i386_get_stack_segment(UINT8 privilege)
{
UINT32 ret;
if(privilege >= 3)
return 0;
- if(cpustate->task.flags & 8)
- ret = READ32PL0(cpustate,(cpustate->task.base+8) + (8*privilege));
+ if(m_task.flags & 8)
+ ret = READ32PL0((m_task.base+8) + (8*privilege));
else
- ret = READ16PL0(cpustate,(cpustate->task.base+4) + (4*privilege));
+ ret = READ16PL0((m_task.base+4) + (4*privilege));
return ret;
}
/* Retrieves the stack pointer located in the current TSS */
-static UINT32 i386_get_stack_ptr(i386_state* cpustate, UINT8 privilege)
+UINT32 i386_device::i386_get_stack_ptr(UINT8 privilege)
{
UINT32 ret;
if(privilege >= 3)
return 0;
- if(cpustate->task.flags & 8)
- ret = READ32PL0(cpustate,(cpustate->task.base+4) + (8*privilege));
+ if(m_task.flags & 8)
+ ret = READ32PL0((m_task.base+4) + (8*privilege));
else
- ret = READ16PL0(cpustate,(cpustate->task.base+2) + (4*privilege));
+ ret = READ16PL0((m_task.base+2) + (4*privilege));
return ret;
}
-static UINT32 get_flags(i386_state *cpustate)
+UINT32 i386_device::get_flags()
{
UINT32 f = 0x2;
- f |= cpustate->CF;
- f |= cpustate->PF << 2;
- f |= cpustate->AF << 4;
- f |= cpustate->ZF << 6;
- f |= cpustate->SF << 7;
- f |= cpustate->TF << 8;
- f |= cpustate->IF << 9;
- f |= cpustate->DF << 10;
- f |= cpustate->OF << 11;
- f |= cpustate->IOP1 << 12;
- f |= cpustate->IOP2 << 13;
- f |= cpustate->NT << 14;
- f |= cpustate->RF << 16;
- f |= cpustate->VM << 17;
- f |= cpustate->AC << 18;
- f |= cpustate->VIF << 19;
- f |= cpustate->VIP << 20;
- f |= cpustate->ID << 21;
- return (cpustate->eflags & ~cpustate->eflags_mask) | (f & cpustate->eflags_mask);
+ f |= m_CF;
+ f |= m_PF << 2;
+ f |= m_AF << 4;
+ f |= m_ZF << 6;
+ f |= m_SF << 7;
+ f |= m_TF << 8;
+ f |= m_IF << 9;
+ f |= m_DF << 10;
+ f |= m_OF << 11;
+ f |= m_IOP1 << 12;
+ f |= m_IOP2 << 13;
+ f |= m_NT << 14;
+ f |= m_RF << 16;
+ f |= m_VM << 17;
+ f |= m_AC << 18;
+ f |= m_VIF << 19;
+ f |= m_VIP << 20;
+ f |= m_ID << 21;
+ return (m_eflags & ~m_eflags_mask) | (f & m_eflags_mask);
}
-static void set_flags(i386_state *cpustate, UINT32 f )
+void i386_device::set_flags(UINT32 f )
{
- cpustate->CF = (f & 0x1) ? 1 : 0;
- cpustate->PF = (f & 0x4) ? 1 : 0;
- cpustate->AF = (f & 0x10) ? 1 : 0;
- cpustate->ZF = (f & 0x40) ? 1 : 0;
- cpustate->SF = (f & 0x80) ? 1 : 0;
- cpustate->TF = (f & 0x100) ? 1 : 0;
- cpustate->IF = (f & 0x200) ? 1 : 0;
- cpustate->DF = (f & 0x400) ? 1 : 0;
- cpustate->OF = (f & 0x800) ? 1 : 0;
- cpustate->IOP1 = (f & 0x1000) ? 1 : 0;
- cpustate->IOP2 = (f & 0x2000) ? 1 : 0;
- cpustate->NT = (f & 0x4000) ? 1 : 0;
- cpustate->RF = (f & 0x10000) ? 1 : 0;
- cpustate->VM = (f & 0x20000) ? 1 : 0;
- cpustate->AC = (f & 0x40000) ? 1 : 0;
- cpustate->VIF = (f & 0x80000) ? 1 : 0;
- cpustate->VIP = (f & 0x100000) ? 1 : 0;
- cpustate->ID = (f & 0x200000) ? 1 : 0;
- cpustate->eflags = f & cpustate->eflags_mask;
+ m_CF = (f & 0x1) ? 1 : 0;
+ m_PF = (f & 0x4) ? 1 : 0;
+ m_AF = (f & 0x10) ? 1 : 0;
+ m_ZF = (f & 0x40) ? 1 : 0;
+ m_SF = (f & 0x80) ? 1 : 0;
+ m_TF = (f & 0x100) ? 1 : 0;
+ m_IF = (f & 0x200) ? 1 : 0;
+ m_DF = (f & 0x400) ? 1 : 0;
+ m_OF = (f & 0x800) ? 1 : 0;
+ m_IOP1 = (f & 0x1000) ? 1 : 0;
+ m_IOP2 = (f & 0x2000) ? 1 : 0;
+ m_NT = (f & 0x4000) ? 1 : 0;
+ m_RF = (f & 0x10000) ? 1 : 0;
+ m_VM = (f & 0x20000) ? 1 : 0;
+ m_AC = (f & 0x40000) ? 1 : 0;
+ m_VIF = (f & 0x80000) ? 1 : 0;
+ m_VIP = (f & 0x100000) ? 1 : 0;
+ m_ID = (f & 0x200000) ? 1 : 0;
+ m_eflags = f & m_eflags_mask;
}
-static void sib_byte(i386_state *cpustate,UINT8 mod, UINT32* out_ea, UINT8* out_segment)
+void i386_device::sib_byte(UINT8 mod, UINT32* out_ea, UINT8* out_segment)
{
UINT32 ea = 0;
UINT8 segment = 0;
UINT8 scale, i, base;
- UINT8 sib = FETCH(cpustate);
+ UINT8 sib = FETCH();
scale = (sib >> 6) & 0x3;
i = (sib >> 3) & 0x7;
base = sib & 0x7;
@@ -249,7 +328,7 @@ static void sib_byte(i386_state *cpustate,UINT8 mod, UINT32* out_ea, UINT8* out_
case 4: ea = REG32(ESP); segment = SS; break;
case 5:
if( mod == 0 ) {
- ea = FETCH32(cpustate);
+ ea = FETCH32();
segment = DS;
} else if( mod == 1 ) {
ea = REG32(EBP);
@@ -277,7 +356,7 @@ static void sib_byte(i386_state *cpustate,UINT8 mod, UINT32* out_ea, UINT8* out_
*out_segment = segment;
}
-static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment)
+void i386_device::modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment)
{
INT8 disp8;
INT16 disp16;
@@ -291,7 +370,7 @@ static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8
fatalerror("i386: Called modrm_to_EA with modrm value %02X!\n",mod_rm);
- if( cpustate->address_size ) {
+ if( m_address_size ) {
switch( rm )
{
default:
@@ -299,10 +378,10 @@ static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8
case 1: ea = REG32(ECX); segment = DS; break;
case 2: ea = REG32(EDX); segment = DS; break;
case 3: ea = REG32(EBX); segment = DS; break;
- case 4: sib_byte(cpustate, mod, &ea, &segment ); break;
+ case 4: sib_byte(mod, &ea, &segment ); break;
case 5:
if( mod == 0 ) {
- ea = FETCH32(cpustate); segment = DS;
+ ea = FETCH32(); segment = DS;
} else {
ea = REG32(EBP); segment = SS;
}
@@ -311,15 +390,15 @@ static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8
case 7: ea = REG32(EDI); segment = DS; break;
}
if( mod == 1 ) {
- disp8 = FETCH(cpustate);
+ disp8 = FETCH();
ea += (INT32)disp8;
} else if( mod == 2 ) {
- disp32 = FETCH32(cpustate);
+ disp32 = FETCH32();
ea += disp32;
}
- if( cpustate->segment_prefix )
- segment = cpustate->segment_override;
+ if( m_segment_prefix )
+ segment = m_segment_override;
*out_ea = ea;
*out_segment = segment;
@@ -336,7 +415,7 @@ static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8
case 5: ea = REG16(DI); segment = DS; break;
case 6:
if( mod == 0 ) {
- ea = FETCH16(cpustate); segment = DS;
+ ea = FETCH16(); segment = DS;
} else {
ea = REG16(BP); segment = SS;
}
@@ -344,62 +423,62 @@ static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8
case 7: ea = REG16(BX); segment = DS; break;
}
if( mod == 1 ) {
- disp8 = FETCH(cpustate);
+ disp8 = FETCH();
ea += (INT32)disp8;
} else if( mod == 2 ) {
- disp16 = FETCH16(cpustate);
+ disp16 = FETCH16();
ea += (INT32)disp16;
}
- if( cpustate->segment_prefix )
- segment = cpustate->segment_override;
+ if( m_segment_prefix )
+ segment = m_segment_override;
*out_ea = ea & 0xffff;
*out_segment = segment;
}
}
-static UINT32 GetNonTranslatedEA(i386_state *cpustate,UINT8 modrm,UINT8 *seg)
+UINT32 i386_device::GetNonTranslatedEA(UINT8 modrm,UINT8 *seg)
{
UINT8 segment;
UINT32 ea;
- modrm_to_EA(cpustate, modrm, &ea, &segment );
+ modrm_to_EA(modrm, &ea, &segment );
if(seg) *seg = segment;
return ea;
}
-static UINT32 GetEA(i386_state *cpustate,UINT8 modrm, int rwn)
+UINT32 i386_device::GetEA(UINT8 modrm, int rwn)
{
UINT8 segment;
UINT32 ea;
- modrm_to_EA(cpustate, modrm, &ea, &segment );
- return i386_translate(cpustate, segment, ea, rwn );
+ modrm_to_EA(modrm, &ea, &segment );
+ return i386_translate(segment, ea, rwn );
}
/* Check segment register for validity when changing privilege level after an RETF */
-static void i386_check_sreg_validity(i386_state* cpustate, int reg)
+void i386_device::i386_check_sreg_validity(int reg)
{
- UINT16 selector = cpustate->sreg[reg].selector;
- UINT8 CPL = cpustate->CPL;
+ UINT16 selector = m_sreg[reg].selector;
+ UINT8 CPL = m_CPL;
UINT8 DPL,RPL;
I386_SREG desc;
int invalid = 0;
memset(&desc, 0, sizeof(desc));
desc.selector = selector;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
RPL = selector & 0x03;
/* Must be within the relevant descriptor table limits */
if(selector & 0x04)
{
- if((selector & ~0x07) > cpustate->ldtr.limit)
+ if((selector & ~0x07) > m_ldtr.limit)
invalid = 1;
}
else
{
- if((selector & ~0x07) > cpustate->gdtr.limit)
+ if((selector & ~0x07) > m_gdtr.limit)
invalid = 1;
}
@@ -419,29 +498,29 @@ static void i386_check_sreg_validity(i386_state* cpustate, int reg)
/* if segment is invalid, then segment register is nulled */
if(invalid != 0)
{
- cpustate->sreg[reg].selector = 0;
- i386_load_segment_descriptor(cpustate,reg);
+ m_sreg[reg].selector = 0;
+ i386_load_segment_descriptor(reg);
}
}
-static int i386_limit_check(i386_state *cpustate, int seg, UINT32 offset)
+int i386_device::i386_limit_check(int seg, UINT32 offset)
{
if(PROTECTED_MODE && !V8086_MODE)
{
- if((cpustate->sreg[seg].flags & 0x0018) == 0x0010 && cpustate->sreg[seg].flags & 0x0004) // if expand-down data segment
+ if((m_sreg[seg].flags & 0x0018) == 0x0010 && m_sreg[seg].flags & 0x0004) // if expand-down data segment
{
// compare if greater then 0xffffffff when we're passed the access size
- if((offset <= cpustate->sreg[seg].limit) || ((cpustate->sreg[seg].d)?0:(offset > 0xffff)))
+ if((offset <= m_sreg[seg].limit) || ((m_sreg[seg].d)?0:(offset > 0xffff)))
{
- logerror("Limit check at 0x%08x failed. Segment %04x, limit %08x, offset %08x (expand-down)\n",cpustate->pc,cpustate->sreg[seg].selector,cpustate->sreg[seg].limit,offset);
+ logerror("Limit check at 0x%08x failed. Segment %04x, limit %08x, offset %08x (expand-down)\n",m_pc,m_sreg[seg].selector,m_sreg[seg].limit,offset);
return 1;
}
}
else
{
- if(offset > cpustate->sreg[seg].limit)
+ if(offset > m_sreg[seg].limit)
{
- logerror("Limit check at 0x%08x failed. Segment %04x, limit %08x, offset %08x\n",cpustate->pc,cpustate->sreg[seg].selector,cpustate->sreg[seg].limit,offset);
+ logerror("Limit check at 0x%08x failed. Segment %04x, limit %08x, offset %08x\n",m_pc,m_sreg[seg].selector,m_sreg[seg].limit,offset);
return 1;
}
}
@@ -449,18 +528,18 @@ static int i386_limit_check(i386_state *cpustate, int seg, UINT32 offset)
return 0;
}
-static void i386_sreg_load(i386_state *cpustate, UINT16 selector, UINT8 reg, bool *fault)
+void i386_device::i386_sreg_load(UINT16 selector, UINT8 reg, bool *fault)
{
// Checks done when MOV changes a segment register in protected mode
UINT8 CPL,RPL,DPL;
- CPL = cpustate->CPL;
+ CPL = m_CPL;
RPL = selector & 0x0003;
if(!PROTECTED_MODE || V8086_MODE)
{
- cpustate->sreg[reg].selector = selector;
- i386_load_segment_descriptor(cpustate, reg);
+ m_sreg[reg].selector = selector;
+ i386_load_segment_descriptor(reg);
if(fault) *fault = false;
return;
}
@@ -472,48 +551,48 @@ static void i386_sreg_load(i386_state *cpustate, UINT16 selector, UINT8 reg, boo
memset(&stack, 0, sizeof(stack));
stack.selector = selector;
- i386_load_protected_mode_segment(cpustate,&stack,NULL);
+ i386_load_protected_mode_segment(&stack,NULL);
DPL = (stack.flags >> 5) & 0x03;
if((selector & ~0x0003) == 0)
{
- logerror("SReg Load (%08x): Selector is null.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Selector is null.\n",m_pc);
FAULT(FAULT_GP,0)
}
if(selector & 0x0004) // LDT
{
- if((selector & ~0x0007) > cpustate->ldtr.limit)
+ if((selector & ~0x0007) > m_ldtr.limit)
{
- logerror("SReg Load (%08x): Selector is out of LDT bounds.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Selector is out of LDT bounds.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
}
else // GDT
{
- if((selector & ~0x0007) > cpustate->gdtr.limit)
+ if((selector & ~0x0007) > m_gdtr.limit)
{
- logerror("SReg Load (%08x): Selector is out of GDT bounds.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Selector is out of GDT bounds.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
}
if (RPL != CPL)
{
- logerror("SReg Load (%08x): Selector RPL does not equal CPL.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Selector RPL does not equal CPL.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
if(((stack.flags & 0x0018) != 0x10) && (stack.flags & 0x0002) != 0)
{
- logerror("SReg Load (%08x): Segment is not a writable data segment.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Segment is not a writable data segment.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
if(DPL != CPL)
{
- logerror("SReg Load (%08x): Segment DPL does not equal CPL.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Segment DPL does not equal CPL.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
if(!(stack.flags & 0x0080))
{
- logerror("SReg Load (%08x): Segment is not present.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Segment is not present.\n",m_pc);
FAULT(FAULT_SS,selector & ~0x03)
}
}
@@ -523,30 +602,30 @@ static void i386_sreg_load(i386_state *cpustate, UINT16 selector, UINT8 reg, boo
if((selector & ~0x0003) == 0)
{
- cpustate->sreg[reg].selector = selector;
- i386_load_segment_descriptor(cpustate, reg );
+ m_sreg[reg].selector = selector;
+ i386_load_segment_descriptor(reg );
if(fault) *fault = false;
return;
}
memset(&desc, 0, sizeof(desc));
desc.selector = selector;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
DPL = (desc.flags >> 5) & 0x03;
if(selector & 0x0004) // LDT
{
- if((selector & ~0x0007) > cpustate->ldtr.limit)
+ if((selector & ~0x0007) > m_ldtr.limit)
{
- logerror("SReg Load (%08x): Selector is out of LDT bounds.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Selector is out of LDT bounds.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
}
else // GDT
{
- if((selector & ~0x0007) > cpustate->gdtr.limit)
+ if((selector & ~0x0007) > m_gdtr.limit)
{
- logerror("SReg Load (%08x): Selector is out of GDT bounds.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Selector is out of GDT bounds.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
}
@@ -554,7 +633,7 @@ static void i386_sreg_load(i386_state *cpustate, UINT16 selector, UINT8 reg, boo
{
if((((desc.flags & 0x0002) != 0) && ((desc.flags & 0x0018) != 0x18)) || !(desc.flags & 0x10))
{
- logerror("SReg Load (%08x): Segment is not a data segment or readable code segment.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Segment is not a data segment or readable code segment.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
}
@@ -563,23 +642,23 @@ static void i386_sreg_load(i386_state *cpustate, UINT16 selector, UINT8 reg, boo
// if data or non-conforming code segment
if((RPL > DPL) || (CPL > DPL))
{
- logerror("SReg Load (%08x): Selector RPL or CPL is not less or equal to segment DPL.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Selector RPL or CPL is not less or equal to segment DPL.\n",m_pc);
FAULT(FAULT_GP,selector & ~0x03)
}
}
if(!(desc.flags & 0x0080))
{
- logerror("SReg Load (%08x): Segment is not present.\n",cpustate->pc);
+ logerror("SReg Load (%08x): Segment is not present.\n",m_pc);
FAULT(FAULT_NP,selector & ~0x03)
}
}
- cpustate->sreg[reg].selector = selector;
- i386_load_segment_descriptor(cpustate, reg );
+ m_sreg[reg].selector = selector;
+ i386_load_segment_descriptor(reg );
if(fault) *fault = false;
}
-static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level)
+void i386_device::i386_trap(int irq, int irq_gate, int trap_level)
{
/* I386 Interrupts/Traps/Faults:
*
@@ -602,7 +681,7 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
* 0x10 Coprocessor error
*/
UINT32 v1, v2;
- UINT32 offset, oldflags = get_flags(cpustate);
+ UINT32 offset, oldflags = get_flags();
UINT16 segment;
int entry = irq * (PROTECTED_MODE ? 8 : 4);
int SetRPL = 0;
@@ -610,29 +689,29 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
if( !(PROTECTED_MODE) )
{
/* 16-bit */
- PUSH16(cpustate, oldflags & 0xffff );
- PUSH16(cpustate, cpustate->sreg[CS].selector );
+ PUSH16(oldflags & 0xffff );
+ PUSH16(m_sreg[CS].selector );
if(irq == 3 || irq == 4 || irq == 9 || irq_gate == 1)
- PUSH16(cpustate, cpustate->eip );
+ PUSH16(m_eip );
else
- PUSH16(cpustate, cpustate->prev_eip );
+ PUSH16(m_prev_eip );
- cpustate->sreg[CS].selector = READ16(cpustate, cpustate->idtr.base + entry + 2 );
- cpustate->eip = READ16(cpustate, cpustate->idtr.base + entry );
+ m_sreg[CS].selector = READ16(m_idtr.base + entry + 2 );
+ m_eip = READ16(m_idtr.base + entry );
- cpustate->TF = 0;
- cpustate->IF = 0;
+ m_TF = 0;
+ m_IF = 0;
}
else
{
int type;
UINT16 flags;
I386_SREG desc;
- UINT8 CPL = cpustate->CPL, DPL = 0; //, RPL = 0;
+ UINT8 CPL = m_CPL, DPL = 0; //, RPL = 0;
/* 32-bit */
- v1 = READ32PL0(cpustate, cpustate->idtr.base + entry );
- v2 = READ32PL0(cpustate, cpustate->idtr.base + entry + 4 );
+ v1 = READ32PL0(m_idtr.base + entry );
+ v2 = READ32PL0(m_idtr.base + entry + 4 );
offset = (v2 & 0xffff0000) | (v1 & 0xffff);
segment = (v1 >> 16) & 0xffff;
type = (v2>>8) & 0x1F;
@@ -646,28 +725,28 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
if(trap_level >= 3)
{
logerror("IRQ: Triple fault. CPU reset.\n");
- cpustate->device->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
+ set_input_line(INPUT_LINE_RESET, PULSE_LINE);
return;
}
/* segment privilege checks */
- if(entry >= cpustate->idtr.limit)
+ if(entry >= m_idtr.limit)
{
- logerror("IRQ (%08x): Vector %02xh is past IDT limit.\n",cpustate->pc,entry);
+ logerror("IRQ (%08x): Vector %02xh is past IDT limit.\n",m_pc,entry);
FAULT_EXP(FAULT_GP,entry+2)
}
/* segment must be interrupt gate, trap gate, or task gate */
if(type != 0x05 && type != 0x06 && type != 0x07 && type != 0x0e && type != 0x0f)
{
- logerror("IRQ#%02x (%08x): Vector segment %04x is not an interrupt, trap or task gate.\n",irq,cpustate->pc,segment);
+ logerror("IRQ#%02x (%08x): Vector segment %04x is not an interrupt, trap or task gate.\n",irq,m_pc,segment);
FAULT_EXP(FAULT_GP,entry+2)
}
- if(cpustate->ext == 0) // if software interrupt (caused by INT/INTO/INT3)
+ if(m_ext == 0) // if software interrupt (caused by INT/INTO/INT3)
{
if(((flags >> 5) & 0x03) < CPL)
{
- logerror("IRQ (%08x): Software IRQ - gate DPL is less than CPL.\n",cpustate->pc);
+ logerror("IRQ (%08x): Software IRQ - gate DPL is less than CPL.\n",m_pc);
FAULT_EXP(FAULT_GP,entry+2)
}
}
@@ -683,7 +762,7 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
/* Task gate */
memset(&desc, 0, sizeof(desc));
desc.selector = segment;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
if(segment & 0x04)
{
logerror("IRQ: Task gate: TSS is not in the GDT.\n");
@@ -691,7 +770,7 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
}
else
{
- if(segment > cpustate->gdtr.limit)
+ if(segment > m_gdtr.limit)
{
logerror("IRQ: Task gate: TSS is past GDT limit.\n");
FAULT_EXP(FAULT_TS,segment & ~0x03);
@@ -708,11 +787,11 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
FAULT_EXP(FAULT_NP,segment & ~0x03);
}
if(!(irq == 3 || irq == 4 || irq == 9 || irq_gate == 1))
- cpustate->eip = cpustate->prev_eip;
+ m_eip = m_prev_eip;
if(desc.flags & 0x08)
- i386_task_switch(cpustate,desc.selector,1);
+ i386_task_switch(desc.selector,1);
else
- i286_task_switch(cpustate,desc.selector,1);
+ i286_task_switch(desc.selector,1);
return;
}
else
@@ -720,41 +799,41 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
/* Interrupt or Trap gate */
memset(&desc, 0, sizeof(desc));
desc.selector = segment;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
- CPL = cpustate->CPL; // current privilege level
+ i386_load_protected_mode_segment(&desc,NULL);
+ CPL = m_CPL; // current privilege level
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
// RPL = segment & 0x03; // requested privilege level
if((segment & ~0x03) == 0)
{
logerror("IRQ: Gate segment is null.\n");
- FAULT_EXP(FAULT_GP,cpustate->ext)
+ FAULT_EXP(FAULT_GP,m_ext)
}
if(segment & 0x04)
{
- if((segment & ~0x07) > cpustate->ldtr.limit)
+ if((segment & ~0x07) > m_ldtr.limit)
{
logerror("IRQ: Gate segment is past LDT limit.\n");
- FAULT_EXP(FAULT_GP,(segment & 0x03)+cpustate->ext)
+ FAULT_EXP(FAULT_GP,(segment & 0x03)+m_ext)
}
}
else
{
- if((segment & ~0x07) > cpustate->gdtr.limit)
+ if((segment & ~0x07) > m_gdtr.limit)
{
logerror("IRQ: Gate segment is past GDT limit.\n");
- FAULT_EXP(FAULT_GP,(segment & 0x03)+cpustate->ext)
+ FAULT_EXP(FAULT_GP,(segment & 0x03)+m_ext)
}
}
if((desc.flags & 0x0018) != 0x18)
{
logerror("IRQ: Gate descriptor is not a code segment.\n");
- FAULT_EXP(FAULT_GP,(segment & 0x03)+cpustate->ext)
+ FAULT_EXP(FAULT_GP,(segment & 0x03)+m_ext)
}
if((desc.flags & 0x0080) == 0)
{
logerror("IRQ: Gate segment is not present.\n");
- FAULT_EXP(FAULT_NP,(segment & 0x03)+cpustate->ext)
+ FAULT_EXP(FAULT_NP,(segment & 0x03)+m_ext)
}
if((desc.flags & 0x0004) == 0 && (DPL < CPL))
{
@@ -769,9 +848,9 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
}
/* Check new stack segment in TSS */
memset(&stack, 0, sizeof(stack));
- stack.selector = i386_get_stack_segment(cpustate,DPL);
- i386_load_protected_mode_segment(cpustate,&stack,NULL);
- oldSS = cpustate->sreg[SS].selector;
+ stack.selector = i386_get_stack_segment(DPL);
+ i386_load_protected_mode_segment(&stack,NULL);
+ oldSS = m_sreg[SS].selector;
if(flags & 0x0008)
oldESP = REG32(ESP);
else
@@ -779,45 +858,45 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
if((stack.selector & ~0x03) == 0)
{
logerror("IRQ: New stack selector is null.\n");
- FAULT_EXP(FAULT_GP,cpustate->ext)
+ FAULT_EXP(FAULT_GP,m_ext)
}
if(stack.selector & 0x04)
{
- if((stack.selector & ~0x07) > cpustate->ldtr.base)
+ if((stack.selector & ~0x07) > m_ldtr.base)
{
logerror("IRQ: New stack selector is past LDT limit.\n");
- FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+cpustate->ext)
+ FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+m_ext)
}
}
else
{
- if((stack.selector & ~0x07) > cpustate->gdtr.base)
+ if((stack.selector & ~0x07) > m_gdtr.base)
{
logerror("IRQ: New stack selector is past GDT limit.\n");
- FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+cpustate->ext)
+ FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+m_ext)
}
}
if((stack.selector & 0x03) != DPL)
{
logerror("IRQ: New stack selector RPL is not equal to code segment DPL.\n");
- FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+cpustate->ext)
+ FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+m_ext)
}
if(((stack.flags >> 5) & 0x03) != DPL)
{
logerror("IRQ: New stack segment DPL is not equal to code segment DPL.\n");
- FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+cpustate->ext)
+ FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+m_ext)
}
if(((stack.flags & 0x0018) != 0x10) && (stack.flags & 0x0002) != 0)
{
logerror("IRQ: New stack segment is not a writable data segment.\n");
- FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+cpustate->ext) // #TS(stack selector + EXT)
+ FAULT_EXP(FAULT_TS,(stack.selector & ~0x03)+m_ext) // #TS(stack selector + EXT)
}
if((stack.flags & 0x0080) == 0)
{
logerror("IRQ: New stack segment is not present.\n");
- FAULT_EXP(FAULT_SS,(stack.selector & ~0x03)+cpustate->ext) // #TS(stack selector + EXT)
+ FAULT_EXP(FAULT_SS,(stack.selector & ~0x03)+m_ext) // #TS(stack selector + EXT)
}
- newESP = i386_get_stack_ptr(cpustate,DPL);
+ newESP = i386_get_stack_ptr(DPL);
if(type & 0x08) // 32-bit gate
{
if(newESP < (V8086_MODE?36:20))
@@ -841,52 +920,52 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
FAULT_EXP(FAULT_GP,0)
}
/* change CPL before accessing the stack */
- cpustate->CPL = DPL;
+ m_CPL = DPL;
/* check for page fault at new stack TODO: check if stack frame crosses page boundary */
- WRITE_TEST(cpustate, stack.base+newESP-1);
+ WRITE_TEST(stack.base+newESP-1);
/* Load new stack segment descriptor */
- cpustate->sreg[SS].selector = stack.selector;
- i386_load_protected_mode_segment(cpustate,&cpustate->sreg[SS],NULL);
- i386_set_descriptor_accessed(cpustate, stack.selector);
+ m_sreg[SS].selector = stack.selector;
+ i386_load_protected_mode_segment(&m_sreg[SS],NULL);
+ i386_set_descriptor_accessed(stack.selector);
REG32(ESP) = newESP;
if(V8086_MODE)
{
- //logerror("IRQ (%08x): Interrupt during V8086 task\n",cpustate->pc);
+ //logerror("IRQ (%08x): Interrupt during V8086 task\n",m_pc);
if(type & 0x08)
{
- PUSH32(cpustate,cpustate->sreg[GS].selector & 0xffff);
- PUSH32(cpustate,cpustate->sreg[FS].selector & 0xffff);
- PUSH32(cpustate,cpustate->sreg[DS].selector & 0xffff);
- PUSH32(cpustate,cpustate->sreg[ES].selector & 0xffff);
+ PUSH32(m_sreg[GS].selector & 0xffff);
+ PUSH32(m_sreg[FS].selector & 0xffff);
+ PUSH32(m_sreg[DS].selector & 0xffff);
+ PUSH32(m_sreg[ES].selector & 0xffff);
}
else
{
- PUSH16(cpustate,cpustate->sreg[GS].selector);
- PUSH16(cpustate,cpustate->sreg[FS].selector);
- PUSH16(cpustate,cpustate->sreg[DS].selector);
- PUSH16(cpustate,cpustate->sreg[ES].selector);
+ PUSH16(m_sreg[GS].selector);
+ PUSH16(m_sreg[FS].selector);
+ PUSH16(m_sreg[DS].selector);
+ PUSH16(m_sreg[ES].selector);
}
- cpustate->sreg[GS].selector = 0;
- cpustate->sreg[FS].selector = 0;
- cpustate->sreg[DS].selector = 0;
- cpustate->sreg[ES].selector = 0;
- cpustate->VM = 0;
- i386_load_segment_descriptor(cpustate,GS);
- i386_load_segment_descriptor(cpustate,FS);
- i386_load_segment_descriptor(cpustate,DS);
- i386_load_segment_descriptor(cpustate,ES);
+ m_sreg[GS].selector = 0;
+ m_sreg[FS].selector = 0;
+ m_sreg[DS].selector = 0;
+ m_sreg[ES].selector = 0;
+ m_VM = 0;
+ i386_load_segment_descriptor(GS);
+ i386_load_segment_descriptor(FS);
+ i386_load_segment_descriptor(DS);
+ i386_load_segment_descriptor(ES);
}
if(type & 0x08)
{
// 32-bit gate
- PUSH32(cpustate,oldSS);
- PUSH32(cpustate,oldESP);
+ PUSH32(oldSS);
+ PUSH32(oldESP);
}
else
{
// 16-bit gate
- PUSH16(cpustate,oldSS);
- PUSH16(cpustate,oldESP);
+ PUSH16(oldSS);
+ PUSH16(oldESP);
}
SetRPL = 1;
}
@@ -931,21 +1010,21 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
// this is ugly but the alternative is worse
if(type != 0x0e && type != 0x0f) // if not 386 interrupt or trap gate
{
- PUSH16(cpustate, oldflags & 0xffff );
- PUSH16(cpustate, cpustate->sreg[CS].selector );
+ PUSH16(oldflags & 0xffff );
+ PUSH16(m_sreg[CS].selector );
if(irq == 3 || irq == 4 || irq == 9 || irq_gate == 1)
- PUSH16(cpustate, cpustate->eip );
+ PUSH16(m_eip );
else
- PUSH16(cpustate, cpustate->prev_eip );
+ PUSH16(m_prev_eip );
}
else
{
- PUSH32(cpustate, oldflags & 0x00ffffff );
- PUSH32(cpustate, cpustate->sreg[CS].selector );
+ PUSH32(oldflags & 0x00ffffff );
+ PUSH32(m_sreg[CS].selector );
if(irq == 3 || irq == 4 || irq == 9 || irq_gate == 1)
- PUSH32(cpustate, cpustate->eip );
+ PUSH32(m_eip );
else
- PUSH32(cpustate, cpustate->prev_eip );
+ PUSH32(m_prev_eip );
}
}
catch(UINT64 e)
@@ -954,24 +1033,24 @@ static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level
throw e;
}
if(SetRPL != 0)
- segment = (segment & ~0x03) | cpustate->CPL;
- cpustate->sreg[CS].selector = segment;
- cpustate->eip = offset;
+ segment = (segment & ~0x03) | m_CPL;
+ m_sreg[CS].selector = segment;
+ m_eip = offset;
if(type == 0x0e || type == 0x06)
- cpustate->IF = 0;
- cpustate->TF = 0;
- cpustate->NT = 0;
+ m_IF = 0;
+ m_TF = 0;
+ m_NT = 0;
}
- i386_load_segment_descriptor(cpustate,CS);
- CHANGE_PC(cpustate,cpustate->eip);
+ i386_load_segment_descriptor(CS);
+ CHANGE_PC(m_eip);
}
-static void i386_trap_with_error(i386_state *cpustate,int irq, int irq_gate, int trap_level, UINT32 error)
+void i386_device::i386_trap_with_error(int irq, int irq_gate, int trap_level, UINT32 error)
{
- i386_trap(cpustate,irq,irq_gate,trap_level);
+ i386_trap(irq,irq_gate,trap_level);
if(irq == 8 || irq == 10 || irq == 11 || irq == 12 || irq == 13 || irq == 14)
{
// for these exceptions, an error code is pushed onto the stack by the processor.
@@ -980,26 +1059,26 @@ static void i386_trap_with_error(i386_state *cpustate,int irq, int irq_gate, int
{
UINT32 entry = irq * 8;
UINT32 v2,type;
- v2 = READ32PL0(cpustate, cpustate->idtr.base + entry + 4 );
+ v2 = READ32PL0(m_idtr.base + entry + 4 );
type = (v2>>8) & 0x1F;
if(type == 5)
{
- v2 = READ32PL0(cpustate, cpustate->idtr.base + entry);
- v2 = READ32PL0(cpustate, cpustate->gdtr.base + ((v2 >> 16) & 0xfff8) + 4);
+ v2 = READ32PL0(m_idtr.base + entry);
+ v2 = READ32PL0(m_gdtr.base + ((v2 >> 16) & 0xfff8) + 4);
type = (v2>>8) & 0x1F;
}
if(type >= 9)
- PUSH32(cpustate,error);
+ PUSH32(error);
else
- PUSH16(cpustate,error);
+ PUSH16(error);
}
else
- PUSH16(cpustate,error);
+ PUSH16(error);
}
}
-static void i286_task_switch(i386_state *cpustate, UINT16 selector, UINT8 nested)
+void i386_device::i286_task_switch(UINT16 selector, UINT8 nested)
{
UINT32 tss;
I386_SREG seg;
@@ -1011,236 +1090,236 @@ static void i286_task_switch(i386_state *cpustate, UINT16 selector, UINT8 nested
/* For tasks that aren't nested, clear the busy bit in the task's descriptor */
if(nested == 0)
{
- if(cpustate->task.segment & 0x0004)
+ if(m_task.segment & 0x0004)
{
- ar_byte = READ8(cpustate,cpustate->ldtr.base + (cpustate->task.segment & ~0x0007) + 5);
- WRITE8(cpustate,cpustate->ldtr.base + (cpustate->task.segment & ~0x0007) + 5,ar_byte & ~0x02);
+ ar_byte = READ8(m_ldtr.base + (m_task.segment & ~0x0007) + 5);
+ WRITE8(m_ldtr.base + (m_task.segment & ~0x0007) + 5,ar_byte & ~0x02);
}
else
{
- ar_byte = READ8(cpustate,cpustate->gdtr.base + (cpustate->task.segment & ~0x0007) + 5);
- WRITE8(cpustate,cpustate->gdtr.base + (cpustate->task.segment & ~0x0007) + 5,ar_byte & ~0x02);
+ ar_byte = READ8(m_gdtr.base + (m_task.segment & ~0x0007) + 5);
+ WRITE8(m_gdtr.base + (m_task.segment & ~0x0007) + 5,ar_byte & ~0x02);
}
}
/* Save the state of the current task in the current TSS (TR register base) */
- tss = cpustate->task.base;
- WRITE16(cpustate,tss+0x0e,cpustate->eip & 0x0000ffff);
- WRITE16(cpustate,tss+0x10,get_flags(cpustate) & 0x0000ffff);
- WRITE16(cpustate,tss+0x12,REG16(AX));
- WRITE16(cpustate,tss+0x14,REG16(CX));
- WRITE16(cpustate,tss+0x16,REG16(DX));
- WRITE16(cpustate,tss+0x18,REG16(BX));
- WRITE16(cpustate,tss+0x1a,REG16(SP));
- WRITE16(cpustate,tss+0x1c,REG16(BP));
- WRITE16(cpustate,tss+0x1e,REG16(SI));
- WRITE16(cpustate,tss+0x20,REG16(DI));
- WRITE16(cpustate,tss+0x22,cpustate->sreg[ES].selector);
- WRITE16(cpustate,tss+0x24,cpustate->sreg[CS].selector);
- WRITE16(cpustate,tss+0x26,cpustate->sreg[SS].selector);
- WRITE16(cpustate,tss+0x28,cpustate->sreg[DS].selector);
-
- old_task = cpustate->task.segment;
+ tss = m_task.base;
+ WRITE16(tss+0x0e,m_eip & 0x0000ffff);
+ WRITE16(tss+0x10,get_flags() & 0x0000ffff);
+ WRITE16(tss+0x12,REG16(AX));
+ WRITE16(tss+0x14,REG16(CX));
+ WRITE16(tss+0x16,REG16(DX));
+ WRITE16(tss+0x18,REG16(BX));
+ WRITE16(tss+0x1a,REG16(SP));
+ WRITE16(tss+0x1c,REG16(BP));
+ WRITE16(tss+0x1e,REG16(SI));
+ WRITE16(tss+0x20,REG16(DI));
+ WRITE16(tss+0x22,m_sreg[ES].selector);
+ WRITE16(tss+0x24,m_sreg[CS].selector);
+ WRITE16(tss+0x26,m_sreg[SS].selector);
+ WRITE16(tss+0x28,m_sreg[DS].selector);
+
+ old_task = m_task.segment;
/* Load task register with the selector of the incoming task */
- cpustate->task.segment = selector;
+ m_task.segment = selector;
memset(&seg, 0, sizeof(seg));
- seg.selector = cpustate->task.segment;
- i386_load_protected_mode_segment(cpustate,&seg,NULL);
- cpustate->task.limit = seg.limit;
- cpustate->task.base = seg.base;
- cpustate->task.flags = seg.flags;
+ seg.selector = m_task.segment;
+ i386_load_protected_mode_segment(&seg,NULL);
+ m_task.limit = seg.limit;
+ m_task.base = seg.base;
+ m_task.flags = seg.flags;
/* Set TS bit in CR0 */
- cpustate->cr[0] |= 0x08;
+ m_cr[0] |= 0x08;
/* Load incoming task state from the new task's TSS */
- tss = cpustate->task.base;
- cpustate->ldtr.segment = READ16(cpustate,tss+0x2a) & 0xffff;
- seg.selector = cpustate->ldtr.segment;
- i386_load_protected_mode_segment(cpustate,&seg,NULL);
- cpustate->ldtr.limit = seg.limit;
- cpustate->ldtr.base = seg.base;
- cpustate->ldtr.flags = seg.flags;
- cpustate->eip = READ16(cpustate,tss+0x0e);
- set_flags(cpustate,READ16(cpustate,tss+0x10));
- REG16(AX) = READ16(cpustate,tss+0x12);
- REG16(CX) = READ16(cpustate,tss+0x14);
- REG16(DX) = READ16(cpustate,tss+0x16);
- REG16(BX) = READ16(cpustate,tss+0x18);
- REG16(SP) = READ16(cpustate,tss+0x1a);
- REG16(BP) = READ16(cpustate,tss+0x1c);
- REG16(SI) = READ16(cpustate,tss+0x1e);
- REG16(DI) = READ16(cpustate,tss+0x20);
- cpustate->sreg[ES].selector = READ16(cpustate,tss+0x22) & 0xffff;
- i386_load_segment_descriptor(cpustate, ES);
- cpustate->sreg[CS].selector = READ16(cpustate,tss+0x24) & 0xffff;
- i386_load_segment_descriptor(cpustate, CS);
- cpustate->sreg[SS].selector = READ16(cpustate,tss+0x26) & 0xffff;
- i386_load_segment_descriptor(cpustate, SS);
- cpustate->sreg[DS].selector = READ16(cpustate,tss+0x28) & 0xffff;
- i386_load_segment_descriptor(cpustate, DS);
+ tss = m_task.base;
+ m_ldtr.segment = READ16(tss+0x2a) & 0xffff;
+ seg.selector = m_ldtr.segment;
+ i386_load_protected_mode_segment(&seg,NULL);
+ m_ldtr.limit = seg.limit;
+ m_ldtr.base = seg.base;
+ m_ldtr.flags = seg.flags;
+ m_eip = READ16(tss+0x0e);
+ set_flags(READ16(tss+0x10));
+ REG16(AX) = READ16(tss+0x12);
+ REG16(CX) = READ16(tss+0x14);
+ REG16(DX) = READ16(tss+0x16);
+ REG16(BX) = READ16(tss+0x18);
+ REG16(SP) = READ16(tss+0x1a);
+ REG16(BP) = READ16(tss+0x1c);
+ REG16(SI) = READ16(tss+0x1e);
+ REG16(DI) = READ16(tss+0x20);
+ m_sreg[ES].selector = READ16(tss+0x22) & 0xffff;
+ i386_load_segment_descriptor(ES);
+ m_sreg[CS].selector = READ16(tss+0x24) & 0xffff;
+ i386_load_segment_descriptor(CS);
+ m_sreg[SS].selector = READ16(tss+0x26) & 0xffff;
+ i386_load_segment_descriptor(SS);
+ m_sreg[DS].selector = READ16(tss+0x28) & 0xffff;
+ i386_load_segment_descriptor(DS);
/* Set the busy bit in the new task's descriptor */
if(selector & 0x0004)
{
- ar_byte = READ8(cpustate,cpustate->ldtr.base + (selector & ~0x0007) + 5);
- WRITE8(cpustate,cpustate->ldtr.base + (selector & ~0x0007) + 5,ar_byte | 0x02);
+ ar_byte = READ8(m_ldtr.base + (selector & ~0x0007) + 5);
+ WRITE8(m_ldtr.base + (selector & ~0x0007) + 5,ar_byte | 0x02);
}
else
{
- ar_byte = READ8(cpustate,cpustate->gdtr.base + (selector & ~0x0007) + 5);
- WRITE8(cpustate,cpustate->gdtr.base + (selector & ~0x0007) + 5,ar_byte | 0x02);
+ ar_byte = READ8(m_gdtr.base + (selector & ~0x0007) + 5);
+ WRITE8(m_gdtr.base + (selector & ~0x0007) + 5,ar_byte | 0x02);
}
/* For nested tasks, we write the outgoing task's selector to the back-link field of the new TSS,
and set the NT flag in the EFLAGS register */
if(nested != 0)
{
- WRITE16(cpustate,tss+0,old_task);
- cpustate->NT = 1;
+ WRITE16(tss+0,old_task);
+ m_NT = 1;
}
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
- cpustate->CPL = cpustate->sreg[CS].selector & 0x03;
+ m_CPL = m_sreg[CS].selector & 0x03;
// printf("286 Task Switch from selector %04x to %04x\n",old_task,selector);
}
-static void i386_task_switch(i386_state *cpustate, UINT16 selector, UINT8 nested)
+void i386_device::i386_task_switch(UINT16 selector, UINT8 nested)
{
UINT32 tss;
I386_SREG seg;
UINT16 old_task;
UINT8 ar_byte; // access rights byte
- UINT32 oldcr3 = cpustate->cr[3];
+ UINT32 oldcr3 = m_cr[3];
/* TODO: Task State Segment privilege checks */
/* For tasks that aren't nested, clear the busy bit in the task's descriptor */
if(nested == 0)
{
- if(cpustate->task.segment & 0x0004)
+ if(m_task.segment & 0x0004)
{
- ar_byte = READ8(cpustate,cpustate->ldtr.base + (cpustate->task.segment & ~0x0007) + 5);
- WRITE8(cpustate,cpustate->ldtr.base + (cpustate->task.segment & ~0x0007) + 5,ar_byte & ~0x02);
+ ar_byte = READ8(m_ldtr.base + (m_task.segment & ~0x0007) + 5);
+ WRITE8(m_ldtr.base + (m_task.segment & ~0x0007) + 5,ar_byte & ~0x02);
}
else
{
- ar_byte = READ8(cpustate,cpustate->gdtr.base + (cpustate->task.segment & ~0x0007) + 5);
- WRITE8(cpustate,cpustate->gdtr.base + (cpustate->task.segment & ~0x0007) + 5,ar_byte & ~0x02);
+ ar_byte = READ8(m_gdtr.base + (m_task.segment & ~0x0007) + 5);
+ WRITE8(m_gdtr.base + (m_task.segment & ~0x0007) + 5,ar_byte & ~0x02);
}
}
/* Save the state of the current task in the current TSS (TR register base) */
- tss = cpustate->task.base;
- WRITE32(cpustate,tss+0x1c,cpustate->cr[3]); // correct?
- WRITE32(cpustate,tss+0x20,cpustate->eip);
- WRITE32(cpustate,tss+0x24,get_flags(cpustate));
- WRITE32(cpustate,tss+0x28,REG32(EAX));
- WRITE32(cpustate,tss+0x2c,REG32(ECX));
- WRITE32(cpustate,tss+0x30,REG32(EDX));
- WRITE32(cpustate,tss+0x34,REG32(EBX));
- WRITE32(cpustate,tss+0x38,REG32(ESP));
- WRITE32(cpustate,tss+0x3c,REG32(EBP));
- WRITE32(cpustate,tss+0x40,REG32(ESI));
- WRITE32(cpustate,tss+0x44,REG32(EDI));
- WRITE32(cpustate,tss+0x48,cpustate->sreg[ES].selector);
- WRITE32(cpustate,tss+0x4c,cpustate->sreg[CS].selector);
- WRITE32(cpustate,tss+0x50,cpustate->sreg[SS].selector);
- WRITE32(cpustate,tss+0x54,cpustate->sreg[DS].selector);
- WRITE32(cpustate,tss+0x58,cpustate->sreg[FS].selector);
- WRITE32(cpustate,tss+0x5c,cpustate->sreg[GS].selector);
-
- old_task = cpustate->task.segment;
+ tss = m_task.base;
+ WRITE32(tss+0x1c,m_cr[3]); // correct?
+ WRITE32(tss+0x20,m_eip);
+ WRITE32(tss+0x24,get_flags());
+ WRITE32(tss+0x28,REG32(EAX));
+ WRITE32(tss+0x2c,REG32(ECX));
+ WRITE32(tss+0x30,REG32(EDX));
+ WRITE32(tss+0x34,REG32(EBX));
+ WRITE32(tss+0x38,REG32(ESP));
+ WRITE32(tss+0x3c,REG32(EBP));
+ WRITE32(tss+0x40,REG32(ESI));
+ WRITE32(tss+0x44,REG32(EDI));
+ WRITE32(tss+0x48,m_sreg[ES].selector);
+ WRITE32(tss+0x4c,m_sreg[CS].selector);
+ WRITE32(tss+0x50,m_sreg[SS].selector);
+ WRITE32(tss+0x54,m_sreg[DS].selector);
+ WRITE32(tss+0x58,m_sreg[FS].selector);
+ WRITE32(tss+0x5c,m_sreg[GS].selector);
+
+ old_task = m_task.segment;
/* Load task register with the selector of the incoming task */
- cpustate->task.segment = selector;
+ m_task.segment = selector;
memset(&seg, 0, sizeof(seg));
- seg.selector = cpustate->task.segment;
- i386_load_protected_mode_segment(cpustate,&seg,NULL);
- cpustate->task.limit = seg.limit;
- cpustate->task.base = seg.base;
- cpustate->task.flags = seg.flags;
+ seg.selector = m_task.segment;
+ i386_load_protected_mode_segment(&seg,NULL);
+ m_task.limit = seg.limit;
+ m_task.base = seg.base;
+ m_task.flags = seg.flags;
/* Set TS bit in CR0 */
- cpustate->cr[0] |= 0x08;
+ m_cr[0] |= 0x08;
/* Load incoming task state from the new task's TSS */
- tss = cpustate->task.base;
- cpustate->ldtr.segment = READ32(cpustate,tss+0x60) & 0xffff;
- seg.selector = cpustate->ldtr.segment;
- i386_load_protected_mode_segment(cpustate,&seg,NULL);
- cpustate->ldtr.limit = seg.limit;
- cpustate->ldtr.base = seg.base;
- cpustate->ldtr.flags = seg.flags;
- cpustate->eip = READ32(cpustate,tss+0x20);
- set_flags(cpustate,READ32(cpustate,tss+0x24));
- REG32(EAX) = READ32(cpustate,tss+0x28);
- REG32(ECX) = READ32(cpustate,tss+0x2c);
- REG32(EDX) = READ32(cpustate,tss+0x30);
- REG32(EBX) = READ32(cpustate,tss+0x34);
- REG32(ESP) = READ32(cpustate,tss+0x38);
- REG32(EBP) = READ32(cpustate,tss+0x3c);
- REG32(ESI) = READ32(cpustate,tss+0x40);
- REG32(EDI) = READ32(cpustate,tss+0x44);
- cpustate->sreg[ES].selector = READ32(cpustate,tss+0x48) & 0xffff;
- i386_load_segment_descriptor(cpustate, ES);
- cpustate->sreg[CS].selector = READ32(cpustate,tss+0x4c) & 0xffff;
- i386_load_segment_descriptor(cpustate, CS);
- cpustate->sreg[SS].selector = READ32(cpustate,tss+0x50) & 0xffff;
- i386_load_segment_descriptor(cpustate, SS);
- cpustate->sreg[DS].selector = READ32(cpustate,tss+0x54) & 0xffff;
- i386_load_segment_descriptor(cpustate, DS);
- cpustate->sreg[FS].selector = READ32(cpustate,tss+0x58) & 0xffff;
- i386_load_segment_descriptor(cpustate, FS);
- cpustate->sreg[GS].selector = READ32(cpustate,tss+0x5c) & 0xffff;
- i386_load_segment_descriptor(cpustate, GS);
+ tss = m_task.base;
+ m_ldtr.segment = READ32(tss+0x60) & 0xffff;
+ seg.selector = m_ldtr.segment;
+ i386_load_protected_mode_segment(&seg,NULL);
+ m_ldtr.limit = seg.limit;
+ m_ldtr.base = seg.base;
+ m_ldtr.flags = seg.flags;
+ m_eip = READ32(tss+0x20);
+ set_flags(READ32(tss+0x24));
+ REG32(EAX) = READ32(tss+0x28);
+ REG32(ECX) = READ32(tss+0x2c);
+ REG32(EDX) = READ32(tss+0x30);
+ REG32(EBX) = READ32(tss+0x34);
+ REG32(ESP) = READ32(tss+0x38);
+ REG32(EBP) = READ32(tss+0x3c);
+ REG32(ESI) = READ32(tss+0x40);
+ REG32(EDI) = READ32(tss+0x44);
+ m_sreg[ES].selector = READ32(tss+0x48) & 0xffff;
+ i386_load_segment_descriptor(ES);
+ m_sreg[CS].selector = READ32(tss+0x4c) & 0xffff;
+ i386_load_segment_descriptor(CS);
+ m_sreg[SS].selector = READ32(tss+0x50) & 0xffff;
+ i386_load_segment_descriptor(SS);
+ m_sreg[DS].selector = READ32(tss+0x54) & 0xffff;
+ i386_load_segment_descriptor(DS);
+ m_sreg[FS].selector = READ32(tss+0x58) & 0xffff;
+ i386_load_segment_descriptor(FS);
+ m_sreg[GS].selector = READ32(tss+0x5c) & 0xffff;
+ i386_load_segment_descriptor(GS);
/* For nested tasks, we write the outgoing task's selector to the back-link field of the new TSS,
and set the NT flag in the EFLAGS register before setting cr3 as the old tss address might be gone */
if(nested != 0)
{
- WRITE32(cpustate,tss+0,old_task);
- cpustate->NT = 1;
+ WRITE32(tss+0,old_task);
+ m_NT = 1;
}
- cpustate->cr[3] = READ32(cpustate,tss+0x1c); // CR3 (PDBR)
- if(oldcr3 != cpustate->cr[3])
- vtlb_flush_dynamic(cpustate->vtlb);
+ m_cr[3] = READ32(tss+0x1c); // CR3 (PDBR)
+ if(oldcr3 != m_cr[3])
+ vtlb_flush_dynamic(m_vtlb);
/* Set the busy bit in the new task's descriptor */
if(selector & 0x0004)
{
- ar_byte = READ8(cpustate,cpustate->ldtr.base + (selector & ~0x0007) + 5);
- WRITE8(cpustate,cpustate->ldtr.base + (selector & ~0x0007) + 5,ar_byte | 0x02);
+ ar_byte = READ8(m_ldtr.base + (selector & ~0x0007) + 5);
+ WRITE8(m_ldtr.base + (selector & ~0x0007) + 5,ar_byte | 0x02);
}
else
{
- ar_byte = READ8(cpustate,cpustate->gdtr.base + (selector & ~0x0007) + 5);
- WRITE8(cpustate,cpustate->gdtr.base + (selector & ~0x0007) + 5,ar_byte | 0x02);
+ ar_byte = READ8(m_gdtr.base + (selector & ~0x0007) + 5);
+ WRITE8(m_gdtr.base + (selector & ~0x0007) + 5,ar_byte | 0x02);
}
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
- cpustate->CPL = cpustate->sreg[CS].selector & 0x03;
+ m_CPL = m_sreg[CS].selector & 0x03;
// printf("386 Task Switch from selector %04x to %04x\n",old_task,selector);
}
-static void i386_check_irq_line(i386_state *cpustate)
+void i386_device::i386_check_irq_line()
{
- if(!cpustate->smm && cpustate->smi)
+ if(!m_smm && m_smi)
{
- pentium_smi(cpustate);
+ pentium_smi();
return;
}
/* Check if the interrupts are enabled */
- if ( (cpustate->irq_state) && cpustate->IF )
+ if ( (m_irq_state) && m_IF )
{
- cpustate->cycles -= 2;
- i386_trap(cpustate,cpustate->irq_callback(cpustate->device, 0), 1, 0);
+ m_cycles -= 2;
+ i386_trap(standard_irq_callback(0), 1, 0);
}
}
-static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 off, int indirect, int operand32)
+void i386_device::i386_protected_mode_jump(UINT16 seg, UINT32 off, int indirect, int operand32)
{
I386_SREG desc;
I386_CALL_GATE call_gate;
@@ -1259,7 +1338,7 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
if((segment & 0x04) == 0)
{
/* check GDT limit */
- if((segment & ~0x07) > (cpustate->gdtr.limit))
+ if((segment & ~0x07) > (m_gdtr.limit))
{
logerror("JMP: Segment is past GDT limit.\n");
FAULT(FAULT_GP,segment & 0xfffc)
@@ -1268,7 +1347,7 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
else
{
/* check LDT limit */
- if((segment & ~0x07) > (cpustate->ldtr.limit))
+ if((segment & ~0x07) > (m_ldtr.limit))
{
logerror("JMP: Segment is past LDT limit.\n");
FAULT(FAULT_GP,segment & 0xfffc)
@@ -1277,8 +1356,8 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
/* Determine segment type */
memset(&desc, 0, sizeof(desc));
desc.selector = segment;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
- CPL = cpustate->CPL; // current privilege level
+ i386_load_protected_mode_segment(&desc,NULL);
+ CPL = m_CPL; // current privilege level
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
RPL = segment & 0x03; // requested privilege level
if((desc.flags & 0x0018) == 0x0018)
@@ -1332,10 +1411,10 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
{
case 0x01: // 286 Available TSS
case 0x09: // 386 Available TSS
- logerror("JMP: Available 386 TSS at %08x\n",cpustate->pc);
+ logerror("JMP: Available 386 TSS at %08x\n",m_pc);
memset(&desc, 0, sizeof(desc));
desc.selector = segment;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
if(DPL < CPL)
{
@@ -1353,17 +1432,17 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
FAULT(FAULT_GP,segment & 0xfffc)
}
if(desc.flags & 0x0008)
- i386_task_switch(cpustate,desc.selector,0);
+ i386_task_switch(desc.selector,0);
else
- i286_task_switch(cpustate,desc.selector,0);
+ i286_task_switch(desc.selector,0);
return;
case 0x04: // 286 Call Gate
case 0x0c: // 386 Call Gate
- //logerror("JMP: Call gate at %08x\n",cpustate->pc);
+ //logerror("JMP: Call gate at %08x\n",m_pc);
SetRPL = 1;
memset(&call_gate, 0, sizeof(call_gate));
call_gate.segment = segment;
- i386_load_call_gate(cpustate,&call_gate);
+ i386_load_call_gate(&call_gate);
DPL = call_gate.dpl;
if(DPL < CPL)
{
@@ -1388,7 +1467,7 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
}
if(call_gate.selector & 0x04)
{
- if((call_gate.selector & ~0x07) > cpustate->ldtr.limit)
+ if((call_gate.selector & ~0x07) > m_ldtr.limit)
{
logerror("JMP: Call Gate: Gate Selector is past LDT segment limit\n");
FAULT(FAULT_GP,call_gate.selector & 0xfffc)
@@ -1396,14 +1475,14 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
}
else
{
- if((call_gate.selector & ~0x07) > cpustate->gdtr.limit)
+ if((call_gate.selector & ~0x07) > m_gdtr.limit)
{
logerror("JMP: Call Gate: Gate Selector is past GDT segment limit\n");
FAULT(FAULT_GP,call_gate.selector & 0xfffc)
}
}
desc.selector = call_gate.selector;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
DPL = (desc.flags >> 5) & 0x03;
if((desc.flags & 0x0018) != 0x18)
{
@@ -1440,10 +1519,10 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
offset = call_gate.offset;
break;
case 0x05: // Task Gate
- logerror("JMP: Task gate at %08x\n",cpustate->pc);
+ logerror("JMP: Task gate at %08x\n",m_pc);
memset(&call_gate, 0, sizeof(call_gate));
call_gate.segment = segment;
- i386_load_call_gate(cpustate,&call_gate);
+ i386_load_call_gate(&call_gate);
DPL = call_gate.dpl;
if(DPL < CPL)
{
@@ -1462,7 +1541,7 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
}
/* Check the TSS that the task gate points to */
desc.selector = call_gate.selector;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
RPL = call_gate.selector & 0x03; // requested privilege level
if(call_gate.selector & 0x04)
@@ -1472,7 +1551,7 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
}
else
{
- if((call_gate.selector & ~0x07) > cpustate->gdtr.limit)
+ if((call_gate.selector & ~0x07) > m_gdtr.limit)
{
logerror("JMP: Task Gate TSS: TSS is past GDT limit.\n");
FAULT(FAULT_GP,call_gate.selector & 0xfffc)
@@ -1489,9 +1568,9 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
FAULT(FAULT_NP,call_gate.selector & 0xfffc)
}
if(call_gate.ar & 0x08)
- i386_task_switch(cpustate,call_gate.selector,0);
+ i386_task_switch(call_gate.selector,0);
else
- i286_task_switch(cpustate,call_gate.selector,0);
+ i286_task_switch(call_gate.selector,0);
return;
default: // invalid segment type
logerror("JMP: Invalid segment type (%i) to jump to.\n",desc.flags & 0x000f);
@@ -1501,18 +1580,18 @@ static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 of
}
if(SetRPL != 0)
- segment = (segment & ~0x03) | cpustate->CPL;
+ segment = (segment & ~0x03) | m_CPL;
if(operand32 == 0)
- cpustate->eip = offset & 0x0000ffff;
+ m_eip = offset & 0x0000ffff;
else
- cpustate->eip = offset;
- cpustate->sreg[CS].selector = segment;
- cpustate->performed_intersegment_jump = 1;
- i386_load_segment_descriptor(cpustate,CS);
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = offset;
+ m_sreg[CS].selector = segment;
+ m_performed_intersegment_jump = 1;
+ i386_load_segment_descriptor(CS);
+ CHANGE_PC(m_eip);
}
-static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 off, int indirect, int operand32)
+void i386_device::i386_protected_mode_call(UINT16 seg, UINT32 off, int indirect, int operand32)
{
I386_SREG desc;
I386_CALL_GATE gate;
@@ -1524,12 +1603,12 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
if((selector & ~0x03) == 0)
{
- logerror("CALL (%08x): Selector is null.\n",cpustate->pc);
+ logerror("CALL (%08x): Selector is null.\n",m_pc);
FAULT(FAULT_GP,0) // #GP(0)
}
if(selector & 0x04)
{
- if((selector & ~0x07) > cpustate->ldtr.limit)
+ if((selector & ~0x07) > m_ldtr.limit)
{
logerror("CALL: Selector is past LDT limit.\n");
FAULT(FAULT_GP,selector & ~0x03) // #GP(selector)
@@ -1537,7 +1616,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
else
{
- if((selector & ~0x07) > cpustate->gdtr.limit)
+ if((selector & ~0x07) > m_gdtr.limit)
{
logerror("CALL: Selector is past GDT limit.\n");
FAULT(FAULT_GP,selector & ~0x03) // #GP(selector)
@@ -1547,8 +1626,8 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
/* Determine segment type */
memset(&desc, 0, sizeof(desc));
desc.selector = selector;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
- CPL = cpustate->CPL; // current privilege level
+ i386_load_protected_mode_segment(&desc,NULL);
+ CPL = m_CPL; // current privilege level
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
RPL = selector & 0x03; // requested privilege level
if((desc.flags & 0x0018) == 0x18) // is a code segment
@@ -1579,7 +1658,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
SetRPL = 1;
if((desc.flags & 0x0080) == 0)
{
- logerror("CALL (%08x): Code segment is not present.\n",cpustate->pc);
+ logerror("CALL (%08x): Code segment is not present.\n",m_pc);
FAULT(FAULT_NP,selector & ~0x03) // #NP(selector)
}
if (operand32 != 0) // if 32-bit
@@ -1618,7 +1697,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
{
case 0x01: // Available 286 TSS
case 0x09: // Available 386 TSS
- logerror("CALL: Available TSS at %08x\n",cpustate->pc);
+ logerror("CALL: Available TSS at %08x\n",m_pc);
if(DPL < CPL)
{
logerror("CALL: TSS: DPL is less than CPL.\n");
@@ -1640,9 +1719,9 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
FAULT(FAULT_NP,selector & ~0x03) // #NP(selector)
}
if(desc.flags & 0x08)
- i386_task_switch(cpustate,desc.selector,1);
+ i386_task_switch(desc.selector,1);
else
- i286_task_switch(cpustate,desc.selector,1);
+ i286_task_switch(desc.selector,1);
return;
case 0x04: // 286 call gate
case 0x0c: // 386 call gate
@@ -1652,9 +1731,9 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
operand32 = 1;
memset(&gate, 0, sizeof(gate));
gate.segment = selector;
- i386_load_call_gate(cpustate,&gate);
+ i386_load_call_gate(&gate);
DPL = gate.dpl;
- //logerror("CALL: Call gate at %08x (%i parameters)\n",cpustate->pc,gate.dword_count);
+ //logerror("CALL: Call gate at %08x (%i parameters)\n",m_pc,gate.dword_count);
if(DPL < CPL)
{
logerror("CALL: Call gate DPL %i is less than CPL %i.\n",DPL,CPL);
@@ -1678,7 +1757,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
if(desc.selector & 0x04)
{
- if((desc.selector & ~0x07) > cpustate->ldtr.limit)
+ if((desc.selector & ~0x07) > m_ldtr.limit)
{
logerror("CALL: Call gate: Segment is past LDT limit\n");
FAULT(FAULT_GP,desc.selector & ~0x03) // #GP(selector)
@@ -1686,13 +1765,13 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
else
{
- if((desc.selector & ~0x07) > cpustate->gdtr.limit)
+ if((desc.selector & ~0x07) > m_gdtr.limit)
{
logerror("CALL: Call gate: Segment is past GDT limit\n");
FAULT(FAULT_GP,desc.selector & ~0x03) // #GP(selector)
}
}
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
if((desc.flags & 0x0018) != 0x18)
{
logerror("CALL: Call gate: Segment is not a code segment.\n");
@@ -1706,7 +1785,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
if((desc.flags & 0x0080) == 0)
{
- logerror("CALL (%08x): Code segment is not present.\n",cpustate->pc);
+ logerror("CALL (%08x): Code segment is not present.\n",m_pc);
FAULT(FAULT_NP,desc.selector & ~0x03) // #NP(selector)
}
if(DPL < CPL && (desc.flags & 0x0004) == 0)
@@ -1717,8 +1796,8 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
/* more privilege */
/* Check new SS segment for privilege level from TSS */
memset(&stack, 0, sizeof(stack));
- stack.selector = i386_get_stack_segment(cpustate,DPL);
- i386_load_protected_mode_segment(cpustate,&stack,NULL);
+ stack.selector = i386_get_stack_segment(DPL);
+ i386_load_protected_mode_segment(&stack,NULL);
if((stack.selector & ~0x03) == 0)
{
logerror("CALL: Call gate: TSS selector is null\n");
@@ -1726,7 +1805,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
if(stack.selector & 0x04)
{
- if((stack.selector & ~0x07) > cpustate->ldtr.limit)
+ if((stack.selector & ~0x07) > m_ldtr.limit)
{
logerror("CALL: Call gate: TSS selector is past LDT limit\n");
FAULT(FAULT_TS,stack.selector) // #TS(SS selector)
@@ -1734,7 +1813,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
else
{
- if((stack.selector & ~0x07) > cpustate->gdtr.limit)
+ if((stack.selector & ~0x07) > m_gdtr.limit)
{
logerror("CALL: Call gate: TSS selector is past GDT limit\n");
FAULT(FAULT_TS,stack.selector) // #TS(SS selector)
@@ -1760,7 +1839,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
logerror("CALL: Call gate: Stack segment is not present\n");
FAULT(FAULT_SS,stack.selector) // #SS(SS selector)
}
- UINT32 newESP = i386_get_stack_ptr(cpustate,DPL);
+ UINT32 newESP = i386_get_stack_ptr(DPL);
if(!stack.d)
{
newESP &= 0xffff;
@@ -1794,12 +1873,12 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
selector = gate.selector;
offset = gate.offset;
- cpustate->CPL = (stack.flags >> 5) & 0x03;
+ m_CPL = (stack.flags >> 5) & 0x03;
/* check for page fault at new stack */
- WRITE_TEST(cpustate, stack.base+newESP-1);
+ WRITE_TEST(stack.base+newESP-1);
/* switch to new stack */
- oldSS = cpustate->sreg[SS].selector;
- cpustate->sreg[SS].selector = i386_get_stack_segment(cpustate,cpustate->CPL);
+ oldSS = m_sreg[SS].selector;
+ m_sreg[SS].selector = i386_get_stack_segment(m_CPL);
if(operand32 != 0)
{
oldESP = REG32(ESP);
@@ -1808,32 +1887,32 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
{
oldESP = REG16(SP);
}
- i386_load_segment_descriptor(cpustate, SS );
+ i386_load_segment_descriptor(SS );
REG32(ESP) = newESP;
if(operand32 != 0)
{
- PUSH32(cpustate,oldSS);
- PUSH32(cpustate,oldESP);
+ PUSH32(oldSS);
+ PUSH32(oldESP);
}
else
{
- PUSH16(cpustate,oldSS);
- PUSH16(cpustate,oldESP & 0xffff);
+ PUSH16(oldSS);
+ PUSH16(oldESP & 0xffff);
}
memset(&temp, 0, sizeof(temp));
temp.selector = oldSS;
- i386_load_protected_mode_segment(cpustate,&temp,NULL);
+ i386_load_protected_mode_segment(&temp,NULL);
/* copy parameters from old stack to new stack */
for(x=(gate.dword_count & 0x1f)-1;x>=0;x--)
{
UINT32 addr = oldESP + (operand32?(x*4):(x*2));
addr = temp.base + (temp.d?addr:(addr&0xffff));
if(operand32)
- PUSH32(cpustate,READ32(cpustate,addr));
+ PUSH32(READ32(addr));
else
- PUSH16(cpustate,READ16(cpustate,addr));
+ PUSH16(READ16(addr));
}
SetRPL = 1;
}
@@ -1869,10 +1948,10 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
break;
case 0x05: // task gate
- logerror("CALL: Task gate at %08x\n",cpustate->pc);
+ logerror("CALL: Task gate at %08x\n",m_pc);
memset(&gate, 0, sizeof(gate));
gate.segment = selector;
- i386_load_call_gate(cpustate,&gate);
+ i386_load_call_gate(&gate);
DPL = gate.dpl;
if(DPL < CPL)
{
@@ -1891,7 +1970,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
/* Check the TSS that the task gate points to */
desc.selector = gate.selector;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
if(gate.selector & 0x04)
{
logerror("CALL: Task Gate: TSS is not global.\n");
@@ -1899,7 +1978,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
else
{
- if((gate.selector & ~0x07) > cpustate->gdtr.limit)
+ if((gate.selector & ~0x07) > m_gdtr.limit)
{
logerror("CALL: Task Gate: TSS is past GDT limit.\n");
FAULT(FAULT_TS,gate.selector & ~0x03) // #TS(selector)
@@ -1916,9 +1995,9 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
FAULT(FAULT_NP,gate.selector & ~0x03) // #TS(selector)
}
if(desc.flags & 0x08)
- i386_task_switch(cpustate,desc.selector,1); // with nesting
+ i386_task_switch(desc.selector,1); // with nesting
else
- i286_task_switch(cpustate,desc.selector,1);
+ i286_task_switch(desc.selector,1);
return;
default:
logerror("CALL: Invalid special segment type (%i) to jump to.\n",desc.flags & 0x000f);
@@ -1928,7 +2007,7 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
}
if(SetRPL != 0)
- selector = (selector & ~0x03) | cpustate->CPL;
+ selector = (selector & ~0x03) | m_CPL;
UINT32 tempSP = REG32(ESP);
try
@@ -1937,22 +2016,22 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
if(operand32 == 0)
{
/* 16-bit operand size */
- PUSH16(cpustate, cpustate->sreg[CS].selector );
- PUSH16(cpustate, cpustate->eip & 0x0000ffff );
- cpustate->sreg[CS].selector = selector;
- cpustate->performed_intersegment_jump = 1;
- cpustate->eip = offset;
- i386_load_segment_descriptor(cpustate,CS);
+ PUSH16(m_sreg[CS].selector );
+ PUSH16(m_eip & 0x0000ffff );
+ m_sreg[CS].selector = selector;
+ m_performed_intersegment_jump = 1;
+ m_eip = offset;
+ i386_load_segment_descriptor(CS);
}
else
{
/* 32-bit operand size */
- PUSH32(cpustate, cpustate->sreg[CS].selector );
- PUSH32(cpustate, cpustate->eip );
- cpustate->sreg[CS].selector = selector;
- cpustate->performed_intersegment_jump = 1;
- cpustate->eip = offset;
- i386_load_segment_descriptor(cpustate, CS );
+ PUSH32(m_sreg[CS].selector );
+ PUSH32(m_eip );
+ m_sreg[CS].selector = selector;
+ m_performed_intersegment_jump = 1;
+ m_eip = offset;
+ i386_load_segment_descriptor(CS );
}
}
catch(UINT64 e)
@@ -1961,38 +2040,38 @@ static void i386_protected_mode_call(i386_state *cpustate, UINT16 seg, UINT32 of
throw e;
}
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 operand32)
+void i386_device::i386_protected_mode_retf(UINT8 count, UINT8 operand32)
{
UINT32 newCS, newEIP;
I386_SREG desc;
UINT8 CPL, RPL, DPL;
- UINT32 ea = i386_translate(cpustate, SS, (STACK_32BIT)?REG32(ESP):REG16(SP), 0);
+ UINT32 ea = i386_translate(SS, (STACK_32BIT)?REG32(ESP):REG16(SP), 0);
if(operand32 == 0)
{
- newEIP = READ16(cpustate, ea) & 0xffff;
- newCS = READ16(cpustate, ea+2) & 0xffff;
+ newEIP = READ16(ea) & 0xffff;
+ newCS = READ16(ea+2) & 0xffff;
}
else
{
- newEIP = READ32(cpustate, ea);
- newCS = READ32(cpustate, ea+4) & 0xffff;
+ newEIP = READ32(ea);
+ newCS = READ32(ea+4) & 0xffff;
}
memset(&desc, 0, sizeof(desc));
desc.selector = newCS;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
- CPL = cpustate->CPL; // current privilege level
+ i386_load_protected_mode_segment(&desc,NULL);
+ CPL = m_CPL; // current privilege level
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
RPL = newCS & 0x03;
if(RPL < CPL)
{
- logerror("RETF (%08x): Return segment RPL is less than CPL.\n",cpustate->pc);
+ logerror("RETF (%08x): Return segment RPL is less than CPL.\n",m_pc);
FAULT(FAULT_GP,newCS & ~0x03)
}
@@ -2006,7 +2085,7 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
}
if(newCS & 0x04)
{
- if((newCS & ~0x07) >= cpustate->ldtr.limit)
+ if((newCS & ~0x07) >= m_ldtr.limit)
{
logerror("RETF: Return segment is past LDT limit.\n");
FAULT(FAULT_GP,newCS & ~0x03)
@@ -2014,7 +2093,7 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
}
else
{
- if((newCS & ~0x07) >= cpustate->gdtr.limit)
+ if((newCS & ~0x07) >= m_gdtr.limit)
{
logerror("RETF: Return segment is past GDT limit.\n");
FAULT(FAULT_GP,newCS & ~0x03)
@@ -2043,7 +2122,7 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
}
if((desc.flags & 0x0080) == 0)
{
- logerror("RETF (%08x): Code segment is not present.\n",cpustate->pc);
+ logerror("RETF (%08x): Code segment is not present.\n",m_pc);
FAULT(FAULT_NP,newCS & ~0x03)
}
if(newEIP > desc.limit)
@@ -2054,16 +2133,16 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
if(operand32 == 0)
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+count+3) != 0)
+ if(i386_limit_check(SS,offset+count+3) != 0)
{
- logerror("RETF (%08x): SP is past stack segment limit.\n",cpustate->pc);
+ logerror("RETF (%08x): SP is past stack segment limit.\n",m_pc);
FAULT(FAULT_SS,0)
}
}
else
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+count+7) != 0)
+ if(i386_limit_check(SS,offset+count+7) != 0)
{
logerror("RETF: ESP is past stack segment limit.\n");
FAULT(FAULT_SS,0)
@@ -2081,16 +2160,16 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
if(operand32 == 0)
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+count+7) != 0)
+ if(i386_limit_check(SS,offset+count+7) != 0)
{
- logerror("RETF (%08x): SP is past stack segment limit.\n",cpustate->pc);
+ logerror("RETF (%08x): SP is past stack segment limit.\n",m_pc);
FAULT(FAULT_SS,0)
}
}
else
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+count+15) != 0)
+ if(i386_limit_check(SS,offset+count+15) != 0)
{
logerror("RETF: ESP is past stack segment limit.\n");
FAULT(FAULT_SS,0)
@@ -2104,7 +2183,7 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
}
if(newCS & 0x04)
{
- if((newCS & ~0x07) >= cpustate->ldtr.limit)
+ if((newCS & ~0x07) >= m_ldtr.limit)
{
logerror("RETF: CS segment selector is past LDT limit.\n");
FAULT(FAULT_GP,newCS & ~0x03)
@@ -2112,7 +2191,7 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
}
else
{
- if((newCS & ~0x07) >= cpustate->gdtr.limit)
+ if((newCS & ~0x07) >= m_gdtr.limit)
{
logerror("RETF: CS segment selector is past GDT limit.\n");
FAULT(FAULT_GP,newCS & ~0x03)
@@ -2153,19 +2232,19 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
if(operand32 == 0)
{
ea += count+4;
- newESP = READ16(cpustate, ea) & 0xffff;
- newSS = READ16(cpustate, ea+2) & 0xffff;
+ newESP = READ16(ea) & 0xffff;
+ newSS = READ16(ea+2) & 0xffff;
}
else
{
ea += count+8;
- newESP = READ32(cpustate, ea);
- newSS = READ32(cpustate, ea+4) & 0xffff;
+ newESP = READ32(ea);
+ newSS = READ32(ea+4) & 0xffff;
}
/* Check SS selector and descriptor */
desc.selector = newSS;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
if((newSS & ~0x07) == 0)
{
@@ -2174,17 +2253,17 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
}
if(newSS & 0x04)
{
- if((newSS & ~0x07) > cpustate->ldtr.limit)
+ if((newSS & ~0x07) > m_ldtr.limit)
{
- logerror("RETF (%08x): SS segment selector is past LDT limit.\n",cpustate->pc);
+ logerror("RETF (%08x): SS segment selector is past LDT limit.\n",m_pc);
FAULT(FAULT_GP,newSS & ~0x03)
}
}
else
{
- if((newSS & ~0x07) > cpustate->gdtr.limit)
+ if((newSS & ~0x07) > m_gdtr.limit)
{
- logerror("RETF (%08x): SS segment selector is past GDT limit.\n",cpustate->pc);
+ logerror("RETF (%08x): SS segment selector is past GDT limit.\n",m_pc);
FAULT(FAULT_GP,newSS & ~0x03)
}
}
@@ -2208,34 +2287,34 @@ static void i386_protected_mode_retf(i386_state* cpustate, UINT8 count, UINT8 op
logerror("RETF: SS segment is not present.\n");
FAULT(FAULT_GP,newSS & ~0x03)
}
- cpustate->CPL = newCS & 0x03;
+ m_CPL = newCS & 0x03;
/* Load new SS:(E)SP */
if(operand32 == 0)
REG16(SP) = (newESP+count) & 0xffff;
else
REG32(ESP) = newESP+count;
- cpustate->sreg[SS].selector = newSS;
- i386_load_segment_descriptor(cpustate, SS );
+ m_sreg[SS].selector = newSS;
+ i386_load_segment_descriptor(SS );
/* Check that DS, ES, FS and GS are valid for the new privilege level */
- i386_check_sreg_validity(cpustate,DS);
- i386_check_sreg_validity(cpustate,ES);
- i386_check_sreg_validity(cpustate,FS);
- i386_check_sreg_validity(cpustate,GS);
+ i386_check_sreg_validity(DS);
+ i386_check_sreg_validity(ES);
+ i386_check_sreg_validity(FS);
+ i386_check_sreg_validity(GS);
}
/* Load new CS:(E)IP */
if(operand32 == 0)
- cpustate->eip = newEIP & 0xffff;
+ m_eip = newEIP & 0xffff;
else
- cpustate->eip = newEIP;
- cpustate->sreg[CS].selector = newCS;
- i386_load_segment_descriptor(cpustate, CS );
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = newEIP;
+ m_sreg[CS].selector = newCS;
+ i386_load_segment_descriptor(CS );
+ CHANGE_PC(m_eip);
}
-static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
+void i386_device::i386_protected_mode_iret(int operand32)
{
UINT32 newCS, newEIP;
UINT32 newSS, newESP; // when changing privilege
@@ -2243,70 +2322,70 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
UINT8 CPL, RPL, DPL;
UINT32 newflags;
- CPL = cpustate->CPL;
- UINT32 ea = i386_translate(cpustate, SS, (STACK_32BIT)?REG32(ESP):REG16(SP), 0);
+ CPL = m_CPL;
+ UINT32 ea = i386_translate(SS, (STACK_32BIT)?REG32(ESP):REG16(SP), 0);
if(operand32 == 0)
{
- newEIP = READ16(cpustate, ea) & 0xffff;
- newCS = READ16(cpustate, ea+2) & 0xffff;
- newflags = READ16(cpustate, ea+4) & 0xffff;
+ newEIP = READ16(ea) & 0xffff;
+ newCS = READ16(ea+2) & 0xffff;
+ newflags = READ16(ea+4) & 0xffff;
}
else
{
- newEIP = READ32(cpustate, ea);
- newCS = READ32(cpustate, ea+4) & 0xffff;
- newflags = READ32(cpustate, ea+8);
+ newEIP = READ32(ea);
+ newCS = READ32(ea+4) & 0xffff;
+ newflags = READ32(ea+8);
}
if(V8086_MODE)
{
- UINT32 oldflags = get_flags(cpustate);
- if(!cpustate->IOP1 || !cpustate->IOP2)
+ UINT32 oldflags = get_flags();
+ if(!m_IOP1 || !m_IOP2)
{
- logerror("IRET (%08x): Is in Virtual 8086 mode and IOPL != 3.\n",cpustate->pc);
+ logerror("IRET (%08x): Is in Virtual 8086 mode and IOPL != 3.\n",m_pc);
FAULT(FAULT_GP,0)
}
if(operand32 == 0)
{
- cpustate->eip = newEIP & 0xffff;
- cpustate->sreg[CS].selector = newCS & 0xffff;
+ m_eip = newEIP & 0xffff;
+ m_sreg[CS].selector = newCS & 0xffff;
newflags &= ~(3<<12);
newflags |= (((oldflags>>12)&3)<<12); // IOPL cannot be changed in V86 mode
- set_flags(cpustate,(newflags & 0xffff) | (oldflags & ~0xffff));
+ set_flags((newflags & 0xffff) | (oldflags & ~0xffff));
REG16(SP) += 6;
}
else
{
- cpustate->eip = newEIP;
- cpustate->sreg[CS].selector = newCS & 0xffff;
+ m_eip = newEIP;
+ m_sreg[CS].selector = newCS & 0xffff;
newflags &= ~(3<<12);
newflags |= 0x20000 | (((oldflags>>12)&3)<<12); // IOPL and VM cannot be changed in V86 mode
- set_flags(cpustate,newflags);
+ set_flags(newflags);
REG32(ESP) += 12;
}
}
else if(NESTED_TASK)
{
- UINT32 task = READ32(cpustate,cpustate->task.base);
+ UINT32 task = READ32(m_task.base);
/* Task Return */
- logerror("IRET (%08x): Nested task return.\n",cpustate->pc);
+ logerror("IRET (%08x): Nested task return.\n",m_pc);
/* Check back-link selector in TSS */
if(task & 0x04)
{
logerror("IRET: Task return: Back-linked TSS is not in GDT.\n");
FAULT(FAULT_TS,task & ~0x03)
}
- if((task & ~0x07) >= cpustate->gdtr.limit)
+ if((task & ~0x07) >= m_gdtr.limit)
{
logerror("IRET: Task return: Back-linked TSS is not in GDT.\n");
FAULT(FAULT_TS,task & ~0x03)
}
memset(&desc, 0, sizeof(desc));
desc.selector = task;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
if((desc.flags & 0x001f) != 0x000b)
{
- logerror("IRET (%08x): Task return: Back-linked TSS is not a busy TSS.\n",cpustate->pc);
+ logerror("IRET (%08x): Task return: Back-linked TSS is not a busy TSS.\n",m_pc);
FAULT(FAULT_TS,task & ~0x03)
}
if((desc.flags & 0x0080) == 0)
@@ -2315,9 +2394,9 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
FAULT(FAULT_NP,task & ~0x03)
}
if(desc.flags & 0x08)
- i386_task_switch(cpustate,desc.selector,0);
+ i386_task_switch(desc.selector,0);
else
- i286_task_switch(cpustate,desc.selector,0);
+ i286_task_switch(desc.selector,0);
return;
}
else
@@ -2325,40 +2404,40 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
if(newflags & 0x00020000) // if returning to virtual 8086 mode
{
// 16-bit iret can't reach here
- newESP = READ32(cpustate, ea+12);
- newSS = READ32(cpustate, ea+16) & 0xffff;
+ newESP = READ32(ea+12);
+ newSS = READ32(ea+16) & 0xffff;
/* Return to v86 mode */
- //logerror("IRET (%08x): Returning to Virtual 8086 mode.\n",cpustate->pc);
+ //logerror("IRET (%08x): Returning to Virtual 8086 mode.\n",m_pc);
if(CPL != 0)
{
- UINT32 oldflags = get_flags(cpustate);
+ UINT32 oldflags = get_flags();
newflags = (newflags & ~0x00003000) | (oldflags & 0x00003000);
}
- set_flags(cpustate,newflags);
- cpustate->eip = POP32(cpustate) & 0xffff; // high 16 bits are ignored
- cpustate->sreg[CS].selector = POP32(cpustate) & 0xffff;
- POP32(cpustate); // already set flags
- newESP = POP32(cpustate);
- newSS = POP32(cpustate) & 0xffff;
- cpustate->sreg[ES].selector = POP32(cpustate) & 0xffff;
- cpustate->sreg[DS].selector = POP32(cpustate) & 0xffff;
- cpustate->sreg[FS].selector = POP32(cpustate) & 0xffff;
- cpustate->sreg[GS].selector = POP32(cpustate) & 0xffff;
+ set_flags(newflags);
+ m_eip = POP32() & 0xffff; // high 16 bits are ignored
+ m_sreg[CS].selector = POP32() & 0xffff;
+ POP32(); // already set flags
+ newESP = POP32();
+ newSS = POP32() & 0xffff;
+ m_sreg[ES].selector = POP32() & 0xffff;
+ m_sreg[DS].selector = POP32() & 0xffff;
+ m_sreg[FS].selector = POP32() & 0xffff;
+ m_sreg[GS].selector = POP32() & 0xffff;
REG32(ESP) = newESP; // all 32 bits are loaded
- cpustate->sreg[SS].selector = newSS;
- i386_load_segment_descriptor(cpustate,ES);
- i386_load_segment_descriptor(cpustate,DS);
- i386_load_segment_descriptor(cpustate,FS);
- i386_load_segment_descriptor(cpustate,GS);
- i386_load_segment_descriptor(cpustate,SS);
- cpustate->CPL = 3; // Virtual 8086 tasks are always run at CPL 3
+ m_sreg[SS].selector = newSS;
+ i386_load_segment_descriptor(ES);
+ i386_load_segment_descriptor(DS);
+ i386_load_segment_descriptor(FS);
+ i386_load_segment_descriptor(GS);
+ i386_load_segment_descriptor(SS);
+ m_CPL = 3; // Virtual 8086 tasks are always run at CPL 3
}
else
{
if(operand32 == 0)
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) != 0)
+ if(i386_limit_check(SS,offset+3) != 0)
{
logerror("IRET: Data on stack is past SS limit.\n");
FAULT(FAULT_SS,0)
@@ -2367,7 +2446,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
else
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+7) != 0)
+ if(i386_limit_check(SS,offset+7) != 0)
{
logerror("IRET: Data on stack is past SS limit.\n");
FAULT(FAULT_SS,0)
@@ -2376,7 +2455,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
RPL = newCS & 0x03;
if(RPL < CPL)
{
- logerror("IRET (%08x): Return CS RPL is less than CPL.\n",cpustate->pc);
+ logerror("IRET (%08x): Return CS RPL is less than CPL.\n",m_pc);
FAULT(FAULT_GP,newCS & ~0x03)
}
if(RPL == CPL)
@@ -2385,18 +2464,18 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
if(operand32 == 0)
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+5) != 0)
+ if(i386_limit_check(SS,offset+5) != 0)
{
- logerror("IRET (%08x): Data on stack is past SS limit.\n",cpustate->pc);
+ logerror("IRET (%08x): Data on stack is past SS limit.\n",m_pc);
FAULT(FAULT_SS,0)
}
}
else
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+11) != 0)
+ if(i386_limit_check(SS,offset+11) != 0)
{
- logerror("IRET (%08x): Data on stack is past SS limit.\n",cpustate->pc);
+ logerror("IRET (%08x): Data on stack is past SS limit.\n",m_pc);
FAULT(FAULT_SS,0)
}
}
@@ -2407,7 +2486,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
}
if(newCS & 0x04)
{
- if((newCS & ~0x07) >= cpustate->ldtr.limit)
+ if((newCS & ~0x07) >= m_ldtr.limit)
{
logerror("IRET: Return CS selector (%04x) is past LDT limit.\n",newCS);
FAULT(FAULT_GP,newCS & ~0x03)
@@ -2415,7 +2494,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
}
else
{
- if((newCS & ~0x07) >= cpustate->gdtr.limit)
+ if((newCS & ~0x07) >= m_gdtr.limit)
{
logerror("IRET: Return CS selector is past GDT limit.\n");
FAULT(FAULT_GP,newCS & ~0x03)
@@ -2423,12 +2502,12 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
}
memset(&desc, 0, sizeof(desc));
desc.selector = newCS;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
RPL = newCS & 0x03;
if((desc.flags & 0x0018) != 0x0018)
{
- logerror("IRET (%08x): Return CS segment is not a code segment.\n",cpustate->pc);
+ logerror("IRET (%08x): Return CS segment is not a code segment.\n",m_pc);
FAULT(FAULT_GP,newCS & ~0x07)
}
if(desc.flags & 0x0004)
@@ -2460,22 +2539,22 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
if(CPL != 0)
{
- UINT32 oldflags = get_flags(cpustate);
+ UINT32 oldflags = get_flags();
newflags = (newflags & ~0x00003000) | (oldflags & 0x00003000);
}
if(operand32 == 0)
{
- cpustate->eip = newEIP;
- cpustate->sreg[CS].selector = newCS;
- set_flags(cpustate,newflags);
+ m_eip = newEIP;
+ m_sreg[CS].selector = newCS;
+ set_flags(newflags);
REG16(SP) += 6;
}
else
{
- cpustate->eip = newEIP;
- cpustate->sreg[CS].selector = newCS & 0xffff;
- set_flags(cpustate,newflags);
+ m_eip = newEIP;
+ m_sreg[CS].selector = newCS & 0xffff;
+ set_flags(newflags);
REG32(ESP) += 12;
}
}
@@ -2484,13 +2563,13 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
/* return to outer privilege level */
memset(&desc, 0, sizeof(desc));
desc.selector = newCS;
- i386_load_protected_mode_segment(cpustate,&desc,NULL);
+ i386_load_protected_mode_segment(&desc,NULL);
DPL = (desc.flags >> 5) & 0x03; // descriptor privilege level
RPL = newCS & 0x03;
if(operand32 == 0)
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+9) != 0)
+ if(i386_limit_check(SS,offset+9) != 0)
{
logerror("IRET: SP is past SS limit.\n");
FAULT(FAULT_SS,0)
@@ -2499,7 +2578,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
else
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+19) != 0)
+ if(i386_limit_check(SS,offset+19) != 0)
{
logerror("IRET: ESP is past SS limit.\n");
FAULT(FAULT_SS,0)
@@ -2513,7 +2592,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
}
if(newCS & 0x04)
{
- if((newCS & ~0x07) >= cpustate->ldtr.limit)
+ if((newCS & ~0x07) >= m_ldtr.limit)
{
logerror("IRET: Return CS selector is past LDT limit.\n");
FAULT(FAULT_GP,newCS & ~0x03);
@@ -2521,7 +2600,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
}
else
{
- if((newCS & ~0x07) >= cpustate->gdtr.limit)
+ if((newCS & ~0x07) >= m_gdtr.limit)
{
logerror("IRET: Return CS selector is past GDT limit.\n");
FAULT(FAULT_GP,newCS & ~0x03);
@@ -2557,17 +2636,17 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
/* Check SS selector and descriptor */
if(operand32 == 0)
{
- newESP = READ16(cpustate, ea+6) & 0xffff;
- newSS = READ16(cpustate, ea+8) & 0xffff;
+ newESP = READ16(ea+6) & 0xffff;
+ newSS = READ16(ea+8) & 0xffff;
}
else
{
- newESP = READ32(cpustate, ea+12);
- newSS = READ32(cpustate, ea+16) & 0xffff;
+ newESP = READ32(ea+12);
+ newSS = READ32(ea+16) & 0xffff;
}
memset(&stack, 0, sizeof(stack));
stack.selector = newSS;
- i386_load_protected_mode_segment(cpustate,&stack,NULL);
+ i386_load_protected_mode_segment(&stack,NULL);
DPL = (stack.flags >> 5) & 0x03;
if((newSS & ~0x03) == 0)
{
@@ -2576,7 +2655,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
}
if(newSS & 0x04)
{
- if((newSS & ~0x07) >= cpustate->ldtr.limit)
+ if((newSS & ~0x07) >= m_ldtr.limit)
{
logerror("IRET: Return SS selector is past LDT limit.\n");
FAULT(FAULT_GP,newSS & ~0x03);
@@ -2584,7 +2663,7 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
}
else
{
- if((newSS & ~0x07) >= cpustate->gdtr.limit)
+ if((newSS & ~0x07) >= m_gdtr.limit)
{
logerror("IRET: Return SS selector is past GDT limit.\n");
FAULT(FAULT_GP,newSS & ~0x03);
@@ -2629,40 +2708,40 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
// IOPL can only change if CPL is zero
if(CPL != 0)
{
- UINT32 oldflags = get_flags(cpustate);
+ UINT32 oldflags = get_flags();
newflags = (newflags & ~0x00003000) | (oldflags & 0x00003000);
}
if(operand32 == 0)
{
- cpustate->eip = newEIP & 0xffff;
- cpustate->sreg[CS].selector = newCS;
- set_flags(cpustate,newflags);
+ m_eip = newEIP & 0xffff;
+ m_sreg[CS].selector = newCS;
+ set_flags(newflags);
REG16(SP) = newESP & 0xffff;
- cpustate->sreg[SS].selector = newSS;
+ m_sreg[SS].selector = newSS;
}
else
{
- cpustate->eip = newEIP;
- cpustate->sreg[CS].selector = newCS & 0xffff;
- set_flags(cpustate,newflags);
+ m_eip = newEIP;
+ m_sreg[CS].selector = newCS & 0xffff;
+ set_flags(newflags);
REG32(ESP) = newESP;
- cpustate->sreg[SS].selector = newSS & 0xffff;
+ m_sreg[SS].selector = newSS & 0xffff;
}
- cpustate->CPL = newCS & 0x03;
- i386_load_segment_descriptor(cpustate,SS);
+ m_CPL = newCS & 0x03;
+ i386_load_segment_descriptor(SS);
/* Check that DS, ES, FS and GS are valid for the new privilege level */
- i386_check_sreg_validity(cpustate,DS);
- i386_check_sreg_validity(cpustate,ES);
- i386_check_sreg_validity(cpustate,FS);
- i386_check_sreg_validity(cpustate,GS);
+ i386_check_sreg_validity(DS);
+ i386_check_sreg_validity(ES);
+ i386_check_sreg_validity(FS);
+ i386_check_sreg_validity(GS);
}
}
}
- i386_load_segment_descriptor(cpustate,CS);
- CHANGE_PC(cpustate,cpustate->eip);
+ i386_load_segment_descriptor(CS);
+ CHANGE_PC(m_eip);
}
#include "cycles.h"
@@ -2670,53 +2749,53 @@ static void i386_protected_mode_iret(i386_state* cpustate, int operand32)
static UINT8 *cycle_table_rm[X86_NUM_CPUS];
static UINT8 *cycle_table_pm[X86_NUM_CPUS];
-#define CYCLES_NUM(x) (cpustate->cycles -= (x))
+#define CYCLES_NUM(x) (m_cycles -= (x))
-INLINE void CYCLES(i386_state *cpustate,int x)
+void i386_device::CYCLES(int x)
{
if (PROTECTED_MODE)
{
- cpustate->cycles -= cpustate->cycle_table_pm[x];
+ m_cycles -= m_cycle_table_pm[x];
}
else
{
- cpustate->cycles -= cpustate->cycle_table_rm[x];
+ m_cycles -= m_cycle_table_rm[x];
}
}
-INLINE void CYCLES_RM(i386_state *cpustate,int modrm, int r, int m)
+void i386_device::CYCLES_RM(int modrm, int r, int m)
{
if (modrm >= 0xc0)
{
if (PROTECTED_MODE)
{
- cpustate->cycles -= cpustate->cycle_table_pm[r];
+ m_cycles -= m_cycle_table_pm[r];
}
else
{
- cpustate->cycles -= cpustate->cycle_table_rm[r];
+ m_cycles -= m_cycle_table_rm[r];
}
}
else
{
if (PROTECTED_MODE)
{
- cpustate->cycles -= cpustate->cycle_table_pm[m];
+ m_cycles -= m_cycle_table_pm[m];
}
else
{
- cpustate->cycles -= cpustate->cycle_table_rm[m];
+ m_cycles -= m_cycle_table_rm[m];
}
}
}
-static void build_cycle_table(running_machine &machine)
+void i386_device::build_cycle_table()
{
int i, j;
for (j=0; j < X86_NUM_CPUS; j++)
{
- cycle_table_rm[j] = auto_alloc_array(machine, UINT8, CYCLES_NUM_OPCODES);
- cycle_table_pm[j] = auto_alloc_array(machine, UINT8, CYCLES_NUM_OPCODES);
+ cycle_table_rm[j] = auto_alloc_array(machine(), UINT8, CYCLES_NUM_OPCODES);
+ cycle_table_pm[j] = auto_alloc_array(machine(), UINT8, CYCLES_NUM_OPCODES);
for (i=0; i < sizeof(x86_cycle_table)/sizeof(X86_CYCLE_TABLE); i++)
{
@@ -2727,39 +2806,31 @@ static void build_cycle_table(running_machine &machine)
}
}
-static void report_invalid_opcode(i386_state *cpustate)
+void i386_device::report_invalid_opcode()
{
#ifndef DEBUG_MISSING_OPCODE
- logerror("i386: Invalid opcode %02X at %08X\n", cpustate->opcode, cpustate->pc - 1);
+ logerror("i386: Invalid opcode %02X at %08X\n", m_opcode, m_pc - 1);
#else
logerror("i386: Invalid opcode");
- for (int a = 0; a < cpustate->opcode_bytes_length; a++)
- logerror(" %02X", cpustate->opcode_bytes[a]);
- logerror(" at %08X\n", cpustate->opcode_pc);
+ for (int a = 0; a < m_opcode_bytes_length; a++)
+ logerror(" %02X", m_opcode_bytes[a]);
+ logerror(" at %08X\n", m_opcode_pc);
#endif
}
-static void report_invalid_modrm(i386_state *cpustate, const char* opcode, UINT8 modrm)
+void i386_device::report_invalid_modrm(const char* opcode, UINT8 modrm)
{
#ifndef DEBUG_MISSING_OPCODE
- logerror("i386: Invalid %s modrm %01X at %08X\n", opcode, modrm, cpustate->pc - 2);
+ logerror("i386: Invalid %s modrm %01X at %08X\n", opcode, modrm, m_pc - 2);
#else
logerror("i386: Invalid %s modrm %01X", opcode, modrm);
- for (int a = 0; a < cpustate->opcode_bytes_length; a++)
- logerror(" %02X", cpustate->opcode_bytes[a]);
- logerror(" at %08X\n", cpustate->opcode_pc);
+ for (int a = 0; a < m_opcode_bytes_length; a++)
+ logerror(" %02X", m_opcode_bytes[a]);
+ logerror(" at %08X\n", m_opcode_pc);
#endif
- i386_trap(cpustate, 6, 0, 0);
+ i386_trap(6, 0, 0);
}
-/* Forward declarations */
-static void I386OP(decode_opcode)(i386_state *cpustate);
-static void I386OP(decode_two_byte)(i386_state *cpustate);
-static void I386OP(decode_three_byte66)(i386_state *cpustate);
-static void I386OP(decode_three_bytef2)(i386_state *cpustate);
-static void I386OP(decode_three_bytef3)(i386_state *cpustate);
-
-
#include "i386ops.c"
#include "i386op16.c"
@@ -2769,70 +2840,70 @@ static void I386OP(decode_three_bytef3)(i386_state *cpustate);
#include "x87ops.c"
#include "i386ops.h"
-static void I386OP(decode_opcode)(i386_state *cpustate)
+void i386_device::i386_decode_opcode()
{
- cpustate->opcode = FETCH(cpustate);
- if( cpustate->operand_size )
- cpustate->opcode_table1_32[cpustate->opcode](cpustate);
+ m_opcode = FETCH();
+ if( m_operand_size )
+ (this->*m_opcode_table1_32[m_opcode])();
else
- cpustate->opcode_table1_16[cpustate->opcode](cpustate);
+ (this->*m_opcode_table1_16[m_opcode])();
}
/* Two-byte opcode prefix */
-static void I386OP(decode_two_byte)(i386_state *cpustate)
+void i386_device::i386_decode_two_byte()
{
- cpustate->opcode = FETCH(cpustate);
- if( cpustate->operand_size )
- cpustate->opcode_table2_32[cpustate->opcode](cpustate);
+ m_opcode = FETCH();
+ if( m_operand_size )
+ (this->*m_opcode_table2_32[m_opcode])();
else
- cpustate->opcode_table2_16[cpustate->opcode](cpustate);
+ (this->*m_opcode_table2_16[m_opcode])();
}
/* Three-byte opcode prefix 66 0f */
-static void I386OP(decode_three_byte66)(i386_state *cpustate)
+void i386_device::i386_decode_three_byte66()
{
- cpustate->opcode = FETCH(cpustate);
- if( cpustate->operand_size )
- cpustate->opcode_table366_32[cpustate->opcode](cpustate);
+ m_opcode = FETCH();
+ if( m_operand_size )
+ (this->*m_opcode_table366_32[m_opcode])();
else
- cpustate->opcode_table366_16[cpustate->opcode](cpustate);
+ (this->*m_opcode_table366_16[m_opcode])();
}
/* Three-byte opcode prefix f2 0f */
-static void I386OP(decode_three_bytef2)(i386_state *cpustate)
+void i386_device::i386_decode_three_bytef2()
{
- cpustate->opcode = FETCH(cpustate);
- if( cpustate->operand_size )
- cpustate->opcode_table3f2_32[cpustate->opcode](cpustate);
+ m_opcode = FETCH();
+ if( m_operand_size )
+ (this->*m_opcode_table3f2_32[m_opcode])();
else
- cpustate->opcode_table3f2_16[cpustate->opcode](cpustate);
+ (this->*m_opcode_table3f2_16[m_opcode])();
}
/* Three-byte opcode prefix f3 0f */
-static void I386OP(decode_three_bytef3)(i386_state *cpustate)
+void i386_device::i386_decode_three_bytef3()
{
- cpustate->opcode = FETCH(cpustate);
- if( cpustate->operand_size )
- cpustate->opcode_table3f3_32[cpustate->opcode](cpustate);
+ m_opcode = FETCH();
+ if( m_operand_size )
+ (this->*m_opcode_table3f3_32[m_opcode])();
else
- cpustate->opcode_table3f3_16[cpustate->opcode](cpustate);
+ (this->*m_opcode_table3f3_16[m_opcode])();
}
/*************************************************************************/
-static UINT8 read8_debug(i386_state *cpustate, UINT32 ea, UINT8 *data)
+UINT8 i386_device::read8_debug(UINT32 ea, UINT8 *data)
{
UINT32 address = ea;
- if(!i386_translate_address(cpustate,TRANSLATE_DEBUG_MASK,&address,NULL))
+ if(!i386_translate_address(TRANSLATE_DEBUG_MASK,&address,NULL))
return 0;
- address &= cpustate->a20_mask;
- *data = cpustate->program->read_byte(address);
+ address &= m_a20_mask;
+ *data = m_program->read_byte(address);
return 1;
}
-static UINT32 i386_get_debug_desc(i386_state *cpustate, I386_SREG *seg)
+UINT32 i386_device::i386_get_debug_desc(I386_SREG *seg)
{
UINT32 base, limit, address;
union { UINT8 b[8]; UINT32 w[2]; } data;
@@ -2841,11 +2912,11 @@ static UINT32 i386_get_debug_desc(i386_state *cpustate, I386_SREG *seg)
if ( seg->selector & 0x4 )
{
- base = cpustate->ldtr.base;
- limit = cpustate->ldtr.limit;
+ base = m_ldtr.base;
+ limit = m_ldtr.limit;
} else {
- base = cpustate->gdtr.base;
- limit = cpustate->gdtr.limit;
+ base = m_gdtr.base;
+ limit = m_gdtr.limit;
}
entry = seg->selector & ~0x7;
@@ -2855,14 +2926,14 @@ static UINT32 i386_get_debug_desc(i386_state *cpustate, I386_SREG *seg)
address = entry + base;
// todo: bigendian
- ret = read8_debug( cpustate, address+0, &data.b[0] );
- ret += read8_debug( cpustate, address+1, &data.b[1] );
- ret += read8_debug( cpustate, address+2, &data.b[2] );
- ret += read8_debug( cpustate, address+3, &data.b[3] );
- ret += read8_debug( cpustate, address+4, &data.b[4] );
- ret += read8_debug( cpustate, address+5, &data.b[5] );
- ret += read8_debug( cpustate, address+6, &data.b[6] );
- ret += read8_debug( cpustate, address+7, &data.b[7] );
+ ret = read8_debug( address+0, &data.b[0] );
+ ret += read8_debug( address+1, &data.b[1] );
+ ret += read8_debug( address+2, &data.b[2] );
+ ret += read8_debug( address+3, &data.b[3] );
+ ret += read8_debug( address+4, &data.b[4] );
+ ret += read8_debug( address+5, &data.b[5] );
+ ret += read8_debug( address+6, &data.b[6] );
+ ret += read8_debug( address+7, &data.b[7] );
if(ret != 8)
return 0;
@@ -2878,10 +2949,8 @@ static UINT32 i386_get_debug_desc(i386_state *cpustate, I386_SREG *seg)
return seg->valid;
}
-static UINT64 i386_debug_segbase(symbol_table &table, void *ref, int params, const UINT64 *param)
+UINT64 i386_device::debug_segbase(symbol_table &table, int params, const UINT64 *param)
{
- legacy_cpu_device *device = (legacy_cpu_device *)ref;
- i386_state *cpustate = get_safe_token(device);
UINT32 result;
I386_SREG seg;
@@ -2892,7 +2961,7 @@ static UINT64 i386_debug_segbase(symbol_table &table, void *ref, int params, con
{
memset(&seg, 0, sizeof(seg));
seg.selector = param[0];
- if(!i386_get_debug_desc(cpustate,&seg))
+ if(!i386_get_debug_desc(&seg))
return 0;
result = seg.base;
}
@@ -2903,10 +2972,8 @@ static UINT64 i386_debug_segbase(symbol_table &table, void *ref, int params, con
return result;
}
-static UINT64 i386_debug_seglimit(symbol_table &table, void *ref, int params, const UINT64 *param)
+UINT64 i386_device::debug_seglimit(symbol_table &table, int params, const UINT64 *param)
{
- legacy_cpu_device *device = (legacy_cpu_device *)ref;
- i386_state *cpustate = get_safe_token(device);
UINT32 result = 0;
I386_SREG seg;
@@ -2914,17 +2981,15 @@ static UINT64 i386_debug_seglimit(symbol_table &table, void *ref, int params, co
{
memset(&seg, 0, sizeof(seg));
seg.selector = param[0];
- if(!i386_get_debug_desc(cpustate,&seg))
+ if(!i386_get_debug_desc(&seg))
return 0;
result = seg.limit;
}
return result;
}
-static UINT64 i386_debug_segofftovirt(symbol_table &table, void *ref, int params, const UINT64 *param)
+UINT64 i386_device::debug_segofftovirt(symbol_table &table, int params, const UINT64 *param)
{
- legacy_cpu_device *device = (legacy_cpu_device *)ref;
- i386_state *cpustate = get_safe_token(device);
UINT32 result = 0;
I386_SREG seg;
@@ -2935,7 +3000,7 @@ static UINT64 i386_debug_segofftovirt(symbol_table &table, void *ref, int params
{
memset(&seg, 0, sizeof(seg));
seg.selector = param[0];
- if(!i386_get_debug_desc(cpustate,&seg))
+ if(!i386_get_debug_desc(&seg))
return 0;
if((seg.flags & 0x0090) != 0x0090) // not system and present
return 0;
@@ -2961,46 +3026,67 @@ static UINT64 i386_debug_segofftovirt(symbol_table &table, void *ref, int params
return result;
}
-static UINT64 i386_debug_virttophys(symbol_table &table, void *ref, int params, const UINT64 *param)
+UINT64 i386_device::debug_virttophys(symbol_table &table, int params, const UINT64 *param)
{
- legacy_cpu_device *device = (legacy_cpu_device *)ref;
- i386_state *cpustate = get_safe_token(device);
UINT32 result = param[0];
- if(!i386_translate_address(cpustate,TRANSLATE_DEBUG_MASK,&result,NULL))
+ if(!i386_translate_address(TRANSLATE_DEBUG_MASK,&result,NULL))
return 0;
return result;
}
-static CPU_DEBUG_INIT( i386 )
+UINT64 i386_debug_segbase(symbol_table &table, void *ref, int params, const UINT64 *param)
+{
+ i386_device *i386 = (i386_device *)(ref);
+ return i386->debug_segbase(table, params, param);
+}
+
+UINT64 i386_debug_seglimit(symbol_table &table, void *ref, int params, const UINT64 *param)
+{
+ i386_device *i386 = (i386_device *)(ref);
+ return i386->debug_seglimit(table, params, param);
+}
+
+UINT64 i386_debug_segofftovirt(symbol_table &table, void *ref, int params, const UINT64 *param)
+{
+ i386_device *i386 = (i386_device *)(ref);
+ return i386->debug_segofftovirt(table, params, param);
+}
+
+static UINT64 i386_debug_virttophys(symbol_table &table, void *ref, int params, const UINT64 *param)
+{
+ i386_device *i386 = (i386_device *)(ref);
+ return i386->debug_virttophys(table, params, param);
+}
+
+void i386_device::device_debug_setup()
{
- device->debug()->symtable().add("segbase", (void *)device, 1, 1, i386_debug_segbase);
- device->debug()->symtable().add("seglimit", (void *)device, 1, 1, i386_debug_seglimit);
- device->debug()->symtable().add("segofftovirt", (void *)device, 2, 2, i386_debug_segofftovirt);
- device->debug()->symtable().add("virttophys", (void *)device, 1, 1, i386_debug_virttophys);
+ debug()->symtable().add("segbase", (void *)this, 1, 1, i386_debug_segbase);
+ debug()->symtable().add("seglimit", (void *)this, 1, 1, i386_debug_seglimit);
+ debug()->symtable().add("segofftovirt", (void *)this, 2, 2, i386_debug_segofftovirt);
+ debug()->symtable().add("virttophys", (void *)this, 1, 1, i386_debug_virttophys);
}
/*************************************************************************/
-static void i386_postload(i386_state *cpustate)
+void i386_device::i386_postload()
{
int i;
for (i = 0; i < 6; i++)
- i386_load_segment_descriptor(cpustate,i);
- CHANGE_PC(cpustate,cpustate->eip);
+ i386_load_segment_descriptor(i);
+ CHANGE_PC(m_eip);
}
-static void i386_common_init(legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, int tlbsize)
+void i386_device::i386_common_init(int tlbsize)
{
int i, j;
static const int regs8[8] = {AL,CL,DL,BL,AH,CH,DH,BH};
static const int regs16[8] = {AX,CX,DX,BX,SP,BP,SI,DI};
static const int regs32[8] = {EAX,ECX,EDX,EBX,ESP,EBP,ESI,EDI};
- i386_state *cpustate = get_safe_token(device);
assert((sizeof(XMM_REG)/sizeof(double)) == 2);
- build_cycle_table(device->machine());
+ build_cycle_table();
for( i=0; i < 256; i++ ) {
int c=0;
@@ -3021,182 +3107,431 @@ static void i386_common_init(legacy_cpu_device *device, device_irq_acknowledge_c
i386_MODRM_table[i].rm.d = regs32[i & 0x7];
}
- cpustate->irq_callback = irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
- cpustate->vtlb = vtlb_alloc(device, AS_PROGRAM, 0, tlbsize);
- cpustate->smi = false;
-
- device->save_item(NAME( cpustate->reg.d));
- device->save_item(NAME(cpustate->sreg[ES].selector));
- device->save_item(NAME(cpustate->sreg[ES].base));
- device->save_item(NAME(cpustate->sreg[ES].limit));
- device->save_item(NAME(cpustate->sreg[ES].flags));
- device->save_item(NAME(cpustate->sreg[CS].selector));
- device->save_item(NAME(cpustate->sreg[CS].base));
- device->save_item(NAME(cpustate->sreg[CS].limit));
- device->save_item(NAME(cpustate->sreg[CS].flags));
- device->save_item(NAME(cpustate->sreg[SS].selector));
- device->save_item(NAME(cpustate->sreg[SS].base));
- device->save_item(NAME(cpustate->sreg[SS].limit));
- device->save_item(NAME(cpustate->sreg[SS].flags));
- device->save_item(NAME(cpustate->sreg[DS].selector));
- device->save_item(NAME(cpustate->sreg[DS].base));
- device->save_item(NAME(cpustate->sreg[DS].limit));
- device->save_item(NAME(cpustate->sreg[DS].flags));
- device->save_item(NAME(cpustate->sreg[FS].selector));
- device->save_item(NAME(cpustate->sreg[FS].base));
- device->save_item(NAME(cpustate->sreg[FS].limit));
- device->save_item(NAME(cpustate->sreg[FS].flags));
- device->save_item(NAME(cpustate->sreg[GS].selector));
- device->save_item(NAME(cpustate->sreg[GS].base));
- device->save_item(NAME(cpustate->sreg[GS].limit));
- device->save_item(NAME(cpustate->sreg[GS].flags));
- device->save_item(NAME(cpustate->eip));
- device->save_item(NAME(cpustate->prev_eip));
- device->save_item(NAME(cpustate->CF));
- device->save_item(NAME(cpustate->DF));
- device->save_item(NAME(cpustate->SF));
- device->save_item(NAME(cpustate->OF));
- device->save_item(NAME(cpustate->ZF));
- device->save_item(NAME(cpustate->PF));
- device->save_item(NAME(cpustate->AF));
- device->save_item(NAME(cpustate->IF));
- device->save_item(NAME(cpustate->TF));
- device->save_item(NAME( cpustate->cr));
- device->save_item(NAME( cpustate->dr));
- device->save_item(NAME( cpustate->tr));
- device->save_item(NAME(cpustate->idtr.base));
- device->save_item(NAME(cpustate->idtr.limit));
- device->save_item(NAME(cpustate->gdtr.base));
- device->save_item(NAME(cpustate->gdtr.limit));
- device->save_item(NAME(cpustate->task.base));
- device->save_item(NAME(cpustate->task.segment));
- device->save_item(NAME(cpustate->task.limit));
- device->save_item(NAME(cpustate->task.flags));
- device->save_item(NAME(cpustate->ldtr.base));
- device->save_item(NAME(cpustate->ldtr.segment));
- device->save_item(NAME(cpustate->ldtr.limit));
- device->save_item(NAME(cpustate->ldtr.flags));
- device->save_item(NAME(cpustate->irq_state));
- device->save_item(NAME(cpustate->performed_intersegment_jump));
- device->save_item(NAME(cpustate->mxcsr));
- device->save_item(NAME(cpustate->smm));
- device->save_item(NAME(cpustate->smi_latched));
- device->save_item(NAME(cpustate->smi));
- device->save_item(NAME(cpustate->nmi_masked));
- device->save_item(NAME(cpustate->nmi_latched));
- device->save_item(NAME(cpustate->smbase));
- device->machine().save().register_postload(save_prepost_delegate(FUNC(i386_postload), cpustate));
-
- i386_interface *intf = (i386_interface *) device->static_config();
-
- if (intf != NULL)
- cpustate->smiact.resolve(intf->smiact, *device);
- else
- memset(&cpustate->smiact, 0, sizeof(cpustate->smiact));
+ m_program = &space(AS_PROGRAM);
+ m_direct = &m_program->direct();
+ m_io = &space(AS_IO);
+ m_vtlb = vtlb_alloc(this, AS_PROGRAM, 0, tlbsize);
+ m_smi = false;
+
+ save_item(NAME( m_reg.d));
+ save_item(NAME(m_sreg[ES].selector));
+ save_item(NAME(m_sreg[ES].base));
+ save_item(NAME(m_sreg[ES].limit));
+ save_item(NAME(m_sreg[ES].flags));
+ save_item(NAME(m_sreg[CS].selector));
+ save_item(NAME(m_sreg[CS].base));
+ save_item(NAME(m_sreg[CS].limit));
+ save_item(NAME(m_sreg[CS].flags));
+ save_item(NAME(m_sreg[SS].selector));
+ save_item(NAME(m_sreg[SS].base));
+ save_item(NAME(m_sreg[SS].limit));
+ save_item(NAME(m_sreg[SS].flags));
+ save_item(NAME(m_sreg[DS].selector));
+ save_item(NAME(m_sreg[DS].base));
+ save_item(NAME(m_sreg[DS].limit));
+ save_item(NAME(m_sreg[DS].flags));
+ save_item(NAME(m_sreg[FS].selector));
+ save_item(NAME(m_sreg[FS].base));
+ save_item(NAME(m_sreg[FS].limit));
+ save_item(NAME(m_sreg[FS].flags));
+ save_item(NAME(m_sreg[GS].selector));
+ save_item(NAME(m_sreg[GS].base));
+ save_item(NAME(m_sreg[GS].limit));
+ save_item(NAME(m_sreg[GS].flags));
+ save_item(NAME(m_eip));
+ save_item(NAME(m_prev_eip));
+ save_item(NAME(m_CF));
+ save_item(NAME(m_DF));
+ save_item(NAME(m_SF));
+ save_item(NAME(m_OF));
+ save_item(NAME(m_ZF));
+ save_item(NAME(m_PF));
+ save_item(NAME(m_AF));
+ save_item(NAME(m_IF));
+ save_item(NAME(m_TF));
+ save_item(NAME( m_cr));
+ save_item(NAME( m_dr));
+ save_item(NAME( m_tr));
+ save_item(NAME(m_idtr.base));
+ save_item(NAME(m_idtr.limit));
+ save_item(NAME(m_gdtr.base));
+ save_item(NAME(m_gdtr.limit));
+ save_item(NAME(m_task.base));
+ save_item(NAME(m_task.segment));
+ save_item(NAME(m_task.limit));
+ save_item(NAME(m_task.flags));
+ save_item(NAME(m_ldtr.base));
+ save_item(NAME(m_ldtr.segment));
+ save_item(NAME(m_ldtr.limit));
+ save_item(NAME(m_ldtr.flags));
+ save_item(NAME(m_irq_state));
+ save_item(NAME(m_performed_intersegment_jump));
+ save_item(NAME(m_mxcsr));
+ save_item(NAME(m_smm));
+ save_item(NAME(m_smi_latched));
+ save_item(NAME(m_smi));
+ save_item(NAME(m_nmi_masked));
+ save_item(NAME(m_nmi_latched));
+ save_item(NAME(m_smbase));
+ machine().save().register_postload(save_prepost_delegate(FUNC(i386_device::i386_postload), this));
+
+ m_smiact.resolve_safe();
+
+ m_icountptr = &m_cycles;
}
-CPU_INIT( i386 )
+void i386_device::device_start()
{
- i386_common_init(device, irqcallback, 32);
+ i386_common_init(32);
+
+ build_opcode_table(OP_I386);
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_I386];
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_I386];
+
+ register_state_i386();
}
-static void build_opcode_table(i386_state *cpustate, UINT32 features)
+void i386_device::register_state_i386()
+{
+ state_add( I386_PC, "PC", m_pc).formatstr("%08X");
+ state_add( I386_EIP, "EIP", m_eip).callimport().formatstr("%08X");
+ state_add( I386_AL, "~AL", REG8(AL)).formatstr("%02X");
+ state_add( I386_AH, "~AH", REG8(AH)).formatstr("%02X");
+ state_add( I386_BL, "~BL", REG8(BL)).formatstr("%02X");
+ state_add( I386_BH, "~BH", REG8(BH)).formatstr("%02X");
+ state_add( I386_CL, "~CL", REG8(CL)).formatstr("%02X");
+ state_add( I386_CH, "~CH", REG8(CH)).formatstr("%02X");
+ state_add( I386_DL, "~DL", REG8(DL)).formatstr("%02X");
+ state_add( I386_DH, "~DH", REG8(DH)).formatstr("%02X");
+ state_add( I386_AX, "~AX", REG16(AX)).formatstr("%04X");
+ state_add( I386_BX, "~BX", REG16(BX)).formatstr("%04X");
+ state_add( I386_CX, "~CX", REG16(CX)).formatstr("%04X");
+ state_add( I386_DX, "~DX", REG16(DX)).formatstr("%04X");
+ state_add( I386_SI, "~SI", REG16(SI)).formatstr("%04X");
+ state_add( I386_DI, "~DI", REG16(DI)).formatstr("%04X");
+ state_add( I386_BP, "~BP", REG16(BP)).formatstr("%04X");
+ state_add( I386_SP, "~SP", REG16(SP)).formatstr("%04X");
+ state_add( I386_IP, "~IP", m_debugger_temp).mask(0xffff).callimport().callexport().formatstr("%04X");
+ state_add( I386_EAX, "EAX", m_reg.d[EAX]).formatstr("%08X");
+ state_add( I386_EBX, "EBX", m_reg.d[EBX]).formatstr("%08X");
+ state_add( I386_ECX, "ECX", m_reg.d[ECX]).formatstr("%08X");
+ state_add( I386_EDX, "EDX", m_reg.d[EDX]).formatstr("%08X");
+ state_add( I386_EBP, "EBP", m_reg.d[EBP]).formatstr("%08X");
+ state_add( I386_ESP, "ESP", m_reg.d[ESP]).formatstr("%08X");
+ state_add( I386_ESI, "ESI", m_reg.d[ESI]).formatstr("%08X");
+ state_add( I386_EDI, "EDI", m_reg.d[EDI]).formatstr("%08X");
+ state_add( I386_EFLAGS, "EFLAGS", m_eflags).formatstr("%08X");
+ state_add( I386_CS, "CS", m_sreg[CS].selector).callimport().formatstr("%04X");
+ state_add( I386_CS_BASE, "CSBASE", m_sreg[CS].base).formatstr("%08X");
+ state_add( I386_CS_LIMIT, "CSLIMIT", m_sreg[CS].limit).formatstr("%08X");
+ state_add( I386_CS_FLAGS, "CSFLAGS", m_sreg[CS].flags).mask(0xf0ff).formatstr("%04X");
+ state_add( I386_SS, "SS", m_sreg[SS].selector).callimport().formatstr("%04X");
+ state_add( I386_SS_BASE, "SSBASE", m_sreg[SS].base).formatstr("%08X");
+ state_add( I386_SS_LIMIT, "SSLIMIT", m_sreg[SS].limit).formatstr("%08X");
+ state_add( I386_SS_FLAGS, "SSFLAGS", m_sreg[SS].flags).mask(0xf0ff).formatstr("%04X");
+ state_add( I386_DS, "DS", m_sreg[DS].selector).callimport().formatstr("%04X");
+ state_add( I386_DS_BASE, "DSBASE", m_sreg[DS].base).formatstr("%08X");
+ state_add( I386_DS_LIMIT, "DSLIMIT", m_sreg[DS].limit).formatstr("%08X");
+ state_add( I386_DS_FLAGS, "DSFLAGS", m_sreg[DS].flags).mask(0xf0ff).formatstr("%04X");
+ state_add( I386_ES, "ES", m_sreg[ES].selector).callimport().formatstr("%04X");
+ state_add( I386_ES_BASE, "ESBASE", m_sreg[ES].base).formatstr("%08X");
+ state_add( I386_ES_LIMIT, "ESLIMIT", m_sreg[ES].limit).formatstr("%08X");
+ state_add( I386_ES_FLAGS, "ESFLAGS", m_sreg[ES].flags).mask(0xf0ff).formatstr("%04X");
+ state_add( I386_FS, "FS", m_sreg[FS].selector).callimport().formatstr("%04X");
+ state_add( I386_FS_BASE, "FSBASE", m_sreg[FS].base).formatstr("%08X");
+ state_add( I386_FS_LIMIT, "FSLIMIT", m_sreg[FS].limit).formatstr("%08X");
+ state_add( I386_FS_FLAGS, "FSFLAGS", m_sreg[FS].flags).mask(0xf0ff).formatstr("%04X");
+ state_add( I386_GS, "GS", m_sreg[GS].selector).callimport().formatstr("%04X");
+ state_add( I386_GS_BASE, "GSBASE", m_sreg[GS].base).formatstr("%08X");
+ state_add( I386_GS_LIMIT, "GSLIMIT", m_sreg[GS].limit).formatstr("%08X");
+ state_add( I386_GS_FLAGS, "GSFLAGS", m_sreg[GS].flags).mask(0xf0ff).formatstr("%04X");
+ state_add( I386_CR0, "CR0", m_cr[0]).formatstr("%08X");
+ state_add( I386_CR1, "CR1", m_cr[1]).formatstr("%08X");
+ state_add( I386_CR2, "CR2", m_cr[2]).formatstr("%08X");
+ state_add( I386_CR3, "CR3", m_cr[3]).formatstr("%08X");
+ state_add( I386_CR4, "CR4", m_cr[4]).formatstr("%08X");
+ state_add( I386_DR0, "DR0", m_dr[0]).formatstr("%08X");
+ state_add( I386_DR1, "DR1", m_dr[1]).formatstr("%08X");
+ state_add( I386_DR2, "DR2", m_dr[2]).formatstr("%08X");
+ state_add( I386_DR3, "DR3", m_dr[3]).formatstr("%08X");
+ state_add( I386_DR4, "DR4", m_dr[4]).formatstr("%08X");
+ state_add( I386_DR5, "DR5", m_dr[5]).formatstr("%08X");
+ state_add( I386_DR6, "DR6", m_dr[6]).formatstr("%08X");
+ state_add( I386_DR7, "DR7", m_dr[7]).formatstr("%08X");
+ state_add( I386_TR6, "TR6", m_tr[6]).formatstr("%08X");
+ state_add( I386_TR7, "TR7", m_tr[7]).formatstr("%08X");
+ state_add( I386_GDTR_BASE, "GDTRBASE", m_gdtr.base).formatstr("%08X");
+ state_add( I386_GDTR_LIMIT, "GDTRLIMIT", m_gdtr.limit).formatstr("%04X");
+ state_add( I386_IDTR_BASE, "IDTRBASE", m_idtr.base).formatstr("%08X");
+ state_add( I386_IDTR_LIMIT, "IDTRLIMIT", m_idtr.limit).formatstr("%04X");
+ state_add( I386_LDTR, "LDTR", m_ldtr.segment).formatstr("%04X");
+ state_add( I386_LDTR_BASE, "LDTRBASE", m_ldtr.base).formatstr("%08X");
+ state_add( I386_LDTR_LIMIT, "LDTRLIMIT", m_ldtr.limit).formatstr("%08X");
+ state_add( I386_LDTR_FLAGS, "LDTRFLAGS", m_ldtr.flags).mask(0xf0ff).formatstr("%04X");
+ state_add( I386_TR, "TR", m_task.segment).formatstr("%04X");
+ state_add( I386_TR_BASE, "TRBASE", m_task.base).formatstr("%08X");
+ state_add( I386_TR_LIMIT, "TRLIMIT", m_task.limit).formatstr("%08X");
+ state_add( I386_TR_FLAGS, "TRFLAGS", m_task.flags).mask(0xf0ff).formatstr("%04X");
+ state_add( I386_CPL, "CPL", m_CPL).formatstr("%01X");
+
+ state_add( STATE_GENPC, "GENPC", m_pc).noshow();
+ state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_temp).formatstr("%8s").noshow();
+ state_add( STATE_GENSP, "GENSP", REG32(ESP)).noshow();
+}
+
+void i386_device::register_state_i386_x87()
+{
+ register_state_i386();
+
+ state_add( X87_CTRL, "x87_CW", m_x87_cw).formatstr("%04X");
+ state_add( X87_STATUS, "x87_SW", m_x87_sw).formatstr("%04X");
+ state_add( X87_TAG, "x87_TAG", m_x87_tw).formatstr("%04X");
+ state_add( X87_ST0, "ST0", m_debugger_temp ).formatstr("%15s");
+ state_add( X87_ST1, "ST1", m_debugger_temp ).formatstr("%15s");
+ state_add( X87_ST2, "ST2", m_debugger_temp ).formatstr("%15s");
+ state_add( X87_ST3, "ST3", m_debugger_temp ).formatstr("%15s");
+ state_add( X87_ST4, "ST4", m_debugger_temp ).formatstr("%15s");
+ state_add( X87_ST5, "ST5", m_debugger_temp ).formatstr("%15s");
+ state_add( X87_ST6, "ST6", m_debugger_temp ).formatstr("%15s");
+ state_add( X87_ST7, "ST7", m_debugger_temp ).formatstr("%15s");
+}
+
+void i386_device::state_import(const device_state_entry &entry)
+{
+ switch (entry.index())
+ {
+ case I386_EIP:
+ CHANGE_PC(m_eip);
+ break;
+ case I386_IP:
+ m_eip = ( m_eip & ~0xffff ) | ( m_debugger_temp & 0xffff);
+ CHANGE_PC(m_eip);
+ break;
+ case I386_CS:
+ i386_load_segment_descriptor(CS);
+ break;
+ case I386_SS:
+ i386_load_segment_descriptor(SS);
+ break;
+ case I386_DS:
+ i386_load_segment_descriptor(DS);
+ break;
+ case I386_ES:
+ i386_load_segment_descriptor(ES);
+ break;
+ case I386_FS:
+ i386_load_segment_descriptor(FS);
+ break;
+ case I386_GS:
+ i386_load_segment_descriptor(GS);
+ break;
+ }
+}
+
+void i386_device::state_export(const device_state_entry &entry)
+{
+ switch (entry.index())
+ {
+ case I386_IP:
+ m_debugger_temp = m_eip & 0xffff;
+ break;
+ }
+}
+
+void i386_device::state_string_export(const device_state_entry &entry, astring &string)
+{
+ switch (entry.index())
+ {
+ case STATE_GENFLAGS:
+ string.printf("%08X", get_flags());
+ break;
+ case X87_ST0:
+ string.printf("%f", fx80_to_double(ST(0)));
+ break;
+ case X87_ST1:
+ string.printf("%f", fx80_to_double(ST(1)));
+ break;
+ case X87_ST2:
+ string.printf("%f", fx80_to_double(ST(2)));
+ break;
+ case X87_ST3:
+ string.printf("%f", fx80_to_double(ST(3)));
+ break;
+ case X87_ST4:
+ string.printf("%f", fx80_to_double(ST(4)));
+ break;
+ case X87_ST5:
+ string.printf("%f", fx80_to_double(ST(5)));
+ break;
+ case X87_ST6:
+ string.printf("%f", fx80_to_double(ST(6)));
+ break;
+ case X87_ST7:
+ string.printf("%f", fx80_to_double(ST(7)));
+ break;
+ }
+}
+
+void i386_device::build_opcode_table(UINT32 features)
{
int i;
for (i=0; i < 256; i++)
{
- cpustate->opcode_table1_16[i] = I386OP(invalid);
- cpustate->opcode_table1_32[i] = I386OP(invalid);
- cpustate->opcode_table2_16[i] = I386OP(invalid);
- cpustate->opcode_table2_32[i] = I386OP(invalid);
- cpustate->opcode_table366_16[i] = I386OP(invalid);
- cpustate->opcode_table366_32[i] = I386OP(invalid);
- cpustate->opcode_table3f2_16[i] = I386OP(invalid);
- cpustate->opcode_table3f2_32[i] = I386OP(invalid);
- cpustate->opcode_table3f3_16[i] = I386OP(invalid);
- cpustate->opcode_table3f3_32[i] = I386OP(invalid);
+ m_opcode_table1_16[i] = &i386_device::i386_invalid;
+ m_opcode_table1_32[i] = &i386_device::i386_invalid;
+ m_opcode_table2_16[i] = &i386_device::i386_invalid;
+ m_opcode_table2_32[i] = &i386_device::i386_invalid;
+ m_opcode_table366_16[i] = &i386_device::i386_invalid;
+ m_opcode_table366_32[i] = &i386_device::i386_invalid;
+ m_opcode_table3f2_16[i] = &i386_device::i386_invalid;
+ m_opcode_table3f2_32[i] = &i386_device::i386_invalid;
+ m_opcode_table3f3_16[i] = &i386_device::i386_invalid;
+ m_opcode_table3f3_32[i] = &i386_device::i386_invalid;
}
- for (i=0; i < sizeof(x86_opcode_table)/sizeof(X86_OPCODE); i++)
+ for (i=0; i < sizeof(s_x86_opcode_table)/sizeof(X86_OPCODE); i++)
{
- const X86_OPCODE *op = &x86_opcode_table[i];
+ const X86_OPCODE *op = &s_x86_opcode_table[i];
if ((op->flags & features))
{
if (op->flags & OP_2BYTE)
{
- cpustate->opcode_table2_32[op->opcode] = op->handler32;
- cpustate->opcode_table2_16[op->opcode] = op->handler16;
- cpustate->opcode_table366_32[op->opcode] = op->handler32;
- cpustate->opcode_table366_16[op->opcode] = op->handler16;
+ m_opcode_table2_32[op->opcode] = op->handler32;
+ m_opcode_table2_16[op->opcode] = op->handler16;
+ m_opcode_table366_32[op->opcode] = op->handler32;
+ m_opcode_table366_16[op->opcode] = op->handler16;
}
else if (op->flags & OP_3BYTE66)
{
- cpustate->opcode_table366_32[op->opcode] = op->handler32;
- cpustate->opcode_table366_16[op->opcode] = op->handler16;
+ m_opcode_table366_32[op->opcode] = op->handler32;
+ m_opcode_table366_16[op->opcode] = op->handler16;
}
else if (op->flags & OP_3BYTEF2)
{
- cpustate->opcode_table3f2_32[op->opcode] = op->handler32;
- cpustate->opcode_table3f2_16[op->opcode] = op->handler16;
+ m_opcode_table3f2_32[op->opcode] = op->handler32;
+ m_opcode_table3f2_16[op->opcode] = op->handler16;
}
else if (op->flags & OP_3BYTEF3)
{
- cpustate->opcode_table3f3_32[op->opcode] = op->handler32;
- cpustate->opcode_table3f3_16[op->opcode] = op->handler16;
+ m_opcode_table3f3_32[op->opcode] = op->handler32;
+ m_opcode_table3f3_16[op->opcode] = op->handler16;
}
else
{
- cpustate->opcode_table1_32[op->opcode] = op->handler32;
- cpustate->opcode_table1_16[op->opcode] = op->handler16;
+ m_opcode_table1_32[op->opcode] = op->handler32;
+ m_opcode_table1_16[op->opcode] = op->handler16;
}
}
}
}
-static CPU_RESET( i386 )
+void i386_device::zero_state()
{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].valid = true;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
- cpustate->sreg[DS].valid = cpustate->sreg[ES].valid = cpustate->sreg[FS].valid = cpustate->sreg[GS].valid = cpustate->sreg[SS].valid =true;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x7fffffe0; // reserved bits set to 1
- cpustate->eflags = 0;
- cpustate->eflags_mask = 0x00037fd7;
- cpustate->eip = 0xfff0;
+ memset( &m_reg, 0, sizeof(m_reg) );
+ memset( m_sreg, 0, sizeof(m_sreg) );
+ m_eip = 0;
+ m_pc = 0;
+ m_prev_eip = 0;
+ m_eflags = 0;
+ m_eflags_mask = 0;
+ m_CF = 0;
+ m_DF = 0;
+ m_SF = 0;
+ m_OF = 0;
+ m_ZF = 0;
+ m_PF = 0;
+ m_AF = 0;
+ m_IF = 0;
+ m_TF = 0;
+ m_IOP1 = 0;
+ m_IOP2 = 0;
+ m_NT = 0;
+ m_RF = 0;
+ m_VM = 0;
+ m_AC = 0;
+ m_VIF = 0;
+ m_VIP = 0;
+ m_ID = 0;
+ m_CPL = 0;
+ m_performed_intersegment_jump = 0;
+ m_delayed_interrupt_enable = 0;
+ memset( m_cr, 0, sizeof(m_cr) );
+ memset( m_dr, 0, sizeof(m_dr) );
+ memset( m_tr, 0, sizeof(m_tr) );
+ memset( &m_gdtr, 0, sizeof(m_gdtr) );
+ memset( &m_idtr, 0, sizeof(m_idtr) );
+ memset( &m_task, 0, sizeof(m_task) );
+ memset( &m_ldtr, 0, sizeof(m_ldtr) );
+ m_ext = 0;
+ m_halted = 0;
+ m_operand_size = 0;
+ m_address_size = 0;
+ m_operand_prefix = 0;
+ m_address_prefix = 0;
+ m_segment_prefix = 0;
+ m_segment_override = 0;
+ m_cycles = 0;
+ m_base_cycles = 0;
+ m_opcode = 0;
+ m_irq_state = 0;
+ m_a20_mask = 0;
+ m_cpuid_max_input_value_eax = 0;
+ m_cpuid_id0 = 0;
+ m_cpuid_id1 = 0;
+ m_cpuid_id2 = 0;
+ m_cpu_version = 0;
+ m_feature_flags = 0;
+ m_tsc = 0;
+ m_perfctr[0] = m_perfctr[1] = 0;
+ memset( m_x87_reg, 0, sizeof(m_x87_reg) );
+ m_x87_cw = 0;
+ m_x87_sw = 0;
+ m_x87_tw = 0;
+ m_x87_data_ptr = 0;
+ m_x87_inst_ptr = 0;
+ m_x87_opcode = 0;
+ memset( m_sse_reg, 0, sizeof(m_sse_reg) );
+ m_mxcsr = 0;
+ m_smm = false;
+ m_smi = false;
+ m_smi_latched = false;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+ m_smbase = 0;
+ memset( m_opcode_bytes, 0, sizeof(m_opcode_bytes) );
+ m_opcode_pc = 0;
+ m_opcode_bytes_length = 0;
+}
+
+void i386_device::device_reset()
+{
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
+
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].valid = true;
+
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
+ m_sreg[DS].valid = m_sreg[ES].valid = m_sreg[FS].valid = m_sreg[GS].valid = m_sreg[SS].valid =true;
+
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
+ m_smm = false;
+ m_smi_latched = false;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ m_a20_mask = ~0;
+
+ m_cr[0] = 0x7fffffe0; // reserved bits set to 1
+ m_eflags = 0;
+ m_eflags_mask = 0x00037fd7;
+ m_eip = 0xfff0;
// [11:8] Family
// [ 7:4] Model
@@ -3205,602 +3540,287 @@ static CPU_RESET( i386 )
REG32(EAX) = 0;
REG32(EDX) = (3 << 8) | (0 << 4) | (8);
- cpustate->CPL = 0;
-
- build_opcode_table(cpustate, OP_I386);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I386];
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I386];
+ m_CPL = 0;
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static void pentium_smi(i386_state *cpustate)
+void i386_device::pentium_smi()
{
- UINT32 smram_state = cpustate->smbase + 0xfe00;
- UINT32 old_cr0 = cpustate->cr[0];
- UINT32 old_flags = get_flags(cpustate);
+ UINT32 smram_state = m_smbase + 0xfe00;
+ UINT32 old_cr0 = m_cr[0];
+ UINT32 old_flags = get_flags();
- if(cpustate->smm)
+ if(m_smm)
return;
- cpustate->cr[0] &= ~(0x8000000d);
- set_flags(cpustate, 2);
- if(!cpustate->smiact.isnull())
- cpustate->smiact(true);
- cpustate->smm = true;
- cpustate->smi_latched = false;
+ m_cr[0] &= ~(0x8000000d);
+ set_flags(2);
+ if(!m_smiact.isnull())
+ m_smiact(true);
+ m_smm = true;
+ m_smi_latched = false;
// save state
- WRITE32(cpustate, cpustate->cr[4], smram_state+SMRAM_IP5_CR4);
- WRITE32(cpustate, cpustate->sreg[ES].limit, smram_state+SMRAM_IP5_ESLIM);
- WRITE32(cpustate, cpustate->sreg[ES].base, smram_state+SMRAM_IP5_ESBASE);
- WRITE32(cpustate, cpustate->sreg[ES].flags, smram_state+SMRAM_IP5_ESACC);
- WRITE32(cpustate, cpustate->sreg[CS].limit, smram_state+SMRAM_IP5_CSLIM);
- WRITE32(cpustate, cpustate->sreg[CS].base, smram_state+SMRAM_IP5_CSBASE);
- WRITE32(cpustate, cpustate->sreg[CS].flags, smram_state+SMRAM_IP5_CSACC);
- WRITE32(cpustate, cpustate->sreg[SS].limit, smram_state+SMRAM_IP5_SSLIM);
- WRITE32(cpustate, cpustate->sreg[SS].base, smram_state+SMRAM_IP5_SSBASE);
- WRITE32(cpustate, cpustate->sreg[SS].flags, smram_state+SMRAM_IP5_SSACC);
- WRITE32(cpustate, cpustate->sreg[DS].limit, smram_state+SMRAM_IP5_DSLIM);
- WRITE32(cpustate, cpustate->sreg[DS].base, smram_state+SMRAM_IP5_DSBASE);
- WRITE32(cpustate, cpustate->sreg[DS].flags, smram_state+SMRAM_IP5_DSACC);
- WRITE32(cpustate, cpustate->sreg[FS].limit, smram_state+SMRAM_IP5_FSLIM);
- WRITE32(cpustate, cpustate->sreg[FS].base, smram_state+SMRAM_IP5_FSBASE);
- WRITE32(cpustate, cpustate->sreg[FS].flags, smram_state+SMRAM_IP5_FSACC);
- WRITE32(cpustate, cpustate->sreg[GS].limit, smram_state+SMRAM_IP5_GSLIM);
- WRITE32(cpustate, cpustate->sreg[GS].base, smram_state+SMRAM_IP5_GSBASE);
- WRITE32(cpustate, cpustate->sreg[GS].flags, smram_state+SMRAM_IP5_GSACC);
- WRITE32(cpustate, cpustate->ldtr.flags, smram_state+SMRAM_IP5_LDTACC);
- WRITE32(cpustate, cpustate->ldtr.limit, smram_state+SMRAM_IP5_LDTLIM);
- WRITE32(cpustate, cpustate->ldtr.base, smram_state+SMRAM_IP5_LDTBASE);
- WRITE32(cpustate, cpustate->gdtr.limit, smram_state+SMRAM_IP5_GDTLIM);
- WRITE32(cpustate, cpustate->gdtr.base, smram_state+SMRAM_IP5_GDTBASE);
- WRITE32(cpustate, cpustate->idtr.limit, smram_state+SMRAM_IP5_IDTLIM);
- WRITE32(cpustate, cpustate->idtr.base, smram_state+SMRAM_IP5_IDTBASE);
- WRITE32(cpustate, cpustate->task.limit, smram_state+SMRAM_IP5_TRLIM);
- WRITE32(cpustate, cpustate->task.base, smram_state+SMRAM_IP5_TRBASE);
- WRITE32(cpustate, cpustate->task.flags, smram_state+SMRAM_IP5_TRACC);
-
- WRITE32(cpustate, cpustate->sreg[ES].selector, smram_state+SMRAM_ES);
- WRITE32(cpustate, cpustate->sreg[CS].selector, smram_state+SMRAM_CS);
- WRITE32(cpustate, cpustate->sreg[SS].selector, smram_state+SMRAM_SS);
- WRITE32(cpustate, cpustate->sreg[DS].selector, smram_state+SMRAM_DS);
- WRITE32(cpustate, cpustate->sreg[FS].selector, smram_state+SMRAM_FS);
- WRITE32(cpustate, cpustate->sreg[GS].selector, smram_state+SMRAM_GS);
- WRITE32(cpustate, cpustate->ldtr.segment, smram_state+SMRAM_LDTR);
- WRITE32(cpustate, cpustate->task.segment, smram_state+SMRAM_TR);
-
- WRITE32(cpustate, cpustate->dr[7], smram_state+SMRAM_DR7);
- WRITE32(cpustate, cpustate->dr[6], smram_state+SMRAM_DR6);
- WRITE32(cpustate, REG32(EAX), smram_state+SMRAM_EAX);
- WRITE32(cpustate, REG32(ECX), smram_state+SMRAM_ECX);
- WRITE32(cpustate, REG32(EDX), smram_state+SMRAM_EDX);
- WRITE32(cpustate, REG32(EBX), smram_state+SMRAM_EBX);
- WRITE32(cpustate, REG32(ESP), smram_state+SMRAM_ESP);
- WRITE32(cpustate, REG32(EBP), smram_state+SMRAM_EBP);
- WRITE32(cpustate, REG32(ESI), smram_state+SMRAM_ESI);
- WRITE32(cpustate, REG32(EDI), smram_state+SMRAM_EDI);
- WRITE32(cpustate, cpustate->eip, smram_state+SMRAM_EIP);
- WRITE32(cpustate, old_flags, smram_state+SMRAM_EAX);
- WRITE32(cpustate, cpustate->cr[3], smram_state+SMRAM_CR3);
- WRITE32(cpustate, old_cr0, smram_state+SMRAM_CR0);
-
- cpustate->sreg[DS].selector = cpustate->sreg[ES].selector = cpustate->sreg[FS].selector = cpustate->sreg[GS].selector = cpustate->sreg[SS].selector = 0;
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffffffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x8093;
- cpustate->sreg[DS].valid = cpustate->sreg[ES].valid = cpustate->sreg[FS].valid = cpustate->sreg[GS].valid = cpustate->sreg[SS].valid =true;
- cpustate->sreg[CS].selector = 0x3000; // pentium only, ppro sel = smbase >> 4
- cpustate->sreg[CS].base = cpustate->smbase;
- cpustate->sreg[CS].limit = 0xffffffff;
- cpustate->sreg[CS].flags = 0x809b;
- cpustate->sreg[CS].valid = true;
- cpustate->cr[4] = 0;
- cpustate->dr[7] = 0x400;
- cpustate->eip = 0x8000;
-
- cpustate->nmi_masked = true;
- CHANGE_PC(cpustate,cpustate->eip);
+ WRITE32(m_cr[4], smram_state+SMRAM_IP5_CR4);
+ WRITE32(m_sreg[ES].limit, smram_state+SMRAM_IP5_ESLIM);
+ WRITE32(m_sreg[ES].base, smram_state+SMRAM_IP5_ESBASE);
+ WRITE32(m_sreg[ES].flags, smram_state+SMRAM_IP5_ESACC);
+ WRITE32(m_sreg[CS].limit, smram_state+SMRAM_IP5_CSLIM);
+ WRITE32(m_sreg[CS].base, smram_state+SMRAM_IP5_CSBASE);
+ WRITE32(m_sreg[CS].flags, smram_state+SMRAM_IP5_CSACC);
+ WRITE32(m_sreg[SS].limit, smram_state+SMRAM_IP5_SSLIM);
+ WRITE32(m_sreg[SS].base, smram_state+SMRAM_IP5_SSBASE);
+ WRITE32(m_sreg[SS].flags, smram_state+SMRAM_IP5_SSACC);
+ WRITE32(m_sreg[DS].limit, smram_state+SMRAM_IP5_DSLIM);
+ WRITE32(m_sreg[DS].base, smram_state+SMRAM_IP5_DSBASE);
+ WRITE32(m_sreg[DS].flags, smram_state+SMRAM_IP5_DSACC);
+ WRITE32(m_sreg[FS].limit, smram_state+SMRAM_IP5_FSLIM);
+ WRITE32(m_sreg[FS].base, smram_state+SMRAM_IP5_FSBASE);
+ WRITE32(m_sreg[FS].flags, smram_state+SMRAM_IP5_FSACC);
+ WRITE32(m_sreg[GS].limit, smram_state+SMRAM_IP5_GSLIM);
+ WRITE32(m_sreg[GS].base, smram_state+SMRAM_IP5_GSBASE);
+ WRITE32(m_sreg[GS].flags, smram_state+SMRAM_IP5_GSACC);
+ WRITE32(m_ldtr.flags, smram_state+SMRAM_IP5_LDTACC);
+ WRITE32(m_ldtr.limit, smram_state+SMRAM_IP5_LDTLIM);
+ WRITE32(m_ldtr.base, smram_state+SMRAM_IP5_LDTBASE);
+ WRITE32(m_gdtr.limit, smram_state+SMRAM_IP5_GDTLIM);
+ WRITE32(m_gdtr.base, smram_state+SMRAM_IP5_GDTBASE);
+ WRITE32(m_idtr.limit, smram_state+SMRAM_IP5_IDTLIM);
+ WRITE32(m_idtr.base, smram_state+SMRAM_IP5_IDTBASE);
+ WRITE32(m_task.limit, smram_state+SMRAM_IP5_TRLIM);
+ WRITE32(m_task.base, smram_state+SMRAM_IP5_TRBASE);
+ WRITE32(m_task.flags, smram_state+SMRAM_IP5_TRACC);
+
+ WRITE32(m_sreg[ES].selector, smram_state+SMRAM_ES);
+ WRITE32(m_sreg[CS].selector, smram_state+SMRAM_CS);
+ WRITE32(m_sreg[SS].selector, smram_state+SMRAM_SS);
+ WRITE32(m_sreg[DS].selector, smram_state+SMRAM_DS);
+ WRITE32(m_sreg[FS].selector, smram_state+SMRAM_FS);
+ WRITE32(m_sreg[GS].selector, smram_state+SMRAM_GS);
+ WRITE32(m_ldtr.segment, smram_state+SMRAM_LDTR);
+ WRITE32(m_task.segment, smram_state+SMRAM_TR);
+
+ WRITE32(m_dr[7], smram_state+SMRAM_DR7);
+ WRITE32(m_dr[6], smram_state+SMRAM_DR6);
+ WRITE32(REG32(EAX), smram_state+SMRAM_EAX);
+ WRITE32(REG32(ECX), smram_state+SMRAM_ECX);
+ WRITE32(REG32(EDX), smram_state+SMRAM_EDX);
+ WRITE32(REG32(EBX), smram_state+SMRAM_EBX);
+ WRITE32(REG32(ESP), smram_state+SMRAM_ESP);
+ WRITE32(REG32(EBP), smram_state+SMRAM_EBP);
+ WRITE32(REG32(ESI), smram_state+SMRAM_ESI);
+ WRITE32(REG32(EDI), smram_state+SMRAM_EDI);
+ WRITE32(m_eip, smram_state+SMRAM_EIP);
+ WRITE32(old_flags, smram_state+SMRAM_EAX);
+ WRITE32(m_cr[3], smram_state+SMRAM_CR3);
+ WRITE32(old_cr0, smram_state+SMRAM_CR0);
+
+ m_sreg[DS].selector = m_sreg[ES].selector = m_sreg[FS].selector = m_sreg[GS].selector = m_sreg[SS].selector = 0;
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffffffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x8093;
+ m_sreg[DS].valid = m_sreg[ES].valid = m_sreg[FS].valid = m_sreg[GS].valid = m_sreg[SS].valid =true;
+ m_sreg[CS].selector = 0x3000; // pentium only, ppro sel = smbase >> 4
+ m_sreg[CS].base = m_smbase;
+ m_sreg[CS].limit = 0xffffffff;
+ m_sreg[CS].flags = 0x809b;
+ m_sreg[CS].valid = true;
+ m_cr[4] = 0;
+ m_dr[7] = 0x400;
+ m_eip = 0x8000;
+
+ m_nmi_masked = true;
+ CHANGE_PC(m_eip);
}
-static void i386_set_irq_line(i386_state *cpustate,int irqline, int state)
+void i386_device::execute_set_input(int irqline, int state)
{
- if (state != CLEAR_LINE && cpustate->halted)
+ if ( irqline == INPUT_LINE_A20 )
{
- cpustate->halted = 0;
+ i386_set_a20_line( state );
+ return;
}
-
if ( irqline == INPUT_LINE_NMI )
{
+ if ( state != CLEAR_LINE && m_halted)
+ {
+ m_halted = 0;
+ }
+
/* NMI (I do not think that this is 100% right) */
- if(cpustate->nmi_masked)
+ if(m_nmi_masked)
{
- cpustate->nmi_latched = true;
+ m_nmi_latched = true;
return;
}
if ( state )
- i386_trap(cpustate,2, 1, 0);
+ i386_trap(2, 1, 0);
}
else
{
- cpustate->irq_state = state;
+ if (irqline >= 0 && irqline <= MAX_INPUT_LINES)
+ {
+ if ( state != CLEAR_LINE && m_halted )
+ {
+ m_halted = 0;
+ }
+
+ m_irq_state = state;
+ }
}
}
-static void i386_set_a20_line(i386_state *cpustate,int state)
+void pentium_device::execute_set_input(int irqline, int state)
+{
+ if ( irqline == INPUT_LINE_SMI )
+ {
+ if ( !m_smi && state && m_smm )
+ {
+ m_smi_latched = true;
+ }
+ m_smi = state;
+ }
+ else
+ {
+ i386_device::execute_set_input(irqline, state);
+ }
+}
+
+void i386_device::i386_set_a20_line(int state)
{
if (state)
{
- cpustate->a20_mask = ~0;
+ m_a20_mask = ~0;
}
else
{
- cpustate->a20_mask = ~(1 << 20);
+ m_a20_mask = ~(1 << 20);
}
// TODO: how does A20M and the tlb interact
- vtlb_flush_dynamic(cpustate->vtlb);
+ vtlb_flush_dynamic(m_vtlb);
}
-static CPU_EXECUTE( i386 )
+void i386_device::execute_run()
{
- i386_state *cpustate = get_safe_token(device);
-
- int cycles = cpustate->cycles;
- cpustate->base_cycles = cycles;
- CHANGE_PC(cpustate,cpustate->eip);
+ int cycles = m_cycles;
+ m_base_cycles = cycles;
+ CHANGE_PC(m_eip);
- if (cpustate->halted)
+ if (m_halted)
{
- cpustate->tsc += cycles;
- cpustate->cycles = 0;
+ m_tsc += cycles;
+ m_cycles = 0;
return;
}
- while( cpustate->cycles > 0 )
+ while( m_cycles > 0 )
{
- i386_check_irq_line(cpustate);
- cpustate->operand_size = cpustate->sreg[CS].d;
- cpustate->address_size = cpustate->sreg[CS].d;
- cpustate->operand_prefix = 0;
- cpustate->address_prefix = 0;
+ i386_check_irq_line();
+ m_operand_size = m_sreg[CS].d;
+ m_address_size = m_sreg[CS].d;
+ m_operand_prefix = 0;
+ m_address_prefix = 0;
- cpustate->ext = 1;
- int old_tf = cpustate->TF;
+ m_ext = 1;
+ int old_tf = m_TF;
- cpustate->segment_prefix = 0;
- cpustate->prev_eip = cpustate->eip;
+ m_segment_prefix = 0;
+ m_prev_eip = m_eip;
- debugger_instruction_hook(device, cpustate->pc);
+ debugger_instruction_hook(this, m_pc);
- if(cpustate->delayed_interrupt_enable != 0)
+ if(m_delayed_interrupt_enable != 0)
{
- cpustate->IF = 1;
- cpustate->delayed_interrupt_enable = 0;
+ m_IF = 1;
+ m_delayed_interrupt_enable = 0;
}
#ifdef DEBUG_MISSING_OPCODE
- cpustate->opcode_bytes_length = 0;
- cpustate->opcode_pc = cpustate->pc;
+ m_opcode_bytes_length = 0;
+ m_opcode_pc = m_pc;
#endif
try
{
- I386OP(decode_opcode)(cpustate);
- if(cpustate->TF && old_tf)
+ i386_decode_opcode();
+ if(m_TF && old_tf)
{
- cpustate->prev_eip = cpustate->eip;
- cpustate->ext = 1;
- i386_trap(cpustate,1,0,0);
+ m_prev_eip = m_eip;
+ m_ext = 1;
+ i386_trap(1,0,0);
}
}
catch(UINT64 e)
{
- cpustate->ext = 1;
- i386_trap_with_error(cpustate,e&0xffffffff,0,0,e>>32);
+ m_ext = 1;
+ i386_trap_with_error(e&0xffffffff,0,0,e>>32);
}
}
- cpustate->tsc += (cycles - cpustate->cycles);
+ m_tsc += (cycles - m_cycles);
}
/*************************************************************************/
-static CPU_TRANSLATE( i386 )
+bool i386_device::memory_translate(address_spacenum spacenum, int intention, offs_t &address)
{
- i386_state *cpustate = get_safe_token(device);
- int ret = TRUE;
- if(space == AS_PROGRAM)
- ret = i386_translate_address(cpustate, intention, address, NULL);
- *address &= cpustate->a20_mask;
+ bool ret = true;
+ if(spacenum == AS_PROGRAM)
+ ret = i386_translate_address(intention, &address, NULL);
+ address &= m_a20_mask;
return ret;
}
-static CPU_DISASSEMBLE( i386 )
+offs_t i386_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
- i386_state *cpustate = get_safe_token(device);
- return i386_dasm_one(buffer, pc, oprom, cpustate->sreg[CS].d ? 32 : 16);
+ return i386_dasm_one(buffer, pc, oprom, m_sreg[CS].d ? 32 : 16);
}
-static CPU_SET_INFO( i386 )
-{
- i386_state *cpustate = get_safe_token(device);
- if (state == CPUINFO_INT_INPUT_STATE+INPUT_LINE_A20)
- {
- i386_set_a20_line(cpustate,info->i);
- return;
- }
- if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + MAX_INPUT_LINES)
- {
- i386_set_irq_line(cpustate,state-CPUINFO_INT_INPUT_STATE, info->i);
- return;
- }
+/*****************************************************************************/
+/* Intel 486 */
- switch (state)
- {
- /* --- the following bits of info are set as 64-bit signed integers --- */
- case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + I386_PC: cpustate->pc = info->i; break;
- case CPUINFO_INT_REGISTER + I386_EIP: cpustate->eip = info->i; CHANGE_PC(cpustate,cpustate->eip); break;
- case CPUINFO_INT_REGISTER + I386_AL: REG8(AL) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_AH: REG8(AH) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_BL: REG8(BL) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_BH: REG8(BH) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CL: REG8(CL) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CH: REG8(CH) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DL: REG8(DL) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DH: REG8(DH) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_AX: REG16(AX) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_BX: REG16(BX) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CX: REG16(CX) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DX: REG16(DX) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_SI: REG16(SI) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DI: REG16(DI) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_BP: REG16(BP) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_SP: REG16(SP) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_IP: cpustate->eip = (cpustate->eip & ~0xFFFF) | (info->i & 0xFFFF); CHANGE_PC(cpustate,cpustate->eip); break;
- case CPUINFO_INT_REGISTER + I386_EAX: REG32(EAX) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_EBX: REG32(EBX) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_ECX: REG32(ECX) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_EDX: REG32(EDX) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_EBP: REG32(EBP) = info->i; break;
- case CPUINFO_INT_SP:
- case CPUINFO_INT_REGISTER + I386_ESP: REG32(ESP) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_ESI: REG32(ESI) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_EDI: REG32(EDI) = info->i; break;
- case CPUINFO_INT_REGISTER + I386_EFLAGS: cpustate->eflags = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CS: cpustate->sreg[CS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,CS); break;
- case CPUINFO_INT_REGISTER + I386_CS_BASE: cpustate->sreg[CS].base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CS_LIMIT: cpustate->sreg[CS].limit = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CS_FLAGS: cpustate->sreg[CS].flags = info->i & 0xf0ff; break;
- case CPUINFO_INT_REGISTER + I386_SS: cpustate->sreg[SS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,SS); break;
- case CPUINFO_INT_REGISTER + I386_SS_BASE: cpustate->sreg[SS].base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_SS_LIMIT: cpustate->sreg[SS].limit = info->i; break;
- case CPUINFO_INT_REGISTER + I386_SS_FLAGS: cpustate->sreg[SS].flags = info->i & 0xf0ff; break;
- case CPUINFO_INT_REGISTER + I386_DS: cpustate->sreg[DS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,DS); break;
- case CPUINFO_INT_REGISTER + I386_DS_BASE: cpustate->sreg[DS].base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DS_LIMIT: cpustate->sreg[DS].limit = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DS_FLAGS: cpustate->sreg[DS].flags = info->i & 0xf0ff; break;
- case CPUINFO_INT_REGISTER + I386_ES: cpustate->sreg[ES].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,ES); break;
- case CPUINFO_INT_REGISTER + I386_ES_BASE: cpustate->sreg[ES].base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_ES_LIMIT: cpustate->sreg[ES].limit = info->i; break;
- case CPUINFO_INT_REGISTER + I386_ES_FLAGS: cpustate->sreg[ES].flags = info->i & 0xf0ff; break;
- case CPUINFO_INT_REGISTER + I386_FS: cpustate->sreg[FS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,FS); break;
- case CPUINFO_INT_REGISTER + I386_FS_BASE: cpustate->sreg[FS].base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_FS_LIMIT: cpustate->sreg[FS].limit = info->i; break;
- case CPUINFO_INT_REGISTER + I386_FS_FLAGS: cpustate->sreg[FS].flags = info->i & 0xf0ff; break;
- case CPUINFO_INT_REGISTER + I386_GS: cpustate->sreg[GS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,GS); break;
- case CPUINFO_INT_REGISTER + I386_GS_BASE: cpustate->sreg[GS].base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_GS_LIMIT: cpustate->sreg[GS].limit = info->i; break;
- case CPUINFO_INT_REGISTER + I386_GS_FLAGS: cpustate->sreg[GS].flags = info->i & 0xf0ff; break;
- case CPUINFO_INT_REGISTER + I386_CR0: cpustate->cr[0] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CR1: cpustate->cr[1] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CR2: cpustate->cr[2] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CR3: cpustate->cr[3] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_CR4: cpustate->cr[4] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DR0: cpustate->dr[0] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DR1: cpustate->dr[1] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DR2: cpustate->dr[2] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DR3: cpustate->dr[3] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DR4: cpustate->dr[4] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DR5: cpustate->dr[5] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DR6: cpustate->dr[6] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_DR7: cpustate->dr[7] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_TR6: cpustate->tr[6] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_TR7: cpustate->tr[7] = info->i; break;
- case CPUINFO_INT_REGISTER + I386_GDTR_BASE: cpustate->gdtr.base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_GDTR_LIMIT: cpustate->gdtr.limit = info->i & 0xffff; break;
- case CPUINFO_INT_REGISTER + I386_IDTR_BASE: cpustate->idtr.base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_IDTR_LIMIT: cpustate->idtr.limit = info->i & 0xffff; break;
- case CPUINFO_INT_REGISTER + I386_TR: cpustate->task.segment = info->i & 0xffff; break;
- case CPUINFO_INT_REGISTER + I386_TR_BASE: cpustate->task.base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_TR_LIMIT: cpustate->task.limit = info->i; break;
- case CPUINFO_INT_REGISTER + I386_TR_FLAGS: cpustate->task.flags = info->i & 0xf0ff; break;
- case CPUINFO_INT_REGISTER + I386_LDTR: cpustate->ldtr.segment = info->i & 0xffff; break;
- case CPUINFO_INT_REGISTER + I386_LDTR_BASE: cpustate->ldtr.base = info->i; break;
- case CPUINFO_INT_REGISTER + I386_LDTR_LIMIT: cpustate->ldtr.limit = info->i; break;
- case CPUINFO_INT_REGISTER + I386_LDTR_FLAGS: cpustate->ldtr.flags = info->i & 0xf0ff; break;
- }
-}
-CPU_GET_INFO( i386 )
+void i486_device::device_start()
{
- i386_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
+ i386_common_init(32);
- switch (state)
- {
- /* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i386_state); break;
- case CPUINFO_INT_INPUT_LINES: info->i = 32; break;
- case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
- case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
- case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
- case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
- case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
- case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 15; break;
- case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
- case CPUINFO_INT_MAX_CYCLES: info->i = 40; break;
-
- case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
- case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 32; break;
- case CPUINFO_INT_PAGE_SHIFT_PROGRAM: info->i = 12; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
-
- case CPUINFO_INT_INPUT_STATE: info->i = CLEAR_LINE; break;
-
- case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
-
- case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + I386_PC: info->i = cpustate->pc; break;
- case CPUINFO_INT_REGISTER + I386_EIP: info->i = cpustate->eip; break;
- case CPUINFO_INT_REGISTER + I386_AL: info->i = REG8(AL); break;
- case CPUINFO_INT_REGISTER + I386_AH: info->i = REG8(AH); break;
- case CPUINFO_INT_REGISTER + I386_BL: info->i = REG8(BL); break;
- case CPUINFO_INT_REGISTER + I386_BH: info->i = REG8(BH); break;
- case CPUINFO_INT_REGISTER + I386_CL: info->i = REG8(CL); break;
- case CPUINFO_INT_REGISTER + I386_CH: info->i = REG8(CH); break;
- case CPUINFO_INT_REGISTER + I386_DL: info->i = REG8(DL); break;
- case CPUINFO_INT_REGISTER + I386_DH: info->i = REG8(DH); break;
- case CPUINFO_INT_REGISTER + I386_AX: info->i = REG16(AX); break;
- case CPUINFO_INT_REGISTER + I386_BX: info->i = REG16(BX); break;
- case CPUINFO_INT_REGISTER + I386_CX: info->i = REG16(CX); break;
- case CPUINFO_INT_REGISTER + I386_DX: info->i = REG16(DX); break;
- case CPUINFO_INT_REGISTER + I386_SI: info->i = REG16(SI); break;
- case CPUINFO_INT_REGISTER + I386_DI: info->i = REG16(DI); break;
- case CPUINFO_INT_REGISTER + I386_BP: info->i = REG16(BP); break;
- case CPUINFO_INT_REGISTER + I386_SP: info->i = REG16(SP); break;
- case CPUINFO_INT_REGISTER + I386_IP: info->i = cpustate->eip & 0xFFFF; break;
- case CPUINFO_INT_REGISTER + I386_EAX: info->i = REG32(EAX); break;
- case CPUINFO_INT_REGISTER + I386_EBX: info->i = REG32(EBX); break;
- case CPUINFO_INT_REGISTER + I386_ECX: info->i = REG32(ECX); break;
- case CPUINFO_INT_REGISTER + I386_EDX: info->i = REG32(EDX); break;
- case CPUINFO_INT_REGISTER + I386_EBP: info->i = REG32(EBP); break;
- case CPUINFO_INT_REGISTER + I386_ESP: info->i = REG32(ESP); break;
- case CPUINFO_INT_REGISTER + I386_ESI: info->i = REG32(ESI); break;
- case CPUINFO_INT_REGISTER + I386_EDI: info->i = REG32(EDI); break;
- case CPUINFO_INT_REGISTER + I386_EFLAGS: info->i = cpustate->eflags; break;
- case CPUINFO_INT_REGISTER + I386_CS: info->i = cpustate->sreg[CS].selector; break;
- case CPUINFO_INT_REGISTER + I386_CS_BASE: info->i = cpustate->sreg[CS].base; break;
- case CPUINFO_INT_REGISTER + I386_CS_LIMIT: info->i = cpustate->sreg[CS].limit; break;
- case CPUINFO_INT_REGISTER + I386_CS_FLAGS: info->i = cpustate->sreg[CS].flags; break;
- case CPUINFO_INT_REGISTER + I386_SS: info->i = cpustate->sreg[SS].selector; break;
- case CPUINFO_INT_REGISTER + I386_SS_BASE: info->i = cpustate->sreg[SS].base; break;
- case CPUINFO_INT_REGISTER + I386_SS_LIMIT: info->i = cpustate->sreg[SS].limit; break;
- case CPUINFO_INT_REGISTER + I386_SS_FLAGS: info->i = cpustate->sreg[SS].flags; break;
- case CPUINFO_INT_REGISTER + I386_DS: info->i = cpustate->sreg[DS].selector; break;
- case CPUINFO_INT_REGISTER + I386_DS_BASE: info->i = cpustate->sreg[DS].base; break;
- case CPUINFO_INT_REGISTER + I386_DS_LIMIT: info->i = cpustate->sreg[DS].limit; break;
- case CPUINFO_INT_REGISTER + I386_DS_FLAGS: info->i = cpustate->sreg[DS].flags; break;
- case CPUINFO_INT_REGISTER + I386_ES: info->i = cpustate->sreg[ES].selector; break;
- case CPUINFO_INT_REGISTER + I386_ES_BASE: info->i = cpustate->sreg[ES].base; break;
- case CPUINFO_INT_REGISTER + I386_ES_LIMIT: info->i = cpustate->sreg[ES].limit; break;
- case CPUINFO_INT_REGISTER + I386_ES_FLAGS: info->i = cpustate->sreg[ES].flags; break;
- case CPUINFO_INT_REGISTER + I386_FS: info->i = cpustate->sreg[FS].selector; break;
- case CPUINFO_INT_REGISTER + I386_FS_BASE: info->i = cpustate->sreg[FS].base; break;
- case CPUINFO_INT_REGISTER + I386_FS_LIMIT: info->i = cpustate->sreg[FS].limit; break;
- case CPUINFO_INT_REGISTER + I386_FS_FLAGS: info->i = cpustate->sreg[FS].flags; break;
- case CPUINFO_INT_REGISTER + I386_GS: info->i = cpustate->sreg[GS].selector; break;
- case CPUINFO_INT_REGISTER + I386_GS_BASE: info->i = cpustate->sreg[GS].base; break;
- case CPUINFO_INT_REGISTER + I386_GS_LIMIT: info->i = cpustate->sreg[GS].limit; break;
- case CPUINFO_INT_REGISTER + I386_GS_FLAGS: info->i = cpustate->sreg[GS].flags; break;
- case CPUINFO_INT_REGISTER + I386_CR0: info->i = cpustate->cr[0]; break;
- case CPUINFO_INT_REGISTER + I386_CR1: info->i = cpustate->cr[1]; break;
- case CPUINFO_INT_REGISTER + I386_CR2: info->i = cpustate->cr[2]; break;
- case CPUINFO_INT_REGISTER + I386_CR3: info->i = cpustate->cr[3]; break;
- case CPUINFO_INT_REGISTER + I386_CR4: info->i = cpustate->cr[4]; break;
- case CPUINFO_INT_REGISTER + I386_DR0: info->i = cpustate->dr[0]; break;
- case CPUINFO_INT_REGISTER + I386_DR1: info->i = cpustate->dr[1]; break;
- case CPUINFO_INT_REGISTER + I386_DR2: info->i = cpustate->dr[2]; break;
- case CPUINFO_INT_REGISTER + I386_DR3: info->i = cpustate->dr[3]; break;
- case CPUINFO_INT_REGISTER + I386_DR4: info->i = cpustate->dr[4]; break;
- case CPUINFO_INT_REGISTER + I386_DR5: info->i = cpustate->dr[5]; break;
- case CPUINFO_INT_REGISTER + I386_DR6: info->i = cpustate->dr[6]; break;
- case CPUINFO_INT_REGISTER + I386_DR7: info->i = cpustate->dr[7]; break;
- case CPUINFO_INT_REGISTER + I386_TR6: info->i = cpustate->tr[6]; break;
- case CPUINFO_INT_REGISTER + I386_TR7: info->i = cpustate->tr[7]; break;
- case CPUINFO_INT_REGISTER + I386_GDTR_BASE: info->i = cpustate->gdtr.base; break;
- case CPUINFO_INT_REGISTER + I386_GDTR_LIMIT: info->i = cpustate->gdtr.limit; break;
- case CPUINFO_INT_REGISTER + I386_IDTR_BASE: info->i = cpustate->idtr.base; break;
- case CPUINFO_INT_REGISTER + I386_IDTR_LIMIT: info->i = cpustate->idtr.limit; break;
- case CPUINFO_INT_REGISTER + I386_TR: info->i = cpustate->task.segment; break;
- case CPUINFO_INT_REGISTER + I386_TR_BASE: info->i = cpustate->task.base; break;
- case CPUINFO_INT_REGISTER + I386_TR_LIMIT: info->i = cpustate->task.limit; break;
- case CPUINFO_INT_REGISTER + I386_TR_FLAGS: info->i = cpustate->task.flags; break;
- case CPUINFO_INT_REGISTER + I386_LDTR: info->i = cpustate->ldtr.segment; break;
- case CPUINFO_INT_REGISTER + I386_LDTR_BASE: info->i = cpustate->ldtr.base; break;
- case CPUINFO_INT_REGISTER + I386_LDTR_LIMIT: info->i = cpustate->ldtr.limit; break;
- case CPUINFO_INT_REGISTER + I386_LDTR_FLAGS: info->i = cpustate->ldtr.flags; break;
-
- /* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i386); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i386); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(i386); break;
- case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(i386); break;
- case CPUINFO_FCT_BURN: info->burn = NULL; break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->cycles; break;
- case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(i386); break;
- case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i386); break;
- case CPUINFO_FCT_DEBUG_INIT: info->debug_init = CPU_DEBUG_INIT_NAME(i386); break;
-
- /* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_NAME: strcpy(info->s, "I386"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "i386"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel 386"); break;
- case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
- case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break;
-
- case CPUINFO_STR_FLAGS: sprintf(info->s, "%08X", get_flags(cpustate)); break;
-
- case CPUINFO_STR_REGISTER + I386_PC: sprintf(info->s, "PC: %08X", cpustate->pc); break;
- case CPUINFO_STR_REGISTER + I386_EIP: sprintf(info->s, "EIP: %08X", cpustate->eip); break;
- case CPUINFO_STR_REGISTER + I386_AL: sprintf(info->s, "~AL: %02X", REG8(AL)); break;
- case CPUINFO_STR_REGISTER + I386_AH: sprintf(info->s, "~AH: %02X", REG8(AH)); break;
- case CPUINFO_STR_REGISTER + I386_BL: sprintf(info->s, "~BL: %02X", REG8(BL)); break;
- case CPUINFO_STR_REGISTER + I386_BH: sprintf(info->s, "~BH: %02X", REG8(BH)); break;
- case CPUINFO_STR_REGISTER + I386_CL: sprintf(info->s, "~CL: %02X", REG8(CL)); break;
- case CPUINFO_STR_REGISTER + I386_CH: sprintf(info->s, "~CH: %02X", REG8(CH)); break;
- case CPUINFO_STR_REGISTER + I386_DL: sprintf(info->s, "~DL: %02X", REG8(DL)); break;
- case CPUINFO_STR_REGISTER + I386_DH: sprintf(info->s, "~DH: %02X", REG8(DH)); break;
- case CPUINFO_STR_REGISTER + I386_AX: sprintf(info->s, "~AX: %04X", REG16(AX)); break;
- case CPUINFO_STR_REGISTER + I386_BX: sprintf(info->s, "~BX: %04X", REG16(BX)); break;
- case CPUINFO_STR_REGISTER + I386_CX: sprintf(info->s, "~CX: %04X", REG16(CX)); break;
- case CPUINFO_STR_REGISTER + I386_DX: sprintf(info->s, "~DX: %04X", REG16(DX)); break;
- case CPUINFO_STR_REGISTER + I386_SI: sprintf(info->s, "~SI: %04X", REG16(SI)); break;
- case CPUINFO_STR_REGISTER + I386_DI: sprintf(info->s, "~DI: %04X", REG16(DI)); break;
- case CPUINFO_STR_REGISTER + I386_BP: sprintf(info->s, "~BP: %04X", REG16(BP)); break;
- case CPUINFO_STR_REGISTER + I386_SP: sprintf(info->s, "~SP: %04X", REG16(SP)); break;
- case CPUINFO_STR_REGISTER + I386_IP: sprintf(info->s, "~IP: %04X", cpustate->eip & 0xFFFF); break;
- case CPUINFO_STR_REGISTER + I386_EAX: sprintf(info->s, "EAX: %08X", cpustate->reg.d[EAX]); break;
- case CPUINFO_STR_REGISTER + I386_EBX: sprintf(info->s, "EBX: %08X", cpustate->reg.d[EBX]); break;
- case CPUINFO_STR_REGISTER + I386_ECX: sprintf(info->s, "ECX: %08X", cpustate->reg.d[ECX]); break;
- case CPUINFO_STR_REGISTER + I386_EDX: sprintf(info->s, "EDX: %08X", cpustate->reg.d[EDX]); break;
- case CPUINFO_STR_REGISTER + I386_EBP: sprintf(info->s, "EBP: %08X", cpustate->reg.d[EBP]); break;
- case CPUINFO_STR_REGISTER + I386_ESP: sprintf(info->s, "ESP: %08X", cpustate->reg.d[ESP]); break;
- case CPUINFO_STR_REGISTER + I386_ESI: sprintf(info->s, "ESI: %08X", cpustate->reg.d[ESI]); break;
- case CPUINFO_STR_REGISTER + I386_EDI: sprintf(info->s, "EDI: %08X", cpustate->reg.d[EDI]); break;
- case CPUINFO_STR_REGISTER + I386_EFLAGS: sprintf(info->s, "EFLAGS: %08X", cpustate->eflags); break;
- case CPUINFO_STR_REGISTER + I386_CS: sprintf(info->s, "CS: %04X", cpustate->sreg[CS].selector); break;
- case CPUINFO_STR_REGISTER + I386_CS_BASE: sprintf(info->s, "CSBASE: %08X", cpustate->sreg[CS].base); break;
- case CPUINFO_STR_REGISTER + I386_CS_LIMIT: sprintf(info->s, "CSLIMIT: %08X", cpustate->sreg[CS].limit); break;
- case CPUINFO_STR_REGISTER + I386_CS_FLAGS: sprintf(info->s, "CSFLAGS: %04X", cpustate->sreg[CS].flags); break;
- case CPUINFO_STR_REGISTER + I386_SS: sprintf(info->s, "SS: %04X", cpustate->sreg[SS].selector); break;
- case CPUINFO_STR_REGISTER + I386_SS_BASE: sprintf(info->s, "SSBASE: %08X", cpustate->sreg[SS].base); break;
- case CPUINFO_STR_REGISTER + I386_SS_LIMIT: sprintf(info->s, "SSLIMIT: %08X", cpustate->sreg[SS].limit); break;
- case CPUINFO_STR_REGISTER + I386_SS_FLAGS: sprintf(info->s, "SSFLAGS: %04X", cpustate->sreg[SS].flags); break;
- case CPUINFO_STR_REGISTER + I386_DS: sprintf(info->s, "DS: %04X", cpustate->sreg[DS].selector); break;
- case CPUINFO_STR_REGISTER + I386_DS_BASE: sprintf(info->s, "DSBASE: %08X", cpustate->sreg[DS].base); break;
- case CPUINFO_STR_REGISTER + I386_DS_LIMIT: sprintf(info->s, "DSLIMIT: %08X", cpustate->sreg[DS].limit); break;
- case CPUINFO_STR_REGISTER + I386_DS_FLAGS: sprintf(info->s, "DSFLAGS: %04X", cpustate->sreg[DS].flags); break;
- case CPUINFO_STR_REGISTER + I386_ES: sprintf(info->s, "ES: %04X", cpustate->sreg[ES].selector); break;
- case CPUINFO_STR_REGISTER + I386_ES_BASE: sprintf(info->s, "ESBASE: %08X", cpustate->sreg[ES].base); break;
- case CPUINFO_STR_REGISTER + I386_ES_LIMIT: sprintf(info->s, "ESLIMIT: %08X", cpustate->sreg[ES].limit); break;
- case CPUINFO_STR_REGISTER + I386_ES_FLAGS: sprintf(info->s, "ESFLAGS: %04X", cpustate->sreg[ES].flags); break;
- case CPUINFO_STR_REGISTER + I386_FS: sprintf(info->s, "FS: %04X", cpustate->sreg[FS].selector); break;
- case CPUINFO_STR_REGISTER + I386_FS_BASE: sprintf(info->s, "FSBASE: %08X", cpustate->sreg[FS].base); break;
- case CPUINFO_STR_REGISTER + I386_FS_LIMIT: sprintf(info->s, "FSLIMIT: %08X", cpustate->sreg[FS].limit); break;
- case CPUINFO_STR_REGISTER + I386_FS_FLAGS: sprintf(info->s, "FSFLAGS: %04X", cpustate->sreg[FS].flags); break;
- case CPUINFO_STR_REGISTER + I386_GS: sprintf(info->s, "GS: %04X", cpustate->sreg[GS].selector); break;
- case CPUINFO_STR_REGISTER + I386_GS_BASE: sprintf(info->s, "GSBASE: %08X", cpustate->sreg[GS].base); break;
- case CPUINFO_STR_REGISTER + I386_GS_LIMIT: sprintf(info->s, "GSLIMIT: %08X", cpustate->sreg[GS].limit); break;
- case CPUINFO_STR_REGISTER + I386_GS_FLAGS: sprintf(info->s, "GSFLAGS: %04X", cpustate->sreg[GS].flags); break;
- case CPUINFO_STR_REGISTER + I386_CR0: sprintf(info->s, "CR0: %08X", cpustate->cr[0]); break;
- case CPUINFO_STR_REGISTER + I386_CR1: sprintf(info->s, "CR1: %08X", cpustate->cr[1]); break;
- case CPUINFO_STR_REGISTER + I386_CR2: sprintf(info->s, "CR2: %08X", cpustate->cr[2]); break;
- case CPUINFO_STR_REGISTER + I386_CR3: sprintf(info->s, "CR3: %08X", cpustate->cr[3]); break;
- case CPUINFO_STR_REGISTER + I386_CR4: sprintf(info->s, "CR4: %08X", cpustate->cr[4]); break;
- case CPUINFO_STR_REGISTER + I386_DR0: sprintf(info->s, "DR0: %08X", cpustate->dr[0]); break;
- case CPUINFO_STR_REGISTER + I386_DR1: sprintf(info->s, "DR1: %08X", cpustate->dr[1]); break;
- case CPUINFO_STR_REGISTER + I386_DR2: sprintf(info->s, "DR2: %08X", cpustate->dr[2]); break;
- case CPUINFO_STR_REGISTER + I386_DR3: sprintf(info->s, "DR3: %08X", cpustate->dr[3]); break;
- case CPUINFO_STR_REGISTER + I386_DR4: sprintf(info->s, "DR4: %08X", cpustate->dr[4]); break;
- case CPUINFO_STR_REGISTER + I386_DR5: sprintf(info->s, "DR5: %08X", cpustate->dr[5]); break;
- case CPUINFO_STR_REGISTER + I386_DR6: sprintf(info->s, "DR6: %08X", cpustate->dr[6]); break;
- case CPUINFO_STR_REGISTER + I386_DR7: sprintf(info->s, "DR7: %08X", cpustate->dr[7]); break;
- case CPUINFO_STR_REGISTER + I386_TR6: sprintf(info->s, "TR6: %08X", cpustate->tr[6]); break;
- case CPUINFO_STR_REGISTER + I386_TR7: sprintf(info->s, "TR7: %08X", cpustate->tr[7]); break;
- case CPUINFO_STR_REGISTER + I386_GDTR_BASE: sprintf(info->s, "GDTRBASE: %08X", cpustate->gdtr.base); break;
- case CPUINFO_STR_REGISTER + I386_GDTR_LIMIT: sprintf(info->s, "GDTRLIMIT: %04X", cpustate->gdtr.limit); break;
- case CPUINFO_STR_REGISTER + I386_IDTR_BASE: sprintf(info->s, "IDTRBASE: %08X", cpustate->idtr.base); break;
- case CPUINFO_STR_REGISTER + I386_IDTR_LIMIT: sprintf(info->s, "IDTRLIMIT: %04X", cpustate->idtr.limit); break;
- case CPUINFO_STR_REGISTER + I386_LDTR: sprintf(info->s, "LDTR: %04X", cpustate->ldtr.segment); break;
- case CPUINFO_STR_REGISTER + I386_LDTR_BASE: sprintf(info->s, "LDTRBASE: %08X", cpustate->ldtr.base); break;
- case CPUINFO_STR_REGISTER + I386_LDTR_LIMIT: sprintf(info->s, "LDTRLIMIT: %08X", cpustate->ldtr.limit); break;
- case CPUINFO_STR_REGISTER + I386_LDTR_FLAGS: sprintf(info->s, "LDTRFLAGS: %04X", cpustate->ldtr.flags); break;
- case CPUINFO_STR_REGISTER + I386_TR: sprintf(info->s, "TR: %04X", cpustate->task.segment); break;
- case CPUINFO_STR_REGISTER + I386_TR_BASE: sprintf(info->s, "TRBASE: %08X", cpustate->task.base); break;
- case CPUINFO_STR_REGISTER + I386_TR_LIMIT: sprintf(info->s, "TRLIMIT: %08X", cpustate->task.limit); break;
- case CPUINFO_STR_REGISTER + I386_TR_FLAGS: sprintf(info->s, "TRFLAGS: %04X", cpustate->task.flags); break;
- case CPUINFO_STR_REGISTER + I386_CPL: sprintf(info->s, "CPL: %01X", cpustate->CPL); break;
- }
+ build_opcode_table(OP_I386 | OP_FPU | OP_I486);
+ build_x87_opcode_table();
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_I486];
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_I486];
+
+ register_state_i386_x87();
}
-CPU_GET_INFO( i386SX )
+void i486_device::device_reset()
{
- switch (state)
- {
- /* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 16; break;
- default: CPU_GET_INFO_CALL(i386); break;
- }
-}
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
-/*****************************************************************************/
-/* Intel 486 */
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].flags = 0x009b;
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
-static CPU_INIT( i486 )
-{
- i386_common_init(device, irqcallback, 32);
-}
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
-static CPU_RESET( i486 )
-{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x00000010;
- cpustate->eflags = 0;
- cpustate->eflags_mask = 0x00077fd7;
- cpustate->eip = 0xfff0;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
+ m_a20_mask = ~0;
+
+ m_cr[0] = 0x00000010;
+ m_eflags = 0;
+ m_eflags_mask = 0x00077fd7;
+ m_eip = 0xfff0;
+ m_smm = false;
+ m_smi_latched = false;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ x87_reset();
// [11:8] Family
// [ 7:4] Model
@@ -3809,116 +3829,57 @@ static CPU_RESET( i486 )
REG32(EAX) = 0;
REG32(EDX) = (4 << 8) | (0 << 4) | (3);
- build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486);
- build_x87_opcode_table(get_safe_token(device));
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I486];
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I486];
-
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static CPU_EXIT( i486 )
-{
-}
-
-static CPU_SET_INFO( i486 )
-{
- i386_state *cpustate = get_safe_token(device);
- switch (state)
- {
- case CPUINFO_INT_REGISTER + X87_CTRL: cpustate->x87_cw = info->i; break;
- case CPUINFO_INT_REGISTER + X87_STATUS: cpustate->x87_sw = info->i; break;
- case CPUINFO_INT_REGISTER + X87_TAG: cpustate->x87_tw = info->i; break;
-
- default: CPU_SET_INFO_CALL(i386); break;
- }
-}
-
-CPU_GET_INFO( i486 )
-{
- i386_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
- switch (state)
- {
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i486);break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i486); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(i486); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(i486); break;
-
- case CPUINFO_INT_REGISTER + X87_CTRL: info->i = cpustate->x87_cw; break;
- case CPUINFO_INT_REGISTER + X87_STATUS: info->i = cpustate->x87_sw; break;
- case CPUINFO_INT_REGISTER + X87_TAG: info->i = cpustate->x87_tw; break;
-
- case CPUINFO_STR_NAME: strcpy(info->s, "I486"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "i486"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel 486"); break;
- case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "x87_CW: %04X", cpustate->x87_cw); break;
- case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "x87_SW: %04X", cpustate->x87_sw); break;
- case CPUINFO_STR_REGISTER + X87_TAG: sprintf(info->s, "x87_TAG:%04X", cpustate->x87_tw); break;
- case CPUINFO_STR_REGISTER + X87_ST0: sprintf(info->s, "ST0: %f", fx80_to_double(ST(0))); break;
- case CPUINFO_STR_REGISTER + X87_ST1: sprintf(info->s, "ST1: %f", fx80_to_double(ST(1))); break;
- case CPUINFO_STR_REGISTER + X87_ST2: sprintf(info->s, "ST2: %f", fx80_to_double(ST(2))); break;
- case CPUINFO_STR_REGISTER + X87_ST3: sprintf(info->s, "ST3: %f", fx80_to_double(ST(3))); break;
- case CPUINFO_STR_REGISTER + X87_ST4: sprintf(info->s, "ST4: %f", fx80_to_double(ST(4))); break;
- case CPUINFO_STR_REGISTER + X87_ST5: sprintf(info->s, "ST5: %f", fx80_to_double(ST(5))); break;
- case CPUINFO_STR_REGISTER + X87_ST6: sprintf(info->s, "ST6: %f", fx80_to_double(ST(6))); break;
- case CPUINFO_STR_REGISTER + X87_ST7: sprintf(info->s, "ST7: %f", fx80_to_double(ST(7))); break;
-
- default: CPU_GET_INFO_CALL(i386); break;
- }
-}
/*****************************************************************************/
/* Pentium */
-static CPU_INIT( pentium )
+void pentium_device::device_start()
{
// 64 dtlb small, 8 dtlb large, 32 itlb
- i386_common_init(device, irqcallback, 96);
+ i386_common_init(96);
+ register_state_i386_x87();
+
+ build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM);
+ build_x87_opcode_table();
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM];
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM];
}
-static CPU_RESET( pentium )
+void pentium_device::device_reset()
{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x00000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x003f7fd7;
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
+
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].flags = 0x009b;
+
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
+
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
+
+ m_a20_mask = ~0;
+
+ m_cr[0] = 0x00000010;
+ m_eflags = 0x00200000;
+ m_eflags_mask = 0x003f7fd7;
+ m_eip = 0xfff0;
+ m_mxcsr = 0x1f80;
+ m_smm = false;
+ m_smi_latched = false;
+ m_smbase = 0x30000;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ x87_reset();
// [11:8] Family
// [ 7:4] Model
@@ -3927,17 +3888,12 @@ static CPU_RESET( pentium )
REG32(EAX) = 0;
REG32(EDX) = (5 << 8) | (2 << 4) | (5);
- build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM);
- build_x87_opcode_table(get_safe_token(device));
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM];
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM];
+ m_cpuid_id0 = 0x756e6547; // Genu
+ m_cpuid_id1 = 0x49656e69; // ineI
+ m_cpuid_id2 = 0x6c65746e; // ntel
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
-
- cpustate->cpuid_max_input_value_eax = 0x01;
- cpustate->cpu_version = REG32(EDX);
+ m_cpuid_max_input_value_eax = 0x01;
+ m_cpu_version = REG32(EDX);
// [ 0:0] FPU on chip
// [ 2:2] I/O breakpoints
@@ -3945,116 +3901,57 @@ static CPU_RESET( pentium )
// [ 5:5] Pentium CPU style model specific registers
// [ 7:7] Machine Check Exception
// [ 8:8] CMPXCHG8B instruction
- cpustate->feature_flags = 0x000001bf;
+ m_feature_flags = 0x000001bf;
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static CPU_EXIT( pentium )
-{
-}
-
-static CPU_SET_INFO( pentium )
-{
- i386_state *cpustate = get_safe_token(device);
- switch (state)
- {
- case CPUINFO_INT_INPUT_STATE+INPUT_LINE_SMI:
- if(!cpustate->smi && state && cpustate->smm)
- cpustate->smi_latched = true;
- cpustate->smi = state;
- break;
- case CPUINFO_INT_REGISTER + X87_CTRL: cpustate->x87_cw = info->i; break;
- case CPUINFO_INT_REGISTER + X87_STATUS: cpustate->x87_sw = info->i; break;
- case CPUINFO_INT_REGISTER + X87_TAG: cpustate->x87_tw = info->i; break;
-
- default: CPU_SET_INFO_CALL(i386); break;
- }
-}
-
-CPU_GET_INFO( pentium )
-{
- i386_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
- switch (state)
- {
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(pentium); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(pentium); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(pentium); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(pentium); break;
-
- case CPUINFO_INT_REGISTER + X87_CTRL: info->i = cpustate->x87_cw; break;
- case CPUINFO_INT_REGISTER + X87_STATUS: info->i = cpustate->x87_sw; break;
- case CPUINFO_INT_REGISTER + X87_TAG: info->i = cpustate->x87_tw; break;
-
- case CPUINFO_STR_NAME: strcpy(info->s, "PENTIUM"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "pentium"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel Pentium"); break;
- case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "x87_CW: %04X", cpustate->x87_cw); break;
- case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "x87_SW: %04X", cpustate->x87_sw); break;
- case CPUINFO_STR_REGISTER + X87_TAG: sprintf(info->s, "x87_TAG:%04X", cpustate->x87_tw); break;
- case CPUINFO_STR_REGISTER + X87_ST0: sprintf(info->s, "ST0: %f", fx80_to_double(ST(0))); break;
- case CPUINFO_STR_REGISTER + X87_ST1: sprintf(info->s, "ST1: %f", fx80_to_double(ST(1))); break;
- case CPUINFO_STR_REGISTER + X87_ST2: sprintf(info->s, "ST2: %f", fx80_to_double(ST(2))); break;
- case CPUINFO_STR_REGISTER + X87_ST3: sprintf(info->s, "ST3: %f", fx80_to_double(ST(3))); break;
- case CPUINFO_STR_REGISTER + X87_ST4: sprintf(info->s, "ST4: %f", fx80_to_double(ST(4))); break;
- case CPUINFO_STR_REGISTER + X87_ST5: sprintf(info->s, "ST5: %f", fx80_to_double(ST(5))); break;
- case CPUINFO_STR_REGISTER + X87_ST6: sprintf(info->s, "ST6: %f", fx80_to_double(ST(6))); break;
- case CPUINFO_STR_REGISTER + X87_ST7: sprintf(info->s, "ST7: %f", fx80_to_double(ST(7))); break;
-
- default: CPU_GET_INFO_CALL(i386); break;
- }
-}
/*****************************************************************************/
/* Cyrix MediaGX */
-static CPU_INIT( mediagx )
+void mediagx_device::device_start()
{
// probably 32 unified
- i386_common_init(device, irqcallback, 32);
+ i386_common_init(32);
+ register_state_i386_x87();
+
+ build_x87_opcode_table();
+ build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_CYRIX);
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_MEDIAGX];
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_MEDIAGX];
}
-static CPU_RESET( mediagx )
+void mediagx_device::device_reset()
{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x00000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
+
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].flags = 0x009b;
+
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
+
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
+
+ m_a20_mask = ~0;
+
+ m_cr[0] = 0x00000010;
+ m_eflags = 0x00200000;
+ m_eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ m_eip = 0xfff0;
+ m_smm = false;
+ m_smi_latched = false;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ x87_reset();
// [11:8] Family
// [ 7:4] Model
@@ -4063,124 +3960,65 @@ static CPU_RESET( mediagx )
REG32(EAX) = 0;
REG32(EDX) = (4 << 8) | (4 << 4) | (1); /* TODO: is this correct? */
- build_x87_opcode_table(get_safe_token(device));
- build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_CYRIX);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_MEDIAGX];
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_MEDIAGX];
-
- cpustate->cpuid_id0 = 0x69727943; // Cyri
- cpustate->cpuid_id1 = 0x736e4978; // xIns
- cpustate->cpuid_id2 = 0x6d616574; // tead
+ m_cpuid_id0 = 0x69727943; // Cyri
+ m_cpuid_id1 = 0x736e4978; // xIns
+ m_cpuid_id2 = 0x6d616574; // tead
- cpustate->cpuid_max_input_value_eax = 0x01;
- cpustate->cpu_version = REG32(EDX);
+ m_cpuid_max_input_value_eax = 0x01;
+ m_cpu_version = REG32(EDX);
// [ 0:0] FPU on chip
- cpustate->feature_flags = 0x00000001;
+ m_feature_flags = 0x00000001;
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static CPU_EXIT( mediagx )
-{
-}
+/*****************************************************************************/
+/* Intel Pentium Pro */
-static CPU_SET_INFO( mediagx )
+void pentium_pro_device::device_start()
{
- i386_state *cpustate = get_safe_token(device);
- switch (state)
- {
- case CPUINFO_INT_REGISTER + X87_CTRL: cpustate->x87_cw = info->i; break;
- case CPUINFO_INT_REGISTER + X87_STATUS: cpustate->x87_sw = info->i; break;
+ // 64 dtlb small, 32 itlb
+ i386_common_init(96);
+ register_state_i386_x87();
- default: CPU_SET_INFO_CALL(i386); break;
- }
+ build_x87_opcode_table();
+ build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO);
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
}
-CPU_GET_INFO( mediagx )
+void pentium_pro_device::device_reset()
{
- i386_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
- switch (state)
- {
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mediagx); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(mediagx); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(mediagx); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(mediagx); break;
-
- case CPUINFO_INT_REGISTER + X87_CTRL: info->i = cpustate->x87_cw; break;
- case CPUINFO_INT_REGISTER + X87_STATUS: info->i = cpustate->x87_sw; break;
- case CPUINFO_INT_REGISTER + X87_TAG: info->i = cpustate->x87_tw; break;
-
- case CPUINFO_STR_NAME: strcpy(info->s, "MEDIAGX"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "mediagx"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Cyrix MediaGX"); break;
- case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "x87_CW: %04X", cpustate->x87_cw); break;
- case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "x87_SW: %04X", cpustate->x87_sw); break;
- case CPUINFO_STR_REGISTER + X87_TAG: sprintf(info->s, "x87_TAG: %04X", cpustate->x87_tw); break;
- case CPUINFO_STR_REGISTER + X87_ST0: sprintf(info->s, "ST0: %f", fx80_to_double(ST(0))); break;
- case CPUINFO_STR_REGISTER + X87_ST1: sprintf(info->s, "ST1: %f", fx80_to_double(ST(1))); break;
- case CPUINFO_STR_REGISTER + X87_ST2: sprintf(info->s, "ST2: %f", fx80_to_double(ST(2))); break;
- case CPUINFO_STR_REGISTER + X87_ST3: sprintf(info->s, "ST3: %f", fx80_to_double(ST(3))); break;
- case CPUINFO_STR_REGISTER + X87_ST4: sprintf(info->s, "ST4: %f", fx80_to_double(ST(4))); break;
- case CPUINFO_STR_REGISTER + X87_ST5: sprintf(info->s, "ST5: %f", fx80_to_double(ST(5))); break;
- case CPUINFO_STR_REGISTER + X87_ST6: sprintf(info->s, "ST6: %f", fx80_to_double(ST(6))); break;
- case CPUINFO_STR_REGISTER + X87_ST7: sprintf(info->s, "ST7: %f", fx80_to_double(ST(7))); break;
-
- default: CPU_GET_INFO_CALL(i386); break;
- }
-}
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
-/*****************************************************************************/
-/* Intel Pentium Pro */
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].flags = 0x009b;
-static CPU_INIT( pentium_pro )
-{
- // 64 dtlb small, 32 itlb
- i386_common_init(device, irqcallback, 96);
-}
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
-static CPU_RESET( pentium_pro )
-{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
+
+ m_a20_mask = ~0;
+
+ m_cr[0] = 0x60000010;
+ m_eflags = 0x00200000;
+ m_eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ m_eip = 0xfff0;
+ m_mxcsr = 0x1f80;
+ m_smm = false;
+ m_smi_latched = false;
+ m_smbase = 0x30000;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ x87_reset();
// [11:8] Family
// [ 7:4] Model
@@ -4189,17 +4027,12 @@ static CPU_RESET( pentium_pro )
REG32(EAX) = 0;
REG32(EDX) = (6 << 8) | (1 << 4) | (1); /* TODO: is this correct? */
- build_x87_opcode_table(get_safe_token(device));
- build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
+ m_cpuid_id0 = 0x756e6547; // Genu
+ m_cpuid_id1 = 0x49656e69; // ineI
+ m_cpuid_id2 = 0x6c65746e; // ntel
- cpustate->cpuid_max_input_value_eax = 0x02;
- cpustate->cpu_version = REG32(EDX);
+ m_cpuid_max_input_value_eax = 0x02;
+ m_cpu_version = REG32(EDX);
// [ 0:0] FPU on chip
// [ 2:2] I/O breakpoints
@@ -4209,91 +4042,58 @@ static CPU_RESET( pentium_pro )
// [ 8:8] CMPXCHG8B instruction
// [15:15] CMOV and FCMOV
// No MMX
- cpustate->feature_flags = 0x000081bf;
+ m_feature_flags = 0x000081bf;
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static CPU_EXIT( pentium_pro )
-{
-}
-static CPU_SET_INFO( pentium_pro )
+/*****************************************************************************/
+/* Intel Pentium MMX */
+
+void pentium_mmx_device::device_start()
{
- switch (state)
- {
- default: CPU_SET_INFO_CALL(pentium); break;
- }
+ // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
+ i386_common_init(96);
+ register_state_i386_x87();
+
+ build_x87_opcode_table();
+ build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_MMX);
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
}
-CPU_GET_INFO( pentium_pro )
+void pentium_mmx_device::device_reset()
{
- switch (state)
- {
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(pentium_pro); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(pentium_pro); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(pentium_pro); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(pentium_pro); break;
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
- case CPUINFO_STR_NAME: strcpy(info->s, "Pentium Pro"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "pentium_pro"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel Pentium Pro"); break;
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].flags = 0x009b;
- default: CPU_GET_INFO_CALL(pentium); break;
- }
-}
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
-/*****************************************************************************/
-/* Intel Pentium MMX */
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
-static CPU_INIT( pentium_mmx )
-{
- // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
- i386_common_init(device, irqcallback, 96);
-}
+ m_a20_mask = ~0;
-static CPU_RESET( pentium_mmx )
-{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
+ m_cr[0] = 0x60000010;
+ m_eflags = 0x00200000;
+ m_eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ m_eip = 0xfff0;
+ m_mxcsr = 0x1f80;
+ m_smm = false;
+ m_smi_latched = false;
+ m_smbase = 0x30000;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ x87_reset();
// [11:8] Family
// [ 7:4] Model
@@ -4302,17 +4102,12 @@ static CPU_RESET( pentium_mmx )
REG32(EAX) = 0;
REG32(EDX) = (5 << 8) | (4 << 4) | (1);
- build_x87_opcode_table(get_safe_token(device));
- build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_MMX);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ m_cpuid_id0 = 0x756e6547; // Genu
+ m_cpuid_id1 = 0x49656e69; // ineI
+ m_cpuid_id2 = 0x6c65746e; // ntel
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
-
- cpustate->cpuid_max_input_value_eax = 0x01;
- cpustate->cpu_version = REG32(EDX);
+ m_cpuid_max_input_value_eax = 0x01;
+ m_cpu_version = REG32(EDX);
// [ 0:0] FPU on chip
// [ 2:2] I/O breakpoints
@@ -4321,91 +4116,57 @@ static CPU_RESET( pentium_mmx )
// [ 7:7] Machine Check Exception
// [ 8:8] CMPXCHG8B instruction
// [23:23] MMX instructions
- cpustate->feature_flags = 0x008001bf;
+ m_feature_flags = 0x008001bf;
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static CPU_EXIT( pentium_mmx )
-{
-}
+/*****************************************************************************/
+/* Intel Pentium II */
-static CPU_SET_INFO( pentium_mmx )
+void pentium2_device::device_start()
{
- switch (state)
- {
- default: CPU_SET_INFO_CALL(pentium); break;
- }
+ // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
+ i386_common_init(96);
+ register_state_i386_x87();
+
+ build_x87_opcode_table();
+ build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX);
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
}
-CPU_GET_INFO( pentium_mmx )
+void pentium2_device::device_reset()
{
- switch (state)
- {
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(pentium_mmx); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(pentium_mmx); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(pentium_mmx); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(pentium_mmx); break;
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
- case CPUINFO_STR_NAME: strcpy(info->s, "Pentium MMX"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "pentium_mmx"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel Pentium"); break;
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].flags = 0x009b;
- default: CPU_GET_INFO_CALL(pentium); break;
- }
-}
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
-/*****************************************************************************/
-/* Intel Pentium II */
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
-static CPU_INIT( pentium2 )
-{
- // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
- i386_common_init(device, irqcallback, 96);
-}
+ m_a20_mask = ~0;
-static CPU_RESET( pentium2 )
-{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
+ m_cr[0] = 0x60000010;
+ m_eflags = 0x00200000;
+ m_eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ m_eip = 0xfff0;
+ m_mxcsr = 0x1f80;
+ m_smm = false;
+ m_smi_latched = false;
+ m_smbase = 0x30000;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ x87_reset();
// [11:8] Family
// [ 7:4] Model
@@ -4414,104 +4175,65 @@ static CPU_RESET( pentium2 )
REG32(EAX) = 0;
REG32(EDX) = (6 << 8) | (3 << 4) | (1); /* TODO: is this correct? */
- build_x87_opcode_table(get_safe_token(device));
- build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
+ m_cpuid_id0 = 0x756e6547; // Genu
+ m_cpuid_id1 = 0x49656e69; // ineI
+ m_cpuid_id2 = 0x6c65746e; // ntel
- cpustate->cpuid_max_input_value_eax = 0x02;
- cpustate->cpu_version = REG32(EDX);
+ m_cpuid_max_input_value_eax = 0x02;
+ m_cpu_version = REG32(EDX);
// [ 0:0] FPU on chip
- cpustate->feature_flags = 0x008081bf; // TODO: enable relevant flags here
+ m_feature_flags = 0x008081bf; // TODO: enable relevant flags here
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static CPU_EXIT( pentium2 )
-{
-}
+/*****************************************************************************/
+/* Intel Pentium III */
-static CPU_SET_INFO( pentium2 )
+void pentium3_device::device_start()
{
- switch (state)
- {
- default: CPU_SET_INFO_CALL(pentium); break;
- }
+ // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
+ i386_common_init(96);
+ register_state_i386_x87();
+
+ build_x87_opcode_table();
+ build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE);
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
}
-CPU_GET_INFO( pentium2 )
+void pentium3_device::device_reset()
{
- switch (state)
- {
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(pentium2); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(pentium2); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(pentium2); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(pentium2); break;
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
- case CPUINFO_STR_NAME: strcpy(info->s, "Pentium II"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "pentium2"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel Pentium II"); break;
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].flags = 0x009b;
- default: CPU_GET_INFO_CALL(pentium); break;
- }
-}
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
-/*****************************************************************************/
-/* Intel Pentium III */
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
-static CPU_INIT( pentium3 )
-{
- // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
- i386_common_init(device, irqcallback, 96);
-}
+ m_a20_mask = ~0;
-static CPU_RESET( pentium3 )
-{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
+ m_cr[0] = 0x60000010;
+ m_eflags = 0x00200000;
+ m_eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ m_eip = 0xfff0;
+ m_mxcsr = 0x1f80;
+ m_smm = false;
+ m_smi_latched = false;
+ m_smbase = 0x30000;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ x87_reset();
// [11:8] Family
// [ 7:4] Model
@@ -4520,106 +4242,67 @@ static CPU_RESET( pentium3 )
REG32(EAX) = 0;
REG32(EDX) = (6 << 8) | (8 << 4) | (10);
- build_x87_opcode_table(get_safe_token(device));
- build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
+ m_cpuid_id0 = 0x756e6547; // Genu
+ m_cpuid_id1 = 0x49656e69; // ineI
+ m_cpuid_id2 = 0x6c65746e; // ntel
- cpustate->cpuid_max_input_value_eax = 0x03;
- cpustate->cpu_version = REG32(EDX);
+ m_cpuid_max_input_value_eax = 0x03;
+ m_cpu_version = REG32(EDX);
// [ 0:0] FPU on chip
// [ 4:4] Time Stamp Counter
// [ D:D] PTE Global Bit
- cpustate->feature_flags = 0x00002011; // TODO: enable relevant flags here
+ m_feature_flags = 0x00002011; // TODO: enable relevant flags here
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
-static CPU_EXIT( pentium3 )
-{
-}
+/*****************************************************************************/
+/* Intel Pentium 4 */
-static CPU_SET_INFO( pentium3 )
+void pentium4_device::device_start()
{
- switch (state)
- {
- default: CPU_SET_INFO_CALL(pentium); break;
- }
+ // 128 dtlb, 64 itlb
+ i386_common_init(196);
+ register_state_i386_x87();
+
+ build_x87_opcode_table();
+ build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE | OP_SSE2);
+ m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
}
-CPU_GET_INFO( pentium3 )
+void pentium4_device::device_reset()
{
- switch (state)
- {
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(pentium3); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(pentium3); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(pentium3); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(pentium3); break;
+ zero_state();
+ vtlb_flush_dynamic(m_vtlb);
- case CPUINFO_STR_NAME: strcpy(info->s, "Pentium III"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "pentium3"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel Pentium III"); break;
+ m_sreg[CS].selector = 0xf000;
+ m_sreg[CS].base = 0xffff0000;
+ m_sreg[CS].limit = 0xffff;
+ m_sreg[CS].flags = 0x009b;
- default: CPU_GET_INFO_CALL(pentium); break;
- }
-}
+ m_sreg[DS].base = m_sreg[ES].base = m_sreg[FS].base = m_sreg[GS].base = m_sreg[SS].base = 0x00000000;
+ m_sreg[DS].limit = m_sreg[ES].limit = m_sreg[FS].limit = m_sreg[GS].limit = m_sreg[SS].limit = 0xffff;
+ m_sreg[DS].flags = m_sreg[ES].flags = m_sreg[FS].flags = m_sreg[GS].flags = m_sreg[SS].flags = 0x0092;
-/*****************************************************************************/
-/* Intel Pentium 4 */
+ m_idtr.base = 0;
+ m_idtr.limit = 0x3ff;
-static CPU_INIT( pentium4 )
-{
- // 128 dtlb, 64 itlb
- i386_common_init(device, irqcallback, 196);
-}
+ m_a20_mask = ~0;
-static CPU_RESET( pentium4 )
-{
- i386_state *cpustate = get_safe_token(device);
- device_irq_acknowledge_callback save_irqcallback;
- vtlb_state *save_vtlb = cpustate->vtlb;
-
- save_irqcallback = cpustate->irq_callback;
- memset( cpustate, 0, sizeof(*cpustate) );
- vtlb_flush_dynamic(save_vtlb);
- cpustate->vtlb = save_vtlb;
- cpustate->irq_callback = save_irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->direct = &cpustate->program->direct();
- cpustate->io = &device->space(AS_IO);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
+ m_cr[0] = 0x60000010;
+ m_eflags = 0x00200000;
+ m_eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ m_eip = 0xfff0;
+ m_mxcsr = 0x1f80;
+ m_smm = false;
+ m_smi_latched = false;
+ m_smbase = 0x30000;
+ m_nmi_masked = false;
+ m_nmi_latched = false;
+
+ x87_reset();
// [27:20] Extended family
// [19:16] Extended model
@@ -4631,61 +4314,16 @@ static CPU_RESET( pentium4 )
REG32(EAX) = 0;
REG32(EDX) = (0 << 20) | (0xf << 8) | (0 << 4) | (1);
- build_x87_opcode_table(get_safe_token(device));
- build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE | OP_SSE2);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
+ m_cpuid_id0 = 0x756e6547; // Genu
+ m_cpuid_id1 = 0x49656e69; // ineI
+ m_cpuid_id2 = 0x6c65746e; // ntel
- cpustate->cpuid_max_input_value_eax = 0x02;
- cpustate->cpu_version = REG32(EDX);
+ m_cpuid_max_input_value_eax = 0x02;
+ m_cpu_version = REG32(EDX);
// [ 0:0] FPU on chip
- cpustate->feature_flags = 0x00000001; // TODO: enable relevant flags here
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
+ m_feature_flags = 0x00000001; // TODO: enable relevant flags here
-static CPU_EXIT( pentium4 )
-{
+ CHANGE_PC(m_eip);
}
-static CPU_SET_INFO( pentium4 )
-{
- switch (state)
- {
- default: CPU_SET_INFO_CALL(pentium); break;
- }
-}
-
-CPU_GET_INFO( pentium4 )
-{
- switch (state)
- {
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(pentium4); break;
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(pentium4); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(pentium4); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(pentium4); break;
-
- case CPUINFO_STR_NAME: strcpy(info->s, "Pentium 4"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "pentium4"); break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel Pentium 4"); break;
-
- default: CPU_GET_INFO_CALL(pentium); break;
- }
-}
-
-
-DEFINE_LEGACY_CPU_DEVICE(I386, i386);
-DEFINE_LEGACY_CPU_DEVICE(I386SX, i386SX);
-DEFINE_LEGACY_CPU_DEVICE(I486, i486);
-DEFINE_LEGACY_CPU_DEVICE(PENTIUM, pentium);
-DEFINE_LEGACY_CPU_DEVICE(MEDIAGX, mediagx);
-DEFINE_LEGACY_CPU_DEVICE(PENTIUM_PRO, pentium_pro);
-DEFINE_LEGACY_CPU_DEVICE(PENTIUM_MMX, pentium_mmx);
-DEFINE_LEGACY_CPU_DEVICE(PENTIUM2, pentium2);
-DEFINE_LEGACY_CPU_DEVICE(PENTIUM3, pentium3);
-DEFINE_LEGACY_CPU_DEVICE(PENTIUM4, pentium4);
diff --git a/src/emu/cpu/i386/i386.h b/src/emu/cpu/i386/i386.h
index d2a1a87bbd2..01722a5a38b 100644
--- a/src/emu/cpu/i386/i386.h
+++ b/src/emu/cpu/i386/i386.h
@@ -3,28 +3,1354 @@
#ifndef __I386INTF_H__
#define __I386INTF_H__
+#include "../../../lib/softfloat/milieu.h"
+#include "../../../lib/softfloat/softfloat.h"
+#include "debug/debugcpu.h"
+#include "cpu/vtlb.h"
+
+
#define INPUT_LINE_A20 1
#define INPUT_LINE_SMI 2
-struct i386_interface
-{
- devcb_write_line smiact;
-};
// mingw has this defined for 32-bit compiles
#undef i386
-DECLARE_LEGACY_CPU_DEVICE(I386, i386);
-DECLARE_LEGACY_CPU_DEVICE(I386SX, i386SX);
-DECLARE_LEGACY_CPU_DEVICE(I486, i486);
-DECLARE_LEGACY_CPU_DEVICE(PENTIUM, pentium);
-DECLARE_LEGACY_CPU_DEVICE(MEDIAGX, mediagx);
-DECLARE_LEGACY_CPU_DEVICE(PENTIUM_PRO, pentium_pro);
-DECLARE_LEGACY_CPU_DEVICE(PENTIUM_MMX, pentium_mmx);
-DECLARE_LEGACY_CPU_DEVICE(PENTIUM2, pentium2);
-DECLARE_LEGACY_CPU_DEVICE(PENTIUM3, pentium3);
-DECLARE_LEGACY_CPU_DEVICE(PENTIUM4, pentium4);
+#define MCFG_I386_SMIACT(_devcb) \
+ i386_device::set_smiact(*device, DEVCB2_##_devcb);
+
+
+class i386_device : public cpu_device
+{
+public:
+ // construction/destruction
+ i386_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ i386_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int program_data_width=32, int program_addr_width=32, int io_data_width=32);
+
+ // static configuration helpers
+ template<class _Object> static devcb2_base &set_smiact(device_t &device, _Object object) { return downcast<i386_device &>(device).m_smiact.set_callback(object); }
+
+ UINT64 debug_segbase(symbol_table &table, int params, const UINT64 *param);
+ UINT64 debug_seglimit(symbol_table &table, int params, const UINT64 *param);
+ UINT64 debug_segofftovirt(symbol_table &table, int params, const UINT64 *param);
+ UINT64 debug_virttophys(symbol_table &table, int params, const UINT64 *param);
+
+protected:
+ // device-level overrides
+ virtual void device_start();
+ virtual void device_reset();
+ virtual void device_debug_setup();
+
+ // device_execute_interface overrides
+ virtual UINT32 execute_min_cycles() const { return 1; }
+ virtual UINT32 execute_max_cycles() const { return 40; }
+ virtual UINT32 execute_input_lines() const { return 32; }
+ virtual void execute_run();
+ virtual void execute_set_input(int inputnum, int state);
+
+ // device_memory_interface overrides
+ virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
+ virtual bool memory_translate(address_spacenum spacenum, int intention, offs_t &address);
+
+ // device_state_interface overrides
+ virtual void state_import(const device_state_entry &entry);
+ virtual void state_export(const device_state_entry &entry);
+ virtual void state_string_export(const device_state_entry &entry, astring &string);
+
+ // device_disasm_interface overrides
+ virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
+ virtual UINT32 disasm_max_opcode_bytes() const { return 15; }
+ virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
+
+ address_space_config m_program_config;
+ address_space_config m_io_config;
+
+union I386_GPR {
+ UINT32 d[8];
+ UINT16 w[16];
+ UINT8 b[32];
+};
+
+struct I386_SREG {
+ UINT16 selector;
+ UINT16 flags;
+ UINT32 base;
+ UINT32 limit;
+ int d; // Operand size
+ bool valid;
+};
+
+struct I386_SYS_TABLE {
+ UINT32 base;
+ UINT16 limit;
+};
+
+struct I386_SEG_DESC {
+ UINT16 segment;
+ UINT16 flags;
+ UINT32 base;
+ UINT32 limit;
+};
+
+union XMM_REG {
+ UINT8 b[16];
+ UINT16 w[8];
+ UINT32 d[4];
+ UINT64 q[2];
+ INT8 c[16];
+ INT16 s[8];
+ INT32 i[4];
+ INT64 l[2];
+ float f[4];
+ double f64[2];
+};
+
+union MMX_REG {
+ UINT32 d[2];
+ INT32 i[2];
+ UINT16 w[4];
+ INT16 s[4];
+ UINT8 b[8];
+ INT8 c[8];
+ float f[2];
+ UINT64 q;
+ INT64 l;
+};
+
+struct I386_CALL_GATE
+{
+ UINT16 segment;
+ UINT16 selector;
+ UINT32 offset;
+ UINT8 ar; // access rights
+ UINT8 dpl;
+ UINT8 dword_count;
+ UINT8 present;
+};
+
+ typedef void (i386_device::*i386_modrm_func)(UINT8 modrm);
+ typedef void (i386_device::*i386_op_func)();
+ struct X86_OPCODE {
+ UINT8 opcode;
+ UINT32 flags;
+ i386_op_func handler16;
+ i386_op_func handler32;
+ };
+ static const X86_OPCODE s_x86_opcode_table[];
+
+ I386_GPR m_reg;
+ I386_SREG m_sreg[6];
+ UINT32 m_eip;
+ UINT32 m_pc;
+ UINT32 m_prev_eip;
+ UINT32 m_eflags;
+ UINT32 m_eflags_mask;
+ UINT8 m_CF;
+ UINT8 m_DF;
+ UINT8 m_SF;
+ UINT8 m_OF;
+ UINT8 m_ZF;
+ UINT8 m_PF;
+ UINT8 m_AF;
+ UINT8 m_IF;
+ UINT8 m_TF;
+ UINT8 m_IOP1;
+ UINT8 m_IOP2;
+ UINT8 m_NT;
+ UINT8 m_RF;
+ UINT8 m_VM;
+ UINT8 m_AC;
+ UINT8 m_VIF;
+ UINT8 m_VIP;
+ UINT8 m_ID;
+
+ UINT8 m_CPL; // current privilege level
+
+ UINT8 m_performed_intersegment_jump;
+ UINT8 m_delayed_interrupt_enable;
+
+ UINT32 m_cr[5]; // Control registers
+ UINT32 m_dr[8]; // Debug registers
+ UINT32 m_tr[8]; // Test registers
+
+ I386_SYS_TABLE m_gdtr; // Global Descriptor Table Register
+ I386_SYS_TABLE m_idtr; // Interrupt Descriptor Table Register
+ I386_SEG_DESC m_task; // Task register
+ I386_SEG_DESC m_ldtr; // Local Descriptor Table Register
+
+ UINT8 m_ext; // external interrupt
+
+ int m_halted;
+
+ int m_operand_size;
+ int m_address_size;
+ int m_operand_prefix;
+ int m_address_prefix;
+
+ int m_segment_prefix;
+ int m_segment_override;
+
+ int m_cycles;
+ int m_base_cycles;
+ UINT8 m_opcode;
+
+ UINT8 m_irq_state;
+ address_space *m_program;
+ direct_read_data *m_direct;
+ address_space *m_io;
+ UINT32 m_a20_mask;
+
+ int m_cpuid_max_input_value_eax;
+ UINT32 m_cpuid_id0, m_cpuid_id1, m_cpuid_id2;
+ UINT32 m_cpu_version;
+ UINT32 m_feature_flags;
+ UINT64 m_tsc;
+ UINT64 m_perfctr[2];
+
+ // FPU
+ floatx80 m_x87_reg[8];
+
+ UINT16 m_x87_cw;
+ UINT16 m_x87_sw;
+ UINT16 m_x87_tw;
+ UINT64 m_x87_data_ptr;
+ UINT64 m_x87_inst_ptr;
+ UINT16 m_x87_opcode;
+
+ i386_modrm_func m_opcode_table_x87_d8[256];
+ i386_modrm_func m_opcode_table_x87_d9[256];
+ i386_modrm_func m_opcode_table_x87_da[256];
+ i386_modrm_func m_opcode_table_x87_db[256];
+ i386_modrm_func m_opcode_table_x87_dc[256];
+ i386_modrm_func m_opcode_table_x87_dd[256];
+ i386_modrm_func m_opcode_table_x87_de[256];
+ i386_modrm_func m_opcode_table_x87_df[256];
+
+ // SSE
+ XMM_REG m_sse_reg[8];
+ UINT32 m_mxcsr;
+
+ i386_op_func m_opcode_table1_16[256];
+ i386_op_func m_opcode_table1_32[256];
+ i386_op_func m_opcode_table2_16[256];
+ i386_op_func m_opcode_table2_32[256];
+ i386_op_func m_opcode_table366_16[256];
+ i386_op_func m_opcode_table366_32[256];
+ i386_op_func m_opcode_table3f2_16[256];
+ i386_op_func m_opcode_table3f2_32[256];
+ i386_op_func m_opcode_table3f3_16[256];
+ i386_op_func m_opcode_table3f3_32[256];
+
+ UINT8 *m_cycle_table_pm;
+ UINT8 *m_cycle_table_rm;
+
+ vtlb_state *m_vtlb;
+
+ bool m_smm;
+ bool m_smi;
+ bool m_smi_latched;
+ bool m_nmi_masked;
+ bool m_nmi_latched;
+ UINT32 m_smbase;
+ devcb2_write_line m_smiact;
+
+ // bytes in current opcode, debug only
+ UINT8 m_opcode_bytes[16];
+ UINT32 m_opcode_pc;
+ int m_opcode_bytes_length;
+
+ UINT64 m_debugger_temp;
+
+ void register_state_i386();
+ void register_state_i386_x87();
+ inline UINT32 i386_translate(int segment, UINT32 ip, int rwn);
+ inline vtlb_entry get_permissions(UINT32 pte, int wp);
+ bool i386_translate_address(int intention, offs_t *address, vtlb_entry *entry);
+ inline int translate_address(int pl, int type, UINT32 *address, UINT32 *error);
+ inline void CHANGE_PC(UINT32 pc);
+ inline void NEAR_BRANCH(INT32 offs);
+ inline UINT8 FETCH();
+ inline UINT16 FETCH16();
+ inline UINT32 FETCH32();
+ inline UINT8 READ8(UINT32 ea);
+ inline UINT16 READ16(UINT32 ea);
+ inline UINT32 READ32(UINT32 ea);
+ inline UINT64 READ64(UINT32 ea);
+ inline UINT8 READ8PL0(UINT32 ea);
+ inline UINT16 READ16PL0(UINT32 ea);
+ inline UINT32 READ32PL0(UINT32 ea);
+ inline void WRITE_TEST(UINT32 ea);
+ inline void WRITE8(UINT32 ea, UINT8 value);
+ inline void WRITE16(UINT32 ea, UINT16 value);
+ inline void WRITE32(UINT32 ea, UINT32 value);
+ inline void WRITE64(UINT32 ea, UINT64 value);
+ inline UINT8 OR8(UINT8 dst, UINT8 src);
+ inline UINT16 OR16(UINT16 dst, UINT16 src);
+ inline UINT32 OR32(UINT32 dst, UINT32 src);
+ inline UINT8 AND8(UINT8 dst, UINT8 src);
+ inline UINT16 AND16(UINT16 dst, UINT16 src);
+ inline UINT32 AND32(UINT32 dst, UINT32 src);
+ inline UINT8 XOR8(UINT8 dst, UINT8 src);
+ inline UINT16 XOR16(UINT16 dst, UINT16 src);
+ inline UINT32 XOR32(UINT32 dst, UINT32 src);
+ inline UINT8 SBB8(UINT8 dst, UINT8 src, UINT8 b);
+ inline UINT16 SBB16(UINT16 dst, UINT16 src, UINT16 b);
+ inline UINT32 SBB32(UINT32 dst, UINT32 src, UINT32 b);
+ inline UINT8 ADC8(UINT8 dst, UINT8 src, UINT8 c);
+ inline UINT16 ADC16(UINT16 dst, UINT16 src, UINT8 c);
+ inline UINT32 ADC32(UINT32 dst, UINT32 src, UINT32 c);
+ inline UINT8 INC8(UINT8 dst);
+ inline UINT16 INC16(UINT16 dst);
+ inline UINT32 INC32(UINT32 dst);
+ inline UINT8 DEC8(UINT8 dst);
+ inline UINT16 DEC16(UINT16 dst);
+ inline UINT32 DEC32(UINT32 dst);
+ inline void PUSH16(UINT16 value);
+ inline void PUSH32(UINT32 value);
+ inline void PUSH8(UINT8 value);
+ inline UINT8 POP8();
+ inline UINT16 POP16();
+ inline UINT32 POP32();
+ inline void BUMP_SI(int adjustment);
+ inline void BUMP_DI(int adjustment);
+ inline void check_ioperm(offs_t port, UINT8 mask);
+ inline UINT8 READPORT8(offs_t port);
+ inline void WRITEPORT8(offs_t port, UINT8 value);
+ inline UINT16 READPORT16(offs_t port);
+ inline void WRITEPORT16(offs_t port, UINT16 value);
+ inline UINT32 READPORT32(offs_t port);
+ inline void WRITEPORT32(offs_t port, UINT32 value);
+ UINT64 pentium_msr_read(UINT32 offset,UINT8 *valid_msr);
+ void pentium_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr);
+ UINT64 p6_msr_read(UINT32 offset,UINT8 *valid_msr);
+ void p6_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr);
+ inline UINT64 MSR_READ(UINT32 offset,UINT8 *valid_msr);
+ inline void MSR_WRITE(UINT32 offset, UINT64 data, UINT8 *valid_msr);
+ UINT32 i386_load_protected_mode_segment(I386_SREG *seg, UINT64 *desc );
+ void i386_load_call_gate(I386_CALL_GATE *gate);
+ void i386_set_descriptor_accessed(UINT16 selector);
+ void i386_load_segment_descriptor(int segment );
+ UINT32 i386_get_stack_segment(UINT8 privilege);
+ UINT32 i386_get_stack_ptr(UINT8 privilege);
+ UINT32 get_flags();
+ void set_flags(UINT32 f );
+ void sib_byte(UINT8 mod, UINT32* out_ea, UINT8* out_segment);
+ void modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment);
+ UINT32 GetNonTranslatedEA(UINT8 modrm,UINT8 *seg);
+ UINT32 GetEA(UINT8 modrm, int rwn);
+ void i386_check_sreg_validity(int reg);
+ int i386_limit_check(int seg, UINT32 offset);
+ void i386_sreg_load(UINT16 selector, UINT8 reg, bool *fault);
+ void i386_trap(int irq, int irq_gate, int trap_level);
+ void i386_trap_with_error(int irq, int irq_gate, int trap_level, UINT32 error);
+ void i286_task_switch(UINT16 selector, UINT8 nested);
+ void i386_task_switch(UINT16 selector, UINT8 nested);
+ void i386_check_irq_line();
+ void i386_protected_mode_jump(UINT16 seg, UINT32 off, int indirect, int operand32);
+ void i386_protected_mode_call(UINT16 seg, UINT32 off, int indirect, int operand32);
+ void i386_protected_mode_retf(UINT8 count, UINT8 operand32);
+ void i386_protected_mode_iret(int operand32);
+ void build_cycle_table();
+ void report_invalid_opcode();
+ void report_invalid_modrm(const char* opcode, UINT8 modrm);
+ void i386_decode_opcode();
+ void i386_decode_two_byte();
+ void i386_decode_three_byte66();
+ void i386_decode_three_bytef2();
+ void i386_decode_three_bytef3();
+ UINT8 read8_debug(UINT32 ea, UINT8 *data);
+ UINT32 i386_get_debug_desc(I386_SREG *seg);
+ inline void CYCLES(int x);
+ inline void CYCLES_RM(int modrm, int r, int m);
+ UINT8 i386_shift_rotate8(UINT8 modrm, UINT32 value, UINT8 shift);
+ void i386_adc_rm8_r8();
+ void i386_adc_r8_rm8();
+ void i386_adc_al_i8();
+ void i386_add_rm8_r8();
+ void i386_add_r8_rm8();
+ void i386_add_al_i8();
+ void i386_and_rm8_r8();
+ void i386_and_r8_rm8();
+ void i386_and_al_i8();
+ void i386_clc();
+ void i386_cld();
+ void i386_cli();
+ void i386_cmc();
+ void i386_cmp_rm8_r8();
+ void i386_cmp_r8_rm8();
+ void i386_cmp_al_i8();
+ void i386_cmpsb();
+ void i386_in_al_i8();
+ void i386_in_al_dx();
+ void i386_ja_rel8();
+ void i386_jbe_rel8();
+ void i386_jc_rel8();
+ void i386_jg_rel8();
+ void i386_jge_rel8();
+ void i386_jl_rel8();
+ void i386_jle_rel8();
+ void i386_jnc_rel8();
+ void i386_jno_rel8();
+ void i386_jnp_rel8();
+ void i386_jns_rel8();
+ void i386_jnz_rel8();
+ void i386_jo_rel8();
+ void i386_jp_rel8();
+ void i386_js_rel8();
+ void i386_jz_rel8();
+ void i386_jmp_rel8();
+ void i386_lahf();
+ void i386_lodsb();
+ void i386_mov_rm8_r8();
+ void i386_mov_r8_rm8();
+ void i386_mov_rm8_i8();
+ void i386_mov_r32_cr();
+ void i386_mov_r32_dr();
+ void i386_mov_cr_r32();
+ void i386_mov_dr_r32();
+ void i386_mov_al_m8();
+ void i386_mov_m8_al();
+ void i386_mov_rm16_sreg();
+ void i386_mov_sreg_rm16();
+ void i386_mov_al_i8();
+ void i386_mov_cl_i8();
+ void i386_mov_dl_i8();
+ void i386_mov_bl_i8();
+ void i386_mov_ah_i8();
+ void i386_mov_ch_i8();
+ void i386_mov_dh_i8();
+ void i386_mov_bh_i8();
+ void i386_movsb();
+ void i386_or_rm8_r8();
+ void i386_or_r8_rm8();
+ void i386_or_al_i8();
+ void i386_out_al_i8();
+ void i386_out_al_dx();
+ void i386_arpl();
+ void i386_push_i8();
+ void i386_ins_generic(int size);
+ void i386_insb();
+ void i386_insw();
+ void i386_insd();
+ void i386_outs_generic(int size);
+ void i386_outsb();
+ void i386_outsw();
+ void i386_outsd();
+ void i386_repeat(int invert_flag);
+ void i386_rep();
+ void i386_repne();
+ void i386_sahf();
+ void i386_sbb_rm8_r8();
+ void i386_sbb_r8_rm8();
+ void i386_sbb_al_i8();
+ void i386_scasb();
+ void i386_setalc();
+ void i386_seta_rm8();
+ void i386_setbe_rm8();
+ void i386_setc_rm8();
+ void i386_setg_rm8();
+ void i386_setge_rm8();
+ void i386_setl_rm8();
+ void i386_setle_rm8();
+ void i386_setnc_rm8();
+ void i386_setno_rm8();
+ void i386_setnp_rm8();
+ void i386_setns_rm8();
+ void i386_setnz_rm8();
+ void i386_seto_rm8();
+ void i386_setp_rm8();
+ void i386_sets_rm8();
+ void i386_setz_rm8();
+ void i386_stc();
+ void i386_std();
+ void i386_sti();
+ void i386_stosb();
+ void i386_sub_rm8_r8();
+ void i386_sub_r8_rm8();
+ void i386_sub_al_i8();
+ void i386_test_al_i8();
+ void i386_test_rm8_r8();
+ void i386_xchg_r8_rm8();
+ void i386_xor_rm8_r8();
+ void i386_xor_r8_rm8();
+ void i386_xor_al_i8();
+ void i386_group80_8();
+ void i386_groupC0_8();
+ void i386_groupD0_8();
+ void i386_groupD2_8();
+ void i386_groupF6_8();
+ void i386_groupFE_8();
+ void i386_segment_CS();
+ void i386_segment_DS();
+ void i386_segment_ES();
+ void i386_segment_FS();
+ void i386_segment_GS();
+ void i386_segment_SS();
+ void i386_operand_size();
+ void i386_address_size();
+ void i386_nop();
+ void i386_int3();
+ void i386_int();
+ void i386_into();
+ void i386_escape();
+ void i386_hlt();
+ void i386_decimal_adjust(int direction);
+ void i386_daa();
+ void i386_das();
+ void i386_aaa();
+ void i386_aas();
+ void i386_aad();
+ void i386_aam();
+ void i386_clts();
+ void i386_wait();
+ void i386_lock();
+ void i386_mov_r32_tr();
+ void i386_mov_tr_r32();
+ void i386_loadall();
+ void i386_invalid();
+ void i386_xlat();
+ UINT16 i386_shift_rotate16(UINT8 modrm, UINT32 value, UINT8 shift);
+ void i386_adc_rm16_r16();
+ void i386_adc_r16_rm16();
+ void i386_adc_ax_i16();
+ void i386_add_rm16_r16();
+ void i386_add_r16_rm16();
+ void i386_add_ax_i16();
+ void i386_and_rm16_r16();
+ void i386_and_r16_rm16();
+ void i386_and_ax_i16();
+ void i386_bsf_r16_rm16();
+ void i386_bsr_r16_rm16();
+ void i386_bt_rm16_r16();
+ void i386_btc_rm16_r16();
+ void i386_btr_rm16_r16();
+ void i386_bts_rm16_r16();
+ void i386_call_abs16();
+ void i386_call_rel16();
+ void i386_cbw();
+ void i386_cmp_rm16_r16();
+ void i386_cmp_r16_rm16();
+ void i386_cmp_ax_i16();
+ void i386_cmpsw();
+ void i386_cwd();
+ void i386_dec_ax();
+ void i386_dec_cx();
+ void i386_dec_dx();
+ void i386_dec_bx();
+ void i386_dec_sp();
+ void i386_dec_bp();
+ void i386_dec_si();
+ void i386_dec_di();
+ void i386_imul_r16_rm16();
+ void i386_imul_r16_rm16_i16();
+ void i386_imul_r16_rm16_i8();
+ void i386_in_ax_i8();
+ void i386_in_ax_dx();
+ void i386_inc_ax();
+ void i386_inc_cx();
+ void i386_inc_dx();
+ void i386_inc_bx();
+ void i386_inc_sp();
+ void i386_inc_bp();
+ void i386_inc_si();
+ void i386_inc_di();
+ void i386_iret16();
+ void i386_ja_rel16();
+ void i386_jbe_rel16();
+ void i386_jc_rel16();
+ void i386_jg_rel16();
+ void i386_jge_rel16();
+ void i386_jl_rel16();
+ void i386_jle_rel16();
+ void i386_jnc_rel16();
+ void i386_jno_rel16();
+ void i386_jnp_rel16();
+ void i386_jns_rel16();
+ void i386_jnz_rel16();
+ void i386_jo_rel16();
+ void i386_jp_rel16();
+ void i386_js_rel16();
+ void i386_jz_rel16();
+ void i386_jcxz16();
+ void i386_jmp_rel16();
+ void i386_jmp_abs16();
+ void i386_lea16();
+ void i386_enter16();
+ void i386_leave16();
+ void i386_lodsw();
+ void i386_loop16();
+ void i386_loopne16();
+ void i386_loopz16();
+ void i386_mov_rm16_r16();
+ void i386_mov_r16_rm16();
+ void i386_mov_rm16_i16();
+ void i386_mov_ax_m16();
+ void i386_mov_m16_ax();
+ void i386_mov_ax_i16();
+ void i386_mov_cx_i16();
+ void i386_mov_dx_i16();
+ void i386_mov_bx_i16();
+ void i386_mov_sp_i16();
+ void i386_mov_bp_i16();
+ void i386_mov_si_i16();
+ void i386_mov_di_i16();
+ void i386_movsw();
+ void i386_movsx_r16_rm8();
+ void i386_movzx_r16_rm8();
+ void i386_or_rm16_r16();
+ void i386_or_r16_rm16();
+ void i386_or_ax_i16();
+ void i386_out_ax_i8();
+ void i386_out_ax_dx();
+ void i386_pop_ax();
+ void i386_pop_cx();
+ void i386_pop_dx();
+ void i386_pop_bx();
+ void i386_pop_sp();
+ void i386_pop_bp();
+ void i386_pop_si();
+ void i386_pop_di();
+ bool i386_pop_seg16(int segment);
+ void i386_pop_ds16();
+ void i386_pop_es16();
+ void i386_pop_fs16();
+ void i386_pop_gs16();
+ void i386_pop_ss16();
+ void i386_pop_rm16();
+ void i386_popa();
+ void i386_popf();
+ void i386_push_ax();
+ void i386_push_cx();
+ void i386_push_dx();
+ void i386_push_bx();
+ void i386_push_sp();
+ void i386_push_bp();
+ void i386_push_si();
+ void i386_push_di();
+ void i386_push_cs16();
+ void i386_push_ds16();
+ void i386_push_es16();
+ void i386_push_fs16();
+ void i386_push_gs16();
+ void i386_push_ss16();
+ void i386_push_i16();
+ void i386_pusha();
+ void i386_pushf();
+ void i386_ret_near16_i16();
+ void i386_ret_near16();
+ void i386_sbb_rm16_r16();
+ void i386_sbb_r16_rm16();
+ void i386_sbb_ax_i16();
+ void i386_scasw();
+ void i386_shld16_i8();
+ void i386_shld16_cl();
+ void i386_shrd16_i8();
+ void i386_shrd16_cl();
+ void i386_stosw();
+ void i386_sub_rm16_r16();
+ void i386_sub_r16_rm16();
+ void i386_sub_ax_i16();
+ void i386_test_ax_i16();
+ void i386_test_rm16_r16();
+ void i386_xchg_ax_cx();
+ void i386_xchg_ax_dx();
+ void i386_xchg_ax_bx();
+ void i386_xchg_ax_sp();
+ void i386_xchg_ax_bp();
+ void i386_xchg_ax_si();
+ void i386_xchg_ax_di();
+ void i386_xchg_r16_rm16();
+ void i386_xor_rm16_r16();
+ void i386_xor_r16_rm16();
+ void i386_xor_ax_i16();
+ void i386_group81_16();
+ void i386_group83_16();
+ void i386_groupC1_16();
+ void i386_groupD1_16();
+ void i386_groupD3_16();
+ void i386_groupF7_16();
+ void i386_groupFF_16();
+ void i386_group0F00_16();
+ void i386_group0F01_16();
+ void i386_group0FBA_16();
+ void i386_lar_r16_rm16();
+ void i386_lsl_r16_rm16();
+ void i386_bound_r16_m16_m16();
+ void i386_retf16();
+ void i386_retf_i16();
+ bool i386_load_far_pointer16(int s);
+ void i386_lds16();
+ void i386_lss16();
+ void i386_les16();
+ void i386_lfs16();
+ void i386_lgs16();
+ UINT32 i386_shift_rotate32(UINT8 modrm, UINT32 value, UINT8 shift);
+ void i386_adc_rm32_r32();
+ void i386_adc_r32_rm32();
+ void i386_adc_eax_i32();
+ void i386_add_rm32_r32();
+ void i386_add_r32_rm32();
+ void i386_add_eax_i32();
+ void i386_and_rm32_r32();
+ void i386_and_r32_rm32();
+ void i386_and_eax_i32();
+ void i386_bsf_r32_rm32();
+ void i386_bsr_r32_rm32();
+ void i386_bt_rm32_r32();
+ void i386_btc_rm32_r32();
+ void i386_btr_rm32_r32();
+ void i386_bts_rm32_r32();
+ void i386_call_abs32();
+ void i386_call_rel32();
+ void i386_cdq();
+ void i386_cmp_rm32_r32();
+ void i386_cmp_r32_rm32();
+ void i386_cmp_eax_i32();
+ void i386_cmpsd();
+ void i386_cwde();
+ void i386_dec_eax();
+ void i386_dec_ecx();
+ void i386_dec_edx();
+ void i386_dec_ebx();
+ void i386_dec_esp();
+ void i386_dec_ebp();
+ void i386_dec_esi();
+ void i386_dec_edi();
+ void i386_imul_r32_rm32();
+ void i386_imul_r32_rm32_i32();
+ void i386_imul_r32_rm32_i8();
+ void i386_in_eax_i8();
+ void i386_in_eax_dx();
+ void i386_inc_eax();
+ void i386_inc_ecx();
+ void i386_inc_edx();
+ void i386_inc_ebx();
+ void i386_inc_esp();
+ void i386_inc_ebp();
+ void i386_inc_esi();
+ void i386_inc_edi();
+ void i386_iret32();
+ void i386_ja_rel32();
+ void i386_jbe_rel32();
+ void i386_jc_rel32();
+ void i386_jg_rel32();
+ void i386_jge_rel32();
+ void i386_jl_rel32();
+ void i386_jle_rel32();
+ void i386_jnc_rel32();
+ void i386_jno_rel32();
+ void i386_jnp_rel32();
+ void i386_jns_rel32();
+ void i386_jnz_rel32();
+ void i386_jo_rel32();
+ void i386_jp_rel32();
+ void i386_js_rel32();
+ void i386_jz_rel32();
+ void i386_jcxz32();
+ void i386_jmp_rel32();
+ void i386_jmp_abs32();
+ void i386_lea32();
+ void i386_enter32();
+ void i386_leave32();
+ void i386_lodsd();
+ void i386_loop32();
+ void i386_loopne32();
+ void i386_loopz32();
+ void i386_mov_rm32_r32();
+ void i386_mov_r32_rm32();
+ void i386_mov_rm32_i32();
+ void i386_mov_eax_m32();
+ void i386_mov_m32_eax();
+ void i386_mov_eax_i32();
+ void i386_mov_ecx_i32();
+ void i386_mov_edx_i32();
+ void i386_mov_ebx_i32();
+ void i386_mov_esp_i32();
+ void i386_mov_ebp_i32();
+ void i386_mov_esi_i32();
+ void i386_mov_edi_i32();
+ void i386_movsd();
+ void i386_movsx_r32_rm8();
+ void i386_movsx_r32_rm16();
+ void i386_movzx_r32_rm8();
+ void i386_movzx_r32_rm16();
+ void i386_or_rm32_r32();
+ void i386_or_r32_rm32();
+ void i386_or_eax_i32();
+ void i386_out_eax_i8();
+ void i386_out_eax_dx();
+ void i386_pop_eax();
+ void i386_pop_ecx();
+ void i386_pop_edx();
+ void i386_pop_ebx();
+ void i386_pop_esp();
+ void i386_pop_ebp();
+ void i386_pop_esi();
+ void i386_pop_edi();
+ bool i386_pop_seg32(int segment);
+ void i386_pop_ds32();
+ void i386_pop_es32();
+ void i386_pop_fs32();
+ void i386_pop_gs32();
+ void i386_pop_ss32();
+ void i386_pop_rm32();
+ void i386_popad();
+ void i386_popfd();
+ void i386_push_eax();
+ void i386_push_ecx();
+ void i386_push_edx();
+ void i386_push_ebx();
+ void i386_push_esp();
+ void i386_push_ebp();
+ void i386_push_esi();
+ void i386_push_edi();
+ void i386_push_cs32();
+ void i386_push_ds32();
+ void i386_push_es32();
+ void i386_push_fs32();
+ void i386_push_gs32();
+ void i386_push_ss32();
+ void i386_push_i32();
+ void i386_pushad();
+ void i386_pushfd();
+ void i386_ret_near32_i16();
+ void i386_ret_near32();
+ void i386_sbb_rm32_r32();
+ void i386_sbb_r32_rm32();
+ void i386_sbb_eax_i32();
+ void i386_scasd();
+ void i386_shld32_i8();
+ void i386_shld32_cl();
+ void i386_shrd32_i8();
+ void i386_shrd32_cl();
+ void i386_stosd();
+ void i386_sub_rm32_r32();
+ void i386_sub_r32_rm32();
+ void i386_sub_eax_i32();
+ void i386_test_eax_i32();
+ void i386_test_rm32_r32();
+ void i386_xchg_eax_ecx();
+ void i386_xchg_eax_edx();
+ void i386_xchg_eax_ebx();
+ void i386_xchg_eax_esp();
+ void i386_xchg_eax_ebp();
+ void i386_xchg_eax_esi();
+ void i386_xchg_eax_edi();
+ void i386_xchg_r32_rm32();
+ void i386_xor_rm32_r32();
+ void i386_xor_r32_rm32();
+ void i386_xor_eax_i32();
+ void i386_group81_32();
+ void i386_group83_32();
+ void i386_groupC1_32();
+ void i386_groupD1_32();
+ void i386_groupD3_32();
+ void i386_groupF7_32();
+ void i386_groupFF_32();
+ void i386_group0F00_32();
+ void i386_group0F01_32();
+ void i386_group0FBA_32();
+ void i386_lar_r32_rm32();
+ void i386_lsl_r32_rm32();
+ void i386_bound_r32_m32_m32();
+ void i386_retf32();
+ void i386_retf_i32();
+ void i386_load_far_pointer32(int s);
+ void i386_lds32();
+ void i386_lss32();
+ void i386_les32();
+ void i386_lfs32();
+ void i386_lgs32();
+ void i486_cpuid();
+ void i486_invd();
+ void i486_wbinvd();
+ void i486_cmpxchg_rm8_r8();
+ void i486_cmpxchg_rm16_r16();
+ void i486_cmpxchg_rm32_r32();
+ void i486_xadd_rm8_r8();
+ void i486_xadd_rm16_r16();
+ void i486_xadd_rm32_r32();
+ void i486_group0F01_16();
+ void i486_group0F01_32();
+ void i486_bswap_eax();
+ void i486_bswap_ecx();
+ void i486_bswap_edx();
+ void i486_bswap_ebx();
+ void i486_bswap_esp();
+ void i486_bswap_ebp();
+ void i486_bswap_esi();
+ void i486_bswap_edi();
+ void i486_mov_cr_r32();
+ inline void MMXPROLOG();
+ inline void READMMX(UINT32 ea,MMX_REG &r);
+ inline void WRITEMMX(UINT32 ea,MMX_REG &r);
+ inline void READXMM(UINT32 ea,XMM_REG &r);
+ inline void WRITEXMM(UINT32 ea,XMM_REG &r);
+ inline void READXMM_LO64(UINT32 ea,XMM_REG &r);
+ inline void WRITEXMM_LO64(UINT32 ea,XMM_REG &r);
+ inline void READXMM_HI64(UINT32 ea,XMM_REG &r);
+ inline void WRITEXMM_HI64(UINT32 ea,XMM_REG &r);
+ void pentium_rdmsr();
+ void pentium_wrmsr();
+ void pentium_rdtsc();
+ void pentium_ud2();
+ void pentium_rsm();
+ void pentium_prefetch_m8();
+ void pentium_cmovo_r16_rm16();
+ void pentium_cmovo_r32_rm32();
+ void pentium_cmovno_r16_rm16();
+ void pentium_cmovno_r32_rm32();
+ void pentium_cmovb_r16_rm16();
+ void pentium_cmovb_r32_rm32();
+ void pentium_cmovae_r16_rm16();
+ void pentium_cmovae_r32_rm32();
+ void pentium_cmove_r16_rm16();
+ void pentium_cmove_r32_rm32();
+ void pentium_cmovne_r16_rm16();
+ void pentium_cmovne_r32_rm32();
+ void pentium_cmovbe_r16_rm16();
+ void pentium_cmovbe_r32_rm32();
+ void pentium_cmova_r16_rm16();
+ void pentium_cmova_r32_rm32();
+ void pentium_cmovs_r16_rm16();
+ void pentium_cmovs_r32_rm32();
+ void pentium_cmovns_r16_rm16();
+ void pentium_cmovns_r32_rm32();
+ void pentium_cmovp_r16_rm16();
+ void pentium_cmovp_r32_rm32();
+ void pentium_cmovnp_r16_rm16();
+ void pentium_cmovnp_r32_rm32();
+ void pentium_cmovl_r16_rm16();
+ void pentium_cmovl_r32_rm32();
+ void pentium_cmovge_r16_rm16();
+ void pentium_cmovge_r32_rm32();
+ void pentium_cmovle_r16_rm16();
+ void pentium_cmovle_r32_rm32();
+ void pentium_cmovg_r16_rm16();
+ void pentium_cmovg_r32_rm32();
+ void pentium_movnti_m16_r16();
+ void pentium_movnti_m32_r32();
+ void i386_cyrix_unknown();
+ void pentium_cmpxchg8b_m64();
+ void pentium_movntq_m64_r64();
+ void pentium_maskmovq_r64_r64();
+ void pentium_popcnt_r16_rm16();
+ void pentium_popcnt_r32_rm32();
+ void pentium_tzcnt_r16_rm16();
+ void pentium_tzcnt_r32_rm32();
+ void mmx_group_0f71();
+ void mmx_group_0f72();
+ void mmx_group_0f73();
+ void mmx_psrlw_r64_rm64();
+ void mmx_psrld_r64_rm64();
+ void mmx_psrlq_r64_rm64();
+ void mmx_paddq_r64_rm64();
+ void mmx_pmullw_r64_rm64();
+ void mmx_psubusb_r64_rm64();
+ void mmx_psubusw_r64_rm64();
+ void mmx_pand_r64_rm64();
+ void mmx_paddusb_r64_rm64();
+ void mmx_paddusw_r64_rm64();
+ void mmx_pandn_r64_rm64();
+ void mmx_psraw_r64_rm64();
+ void mmx_psrad_r64_rm64();
+ void mmx_pmulhw_r64_rm64();
+ void mmx_psubsb_r64_rm64();
+ void mmx_psubsw_r64_rm64();
+ void mmx_por_r64_rm64();
+ void mmx_paddsb_r64_rm64();
+ void mmx_paddsw_r64_rm64();
+ void mmx_pxor_r64_rm64();
+ void mmx_psllw_r64_rm64();
+ void mmx_pslld_r64_rm64();
+ void mmx_psllq_r64_rm64();
+ void mmx_pmaddwd_r64_rm64();
+ void mmx_psubb_r64_rm64();
+ void mmx_psubw_r64_rm64();
+ void mmx_psubd_r64_rm64();
+ void mmx_paddb_r64_rm64();
+ void mmx_paddw_r64_rm64();
+ void mmx_paddd_r64_rm64();
+ void mmx_emms();
+ void mmx_movd_r64_rm32();
+ void mmx_movq_r64_rm64();
+ void mmx_movd_rm32_r64();
+ void mmx_movq_rm64_r64();
+ void mmx_pcmpeqb_r64_rm64();
+ void mmx_pcmpeqw_r64_rm64();
+ void mmx_pcmpeqd_r64_rm64();
+ void mmx_pshufw_r64_rm64_i8();
+ void mmx_punpcklbw_r64_r64m32();
+ void mmx_punpcklwd_r64_r64m32();
+ void mmx_punpckldq_r64_r64m32();
+ void mmx_packsswb_r64_rm64();
+ void mmx_pcmpgtb_r64_rm64();
+ void mmx_pcmpgtw_r64_rm64();
+ void mmx_pcmpgtd_r64_rm64();
+ void mmx_packuswb_r64_rm64();
+ void mmx_punpckhbw_r64_rm64();
+ void mmx_punpckhwd_r64_rm64();
+ void mmx_punpckhdq_r64_rm64();
+ void mmx_packssdw_r64_rm64();
+ void sse_sse_group0fae();
+ void sse_cvttps2dq_r128_rm128();
+ void sse_cvtss2sd_r128_r128m32();
+ void sse_cvttss2si_r32_r128m32();
+ void sse_cvtss2si_r32_r128m32();
+ void sse_cvtsi2ss_r128_rm32();
+ void sse_cvtpi2ps_r128_rm64();
+ void sse_cvttps2pi_r64_r128m64();
+ void sse_cvtps2pi_r64_r128m64();
+ void sse_cvtps2pd_r128_r128m64();
+ void sse_cvtdq2ps_r128_rm128();
+ void sse_cvtdq2pd_r128_r128m64();
+ void sse_movss_r128_rm128();
+ void sse_movss_rm128_r128();
+ void sse_movsldup_r128_rm128();
+ void sse_movshdup_r128_rm128();
+ void sse_movaps_r128_rm128();
+ void sse_movaps_rm128_r128();
+ void sse_movups_r128_rm128();
+ void sse_movups_rm128_r128();
+ void sse_movlps_r128_m64();
+ void sse_movlps_m64_r128();
+ void sse_movhps_r128_m64();
+ void sse_movhps_m64_r128();
+ void sse_movntps_m128_r128();
+ void sse_movmskps_r16_r128();
+ void sse_movmskps_r32_r128();
+ void sse_movq2dq_r128_r64();
+ void sse_movdqu_r128_rm128();
+ void sse_movdqu_rm128_r128();
+ void sse_movq_r128_r128m64();
+ void sse_pmovmskb_r16_r64();
+ void sse_pmovmskb_r32_r64();
+ void sse_xorps();
+ void sse_addps();
+ void sse_sqrtps_r128_rm128();
+ void sse_rsqrtps_r128_rm128();
+ void sse_rcpps_r128_rm128();
+ void sse_andps_r128_rm128();
+ void sse_andnps_r128_rm128();
+ void sse_orps_r128_rm128();
+ void sse_mulps();
+ void sse_subps();
+ void sse_minps();
+ void sse_divps();
+ void sse_maxps();
+ void sse_maxss_r128_r128m32();
+ void sse_addss();
+ void sse_subss();
+ void sse_mulss();
+ void sse_divss();
+ void sse_rcpss_r128_r128m32();
+ void sse_sqrtss_r128_r128m32();
+ void sse_rsqrtss_r128_r128m32();
+ void sse_minss_r128_r128m32();
+ void sse_comiss_r128_r128m32();
+ void sse_ucomiss_r128_r128m32();
+ void sse_shufps();
+ void sse_unpcklps_r128_rm128();
+ void sse_unpckhps_r128_rm128();
+ void sse_cmpps_r128_rm128_i8();
+ void sse_cmpss_r128_r128m32_i8();
+ void sse_pinsrw_r64_r16m16_i8();
+ void sse_pinsrw_r64_r32m16_i8();
+ void sse_pextrw_r16_r64_i8();
+ void sse_pextrw_r32_r64_i8();
+ void sse_pminub_r64_rm64();
+ void sse_pmaxub_r64_rm64();
+ void sse_pavgb_r64_rm64();
+ void sse_pavgw_r64_rm64();
+ void sse_pmulhuw_r64_rm64();
+ void sse_pminsw_r64_rm64();
+ void sse_pmaxsw_r64_rm64();
+ void sse_pmuludq_r64_rm64();
+ void sse_psadbw_r64_rm64();
+ void sse_psubq_r64_rm64();
+ void sse_pshufhw_r128_rm128_i8();
+ inline void sse_predicate_compare_single(UINT8 imm8, XMM_REG d, XMM_REG s);
+ inline void sse_predicate_compare_single_scalar(UINT8 imm8, XMM_REG d, XMM_REG s);
+ inline floatx80 READ80(UINT32 ea);
+ inline void WRITE80(UINT32 ea, floatx80 t);
+ inline void x87_set_stack_top(int top);
+ inline void x87_set_tag(int reg, int tag);
+ void x87_write_stack(int i, floatx80 value, int update_tag);
+ inline void x87_set_stack_underflow();
+ inline void x87_set_stack_overflow();
+ int x87_inc_stack();
+ int x87_dec_stack();
+ int x87_check_exceptions();
+ inline void x87_write_cw(UINT16 cw);
+ void x87_reset();
+ floatx80 x87_add(floatx80 a, floatx80 b);
+ floatx80 x87_sub(floatx80 a, floatx80 b);
+ floatx80 x87_mul(floatx80 a, floatx80 b);
+ floatx80 x87_div(floatx80 a, floatx80 b);
+ void x87_fadd_m32real(UINT8 modrm);
+ void x87_fadd_m64real(UINT8 modrm);
+ void x87_fadd_st_sti(UINT8 modrm);
+ void x87_fadd_sti_st(UINT8 modrm);
+ void x87_faddp(UINT8 modrm);
+ void x87_fiadd_m32int(UINT8 modrm);
+ void x87_fiadd_m16int(UINT8 modrm);
+ void x87_fsub_m32real(UINT8 modrm);
+ void x87_fsub_m64real(UINT8 modrm);
+ void x87_fsub_st_sti(UINT8 modrm);
+ void x87_fsub_sti_st(UINT8 modrm);
+ void x87_fsubp(UINT8 modrm);
+ void x87_fisub_m32int(UINT8 modrm);
+ void x87_fisub_m16int(UINT8 modrm);
+ void x87_fsubr_m32real(UINT8 modrm);
+ void x87_fsubr_m64real(UINT8 modrm);
+ void x87_fsubr_st_sti(UINT8 modrm);
+ void x87_fsubr_sti_st(UINT8 modrm);
+ void x87_fsubrp(UINT8 modrm);
+ void x87_fisubr_m32int(UINT8 modrm);
+ void x87_fisubr_m16int(UINT8 modrm);
+ void x87_fdiv_m32real(UINT8 modrm);
+ void x87_fdiv_m64real(UINT8 modrm);
+ void x87_fdiv_st_sti(UINT8 modrm);
+ void x87_fdiv_sti_st(UINT8 modrm);
+ void x87_fdivp(UINT8 modrm);
+ void x87_fidiv_m32int(UINT8 modrm);
+ void x87_fidiv_m16int(UINT8 modrm);
+ void x87_fdivr_m32real(UINT8 modrm);
+ void x87_fdivr_m64real(UINT8 modrm);
+ void x87_fdivr_st_sti(UINT8 modrm);
+ void x87_fdivr_sti_st(UINT8 modrm);
+ void x87_fdivrp(UINT8 modrm);
+ void x87_fidivr_m32int(UINT8 modrm);
+ void x87_fidivr_m16int(UINT8 modrm);
+ void x87_fmul_m32real(UINT8 modrm);
+ void x87_fmul_m64real(UINT8 modrm);
+ void x87_fmul_st_sti(UINT8 modrm);
+ void x87_fmul_sti_st(UINT8 modrm);
+ void x87_fmulp(UINT8 modrm);
+ void x87_fimul_m32int(UINT8 modrm);
+ void x87_fimul_m16int(UINT8 modrm);
+ void x87_fprem(UINT8 modrm);
+ void x87_fprem1(UINT8 modrm);
+ void x87_fsqrt(UINT8 modrm);
+ void x87_f2xm1(UINT8 modrm);
+ void x87_fyl2x(UINT8 modrm);
+ void x87_fyl2xp1(UINT8 modrm);
+ void x87_fptan(UINT8 modrm);
+ void x87_fpatan(UINT8 modrm);
+ void x87_fsin(UINT8 modrm);
+ void x87_fcos(UINT8 modrm);
+ void x87_fsincos(UINT8 modrm);
+ void x87_fld_m32real(UINT8 modrm);
+ void x87_fld_m64real(UINT8 modrm);
+ void x87_fld_m80real(UINT8 modrm);
+ void x87_fld_sti(UINT8 modrm);
+ void x87_fild_m16int(UINT8 modrm);
+ void x87_fild_m32int(UINT8 modrm);
+ void x87_fild_m64int(UINT8 modrm);
+ void x87_fbld(UINT8 modrm);
+ void x87_fst_m32real(UINT8 modrm);
+ void x87_fst_m64real(UINT8 modrm);
+ void x87_fst_sti(UINT8 modrm);
+ void x87_fstp_m32real(UINT8 modrm);
+ void x87_fstp_m64real(UINT8 modrm);
+ void x87_fstp_m80real(UINT8 modrm);
+ void x87_fstp_sti(UINT8 modrm);
+ void x87_fist_m16int(UINT8 modrm);
+ void x87_fist_m32int(UINT8 modrm);
+ void x87_fistp_m16int(UINT8 modrm);
+ void x87_fistp_m32int(UINT8 modrm);
+ void x87_fistp_m64int(UINT8 modrm);
+ void x87_fbstp(UINT8 modrm);
+ void x87_fld1(UINT8 modrm);
+ void x87_fldl2t(UINT8 modrm);
+ void x87_fldl2e(UINT8 modrm);
+ void x87_fldpi(UINT8 modrm);
+ void x87_fldlg2(UINT8 modrm);
+ void x87_fldln2(UINT8 modrm);
+ void x87_fldz(UINT8 modrm);
+ void x87_fnop(UINT8 modrm);
+ void x87_fchs(UINT8 modrm);
+ void x87_fabs(UINT8 modrm);
+ void x87_fscale(UINT8 modrm);
+ void x87_frndint(UINT8 modrm);
+ void x87_fxtract(UINT8 modrm);
+ void x87_ftst(UINT8 modrm);
+ void x87_fxam(UINT8 modrm);
+ void x87_ficom_m16int(UINT8 modrm);
+ void x87_ficom_m32int(UINT8 modrm);
+ void x87_ficomp_m16int(UINT8 modrm);
+ void x87_ficomp_m32int(UINT8 modrm);
+ void x87_fcom_m32real(UINT8 modrm);
+ void x87_fcom_m64real(UINT8 modrm);
+ void x87_fcom_sti(UINT8 modrm);
+ void x87_fcomp_m32real(UINT8 modrm);
+ void x87_fcomp_m64real(UINT8 modrm);
+ void x87_fcomp_sti(UINT8 modrm);
+ void x87_fcomip_sti(UINT8 modrm);
+ void x87_fcompp(UINT8 modrm);
+ void x87_fucom_sti(UINT8 modrm);
+ void x87_fucomp_sti(UINT8 modrm);
+ void x87_fucompp(UINT8 modrm);
+ void x87_fdecstp(UINT8 modrm);
+ void x87_fincstp(UINT8 modrm);
+ void x87_fclex(UINT8 modrm);
+ void x87_ffree(UINT8 modrm);
+ void x87_finit(UINT8 modrm);
+ void x87_fldcw(UINT8 modrm);
+ void x87_fstcw(UINT8 modrm);
+ void x87_fldenv(UINT8 modrm);
+ void x87_fstenv(UINT8 modrm);
+ void x87_fsave(UINT8 modrm);
+ void x87_frstor(UINT8 modrm);
+ void x87_fxch(UINT8 modrm);
+ void x87_fxch_sti(UINT8 modrm);
+ void x87_fstsw_ax(UINT8 modrm);
+ void x87_fstsw_m2byte(UINT8 modrm);
+ void x87_invalid(UINT8 modrm);
+ void i386_x87_group_d8();
+ void i386_x87_group_d9();
+ void i386_x87_group_da();
+ void i386_x87_group_db();
+ void i386_x87_group_dc();
+ void i386_x87_group_dd();
+ void i386_x87_group_de();
+ void i386_x87_group_df();
+ void build_x87_opcode_table_d8();
+ void build_x87_opcode_table_d9();
+ void build_x87_opcode_table_da();
+ void build_x87_opcode_table_db();
+ void build_x87_opcode_table_dc();
+ void build_x87_opcode_table_dd();
+ void build_x87_opcode_table_de();
+ void build_x87_opcode_table_df();
+ void build_x87_opcode_table();
+ void i386_postload();
+ void i386_common_init(int tlbsize);
+ void build_opcode_table(UINT32 features);
+ void pentium_smi();
+ void zero_state();
+ void i386_set_a20_line(int state);
+
+};
+
+
+class i386SX_device : public i386_device
+{
+public:
+ // construction/destruction
+ i386SX_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+};
+
+
+class i486_device : public i386_device
+{
+public:
+ // construction/destruction
+ i486_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+protected:
+ virtual void device_start();
+ virtual void device_reset();
+};
+
+
+class pentium_device : public i386_device
+{
+public:
+ // construction/destruction
+ pentium_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ pentium_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
+
+protected:
+ virtual void execute_set_input(int inputnum, int state);
+ virtual void device_start();
+ virtual void device_reset();
+};
+
+
+class mediagx_device : public i386_device
+{
+public:
+ // construction/destruction
+ mediagx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+protected:
+ virtual void device_start();
+ virtual void device_reset();
+};
+
+
+class pentium_pro_device : public pentium_device
+{
+public:
+ // construction/destruction
+ pentium_pro_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+protected:
+ virtual void device_start();
+ virtual void device_reset();
+};
+
+
+class pentium_mmx_device : public pentium_device
+{
+public:
+ // construction/destruction
+ pentium_mmx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+protected:
+ virtual void device_start();
+ virtual void device_reset();
+};
+
+
+class pentium2_device : public pentium_device
+{
+public:
+ // construction/destruction
+ pentium2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+protected:
+ virtual void device_start();
+ virtual void device_reset();
+};
+
+
+class pentium3_device : public pentium_device
+{
+public:
+ // construction/destruction
+ pentium3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+protected:
+ virtual void device_start();
+ virtual void device_reset();
+};
+
+
+class pentium4_device : public pentium_device
+{
+public:
+ // construction/destruction
+ pentium4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+protected:
+ virtual void device_start();
+ virtual void device_reset();
+};
+
+
+extern const device_type I386;
+extern const device_type I386SX;
+extern const device_type I486;
+extern const device_type PENTIUM;
+extern const device_type MEDIAGX;
+extern const device_type PENTIUM_PRO;
+extern const device_type PENTIUM_MMX;
+extern const device_type PENTIUM2;
+extern const device_type PENTIUM3;
+extern const device_type PENTIUM4;
#endif /* __I386INTF_H__ */
diff --git a/src/emu/cpu/i386/i386op16.c b/src/emu/cpu/i386/i386op16.c
index 35b0e9571a7..c1a63195f16 100644
--- a/src/emu/cpu/i386/i386op16.c
+++ b/src/emu/cpu/i386/i386op16.c
@@ -1,58 +1,58 @@
-static UINT16 I386OP(shift_rotate16)(i386_state *cpustate, UINT8 modrm, UINT32 value, UINT8 shift)
+UINT16 i386_device::i386_shift_rotate16(UINT8 modrm, UINT32 value, UINT8 shift)
{
UINT32 src = value & 0xffff;
UINT16 dst = value;
if( shift == 0 ) {
- CYCLES_RM(cpustate,modrm, 3, 7);
+ CYCLES_RM(modrm, 3, 7);
} else if( shift == 1 ) {
switch( (modrm >> 3) & 0x7 )
{
case 0: /* ROL rm16, 1 */
- cpustate->CF = (src & 0x8000) ? 1 : 0;
- dst = (src << 1) + cpustate->CF;
- cpustate->OF = ((src ^ dst) & 0x8000) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (src & 0x8000) ? 1 : 0;
+ dst = (src << 1) + m_CF;
+ m_OF = ((src ^ dst) & 0x8000) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 1: /* ROR rm16, 1 */
- cpustate->CF = (src & 0x1) ? 1 : 0;
- dst = (cpustate->CF << 15) | (src >> 1);
- cpustate->OF = ((src ^ dst) & 0x8000) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (src & 0x1) ? 1 : 0;
+ dst = (m_CF << 15) | (src >> 1);
+ m_OF = ((src ^ dst) & 0x8000) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 2: /* RCL rm16, 1 */
- dst = (src << 1) + cpustate->CF;
- cpustate->CF = (src & 0x8000) ? 1 : 0;
- cpustate->OF = ((src ^ dst) & 0x8000) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ dst = (src << 1) + m_CF;
+ m_CF = (src & 0x8000) ? 1 : 0;
+ m_OF = ((src ^ dst) & 0x8000) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 3: /* RCR rm16, 1 */
- dst = (cpustate->CF << 15) | (src >> 1);
- cpustate->CF = src & 0x1;
- cpustate->OF = ((src ^ dst) & 0x8000) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ dst = (m_CF << 15) | (src >> 1);
+ m_CF = src & 0x1;
+ m_OF = ((src ^ dst) & 0x8000) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 4: /* SHL/SAL rm16, 1 */
case 6:
dst = src << 1;
- cpustate->CF = (src & 0x8000) ? 1 : 0;
- cpustate->OF = (((cpustate->CF << 15) ^ dst) & 0x8000) ? 1 : 0;
+ m_CF = (src & 0x8000) ? 1 : 0;
+ m_OF = (((m_CF << 15) ^ dst) & 0x8000) ? 1 : 0;
SetSZPF16(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 5: /* SHR rm16, 1 */
dst = src >> 1;
- cpustate->CF = src & 0x1;
- cpustate->OF = (dst & 0x8000) ? 1 : 0;
+ m_CF = src & 0x1;
+ m_OF = (dst & 0x8000) ? 1 : 0;
SetSZPF16(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 7: /* SAR rm16, 1 */
dst = (INT16)(src) >> 1;
- cpustate->CF = src & 0x1;
- cpustate->OF = 0;
+ m_CF = src & 0x1;
+ m_OF = 0;
SetSZPF16(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
}
} else {
@@ -63,74 +63,74 @@ static UINT16 I386OP(shift_rotate16)(i386_state *cpustate, UINT8 modrm, UINT32 v
{
if(shift & 16)
{
- cpustate->CF = src & 1;
- cpustate->OF = (src & 1) ^ ((src >> 15) & 1);
+ m_CF = src & 1;
+ m_OF = (src & 1) ^ ((src >> 15) & 1);
}
break;
}
shift &= 15;
dst = ((src & ((UINT16)0xffff >> shift)) << shift) |
((src & ((UINT16)0xffff << (16-shift))) >> (16-shift));
- cpustate->CF = dst & 0x1;
- cpustate->OF = (dst & 1) ^ (dst >> 15);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = dst & 0x1;
+ m_OF = (dst & 1) ^ (dst >> 15);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 1: /* ROR rm16, i8 */
if(!(shift & 15))
{
if(shift & 16)
{
- cpustate->CF = (src >> 15) & 1;
- cpustate->OF = ((src >> 15) & 1) ^ ((src >> 14) & 1);
+ m_CF = (src >> 15) & 1;
+ m_OF = ((src >> 15) & 1) ^ ((src >> 14) & 1);
}
break;
}
shift &= 15;
dst = ((src & ((UINT16)0xffff << shift)) >> shift) |
((src & ((UINT16)0xffff >> (16-shift))) << (16-shift));
- cpustate->CF = (dst >> 15) & 1;
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (dst >> 15) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 2: /* RCL rm16, i8 */
shift %= 17;
dst = ((src & ((UINT16)0xffff >> shift)) << shift) |
((src & ((UINT16)0xffff << (17-shift))) >> (17-shift)) |
- (cpustate->CF << (shift-1));
- if(shift) cpustate->CF = (src >> (16-shift)) & 0x1;
- cpustate->OF = cpustate->CF ^ ((dst >> 15) & 1);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ (m_CF << (shift-1));
+ if(shift) m_CF = (src >> (16-shift)) & 0x1;
+ m_OF = m_CF ^ ((dst >> 15) & 1);
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 3: /* RCR rm16, i8 */
shift %= 17;
dst = ((src & ((UINT16)0xffff << shift)) >> shift) |
((src & ((UINT16)0xffff >> (16-shift))) << (17-shift)) |
- (cpustate->CF << (16-shift));
- if(shift) cpustate->CF = (src >> (shift-1)) & 0x1;
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ (m_CF << (16-shift));
+ if(shift) m_CF = (src >> (shift-1)) & 0x1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 4: /* SHL/SAL rm16, i8 */
case 6:
shift &= 31;
dst = src << shift;
- cpustate->CF = (shift <= 16) && (src & (1 << (16-shift)));
+ m_CF = (shift <= 16) && (src & (1 << (16-shift)));
SetSZPF16(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 5: /* SHR rm16, i8 */
shift &= 31;
dst = src >> shift;
- cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (src & (1 << (shift-1))) ? 1 : 0;
SetSZPF16(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 7: /* SAR rm16, i8 */
shift &= 31;
dst = (INT16)src >> shift;
- cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (src & (1 << (shift-1))) ? 1 : 0;
SetSZPF16(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
}
@@ -140,529 +140,529 @@ static UINT16 I386OP(shift_rotate16)(i386_state *cpustate, UINT8 modrm, UINT32 v
-static void I386OP(adc_rm16_r16)(i386_state *cpustate) // Opcode 0x11
+void i386_device::i386_adc_rm16_r16() // Opcode 0x11
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
+ dst = ADC16(dst, src, m_CF);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ16(ea);
+ dst = ADC16(dst, src, m_CF);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(adc_r16_rm16)(i386_state *cpustate) // Opcode 0x13
+void i386_device::i386_adc_r16_rm16() // Opcode 0x13
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
dst = LOAD_REG16(modrm);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
+ dst = ADC16(dst, src, m_CF);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
dst = LOAD_REG16(modrm);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
+ dst = ADC16(dst, src, m_CF);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(adc_ax_i16)(i386_state *cpustate) // Opcode 0x15
+void i386_device::i386_adc_ax_i16() // Opcode 0x15
{
UINT16 src, dst;
- src = FETCH16(cpustate);
+ src = FETCH16();
dst = REG16(AX);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
+ dst = ADC16(dst, src, m_CF);
REG16(AX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(add_rm16_r16)(i386_state *cpustate) // Opcode 0x01
+void i386_device::i386_add_rm16_r16() // Opcode 0x01
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
- dst = ADD16(cpustate,dst, src);
+ dst = ADD16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
- dst = ADD16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ16(ea);
+ dst = ADD16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(add_r16_rm16)(i386_state *cpustate) // Opcode 0x03
+void i386_device::i386_add_r16_rm16() // Opcode 0x03
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
dst = LOAD_REG16(modrm);
- dst = ADD16(cpustate,dst, src);
+ dst = ADD16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
dst = LOAD_REG16(modrm);
- dst = ADD16(cpustate,dst, src);
+ dst = ADD16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(add_ax_i16)(i386_state *cpustate) // Opcode 0x05
+void i386_device::i386_add_ax_i16() // Opcode 0x05
{
UINT16 src, dst;
- src = FETCH16(cpustate);
+ src = FETCH16();
dst = REG16(AX);
- dst = ADD16(cpustate,dst, src);
+ dst = ADD16(dst, src);
REG16(AX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(and_rm16_r16)(i386_state *cpustate) // Opcode 0x21
+void i386_device::i386_and_rm16_r16() // Opcode 0x21
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
- dst = AND16(cpustate,dst, src);
+ dst = AND16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
- dst = AND16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ16(ea);
+ dst = AND16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(and_r16_rm16)(i386_state *cpustate) // Opcode 0x23
+void i386_device::i386_and_r16_rm16() // Opcode 0x23
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
dst = LOAD_REG16(modrm);
- dst = AND16(cpustate,dst, src);
+ dst = AND16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
dst = LOAD_REG16(modrm);
- dst = AND16(cpustate,dst, src);
+ dst = AND16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(and_ax_i16)(i386_state *cpustate) // Opcode 0x25
+void i386_device::i386_and_ax_i16() // Opcode 0x25
{
UINT16 src, dst;
- src = FETCH16(cpustate);
+ src = FETCH16();
dst = REG16(AX);
- dst = AND16(cpustate,dst, src);
+ dst = AND16(dst, src);
REG16(AX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(bsf_r16_rm16)(i386_state *cpustate) // Opcode 0x0f bc
+void i386_device::i386_bsf_r16_rm16() // Opcode 0x0f bc
{
UINT16 src, dst, temp;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
}
dst = 0;
if( src == 0 ) {
- cpustate->ZF = 1;
+ m_ZF = 1;
} else {
- cpustate->ZF = 0;
+ m_ZF = 0;
temp = 0;
while( (src & (1 << temp)) == 0 ) {
temp++;
dst = temp;
- CYCLES(cpustate,CYCLES_BSF);
+ CYCLES(CYCLES_BSF);
}
STORE_REG16(modrm, dst);
}
- CYCLES(cpustate,CYCLES_BSF_BASE);
+ CYCLES(CYCLES_BSF_BASE);
}
-static void I386OP(bsr_r16_rm16)(i386_state *cpustate) // Opcode 0x0f bd
+void i386_device::i386_bsr_r16_rm16() // Opcode 0x0f bd
{
UINT16 src, dst, temp;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
}
dst = 0;
if( src == 0 ) {
- cpustate->ZF = 1;
+ m_ZF = 1;
} else {
- cpustate->ZF = 0;
+ m_ZF = 0;
dst = temp = 15;
while( (src & (1 << temp)) == 0 ) {
temp--;
dst = temp;
- CYCLES(cpustate,CYCLES_BSR);
+ CYCLES(CYCLES_BSR);
}
STORE_REG16(modrm, dst);
}
- CYCLES(cpustate,CYCLES_BSR_BASE);
+ CYCLES(CYCLES_BSR_BASE);
}
-static void I386OP(bt_rm16_r16)(i386_state *cpustate) // Opcode 0x0f a3
+void i386_device::i386_bt_rm16_r16() // Opcode 0x0f a3
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 bit = LOAD_REG16(modrm);
if( dst & (1 << (bit & 0xf)) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
- CYCLES(cpustate,CYCLES_BT_REG_REG);
+ CYCLES(CYCLES_BT_REG_REG);
} else {
UINT8 segment;
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,&segment);
+ UINT32 ea = GetNonTranslatedEA(modrm,&segment);
UINT16 bit = LOAD_REG16(modrm);
ea += 2*(bit/16);
- ea = i386_translate(cpustate,segment,(cpustate->address_size)?ea:(ea&0xffff),0);
+ ea = i386_translate(segment,(m_address_size)?ea:(ea&0xffff),0);
bit %= 16;
- UINT16 dst = READ16(cpustate,ea);
+ UINT16 dst = READ16(ea);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
- CYCLES(cpustate,CYCLES_BT_REG_MEM);
+ CYCLES(CYCLES_BT_REG_MEM);
}
}
-static void I386OP(btc_rm16_r16)(i386_state *cpustate) // Opcode 0x0f bb
+void i386_device::i386_btc_rm16_r16() // Opcode 0x0f bb
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 bit = LOAD_REG16(modrm);
if( dst & (1 << (bit & 0xf)) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst ^= (1 << (bit & 0xf));
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_BTC_REG_REG);
+ CYCLES(CYCLES_BTC_REG_REG);
} else {
UINT8 segment;
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,&segment);
+ UINT32 ea = GetNonTranslatedEA(modrm,&segment);
UINT16 bit = LOAD_REG16(modrm);
ea += 2*(bit/16);
- ea = i386_translate(cpustate,segment,(cpustate->address_size)?ea:(ea&0xffff),1);
+ ea = i386_translate(segment,(m_address_size)?ea:(ea&0xffff),1);
bit %= 16;
- UINT16 dst = READ16(cpustate,ea);
+ UINT16 dst = READ16(ea);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst ^= (1 << bit);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTC_REG_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_BTC_REG_MEM);
}
}
-static void I386OP(btr_rm16_r16)(i386_state *cpustate) // Opcode 0x0f b3
+void i386_device::i386_btr_rm16_r16() // Opcode 0x0f b3
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 bit = LOAD_REG16(modrm);
if( dst & (1 << (bit & 0xf)) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst &= ~(1 << (bit & 0xf));
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_BTR_REG_REG);
+ CYCLES(CYCLES_BTR_REG_REG);
} else {
UINT8 segment;
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,&segment);
+ UINT32 ea = GetNonTranslatedEA(modrm,&segment);
UINT16 bit = LOAD_REG16(modrm);
ea += 2*(bit/16);
- ea = i386_translate(cpustate,segment,(cpustate->address_size)?ea:(ea&0xffff),1);
+ ea = i386_translate(segment,(m_address_size)?ea:(ea&0xffff),1);
bit %= 16;
- UINT16 dst = READ16(cpustate,ea);
+ UINT16 dst = READ16(ea);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst &= ~(1 << bit);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTR_REG_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_BTR_REG_MEM);
}
}
-static void I386OP(bts_rm16_r16)(i386_state *cpustate) // Opcode 0x0f ab
+void i386_device::i386_bts_rm16_r16() // Opcode 0x0f ab
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 bit = LOAD_REG16(modrm);
if( dst & (1 << (bit & 0xf)) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst |= (1 << (bit & 0xf));
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_BTS_REG_REG);
+ CYCLES(CYCLES_BTS_REG_REG);
} else {
UINT8 segment;
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,&segment);
+ UINT32 ea = GetNonTranslatedEA(modrm,&segment);
UINT16 bit = LOAD_REG16(modrm);
ea += 2*(bit/16);
- ea = i386_translate(cpustate,segment,(cpustate->address_size)?ea:(ea&0xffff),1);
+ ea = i386_translate(segment,(m_address_size)?ea:(ea&0xffff),1);
bit %= 16;
- UINT16 dst = READ16(cpustate,ea);
+ UINT16 dst = READ16(ea);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst |= (1 << bit);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTS_REG_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_BTS_REG_MEM);
}
}
-static void I386OP(call_abs16)(i386_state *cpustate) // Opcode 0x9a
+void i386_device::i386_call_abs16() // Opcode 0x9a
{
- UINT16 offset = FETCH16(cpustate);
- UINT16 ptr = FETCH16(cpustate);
+ UINT16 offset = FETCH16();
+ UINT16 ptr = FETCH16();
if( PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_call(cpustate,ptr,offset,0,0);
+ i386_protected_mode_call(ptr,offset,0,0);
}
else
{
- PUSH16(cpustate, cpustate->sreg[CS].selector );
- PUSH16(cpustate, cpustate->eip );
- cpustate->sreg[CS].selector = ptr;
- cpustate->performed_intersegment_jump = 1;
- cpustate->eip = offset;
- i386_load_segment_descriptor(cpustate,CS);
+ PUSH16(m_sreg[CS].selector );
+ PUSH16(m_eip );
+ m_sreg[CS].selector = ptr;
+ m_performed_intersegment_jump = 1;
+ m_eip = offset;
+ i386_load_segment_descriptor(CS);
}
- CYCLES(cpustate,CYCLES_CALL_INTERSEG); /* TODO: Timing = 17 + m */
- CHANGE_PC(cpustate,cpustate->eip);
+ CYCLES(CYCLES_CALL_INTERSEG); /* TODO: Timing = 17 + m */
+ CHANGE_PC(m_eip);
}
-static void I386OP(call_rel16)(i386_state *cpustate) // Opcode 0xe8
+void i386_device::i386_call_rel16() // Opcode 0xe8
{
- INT16 disp = FETCH16(cpustate);
+ INT16 disp = FETCH16();
- PUSH16(cpustate, cpustate->eip );
- if (cpustate->sreg[CS].d)
+ PUSH16(m_eip );
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_CALL); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_CALL); /* TODO: Timing = 7 + m */
}
-static void I386OP(cbw)(i386_state *cpustate) // Opcode 0x98
+void i386_device::i386_cbw() // Opcode 0x98
{
REG16(AX) = (INT16)((INT8)REG8(AL));
- CYCLES(cpustate,CYCLES_CBW);
+ CYCLES(CYCLES_CBW);
}
-static void I386OP(cmp_rm16_r16)(i386_state *cpustate) // Opcode 0x39
+void i386_device::i386_cmp_rm16_r16() // Opcode 0x39
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
+ UINT32 ea = GetEA(modrm,0);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_MEM);
+ dst = READ16(ea);
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_REG_MEM);
}
}
-static void I386OP(cmp_r16_rm16)(i386_state *cpustate) // Opcode 0x3b
+void i386_device::i386_cmp_r16_rm16() // Opcode 0x3b
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
dst = LOAD_REG16(modrm);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
dst = LOAD_REG16(modrm);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_MEM_REG);
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_MEM_REG);
}
}
-static void I386OP(cmp_ax_i16)(i386_state *cpustate) // Opcode 0x3d
+void i386_device::i386_cmp_ax_i16() // Opcode 0x3d
{
UINT16 src, dst;
- src = FETCH16(cpustate);
+ src = FETCH16();
dst = REG16(AX);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_IMM_ACC);
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_IMM_ACC);
}
-static void I386OP(cmpsw)(i386_state *cpustate) // Opcode 0xa7
+void i386_device::i386_cmpsw() // Opcode 0xa7
{
UINT32 eas, ead;
UINT16 src, dst;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 0 );
- src = READ16(cpustate,eas);
- dst = READ16(cpustate,ead);
- SUB16(cpustate,src,dst);
- BUMP_SI(cpustate,2);
- BUMP_DI(cpustate,2);
- CYCLES(cpustate,CYCLES_CMPS);
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 0 );
+ src = READ16(eas);
+ dst = READ16(ead);
+ SUB16(src,dst);
+ BUMP_SI(2);
+ BUMP_DI(2);
+ CYCLES(CYCLES_CMPS);
}
-static void I386OP(cwd)(i386_state *cpustate) // Opcode 0x99
+void i386_device::i386_cwd() // Opcode 0x99
{
if( REG16(AX) & 0x8000 ) {
REG16(DX) = 0xffff;
} else {
REG16(DX) = 0x0000;
}
- CYCLES(cpustate,CYCLES_CWD);
+ CYCLES(CYCLES_CWD);
}
-static void I386OP(dec_ax)(i386_state *cpustate) // Opcode 0x48
+void i386_device::i386_dec_ax() // Opcode 0x48
{
- REG16(AX) = DEC16(cpustate, REG16(AX) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG16(AX) = DEC16(REG16(AX) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_cx)(i386_state *cpustate) // Opcode 0x49
+void i386_device::i386_dec_cx() // Opcode 0x49
{
- REG16(CX) = DEC16(cpustate, REG16(CX) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG16(CX) = DEC16(REG16(CX) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_dx)(i386_state *cpustate) // Opcode 0x4a
+void i386_device::i386_dec_dx() // Opcode 0x4a
{
- REG16(DX) = DEC16(cpustate, REG16(DX) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG16(DX) = DEC16(REG16(DX) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_bx)(i386_state *cpustate) // Opcode 0x4b
+void i386_device::i386_dec_bx() // Opcode 0x4b
{
- REG16(BX) = DEC16(cpustate, REG16(BX) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG16(BX) = DEC16(REG16(BX) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_sp)(i386_state *cpustate) // Opcode 0x4c
+void i386_device::i386_dec_sp() // Opcode 0x4c
{
- REG16(SP) = DEC16(cpustate, REG16(SP) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG16(SP) = DEC16(REG16(SP) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_bp)(i386_state *cpustate) // Opcode 0x4d
+void i386_device::i386_dec_bp() // Opcode 0x4d
{
- REG16(BP) = DEC16(cpustate, REG16(BP) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG16(BP) = DEC16(REG16(BP) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_si)(i386_state *cpustate) // Opcode 0x4e
+void i386_device::i386_dec_si() // Opcode 0x4e
{
- REG16(SI) = DEC16(cpustate, REG16(SI) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG16(SI) = DEC16(REG16(SI) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_di)(i386_state *cpustate) // Opcode 0x4f
+void i386_device::i386_dec_di() // Opcode 0x4f
{
- REG16(DI) = DEC16(cpustate, REG16(DI) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG16(DI) = DEC16(REG16(DI) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(imul_r16_rm16)(i386_state *cpustate) // Opcode 0x0f af
+void i386_device::i386_imul_r16_rm16() // Opcode 0x0f af
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
INT32 result;
INT32 src, dst;
if( modrm >= 0xc0 ) {
src = (INT32)(INT16)LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_IMUL16_REG_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL16_REG_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = (INT32)(INT16)READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL16_REG_MEM); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ src = (INT32)(INT16)READ16(ea);
+ CYCLES(CYCLES_IMUL16_REG_MEM); /* TODO: Correct multiply timing */
}
dst = (INT32)(INT16)LOAD_REG16(modrm);
@@ -670,511 +670,511 @@ static void I386OP(imul_r16_rm16)(i386_state *cpustate) // Opcode 0x0f af
STORE_REG16(modrm, (UINT16)result);
- cpustate->CF = cpustate->OF = !(result == (INT32)(INT16)result);
+ m_CF = m_OF = !(result == (INT32)(INT16)result);
}
-static void I386OP(imul_r16_rm16_i16)(i386_state *cpustate) // Opcode 0x69
+void i386_device::i386_imul_r16_rm16_i16() // Opcode 0x69
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
INT32 result;
INT32 src, dst;
if( modrm >= 0xc0 ) {
dst = (INT32)(INT16)LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_IMUL16_REG_IMM_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL16_REG_IMM_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- dst = (INT32)(INT16)READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL16_MEM_IMM_REG); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ dst = (INT32)(INT16)READ16(ea);
+ CYCLES(CYCLES_IMUL16_MEM_IMM_REG); /* TODO: Correct multiply timing */
}
- src = (INT32)(INT16)FETCH16(cpustate);
+ src = (INT32)(INT16)FETCH16();
result = src * dst;
STORE_REG16(modrm, (UINT16)result);
- cpustate->CF = cpustate->OF = !(result == (INT32)(INT16)result);
+ m_CF = m_OF = !(result == (INT32)(INT16)result);
}
-static void I386OP(imul_r16_rm16_i8)(i386_state *cpustate) // Opcode 0x6b
+void i386_device::i386_imul_r16_rm16_i8() // Opcode 0x6b
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
INT32 result;
INT32 src, dst;
if( modrm >= 0xc0 ) {
dst = (INT32)(INT16)LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_IMUL16_REG_IMM_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL16_REG_IMM_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- dst = (INT32)(INT16)READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL16_MEM_IMM_REG); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ dst = (INT32)(INT16)READ16(ea);
+ CYCLES(CYCLES_IMUL16_MEM_IMM_REG); /* TODO: Correct multiply timing */
}
- src = (INT32)(INT8)FETCH(cpustate);
+ src = (INT32)(INT8)FETCH();
result = src * dst;
STORE_REG16(modrm, (UINT16)result);
- cpustate->CF = cpustate->OF = !(result == (INT32)(INT16)result);
+ m_CF = m_OF = !(result == (INT32)(INT16)result);
}
-static void I386OP(in_ax_i8)(i386_state *cpustate) // Opcode 0xe5
+void i386_device::i386_in_ax_i8() // Opcode 0xe5
{
- UINT16 port = FETCH(cpustate);
- UINT16 data = READPORT16(cpustate, port);
+ UINT16 port = FETCH();
+ UINT16 data = READPORT16(port);
REG16(AX) = data;
- CYCLES(cpustate,CYCLES_IN_VAR);
+ CYCLES(CYCLES_IN_VAR);
}
-static void I386OP(in_ax_dx)(i386_state *cpustate) // Opcode 0xed
+void i386_device::i386_in_ax_dx() // Opcode 0xed
{
UINT16 port = REG16(DX);
- UINT16 data = READPORT16(cpustate, port);
+ UINT16 data = READPORT16(port);
REG16(AX) = data;
- CYCLES(cpustate,CYCLES_IN);
+ CYCLES(CYCLES_IN);
}
-static void I386OP(inc_ax)(i386_state *cpustate) // Opcode 0x40
+void i386_device::i386_inc_ax() // Opcode 0x40
{
- REG16(AX) = INC16(cpustate, REG16(AX) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG16(AX) = INC16(REG16(AX) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_cx)(i386_state *cpustate) // Opcode 0x41
+void i386_device::i386_inc_cx() // Opcode 0x41
{
- REG16(CX) = INC16(cpustate, REG16(CX) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG16(CX) = INC16(REG16(CX) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_dx)(i386_state *cpustate) // Opcode 0x42
+void i386_device::i386_inc_dx() // Opcode 0x42
{
- REG16(DX) = INC16(cpustate, REG16(DX) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG16(DX) = INC16(REG16(DX) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_bx)(i386_state *cpustate) // Opcode 0x43
+void i386_device::i386_inc_bx() // Opcode 0x43
{
- REG16(BX) = INC16(cpustate, REG16(BX) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG16(BX) = INC16(REG16(BX) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_sp)(i386_state *cpustate) // Opcode 0x44
+void i386_device::i386_inc_sp() // Opcode 0x44
{
- REG16(SP) = INC16(cpustate, REG16(SP) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG16(SP) = INC16(REG16(SP) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_bp)(i386_state *cpustate) // Opcode 0x45
+void i386_device::i386_inc_bp() // Opcode 0x45
{
- REG16(BP) = INC16(cpustate, REG16(BP) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG16(BP) = INC16(REG16(BP) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_si)(i386_state *cpustate) // Opcode 0x46
+void i386_device::i386_inc_si() // Opcode 0x46
{
- REG16(SI) = INC16(cpustate, REG16(SI) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG16(SI) = INC16(REG16(SI) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_di)(i386_state *cpustate) // Opcode 0x47
+void i386_device::i386_inc_di() // Opcode 0x47
{
- REG16(DI) = INC16(cpustate, REG16(DI) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG16(DI) = INC16(REG16(DI) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(iret16)(i386_state *cpustate) // Opcode 0xcf
+void i386_device::i386_iret16() // Opcode 0xcf
{
if( PROTECTED_MODE )
{
- i386_protected_mode_iret(cpustate,0);
+ i386_protected_mode_iret(0);
}
else
{
/* TODO: #SS(0) exception */
/* TODO: #GP(0) exception */
- cpustate->eip = POP16(cpustate);
- cpustate->sreg[CS].selector = POP16(cpustate);
- set_flags(cpustate, POP16(cpustate) );
- i386_load_segment_descriptor(cpustate,CS);
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = POP16();
+ m_sreg[CS].selector = POP16();
+ set_flags(POP16() );
+ i386_load_segment_descriptor(CS);
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_IRET);
+ CYCLES(CYCLES_IRET);
}
-static void I386OP(ja_rel16)(i386_state *cpustate) // Opcode 0x0f 87
+void i386_device::i386_ja_rel16() // Opcode 0x0f 87
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->CF == 0 && cpustate->ZF == 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_CF == 0 && m_ZF == 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jbe_rel16)(i386_state *cpustate) // Opcode 0x0f 86
+void i386_device::i386_jbe_rel16() // Opcode 0x0f 86
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->CF != 0 || cpustate->ZF != 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_CF != 0 || m_ZF != 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jc_rel16)(i386_state *cpustate) // Opcode 0x0f 82
+void i386_device::i386_jc_rel16() // Opcode 0x0f 82
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->CF != 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_CF != 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jg_rel16)(i386_state *cpustate) // Opcode 0x0f 8f
+void i386_device::i386_jg_rel16() // Opcode 0x0f 8f
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->ZF == 0 && (cpustate->SF == cpustate->OF) ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_ZF == 0 && (m_SF == m_OF) ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jge_rel16)(i386_state *cpustate) // Opcode 0x0f 8d
+void i386_device::i386_jge_rel16() // Opcode 0x0f 8d
{
- INT16 disp = FETCH16(cpustate);
- if(cpustate->SF == cpustate->OF) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if(m_SF == m_OF) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jl_rel16)(i386_state *cpustate) // Opcode 0x0f 8c
+void i386_device::i386_jl_rel16() // Opcode 0x0f 8c
{
- INT16 disp = FETCH16(cpustate);
- if( (cpustate->SF != cpustate->OF) ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( (m_SF != m_OF) ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jle_rel16)(i386_state *cpustate) // Opcode 0x0f 8e
+void i386_device::i386_jle_rel16() // Opcode 0x0f 8e
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->ZF != 0 || (cpustate->SF != cpustate->OF) ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_ZF != 0 || (m_SF != m_OF) ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jnc_rel16)(i386_state *cpustate) // Opcode 0x0f 83
+void i386_device::i386_jnc_rel16() // Opcode 0x0f 83
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->CF == 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_CF == 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jno_rel16)(i386_state *cpustate) // Opcode 0x0f 81
+void i386_device::i386_jno_rel16() // Opcode 0x0f 81
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->OF == 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_OF == 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jnp_rel16)(i386_state *cpustate) // Opcode 0x0f 8b
+void i386_device::i386_jnp_rel16() // Opcode 0x0f 8b
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->PF == 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_PF == 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jns_rel16)(i386_state *cpustate) // Opcode 0x0f 89
+void i386_device::i386_jns_rel16() // Opcode 0x0f 89
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->SF == 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_SF == 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jnz_rel16)(i386_state *cpustate) // Opcode 0x0f 85
+void i386_device::i386_jnz_rel16() // Opcode 0x0f 85
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->ZF == 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_ZF == 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jo_rel16)(i386_state *cpustate) // Opcode 0x0f 80
+void i386_device::i386_jo_rel16() // Opcode 0x0f 80
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->OF != 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_OF != 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jp_rel16)(i386_state *cpustate) // Opcode 0x0f 8a
+void i386_device::i386_jp_rel16() // Opcode 0x0f 8a
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->PF != 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_PF != 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(js_rel16)(i386_state *cpustate) // Opcode 0x0f 88
+void i386_device::i386_js_rel16() // Opcode 0x0f 88
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->SF != 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_SF != 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jz_rel16)(i386_state *cpustate) // Opcode 0x0f 84
+void i386_device::i386_jz_rel16() // Opcode 0x0f 84
{
- INT16 disp = FETCH16(cpustate);
- if( cpustate->ZF != 0 ) {
- if (cpustate->sreg[CS].d)
+ INT16 disp = FETCH16();
+ if( m_ZF != 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jcxz16)(i386_state *cpustate) // Opcode 0xe3
+void i386_device::i386_jcxz16() // Opcode 0xe3
{
- INT8 disp = FETCH(cpustate);
- int val = (cpustate->address_size)?(REG32(ECX) == 0):(REG16(CX) == 0);
+ INT8 disp = FETCH();
+ int val = (m_address_size)?(REG32(ECX) == 0):(REG16(CX) == 0);
if( val ) {
- if (cpustate->sreg[CS].d)
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCXZ); /* TODO: Timing = 9 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCXZ); /* TODO: Timing = 9 + m */
} else {
- CYCLES(cpustate,CYCLES_JCXZ_NOBRANCH);
+ CYCLES(CYCLES_JCXZ_NOBRANCH);
}
}
-static void I386OP(jmp_rel16)(i386_state *cpustate) // Opcode 0xe9
+void i386_device::i386_jmp_rel16() // Opcode 0xe9
{
- INT16 disp = FETCH16(cpustate);
+ INT16 disp = FETCH16();
- if (cpustate->sreg[CS].d)
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JMP); /* TODO: Timing = 7 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JMP); /* TODO: Timing = 7 + m */
}
-static void I386OP(jmp_abs16)(i386_state *cpustate) // Opcode 0xea
+void i386_device::i386_jmp_abs16() // Opcode 0xea
{
- UINT16 address = FETCH16(cpustate);
- UINT16 segment = FETCH16(cpustate);
+ UINT16 address = FETCH16();
+ UINT16 segment = FETCH16();
if( PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_jump(cpustate,segment,address,0,0);
+ i386_protected_mode_jump(segment,address,0,0);
}
else
{
- cpustate->eip = address;
- cpustate->sreg[CS].selector = segment;
- cpustate->performed_intersegment_jump = 1;
- i386_load_segment_descriptor(cpustate,CS);
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = address;
+ m_sreg[CS].selector = segment;
+ m_performed_intersegment_jump = 1;
+ i386_load_segment_descriptor(CS);
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_JMP_INTERSEG);
+ CYCLES(CYCLES_JMP_INTERSEG);
}
-static void I386OP(lea16)(i386_state *cpustate) // Opcode 0x8d
+void i386_device::i386_lea16() // Opcode 0x8d
{
- UINT8 modrm = FETCH(cpustate);
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,NULL);
+ UINT8 modrm = FETCH();
+ UINT32 ea = GetNonTranslatedEA(modrm,NULL);
STORE_REG16(modrm, ea);
- CYCLES(cpustate,CYCLES_LEA);
+ CYCLES(CYCLES_LEA);
}
-static void I386OP(enter16)(i386_state *cpustate) // Opcode 0xc8
+void i386_device::i386_enter16() // Opcode 0xc8
{
- UINT16 framesize = FETCH16(cpustate);
- UINT8 level = FETCH(cpustate) % 32;
+ UINT16 framesize = FETCH16();
+ UINT8 level = FETCH() % 32;
UINT8 x;
UINT16 frameptr;
- PUSH16(cpustate,REG16(BP));
+ PUSH16(REG16(BP));
if(!STACK_32BIT)
frameptr = REG16(SP);
@@ -1186,429 +1186,429 @@ static void I386OP(enter16)(i386_state *cpustate) // Opcode 0xc8
for(x=1;x<level-1;x++)
{
REG16(BP) -= 2;
- PUSH16(cpustate,READ16(cpustate,REG16(BP)));
+ PUSH16(READ16(REG16(BP)));
}
- PUSH16(cpustate,frameptr);
+ PUSH16(frameptr);
}
REG16(BP) = frameptr;
if(!STACK_32BIT)
REG16(SP) -= framesize;
else
REG32(ESP) -= framesize;
- CYCLES(cpustate,CYCLES_ENTER);
+ CYCLES(CYCLES_ENTER);
}
-static void I386OP(leave16)(i386_state *cpustate) // Opcode 0xc9
+void i386_device::i386_leave16() // Opcode 0xc9
{
if(!STACK_32BIT)
REG16(SP) = REG16(BP);
else
REG32(ESP) = REG32(EBP);
- REG16(BP) = POP16(cpustate);
- CYCLES(cpustate,CYCLES_LEAVE);
+ REG16(BP) = POP16();
+ CYCLES(CYCLES_LEAVE);
}
-static void I386OP(lodsw)(i386_state *cpustate) // Opcode 0xad
+void i386_device::i386_lodsw() // Opcode 0xad
{
UINT32 eas;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- REG16(AX) = READ16(cpustate,eas);
- BUMP_SI(cpustate,2);
- CYCLES(cpustate,CYCLES_LODS);
+ REG16(AX) = READ16(eas);
+ BUMP_SI(2);
+ CYCLES(CYCLES_LODS);
}
-static void I386OP(loop16)(i386_state *cpustate) // Opcode 0xe2
+void i386_device::i386_loop16() // Opcode 0xe2
{
- INT8 disp = FETCH(cpustate);
- INT32 val = (cpustate->address_size)?(--REG32(ECX)):(--REG16(CX));
+ INT8 disp = FETCH();
+ INT32 val = (m_address_size)?(--REG32(ECX)):(--REG16(CX));
if( val != 0 ) {
- if (cpustate->sreg[CS].d)
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_LOOP); /* TODO: Timing = 11 + m */
+ CYCLES(CYCLES_LOOP); /* TODO: Timing = 11 + m */
}
-static void I386OP(loopne16)(i386_state *cpustate) // Opcode 0xe0
+void i386_device::i386_loopne16() // Opcode 0xe0
{
- INT8 disp = FETCH(cpustate);
- INT32 val = (cpustate->address_size)?(--REG32(ECX)):(--REG16(CX));
- if( val != 0 && cpustate->ZF == 0 ) {
- if (cpustate->sreg[CS].d)
+ INT8 disp = FETCH();
+ INT32 val = (m_address_size)?(--REG32(ECX)):(--REG16(CX));
+ if( val != 0 && m_ZF == 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_LOOPNZ); /* TODO: Timing = 11 + m */
+ CYCLES(CYCLES_LOOPNZ); /* TODO: Timing = 11 + m */
}
-static void I386OP(loopz16)(i386_state *cpustate) // Opcode 0xe1
+void i386_device::i386_loopz16() // Opcode 0xe1
{
- INT8 disp = FETCH(cpustate);
- INT32 val = (cpustate->address_size)?(--REG32(ECX)):(--REG16(CX));
- if( val != 0 && cpustate->ZF != 0 ) {
- if (cpustate->sreg[CS].d)
+ INT8 disp = FETCH();
+ INT32 val = (m_address_size)?(--REG32(ECX)):(--REG16(CX));
+ if( val != 0 && m_ZF != 0 ) {
+ if (m_sreg[CS].d)
{
- cpustate->eip += disp;
+ m_eip += disp;
}
else
{
- cpustate->eip = (cpustate->eip + disp) & 0xffff;
+ m_eip = (m_eip + disp) & 0xffff;
}
- CHANGE_PC(cpustate,cpustate->eip);
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_LOOPZ); /* TODO: Timing = 11 + m */
+ CYCLES(CYCLES_LOOPZ); /* TODO: Timing = 11 + m */
}
-static void I386OP(mov_rm16_r16)(i386_state *cpustate) // Opcode 0x89
+void i386_device::i386_mov_rm16_r16() // Opcode 0x89
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
STORE_RM16(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_REG_REG);
+ CYCLES(CYCLES_MOV_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- WRITE16(cpustate,ea, src);
- CYCLES(cpustate,CYCLES_MOV_REG_MEM);
+ WRITE16(ea, src);
+ CYCLES(CYCLES_MOV_REG_MEM);
}
}
-static void I386OP(mov_r16_rm16)(i386_state *cpustate) // Opcode 0x8b
+void i386_device::i386_mov_r16_rm16() // Opcode 0x8b
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_REG_REG);
+ CYCLES(CYCLES_MOV_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
STORE_REG16(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_MEM_REG);
+ CYCLES(CYCLES_MOV_MEM_REG);
}
}
-static void I386OP(mov_rm16_i16)(i386_state *cpustate) // Opcode 0xc7
+void i386_device::i386_mov_rm16_i16() // Opcode 0xc7
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
- UINT16 value = FETCH16(cpustate);
+ UINT16 value = FETCH16();
STORE_RM16(modrm, value);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ CYCLES(CYCLES_MOV_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 value = FETCH16(cpustate);
- WRITE16(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_MOV_IMM_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 value = FETCH16();
+ WRITE16(ea, value);
+ CYCLES(CYCLES_MOV_IMM_MEM);
}
}
-static void I386OP(mov_ax_m16)(i386_state *cpustate) // Opcode 0xa1
+void i386_device::i386_mov_ax_m16() // Opcode 0xa1
{
UINT32 offset, ea;
- if( cpustate->address_size ) {
- offset = FETCH32(cpustate);
+ if( m_address_size ) {
+ offset = FETCH32();
} else {
- offset = FETCH16(cpustate);
+ offset = FETCH16();
}
/* TODO: Not sure if this is correct... */
- if( cpustate->segment_prefix ) {
- ea = i386_translate(cpustate, cpustate->segment_override, offset, 0 );
+ if( m_segment_prefix ) {
+ ea = i386_translate(m_segment_override, offset, 0 );
} else {
- ea = i386_translate(cpustate, DS, offset, 0 );
+ ea = i386_translate(DS, offset, 0 );
}
- REG16(AX) = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_MOV_MEM_ACC);
+ REG16(AX) = READ16(ea);
+ CYCLES(CYCLES_MOV_MEM_ACC);
}
-static void I386OP(mov_m16_ax)(i386_state *cpustate) // Opcode 0xa3
+void i386_device::i386_mov_m16_ax() // Opcode 0xa3
{
UINT32 offset, ea;
- if( cpustate->address_size ) {
- offset = FETCH32(cpustate);
+ if( m_address_size ) {
+ offset = FETCH32();
} else {
- offset = FETCH16(cpustate);
+ offset = FETCH16();
}
/* TODO: Not sure if this is correct... */
- if( cpustate->segment_prefix ) {
- ea = i386_translate(cpustate, cpustate->segment_override, offset, 1 );
+ if( m_segment_prefix ) {
+ ea = i386_translate(m_segment_override, offset, 1 );
} else {
- ea = i386_translate(cpustate, DS, offset, 1 );
+ ea = i386_translate(DS, offset, 1 );
}
- WRITE16(cpustate, ea, REG16(AX) );
- CYCLES(cpustate,CYCLES_MOV_ACC_MEM);
+ WRITE16(ea, REG16(AX) );
+ CYCLES(CYCLES_MOV_ACC_MEM);
}
-static void I386OP(mov_ax_i16)(i386_state *cpustate) // Opcode 0xb8
+void i386_device::i386_mov_ax_i16() // Opcode 0xb8
{
- REG16(AX) = FETCH16(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG16(AX) = FETCH16();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_cx_i16)(i386_state *cpustate) // Opcode 0xb9
+void i386_device::i386_mov_cx_i16() // Opcode 0xb9
{
- REG16(CX) = FETCH16(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG16(CX) = FETCH16();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_dx_i16)(i386_state *cpustate) // Opcode 0xba
+void i386_device::i386_mov_dx_i16() // Opcode 0xba
{
- REG16(DX) = FETCH16(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG16(DX) = FETCH16();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_bx_i16)(i386_state *cpustate) // Opcode 0xbb
+void i386_device::i386_mov_bx_i16() // Opcode 0xbb
{
- REG16(BX) = FETCH16(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG16(BX) = FETCH16();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_sp_i16)(i386_state *cpustate) // Opcode 0xbc
+void i386_device::i386_mov_sp_i16() // Opcode 0xbc
{
- REG16(SP) = FETCH16(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG16(SP) = FETCH16();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_bp_i16)(i386_state *cpustate) // Opcode 0xbd
+void i386_device::i386_mov_bp_i16() // Opcode 0xbd
{
- REG16(BP) = FETCH16(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG16(BP) = FETCH16();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_si_i16)(i386_state *cpustate) // Opcode 0xbe
+void i386_device::i386_mov_si_i16() // Opcode 0xbe
{
- REG16(SI) = FETCH16(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG16(SI) = FETCH16();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_di_i16)(i386_state *cpustate) // Opcode 0xbf
+void i386_device::i386_mov_di_i16() // Opcode 0xbf
{
- REG16(DI) = FETCH16(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG16(DI) = FETCH16();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(movsw)(i386_state *cpustate) // Opcode 0xa5
+void i386_device::i386_movsw() // Opcode 0xa5
{
UINT32 eas, ead;
UINT16 v;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 1 );
- v = READ16(cpustate,eas);
- WRITE16(cpustate,ead, v);
- BUMP_SI(cpustate,2);
- BUMP_DI(cpustate,2);
- CYCLES(cpustate,CYCLES_MOVS);
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 1 );
+ v = READ16(eas);
+ WRITE16(ead, v);
+ BUMP_SI(2);
+ BUMP_DI(2);
+ CYCLES(CYCLES_MOVS);
}
-static void I386OP(movsx_r16_rm8)(i386_state *cpustate) // Opcode 0x0f be
+void i386_device::i386_movsx_r16_rm8() // Opcode 0x0f be
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
INT16 src = (INT8)LOAD_RM8(modrm);
STORE_REG16(modrm, src);
- CYCLES(cpustate,CYCLES_MOVSX_REG_REG);
+ CYCLES(CYCLES_MOVSX_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- INT16 src = (INT8)READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ INT16 src = (INT8)READ8(ea);
STORE_REG16(modrm, src);
- CYCLES(cpustate,CYCLES_MOVSX_MEM_REG);
+ CYCLES(CYCLES_MOVSX_MEM_REG);
}
}
-static void I386OP(movzx_r16_rm8)(i386_state *cpustate) // Opcode 0x0f b6
+void i386_device::i386_movzx_r16_rm8() // Opcode 0x0f b6
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 src = (UINT8)LOAD_RM8(modrm);
STORE_REG16(modrm, src);
- CYCLES(cpustate,CYCLES_MOVZX_REG_REG);
+ CYCLES(CYCLES_MOVZX_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT16 src = (UINT8)READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ UINT16 src = (UINT8)READ8(ea);
STORE_REG16(modrm, src);
- CYCLES(cpustate,CYCLES_MOVZX_MEM_REG);
+ CYCLES(CYCLES_MOVZX_MEM_REG);
}
}
-static void I386OP(or_rm16_r16)(i386_state *cpustate) // Opcode 0x09
+void i386_device::i386_or_rm16_r16() // Opcode 0x09
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
- dst = OR16(cpustate,dst, src);
+ dst = OR16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
- dst = OR16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ16(ea);
+ dst = OR16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(or_r16_rm16)(i386_state *cpustate) // Opcode 0x0b
+void i386_device::i386_or_r16_rm16() // Opcode 0x0b
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
dst = LOAD_REG16(modrm);
- dst = OR16(cpustate,dst, src);
+ dst = OR16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
dst = LOAD_REG16(modrm);
- dst = OR16(cpustate,dst, src);
+ dst = OR16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(or_ax_i16)(i386_state *cpustate) // Opcode 0x0d
+void i386_device::i386_or_ax_i16() // Opcode 0x0d
{
UINT16 src, dst;
- src = FETCH16(cpustate);
+ src = FETCH16();
dst = REG16(AX);
- dst = OR16(cpustate,dst, src);
+ dst = OR16(dst, src);
REG16(AX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(out_ax_i8)(i386_state *cpustate) // Opcode 0xe7
+void i386_device::i386_out_ax_i8() // Opcode 0xe7
{
- UINT16 port = FETCH(cpustate);
+ UINT16 port = FETCH();
UINT16 data = REG16(AX);
- WRITEPORT16(cpustate, port, data);
- CYCLES(cpustate,CYCLES_OUT_VAR);
+ WRITEPORT16(port, data);
+ CYCLES(CYCLES_OUT_VAR);
}
-static void I386OP(out_ax_dx)(i386_state *cpustate) // Opcode 0xef
+void i386_device::i386_out_ax_dx() // Opcode 0xef
{
UINT16 port = REG16(DX);
UINT16 data = REG16(AX);
- WRITEPORT16(cpustate, port, data);
- CYCLES(cpustate,CYCLES_OUT);
+ WRITEPORT16(port, data);
+ CYCLES(CYCLES_OUT);
}
-static void I386OP(pop_ax)(i386_state *cpustate) // Opcode 0x58
+void i386_device::i386_pop_ax() // Opcode 0x58
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
- REG16(AX) = POP16(cpustate);
+ if(i386_limit_check(SS,offset+1) == 0)
+ REG16(AX) = POP16();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_cx)(i386_state *cpustate) // Opcode 0x59
+void i386_device::i386_pop_cx() // Opcode 0x59
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
- REG16(CX) = POP16(cpustate);
+ if(i386_limit_check(SS,offset+1) == 0)
+ REG16(CX) = POP16();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_dx)(i386_state *cpustate) // Opcode 0x5a
+void i386_device::i386_pop_dx() // Opcode 0x5a
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
- REG16(DX) = POP16(cpustate);
+ if(i386_limit_check(SS,offset+1) == 0)
+ REG16(DX) = POP16();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_bx)(i386_state *cpustate) // Opcode 0x5b
+void i386_device::i386_pop_bx() // Opcode 0x5b
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
- REG16(BX) = POP16(cpustate);
+ if(i386_limit_check(SS,offset+1) == 0)
+ REG16(BX) = POP16();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_sp)(i386_state *cpustate) // Opcode 0x5c
+void i386_device::i386_pop_sp() // Opcode 0x5c
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
- REG16(SP) = POP16(cpustate);
+ if(i386_limit_check(SS,offset+1) == 0)
+ REG16(SP) = POP16();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_bp)(i386_state *cpustate) // Opcode 0x5d
+void i386_device::i386_pop_bp() // Opcode 0x5d
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
- REG16(BP) = POP16(cpustate);
+ if(i386_limit_check(SS,offset+1) == 0)
+ REG16(BP) = POP16();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_si)(i386_state *cpustate) // Opcode 0x5e
+void i386_device::i386_pop_si() // Opcode 0x5e
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
- REG16(SI) = POP16(cpustate);
+ if(i386_limit_check(SS,offset+1) == 0)
+ REG16(SI) = POP16();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_di)(i386_state *cpustate) // Opcode 0x5f
+void i386_device::i386_pop_di() // Opcode 0x5f
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
- REG16(DI) = POP16(cpustate);
+ if(i386_limit_check(SS,offset+1) == 0)
+ REG16(DI) = POP16();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static bool I386OP(pop_seg16)(i386_state *cpustate, int segment)
+bool i386_device::i386_pop_seg16(int segment)
{
UINT32 ea, offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
UINT16 value;
bool fault;
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
+ if(i386_limit_check(SS,offset+1) == 0)
{
- ea = i386_translate(cpustate, SS, offset, 0);
- value = READ16(cpustate, ea);
- i386_sreg_load(cpustate,value, segment, &fault);
+ ea = i386_translate(SS, offset, 0);
+ value = READ16(ea);
+ i386_sreg_load(value, segment, &fault);
if(fault) return false;
if(STACK_32BIT)
REG32(ESP) = offset + 2;
@@ -1617,62 +1617,62 @@ static bool I386OP(pop_seg16)(i386_state *cpustate, int segment)
}
else
{
- cpustate->ext = 1;
- i386_trap_with_error(cpustate,FAULT_SS,0,0,0);
+ m_ext = 1;
+ i386_trap_with_error(FAULT_SS,0,0,0);
return false;
}
- CYCLES(cpustate,CYCLES_POP_SREG);
+ CYCLES(CYCLES_POP_SREG);
return true;
}
-static void I386OP(pop_ds16)(i386_state *cpustate) // Opcode 0x1f
+void i386_device::i386_pop_ds16() // Opcode 0x1f
{
- I386OP(pop_seg16)(cpustate, DS);
+ i386_pop_seg16(DS);
}
-static void I386OP(pop_es16)(i386_state *cpustate) // Opcode 0x07
+void i386_device::i386_pop_es16() // Opcode 0x07
{
- I386OP(pop_seg16)(cpustate, ES);
+ i386_pop_seg16(ES);
}
-static void I386OP(pop_fs16)(i386_state *cpustate) // Opcode 0x0f a1
+void i386_device::i386_pop_fs16() // Opcode 0x0f a1
{
- I386OP(pop_seg16)(cpustate, FS);
+ i386_pop_seg16(FS);
}
-static void I386OP(pop_gs16)(i386_state *cpustate) // Opcode 0x0f a9
+void i386_device::i386_pop_gs16() // Opcode 0x0f a9
{
- I386OP(pop_seg16)(cpustate, GS);
+ i386_pop_seg16(GS);
}
-static void I386OP(pop_ss16)(i386_state *cpustate) // Opcode 0x17
+void i386_device::i386_pop_ss16() // Opcode 0x17
{
- if(!I386OP(pop_seg16)(cpustate, SS)) return;
- if(cpustate->IF != 0) // if external interrupts are enabled
+ if(!i386_pop_seg16(SS)) return;
+ if(m_IF != 0) // if external interrupts are enabled
{
- cpustate->IF = 0; // reset IF for the next instruction
- cpustate->delayed_interrupt_enable = 1;
+ m_IF = 0; // reset IF for the next instruction
+ m_delayed_interrupt_enable = 1;
}
}
-static void I386OP(pop_rm16)(i386_state *cpustate) // Opcode 0x8f
+void i386_device::i386_pop_rm16() // Opcode 0x8f
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT16 value;
UINT32 ea, offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
+ if(i386_limit_check(SS,offset+1) == 0)
{
UINT32 temp_sp = REG32(ESP);
- value = POP16(cpustate);
+ value = POP16();
if( modrm >= 0xc0 ) {
STORE_RM16(modrm, value);
} else {
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
try
{
- WRITE16(cpustate,ea, value);
+ WRITE16(ea, value);
}
catch(UINT64 e)
{
@@ -1683,373 +1683,373 @@ static void I386OP(pop_rm16)(i386_state *cpustate) // Opcode 0x8f
}
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_RM);
+ CYCLES(CYCLES_POP_RM);
}
-static void I386OP(popa)(i386_state *cpustate) // Opcode 0x61
+void i386_device::i386_popa() // Opcode 0x61
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+15) == 0)
+ if(i386_limit_check(SS,offset+15) == 0)
{
- REG16(DI) = POP16(cpustate);
- REG16(SI) = POP16(cpustate);
- REG16(BP) = POP16(cpustate);
+ REG16(DI) = POP16();
+ REG16(SI) = POP16();
+ REG16(BP) = POP16();
REG16(SP) += 2;
- REG16(BX) = POP16(cpustate);
- REG16(DX) = POP16(cpustate);
- REG16(CX) = POP16(cpustate);
- REG16(AX) = POP16(cpustate);
+ REG16(BX) = POP16();
+ REG16(DX) = POP16();
+ REG16(CX) = POP16();
+ REG16(AX) = POP16();
}
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POPA);
+ CYCLES(CYCLES_POPA);
}
-static void I386OP(popf)(i386_state *cpustate) // Opcode 0x9d
+void i386_device::i386_popf() // Opcode 0x9d
{
UINT32 value;
- UINT32 current = get_flags(cpustate);
+ UINT32 current = get_flags();
UINT8 IOPL = (current >> 12) & 0x03;
UINT32 mask = 0x7fd5;
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
// IOPL can only change if CPL is 0
- if(cpustate->CPL != 0)
+ if(m_CPL != 0)
mask &= ~0x00003000;
// IF can only change if CPL is at least as privileged as IOPL
- if(cpustate->CPL > IOPL)
+ if(m_CPL > IOPL)
mask &= ~0x00000200;
if(V8086_MODE)
{
if(IOPL < 3)
{
- logerror("POPFD(%08x): IOPL < 3 while in V86 mode.\n",cpustate->pc);
+ logerror("POPFD(%08x): IOPL < 3 while in V86 mode.\n",m_pc);
FAULT(FAULT_GP,0) // #GP(0)
}
mask &= ~0x00003000; // IOPL cannot be changed while in V8086 mode
}
- if(i386_limit_check(cpustate,SS,offset+1) == 0)
+ if(i386_limit_check(SS,offset+1) == 0)
{
- value = POP16(cpustate);
- set_flags(cpustate,(current & ~mask) | (value & mask)); // mask out reserved bits
+ value = POP16();
+ set_flags((current & ~mask) | (value & mask)); // mask out reserved bits
}
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POPF);
+ CYCLES(CYCLES_POPF);
}
-static void I386OP(push_ax)(i386_state *cpustate) // Opcode 0x50
+void i386_device::i386_push_ax() // Opcode 0x50
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, REG16(AX) );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(REG16(AX) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_cx)(i386_state *cpustate) // Opcode 0x51
+void i386_device::i386_push_cx() // Opcode 0x51
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, REG16(CX) );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(REG16(CX) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_dx)(i386_state *cpustate) // Opcode 0x52
+void i386_device::i386_push_dx() // Opcode 0x52
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, REG16(DX) );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(REG16(DX) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_bx)(i386_state *cpustate) // Opcode 0x53
+void i386_device::i386_push_bx() // Opcode 0x53
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, REG16(BX) );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(REG16(BX) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_sp)(i386_state *cpustate) // Opcode 0x54
+void i386_device::i386_push_sp() // Opcode 0x54
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, REG16(SP) );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(REG16(SP) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_bp)(i386_state *cpustate) // Opcode 0x55
+void i386_device::i386_push_bp() // Opcode 0x55
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, REG16(BP) );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(REG16(BP) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_si)(i386_state *cpustate) // Opcode 0x56
+void i386_device::i386_push_si() // Opcode 0x56
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, REG16(SI) );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(REG16(SI) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_di)(i386_state *cpustate) // Opcode 0x57
+void i386_device::i386_push_di() // Opcode 0x57
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, REG16(DI) );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(REG16(DI) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_cs16)(i386_state *cpustate) // Opcode 0x0e
+void i386_device::i386_push_cs16() // Opcode 0x0e
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, cpustate->sreg[CS].selector );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(m_sreg[CS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_ds16)(i386_state *cpustate) // Opcode 0x1e
+void i386_device::i386_push_ds16() // Opcode 0x1e
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, cpustate->sreg[DS].selector );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(m_sreg[DS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_es16)(i386_state *cpustate) // Opcode 0x06
+void i386_device::i386_push_es16() // Opcode 0x06
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, cpustate->sreg[ES].selector );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(m_sreg[ES].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_fs16)(i386_state *cpustate) // Opcode 0x0f a0
+void i386_device::i386_push_fs16() // Opcode 0x0f a0
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, cpustate->sreg[FS].selector );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(m_sreg[FS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_gs16)(i386_state *cpustate) // Opcode 0x0f a8
+void i386_device::i386_push_gs16() // Opcode 0x0f a8
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, cpustate->sreg[GS].selector );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(m_sreg[GS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_ss16)(i386_state *cpustate) // Opcode 0x16
+void i386_device::i386_push_ss16() // Opcode 0x16
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, cpustate->sreg[SS].selector );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(m_sreg[SS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_i16)(i386_state *cpustate) // Opcode 0x68
+void i386_device::i386_push_i16() // Opcode 0x68
{
- UINT16 value = FETCH16(cpustate);
+ UINT16 value = FETCH16();
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate,value);
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(value);
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_IMM);
+ CYCLES(CYCLES_PUSH_IMM);
}
-static void I386OP(pusha)(i386_state *cpustate) // Opcode 0x60
+void i386_device::i386_pusha() // Opcode 0x60
{
UINT16 temp = REG16(SP);
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-16) == 0)
+ if(i386_limit_check(SS,offset-16) == 0)
{
- PUSH16(cpustate, REG16(AX) );
- PUSH16(cpustate, REG16(CX) );
- PUSH16(cpustate, REG16(DX) );
- PUSH16(cpustate, REG16(BX) );
- PUSH16(cpustate, temp );
- PUSH16(cpustate, REG16(BP) );
- PUSH16(cpustate, REG16(SI) );
- PUSH16(cpustate, REG16(DI) );
+ PUSH16(REG16(AX) );
+ PUSH16(REG16(CX) );
+ PUSH16(REG16(DX) );
+ PUSH16(REG16(BX) );
+ PUSH16(temp );
+ PUSH16(REG16(BP) );
+ PUSH16(REG16(SI) );
+ PUSH16(REG16(DI) );
}
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSHA);
+ CYCLES(CYCLES_PUSHA);
}
-static void I386OP(pushf)(i386_state *cpustate) // Opcode 0x9c
+void i386_device::i386_pushf() // Opcode 0x9c
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-2) == 0)
- PUSH16(cpustate, get_flags(cpustate) & 0xffff );
+ if(i386_limit_check(SS,offset-2) == 0)
+ PUSH16(get_flags() & 0xffff );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSHF);
+ CYCLES(CYCLES_PUSHF);
}
-static void I386OP(ret_near16_i16)(i386_state *cpustate) // Opcode 0xc2
+void i386_device::i386_ret_near16_i16() // Opcode 0xc2
{
- INT16 disp = FETCH16(cpustate);
- cpustate->eip = POP16(cpustate);
+ INT16 disp = FETCH16();
+ m_eip = POP16();
REG16(SP) += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_RET_IMM); /* TODO: Timing = 10 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_RET_IMM); /* TODO: Timing = 10 + m */
}
-static void I386OP(ret_near16)(i386_state *cpustate) // Opcode 0xc3
+void i386_device::i386_ret_near16() // Opcode 0xc3
{
- cpustate->eip = POP16(cpustate);
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_RET); /* TODO: Timing = 10 + m */
+ m_eip = POP16();
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_RET); /* TODO: Timing = 10 + m */
}
-static void I386OP(sbb_rm16_r16)(i386_state *cpustate) // Opcode 0x19
+void i386_device::i386_sbb_rm16_r16() // Opcode 0x19
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
- dst = SBB16(cpustate, dst, src, cpustate->CF);
+ dst = SBB16(dst, src, m_CF);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
- dst = SBB16(cpustate, dst, src, cpustate->CF);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ16(ea);
+ dst = SBB16(dst, src, m_CF);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(sbb_r16_rm16)(i386_state *cpustate) // Opcode 0x1b
+void i386_device::i386_sbb_r16_rm16() // Opcode 0x1b
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
dst = LOAD_REG16(modrm);
- dst = SBB16(cpustate, dst, src, cpustate->CF);
+ dst = SBB16(dst, src, m_CF);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
dst = LOAD_REG16(modrm);
- dst = SBB16(cpustate, dst, src, cpustate->CF);
+ dst = SBB16(dst, src, m_CF);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(sbb_ax_i16)(i386_state *cpustate) // Opcode 0x1d
+void i386_device::i386_sbb_ax_i16() // Opcode 0x1d
{
UINT16 src, dst;
- src = FETCH16(cpustate);
+ src = FETCH16();
dst = REG16(AX);
- dst = SBB16(cpustate, dst, src, cpustate->CF);
+ dst = SBB16(dst, src, m_CF);
REG16(AX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(scasw)(i386_state *cpustate) // Opcode 0xaf
+void i386_device::i386_scasw() // Opcode 0xaf
{
UINT32 eas;
UINT16 src, dst;
- eas = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 0 );
- src = READ16(cpustate,eas);
+ eas = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 0 );
+ src = READ16(eas);
dst = REG16(AX);
- SUB16(cpustate,dst, src);
- BUMP_DI(cpustate,2);
- CYCLES(cpustate,CYCLES_SCAS);
+ SUB16(dst, src);
+ BUMP_DI(2);
+ CYCLES(CYCLES_SCAS);
}
-static void I386OP(shld16_i8)(i386_state *cpustate) // Opcode 0x0f a4
+void i386_device::i386_shld16_i8() // Opcode 0x0f a4
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 upper = LOAD_REG16(modrm);
- UINT8 shift = FETCH(cpustate);
+ UINT8 shift = FETCH();
shift &= 31;
if( shift == 0 ) {
} else if( shift > 15 ) {
- cpustate->CF = (upper & (1 << (16-shift))) ? 1 : 0;
+ m_CF = (upper & (1 << (16-shift))) ? 1 : 0;
// ppro and above should be (dst >> (32-shift))
dst = (upper << (shift-16)) | (upper >> (32-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 15);
+ m_OF = m_CF ^ (dst >> 15);
SetSZPF16(dst);
} else {
- cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0;
+ m_CF = (dst & (1 << (16-shift))) ? 1 : 0;
dst = (dst << shift) | (upper >> (16-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 15);
+ m_OF = m_CF ^ (dst >> 15);
SetSZPF16(dst);
}
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_SHLD_REG);
+ CYCLES(CYCLES_SHLD_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
UINT16 upper = LOAD_REG16(modrm);
- UINT8 shift = FETCH(cpustate);
+ UINT8 shift = FETCH();
shift &= 31;
if( shift == 0 ) {
} else if( shift > 15 ) {
- cpustate->CF = (upper & (1 << (16-shift))) ? 1 : 0;
+ m_CF = (upper & (1 << (16-shift))) ? 1 : 0;
dst = (upper << (shift-16)) | (upper >> (32-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 15);
+ m_OF = m_CF ^ (dst >> 15);
SetSZPF16(dst);
} else {
- cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0;
+ m_CF = (dst & (1 << (16-shift))) ? 1 : 0;
dst = (dst << shift) | (upper >> (16-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 15);
+ m_OF = m_CF ^ (dst >> 15);
SetSZPF16(dst);
}
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_SHLD_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_SHLD_MEM);
}
}
-static void I386OP(shld16_cl)(i386_state *cpustate) // Opcode 0x0f a5
+void i386_device::i386_shld16_cl() // Opcode 0x0f a5
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 upper = LOAD_REG16(modrm);
@@ -2057,89 +2057,89 @@ static void I386OP(shld16_cl)(i386_state *cpustate) // Opcode 0x0f a5
shift &= 31;
if( shift == 0 ) {
} else if( shift > 15 ) {
- cpustate->CF = (upper & (1 << (16-shift))) ? 1 : 0;
+ m_CF = (upper & (1 << (16-shift))) ? 1 : 0;
dst = (upper << (shift-16)) | (upper >> (32-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 15);
+ m_OF = m_CF ^ (dst >> 15);
SetSZPF16(dst);
} else {
- cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0;
+ m_CF = (dst & (1 << (16-shift))) ? 1 : 0;
dst = (dst << shift) | (upper >> (16-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 15);
+ m_OF = m_CF ^ (dst >> 15);
SetSZPF16(dst);
}
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_SHLD_REG);
+ CYCLES(CYCLES_SHLD_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
UINT16 upper = LOAD_REG16(modrm);
UINT8 shift = REG8(CL);
shift &= 31;
if( shift == 0 ) {
} else if( shift > 15 ) {
- cpustate->CF = (upper & (1 << (16-shift))) ? 1 : 0;
+ m_CF = (upper & (1 << (16-shift))) ? 1 : 0;
dst = (upper << (shift-16)) | (upper >> (32-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 15);
+ m_OF = m_CF ^ (dst >> 15);
SetSZPF16(dst);
} else {
- cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0;
+ m_CF = (dst & (1 << (16-shift))) ? 1 : 0;
dst = (dst << shift) | (upper >> (16-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 15);
+ m_OF = m_CF ^ (dst >> 15);
SetSZPF16(dst);
}
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_SHLD_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_SHLD_MEM);
}
}
-static void I386OP(shrd16_i8)(i386_state *cpustate) // Opcode 0x0f ac
+void i386_device::i386_shrd16_i8() // Opcode 0x0f ac
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 upper = LOAD_REG16(modrm);
- UINT8 shift = FETCH(cpustate);
+ UINT8 shift = FETCH();
shift &= 31;
if( shift == 0) {
} else if( shift > 15 ) {
- cpustate->CF = (upper & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (upper & (1 << (shift-1))) ? 1 : 0;
dst = (upper >> (shift-16)) | (upper << (32-shift));
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
SetSZPF16(dst);
} else {
- cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (dst & (1 << (shift-1))) ? 1 : 0;
dst = (dst >> shift) | (upper << (16-shift));
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
SetSZPF16(dst);
}
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_SHRD_REG);
+ CYCLES(CYCLES_SHRD_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
UINT16 upper = LOAD_REG16(modrm);
- UINT8 shift = FETCH(cpustate);
+ UINT8 shift = FETCH();
shift &= 31;
if( shift == 0) {
} else if( shift > 15 ) {
- cpustate->CF = (upper & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (upper & (1 << (shift-1))) ? 1 : 0;
dst = (upper >> (shift-16)) | (upper << (32-shift));
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
SetSZPF16(dst);
} else {
- cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (dst & (1 << (shift-1))) ? 1 : 0;
dst = (dst >> shift) | (upper << (16-shift));
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
SetSZPF16(dst);
}
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_SHRD_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_SHRD_MEM);
}
}
-static void I386OP(shrd16_cl)(i386_state *cpustate) // Opcode 0x0f ad
+void i386_device::i386_shrd16_cl() // Opcode 0x0f ad
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 upper = LOAD_REG16(modrm);
@@ -2147,619 +2147,619 @@ static void I386OP(shrd16_cl)(i386_state *cpustate) // Opcode 0x0f ad
shift &= 31;
if( shift == 0) {
} else if( shift > 15 ) {
- cpustate->CF = (upper & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (upper & (1 << (shift-1))) ? 1 : 0;
dst = (upper >> (shift-16)) | (upper << (32-shift));
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
SetSZPF16(dst);
} else {
- cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (dst & (1 << (shift-1))) ? 1 : 0;
dst = (dst >> shift) | (upper << (16-shift));
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
SetSZPF16(dst);
}
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_SHRD_REG);
+ CYCLES(CYCLES_SHRD_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
UINT16 upper = LOAD_REG16(modrm);
UINT8 shift = REG8(CL);
shift &= 31;
if( shift == 0) {
} else if( shift > 15 ) {
- cpustate->CF = (upper & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (upper & (1 << (shift-1))) ? 1 : 0;
dst = (upper >> (shift-16)) | (upper << (32-shift));
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
SetSZPF16(dst);
} else {
- cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (dst & (1 << (shift-1))) ? 1 : 0;
dst = (dst >> shift) | (upper << (16-shift));
- cpustate->OF = ((dst >> 15) ^ (dst >> 14)) & 1;
+ m_OF = ((dst >> 15) ^ (dst >> 14)) & 1;
SetSZPF16(dst);
}
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_SHRD_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_SHRD_MEM);
}
}
-static void I386OP(stosw)(i386_state *cpustate) // Opcode 0xab
+void i386_device::i386_stosw() // Opcode 0xab
{
UINT32 ead;
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 1 );
- WRITE16(cpustate,ead, REG16(AX));
- BUMP_DI(cpustate,2);
- CYCLES(cpustate,CYCLES_STOS);
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 1 );
+ WRITE16(ead, REG16(AX));
+ BUMP_DI(2);
+ CYCLES(CYCLES_STOS);
}
-static void I386OP(sub_rm16_r16)(i386_state *cpustate) // Opcode 0x29
+void i386_device::i386_sub_rm16_r16() // Opcode 0x29
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
- dst = SUB16(cpustate,dst, src);
+ dst = SUB16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
- dst = SUB16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ16(ea);
+ dst = SUB16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(sub_r16_rm16)(i386_state *cpustate) // Opcode 0x2b
+void i386_device::i386_sub_r16_rm16() // Opcode 0x2b
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
dst = LOAD_REG16(modrm);
- dst = SUB16(cpustate,dst, src);
+ dst = SUB16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
dst = LOAD_REG16(modrm);
- dst = SUB16(cpustate,dst, src);
+ dst = SUB16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(sub_ax_i16)(i386_state *cpustate) // Opcode 0x2d
+void i386_device::i386_sub_ax_i16() // Opcode 0x2d
{
UINT16 src, dst;
- src = FETCH16(cpustate);
+ src = FETCH16();
dst = REG16(AX);
- dst = SUB16(cpustate,dst, src);
+ dst = SUB16(dst, src);
REG16(AX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(test_ax_i16)(i386_state *cpustate) // Opcode 0xa9
+void i386_device::i386_test_ax_i16() // Opcode 0xa9
{
- UINT16 src = FETCH16(cpustate);
+ UINT16 src = FETCH16();
UINT16 dst = REG16(AX);
dst = src & dst;
SetSZPF16(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_TEST_IMM_ACC);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_TEST_IMM_ACC);
}
-static void I386OP(test_rm16_r16)(i386_state *cpustate) // Opcode 0x85
+void i386_device::i386_test_rm16_r16() // Opcode 0x85
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
dst = src & dst;
SetSZPF16(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_TEST_REG_REG);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_TEST_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
+ UINT32 ea = GetEA(modrm,0);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
+ dst = READ16(ea);
dst = src & dst;
SetSZPF16(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_TEST_REG_MEM);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_TEST_REG_MEM);
}
}
-static void I386OP(xchg_ax_cx)(i386_state *cpustate) // Opcode 0x91
+void i386_device::i386_xchg_ax_cx() // Opcode 0x91
{
UINT16 temp;
temp = REG16(AX);
REG16(AX) = REG16(CX);
REG16(CX) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_ax_dx)(i386_state *cpustate) // Opcode 0x92
+void i386_device::i386_xchg_ax_dx() // Opcode 0x92
{
UINT16 temp;
temp = REG16(AX);
REG16(AX) = REG16(DX);
REG16(DX) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_ax_bx)(i386_state *cpustate) // Opcode 0x93
+void i386_device::i386_xchg_ax_bx() // Opcode 0x93
{
UINT16 temp;
temp = REG16(AX);
REG16(AX) = REG16(BX);
REG16(BX) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_ax_sp)(i386_state *cpustate) // Opcode 0x94
+void i386_device::i386_xchg_ax_sp() // Opcode 0x94
{
UINT16 temp;
temp = REG16(AX);
REG16(AX) = REG16(SP);
REG16(SP) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_ax_bp)(i386_state *cpustate) // Opcode 0x95
+void i386_device::i386_xchg_ax_bp() // Opcode 0x95
{
UINT16 temp;
temp = REG16(AX);
REG16(AX) = REG16(BP);
REG16(BP) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_ax_si)(i386_state *cpustate) // Opcode 0x96
+void i386_device::i386_xchg_ax_si() // Opcode 0x96
{
UINT16 temp;
temp = REG16(AX);
REG16(AX) = REG16(SI);
REG16(SI) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_ax_di)(i386_state *cpustate) // Opcode 0x97
+void i386_device::i386_xchg_ax_di() // Opcode 0x97
{
UINT16 temp;
temp = REG16(AX);
REG16(AX) = REG16(DI);
REG16(DI) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_r16_rm16)(i386_state *cpustate) // Opcode 0x87
+void i386_device::i386_xchg_r16_rm16() // Opcode 0x87
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 src = LOAD_RM16(modrm);
UINT16 dst = LOAD_REG16(modrm);
STORE_REG16(modrm, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 src = READ16(ea);
UINT16 dst = LOAD_REG16(modrm);
STORE_REG16(modrm, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_XCHG_REG_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_XCHG_REG_MEM);
}
}
-static void I386OP(xor_rm16_r16)(i386_state *cpustate) // Opcode 0x31
+void i386_device::i386_xor_rm16_r16() // Opcode 0x31
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG16(modrm);
dst = LOAD_RM16(modrm);
- dst = XOR16(cpustate,dst, src);
+ dst = XOR16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate,ea);
- dst = XOR16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ16(ea);
+ dst = XOR16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(xor_r16_rm16)(i386_state *cpustate) // Opcode 0x33
+void i386_device::i386_xor_r16_rm16() // Opcode 0x33
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
dst = LOAD_REG16(modrm);
- dst = XOR16(cpustate,dst, src);
+ dst = XOR16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
dst = LOAD_REG16(modrm);
- dst = XOR16(cpustate,dst, src);
+ dst = XOR16(dst, src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(xor_ax_i16)(i386_state *cpustate) // Opcode 0x35
+void i386_device::i386_xor_ax_i16() // Opcode 0x35
{
UINT16 src, dst;
- src = FETCH16(cpustate);
+ src = FETCH16();
dst = REG16(AX);
- dst = XOR16(cpustate,dst, src);
+ dst = XOR16(dst, src);
REG16(AX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(group81_16)(i386_state *cpustate) // Opcode 0x81
+void i386_device::i386_group81_16() // Opcode 0x81
{
UINT32 ea;
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: // ADD Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = FETCH16(cpustate);
- dst = ADD16(cpustate,dst, src);
+ src = FETCH16();
+ dst = ADD16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = FETCH16(cpustate);
- dst = ADD16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = FETCH16();
+ dst = ADD16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 1: // OR Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = FETCH16(cpustate);
- dst = OR16(cpustate,dst, src);
+ src = FETCH16();
+ dst = OR16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = FETCH16(cpustate);
- dst = OR16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = FETCH16();
+ dst = OR16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 2: // ADC Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = FETCH16(cpustate);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
+ src = FETCH16();
+ dst = ADC16(dst, src, m_CF);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = FETCH16(cpustate);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = FETCH16();
+ dst = ADC16(dst, src, m_CF);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 3: // SBB Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = FETCH16(cpustate);
- dst = SBB16(cpustate, dst, src, cpustate->CF);
+ src = FETCH16();
+ dst = SBB16(dst, src, m_CF);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = FETCH16(cpustate);
- dst = SBB16(cpustate, dst, src, cpustate->CF);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = FETCH16();
+ dst = SBB16(dst, src, m_CF);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 4: // AND Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = FETCH16(cpustate);
- dst = AND16(cpustate,dst, src);
+ src = FETCH16();
+ dst = AND16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = FETCH16(cpustate);
- dst = AND16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = FETCH16();
+ dst = AND16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 5: // SUB Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = FETCH16(cpustate);
- dst = SUB16(cpustate,dst, src);
+ src = FETCH16();
+ dst = SUB16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = FETCH16(cpustate);
- dst = SUB16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = FETCH16();
+ dst = SUB16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 6: // XOR Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = FETCH16(cpustate);
- dst = XOR16(cpustate,dst, src);
+ src = FETCH16();
+ dst = XOR16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = FETCH16(cpustate);
- dst = XOR16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = FETCH16();
+ dst = XOR16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 7: // CMP Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = FETCH16(cpustate);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ src = FETCH16();
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- dst = READ16(cpustate,ea);
- src = FETCH16(cpustate);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_MEM);
+ ea = GetEA(modrm,0);
+ dst = READ16(ea);
+ src = FETCH16();
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_REG_MEM);
}
break;
}
}
-static void I386OP(group83_16)(i386_state *cpustate) // Opcode 0x83
+void i386_device::i386_group83_16() // Opcode 0x83
{
UINT32 ea;
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: // ADD Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = ADD16(cpustate,dst, src);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = ADD16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = ADD16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = ADD16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 1: // OR Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = OR16(cpustate,dst, src);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = OR16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = OR16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = OR16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 2: // ADC Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = ADC16(dst, src, m_CF);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = ADC16(cpustate, dst, src, cpustate->CF);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = ADC16(dst, src, m_CF);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 3: // SBB Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = ((UINT16)(INT16)(INT8)FETCH(cpustate));
- dst = SBB16(cpustate, dst, src, cpustate->CF);
+ src = ((UINT16)(INT16)(INT8)FETCH());
+ dst = SBB16(dst, src, m_CF);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = ((UINT16)(INT16)(INT8)FETCH(cpustate));
- dst = SBB16(cpustate, dst, src, cpustate->CF);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = ((UINT16)(INT16)(INT8)FETCH());
+ dst = SBB16(dst, src, m_CF);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 4: // AND Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = AND16(cpustate,dst, src);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = AND16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = AND16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = AND16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 5: // SUB Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = SUB16(cpustate,dst, src);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = SUB16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = SUB16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = SUB16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 6: // XOR Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = XOR16(cpustate,dst, src);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = XOR16(dst, src);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- dst = XOR16(cpustate,dst, src);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ dst = XOR16(dst, src);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 7: // CMP Rm16, i16
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- dst = READ16(cpustate,ea);
- src = (UINT16)(INT16)(INT8)FETCH(cpustate);
- SUB16(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_MEM);
+ ea = GetEA(modrm,0);
+ dst = READ16(ea);
+ src = (UINT16)(INT16)(INT8)FETCH();
+ SUB16(dst, src);
+ CYCLES(CYCLES_CMP_REG_MEM);
}
break;
}
}
-static void I386OP(groupC1_16)(i386_state *cpustate) // Opcode 0xc1
+void i386_device::i386_groupC1_16() // Opcode 0xc1
{
UINT16 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 shift;
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- shift = FETCH(cpustate) & 0x1f;
- dst = i386_shift_rotate16(cpustate, modrm, dst, shift);
+ shift = FETCH() & 0x1f;
+ dst = i386_shift_rotate16(modrm, dst, shift);
STORE_RM16(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- shift = FETCH(cpustate) & 0x1f;
- dst = i386_shift_rotate16(cpustate, modrm, dst, shift);
- WRITE16(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ shift = FETCH() & 0x1f;
+ dst = i386_shift_rotate16(modrm, dst, shift);
+ WRITE16(ea, dst);
}
}
-static void I386OP(groupD1_16)(i386_state *cpustate) // Opcode 0xd1
+void i386_device::i386_groupD1_16() // Opcode 0xd1
{
UINT16 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- dst = i386_shift_rotate16(cpustate, modrm, dst, 1);
+ dst = i386_shift_rotate16(modrm, dst, 1);
STORE_RM16(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- dst = i386_shift_rotate16(cpustate, modrm, dst, 1);
- WRITE16(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ dst = i386_shift_rotate16(modrm, dst, 1);
+ WRITE16(ea, dst);
}
}
-static void I386OP(groupD3_16)(i386_state *cpustate) // Opcode 0xd3
+void i386_device::i386_groupD3_16() // Opcode 0xd3
{
UINT16 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
dst = LOAD_RM16(modrm);
- dst = i386_shift_rotate16(cpustate, modrm, dst, REG8(CL));
+ dst = i386_shift_rotate16(modrm, dst, REG8(CL));
STORE_RM16(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ16(cpustate,ea);
- dst = i386_shift_rotate16(cpustate, modrm, dst, REG8(CL));
- WRITE16(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ16(ea);
+ dst = i386_shift_rotate16(modrm, dst, REG8(CL));
+ WRITE16(ea, dst);
}
}
-static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
+void i386_device::i386_groupF7_16() // Opcode 0xf7
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: /* TEST Rm16, i16 */
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
- UINT16 src = FETCH16(cpustate);
+ UINT16 src = FETCH16();
dst &= src;
- cpustate->CF = cpustate->OF = cpustate->AF = 0;
+ m_CF = m_OF = m_AF = 0;
SetSZPF16(dst);
- CYCLES(cpustate,CYCLES_TEST_IMM_REG);
+ CYCLES(CYCLES_TEST_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT16 dst = READ16(cpustate,ea);
- UINT16 src = FETCH16(cpustate);
+ UINT32 ea = GetEA(modrm,0);
+ UINT16 dst = READ16(ea);
+ UINT16 src = FETCH16();
dst &= src;
- cpustate->CF = cpustate->OF = cpustate->AF = 0;
+ m_CF = m_OF = m_AF = 0;
SetSZPF16(dst);
- CYCLES(cpustate,CYCLES_TEST_IMM_MEM);
+ CYCLES(CYCLES_TEST_IMM_MEM);
}
break;
case 2: /* NOT Rm16 */
@@ -2767,27 +2767,27 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
UINT16 dst = LOAD_RM16(modrm);
dst = ~dst;
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_NOT_REG);
+ CYCLES(CYCLES_NOT_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
dst = ~dst;
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_NOT_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_NOT_MEM);
}
break;
case 3: /* NEG Rm16 */
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
- dst = SUB16(cpustate, 0, dst );
+ dst = SUB16(0, dst );
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_NEG_REG);
+ CYCLES(CYCLES_NEG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
- dst = SUB16(cpustate, 0, dst );
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_NEG_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
+ dst = SUB16(0, dst );
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_NEG_MEM);
}
break;
case 4: /* MUL AX, Rm16 */
@@ -2796,11 +2796,11 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
UINT16 src, dst;
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_MUL16_ACC_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_MUL16_ACC_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_MUL16_ACC_MEM); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
+ CYCLES(CYCLES_MUL16_ACC_MEM); /* TODO: Correct multiply timing */
}
dst = REG16(AX);
@@ -2808,7 +2808,7 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
REG16(DX) = (UINT16)(result >> 16);
REG16(AX) = (UINT16)result;
- cpustate->CF = cpustate->OF = (REG16(DX) != 0);
+ m_CF = m_OF = (REG16(DX) != 0);
}
break;
case 5: /* IMUL AX, Rm16 */
@@ -2817,11 +2817,11 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
INT32 src, dst;
if( modrm >= 0xc0 ) {
src = (INT32)(INT16)LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_IMUL16_ACC_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL16_ACC_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = (INT32)(INT16)READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL16_ACC_MEM); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ src = (INT32)(INT16)READ16(ea);
+ CYCLES(CYCLES_IMUL16_ACC_MEM); /* TODO: Correct multiply timing */
}
dst = (INT32)(INT16)REG16(AX);
@@ -2830,7 +2830,7 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
REG16(DX) = (UINT16)(result >> 16);
REG16(AX) = (UINT16)result;
- cpustate->CF = cpustate->OF = !(result == (INT32)(INT16)result);
+ m_CF = m_OF = !(result == (INT32)(INT16)result);
}
break;
case 6: /* DIV AX, Rm16 */
@@ -2839,11 +2839,11 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
UINT16 src;
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_DIV16_ACC_REG);
+ CYCLES(CYCLES_DIV16_ACC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_DIV16_ACC_MEM);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
+ CYCLES(CYCLES_DIV16_ACC_MEM);
}
quotient = ((UINT32)(REG16(DX)) << 16) | (UINT32)(REG16(AX));
@@ -2857,11 +2857,11 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
REG16(AX) = (UINT16)result;
// this flag is actually undefined, enable on non-cyrix
- if (cpustate->cpuid_id0 != 0x69727943)
- cpustate->CF = 1;
+ if (m_cpuid_id0 != 0x69727943)
+ m_CF = 1;
}
} else {
- i386_trap(cpustate, 0, 0, 0);
+ i386_trap(0, 0, 0);
}
}
break;
@@ -2871,11 +2871,11 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
UINT16 src;
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_IDIV16_ACC_REG);
+ CYCLES(CYCLES_IDIV16_ACC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_IDIV16_ACC_MEM);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
+ CYCLES(CYCLES_IDIV16_ACC_MEM);
}
quotient = (((INT32)REG16(DX)) << 16) | ((UINT32)REG16(AX));
@@ -2889,49 +2889,49 @@ static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7
REG16(AX) = (UINT16)result;
// this flag is actually undefined, enable on non-cyrix
- if (cpustate->cpuid_id0 != 0x69727943)
- cpustate->CF = 1;
+ if (m_cpuid_id0 != 0x69727943)
+ m_CF = 1;
}
} else {
- i386_trap(cpustate, 0, 0, 0);
+ i386_trap(0, 0, 0);
}
}
break;
}
}
-static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff
+void i386_device::i386_groupFF_16() // Opcode 0xff
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: /* INC Rm16 */
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
- dst = INC16(cpustate,dst);
+ dst = INC16(dst);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_INC_REG);
+ CYCLES(CYCLES_INC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
- dst = INC16(cpustate,dst);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_INC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
+ dst = INC16(dst);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_INC_MEM);
}
break;
case 1: /* DEC Rm16 */
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
- dst = DEC16(cpustate,dst);
+ dst = DEC16(dst);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_DEC_REG);
+ CYCLES(CYCLES_DEC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
- dst = DEC16(cpustate,dst);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_DEC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
+ dst = DEC16(dst);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_DEC_MEM);
}
break;
case 2: /* CALL Rm16 */
@@ -2939,15 +2939,15 @@ static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff
UINT16 address;
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_CALL_REG); /* TODO: Timing = 7 + m */
+ CYCLES(CYCLES_CALL_REG); /* TODO: Timing = 7 + m */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- address = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */
+ UINT32 ea = GetEA(modrm,0);
+ address = READ16(ea);
+ CYCLES(CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */
}
- PUSH16(cpustate, cpustate->eip );
- cpustate->eip = address;
- CHANGE_PC(cpustate,cpustate->eip);
+ PUSH16(m_eip );
+ m_eip = address;
+ CHANGE_PC(m_eip);
}
break;
case 3: /* CALL FAR Rm16 */
@@ -2955,28 +2955,28 @@ static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff
UINT16 address, selector;
if( modrm >= 0xc0 )
{
- report_invalid_modrm(cpustate, "groupFF_16", modrm);
+ report_invalid_modrm("groupFF_16", modrm);
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- address = READ16(cpustate,ea + 0);
- selector = READ16(cpustate,ea + 2);
- CYCLES(cpustate,CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */
+ UINT32 ea = GetEA(modrm,0);
+ address = READ16(ea + 0);
+ selector = READ16(ea + 2);
+ CYCLES(CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_call(cpustate,selector,address,1,0);
+ i386_protected_mode_call(selector,address,1,0);
}
else
{
- PUSH16(cpustate, cpustate->sreg[CS].selector );
- PUSH16(cpustate, cpustate->eip );
- cpustate->sreg[CS].selector = selector;
- cpustate->performed_intersegment_jump = 1;
- i386_load_segment_descriptor(cpustate, CS );
- cpustate->eip = address;
- CHANGE_PC(cpustate,cpustate->eip);
+ PUSH16(m_sreg[CS].selector );
+ PUSH16(m_eip );
+ m_sreg[CS].selector = selector;
+ m_performed_intersegment_jump = 1;
+ i386_load_segment_descriptor(CS );
+ m_eip = address;
+ CHANGE_PC(m_eip);
}
}
}
@@ -2986,14 +2986,14 @@ static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff
UINT16 address;
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_JMP_REG); /* TODO: Timing = 7 + m */
+ CYCLES(CYCLES_JMP_REG); /* TODO: Timing = 7 + m */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- address = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_JMP_MEM); /* TODO: Timing = 10 + m */
+ UINT32 ea = GetEA(modrm,0);
+ address = READ16(ea);
+ CYCLES(CYCLES_JMP_MEM); /* TODO: Timing = 10 + m */
}
- cpustate->eip = address;
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = address;
+ CHANGE_PC(m_eip);
}
break;
case 5: /* JMP FAR Rm16 */
@@ -3002,25 +3002,25 @@ static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff
if( modrm >= 0xc0 )
{
- report_invalid_modrm(cpustate, "groupFF_16", modrm);
+ report_invalid_modrm("groupFF_16", modrm);
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- address = READ16(cpustate,ea + 0);
- selector = READ16(cpustate,ea + 2);
- CYCLES(cpustate,CYCLES_JMP_MEM_INTERSEG); /* TODO: Timing = 10 + m */
+ UINT32 ea = GetEA(modrm,0);
+ address = READ16(ea + 0);
+ selector = READ16(ea + 2);
+ CYCLES(CYCLES_JMP_MEM_INTERSEG); /* TODO: Timing = 10 + m */
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_jump(cpustate,selector,address,1,0);
+ i386_protected_mode_jump(selector,address,1,0);
}
else
{
- cpustate->sreg[CS].selector = selector;
- cpustate->performed_intersegment_jump = 1;
- i386_load_segment_descriptor(cpustate, CS );
- cpustate->eip = address;
- CHANGE_PC(cpustate,cpustate->eip);
+ m_sreg[CS].selector = selector;
+ m_performed_intersegment_jump = 1;
+ i386_load_segment_descriptor(CS );
+ m_eip = address;
+ CHANGE_PC(m_eip);
}
}
}
@@ -3031,23 +3031,23 @@ static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff
if( modrm >= 0xc0 ) {
value = LOAD_RM16(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- value = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ value = READ16(ea);
}
- PUSH16(cpustate,value);
- CYCLES(cpustate,CYCLES_PUSH_RM);
+ PUSH16(value);
+ CYCLES(CYCLES_PUSH_RM);
}
break;
default:
- report_invalid_modrm(cpustate, "groupFF_16", modrm);
+ report_invalid_modrm("groupFF_16", modrm);
break;
}
}
-static void I386OP(group0F00_16)(i386_state *cpustate) // Opcode 0x0f 00
+void i386_device::i386_group0F00_16() // Opcode 0x0f 00
{
UINT32 address, ea;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
I386_SREG seg;
UINT8 result;
@@ -3057,87 +3057,87 @@ static void I386OP(group0F00_16)(i386_state *cpustate) // Opcode 0x0f 0
if ( PROTECTED_MODE && !V8086_MODE )
{
if( modrm >= 0xc0 ) {
- STORE_RM16(modrm, cpustate->ldtr.segment);
- CYCLES(cpustate,CYCLES_SLDT_REG);
+ STORE_RM16(modrm, m_ldtr.segment);
+ CYCLES(CYCLES_SLDT_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate, ea, cpustate->ldtr.segment);
- CYCLES(cpustate,CYCLES_SLDT_MEM);
+ ea = GetEA(modrm,1);
+ WRITE16(ea, m_ldtr.segment);
+ CYCLES(CYCLES_SLDT_MEM);
}
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
break;
case 1: /* STR */
if ( PROTECTED_MODE && !V8086_MODE )
{
if( modrm >= 0xc0 ) {
- STORE_RM16(modrm, cpustate->task.segment);
- CYCLES(cpustate,CYCLES_STR_REG);
+ STORE_RM16(modrm, m_task.segment);
+ CYCLES(CYCLES_STR_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate, ea, cpustate->task.segment);
- CYCLES(cpustate,CYCLES_STR_MEM);
+ ea = GetEA(modrm,1);
+ WRITE16(ea, m_task.segment);
+ CYCLES(CYCLES_STR_MEM);
}
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
break;
case 2: /* LLDT */
if ( PROTECTED_MODE && !V8086_MODE )
{
- if(cpustate->CPL)
+ if(m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- cpustate->ldtr.segment = address;
- CYCLES(cpustate,CYCLES_LLDT_REG);
+ m_ldtr.segment = address;
+ CYCLES(CYCLES_LLDT_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- cpustate->ldtr.segment = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_LLDT_MEM);
+ ea = GetEA(modrm,0);
+ m_ldtr.segment = READ16(ea);
+ CYCLES(CYCLES_LLDT_MEM);
}
memset(&seg, 0, sizeof(seg));
- seg.selector = cpustate->ldtr.segment;
- i386_load_protected_mode_segment(cpustate,&seg,NULL);
- cpustate->ldtr.limit = seg.limit;
- cpustate->ldtr.base = seg.base;
- cpustate->ldtr.flags = seg.flags;
+ seg.selector = m_ldtr.segment;
+ i386_load_protected_mode_segment(&seg,NULL);
+ m_ldtr.limit = seg.limit;
+ m_ldtr.base = seg.base;
+ m_ldtr.flags = seg.flags;
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
break;
case 3: /* LTR */
if ( PROTECTED_MODE && !V8086_MODE )
{
- if(cpustate->CPL)
+ if(m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- cpustate->task.segment = address;
- CYCLES(cpustate,CYCLES_LTR_REG);
+ m_task.segment = address;
+ CYCLES(CYCLES_LTR_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- cpustate->task.segment = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_LTR_MEM);
+ ea = GetEA(modrm,0);
+ m_task.segment = READ16(ea);
+ CYCLES(CYCLES_LTR_MEM);
}
memset(&seg, 0, sizeof(seg));
- seg.selector = cpustate->task.segment;
- i386_load_protected_mode_segment(cpustate,&seg,NULL);
- cpustate->task.limit = seg.limit;
- cpustate->task.base = seg.base;
- cpustate->task.flags = seg.flags;
+ seg.selector = m_task.segment;
+ i386_load_protected_mode_segment(&seg,NULL);
+ m_task.limit = seg.limit;
+ m_task.base = seg.base;
+ m_task.flags = seg.flags;
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
break;
@@ -3147,15 +3147,15 @@ static void I386OP(group0F00_16)(i386_state *cpustate) // Opcode 0x0f 0
result = 1;
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_VERR_REG);
+ CYCLES(CYCLES_VERR_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- address = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_VERR_MEM);
+ ea = GetEA(modrm,0);
+ address = READ16(ea);
+ CYCLES(CYCLES_VERR_MEM);
}
memset(&seg, 0, sizeof(seg));
seg.selector = address;
- result = i386_load_protected_mode_segment(cpustate,&seg,NULL);
+ result = i386_load_protected_mode_segment(&seg,NULL);
// check if the segment is a code or data segment (not a special segment type, like a TSS, gate, LDT...)
if(!(seg.flags & 0x10))
result = 0;
@@ -3184,7 +3184,7 @@ static void I386OP(group0F00_16)(i386_state *cpustate) // Opcode 0x0f 0
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
logerror("i386: VERR: Exception - Running in real mode or virtual 8086 mode.\n");
}
break;
@@ -3195,15 +3195,15 @@ static void I386OP(group0F00_16)(i386_state *cpustate) // Opcode 0x0f 0
result = 1;
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_VERW_REG);
+ CYCLES(CYCLES_VERW_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- address = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_VERW_MEM);
+ ea = GetEA(modrm,0);
+ address = READ16(ea);
+ CYCLES(CYCLES_VERW_MEM);
}
memset(&seg, 0, sizeof(seg));
seg.selector = address;
- result = i386_load_protected_mode_segment(cpustate,&seg,NULL);
+ result = i386_load_protected_mode_segment(&seg,NULL);
// check if the segment is a code or data segment (not a special segment type, like a TSS, gate, LDT...)
if(!(seg.flags & 0x10))
result = 0;
@@ -3227,20 +3227,20 @@ static void I386OP(group0F00_16)(i386_state *cpustate) // Opcode 0x0f 0
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
logerror("i386: VERW: Exception - Running in real mode or virtual 8086 mode.\n");
}
break;
default:
- report_invalid_modrm(cpustate, "group0F00_16", modrm);
+ report_invalid_modrm("group0F00_16", modrm);
break;
}
}
-static void I386OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01
+void i386_device::i386_group0F01_16() // Opcode 0x0f 01
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT16 address;
UINT32 ea;
@@ -3250,13 +3250,13 @@ static void I386OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01
{
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- ea = i386_translate(cpustate, CS, address, 1 );
+ ea = i386_translate(CS, address, 1 );
} else {
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
}
- WRITE16(cpustate,ea, cpustate->gdtr.limit);
- WRITE32(cpustate,ea + 2, cpustate->gdtr.base & 0xffffff);
- CYCLES(cpustate,CYCLES_SGDT);
+ WRITE16(ea, m_gdtr.limit);
+ WRITE32(ea + 2, m_gdtr.base & 0xffffff);
+ CYCLES(CYCLES_SGDT);
break;
}
case 1: /* SIDT */
@@ -3264,207 +3264,207 @@ static void I386OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01
if (modrm >= 0xc0)
{
address = LOAD_RM16(modrm);
- ea = i386_translate(cpustate, CS, address, 1 );
+ ea = i386_translate(CS, address, 1 );
}
else
{
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
}
- WRITE16(cpustate,ea, cpustate->idtr.limit);
- WRITE32(cpustate,ea + 2, cpustate->idtr.base & 0xffffff);
- CYCLES(cpustate,CYCLES_SIDT);
+ WRITE16(ea, m_idtr.limit);
+ WRITE32(ea + 2, m_idtr.base & 0xffffff);
+ CYCLES(CYCLES_SIDT);
break;
}
case 2: /* LGDT */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- ea = i386_translate(cpustate, CS, address, 0 );
+ ea = i386_translate(CS, address, 0 );
} else {
- ea = GetEA(cpustate,modrm,0);
+ ea = GetEA(modrm,0);
}
- cpustate->gdtr.limit = READ16(cpustate,ea);
- cpustate->gdtr.base = READ32(cpustate,ea + 2) & 0xffffff;
- CYCLES(cpustate,CYCLES_LGDT);
+ m_gdtr.limit = READ16(ea);
+ m_gdtr.base = READ32(ea + 2) & 0xffffff;
+ CYCLES(CYCLES_LGDT);
break;
}
case 3: /* LIDT */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- ea = i386_translate(cpustate, CS, address, 0 );
+ ea = i386_translate(CS, address, 0 );
} else {
- ea = GetEA(cpustate,modrm,0);
+ ea = GetEA(modrm,0);
}
- cpustate->idtr.limit = READ16(cpustate,ea);
- cpustate->idtr.base = READ32(cpustate,ea + 2) & 0xffffff;
- CYCLES(cpustate,CYCLES_LIDT);
+ m_idtr.limit = READ16(ea);
+ m_idtr.base = READ32(ea + 2) & 0xffffff;
+ CYCLES(CYCLES_LIDT);
break;
}
case 4: /* SMSW */
{
if( modrm >= 0xc0 ) {
- STORE_RM16(modrm, cpustate->cr[0]);
- CYCLES(cpustate,CYCLES_SMSW_REG);
+ STORE_RM16(modrm, m_cr[0]);
+ CYCLES(CYCLES_SMSW_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate,ea, cpustate->cr[0]);
- CYCLES(cpustate,CYCLES_SMSW_MEM);
+ ea = GetEA(modrm,1);
+ WRITE16(ea, m_cr[0]);
+ CYCLES(CYCLES_SMSW_MEM);
}
break;
}
case 6: /* LMSW */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
UINT16 b;
if( modrm >= 0xc0 ) {
b = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_LMSW_REG);
+ CYCLES(CYCLES_LMSW_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- CYCLES(cpustate,CYCLES_LMSW_MEM);
- b = READ16(cpustate,ea);
+ ea = GetEA(modrm,0);
+ CYCLES(CYCLES_LMSW_MEM);
+ b = READ16(ea);
}
if(PROTECTED_MODE)
b |= 0x0001; // cannot return to real mode using this instruction.
- cpustate->cr[0] &= ~0x0000000f;
- cpustate->cr[0] |= b & 0x0000000f;
+ m_cr[0] &= ~0x0000000f;
+ m_cr[0] |= b & 0x0000000f;
break;
}
default:
- report_invalid_modrm(cpustate, "group0F01_16", modrm);
+ report_invalid_modrm("group0F01_16", modrm);
break;
}
}
-static void I386OP(group0FBA_16)(i386_state *cpustate) // Opcode 0x0f ba
+void i386_device::i386_group0FBA_16() // Opcode 0x0f ba
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 4: /* BT Rm16, i8 */
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
- UINT8 bit = FETCH(cpustate);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
- CYCLES(cpustate,CYCLES_BT_IMM_REG);
+ CYCLES(CYCLES_BT_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT16 dst = READ16(cpustate,ea);
- UINT8 bit = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,0);
+ UINT16 dst = READ16(ea);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
- CYCLES(cpustate,CYCLES_BT_IMM_MEM);
+ CYCLES(CYCLES_BT_IMM_MEM);
}
break;
case 5: /* BTS Rm16, i8 */
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
- UINT8 bit = FETCH(cpustate);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst |= (1 << bit);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_BTS_IMM_REG);
+ CYCLES(CYCLES_BTS_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
- UINT8 bit = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst |= (1 << bit);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTS_IMM_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_BTS_IMM_MEM);
}
break;
case 6: /* BTR Rm16, i8 */
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
- UINT8 bit = FETCH(cpustate);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst &= ~(1 << bit);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_BTR_IMM_REG);
+ CYCLES(CYCLES_BTR_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
- UINT8 bit = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst &= ~(1 << bit);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTR_IMM_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_BTR_IMM_MEM);
}
break;
case 7: /* BTC Rm16, i8 */
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
- UINT8 bit = FETCH(cpustate);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst ^= (1 << bit);
STORE_RM16(modrm, dst);
- CYCLES(cpustate,CYCLES_BTC_IMM_REG);
+ CYCLES(CYCLES_BTC_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
- UINT8 bit = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst ^= (1 << bit);
- WRITE16(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTC_IMM_MEM);
+ WRITE16(ea, dst);
+ CYCLES(CYCLES_BTC_IMM_MEM);
}
break;
default:
- report_invalid_modrm(cpustate, "group0FBA_16", modrm);
+ report_invalid_modrm("group0FBA_16", modrm);
break;
}
}
-static void I386OP(lar_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 0x02
+void i386_device::i386_lar_r16_rm16() // Opcode 0x0f 0x02
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
I386_SREG seg;
UINT8 type;
@@ -3474,28 +3474,28 @@ static void I386OP(lar_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 0x02
if(modrm >= 0xc0)
{
seg.selector = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_LAR_REG);
+ CYCLES(CYCLES_LAR_REG);
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- seg.selector = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_LAR_MEM);
+ UINT32 ea = GetEA(modrm,0);
+ seg.selector = READ16(ea);
+ CYCLES(CYCLES_LAR_MEM);
}
if(seg.selector == 0)
{
SetZF(0); // not a valid segment
- // logerror("i386 (%08x): LAR: Selector %04x is invalid type.\n",cpustate->pc,seg.selector);
+ // logerror("i386 (%08x): LAR: Selector %04x is invalid type.\n",m_pc,seg.selector);
}
else
{
- if(!i386_load_protected_mode_segment(cpustate,&seg,NULL))
+ if(!i386_load_protected_mode_segment(&seg,NULL))
{
SetZF(0);
return;
}
UINT8 DPL = (seg.flags >> 5) & 3;
- if(((DPL < cpustate->CPL) || (DPL < (seg.selector & 3))) && ((seg.flags & 0x1c) != 0x1c))
+ if(((DPL < m_CPL) || (DPL < (seg.selector & 3))) && ((seg.flags & 0x1c) != 0x1c))
{
SetZF(0);
return;
@@ -3524,14 +3524,14 @@ static void I386OP(lar_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 0x02
else
{
// illegal opcode
- i386_trap(cpustate,6,0, 0);
+ i386_trap(6,0, 0);
logerror("i386: LAR: Exception - running in real mode or virtual 8086 mode.\n");
}
}
-static void I386OP(lsl_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 0x03
+void i386_device::i386_lsl_r16_rm16() // Opcode 0x0f 0x03
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT32 limit;
I386_SREG seg;
@@ -3544,8 +3544,8 @@ static void I386OP(lsl_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 0x03
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- seg.selector = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ seg.selector = READ16(ea);
}
if(seg.selector == 0)
{
@@ -3554,13 +3554,13 @@ static void I386OP(lsl_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 0x03
else
{
UINT8 type;
- if(!i386_load_protected_mode_segment(cpustate,&seg,NULL))
+ if(!i386_load_protected_mode_segment(&seg,NULL))
{
SetZF(0);
return;
}
UINT8 DPL = (seg.flags >> 5) & 3;
- if(((DPL < cpustate->CPL) || (DPL < (seg.selector & 3))) && ((seg.flags & 0x1c) != 0x1c))
+ if(((DPL < m_CPL) || (DPL < (seg.selector & 3))) && ((seg.flags & 0x1c) != 0x1c))
{
SetZF(0);
return;
@@ -3589,15 +3589,15 @@ static void I386OP(lsl_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 0x03
}
}
else
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
-static void I386OP(bound_r16_m16_m16)(i386_state *cpustate) // Opcode 0x62
+void i386_device::i386_bound_r16_m16_m16() // Opcode 0x62
{
UINT8 modrm;
INT16 val, low, high;
- modrm = FETCH(cpustate);
+ modrm = FETCH();
if (modrm >= 0xc0)
{
@@ -3605,104 +3605,104 @@ static void I386OP(bound_r16_m16_m16)(i386_state *cpustate) // Opcode 0x62
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- low = READ16(cpustate,ea + 0);
- high = READ16(cpustate,ea + 2);
+ UINT32 ea = GetEA(modrm,0);
+ low = READ16(ea + 0);
+ high = READ16(ea + 2);
}
val = LOAD_REG16(modrm);
if ((val < low) || (val > high))
{
- CYCLES(cpustate,CYCLES_BOUND_OUT_RANGE);
- i386_trap(cpustate,5, 0, 0);
+ CYCLES(CYCLES_BOUND_OUT_RANGE);
+ i386_trap(5, 0, 0);
}
else
{
- CYCLES(cpustate,CYCLES_BOUND_IN_RANGE);
+ CYCLES(CYCLES_BOUND_IN_RANGE);
}
}
-static void I386OP(retf16)(i386_state *cpustate) // Opcode 0xcb
+void i386_device::i386_retf16() // Opcode 0xcb
{
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_retf(cpustate,0,0);
+ i386_protected_mode_retf(0,0);
}
else
{
- cpustate->eip = POP16(cpustate);
- cpustate->sreg[CS].selector = POP16(cpustate);
- i386_load_segment_descriptor(cpustate, CS );
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = POP16();
+ m_sreg[CS].selector = POP16();
+ i386_load_segment_descriptor(CS );
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_RET_INTERSEG);
+ CYCLES(CYCLES_RET_INTERSEG);
}
-static void I386OP(retf_i16)(i386_state *cpustate) // Opcode 0xca
+void i386_device::i386_retf_i16() // Opcode 0xca
{
- UINT16 count = FETCH16(cpustate);
+ UINT16 count = FETCH16();
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_retf(cpustate,count,0);
+ i386_protected_mode_retf(count,0);
}
else
{
- cpustate->eip = POP16(cpustate);
- cpustate->sreg[CS].selector = POP16(cpustate);
- i386_load_segment_descriptor(cpustate, CS );
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = POP16();
+ m_sreg[CS].selector = POP16();
+ i386_load_segment_descriptor(CS );
+ CHANGE_PC(m_eip);
REG16(SP) += count;
}
- CYCLES(cpustate,CYCLES_RET_IMM_INTERSEG);
+ CYCLES(CYCLES_RET_IMM_INTERSEG);
}
-static bool I386OP(load_far_pointer16)(i386_state *cpustate, int s)
+bool i386_device::i386_load_far_pointer16(int s)
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT16 selector;
if( modrm >= 0xc0 ) {
//logerror("i386: load_far_pointer16 NYI\n"); // don't log, NT will use this a lot
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
return false;
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- STORE_REG16(modrm, READ16(cpustate,ea + 0));
- selector = READ16(cpustate,ea + 2);
- i386_sreg_load(cpustate,selector,s,NULL);
+ UINT32 ea = GetEA(modrm,0);
+ STORE_REG16(modrm, READ16(ea + 0));
+ selector = READ16(ea + 2);
+ i386_sreg_load(selector,s,NULL);
}
return true;
}
-static void I386OP(lds16)(i386_state *cpustate) // Opcode 0xc5
+void i386_device::i386_lds16() // Opcode 0xc5
{
- if(I386OP(load_far_pointer16)(cpustate, DS))
- CYCLES(cpustate,CYCLES_LDS);
+ if(i386_load_far_pointer16(DS))
+ CYCLES(CYCLES_LDS);
}
-static void I386OP(lss16)(i386_state *cpustate) // Opcode 0x0f 0xb2
+void i386_device::i386_lss16() // Opcode 0x0f 0xb2
{
- if(I386OP(load_far_pointer16)(cpustate, SS))
- CYCLES(cpustate,CYCLES_LSS);
+ if(i386_load_far_pointer16(SS))
+ CYCLES(CYCLES_LSS);
}
-static void I386OP(les16)(i386_state *cpustate) // Opcode 0xc4
+void i386_device::i386_les16() // Opcode 0xc4
{
- if(I386OP(load_far_pointer16)(cpustate, ES))
- CYCLES(cpustate,CYCLES_LES);
+ if(i386_load_far_pointer16(ES))
+ CYCLES(CYCLES_LES);
}
-static void I386OP(lfs16)(i386_state *cpustate) // Opcode 0x0f 0xb4
+void i386_device::i386_lfs16() // Opcode 0x0f 0xb4
{
- if(I386OP(load_far_pointer16)(cpustate, FS))
- CYCLES(cpustate,CYCLES_LFS);
+ if(i386_load_far_pointer16(FS))
+ CYCLES(CYCLES_LFS);
}
-static void I386OP(lgs16)(i386_state *cpustate) // Opcode 0x0f 0xb5
+void i386_device::i386_lgs16() // Opcode 0x0f 0xb5
{
- if(I386OP(load_far_pointer16)(cpustate, GS))
- CYCLES(cpustate,CYCLES_LGS);
+ if(i386_load_far_pointer16(GS))
+ CYCLES(CYCLES_LGS);
}
diff --git a/src/emu/cpu/i386/i386op32.c b/src/emu/cpu/i386/i386op32.c
index 26d3b754d47..c476103d49d 100644
--- a/src/emu/cpu/i386/i386op32.c
+++ b/src/emu/cpu/i386/i386op32.c
@@ -1,59 +1,59 @@
-static UINT32 I386OP(shift_rotate32)(i386_state *cpustate, UINT8 modrm, UINT32 value, UINT8 shift)
+UINT32 i386_device::i386_shift_rotate32(UINT8 modrm, UINT32 value, UINT8 shift)
{
UINT32 dst, src;
dst = value;
src = value;
if( shift == 0 ) {
- CYCLES_RM(cpustate,modrm, 3, 7);
+ CYCLES_RM(modrm, 3, 7);
} else if( shift == 1 ) {
switch( (modrm >> 3) & 0x7 )
{
case 0: /* ROL rm32, 1 */
- cpustate->CF = (src & 0x80000000) ? 1 : 0;
- dst = (src << 1) + cpustate->CF;
- cpustate->OF = ((src ^ dst) & 0x80000000) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (src & 0x80000000) ? 1 : 0;
+ dst = (src << 1) + m_CF;
+ m_OF = ((src ^ dst) & 0x80000000) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 1: /* ROR rm32, 1 */
- cpustate->CF = (src & 0x1) ? 1 : 0;
- dst = (cpustate->CF << 31) | (src >> 1);
- cpustate->OF = ((src ^ dst) & 0x80000000) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (src & 0x1) ? 1 : 0;
+ dst = (m_CF << 31) | (src >> 1);
+ m_OF = ((src ^ dst) & 0x80000000) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 2: /* RCL rm32, 1 */
- dst = (src << 1) + cpustate->CF;
- cpustate->CF = (src & 0x80000000) ? 1 : 0;
- cpustate->OF = ((src ^ dst) & 0x80000000) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ dst = (src << 1) + m_CF;
+ m_CF = (src & 0x80000000) ? 1 : 0;
+ m_OF = ((src ^ dst) & 0x80000000) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 3: /* RCR rm32, 1 */
- dst = (cpustate->CF << 31) | (src >> 1);
- cpustate->CF = src & 0x1;
- cpustate->OF = ((src ^ dst) & 0x80000000) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ dst = (m_CF << 31) | (src >> 1);
+ m_CF = src & 0x1;
+ m_OF = ((src ^ dst) & 0x80000000) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 4: /* SHL/SAL rm32, 1 */
case 6:
dst = src << 1;
- cpustate->CF = (src & 0x80000000) ? 1 : 0;
- cpustate->OF = (((cpustate->CF << 31) ^ dst) & 0x80000000) ? 1 : 0;
+ m_CF = (src & 0x80000000) ? 1 : 0;
+ m_OF = (((m_CF << 31) ^ dst) & 0x80000000) ? 1 : 0;
SetSZPF32(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 5: /* SHR rm32, 1 */
dst = src >> 1;
- cpustate->CF = src & 0x1;
- cpustate->OF = (src & 0x80000000) ? 1 : 0;
+ m_CF = src & 0x1;
+ m_OF = (src & 0x80000000) ? 1 : 0;
SetSZPF32(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 7: /* SAR rm32, 1 */
dst = (INT32)(src) >> 1;
- cpustate->CF = src & 0x1;
- cpustate->OF = 0;
+ m_CF = src & 0x1;
+ m_OF = 0;
SetSZPF32(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
}
@@ -64,51 +64,51 @@ static UINT32 I386OP(shift_rotate32)(i386_state *cpustate, UINT8 modrm, UINT32 v
case 0: /* ROL rm32, i8 */
dst = ((src & ((UINT32)0xffffffff >> shift)) << shift) |
((src & ((UINT32)0xffffffff << (32-shift))) >> (32-shift));
- cpustate->CF = dst & 0x1;
- cpustate->OF = (dst & 1) ^ (dst >> 31);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = dst & 0x1;
+ m_OF = (dst & 1) ^ (dst >> 31);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 1: /* ROR rm32, i8 */
dst = ((src & ((UINT32)0xffffffff << shift)) >> shift) |
((src & ((UINT32)0xffffffff >> (32-shift))) << (32-shift));
- cpustate->CF = (dst >> 31) & 0x1;
- cpustate->OF = ((dst >> 31) ^ (dst >> 30)) & 1;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (dst >> 31) & 0x1;
+ m_OF = ((dst >> 31) ^ (dst >> 30)) & 1;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 2: /* RCL rm32, i8 */
dst = ((src & ((UINT32)0xffffffff >> shift)) << shift) |
((src & ((UINT32)0xffffffff << (33-shift))) >> (33-shift)) |
- (cpustate->CF << (shift-1));
- cpustate->CF = (src >> (32-shift)) & 0x1;
- cpustate->OF = cpustate->CF ^ ((dst >> 31) & 1);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ (m_CF << (shift-1));
+ m_CF = (src >> (32-shift)) & 0x1;
+ m_OF = m_CF ^ ((dst >> 31) & 1);
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 3: /* RCR rm32, i8 */
dst = ((src & ((UINT32)0xffffffff << shift)) >> shift) |
((src & ((UINT32)0xffffffff >> (32-shift))) << (33-shift)) |
- (cpustate->CF << (32-shift));
- cpustate->CF = (src >> (shift-1)) & 0x1;
- cpustate->OF = ((dst >> 31) ^ (dst >> 30)) & 1;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ (m_CF << (32-shift));
+ m_CF = (src >> (shift-1)) & 0x1;
+ m_OF = ((dst >> 31) ^ (dst >> 30)) & 1;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 4: /* SHL/SAL rm32, i8 */
case 6:
dst = src << shift;
- cpustate->CF = (src & (1 << (32-shift))) ? 1 : 0;
+ m_CF = (src & (1 << (32-shift))) ? 1 : 0;
SetSZPF32(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 5: /* SHR rm32, i8 */
dst = src >> shift;
- cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (src & (1 << (shift-1))) ? 1 : 0;
SetSZPF32(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 7: /* SAR rm32, i8 */
dst = (INT32)src >> shift;
- cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (src & (1 << (shift-1))) ? 1 : 0;
SetSZPF32(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
}
@@ -118,519 +118,519 @@ static UINT32 I386OP(shift_rotate32)(i386_state *cpustate, UINT8 modrm, UINT32 v
-static void I386OP(adc_rm32_r32)(i386_state *cpustate) // Opcode 0x11
+void i386_device::i386_adc_rm32_r32() // Opcode 0x11
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
+ dst = ADC32(dst, src, m_CF);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ32(ea);
+ dst = ADC32(dst, src, m_CF);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(adc_r32_rm32)(i386_state *cpustate) // Opcode 0x13
+void i386_device::i386_adc_r32_rm32() // Opcode 0x13
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
dst = LOAD_REG32(modrm);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
+ dst = ADC32(dst, src, m_CF);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
dst = LOAD_REG32(modrm);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
+ dst = ADC32(dst, src, m_CF);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(adc_eax_i32)(i386_state *cpustate) // Opcode 0x15
+void i386_device::i386_adc_eax_i32() // Opcode 0x15
{
UINT32 src, dst;
- src = FETCH32(cpustate);
+ src = FETCH32();
dst = REG32(EAX);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
+ dst = ADC32(dst, src, m_CF);
REG32(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(add_rm32_r32)(i386_state *cpustate) // Opcode 0x01
+void i386_device::i386_add_rm32_r32() // Opcode 0x01
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
- dst = ADD32(cpustate,dst, src);
+ dst = ADD32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
- dst = ADD32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ32(ea);
+ dst = ADD32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(add_r32_rm32)(i386_state *cpustate) // Opcode 0x03
+void i386_device::i386_add_r32_rm32() // Opcode 0x03
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
dst = LOAD_REG32(modrm);
- dst = ADD32(cpustate,dst, src);
+ dst = ADD32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
dst = LOAD_REG32(modrm);
- dst = ADD32(cpustate,dst, src);
+ dst = ADD32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(add_eax_i32)(i386_state *cpustate) // Opcode 0x05
+void i386_device::i386_add_eax_i32() // Opcode 0x05
{
UINT32 src, dst;
- src = FETCH32(cpustate);
+ src = FETCH32();
dst = REG32(EAX);
- dst = ADD32(cpustate,dst, src);
+ dst = ADD32(dst, src);
REG32(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(and_rm32_r32)(i386_state *cpustate) // Opcode 0x21
+void i386_device::i386_and_rm32_r32() // Opcode 0x21
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
- dst = AND32(cpustate,dst, src);
+ dst = AND32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
- dst = AND32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ32(ea);
+ dst = AND32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(and_r32_rm32)(i386_state *cpustate) // Opcode 0x23
+void i386_device::i386_and_r32_rm32() // Opcode 0x23
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
dst = LOAD_REG32(modrm);
- dst = AND32(cpustate,dst, src);
+ dst = AND32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
dst = LOAD_REG32(modrm);
- dst = AND32(cpustate,dst, src);
+ dst = AND32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(and_eax_i32)(i386_state *cpustate) // Opcode 0x25
+void i386_device::i386_and_eax_i32() // Opcode 0x25
{
UINT32 src, dst;
- src = FETCH32(cpustate);
+ src = FETCH32();
dst = REG32(EAX);
- dst = AND32(cpustate,dst, src);
+ dst = AND32(dst, src);
REG32(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(bsf_r32_rm32)(i386_state *cpustate) // Opcode 0x0f bc
+void i386_device::i386_bsf_r32_rm32() // Opcode 0x0f bc
{
UINT32 src, dst, temp;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
}
dst = 0;
if( src == 0 ) {
- cpustate->ZF = 1;
+ m_ZF = 1;
} else {
- cpustate->ZF = 0;
+ m_ZF = 0;
temp = 0;
while( (src & (1 << temp)) == 0 ) {
temp++;
dst = temp;
- CYCLES(cpustate,CYCLES_BSF);
+ CYCLES(CYCLES_BSF);
}
STORE_REG32(modrm, dst);
}
- CYCLES(cpustate,CYCLES_BSF_BASE);
+ CYCLES(CYCLES_BSF_BASE);
}
-static void I386OP(bsr_r32_rm32)(i386_state *cpustate) // Opcode 0x0f bd
+void i386_device::i386_bsr_r32_rm32() // Opcode 0x0f bd
{
UINT32 src, dst, temp;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
}
dst = 0;
if( src == 0 ) {
- cpustate->ZF = 1;
+ m_ZF = 1;
} else {
- cpustate->ZF = 0;
+ m_ZF = 0;
dst = temp = 31;
while( (src & (1 << temp)) == 0 ) {
temp--;
dst = temp;
- CYCLES(cpustate,CYCLES_BSR);
+ CYCLES(CYCLES_BSR);
}
STORE_REG32(modrm, dst);
}
- CYCLES(cpustate,CYCLES_BSR_BASE);
+ CYCLES(CYCLES_BSR_BASE);
}
-static void I386OP(bt_rm32_r32)(i386_state *cpustate) // Opcode 0x0f a3
+void i386_device::i386_bt_rm32_r32() // Opcode 0x0f a3
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 bit = LOAD_REG32(modrm);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
- CYCLES(cpustate,CYCLES_BT_REG_REG);
+ CYCLES(CYCLES_BT_REG_REG);
} else {
UINT8 segment;
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,&segment);
+ UINT32 ea = GetNonTranslatedEA(modrm,&segment);
UINT32 bit = LOAD_REG32(modrm);
ea += 4*(bit/32);
- ea = i386_translate(cpustate,segment,(cpustate->address_size)?ea:(ea&0xffff),0);
+ ea = i386_translate(segment,(m_address_size)?ea:(ea&0xffff),0);
bit %= 32;
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 dst = READ32(ea);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
- CYCLES(cpustate,CYCLES_BT_REG_MEM);
+ CYCLES(CYCLES_BT_REG_MEM);
}
}
-static void I386OP(btc_rm32_r32)(i386_state *cpustate) // Opcode 0x0f bb
+void i386_device::i386_btc_rm32_r32() // Opcode 0x0f bb
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 bit = LOAD_REG32(modrm);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst ^= (1 << bit);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_BTC_REG_REG);
+ CYCLES(CYCLES_BTC_REG_REG);
} else {
UINT8 segment;
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,&segment);
+ UINT32 ea = GetNonTranslatedEA(modrm,&segment);
UINT32 bit = LOAD_REG32(modrm);
ea += 4*(bit/32);
- ea = i386_translate(cpustate,segment,(cpustate->address_size)?ea:(ea&0xffff),1);
+ ea = i386_translate(segment,(m_address_size)?ea:(ea&0xffff),1);
bit %= 32;
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 dst = READ32(ea);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst ^= (1 << bit);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTC_REG_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_BTC_REG_MEM);
}
}
-static void I386OP(btr_rm32_r32)(i386_state *cpustate) // Opcode 0x0f b3
+void i386_device::i386_btr_rm32_r32() // Opcode 0x0f b3
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 bit = LOAD_REG32(modrm);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst &= ~(1 << bit);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_BTR_REG_REG);
+ CYCLES(CYCLES_BTR_REG_REG);
} else {
UINT8 segment;
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,&segment);
+ UINT32 ea = GetNonTranslatedEA(modrm,&segment);
UINT32 bit = LOAD_REG32(modrm);
ea += 4*(bit/32);
- ea = i386_translate(cpustate,segment,(cpustate->address_size)?ea:(ea&0xffff),1);
+ ea = i386_translate(segment,(m_address_size)?ea:(ea&0xffff),1);
bit %= 32;
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 dst = READ32(ea);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst &= ~(1 << bit);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTR_REG_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_BTR_REG_MEM);
}
}
-static void I386OP(bts_rm32_r32)(i386_state *cpustate) // Opcode 0x0f ab
+void i386_device::i386_bts_rm32_r32() // Opcode 0x0f ab
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 bit = LOAD_REG32(modrm);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst |= (1 << bit);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_BTS_REG_REG);
+ CYCLES(CYCLES_BTS_REG_REG);
} else {
UINT8 segment;
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,&segment);
+ UINT32 ea = GetNonTranslatedEA(modrm,&segment);
UINT32 bit = LOAD_REG32(modrm);
ea += 4*(bit/32);
- ea = i386_translate(cpustate,segment,(cpustate->address_size)?ea:(ea&0xffff),1);
+ ea = i386_translate(segment,(m_address_size)?ea:(ea&0xffff),1);
bit %= 32;
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 dst = READ32(ea);
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst |= (1 << bit);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTS_REG_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_BTS_REG_MEM);
}
}
-static void I386OP(call_abs32)(i386_state *cpustate) // Opcode 0x9a
+void i386_device::i386_call_abs32() // Opcode 0x9a
{
- UINT32 offset = FETCH32(cpustate);
- UINT16 ptr = FETCH16(cpustate);
+ UINT32 offset = FETCH32();
+ UINT16 ptr = FETCH16();
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_call(cpustate,ptr,offset,0,1);
+ i386_protected_mode_call(ptr,offset,0,1);
}
else
{
- PUSH32(cpustate, cpustate->sreg[CS].selector );
- PUSH32(cpustate, cpustate->eip );
- cpustate->sreg[CS].selector = ptr;
- cpustate->performed_intersegment_jump = 1;
- cpustate->eip = offset;
- i386_load_segment_descriptor(cpustate,CS);
+ PUSH32(m_sreg[CS].selector );
+ PUSH32(m_eip );
+ m_sreg[CS].selector = ptr;
+ m_performed_intersegment_jump = 1;
+ m_eip = offset;
+ i386_load_segment_descriptor(CS);
}
- CYCLES(cpustate,CYCLES_CALL_INTERSEG);
- CHANGE_PC(cpustate,cpustate->eip);
+ CYCLES(CYCLES_CALL_INTERSEG);
+ CHANGE_PC(m_eip);
}
-static void I386OP(call_rel32)(i386_state *cpustate) // Opcode 0xe8
+void i386_device::i386_call_rel32() // Opcode 0xe8
{
- INT32 disp = FETCH32(cpustate);
- PUSH32(cpustate, cpustate->eip );
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_CALL); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ PUSH32(m_eip );
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_CALL); /* TODO: Timing = 7 + m */
}
-static void I386OP(cdq)(i386_state *cpustate) // Opcode 0x99
+void i386_device::i386_cdq() // Opcode 0x99
{
if( REG32(EAX) & 0x80000000 ) {
REG32(EDX) = 0xffffffff;
} else {
REG32(EDX) = 0x00000000;
}
- CYCLES(cpustate,CYCLES_CWD);
+ CYCLES(CYCLES_CWD);
}
-static void I386OP(cmp_rm32_r32)(i386_state *cpustate) // Opcode 0x39
+void i386_device::i386_cmp_rm32_r32() // Opcode 0x39
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
+ UINT32 ea = GetEA(modrm,0);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_MEM);
+ dst = READ32(ea);
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_REG_MEM);
}
}
-static void I386OP(cmp_r32_rm32)(i386_state *cpustate) // Opcode 0x3b
+void i386_device::i386_cmp_r32_rm32() // Opcode 0x3b
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
dst = LOAD_REG32(modrm);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
dst = LOAD_REG32(modrm);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_MEM_REG);
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_MEM_REG);
}
}
-static void I386OP(cmp_eax_i32)(i386_state *cpustate) // Opcode 0x3d
+void i386_device::i386_cmp_eax_i32() // Opcode 0x3d
{
UINT32 src, dst;
- src = FETCH32(cpustate);
+ src = FETCH32();
dst = REG32(EAX);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_IMM_ACC);
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_IMM_ACC);
}
-static void I386OP(cmpsd)(i386_state *cpustate) // Opcode 0xa7
+void i386_device::i386_cmpsd() // Opcode 0xa7
{
UINT32 eas, ead, src, dst;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 0 );
- src = READ32(cpustate,eas);
- dst = READ32(cpustate,ead);
- SUB32(cpustate,src,dst);
- BUMP_SI(cpustate,4);
- BUMP_DI(cpustate,4);
- CYCLES(cpustate,CYCLES_CMPS);
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 0 );
+ src = READ32(eas);
+ dst = READ32(ead);
+ SUB32(src,dst);
+ BUMP_SI(4);
+ BUMP_DI(4);
+ CYCLES(CYCLES_CMPS);
}
-static void I386OP(cwde)(i386_state *cpustate) // Opcode 0x98
+void i386_device::i386_cwde() // Opcode 0x98
{
REG32(EAX) = (INT32)((INT16)REG16(AX));
- CYCLES(cpustate,CYCLES_CBW);
+ CYCLES(CYCLES_CBW);
}
-static void I386OP(dec_eax)(i386_state *cpustate) // Opcode 0x48
+void i386_device::i386_dec_eax() // Opcode 0x48
{
- REG32(EAX) = DEC32(cpustate, REG32(EAX) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG32(EAX) = DEC32(REG32(EAX) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_ecx)(i386_state *cpustate) // Opcode 0x49
+void i386_device::i386_dec_ecx() // Opcode 0x49
{
- REG32(ECX) = DEC32(cpustate, REG32(ECX) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG32(ECX) = DEC32(REG32(ECX) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_edx)(i386_state *cpustate) // Opcode 0x4a
+void i386_device::i386_dec_edx() // Opcode 0x4a
{
- REG32(EDX) = DEC32(cpustate, REG32(EDX) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG32(EDX) = DEC32(REG32(EDX) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_ebx)(i386_state *cpustate) // Opcode 0x4b
+void i386_device::i386_dec_ebx() // Opcode 0x4b
{
- REG32(EBX) = DEC32(cpustate, REG32(EBX) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG32(EBX) = DEC32(REG32(EBX) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_esp)(i386_state *cpustate) // Opcode 0x4c
+void i386_device::i386_dec_esp() // Opcode 0x4c
{
- REG32(ESP) = DEC32(cpustate, REG32(ESP) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG32(ESP) = DEC32(REG32(ESP) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_ebp)(i386_state *cpustate) // Opcode 0x4d
+void i386_device::i386_dec_ebp() // Opcode 0x4d
{
- REG32(EBP) = DEC32(cpustate, REG32(EBP) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG32(EBP) = DEC32(REG32(EBP) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_esi)(i386_state *cpustate) // Opcode 0x4e
+void i386_device::i386_dec_esi() // Opcode 0x4e
{
- REG32(ESI) = DEC32(cpustate, REG32(ESI) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG32(ESI) = DEC32(REG32(ESI) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(dec_edi)(i386_state *cpustate) // Opcode 0x4f
+void i386_device::i386_dec_edi() // Opcode 0x4f
{
- REG32(EDI) = DEC32(cpustate, REG32(EDI) );
- CYCLES(cpustate,CYCLES_DEC_REG);
+ REG32(EDI) = DEC32(REG32(EDI) );
+ CYCLES(CYCLES_DEC_REG);
}
-static void I386OP(imul_r32_rm32)(i386_state *cpustate) // Opcode 0x0f af
+void i386_device::i386_imul_r32_rm32() // Opcode 0x0f af
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
INT64 result;
INT64 src, dst;
if( modrm >= 0xc0 ) {
src = (INT64)(INT32)LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_IMUL32_REG_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL32_REG_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = (INT64)(INT32)READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL32_REG_REG); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ src = (INT64)(INT32)READ32(ea);
+ CYCLES(CYCLES_IMUL32_REG_REG); /* TODO: Correct multiply timing */
}
dst = (INT64)(INT32)LOAD_REG32(modrm);
@@ -638,389 +638,389 @@ static void I386OP(imul_r32_rm32)(i386_state *cpustate) // Opcode 0x0f af
STORE_REG32(modrm, (UINT32)result);
- cpustate->CF = cpustate->OF = !(result == (INT64)(INT32)result);
+ m_CF = m_OF = !(result == (INT64)(INT32)result);
}
-static void I386OP(imul_r32_rm32_i32)(i386_state *cpustate) // Opcode 0x69
+void i386_device::i386_imul_r32_rm32_i32() // Opcode 0x69
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
INT64 result;
INT64 src, dst;
if( modrm >= 0xc0 ) {
dst = (INT64)(INT32)LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_IMUL32_REG_IMM_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL32_REG_IMM_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- dst = (INT64)(INT32)READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL32_MEM_IMM_REG); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ dst = (INT64)(INT32)READ32(ea);
+ CYCLES(CYCLES_IMUL32_MEM_IMM_REG); /* TODO: Correct multiply timing */
}
- src = (INT64)(INT32)FETCH32(cpustate);
+ src = (INT64)(INT32)FETCH32();
result = src * dst;
STORE_REG32(modrm, (UINT32)result);
- cpustate->CF = cpustate->OF = !(result == (INT64)(INT32)result);
+ m_CF = m_OF = !(result == (INT64)(INT32)result);
}
-static void I386OP(imul_r32_rm32_i8)(i386_state *cpustate) // Opcode 0x6b
+void i386_device::i386_imul_r32_rm32_i8() // Opcode 0x6b
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
INT64 result;
INT64 src, dst;
if( modrm >= 0xc0 ) {
dst = (INT64)(INT32)LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_IMUL32_REG_IMM_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL32_REG_IMM_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- dst = (INT64)(INT32)READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL32_MEM_IMM_REG); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ dst = (INT64)(INT32)READ32(ea);
+ CYCLES(CYCLES_IMUL32_MEM_IMM_REG); /* TODO: Correct multiply timing */
}
- src = (INT64)(INT8)FETCH(cpustate);
+ src = (INT64)(INT8)FETCH();
result = src * dst;
STORE_REG32(modrm, (UINT32)result);
- cpustate->CF = cpustate->OF = !(result == (INT64)(INT32)result);
+ m_CF = m_OF = !(result == (INT64)(INT32)result);
}
-static void I386OP(in_eax_i8)(i386_state *cpustate) // Opcode 0xe5
+void i386_device::i386_in_eax_i8() // Opcode 0xe5
{
- UINT16 port = FETCH(cpustate);
- UINT32 data = READPORT32(cpustate, port);
+ UINT16 port = FETCH();
+ UINT32 data = READPORT32(port);
REG32(EAX) = data;
- CYCLES(cpustate,CYCLES_IN_VAR);
+ CYCLES(CYCLES_IN_VAR);
}
-static void I386OP(in_eax_dx)(i386_state *cpustate) // Opcode 0xed
+void i386_device::i386_in_eax_dx() // Opcode 0xed
{
UINT16 port = REG16(DX);
- UINT32 data = READPORT32(cpustate, port);
+ UINT32 data = READPORT32(port);
REG32(EAX) = data;
- CYCLES(cpustate,CYCLES_IN);
+ CYCLES(CYCLES_IN);
}
-static void I386OP(inc_eax)(i386_state *cpustate) // Opcode 0x40
+void i386_device::i386_inc_eax() // Opcode 0x40
{
- REG32(EAX) = INC32(cpustate, REG32(EAX) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG32(EAX) = INC32(REG32(EAX) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_ecx)(i386_state *cpustate) // Opcode 0x41
+void i386_device::i386_inc_ecx() // Opcode 0x41
{
- REG32(ECX) = INC32(cpustate, REG32(ECX) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG32(ECX) = INC32(REG32(ECX) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_edx)(i386_state *cpustate) // Opcode 0x42
+void i386_device::i386_inc_edx() // Opcode 0x42
{
- REG32(EDX) = INC32(cpustate, REG32(EDX) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG32(EDX) = INC32(REG32(EDX) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_ebx)(i386_state *cpustate) // Opcode 0x43
+void i386_device::i386_inc_ebx() // Opcode 0x43
{
- REG32(EBX) = INC32(cpustate, REG32(EBX) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG32(EBX) = INC32(REG32(EBX) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_esp)(i386_state *cpustate) // Opcode 0x44
+void i386_device::i386_inc_esp() // Opcode 0x44
{
- REG32(ESP) = INC32(cpustate, REG32(ESP) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG32(ESP) = INC32(REG32(ESP) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_ebp)(i386_state *cpustate) // Opcode 0x45
+void i386_device::i386_inc_ebp() // Opcode 0x45
{
- REG32(EBP) = INC32(cpustate, REG32(EBP) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG32(EBP) = INC32(REG32(EBP) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_esi)(i386_state *cpustate) // Opcode 0x46
+void i386_device::i386_inc_esi() // Opcode 0x46
{
- REG32(ESI) = INC32(cpustate, REG32(ESI) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG32(ESI) = INC32(REG32(ESI) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(inc_edi)(i386_state *cpustate) // Opcode 0x47
+void i386_device::i386_inc_edi() // Opcode 0x47
{
- REG32(EDI) = INC32(cpustate, REG32(EDI) );
- CYCLES(cpustate,CYCLES_INC_REG);
+ REG32(EDI) = INC32(REG32(EDI) );
+ CYCLES(CYCLES_INC_REG);
}
-static void I386OP(iret32)(i386_state *cpustate) // Opcode 0xcf
+void i386_device::i386_iret32() // Opcode 0xcf
{
if( PROTECTED_MODE )
{
- i386_protected_mode_iret(cpustate,1);
+ i386_protected_mode_iret(1);
}
else
{
/* TODO: #SS(0) exception */
/* TODO: #GP(0) exception */
- cpustate->eip = POP32(cpustate);
- cpustate->sreg[CS].selector = POP32(cpustate) & 0xffff;
- set_flags(cpustate, POP32(cpustate) );
- i386_load_segment_descriptor(cpustate,CS);
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = POP32();
+ m_sreg[CS].selector = POP32() & 0xffff;
+ set_flags(POP32() );
+ i386_load_segment_descriptor(CS);
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_IRET);
+ CYCLES(CYCLES_IRET);
}
-static void I386OP(ja_rel32)(i386_state *cpustate) // Opcode 0x0f 87
+void i386_device::i386_ja_rel32() // Opcode 0x0f 87
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->CF == 0 && cpustate->ZF == 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_CF == 0 && m_ZF == 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jbe_rel32)(i386_state *cpustate) // Opcode 0x0f 86
+void i386_device::i386_jbe_rel32() // Opcode 0x0f 86
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->CF != 0 || cpustate->ZF != 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_CF != 0 || m_ZF != 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jc_rel32)(i386_state *cpustate) // Opcode 0x0f 82
+void i386_device::i386_jc_rel32() // Opcode 0x0f 82
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->CF != 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_CF != 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jg_rel32)(i386_state *cpustate) // Opcode 0x0f 8f
+void i386_device::i386_jg_rel32() // Opcode 0x0f 8f
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->ZF == 0 && (cpustate->SF == cpustate->OF) ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_ZF == 0 && (m_SF == m_OF) ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jge_rel32)(i386_state *cpustate) // Opcode 0x0f 8d
+void i386_device::i386_jge_rel32() // Opcode 0x0f 8d
{
- INT32 disp = FETCH32(cpustate);
- if(cpustate->SF == cpustate->OF) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if(m_SF == m_OF) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jl_rel32)(i386_state *cpustate) // Opcode 0x0f 8c
+void i386_device::i386_jl_rel32() // Opcode 0x0f 8c
{
- INT32 disp = FETCH32(cpustate);
- if( (cpustate->SF != cpustate->OF) ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( (m_SF != m_OF) ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jle_rel32)(i386_state *cpustate) // Opcode 0x0f 8e
+void i386_device::i386_jle_rel32() // Opcode 0x0f 8e
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->ZF != 0 || (cpustate->SF != cpustate->OF) ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_ZF != 0 || (m_SF != m_OF) ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jnc_rel32)(i386_state *cpustate) // Opcode 0x0f 83
+void i386_device::i386_jnc_rel32() // Opcode 0x0f 83
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->CF == 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_CF == 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jno_rel32)(i386_state *cpustate) // Opcode 0x0f 81
+void i386_device::i386_jno_rel32() // Opcode 0x0f 81
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->OF == 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_OF == 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jnp_rel32)(i386_state *cpustate) // Opcode 0x0f 8b
+void i386_device::i386_jnp_rel32() // Opcode 0x0f 8b
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->PF == 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_PF == 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jns_rel32)(i386_state *cpustate) // Opcode 0x0f 89
+void i386_device::i386_jns_rel32() // Opcode 0x0f 89
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->SF == 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_SF == 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jnz_rel32)(i386_state *cpustate) // Opcode 0x0f 85
+void i386_device::i386_jnz_rel32() // Opcode 0x0f 85
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->ZF == 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_ZF == 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jo_rel32)(i386_state *cpustate) // Opcode 0x0f 80
+void i386_device::i386_jo_rel32() // Opcode 0x0f 80
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->OF != 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_OF != 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jp_rel32)(i386_state *cpustate) // Opcode 0x0f 8a
+void i386_device::i386_jp_rel32() // Opcode 0x0f 8a
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->PF != 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_PF != 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(js_rel32)(i386_state *cpustate) // Opcode 0x0f 88
+void i386_device::i386_js_rel32() // Opcode 0x0f 88
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->SF != 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_SF != 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jz_rel32)(i386_state *cpustate) // Opcode 0x0f 84
+void i386_device::i386_jz_rel32() // Opcode 0x0f 84
{
- INT32 disp = FETCH32(cpustate);
- if( cpustate->ZF != 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
+ INT32 disp = FETCH32();
+ if( m_ZF != 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH);
+ CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH);
}
}
-static void I386OP(jcxz32)(i386_state *cpustate) // Opcode 0xe3
+void i386_device::i386_jcxz32() // Opcode 0xe3
{
- INT8 disp = FETCH(cpustate);
- int val = (cpustate->address_size)?(REG32(ECX) == 0):(REG16(CX) == 0);
+ INT8 disp = FETCH();
+ int val = (m_address_size)?(REG32(ECX) == 0):(REG16(CX) == 0);
if( val ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JCXZ); /* TODO: Timing = 9 + m */
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JCXZ); /* TODO: Timing = 9 + m */
} else {
- CYCLES(cpustate,CYCLES_JCXZ_NOBRANCH);
+ CYCLES(CYCLES_JCXZ_NOBRANCH);
}
}
-static void I386OP(jmp_rel32)(i386_state *cpustate) // Opcode 0xe9
+void i386_device::i386_jmp_rel32() // Opcode 0xe9
{
- UINT32 disp = FETCH32(cpustate);
+ UINT32 disp = FETCH32();
/* TODO: Segment limit */
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_JMP); /* TODO: Timing = 7 + m */
+ m_eip += disp;
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_JMP); /* TODO: Timing = 7 + m */
}
-static void I386OP(jmp_abs32)(i386_state *cpustate) // Opcode 0xea
+void i386_device::i386_jmp_abs32() // Opcode 0xea
{
- UINT32 address = FETCH32(cpustate);
- UINT16 segment = FETCH16(cpustate);
+ UINT32 address = FETCH32();
+ UINT16 segment = FETCH16();
if( PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_jump(cpustate,segment,address,0,1);
+ i386_protected_mode_jump(segment,address,0,1);
}
else
{
- cpustate->eip = address;
- cpustate->sreg[CS].selector = segment;
- cpustate->performed_intersegment_jump = 1;
- i386_load_segment_descriptor(cpustate,CS);
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = address;
+ m_sreg[CS].selector = segment;
+ m_performed_intersegment_jump = 1;
+ i386_load_segment_descriptor(CS);
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_JMP_INTERSEG);
+ CYCLES(CYCLES_JMP_INTERSEG);
}
-static void I386OP(lea32)(i386_state *cpustate) // Opcode 0x8d
+void i386_device::i386_lea32() // Opcode 0x8d
{
- UINT8 modrm = FETCH(cpustate);
- UINT32 ea = GetNonTranslatedEA(cpustate,modrm,NULL);
- if (!cpustate->address_size)
+ UINT8 modrm = FETCH();
+ UINT32 ea = GetNonTranslatedEA(modrm,NULL);
+ if (!m_address_size)
{
ea &= 0xffff;
}
STORE_REG32(modrm, ea);
- CYCLES(cpustate,CYCLES_LEA);
+ CYCLES(CYCLES_LEA);
}
-static void I386OP(enter32)(i386_state *cpustate) // Opcode 0xc8
+void i386_device::i386_enter32() // Opcode 0xc8
{
- UINT16 framesize = FETCH16(cpustate);
- UINT8 level = FETCH(cpustate) % 32;
+ UINT16 framesize = FETCH16();
+ UINT8 level = FETCH() % 32;
UINT8 x;
UINT32 frameptr;
- PUSH32(cpustate,REG32(EBP));
+ PUSH32(REG32(EBP));
if(!STACK_32BIT)
frameptr = REG16(SP);
else
@@ -1031,435 +1031,435 @@ static void I386OP(enter32)(i386_state *cpustate) // Opcode 0xc8
for(x=1;x<level-1;x++)
{
REG32(EBP) -= 4;
- PUSH32(cpustate,READ32(cpustate,REG32(EBP)));
+ PUSH32(READ32(REG32(EBP)));
}
- PUSH32(cpustate,frameptr);
+ PUSH32(frameptr);
}
REG32(EBP) = frameptr;
if(!STACK_32BIT)
REG16(SP) -= framesize;
else
REG32(ESP) -= framesize;
- CYCLES(cpustate,CYCLES_ENTER);
+ CYCLES(CYCLES_ENTER);
}
-static void I386OP(leave32)(i386_state *cpustate) // Opcode 0xc9
+void i386_device::i386_leave32() // Opcode 0xc9
{
if(!STACK_32BIT)
REG16(SP) = REG16(BP);
else
REG32(ESP) = REG32(EBP);
- REG32(EBP) = POP32(cpustate);
- CYCLES(cpustate,CYCLES_LEAVE);
+ REG32(EBP) = POP32();
+ CYCLES(CYCLES_LEAVE);
}
-static void I386OP(lodsd)(i386_state *cpustate) // Opcode 0xad
+void i386_device::i386_lodsd() // Opcode 0xad
{
UINT32 eas;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- REG32(EAX) = READ32(cpustate,eas);
- BUMP_SI(cpustate,4);
- CYCLES(cpustate,CYCLES_LODS);
+ REG32(EAX) = READ32(eas);
+ BUMP_SI(4);
+ CYCLES(CYCLES_LODS);
}
-static void I386OP(loop32)(i386_state *cpustate) // Opcode 0xe2
+void i386_device::i386_loop32() // Opcode 0xe2
{
- INT8 disp = FETCH(cpustate);
- INT32 reg = (cpustate->address_size)?--REG32(ECX):--REG16(CX);
+ INT8 disp = FETCH();
+ INT32 reg = (m_address_size)?--REG32(ECX):--REG16(CX);
if( reg != 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip += disp;
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_LOOP); /* TODO: Timing = 11 + m */
+ CYCLES(CYCLES_LOOP); /* TODO: Timing = 11 + m */
}
-static void I386OP(loopne32)(i386_state *cpustate) // Opcode 0xe0
+void i386_device::i386_loopne32() // Opcode 0xe0
{
- INT8 disp = FETCH(cpustate);
- INT32 reg = (cpustate->address_size)?--REG32(ECX):--REG16(CX);
- if( reg != 0 && cpustate->ZF == 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
+ INT8 disp = FETCH();
+ INT32 reg = (m_address_size)?--REG32(ECX):--REG16(CX);
+ if( reg != 0 && m_ZF == 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_LOOPNZ); /* TODO: Timing = 11 + m */
+ CYCLES(CYCLES_LOOPNZ); /* TODO: Timing = 11 + m */
}
-static void I386OP(loopz32)(i386_state *cpustate) // Opcode 0xe1
+void i386_device::i386_loopz32() // Opcode 0xe1
{
- INT8 disp = FETCH(cpustate);
- INT32 reg = (cpustate->address_size)?--REG32(ECX):--REG16(CX);
- if( reg != 0 && cpustate->ZF != 0 ) {
- cpustate->eip += disp;
- CHANGE_PC(cpustate,cpustate->eip);
+ INT8 disp = FETCH();
+ INT32 reg = (m_address_size)?--REG32(ECX):--REG16(CX);
+ if( reg != 0 && m_ZF != 0 ) {
+ m_eip += disp;
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_LOOPZ); /* TODO: Timing = 11 + m */
+ CYCLES(CYCLES_LOOPZ); /* TODO: Timing = 11 + m */
}
-static void I386OP(mov_rm32_r32)(i386_state *cpustate) // Opcode 0x89
+void i386_device::i386_mov_rm32_r32() // Opcode 0x89
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
STORE_RM32(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_REG_REG);
+ CYCLES(CYCLES_MOV_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG32(modrm);
- WRITE32(cpustate,ea, src);
- CYCLES(cpustate,CYCLES_MOV_REG_MEM);
+ WRITE32(ea, src);
+ CYCLES(CYCLES_MOV_REG_MEM);
}
}
-static void I386OP(mov_r32_rm32)(i386_state *cpustate) // Opcode 0x8b
+void i386_device::i386_mov_r32_rm32() // Opcode 0x8b
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_REG_REG);
+ CYCLES(CYCLES_MOV_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_MEM_REG);
+ CYCLES(CYCLES_MOV_MEM_REG);
}
}
-static void I386OP(mov_rm32_i32)(i386_state *cpustate) // Opcode 0xc7
+void i386_device::i386_mov_rm32_i32() // Opcode 0xc7
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
- UINT32 value = FETCH32(cpustate);
+ UINT32 value = FETCH32();
STORE_RM32(modrm, value);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ CYCLES(CYCLES_MOV_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 value = FETCH32(cpustate);
- WRITE32(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_MOV_IMM_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 value = FETCH32();
+ WRITE32(ea, value);
+ CYCLES(CYCLES_MOV_IMM_MEM);
}
}
-static void I386OP(mov_eax_m32)(i386_state *cpustate) // Opcode 0xa1
+void i386_device::i386_mov_eax_m32() // Opcode 0xa1
{
UINT32 offset, ea;
- if( cpustate->address_size ) {
- offset = FETCH32(cpustate);
+ if( m_address_size ) {
+ offset = FETCH32();
} else {
- offset = FETCH16(cpustate);
+ offset = FETCH16();
}
- if( cpustate->segment_prefix ) {
- ea = i386_translate(cpustate, cpustate->segment_override, offset, 0 );
+ if( m_segment_prefix ) {
+ ea = i386_translate(m_segment_override, offset, 0 );
} else {
- ea = i386_translate(cpustate, DS, offset, 0 );
+ ea = i386_translate(DS, offset, 0 );
}
- REG32(EAX) = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_MOV_MEM_ACC);
+ REG32(EAX) = READ32(ea);
+ CYCLES(CYCLES_MOV_MEM_ACC);
}
-static void I386OP(mov_m32_eax)(i386_state *cpustate) // Opcode 0xa3
+void i386_device::i386_mov_m32_eax() // Opcode 0xa3
{
UINT32 offset, ea;
- if( cpustate->address_size ) {
- offset = FETCH32(cpustate);
+ if( m_address_size ) {
+ offset = FETCH32();
} else {
- offset = FETCH16(cpustate);
+ offset = FETCH16();
}
- if( cpustate->segment_prefix ) {
- ea = i386_translate(cpustate, cpustate->segment_override, offset, 1 );
+ if( m_segment_prefix ) {
+ ea = i386_translate(m_segment_override, offset, 1 );
} else {
- ea = i386_translate(cpustate, DS, offset, 1 );
+ ea = i386_translate(DS, offset, 1 );
}
- WRITE32(cpustate, ea, REG32(EAX) );
- CYCLES(cpustate,CYCLES_MOV_ACC_MEM);
+ WRITE32(ea, REG32(EAX) );
+ CYCLES(CYCLES_MOV_ACC_MEM);
}
-static void I386OP(mov_eax_i32)(i386_state *cpustate) // Opcode 0xb8
+void i386_device::i386_mov_eax_i32() // Opcode 0xb8
{
- REG32(EAX) = FETCH32(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG32(EAX) = FETCH32();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_ecx_i32)(i386_state *cpustate) // Opcode 0xb9
+void i386_device::i386_mov_ecx_i32() // Opcode 0xb9
{
- REG32(ECX) = FETCH32(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG32(ECX) = FETCH32();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_edx_i32)(i386_state *cpustate) // Opcode 0xba
+void i386_device::i386_mov_edx_i32() // Opcode 0xba
{
- REG32(EDX) = FETCH32(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG32(EDX) = FETCH32();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_ebx_i32)(i386_state *cpustate) // Opcode 0xbb
+void i386_device::i386_mov_ebx_i32() // Opcode 0xbb
{
- REG32(EBX) = FETCH32(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG32(EBX) = FETCH32();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_esp_i32)(i386_state *cpustate) // Opcode 0xbc
+void i386_device::i386_mov_esp_i32() // Opcode 0xbc
{
- REG32(ESP) = FETCH32(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG32(ESP) = FETCH32();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_ebp_i32)(i386_state *cpustate) // Opcode 0xbd
+void i386_device::i386_mov_ebp_i32() // Opcode 0xbd
{
- REG32(EBP) = FETCH32(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG32(EBP) = FETCH32();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_esi_i32)(i386_state *cpustate) // Opcode 0xbe
+void i386_device::i386_mov_esi_i32() // Opcode 0xbe
{
- REG32(ESI) = FETCH32(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG32(ESI) = FETCH32();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_edi_i32)(i386_state *cpustate) // Opcode 0xbf
+void i386_device::i386_mov_edi_i32() // Opcode 0xbf
{
- REG32(EDI) = FETCH32(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG32(EDI) = FETCH32();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(movsd)(i386_state *cpustate) // Opcode 0xa5
+void i386_device::i386_movsd() // Opcode 0xa5
{
UINT32 eas, ead, v;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 1 );
- v = READ32(cpustate,eas);
- WRITE32(cpustate,ead, v);
- BUMP_SI(cpustate,4);
- BUMP_DI(cpustate,4);
- CYCLES(cpustate,CYCLES_MOVS);
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 1 );
+ v = READ32(eas);
+ WRITE32(ead, v);
+ BUMP_SI(4);
+ BUMP_DI(4);
+ CYCLES(CYCLES_MOVS);
}
-static void I386OP(movsx_r32_rm8)(i386_state *cpustate) // Opcode 0x0f be
+void i386_device::i386_movsx_r32_rm8() // Opcode 0x0f be
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
INT32 src = (INT8)LOAD_RM8(modrm);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOVSX_REG_REG);
+ CYCLES(CYCLES_MOVSX_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- INT32 src = (INT8)READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ INT32 src = (INT8)READ8(ea);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOVSX_MEM_REG);
+ CYCLES(CYCLES_MOVSX_MEM_REG);
}
}
-static void I386OP(movsx_r32_rm16)(i386_state *cpustate) // Opcode 0x0f bf
+void i386_device::i386_movsx_r32_rm16() // Opcode 0x0f bf
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
INT32 src = (INT16)LOAD_RM16(modrm);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOVSX_REG_REG);
+ CYCLES(CYCLES_MOVSX_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- INT32 src = (INT16)READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ INT32 src = (INT16)READ16(ea);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOVSX_MEM_REG);
+ CYCLES(CYCLES_MOVSX_MEM_REG);
}
}
-static void I386OP(movzx_r32_rm8)(i386_state *cpustate) // Opcode 0x0f b6
+void i386_device::i386_movzx_r32_rm8() // Opcode 0x0f b6
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 src = (UINT8)LOAD_RM8(modrm);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOVZX_REG_REG);
+ CYCLES(CYCLES_MOVZX_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT32 src = (UINT8)READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ UINT32 src = (UINT8)READ8(ea);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOVZX_MEM_REG);
+ CYCLES(CYCLES_MOVZX_MEM_REG);
}
}
-static void I386OP(movzx_r32_rm16)(i386_state *cpustate) // Opcode 0x0f b7
+void i386_device::i386_movzx_r32_rm16() // Opcode 0x0f b7
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 src = (UINT16)LOAD_RM16(modrm);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOVZX_REG_REG);
+ CYCLES(CYCLES_MOVZX_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT32 src = (UINT16)READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ UINT32 src = (UINT16)READ16(ea);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_MOVZX_MEM_REG);
+ CYCLES(CYCLES_MOVZX_MEM_REG);
}
}
-static void I386OP(or_rm32_r32)(i386_state *cpustate) // Opcode 0x09
+void i386_device::i386_or_rm32_r32() // Opcode 0x09
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
- dst = OR32(cpustate,dst, src);
+ dst = OR32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
- dst = OR32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ32(ea);
+ dst = OR32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(or_r32_rm32)(i386_state *cpustate) // Opcode 0x0b
+void i386_device::i386_or_r32_rm32() // Opcode 0x0b
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
dst = LOAD_REG32(modrm);
- dst = OR32(cpustate,dst, src);
+ dst = OR32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
dst = LOAD_REG32(modrm);
- dst = OR32(cpustate,dst, src);
+ dst = OR32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(or_eax_i32)(i386_state *cpustate) // Opcode 0x0d
+void i386_device::i386_or_eax_i32() // Opcode 0x0d
{
UINT32 src, dst;
- src = FETCH32(cpustate);
+ src = FETCH32();
dst = REG32(EAX);
- dst = OR32(cpustate,dst, src);
+ dst = OR32(dst, src);
REG32(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(out_eax_i8)(i386_state *cpustate) // Opcode 0xe7
+void i386_device::i386_out_eax_i8() // Opcode 0xe7
{
- UINT16 port = FETCH(cpustate);
+ UINT16 port = FETCH();
UINT32 data = REG32(EAX);
- WRITEPORT32(cpustate, port, data);
- CYCLES(cpustate,CYCLES_OUT_VAR);
+ WRITEPORT32(port, data);
+ CYCLES(CYCLES_OUT_VAR);
}
-static void I386OP(out_eax_dx)(i386_state *cpustate) // Opcode 0xef
+void i386_device::i386_out_eax_dx() // Opcode 0xef
{
UINT16 port = REG16(DX);
UINT32 data = REG32(EAX);
- WRITEPORT32(cpustate, port, data);
- CYCLES(cpustate,CYCLES_OUT);
+ WRITEPORT32(port, data);
+ CYCLES(CYCLES_OUT);
}
-static void I386OP(pop_eax)(i386_state *cpustate) // Opcode 0x58
+void i386_device::i386_pop_eax() // Opcode 0x58
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
- REG32(EAX) = POP32(cpustate);
+ if(i386_limit_check(SS,offset+3) == 0)
+ REG32(EAX) = POP32();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_ecx)(i386_state *cpustate) // Opcode 0x59
+void i386_device::i386_pop_ecx() // Opcode 0x59
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
- REG32(ECX) = POP32(cpustate);
+ if(i386_limit_check(SS,offset+3) == 0)
+ REG32(ECX) = POP32();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_edx)(i386_state *cpustate) // Opcode 0x5a
+void i386_device::i386_pop_edx() // Opcode 0x5a
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
- REG32(EDX) = POP32(cpustate);
+ if(i386_limit_check(SS,offset+3) == 0)
+ REG32(EDX) = POP32();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_ebx)(i386_state *cpustate) // Opcode 0x5b
+void i386_device::i386_pop_ebx() // Opcode 0x5b
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
- REG32(EBX) = POP32(cpustate);
+ if(i386_limit_check(SS,offset+3) == 0)
+ REG32(EBX) = POP32();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_esp)(i386_state *cpustate) // Opcode 0x5c
+void i386_device::i386_pop_esp() // Opcode 0x5c
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
- REG32(ESP) = POP32(cpustate);
+ if(i386_limit_check(SS,offset+3) == 0)
+ REG32(ESP) = POP32();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_ebp)(i386_state *cpustate) // Opcode 0x5d
+void i386_device::i386_pop_ebp() // Opcode 0x5d
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
- REG32(EBP) = POP32(cpustate);
+ if(i386_limit_check(SS,offset+3) == 0)
+ REG32(EBP) = POP32();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_esi)(i386_state *cpustate) // Opcode 0x5e
+void i386_device::i386_pop_esi() // Opcode 0x5e
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
- REG32(ESI) = POP32(cpustate);
+ if(i386_limit_check(SS,offset+3) == 0)
+ REG32(ESI) = POP32();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static void I386OP(pop_edi)(i386_state *cpustate) // Opcode 0x5f
+void i386_device::i386_pop_edi() // Opcode 0x5f
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
- REG32(EDI) = POP32(cpustate);
+ if(i386_limit_check(SS,offset+3) == 0)
+ REG32(EDI) = POP32();
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_REG_SHORT);
+ CYCLES(CYCLES_POP_REG_SHORT);
}
-static bool I386OP(pop_seg32)(i386_state *cpustate, int segment)
+bool i386_device::i386_pop_seg32(int segment)
{
UINT32 ea, offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
UINT32 value;
bool fault;
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
+ if(i386_limit_check(SS,offset+3) == 0)
{
- ea = i386_translate(cpustate, SS, offset, 0);
- value = READ32(cpustate, ea);
- i386_sreg_load(cpustate,value, segment, &fault);
+ ea = i386_translate(SS, offset, 0);
+ value = READ32(ea);
+ i386_sreg_load(value, segment, &fault);
if(fault) return false;
if(STACK_32BIT)
REG32(ESP) = offset + 4;
@@ -1468,64 +1468,64 @@ static bool I386OP(pop_seg32)(i386_state *cpustate, int segment)
}
else
{
- cpustate->ext = 1;
- i386_trap_with_error(cpustate,FAULT_SS,0,0,0);
+ m_ext = 1;
+ i386_trap_with_error(FAULT_SS,0,0,0);
return false;
}
- CYCLES(cpustate,CYCLES_POP_SREG);
+ CYCLES(CYCLES_POP_SREG);
return true;
}
-static void I386OP(pop_ds32)(i386_state *cpustate) // Opcode 0x1f
+void i386_device::i386_pop_ds32() // Opcode 0x1f
{
- I386OP(pop_seg32)(cpustate, DS);
+ i386_pop_seg32(DS);
}
-static void I386OP(pop_es32)(i386_state *cpustate) // Opcode 0x07
+void i386_device::i386_pop_es32() // Opcode 0x07
{
- I386OP(pop_seg32)(cpustate, ES);
+ i386_pop_seg32(ES);
}
-static void I386OP(pop_fs32)(i386_state *cpustate) // Opcode 0x0f a1
+void i386_device::i386_pop_fs32() // Opcode 0x0f a1
{
- I386OP(pop_seg32)(cpustate, FS);
+ i386_pop_seg32(FS);
}
-static void I386OP(pop_gs32)(i386_state *cpustate) // Opcode 0x0f a9
+void i386_device::i386_pop_gs32() // Opcode 0x0f a9
{
- I386OP(pop_seg32)(cpustate, GS);
+ i386_pop_seg32(GS);
}
-static void I386OP(pop_ss32)(i386_state *cpustate) // Opcode 0x17
+void i386_device::i386_pop_ss32() // Opcode 0x17
{
- if(!I386OP(pop_seg32)(cpustate, SS)) return;
- if(cpustate->IF != 0) // if external interrupts are enabled
+ if(!i386_pop_seg32(SS)) return;
+ if(m_IF != 0) // if external interrupts are enabled
{
- cpustate->IF = 0; // reset IF for the next instruction
- cpustate->delayed_interrupt_enable = 1;
+ m_IF = 0; // reset IF for the next instruction
+ m_delayed_interrupt_enable = 1;
}
}
-static void I386OP(pop_rm32)(i386_state *cpustate) // Opcode 0x8f
+void i386_device::i386_pop_rm32() // Opcode 0x8f
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT32 value;
UINT32 ea, offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
+ if(i386_limit_check(SS,offset+3) == 0)
{
// be careful here, if the write references the esp register
// it expects the post-pop value but esp must be wound back
// if the write faults
UINT32 temp_sp = REG32(ESP);
- value = POP32(cpustate);
+ value = POP32();
if( modrm >= 0xc0 ) {
STORE_RM32(modrm, value);
} else {
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
try
{
- WRITE32(cpustate,ea, value);
+ WRITE32(ea, value);
}
catch(UINT64 e)
{
@@ -1536,363 +1536,363 @@ static void I386OP(pop_rm32)(i386_state *cpustate) // Opcode 0x8f
}
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POP_RM);
+ CYCLES(CYCLES_POP_RM);
}
-static void I386OP(popad)(i386_state *cpustate) // Opcode 0x61
+void i386_device::i386_popad() // Opcode 0x61
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset+31) == 0)
+ if(i386_limit_check(SS,offset+31) == 0)
{
- REG32(EDI) = POP32(cpustate);
- REG32(ESI) = POP32(cpustate);
- REG32(EBP) = POP32(cpustate);
+ REG32(EDI) = POP32();
+ REG32(ESI) = POP32();
+ REG32(EBP) = POP32();
REG32(ESP) += 4;
- REG32(EBX) = POP32(cpustate);
- REG32(EDX) = POP32(cpustate);
- REG32(ECX) = POP32(cpustate);
- REG32(EAX) = POP32(cpustate);
+ REG32(EBX) = POP32();
+ REG32(EDX) = POP32();
+ REG32(ECX) = POP32();
+ REG32(EAX) = POP32();
}
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POPA);
+ CYCLES(CYCLES_POPA);
}
-static void I386OP(popfd)(i386_state *cpustate) // Opcode 0x9d
+void i386_device::i386_popfd() // Opcode 0x9d
{
UINT32 value;
- UINT32 current = get_flags(cpustate);
+ UINT32 current = get_flags();
UINT8 IOPL = (current >> 12) & 0x03;
UINT32 mask = 0x00257fd5; // VM, VIP and VIF cannot be set by POPF/POPFD
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
// IOPL can only change if CPL is 0
- if(cpustate->CPL != 0)
+ if(m_CPL != 0)
mask &= ~0x00003000;
// IF can only change if CPL is at least as privileged as IOPL
- if(cpustate->CPL > IOPL)
+ if(m_CPL > IOPL)
mask &= ~0x00000200;
if(V8086_MODE)
{
if(IOPL < 3)
{
- logerror("POPFD(%08x): IOPL < 3 while in V86 mode.\n",cpustate->pc);
+ logerror("POPFD(%08x): IOPL < 3 while in V86 mode.\n",m_pc);
FAULT(FAULT_GP,0) // #GP(0)
}
mask &= ~0x00003000; // IOPL cannot be changed while in V8086 mode
}
- if(i386_limit_check(cpustate,SS,offset+3) == 0)
+ if(i386_limit_check(SS,offset+3) == 0)
{
- value = POP32(cpustate);
+ value = POP32();
value &= ~0x00010000; // RF will always return zero
- set_flags(cpustate,(current & ~mask) | (value & mask)); // mask out reserved bits
+ set_flags((current & ~mask) | (value & mask)); // mask out reserved bits
}
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_POPF);
+ CYCLES(CYCLES_POPF);
}
-static void I386OP(push_eax)(i386_state *cpustate) // Opcode 0x50
+void i386_device::i386_push_eax() // Opcode 0x50
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, REG32(EAX) );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(REG32(EAX) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_ecx)(i386_state *cpustate) // Opcode 0x51
+void i386_device::i386_push_ecx() // Opcode 0x51
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, REG32(ECX) );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(REG32(ECX) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_edx)(i386_state *cpustate) // Opcode 0x52
+void i386_device::i386_push_edx() // Opcode 0x52
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, REG32(EDX) );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(REG32(EDX) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_ebx)(i386_state *cpustate) // Opcode 0x53
+void i386_device::i386_push_ebx() // Opcode 0x53
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, REG32(EBX) );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(REG32(EBX) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_esp)(i386_state *cpustate) // Opcode 0x54
+void i386_device::i386_push_esp() // Opcode 0x54
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, REG32(ESP) );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(REG32(ESP) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_ebp)(i386_state *cpustate) // Opcode 0x55
+void i386_device::i386_push_ebp() // Opcode 0x55
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, REG32(EBP) );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(REG32(EBP) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_esi)(i386_state *cpustate) // Opcode 0x56
+void i386_device::i386_push_esi() // Opcode 0x56
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, REG32(ESI) );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(REG32(ESI) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_edi)(i386_state *cpustate) // Opcode 0x57
+void i386_device::i386_push_edi() // Opcode 0x57
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, REG32(EDI) );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(REG32(EDI) );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_REG_SHORT);
+ CYCLES(CYCLES_PUSH_REG_SHORT);
}
-static void I386OP(push_cs32)(i386_state *cpustate) // Opcode 0x0e
+void i386_device::i386_push_cs32() // Opcode 0x0e
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, cpustate->sreg[CS].selector );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(m_sreg[CS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_ds32)(i386_state *cpustate) // Opcode 0x1e
+void i386_device::i386_push_ds32() // Opcode 0x1e
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, cpustate->sreg[DS].selector );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(m_sreg[DS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_es32)(i386_state *cpustate) // Opcode 0x06
+void i386_device::i386_push_es32() // Opcode 0x06
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, cpustate->sreg[ES].selector );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(m_sreg[ES].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_fs32)(i386_state *cpustate) // Opcode 0x0f a0
+void i386_device::i386_push_fs32() // Opcode 0x0f a0
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, cpustate->sreg[FS].selector );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(m_sreg[FS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_gs32)(i386_state *cpustate) // Opcode 0x0f a8
+void i386_device::i386_push_gs32() // Opcode 0x0f a8
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, cpustate->sreg[GS].selector );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(m_sreg[GS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_ss32)(i386_state *cpustate) // Opcode 0x16
+void i386_device::i386_push_ss32() // Opcode 0x16
{
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, cpustate->sreg[SS].selector );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(m_sreg[SS].selector );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_SREG);
+ CYCLES(CYCLES_PUSH_SREG);
}
-static void I386OP(push_i32)(i386_state *cpustate) // Opcode 0x68
+void i386_device::i386_push_i32() // Opcode 0x68
{
- UINT32 value = FETCH32(cpustate);
+ UINT32 value = FETCH32();
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate,value);
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(value);
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSH_IMM);
+ CYCLES(CYCLES_PUSH_IMM);
}
-static void I386OP(pushad)(i386_state *cpustate) // Opcode 0x60
+void i386_device::i386_pushad() // Opcode 0x60
{
UINT32 temp = REG32(ESP);
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-32) == 0)
+ if(i386_limit_check(SS,offset-32) == 0)
{
- PUSH32(cpustate, REG32(EAX) );
- PUSH32(cpustate, REG32(ECX) );
- PUSH32(cpustate, REG32(EDX) );
- PUSH32(cpustate, REG32(EBX) );
- PUSH32(cpustate, temp );
- PUSH32(cpustate, REG32(EBP) );
- PUSH32(cpustate, REG32(ESI) );
- PUSH32(cpustate, REG32(EDI) );
+ PUSH32(REG32(EAX) );
+ PUSH32(REG32(ECX) );
+ PUSH32(REG32(EDX) );
+ PUSH32(REG32(EBX) );
+ PUSH32(temp );
+ PUSH32(REG32(EBP) );
+ PUSH32(REG32(ESI) );
+ PUSH32(REG32(EDI) );
}
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSHA);
+ CYCLES(CYCLES_PUSHA);
}
-static void I386OP(pushfd)(i386_state *cpustate) // Opcode 0x9c
+void i386_device::i386_pushfd() // Opcode 0x9c
{
- if(!cpustate->IOP1 && !cpustate->IOP2 && V8086_MODE)
+ if(!m_IOP1 && !m_IOP2 && V8086_MODE)
FAULT(FAULT_GP,0)
UINT32 offset = (STACK_32BIT ? REG32(ESP) : REG16(SP));
- if(i386_limit_check(cpustate,SS,offset-4) == 0)
- PUSH32(cpustate, get_flags(cpustate) & 0x00fcffff );
+ if(i386_limit_check(SS,offset-4) == 0)
+ PUSH32(get_flags() & 0x00fcffff );
else
FAULT(FAULT_SS,0)
- CYCLES(cpustate,CYCLES_PUSHF);
+ CYCLES(CYCLES_PUSHF);
}
-static void I386OP(ret_near32_i16)(i386_state *cpustate) // Opcode 0xc2
+void i386_device::i386_ret_near32_i16() // Opcode 0xc2
{
- INT16 disp = FETCH16(cpustate);
- cpustate->eip = POP32(cpustate);
+ INT16 disp = FETCH16();
+ m_eip = POP32();
REG32(ESP) += disp;
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_RET_IMM); /* TODO: Timing = 10 + m */
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_RET_IMM); /* TODO: Timing = 10 + m */
}
-static void I386OP(ret_near32)(i386_state *cpustate) // Opcode 0xc3
+void i386_device::i386_ret_near32() // Opcode 0xc3
{
- cpustate->eip = POP32(cpustate);
- CHANGE_PC(cpustate,cpustate->eip);
- CYCLES(cpustate,CYCLES_RET); /* TODO: Timing = 10 + m */
+ m_eip = POP32();
+ CHANGE_PC(m_eip);
+ CYCLES(CYCLES_RET); /* TODO: Timing = 10 + m */
}
-static void I386OP(sbb_rm32_r32)(i386_state *cpustate) // Opcode 0x19
+void i386_device::i386_sbb_rm32_r32() // Opcode 0x19
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
- dst = SBB32(cpustate, dst, src, cpustate->CF);
+ dst = SBB32(dst, src, m_CF);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
- dst = SBB32(cpustate, dst, src, cpustate->CF);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ32(ea);
+ dst = SBB32(dst, src, m_CF);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(sbb_r32_rm32)(i386_state *cpustate) // Opcode 0x1b
+void i386_device::i386_sbb_r32_rm32() // Opcode 0x1b
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
dst = LOAD_REG32(modrm);
- dst = SBB32(cpustate, dst, src, cpustate->CF);
+ dst = SBB32(dst, src, m_CF);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
dst = LOAD_REG32(modrm);
- dst = SBB32(cpustate, dst, src, cpustate->CF);
+ dst = SBB32(dst, src, m_CF);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(sbb_eax_i32)(i386_state *cpustate) // Opcode 0x1d
+void i386_device::i386_sbb_eax_i32() // Opcode 0x1d
{
UINT32 src, dst;
- src = FETCH32(cpustate);
+ src = FETCH32();
dst = REG32(EAX);
- dst = SBB32(cpustate, dst, src, cpustate->CF);
+ dst = SBB32(dst, src, m_CF);
REG32(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(scasd)(i386_state *cpustate) // Opcode 0xaf
+void i386_device::i386_scasd() // Opcode 0xaf
{
UINT32 eas, src, dst;
- eas = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 0 );
- src = READ32(cpustate,eas);
+ eas = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 0 );
+ src = READ32(eas);
dst = REG32(EAX);
- SUB32(cpustate,dst, src);
- BUMP_DI(cpustate,4);
- CYCLES(cpustate,CYCLES_SCAS);
+ SUB32(dst, src);
+ BUMP_DI(4);
+ CYCLES(CYCLES_SCAS);
}
-static void I386OP(shld32_i8)(i386_state *cpustate) // Opcode 0x0f a4
+void i386_device::i386_shld32_i8() // Opcode 0x0f a4
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 upper = LOAD_REG32(modrm);
- UINT8 shift = FETCH(cpustate);
+ UINT8 shift = FETCH();
shift &= 31;
if( shift == 0 ) {
} else {
- cpustate->CF = (dst & (1 << (32-shift))) ? 1 : 0;
+ m_CF = (dst & (1 << (32-shift))) ? 1 : 0;
dst = (dst << shift) | (upper >> (32-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 31);
+ m_OF = m_CF ^ (dst >> 31);
SetSZPF32(dst);
}
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_SHLD_REG);
+ CYCLES(CYCLES_SHLD_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
UINT32 upper = LOAD_REG32(modrm);
- UINT8 shift = FETCH(cpustate);
+ UINT8 shift = FETCH();
shift &= 31;
if( shift == 0 ) {
} else {
- cpustate->CF = (dst & (1 << (32-shift))) ? 1 : 0;
+ m_CF = (dst & (1 << (32-shift))) ? 1 : 0;
dst = (dst << shift) | (upper >> (32-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 31);
+ m_OF = m_CF ^ (dst >> 31);
SetSZPF32(dst);
}
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_SHLD_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_SHLD_MEM);
}
}
-static void I386OP(shld32_cl)(i386_state *cpustate) // Opcode 0x0f a5
+void i386_device::i386_shld32_cl() // Opcode 0x0f a5
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 upper = LOAD_REG32(modrm);
@@ -1900,69 +1900,69 @@ static void I386OP(shld32_cl)(i386_state *cpustate) // Opcode 0x0f a5
shift &= 31;
if( shift == 0 ) {
} else {
- cpustate->CF = (dst & (1 << (32-shift))) ? 1 : 0;
+ m_CF = (dst & (1 << (32-shift))) ? 1 : 0;
dst = (dst << shift) | (upper >> (32-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 31);
+ m_OF = m_CF ^ (dst >> 31);
SetSZPF32(dst);
}
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_SHLD_REG);
+ CYCLES(CYCLES_SHLD_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
UINT32 upper = LOAD_REG32(modrm);
UINT8 shift = REG8(CL);
shift &= 31;
if( shift == 0 ) {
} else {
- cpustate->CF = (dst & (1 << (32-shift))) ? 1 : 0;
+ m_CF = (dst & (1 << (32-shift))) ? 1 : 0;
dst = (dst << shift) | (upper >> (32-shift));
- cpustate->OF = cpustate->CF ^ (dst >> 31);
+ m_OF = m_CF ^ (dst >> 31);
SetSZPF32(dst);
}
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_SHLD_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_SHLD_MEM);
}
}
-static void I386OP(shrd32_i8)(i386_state *cpustate) // Opcode 0x0f ac
+void i386_device::i386_shrd32_i8() // Opcode 0x0f ac
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 upper = LOAD_REG32(modrm);
- UINT8 shift = FETCH(cpustate);
+ UINT8 shift = FETCH();
shift &= 31;
if( shift == 0 ) {
} else {
- cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (dst & (1 << (shift-1))) ? 1 : 0;
dst = (dst >> shift) | (upper << (32-shift));
- cpustate->OF = ((dst >> 31) ^ (dst >> 30)) & 1;
+ m_OF = ((dst >> 31) ^ (dst >> 30)) & 1;
SetSZPF32(dst);
}
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_SHRD_REG);
+ CYCLES(CYCLES_SHRD_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
UINT32 upper = LOAD_REG32(modrm);
- UINT8 shift = FETCH(cpustate);
+ UINT8 shift = FETCH();
shift &= 31;
if( shift == 0 ) {
} else {
- cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (dst & (1 << (shift-1))) ? 1 : 0;
dst = (dst >> shift) | (upper << (32-shift));
- cpustate->OF = ((dst >> 31) ^ (dst >> 30)) & 1;
+ m_OF = ((dst >> 31) ^ (dst >> 30)) & 1;
SetSZPF32(dst);
}
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_SHRD_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_SHRD_MEM);
}
}
-static void I386OP(shrd32_cl)(i386_state *cpustate) // Opcode 0x0f ad
+void i386_device::i386_shrd32_cl() // Opcode 0x0f ad
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 upper = LOAD_REG32(modrm);
@@ -1970,608 +1970,608 @@ static void I386OP(shrd32_cl)(i386_state *cpustate) // Opcode 0x0f ad
shift &= 31;
if( shift == 0 ) {
} else {
- cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (dst & (1 << (shift-1))) ? 1 : 0;
dst = (dst >> shift) | (upper << (32-shift));
- cpustate->OF = ((dst >> 31) ^ (dst >> 30)) & 1;
+ m_OF = ((dst >> 31) ^ (dst >> 30)) & 1;
SetSZPF32(dst);
}
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_SHRD_REG);
+ CYCLES(CYCLES_SHRD_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
UINT32 upper = LOAD_REG32(modrm);
UINT8 shift = REG8(CL);
shift &= 31;
if( shift == 0 ) {
} else {
- cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (dst & (1 << (shift-1))) ? 1 : 0;
dst = (dst >> shift) | (upper << (32-shift));
- cpustate->OF = ((dst >> 31) ^ (dst >> 30)) & 1;
+ m_OF = ((dst >> 31) ^ (dst >> 30)) & 1;
SetSZPF32(dst);
}
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_SHRD_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_SHRD_MEM);
}
}
-static void I386OP(stosd)(i386_state *cpustate) // Opcode 0xab
+void i386_device::i386_stosd() // Opcode 0xab
{
- UINT32 eas = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 1 );
- WRITE32(cpustate,eas, REG32(EAX));
- BUMP_DI(cpustate,4);
- CYCLES(cpustate,CYCLES_STOS);
+ UINT32 eas = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 1 );
+ WRITE32(eas, REG32(EAX));
+ BUMP_DI(4);
+ CYCLES(CYCLES_STOS);
}
-static void I386OP(sub_rm32_r32)(i386_state *cpustate) // Opcode 0x29
+void i386_device::i386_sub_rm32_r32() // Opcode 0x29
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
- dst = SUB32(cpustate,dst, src);
+ dst = SUB32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
- dst = SUB32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ32(ea);
+ dst = SUB32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(sub_r32_rm32)(i386_state *cpustate) // Opcode 0x2b
+void i386_device::i386_sub_r32_rm32() // Opcode 0x2b
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
dst = LOAD_REG32(modrm);
- dst = SUB32(cpustate,dst, src);
+ dst = SUB32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ src = READ32(ea);
dst = LOAD_REG32(modrm);
- dst = SUB32(cpustate,dst, src);
+ dst = SUB32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(sub_eax_i32)(i386_state *cpustate) // Opcode 0x2d
+void i386_device::i386_sub_eax_i32() // Opcode 0x2d
{
UINT32 src, dst;
- src = FETCH32(cpustate);
+ src = FETCH32();
dst = REG32(EAX);
- dst = SUB32(cpustate,dst, src);
+ dst = SUB32(dst, src);
REG32(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(test_eax_i32)(i386_state *cpustate) // Opcode 0xa9
+void i386_device::i386_test_eax_i32() // Opcode 0xa9
{
- UINT32 src = FETCH32(cpustate);
+ UINT32 src = FETCH32();
UINT32 dst = REG32(EAX);
dst = src & dst;
SetSZPF32(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_TEST_IMM_ACC);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_TEST_IMM_ACC);
}
-static void I386OP(test_rm32_r32)(i386_state *cpustate) // Opcode 0x85
+void i386_device::i386_test_rm32_r32() // Opcode 0x85
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
dst = src & dst;
SetSZPF32(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_TEST_REG_REG);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_TEST_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
+ UINT32 ea = GetEA(modrm,0);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
+ dst = READ32(ea);
dst = src & dst;
SetSZPF32(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_TEST_REG_MEM);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_TEST_REG_MEM);
}
}
-static void I386OP(xchg_eax_ecx)(i386_state *cpustate) // Opcode 0x91
+void i386_device::i386_xchg_eax_ecx() // Opcode 0x91
{
UINT32 temp;
temp = REG32(EAX);
REG32(EAX) = REG32(ECX);
REG32(ECX) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_eax_edx)(i386_state *cpustate) // Opcode 0x92
+void i386_device::i386_xchg_eax_edx() // Opcode 0x92
{
UINT32 temp;
temp = REG32(EAX);
REG32(EAX) = REG32(EDX);
REG32(EDX) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_eax_ebx)(i386_state *cpustate) // Opcode 0x93
+void i386_device::i386_xchg_eax_ebx() // Opcode 0x93
{
UINT32 temp;
temp = REG32(EAX);
REG32(EAX) = REG32(EBX);
REG32(EBX) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_eax_esp)(i386_state *cpustate) // Opcode 0x94
+void i386_device::i386_xchg_eax_esp() // Opcode 0x94
{
UINT32 temp;
temp = REG32(EAX);
REG32(EAX) = REG32(ESP);
REG32(ESP) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_eax_ebp)(i386_state *cpustate) // Opcode 0x95
+void i386_device::i386_xchg_eax_ebp() // Opcode 0x95
{
UINT32 temp;
temp = REG32(EAX);
REG32(EAX) = REG32(EBP);
REG32(EBP) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_eax_esi)(i386_state *cpustate) // Opcode 0x96
+void i386_device::i386_xchg_eax_esi() // Opcode 0x96
{
UINT32 temp;
temp = REG32(EAX);
REG32(EAX) = REG32(ESI);
REG32(ESI) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_eax_edi)(i386_state *cpustate) // Opcode 0x97
+void i386_device::i386_xchg_eax_edi() // Opcode 0x97
{
UINT32 temp;
temp = REG32(EAX);
REG32(EAX) = REG32(EDI);
REG32(EDI) = temp;
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
}
-static void I386OP(xchg_r32_rm32)(i386_state *cpustate) // Opcode 0x87
+void i386_device::i386_xchg_r32_rm32() // Opcode 0x87
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 src = LOAD_RM32(modrm);
UINT32 dst = LOAD_REG32(modrm);
STORE_REG32(modrm, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 src = READ32(ea);
UINT32 dst = LOAD_REG32(modrm);
- WRITE32(cpustate,ea, dst);
+ WRITE32(ea, dst);
STORE_REG32(modrm, src);
- CYCLES(cpustate,CYCLES_XCHG_REG_MEM);
+ CYCLES(CYCLES_XCHG_REG_MEM);
}
}
-static void I386OP(xor_rm32_r32)(i386_state *cpustate) // Opcode 0x31
+void i386_device::i386_xor_rm32_r32() // Opcode 0x31
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG32(modrm);
dst = LOAD_RM32(modrm);
- dst = XOR32(cpustate,dst, src);
+ dst = XOR32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG32(modrm);
- dst = READ32(cpustate,ea);
- dst = XOR32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ32(ea);
+ dst = XOR32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(xor_r32_rm32)(i386_state *cpustate) // Opcode 0x33
+void i386_device::i386_xor_r32_rm32() // Opcode 0x33
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
dst = LOAD_REG32(modrm);
- dst = XOR32(cpustate,dst, src);
+ dst = XOR32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
dst = LOAD_REG32(modrm);
- dst = XOR32(cpustate,dst, src);
+ dst = XOR32(dst, src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(xor_eax_i32)(i386_state *cpustate) // Opcode 0x35
+void i386_device::i386_xor_eax_i32() // Opcode 0x35
{
UINT32 src, dst;
- src = FETCH32(cpustate);
+ src = FETCH32();
dst = REG32(EAX);
- dst = XOR32(cpustate,dst, src);
+ dst = XOR32(dst, src);
REG32(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(group81_32)(i386_state *cpustate) // Opcode 0x81
+void i386_device::i386_group81_32() // Opcode 0x81
{
UINT32 ea;
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: // ADD Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = FETCH32(cpustate);
- dst = ADD32(cpustate,dst, src);
+ src = FETCH32();
+ dst = ADD32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = FETCH32(cpustate);
- dst = ADD32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = FETCH32();
+ dst = ADD32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 1: // OR Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = FETCH32(cpustate);
- dst = OR32(cpustate,dst, src);
+ src = FETCH32();
+ dst = OR32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = FETCH32(cpustate);
- dst = OR32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = FETCH32();
+ dst = OR32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 2: // ADC Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = FETCH32(cpustate);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
+ src = FETCH32();
+ dst = ADC32(dst, src, m_CF);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = FETCH32(cpustate);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = FETCH32();
+ dst = ADC32(dst, src, m_CF);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 3: // SBB Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = FETCH32(cpustate);
- dst = SBB32(cpustate, dst, src, cpustate->CF);
+ src = FETCH32();
+ dst = SBB32(dst, src, m_CF);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = FETCH32(cpustate);
- dst = SBB32(cpustate, dst, src, cpustate->CF);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = FETCH32();
+ dst = SBB32(dst, src, m_CF);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 4: // AND Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = FETCH32(cpustate);
- dst = AND32(cpustate,dst, src);
+ src = FETCH32();
+ dst = AND32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = FETCH32(cpustate);
- dst = AND32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = FETCH32();
+ dst = AND32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 5: // SUB Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = FETCH32(cpustate);
- dst = SUB32(cpustate,dst, src);
+ src = FETCH32();
+ dst = SUB32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = FETCH32(cpustate);
- dst = SUB32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = FETCH32();
+ dst = SUB32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 6: // XOR Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = FETCH32(cpustate);
- dst = XOR32(cpustate,dst, src);
+ src = FETCH32();
+ dst = XOR32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = FETCH32(cpustate);
- dst = XOR32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = FETCH32();
+ dst = XOR32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 7: // CMP Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = FETCH32(cpustate);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ src = FETCH32();
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- dst = READ32(cpustate,ea);
- src = FETCH32(cpustate);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_MEM);
+ ea = GetEA(modrm,0);
+ dst = READ32(ea);
+ src = FETCH32();
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_REG_MEM);
}
break;
}
}
-static void I386OP(group83_32)(i386_state *cpustate) // Opcode 0x83
+void i386_device::i386_group83_32() // Opcode 0x83
{
UINT32 ea;
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: // ADD Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = ADD32(cpustate,dst, src);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = ADD32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = ADD32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = ADD32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 1: // OR Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = OR32(cpustate,dst, src);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = OR32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = OR32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = OR32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 2: // ADC Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = ADC32(dst, src, m_CF);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = ADC32(cpustate, dst, src, cpustate->CF);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = ADC32(dst, src, m_CF);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 3: // SBB Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = ((UINT32)(INT32)(INT8)FETCH(cpustate));
- dst = SBB32(cpustate, dst, src, cpustate->CF);
+ src = ((UINT32)(INT32)(INT8)FETCH());
+ dst = SBB32(dst, src, m_CF);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = ((UINT32)(INT32)(INT8)FETCH(cpustate));
- dst = SBB32(cpustate, dst, src, cpustate->CF);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = ((UINT32)(INT32)(INT8)FETCH());
+ dst = SBB32(dst, src, m_CF);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 4: // AND Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = AND32(cpustate,dst, src);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = AND32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = AND32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = AND32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 5: // SUB Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = SUB32(cpustate,dst, src);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = SUB32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = SUB32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = SUB32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 6: // XOR Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = XOR32(cpustate,dst, src);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = XOR32(dst, src);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- dst = XOR32(cpustate,dst, src);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ dst = XOR32(dst, src);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 7: // CMP Rm32, i32
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- dst = READ32(cpustate,ea);
- src = (UINT32)(INT32)(INT8)FETCH(cpustate);
- SUB32(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_MEM);
+ ea = GetEA(modrm,0);
+ dst = READ32(ea);
+ src = (UINT32)(INT32)(INT8)FETCH();
+ SUB32(dst, src);
+ CYCLES(CYCLES_CMP_REG_MEM);
}
break;
}
}
-static void I386OP(groupC1_32)(i386_state *cpustate) // Opcode 0xc1
+void i386_device::i386_groupC1_32() // Opcode 0xc1
{
UINT32 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 shift;
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- shift = FETCH(cpustate) & 0x1f;
- dst = i386_shift_rotate32(cpustate, modrm, dst, shift);
+ shift = FETCH() & 0x1f;
+ dst = i386_shift_rotate32(modrm, dst, shift);
STORE_RM32(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- shift = FETCH(cpustate) & 0x1f;
- dst = i386_shift_rotate32(cpustate, modrm, dst, shift);
- WRITE32(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ shift = FETCH() & 0x1f;
+ dst = i386_shift_rotate32(modrm, dst, shift);
+ WRITE32(ea, dst);
}
}
-static void I386OP(groupD1_32)(i386_state *cpustate) // Opcode 0xd1
+void i386_device::i386_groupD1_32() // Opcode 0xd1
{
UINT32 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- dst = i386_shift_rotate32(cpustate, modrm, dst, 1);
+ dst = i386_shift_rotate32(modrm, dst, 1);
STORE_RM32(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- dst = i386_shift_rotate32(cpustate, modrm, dst, 1);
- WRITE32(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ dst = i386_shift_rotate32(modrm, dst, 1);
+ WRITE32(ea, dst);
}
}
-static void I386OP(groupD3_32)(i386_state *cpustate) // Opcode 0xd3
+void i386_device::i386_groupD3_32() // Opcode 0xd3
{
UINT32 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
dst = LOAD_RM32(modrm);
- dst = i386_shift_rotate32(cpustate, modrm, dst, REG8(CL));
+ dst = i386_shift_rotate32(modrm, dst, REG8(CL));
STORE_RM32(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ32(cpustate,ea);
- dst = i386_shift_rotate32(cpustate, modrm, dst, REG8(CL));
- WRITE32(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ32(ea);
+ dst = i386_shift_rotate32(modrm, dst, REG8(CL));
+ WRITE32(ea, dst);
}
}
-static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
+void i386_device::i386_groupF7_32() // Opcode 0xf7
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: /* TEST Rm32, i32 */
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
- UINT32 src = FETCH32(cpustate);
+ UINT32 src = FETCH32();
dst &= src;
- cpustate->CF = cpustate->OF = cpustate->AF = 0;
+ m_CF = m_OF = m_AF = 0;
SetSZPF32(dst);
- CYCLES(cpustate,CYCLES_TEST_IMM_REG);
+ CYCLES(CYCLES_TEST_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT32 dst = READ32(cpustate,ea);
- UINT32 src = FETCH32(cpustate);
+ UINT32 ea = GetEA(modrm,0);
+ UINT32 dst = READ32(ea);
+ UINT32 src = FETCH32();
dst &= src;
- cpustate->CF = cpustate->OF = cpustate->AF = 0;
+ m_CF = m_OF = m_AF = 0;
SetSZPF32(dst);
- CYCLES(cpustate,CYCLES_TEST_IMM_MEM);
+ CYCLES(CYCLES_TEST_IMM_MEM);
}
break;
case 2: /* NOT Rm32 */
@@ -2579,27 +2579,27 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
UINT32 dst = LOAD_RM32(modrm);
dst = ~dst;
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_NOT_REG);
+ CYCLES(CYCLES_NOT_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
dst = ~dst;
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_NOT_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_NOT_MEM);
}
break;
case 3: /* NEG Rm32 */
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
- dst = SUB32(cpustate, 0, dst );
+ dst = SUB32(0, dst );
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_NEG_REG);
+ CYCLES(CYCLES_NEG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
- dst = SUB32(cpustate, 0, dst );
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_NEG_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
+ dst = SUB32(0, dst );
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_NEG_MEM);
}
break;
case 4: /* MUL EAX, Rm32 */
@@ -2608,11 +2608,11 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
UINT32 src, dst;
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_MUL32_ACC_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_MUL32_ACC_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_MUL32_ACC_MEM); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
+ CYCLES(CYCLES_MUL32_ACC_MEM); /* TODO: Correct multiply timing */
}
dst = REG32(EAX);
@@ -2620,7 +2620,7 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
REG32(EDX) = (UINT32)(result >> 32);
REG32(EAX) = (UINT32)result;
- cpustate->CF = cpustate->OF = (REG32(EDX) != 0);
+ m_CF = m_OF = (REG32(EDX) != 0);
}
break;
case 5: /* IMUL EAX, Rm32 */
@@ -2629,11 +2629,11 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
INT64 src, dst;
if( modrm >= 0xc0 ) {
src = (INT64)(INT32)LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_IMUL32_ACC_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL32_ACC_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = (INT64)(INT32)READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL32_ACC_MEM); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ src = (INT64)(INT32)READ32(ea);
+ CYCLES(CYCLES_IMUL32_ACC_MEM); /* TODO: Correct multiply timing */
}
dst = (INT64)(INT32)REG32(EAX);
@@ -2642,7 +2642,7 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
REG32(EDX) = (UINT32)(result >> 32);
REG32(EAX) = (UINT32)result;
- cpustate->CF = cpustate->OF = !(result == (INT64)(INT32)result);
+ m_CF = m_OF = !(result == (INT64)(INT32)result);
}
break;
case 6: /* DIV EAX, Rm32 */
@@ -2651,11 +2651,11 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
UINT32 src;
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_DIV32_ACC_REG);
+ CYCLES(CYCLES_DIV32_ACC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_DIV32_ACC_MEM);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
+ CYCLES(CYCLES_DIV32_ACC_MEM);
}
quotient = ((UINT64)(REG32(EDX)) << 32) | (UINT64)(REG32(EAX));
@@ -2669,7 +2669,7 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
REG32(EAX) = (UINT32)result;
}
} else {
- i386_trap(cpustate, 0, 0, 0);
+ i386_trap(0, 0, 0);
}
}
break;
@@ -2679,11 +2679,11 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
UINT32 src;
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_IDIV32_ACC_REG);
+ CYCLES(CYCLES_IDIV32_ACC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_IDIV32_ACC_MEM);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
+ CYCLES(CYCLES_IDIV32_ACC_MEM);
}
quotient = (((INT64)REG32(EDX)) << 32) | ((UINT64)REG32(EAX));
@@ -2697,45 +2697,45 @@ static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7
REG32(EAX) = (UINT32)result;
}
} else {
- i386_trap(cpustate, 0, 0, 0);
+ i386_trap(0, 0, 0);
}
}
break;
}
}
-static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff
+void i386_device::i386_groupFF_32() // Opcode 0xff
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: /* INC Rm32 */
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
- dst = INC32(cpustate,dst);
+ dst = INC32(dst);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_INC_REG);
+ CYCLES(CYCLES_INC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
- dst = INC32(cpustate,dst);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_INC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
+ dst = INC32(dst);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_INC_MEM);
}
break;
case 1: /* DEC Rm32 */
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
- dst = DEC32(cpustate,dst);
+ dst = DEC32(dst);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_DEC_REG);
+ CYCLES(CYCLES_DEC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
- dst = DEC32(cpustate,dst);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_DEC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
+ dst = DEC32(dst);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_DEC_MEM);
}
break;
case 2: /* CALL Rm32 */
@@ -2743,15 +2743,15 @@ static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff
UINT32 address;
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_CALL_REG); /* TODO: Timing = 7 + m */
+ CYCLES(CYCLES_CALL_REG); /* TODO: Timing = 7 + m */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- address = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */
+ UINT32 ea = GetEA(modrm,0);
+ address = READ32(ea);
+ CYCLES(CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */
}
- PUSH32(cpustate, cpustate->eip );
- cpustate->eip = address;
- CHANGE_PC(cpustate,cpustate->eip);
+ PUSH32(m_eip );
+ m_eip = address;
+ CHANGE_PC(m_eip);
}
break;
case 3: /* CALL FAR Rm32 */
@@ -2761,27 +2761,27 @@ static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff
if( modrm >= 0xc0 )
{
- report_invalid_modrm(cpustate, "groupFF_32", modrm);
+ report_invalid_modrm("groupFF_32", modrm);
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- address = READ32(cpustate,ea + 0);
- selector = READ16(cpustate,ea + 4);
- CYCLES(cpustate,CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */
+ UINT32 ea = GetEA(modrm,0);
+ address = READ32(ea + 0);
+ selector = READ16(ea + 4);
+ CYCLES(CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_call(cpustate,selector,address,1,1);
+ i386_protected_mode_call(selector,address,1,1);
}
else
{
- PUSH32(cpustate, cpustate->sreg[CS].selector );
- PUSH32(cpustate, cpustate->eip );
- cpustate->sreg[CS].selector = selector;
- cpustate->performed_intersegment_jump = 1;
- i386_load_segment_descriptor(cpustate, CS );
- cpustate->eip = address;
- CHANGE_PC(cpustate,cpustate->eip);
+ PUSH32(m_sreg[CS].selector );
+ PUSH32(m_eip );
+ m_sreg[CS].selector = selector;
+ m_performed_intersegment_jump = 1;
+ i386_load_segment_descriptor(CS );
+ m_eip = address;
+ CHANGE_PC(m_eip);
}
}
}
@@ -2791,14 +2791,14 @@ static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff
UINT32 address;
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_JMP_REG); /* TODO: Timing = 7 + m */
+ CYCLES(CYCLES_JMP_REG); /* TODO: Timing = 7 + m */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- address = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_JMP_MEM); /* TODO: Timing = 10 + m */
+ UINT32 ea = GetEA(modrm,0);
+ address = READ32(ea);
+ CYCLES(CYCLES_JMP_MEM); /* TODO: Timing = 10 + m */
}
- cpustate->eip = address;
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = address;
+ CHANGE_PC(m_eip);
}
break;
case 5: /* JMP FAR Rm32 */
@@ -2808,25 +2808,25 @@ static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff
if( modrm >= 0xc0 )
{
- report_invalid_modrm(cpustate, "groupFF_32", modrm);
+ report_invalid_modrm("groupFF_32", modrm);
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- address = READ32(cpustate,ea + 0);
- selector = READ16(cpustate,ea + 4);
- CYCLES(cpustate,CYCLES_JMP_MEM_INTERSEG); /* TODO: Timing = 10 + m */
+ UINT32 ea = GetEA(modrm,0);
+ address = READ32(ea + 0);
+ selector = READ16(ea + 4);
+ CYCLES(CYCLES_JMP_MEM_INTERSEG); /* TODO: Timing = 10 + m */
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_jump(cpustate,selector,address,1,1);
+ i386_protected_mode_jump(selector,address,1,1);
}
else
{
- cpustate->sreg[CS].selector = selector;
- cpustate->performed_intersegment_jump = 1;
- i386_load_segment_descriptor(cpustate, CS );
- cpustate->eip = address;
- CHANGE_PC(cpustate,cpustate->eip);
+ m_sreg[CS].selector = selector;
+ m_performed_intersegment_jump = 1;
+ i386_load_segment_descriptor(CS );
+ m_eip = address;
+ CHANGE_PC(m_eip);
}
}
}
@@ -2837,23 +2837,23 @@ static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff
if( modrm >= 0xc0 ) {
value = LOAD_RM32(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- value = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ value = READ32(ea);
}
- PUSH32(cpustate,value);
- CYCLES(cpustate,CYCLES_PUSH_RM);
+ PUSH32(value);
+ CYCLES(CYCLES_PUSH_RM);
}
break;
default:
- report_invalid_modrm(cpustate, "groupFF_32", modrm);
+ report_invalid_modrm("groupFF_32", modrm);
break;
}
}
-static void I386OP(group0F00_32)(i386_state *cpustate) // Opcode 0x0f 00
+void i386_device::i386_group0F00_32() // Opcode 0x0f 00
{
UINT32 address, ea;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
I386_SREG seg;
UINT8 result;
@@ -2863,87 +2863,87 @@ static void I386OP(group0F00_32)(i386_state *cpustate) // Opcode 0x0f 0
if ( PROTECTED_MODE && !V8086_MODE )
{
if( modrm >= 0xc0 ) {
- STORE_RM32(modrm, cpustate->ldtr.segment);
- CYCLES(cpustate,CYCLES_SLDT_REG);
+ STORE_RM32(modrm, m_ldtr.segment);
+ CYCLES(CYCLES_SLDT_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate, ea, cpustate->ldtr.segment);
- CYCLES(cpustate,CYCLES_SLDT_MEM);
+ ea = GetEA(modrm,1);
+ WRITE16(ea, m_ldtr.segment);
+ CYCLES(CYCLES_SLDT_MEM);
}
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
break;
case 1: /* STR */
if ( PROTECTED_MODE && !V8086_MODE )
{
if( modrm >= 0xc0 ) {
- STORE_RM32(modrm, cpustate->task.segment);
- CYCLES(cpustate,CYCLES_STR_REG);
+ STORE_RM32(modrm, m_task.segment);
+ CYCLES(CYCLES_STR_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate, ea, cpustate->task.segment);
- CYCLES(cpustate,CYCLES_STR_MEM);
+ ea = GetEA(modrm,1);
+ WRITE16(ea, m_task.segment);
+ CYCLES(CYCLES_STR_MEM);
}
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
break;
case 2: /* LLDT */
if ( PROTECTED_MODE && !V8086_MODE )
{
- if(cpustate->CPL)
+ if(m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- cpustate->ldtr.segment = address;
- CYCLES(cpustate,CYCLES_LLDT_REG);
+ m_ldtr.segment = address;
+ CYCLES(CYCLES_LLDT_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- cpustate->ldtr.segment = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_LLDT_MEM);
+ ea = GetEA(modrm,0);
+ m_ldtr.segment = READ32(ea);
+ CYCLES(CYCLES_LLDT_MEM);
}
memset(&seg, 0, sizeof(seg));
- seg.selector = cpustate->ldtr.segment;
- i386_load_protected_mode_segment(cpustate,&seg,NULL);
- cpustate->ldtr.limit = seg.limit;
- cpustate->ldtr.base = seg.base;
- cpustate->ldtr.flags = seg.flags;
+ seg.selector = m_ldtr.segment;
+ i386_load_protected_mode_segment(&seg,NULL);
+ m_ldtr.limit = seg.limit;
+ m_ldtr.base = seg.base;
+ m_ldtr.flags = seg.flags;
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
break;
case 3: /* LTR */
if ( PROTECTED_MODE && !V8086_MODE )
{
- if(cpustate->CPL)
+ if(m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- cpustate->task.segment = address;
- CYCLES(cpustate,CYCLES_LTR_REG);
+ m_task.segment = address;
+ CYCLES(CYCLES_LTR_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- cpustate->task.segment = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_LTR_MEM);
+ ea = GetEA(modrm,0);
+ m_task.segment = READ32(ea);
+ CYCLES(CYCLES_LTR_MEM);
}
memset(&seg, 0, sizeof(seg));
- seg.selector = cpustate->task.segment;
- i386_load_protected_mode_segment(cpustate,&seg,NULL);
- cpustate->task.limit = seg.limit;
- cpustate->task.base = seg.base;
- cpustate->task.flags = seg.flags;
+ seg.selector = m_task.segment;
+ i386_load_protected_mode_segment(&seg,NULL);
+ m_task.limit = seg.limit;
+ m_task.base = seg.base;
+ m_task.flags = seg.flags;
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
break;
@@ -2952,15 +2952,15 @@ static void I386OP(group0F00_32)(i386_state *cpustate) // Opcode 0x0f 0
{
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_VERR_REG);
+ CYCLES(CYCLES_VERR_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- address = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_VERR_MEM);
+ ea = GetEA(modrm,0);
+ address = READ32(ea);
+ CYCLES(CYCLES_VERR_MEM);
}
memset(&seg, 0, sizeof(seg));
seg.selector = address;
- result = i386_load_protected_mode_segment(cpustate,&seg,NULL);
+ result = i386_load_protected_mode_segment(&seg,NULL);
// check if the segment is a code or data segment (not a special segment type, like a TSS, gate, LDT...)
if(!(seg.flags & 0x10))
result = 0;
@@ -2989,7 +2989,7 @@ static void I386OP(group0F00_32)(i386_state *cpustate) // Opcode 0x0f 0
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
logerror("i386: VERR: Exception - Running in real mode or virtual 8086 mode.\n");
}
break;
@@ -2999,15 +2999,15 @@ static void I386OP(group0F00_32)(i386_state *cpustate) // Opcode 0x0f 0
{
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_VERW_REG);
+ CYCLES(CYCLES_VERW_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- address = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_VERW_MEM);
+ ea = GetEA(modrm,0);
+ address = READ16(ea);
+ CYCLES(CYCLES_VERW_MEM);
}
memset(&seg, 0, sizeof(seg));
seg.selector = address;
- result = i386_load_protected_mode_segment(cpustate,&seg,NULL);
+ result = i386_load_protected_mode_segment(&seg,NULL);
// check if the segment is a code or data segment (not a special segment type, like a TSS, gate, LDT...)
if(!(seg.flags & 0x10))
result = 0;
@@ -3031,20 +3031,20 @@ static void I386OP(group0F00_32)(i386_state *cpustate) // Opcode 0x0f 0
}
else
{
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
logerror("i386: VERW: Exception - Running in real mode or virtual 8086 mode.\n");
}
break;
default:
- report_invalid_modrm(cpustate, "group0F00_32", modrm);
+ report_invalid_modrm("group0F00_32", modrm);
break;
}
}
-static void I386OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01
+void i386_device::i386_group0F01_32() // Opcode 0x0f 01
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT32 address, ea;
switch( (modrm >> 3) & 0x7 )
@@ -3053,13 +3053,13 @@ static void I386OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01
{
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- ea = i386_translate(cpustate, CS, address, 1 );
+ ea = i386_translate(CS, address, 1 );
} else {
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
}
- WRITE16(cpustate,ea, cpustate->gdtr.limit);
- WRITE32(cpustate,ea + 2, cpustate->gdtr.base);
- CYCLES(cpustate,CYCLES_SGDT);
+ WRITE16(ea, m_gdtr.limit);
+ WRITE32(ea + 2, m_gdtr.base);
+ CYCLES(CYCLES_SGDT);
break;
}
case 1: /* SIDT */
@@ -3067,209 +3067,209 @@ static void I386OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01
if (modrm >= 0xc0)
{
address = LOAD_RM32(modrm);
- ea = i386_translate(cpustate, CS, address, 1 );
+ ea = i386_translate(CS, address, 1 );
}
else
{
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
}
- WRITE16(cpustate,ea, cpustate->idtr.limit);
- WRITE32(cpustate,ea + 2, cpustate->idtr.base);
- CYCLES(cpustate,CYCLES_SIDT);
+ WRITE16(ea, m_idtr.limit);
+ WRITE32(ea + 2, m_idtr.base);
+ CYCLES(CYCLES_SIDT);
break;
}
case 2: /* LGDT */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- ea = i386_translate(cpustate, CS, address, 0 );
+ ea = i386_translate(CS, address, 0 );
} else {
- ea = GetEA(cpustate,modrm,0);
+ ea = GetEA(modrm,0);
}
- cpustate->gdtr.limit = READ16(cpustate,ea);
- cpustate->gdtr.base = READ32(cpustate,ea + 2);
- CYCLES(cpustate,CYCLES_LGDT);
+ m_gdtr.limit = READ16(ea);
+ m_gdtr.base = READ32(ea + 2);
+ CYCLES(CYCLES_LGDT);
break;
}
case 3: /* LIDT */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- ea = i386_translate(cpustate, CS, address, 0 );
+ ea = i386_translate(CS, address, 0 );
} else {
- ea = GetEA(cpustate,modrm,0);
+ ea = GetEA(modrm,0);
}
- cpustate->idtr.limit = READ16(cpustate,ea);
- cpustate->idtr.base = READ32(cpustate,ea + 2);
- CYCLES(cpustate,CYCLES_LIDT);
+ m_idtr.limit = READ16(ea);
+ m_idtr.base = READ32(ea + 2);
+ CYCLES(CYCLES_LIDT);
break;
}
case 4: /* SMSW */
{
if( modrm >= 0xc0 ) {
// smsw stores all of cr0 into register
- STORE_RM32(modrm, cpustate->cr[0]);
- CYCLES(cpustate,CYCLES_SMSW_REG);
+ STORE_RM32(modrm, m_cr[0]);
+ CYCLES(CYCLES_SMSW_REG);
} else {
/* always 16-bit memory operand */
- ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate,ea, cpustate->cr[0]);
- CYCLES(cpustate,CYCLES_SMSW_MEM);
+ ea = GetEA(modrm,1);
+ WRITE16(ea, m_cr[0]);
+ CYCLES(CYCLES_SMSW_MEM);
}
break;
}
case 6: /* LMSW */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
UINT16 b;
if( modrm >= 0xc0 ) {
b = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_LMSW_REG);
+ CYCLES(CYCLES_LMSW_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- CYCLES(cpustate,CYCLES_LMSW_MEM);
- b = READ16(cpustate,ea);
+ ea = GetEA(modrm,0);
+ CYCLES(CYCLES_LMSW_MEM);
+ b = READ16(ea);
}
if(PROTECTED_MODE)
b |= 0x0001; // cannot return to real mode using this instruction.
- cpustate->cr[0] &= ~0x0000000f;
- cpustate->cr[0] |= b & 0x0000000f;
+ m_cr[0] &= ~0x0000000f;
+ m_cr[0] |= b & 0x0000000f;
break;
}
default:
- report_invalid_modrm(cpustate, "group0F01_32", modrm);
+ report_invalid_modrm("group0F01_32", modrm);
break;
}
}
-static void I386OP(group0FBA_32)(i386_state *cpustate) // Opcode 0x0f ba
+void i386_device::i386_group0FBA_32() // Opcode 0x0f ba
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 4: /* BT Rm32, i8 */
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
- UINT8 bit = FETCH(cpustate);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
- CYCLES(cpustate,CYCLES_BT_IMM_REG);
+ CYCLES(CYCLES_BT_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT32 dst = READ32(cpustate,ea);
- UINT8 bit = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,0);
+ UINT32 dst = READ32(ea);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
- CYCLES(cpustate,CYCLES_BT_IMM_MEM);
+ CYCLES(CYCLES_BT_IMM_MEM);
}
break;
case 5: /* BTS Rm32, i8 */
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
- UINT8 bit = FETCH(cpustate);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst |= (1 << bit);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_BTS_IMM_REG);
+ CYCLES(CYCLES_BTS_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
- UINT8 bit = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst |= (1 << bit);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTS_IMM_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_BTS_IMM_MEM);
}
break;
case 6: /* BTR Rm32, i8 */
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
- UINT8 bit = FETCH(cpustate);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst &= ~(1 << bit);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_BTR_IMM_REG);
+ CYCLES(CYCLES_BTR_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
- UINT8 bit = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst &= ~(1 << bit);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTR_IMM_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_BTR_IMM_MEM);
}
break;
case 7: /* BTC Rm32, i8 */
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
- UINT8 bit = FETCH(cpustate);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst ^= (1 << bit);
STORE_RM32(modrm, dst);
- CYCLES(cpustate,CYCLES_BTC_IMM_REG);
+ CYCLES(CYCLES_BTC_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
- UINT8 bit = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
+ UINT8 bit = FETCH();
if( dst & (1 << bit) )
- cpustate->CF = 1;
+ m_CF = 1;
else
- cpustate->CF = 0;
+ m_CF = 0;
dst ^= (1 << bit);
- WRITE32(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_BTC_IMM_MEM);
+ WRITE32(ea, dst);
+ CYCLES(CYCLES_BTC_IMM_MEM);
}
break;
default:
- report_invalid_modrm(cpustate, "group0FBA_32", modrm);
+ report_invalid_modrm("group0FBA_32", modrm);
break;
}
}
-static void I386OP(lar_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 0x02
+void i386_device::i386_lar_r32_rm32() // Opcode 0x0f 0x02
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
I386_SREG seg;
UINT8 type;
@@ -3279,13 +3279,13 @@ static void I386OP(lar_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 0x02
if(modrm >= 0xc0)
{
seg.selector = LOAD_RM32(modrm);
- CYCLES(cpustate,CYCLES_LAR_REG);
+ CYCLES(CYCLES_LAR_REG);
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- seg.selector = READ32(cpustate,ea);
- CYCLES(cpustate,CYCLES_LAR_MEM);
+ UINT32 ea = GetEA(modrm,0);
+ seg.selector = READ32(ea);
+ CYCLES(CYCLES_LAR_MEM);
}
if(seg.selector == 0)
{
@@ -3294,13 +3294,13 @@ static void I386OP(lar_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 0x02
else
{
UINT64 desc;
- if(!i386_load_protected_mode_segment(cpustate,&seg,&desc))
+ if(!i386_load_protected_mode_segment(&seg,&desc))
{
SetZF(0);
return;
}
UINT8 DPL = (seg.flags >> 5) & 3;
- if(((DPL < cpustate->CPL) || (DPL < (seg.selector & 3))) && ((seg.flags & 0x1c) != 0x1c))
+ if(((DPL < m_CPL) || (DPL < (seg.selector & 3))) && ((seg.flags & 0x1c) != 0x1c))
{
SetZF(0);
return;
@@ -3329,14 +3329,14 @@ static void I386OP(lar_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 0x02
else
{
// illegal opcode
- i386_trap(cpustate,6,0, 0);
+ i386_trap(6,0, 0);
logerror("i386: LAR: Exception - running in real mode or virtual 8086 mode.\n");
}
}
-static void I386OP(lsl_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 0x03
+void i386_device::i386_lsl_r32_rm32() // Opcode 0x0f 0x03
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT32 limit;
I386_SREG seg;
@@ -3349,8 +3349,8 @@ static void I386OP(lsl_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 0x03
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- seg.selector = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ seg.selector = READ32(ea);
}
if(seg.selector == 0)
{
@@ -3359,13 +3359,13 @@ static void I386OP(lsl_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 0x03
else
{
UINT8 type;
- if(!i386_load_protected_mode_segment(cpustate,&seg,NULL))
+ if(!i386_load_protected_mode_segment(&seg,NULL))
{
SetZF(0);
return;
}
UINT8 DPL = (seg.flags >> 5) & 3;
- if(((DPL < cpustate->CPL) || (DPL < (seg.selector & 3))) && ((seg.flags & 0x1c) != 0x1c))
+ if(((DPL < m_CPL) || (DPL < (seg.selector & 3))) && ((seg.flags & 0x1c) != 0x1c))
{
SetZF(0);
return;
@@ -3394,15 +3394,15 @@ static void I386OP(lsl_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 0x03
}
}
else
- i386_trap(cpustate,6, 0, 0);
+ i386_trap(6, 0, 0);
}
-static void I386OP(bound_r32_m32_m32)(i386_state *cpustate) // Opcode 0x62
+void i386_device::i386_bound_r32_m32_m32() // Opcode 0x62
{
UINT8 modrm;
INT32 val, low, high;
- modrm = FETCH(cpustate);
+ modrm = FETCH();
if (modrm >= 0xc0)
{
@@ -3410,101 +3410,101 @@ static void I386OP(bound_r32_m32_m32)(i386_state *cpustate) // Opcode 0x62
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- low = READ32(cpustate,ea + 0);
- high = READ32(cpustate,ea + 4);
+ UINT32 ea = GetEA(modrm,0);
+ low = READ32(ea + 0);
+ high = READ32(ea + 4);
}
val = LOAD_REG32(modrm);
if ((val < low) || (val > high))
{
- CYCLES(cpustate,CYCLES_BOUND_OUT_RANGE);
- i386_trap(cpustate,5, 0, 0);
+ CYCLES(CYCLES_BOUND_OUT_RANGE);
+ i386_trap(5, 0, 0);
}
else
{
- CYCLES(cpustate,CYCLES_BOUND_IN_RANGE);
+ CYCLES(CYCLES_BOUND_IN_RANGE);
}
}
-static void I386OP(retf32)(i386_state *cpustate) // Opcode 0xcb
+void i386_device::i386_retf32() // Opcode 0xcb
{
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_retf(cpustate,0,1);
+ i386_protected_mode_retf(0,1);
}
else
{
- cpustate->eip = POP32(cpustate);
- cpustate->sreg[CS].selector = POP32(cpustate);
- i386_load_segment_descriptor(cpustate, CS );
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = POP32();
+ m_sreg[CS].selector = POP32();
+ i386_load_segment_descriptor(CS );
+ CHANGE_PC(m_eip);
}
- CYCLES(cpustate,CYCLES_RET_INTERSEG);
+ CYCLES(CYCLES_RET_INTERSEG);
}
-static void I386OP(retf_i32)(i386_state *cpustate) // Opcode 0xca
+void i386_device::i386_retf_i32() // Opcode 0xca
{
- UINT16 count = FETCH16(cpustate);
+ UINT16 count = FETCH16();
if(PROTECTED_MODE && !V8086_MODE)
{
- i386_protected_mode_retf(cpustate,count,1);
+ i386_protected_mode_retf(count,1);
}
else
{
- cpustate->eip = POP32(cpustate);
- cpustate->sreg[CS].selector = POP32(cpustate);
- i386_load_segment_descriptor(cpustate, CS );
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = POP32();
+ m_sreg[CS].selector = POP32();
+ i386_load_segment_descriptor(CS );
+ CHANGE_PC(m_eip);
REG32(ESP) += count;
}
- CYCLES(cpustate,CYCLES_RET_IMM_INTERSEG);
+ CYCLES(CYCLES_RET_IMM_INTERSEG);
}
-static void I386OP(load_far_pointer32)(i386_state *cpustate, int s)
+void i386_device::i386_load_far_pointer32(int s)
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT16 selector;
if( modrm >= 0xc0 ) {
- report_invalid_modrm(cpustate, "load_far_pointer32", modrm);
+ report_invalid_modrm("load_far_pointer32", modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- STORE_REG32(modrm, READ32(cpustate,ea + 0));
- selector = READ16(cpustate,ea + 4);
- i386_sreg_load(cpustate,selector,s,NULL);
+ UINT32 ea = GetEA(modrm,0);
+ STORE_REG32(modrm, READ32(ea + 0));
+ selector = READ16(ea + 4);
+ i386_sreg_load(selector,s,NULL);
}
}
-static void I386OP(lds32)(i386_state *cpustate) // Opcode 0xc5
+void i386_device::i386_lds32() // Opcode 0xc5
{
- I386OP(load_far_pointer32)(cpustate, DS);
- CYCLES(cpustate,CYCLES_LDS);
+ i386_load_far_pointer32(DS);
+ CYCLES(CYCLES_LDS);
}
-static void I386OP(lss32)(i386_state *cpustate) // Opcode 0x0f 0xb2
+void i386_device::i386_lss32() // Opcode 0x0f 0xb2
{
- I386OP(load_far_pointer32)(cpustate, SS);
- CYCLES(cpustate,CYCLES_LSS);
+ i386_load_far_pointer32(SS);
+ CYCLES(CYCLES_LSS);
}
-static void I386OP(les32)(i386_state *cpustate) // Opcode 0xc4
+void i386_device::i386_les32() // Opcode 0xc4
{
- I386OP(load_far_pointer32)(cpustate, ES);
- CYCLES(cpustate,CYCLES_LES);
+ i386_load_far_pointer32(ES);
+ CYCLES(CYCLES_LES);
}
-static void I386OP(lfs32)(i386_state *cpustate) // Opcode 0x0f 0xb4
+void i386_device::i386_lfs32() // Opcode 0x0f 0xb4
{
- I386OP(load_far_pointer32)(cpustate, FS);
- CYCLES(cpustate,CYCLES_LFS);
+ i386_load_far_pointer32(FS);
+ CYCLES(CYCLES_LFS);
}
-static void I386OP(lgs32)(i386_state *cpustate) // Opcode 0x0f 0xb5
+void i386_device::i386_lgs32() // Opcode 0x0f 0xb5
{
- I386OP(load_far_pointer32)(cpustate, GS);
- CYCLES(cpustate,CYCLES_LGS);
+ i386_load_far_pointer32(GS);
+ CYCLES(CYCLES_LGS);
}
diff --git a/src/emu/cpu/i386/i386ops.c b/src/emu/cpu/i386/i386ops.c
index 30d637fe0bc..b8b961e65a4 100644
--- a/src/emu/cpu/i386/i386ops.c
+++ b/src/emu/cpu/i386/i386ops.c
@@ -1,58 +1,58 @@
-static UINT8 I386OP(shift_rotate8)(i386_state *cpustate, UINT8 modrm, UINT32 value, UINT8 shift)
+UINT8 i386_device::i386_shift_rotate8(UINT8 modrm, UINT32 value, UINT8 shift)
{
UINT32 src = value & 0xff;
UINT8 dst = value;
if( shift == 0 ) {
- CYCLES_RM(cpustate,modrm, 3, 7);
+ CYCLES_RM(modrm, 3, 7);
} else if( shift == 1 ) {
switch( (modrm >> 3) & 0x7 )
{
case 0: /* ROL rm8, 1 */
- cpustate->CF = (src & 0x80) ? 1 : 0;
- dst = (src << 1) + cpustate->CF;
- cpustate->OF = ((src ^ dst) & 0x80) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (src & 0x80) ? 1 : 0;
+ dst = (src << 1) + m_CF;
+ m_OF = ((src ^ dst) & 0x80) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 1: /* ROR rm8, 1 */
- cpustate->CF = (src & 0x1) ? 1 : 0;
- dst = (cpustate->CF << 7) | (src >> 1);
- cpustate->OF = ((src ^ dst) & 0x80) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (src & 0x1) ? 1 : 0;
+ dst = (m_CF << 7) | (src >> 1);
+ m_OF = ((src ^ dst) & 0x80) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 2: /* RCL rm8, 1 */
- dst = (src << 1) + cpustate->CF;
- cpustate->CF = (src & 0x80) ? 1 : 0;
- cpustate->OF = ((src ^ dst) & 0x80) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ dst = (src << 1) + m_CF;
+ m_CF = (src & 0x80) ? 1 : 0;
+ m_OF = ((src ^ dst) & 0x80) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 3: /* RCR rm8, 1 */
- dst = (cpustate->CF << 7) | (src >> 1);
- cpustate->CF = src & 0x1;
- cpustate->OF = ((src ^ dst) & 0x80) ? 1 : 0;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ dst = (m_CF << 7) | (src >> 1);
+ m_CF = src & 0x1;
+ m_OF = ((src ^ dst) & 0x80) ? 1 : 0;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 4: /* SHL/SAL rm8, 1 */
case 6:
dst = src << 1;
- cpustate->CF = (src & 0x80) ? 1 : 0;
- cpustate->OF = (((cpustate->CF << 7) ^ dst) & 0x80) ? 1 : 0;
+ m_CF = (src & 0x80) ? 1 : 0;
+ m_OF = (((m_CF << 7) ^ dst) & 0x80) ? 1 : 0;
SetSZPF8(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 5: /* SHR rm8, 1 */
dst = src >> 1;
- cpustate->CF = src & 0x1;
- cpustate->OF = (dst & 0x80) ? 1 : 0;
+ m_CF = src & 0x1;
+ m_OF = (dst & 0x80) ? 1 : 0;
SetSZPF8(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 7: /* SAR rm8, 1 */
dst = (INT8)(src) >> 1;
- cpustate->CF = src & 0x1;
- cpustate->OF = 0;
+ m_CF = src & 0x1;
+ m_OF = 0;
SetSZPF8(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
}
@@ -64,74 +64,74 @@ static UINT8 I386OP(shift_rotate8)(i386_state *cpustate, UINT8 modrm, UINT32 val
{
if(shift & 0x18)
{
- cpustate->CF = src & 1;
- cpustate->OF = (src & 1) ^ ((src >> 7) & 1);
+ m_CF = src & 1;
+ m_OF = (src & 1) ^ ((src >> 7) & 1);
}
break;
}
shift &= 7;
dst = ((src & ((UINT8)0xff >> shift)) << shift) |
((src & ((UINT8)0xff << (8-shift))) >> (8-shift));
- cpustate->CF = dst & 0x1;
- cpustate->OF = (dst & 1) ^ (dst >> 7);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = dst & 0x1;
+ m_OF = (dst & 1) ^ (dst >> 7);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 1: /* ROR rm8, i8 */
if(!(shift & 7))
{
if(shift & 0x18)
{
- cpustate->CF = (src >> 7) & 1;
- cpustate->OF = ((src >> 7) & 1) ^ ((src >> 6) & 1);
+ m_CF = (src >> 7) & 1;
+ m_OF = ((src >> 7) & 1) ^ ((src >> 6) & 1);
}
break;
}
shift &= 7;
dst = ((src & ((UINT8)0xff << shift)) >> shift) |
((src & ((UINT8)0xff >> (8-shift))) << (8-shift));
- cpustate->CF = (dst >> 7) & 1;
- cpustate->OF = ((dst >> 7) ^ (dst >> 6)) & 1;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ m_CF = (dst >> 7) & 1;
+ m_OF = ((dst >> 7) ^ (dst >> 6)) & 1;
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 2: /* RCL rm8, i8 */
shift %= 9;
dst = ((src & ((UINT8)0xff >> shift)) << shift) |
((src & ((UINT8)0xff << (9-shift))) >> (9-shift)) |
- (cpustate->CF << (shift-1));
- if(shift) cpustate->CF = (src >> (8-shift)) & 0x1;
- cpustate->OF = cpustate->CF ^ ((dst >> 7) & 1);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ (m_CF << (shift-1));
+ if(shift) m_CF = (src >> (8-shift)) & 0x1;
+ m_OF = m_CF ^ ((dst >> 7) & 1);
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 3: /* RCR rm8, i8 */
shift %= 9;
dst = ((src & ((UINT8)0xff << shift)) >> shift) |
((src & ((UINT8)0xff >> (8-shift))) << (9-shift)) |
- (cpustate->CF << (8-shift));
- if(shift) cpustate->CF = (src >> (shift-1)) & 0x1;
- cpustate->OF = ((dst >> 7) ^ (dst >> 6)) & 1;
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
+ (m_CF << (8-shift));
+ if(shift) m_CF = (src >> (shift-1)) & 0x1;
+ m_OF = ((dst >> 7) ^ (dst >> 6)) & 1;
+ CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM);
break;
case 4: /* SHL/SAL rm8, i8 */
case 6:
shift &= 31;
dst = src << shift;
- cpustate->CF = (shift <= 8) && ((src >> (8 - shift)) & 1);
+ m_CF = (shift <= 8) && ((src >> (8 - shift)) & 1);
SetSZPF8(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 5: /* SHR rm8, i8 */
shift &= 31;
dst = src >> shift;
- cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (src & (1 << (shift-1))) ? 1 : 0;
SetSZPF8(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
case 7: /* SAR rm8, i8 */
shift &= 31;
dst = (INT8)src >> shift;
- cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0;
+ m_CF = (src & (1 << (shift-1))) ? 1 : 0;
SetSZPF8(dst);
- CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
+ CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM);
break;
}
}
@@ -141,593 +141,593 @@ static UINT8 I386OP(shift_rotate8)(i386_state *cpustate, UINT8 modrm, UINT32 val
-static void I386OP(adc_rm8_r8)(i386_state *cpustate) // Opcode 0x10
+void i386_device::i386_adc_rm8_r8() // Opcode 0x10
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
- dst = ADC8(cpustate, dst, src, cpustate->CF);
+ dst = ADC8(dst, src, m_CF);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
- dst = ADC8(cpustate, dst, src, cpustate->CF);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ8(ea);
+ dst = ADC8(dst, src, m_CF);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(adc_r8_rm8)(i386_state *cpustate) // Opcode 0x12
+void i386_device::i386_adc_r8_rm8() // Opcode 0x12
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
dst = LOAD_REG8(modrm);
- dst = ADC8(cpustate, dst, src, cpustate->CF);
+ dst = ADC8(dst, src, m_CF);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
dst = LOAD_REG8(modrm);
- dst = ADC8(cpustate, dst, src, cpustate->CF);
+ dst = ADC8(dst, src, m_CF);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(adc_al_i8)(i386_state *cpustate) // Opcode 0x14
+void i386_device::i386_adc_al_i8() // Opcode 0x14
{
UINT8 src, dst;
- src = FETCH(cpustate);
+ src = FETCH();
dst = REG8(AL);
- dst = ADC8(cpustate, dst, src, cpustate->CF);
+ dst = ADC8(dst, src, m_CF);
REG8(AL) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(add_rm8_r8)(i386_state *cpustate) // Opcode 0x00
+void i386_device::i386_add_rm8_r8() // Opcode 0x00
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
- dst = ADD8(cpustate,dst, src);
+ dst = ADD8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
- dst = ADD8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ8(ea);
+ dst = ADD8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(add_r8_rm8)(i386_state *cpustate) // Opcode 0x02
+void i386_device::i386_add_r8_rm8() // Opcode 0x02
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
dst = LOAD_REG8(modrm);
- dst = ADD8(cpustate,dst, src);
+ dst = ADD8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
dst = LOAD_REG8(modrm);
- dst = ADD8(cpustate,dst, src);
+ dst = ADD8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(add_al_i8)(i386_state *cpustate) // Opcode 0x04
+void i386_device::i386_add_al_i8() // Opcode 0x04
{
UINT8 src, dst;
- src = FETCH(cpustate);
+ src = FETCH();
dst = REG8(AL);
- dst = ADD8(cpustate,dst, src);
+ dst = ADD8(dst, src);
REG8(AL) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(and_rm8_r8)(i386_state *cpustate) // Opcode 0x20
+void i386_device::i386_and_rm8_r8() // Opcode 0x20
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
- dst = AND8(cpustate,dst, src);
+ dst = AND8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
- dst = AND8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ8(ea);
+ dst = AND8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(and_r8_rm8)(i386_state *cpustate) // Opcode 0x22
+void i386_device::i386_and_r8_rm8() // Opcode 0x22
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
dst = LOAD_REG8(modrm);
- dst = AND8(cpustate,dst, src);
+ dst = AND8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
dst = LOAD_REG8(modrm);
- dst = AND8(cpustate,dst, src);
+ dst = AND8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(and_al_i8)(i386_state *cpustate) // Opcode 0x24
+void i386_device::i386_and_al_i8() // Opcode 0x24
{
UINT8 src, dst;
- src = FETCH(cpustate);
+ src = FETCH();
dst = REG8(AL);
- dst = AND8(cpustate,dst, src);
+ dst = AND8(dst, src);
REG8(AL) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(clc)(i386_state *cpustate) // Opcode 0xf8
+void i386_device::i386_clc() // Opcode 0xf8
{
- cpustate->CF = 0;
- CYCLES(cpustate,CYCLES_CLC);
+ m_CF = 0;
+ CYCLES(CYCLES_CLC);
}
-static void I386OP(cld)(i386_state *cpustate) // Opcode 0xfc
+void i386_device::i386_cld() // Opcode 0xfc
{
- cpustate->DF = 0;
- CYCLES(cpustate,CYCLES_CLD);
+ m_DF = 0;
+ CYCLES(CYCLES_CLD);
}
-static void I386OP(cli)(i386_state *cpustate) // Opcode 0xfa
+void i386_device::i386_cli() // Opcode 0xfa
{
if(PROTECTED_MODE)
{
- UINT8 IOPL = cpustate->IOP1 | (cpustate->IOP2 << 1);
- if(cpustate->CPL > IOPL)
+ UINT8 IOPL = m_IOP1 | (m_IOP2 << 1);
+ if(m_CPL > IOPL)
FAULT(FAULT_GP,0);
}
- cpustate->IF = 0;
- CYCLES(cpustate,CYCLES_CLI);
+ m_IF = 0;
+ CYCLES(CYCLES_CLI);
}
-static void I386OP(cmc)(i386_state *cpustate) // Opcode 0xf5
+void i386_device::i386_cmc() // Opcode 0xf5
{
- cpustate->CF ^= 1;
- CYCLES(cpustate,CYCLES_CMC);
+ m_CF ^= 1;
+ CYCLES(CYCLES_CMC);
}
-static void I386OP(cmp_rm8_r8)(i386_state *cpustate) // Opcode 0x38
+void i386_device::i386_cmp_rm8_r8() // Opcode 0x38
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
- SUB8(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ SUB8(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
+ UINT32 ea = GetEA(modrm,0);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
- SUB8(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_MEM);
+ dst = READ8(ea);
+ SUB8(dst, src);
+ CYCLES(CYCLES_CMP_REG_MEM);
}
}
-static void I386OP(cmp_r8_rm8)(i386_state *cpustate) // Opcode 0x3a
+void i386_device::i386_cmp_r8_rm8() // Opcode 0x3a
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
dst = LOAD_REG8(modrm);
- SUB8(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ SUB8(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
dst = LOAD_REG8(modrm);
- SUB8(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_MEM_REG);
+ SUB8(dst, src);
+ CYCLES(CYCLES_CMP_MEM_REG);
}
}
-static void I386OP(cmp_al_i8)(i386_state *cpustate) // Opcode 0x3c
+void i386_device::i386_cmp_al_i8() // Opcode 0x3c
{
UINT8 src, dst;
- src = FETCH(cpustate);
+ src = FETCH();
dst = REG8(AL);
- SUB8(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_IMM_ACC);
+ SUB8(dst, src);
+ CYCLES(CYCLES_CMP_IMM_ACC);
}
-static void I386OP(cmpsb)(i386_state *cpustate) // Opcode 0xa6
+void i386_device::i386_cmpsb() // Opcode 0xa6
{
UINT32 eas, ead;
UINT8 src, dst;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 0 );
- src = READ8(cpustate,eas);
- dst = READ8(cpustate,ead);
- SUB8(cpustate,src, dst);
- BUMP_SI(cpustate,1);
- BUMP_DI(cpustate,1);
- CYCLES(cpustate,CYCLES_CMPS);
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 0 );
+ src = READ8(eas);
+ dst = READ8(ead);
+ SUB8(src, dst);
+ BUMP_SI(1);
+ BUMP_DI(1);
+ CYCLES(CYCLES_CMPS);
}
-static void I386OP(in_al_i8)(i386_state *cpustate) // Opcode 0xe4
+void i386_device::i386_in_al_i8() // Opcode 0xe4
{
- UINT16 port = FETCH(cpustate);
- UINT8 data = READPORT8(cpustate, port);
+ UINT16 port = FETCH();
+ UINT8 data = READPORT8(port);
REG8(AL) = data;
- CYCLES(cpustate,CYCLES_IN_VAR);
+ CYCLES(CYCLES_IN_VAR);
}
-static void I386OP(in_al_dx)(i386_state *cpustate) // Opcode 0xec
+void i386_device::i386_in_al_dx() // Opcode 0xec
{
UINT16 port = REG16(DX);
- UINT8 data = READPORT8(cpustate, port);
+ UINT8 data = READPORT8(port);
REG8(AL) = data;
- CYCLES(cpustate,CYCLES_IN);
+ CYCLES(CYCLES_IN);
}
-static void I386OP(ja_rel8)(i386_state *cpustate) // Opcode 0x77
+void i386_device::i386_ja_rel8() // Opcode 0x77
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->CF == 0 && cpustate->ZF == 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_CF == 0 && m_ZF == 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jbe_rel8)(i386_state *cpustate) // Opcode 0x76
+void i386_device::i386_jbe_rel8() // Opcode 0x76
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->CF != 0 || cpustate->ZF != 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_CF != 0 || m_ZF != 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jc_rel8)(i386_state *cpustate) // Opcode 0x72
+void i386_device::i386_jc_rel8() // Opcode 0x72
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->CF != 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_CF != 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jg_rel8)(i386_state *cpustate) // Opcode 0x7f
+void i386_device::i386_jg_rel8() // Opcode 0x7f
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->ZF == 0 && (cpustate->SF == cpustate->OF) ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_ZF == 0 && (m_SF == m_OF) ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jge_rel8)(i386_state *cpustate) // Opcode 0x7d
+void i386_device::i386_jge_rel8() // Opcode 0x7d
{
- INT8 disp = FETCH(cpustate);
- if(cpustate->SF == cpustate->OF) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if(m_SF == m_OF) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jl_rel8)(i386_state *cpustate) // Opcode 0x7c
+void i386_device::i386_jl_rel8() // Opcode 0x7c
{
- INT8 disp = FETCH(cpustate);
- if( (cpustate->SF != cpustate->OF) ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( (m_SF != m_OF) ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jle_rel8)(i386_state *cpustate) // Opcode 0x7e
+void i386_device::i386_jle_rel8() // Opcode 0x7e
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->ZF != 0 || (cpustate->SF != cpustate->OF) ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_ZF != 0 || (m_SF != m_OF) ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jnc_rel8)(i386_state *cpustate) // Opcode 0x73
+void i386_device::i386_jnc_rel8() // Opcode 0x73
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->CF == 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_CF == 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jno_rel8)(i386_state *cpustate) // Opcode 0x71
+void i386_device::i386_jno_rel8() // Opcode 0x71
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->OF == 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_OF == 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jnp_rel8)(i386_state *cpustate) // Opcode 0x7b
+void i386_device::i386_jnp_rel8() // Opcode 0x7b
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->PF == 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_PF == 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jns_rel8)(i386_state *cpustate) // Opcode 0x79
+void i386_device::i386_jns_rel8() // Opcode 0x79
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->SF == 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_SF == 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jnz_rel8)(i386_state *cpustate) // Opcode 0x75
+void i386_device::i386_jnz_rel8() // Opcode 0x75
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->ZF == 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_ZF == 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jo_rel8)(i386_state *cpustate) // Opcode 0x70
+void i386_device::i386_jo_rel8() // Opcode 0x70
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->OF != 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_OF != 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jp_rel8)(i386_state *cpustate) // Opcode 0x7a
+void i386_device::i386_jp_rel8() // Opcode 0x7a
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->PF != 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_PF != 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(js_rel8)(i386_state *cpustate) // Opcode 0x78
+void i386_device::i386_js_rel8() // Opcode 0x78
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->SF != 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_SF != 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jz_rel8)(i386_state *cpustate) // Opcode 0x74
+void i386_device::i386_jz_rel8() // Opcode 0x74
{
- INT8 disp = FETCH(cpustate);
- if( cpustate->ZF != 0 ) {
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ if( m_ZF != 0 ) {
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */
} else {
- CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH);
+ CYCLES(CYCLES_JCC_DISP8_NOBRANCH);
}
}
-static void I386OP(jmp_rel8)(i386_state *cpustate) // Opcode 0xeb
+void i386_device::i386_jmp_rel8() // Opcode 0xeb
{
- INT8 disp = FETCH(cpustate);
- NEAR_BRANCH(cpustate,disp);
- CYCLES(cpustate,CYCLES_JMP_SHORT); /* TODO: Timing = 7 + m */
+ INT8 disp = FETCH();
+ NEAR_BRANCH(disp);
+ CYCLES(CYCLES_JMP_SHORT); /* TODO: Timing = 7 + m */
}
-static void I386OP(lahf)(i386_state *cpustate) // Opcode 0x9f
+void i386_device::i386_lahf() // Opcode 0x9f
{
- REG8(AH) = get_flags(cpustate) & 0xd7;
- CYCLES(cpustate,CYCLES_LAHF);
+ REG8(AH) = get_flags() & 0xd7;
+ CYCLES(CYCLES_LAHF);
}
-static void I386OP(lodsb)(i386_state *cpustate) // Opcode 0xac
+void i386_device::i386_lodsb() // Opcode 0xac
{
UINT32 eas;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- REG8(AL) = READ8(cpustate,eas);
- BUMP_SI(cpustate,1);
- CYCLES(cpustate,CYCLES_LODS);
+ REG8(AL) = READ8(eas);
+ BUMP_SI(1);
+ CYCLES(CYCLES_LODS);
}
-static void I386OP(mov_rm8_r8)(i386_state *cpustate) // Opcode 0x88
+void i386_device::i386_mov_rm8_r8() // Opcode 0x88
{
UINT8 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
STORE_RM8(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_REG_REG);
+ CYCLES(CYCLES_MOV_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG8(modrm);
- WRITE8(cpustate,ea, src);
- CYCLES(cpustate,CYCLES_MOV_REG_MEM);
+ WRITE8(ea, src);
+ CYCLES(CYCLES_MOV_REG_MEM);
}
}
-static void I386OP(mov_r8_rm8)(i386_state *cpustate) // Opcode 0x8a
+void i386_device::i386_mov_r8_rm8() // Opcode 0x8a
{
UINT8 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
STORE_REG8(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_REG_REG);
+ CYCLES(CYCLES_MOV_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
STORE_REG8(modrm, src);
- CYCLES(cpustate,CYCLES_MOV_MEM_REG);
+ CYCLES(CYCLES_MOV_MEM_REG);
}
}
-static void I386OP(mov_rm8_i8)(i386_state *cpustate) // Opcode 0xc6
+void i386_device::i386_mov_rm8_i8() // Opcode 0xc6
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
- UINT8 value = FETCH(cpustate);
+ UINT8 value = FETCH();
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ CYCLES(CYCLES_MOV_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT8 value = FETCH(cpustate);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_MOV_IMM_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT8 value = FETCH();
+ WRITE8(ea, value);
+ CYCLES(CYCLES_MOV_IMM_MEM);
}
}
-static void I386OP(mov_r32_cr)(i386_state *cpustate) // Opcode 0x0f 20
+void i386_device::i386_mov_r32_cr() // Opcode 0x0f 20
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP, 0);
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 cr = (modrm >> 3) & 0x7;
- STORE_RM32(modrm, cpustate->cr[cr]);
- CYCLES(cpustate,CYCLES_MOV_CR_REG);
+ STORE_RM32(modrm, m_cr[cr]);
+ CYCLES(CYCLES_MOV_CR_REG);
}
-static void I386OP(mov_r32_dr)(i386_state *cpustate) // Opcode 0x0f 21
+void i386_device::i386_mov_r32_dr() // Opcode 0x0f 21
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP, 0);
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 dr = (modrm >> 3) & 0x7;
- STORE_RM32(modrm, cpustate->dr[dr]);
+ STORE_RM32(modrm, m_dr[dr]);
switch(dr)
{
case 0:
case 1:
case 2:
case 3:
- CYCLES(cpustate,CYCLES_MOV_REG_DR0_3);
+ CYCLES(CYCLES_MOV_REG_DR0_3);
break;
case 6:
case 7:
- CYCLES(cpustate,CYCLES_MOV_REG_DR6_7);
+ CYCLES(CYCLES_MOV_REG_DR6_7);
break;
}
}
-static void I386OP(mov_cr_r32)(i386_state *cpustate) // Opcode 0x0f 22
+void i386_device::i386_mov_cr_r32() // Opcode 0x0f 22
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP, 0);
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 cr = (modrm >> 3) & 0x7;
UINT32 data = LOAD_RM32(modrm);
switch(cr)
{
case 0:
data &= 0xfffeffff; // wp not supported on 386
- CYCLES(cpustate,CYCLES_MOV_REG_CR0);
+ CYCLES(CYCLES_MOV_REG_CR0);
break;
- case 2: CYCLES(cpustate,CYCLES_MOV_REG_CR2); break;
+ case 2: CYCLES(CYCLES_MOV_REG_CR2); break;
case 3:
- CYCLES(cpustate,CYCLES_MOV_REG_CR3);
- vtlb_flush_dynamic(cpustate->vtlb);
+ CYCLES(CYCLES_MOV_REG_CR3);
+ vtlb_flush_dynamic(m_vtlb);
break;
- case 4: CYCLES(cpustate,1); break; // TODO
+ case 4: CYCLES(1); break; // TODO
default:
logerror("i386: mov_cr_r32 CR%d!\n", cr);
return;
}
- cpustate->cr[cr] = data;
+ m_cr[cr] = data;
}
-static void I386OP(mov_dr_r32)(i386_state *cpustate) // Opcode 0x0f 23
+void i386_device::i386_mov_dr_r32() // Opcode 0x0f 23
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP, 0);
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 dr = (modrm >> 3) & 0x7;
- cpustate->dr[dr] = LOAD_RM32(modrm);
+ m_dr[dr] = LOAD_RM32(modrm);
switch(dr)
{
case 0:
case 1:
case 2:
case 3:
- CYCLES(cpustate,CYCLES_MOV_DR0_3_REG);
+ CYCLES(CYCLES_MOV_DR0_3_REG);
break;
case 6:
case 7:
- CYCLES(cpustate,CYCLES_MOV_DR6_7_REG);
+ CYCLES(CYCLES_MOV_DR6_7_REG);
break;
default:
logerror("i386: mov_dr_r32 DR%d!\n", dr);
@@ -735,223 +735,223 @@ static void I386OP(mov_dr_r32)(i386_state *cpustate) // Opcode 0x0f 23
}
}
-static void I386OP(mov_al_m8)(i386_state *cpustate) // Opcode 0xa0
+void i386_device::i386_mov_al_m8() // Opcode 0xa0
{
UINT32 offset, ea;
- if( cpustate->address_size ) {
- offset = FETCH32(cpustate);
+ if( m_address_size ) {
+ offset = FETCH32();
} else {
- offset = FETCH16(cpustate);
+ offset = FETCH16();
}
/* TODO: Not sure if this is correct... */
- if( cpustate->segment_prefix ) {
- ea = i386_translate(cpustate, cpustate->segment_override, offset, 0 );
+ if( m_segment_prefix ) {
+ ea = i386_translate(m_segment_override, offset, 0 );
} else {
- ea = i386_translate(cpustate, DS, offset, 0 );
+ ea = i386_translate(DS, offset, 0 );
}
- REG8(AL) = READ8(cpustate,ea);
- CYCLES(cpustate,CYCLES_MOV_IMM_MEM);
+ REG8(AL) = READ8(ea);
+ CYCLES(CYCLES_MOV_IMM_MEM);
}
-static void I386OP(mov_m8_al)(i386_state *cpustate) // Opcode 0xa2
+void i386_device::i386_mov_m8_al() // Opcode 0xa2
{
UINT32 offset, ea;
- if( cpustate->address_size ) {
- offset = FETCH32(cpustate);
+ if( m_address_size ) {
+ offset = FETCH32();
} else {
- offset = FETCH16(cpustate);
+ offset = FETCH16();
}
/* TODO: Not sure if this is correct... */
- if( cpustate->segment_prefix ) {
- ea = i386_translate(cpustate, cpustate->segment_override, offset, 1 );
+ if( m_segment_prefix ) {
+ ea = i386_translate(m_segment_override, offset, 1 );
} else {
- ea = i386_translate(cpustate, DS, offset, 1 );
+ ea = i386_translate(DS, offset, 1 );
}
- WRITE8(cpustate, ea, REG8(AL) );
- CYCLES(cpustate,CYCLES_MOV_MEM_ACC);
+ WRITE8(ea, REG8(AL) );
+ CYCLES(CYCLES_MOV_MEM_ACC);
}
-static void I386OP(mov_rm16_sreg)(i386_state *cpustate) // Opcode 0x8c
+void i386_device::i386_mov_rm16_sreg() // Opcode 0x8c
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
int s = (modrm >> 3) & 0x7;
if( modrm >= 0xc0 ) {
- if(cpustate->operand_size)
- STORE_RM32(modrm, cpustate->sreg[s].selector);
+ if(m_operand_size)
+ STORE_RM32(modrm, m_sreg[s].selector);
else
- STORE_RM16(modrm, cpustate->sreg[s].selector);
- CYCLES(cpustate,CYCLES_MOV_SREG_REG);
+ STORE_RM16(modrm, m_sreg[s].selector);
+ CYCLES(CYCLES_MOV_SREG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate,ea, cpustate->sreg[s].selector);
- CYCLES(cpustate,CYCLES_MOV_SREG_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE16(ea, m_sreg[s].selector);
+ CYCLES(CYCLES_MOV_SREG_MEM);
}
}
-static void I386OP(mov_sreg_rm16)(i386_state *cpustate) // Opcode 0x8e
+void i386_device::i386_mov_sreg_rm16() // Opcode 0x8e
{
UINT16 selector;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
bool fault;
int s = (modrm >> 3) & 0x7;
if( modrm >= 0xc0 ) {
selector = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_MOV_REG_SREG);
+ CYCLES(CYCLES_MOV_REG_SREG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- selector = READ16(cpustate,ea);
- CYCLES(cpustate,CYCLES_MOV_MEM_SREG);
+ UINT32 ea = GetEA(modrm,0);
+ selector = READ16(ea);
+ CYCLES(CYCLES_MOV_MEM_SREG);
}
- i386_sreg_load(cpustate,selector,s,&fault);
+ i386_sreg_load(selector,s,&fault);
if((s == SS) && !fault)
{
- if(cpustate->IF != 0) // if external interrupts are enabled
+ if(m_IF != 0) // if external interrupts are enabled
{
- cpustate->IF = 0; // reset IF for the next instruction
- cpustate->delayed_interrupt_enable = 1;
+ m_IF = 0; // reset IF for the next instruction
+ m_delayed_interrupt_enable = 1;
}
}
}
-static void I386OP(mov_al_i8)(i386_state *cpustate) // Opcode 0xb0
+void i386_device::i386_mov_al_i8() // Opcode 0xb0
{
- REG8(AL) = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG8(AL) = FETCH();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_cl_i8)(i386_state *cpustate) // Opcode 0xb1
+void i386_device::i386_mov_cl_i8() // Opcode 0xb1
{
- REG8(CL) = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG8(CL) = FETCH();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_dl_i8)(i386_state *cpustate) // Opcode 0xb2
+void i386_device::i386_mov_dl_i8() // Opcode 0xb2
{
- REG8(DL) = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG8(DL) = FETCH();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_bl_i8)(i386_state *cpustate) // Opcode 0xb3
+void i386_device::i386_mov_bl_i8() // Opcode 0xb3
{
- REG8(BL) = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG8(BL) = FETCH();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_ah_i8)(i386_state *cpustate) // Opcode 0xb4
+void i386_device::i386_mov_ah_i8() // Opcode 0xb4
{
- REG8(AH) = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG8(AH) = FETCH();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_ch_i8)(i386_state *cpustate) // Opcode 0xb5
+void i386_device::i386_mov_ch_i8() // Opcode 0xb5
{
- REG8(CH) = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG8(CH) = FETCH();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_dh_i8)(i386_state *cpustate) // Opcode 0xb6
+void i386_device::i386_mov_dh_i8() // Opcode 0xb6
{
- REG8(DH) = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG8(DH) = FETCH();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(mov_bh_i8)(i386_state *cpustate) // Opcode 0xb7
+void i386_device::i386_mov_bh_i8() // Opcode 0xb7
{
- REG8(BH) = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_MOV_IMM_REG);
+ REG8(BH) = FETCH();
+ CYCLES(CYCLES_MOV_IMM_REG);
}
-static void I386OP(movsb)(i386_state *cpustate) // Opcode 0xa4
+void i386_device::i386_movsb() // Opcode 0xa4
{
UINT32 eas, ead;
UINT8 v;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 1 );
- v = READ8(cpustate,eas);
- WRITE8(cpustate,ead, v);
- BUMP_SI(cpustate,1);
- BUMP_DI(cpustate,1);
- CYCLES(cpustate,CYCLES_MOVS);
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 1 );
+ v = READ8(eas);
+ WRITE8(ead, v);
+ BUMP_SI(1);
+ BUMP_DI(1);
+ CYCLES(CYCLES_MOVS);
}
-static void I386OP(or_rm8_r8)(i386_state *cpustate) // Opcode 0x08
+void i386_device::i386_or_rm8_r8() // Opcode 0x08
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
- dst = OR8(cpustate,dst, src);
+ dst = OR8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
- dst = OR8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ8(ea);
+ dst = OR8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(or_r8_rm8)(i386_state *cpustate) // Opcode 0x0a
+void i386_device::i386_or_r8_rm8() // Opcode 0x0a
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
dst = LOAD_REG8(modrm);
- dst = OR8(cpustate,dst, src);
+ dst = OR8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
dst = LOAD_REG8(modrm);
- dst = OR8(cpustate,dst, src);
+ dst = OR8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(or_al_i8)(i386_state *cpustate) // Opcode 0x0c
+void i386_device::i386_or_al_i8() // Opcode 0x0c
{
UINT8 src, dst;
- src = FETCH(cpustate);
+ src = FETCH();
dst = REG8(AL);
- dst = OR8(cpustate,dst, src);
+ dst = OR8(dst, src);
REG8(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(out_al_i8)(i386_state *cpustate) // Opcode 0xe6
+void i386_device::i386_out_al_i8() // Opcode 0xe6
{
- UINT16 port = FETCH(cpustate);
+ UINT16 port = FETCH();
UINT8 data = REG8(AL);
- WRITEPORT8(cpustate, port, data);
- CYCLES(cpustate,CYCLES_OUT_VAR);
+ WRITEPORT8(port, data);
+ CYCLES(CYCLES_OUT_VAR);
}
-static void I386OP(out_al_dx)(i386_state *cpustate) // Opcode 0xee
+void i386_device::i386_out_al_dx() // Opcode 0xee
{
UINT16 port = REG16(DX);
UINT8 data = REG8(AL);
- WRITEPORT8(cpustate, port, data);
- CYCLES(cpustate,CYCLES_OUT);
+ WRITEPORT8(port, data);
+ CYCLES(CYCLES_OUT);
}
-static void I386OP(arpl)(i386_state *cpustate) // Opcode 0x63
+void i386_device::i386_arpl() // Opcode 0x63
{
UINT16 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 flag = 0;
if(PROTECTED_MODE && !V8086_MODE)
@@ -965,129 +965,129 @@ static void I386OP(arpl)(i386_state *cpustate) // Opcode 0x63
STORE_RM16(modrm, dst);
}
} else {
- UINT32 ea = GetEA(cpustate, modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG16(modrm);
- dst = READ16(cpustate, ea);
+ dst = READ16(ea);
if( (dst&0x3) < (src&0x3) ) {
dst = (dst&0xfffc) | (src&0x3);
flag = 1;
- WRITE16(cpustate, ea, dst);
+ WRITE16(ea, dst);
}
}
SetZF(flag);
}
else
- i386_trap(cpustate, 6, 0, 0); // invalid opcode in real mode or v8086 mode
+ i386_trap(6, 0, 0); // invalid opcode in real mode or v8086 mode
}
-static void I386OP(push_i8)(i386_state *cpustate) // Opcode 0x6a
+void i386_device::i386_push_i8() // Opcode 0x6a
{
- UINT8 value = FETCH(cpustate);
- PUSH8(cpustate,value);
- CYCLES(cpustate,CYCLES_PUSH_IMM);
+ UINT8 value = FETCH();
+ PUSH8(value);
+ CYCLES(CYCLES_PUSH_IMM);
}
-static void I386OP(ins_generic)(i386_state *cpustate, int size)
+void i386_device::i386_ins_generic(int size)
{
UINT32 ead;
UINT8 vb;
UINT16 vw;
UINT32 vd;
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 1 );
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 1 );
switch(size) {
case 1:
- vb = READPORT8(cpustate, REG16(DX));
- WRITE8(cpustate,ead, vb);
+ vb = READPORT8(REG16(DX));
+ WRITE8(ead, vb);
break;
case 2:
- vw = READPORT16(cpustate, REG16(DX));
- WRITE16(cpustate,ead, vw);
+ vw = READPORT16(REG16(DX));
+ WRITE16(ead, vw);
break;
case 4:
- vd = READPORT32(cpustate, REG16(DX));
- WRITE32(cpustate,ead, vd);
+ vd = READPORT32(REG16(DX));
+ WRITE32(ead, vd);
break;
}
- if(cpustate->address_size)
- REG32(EDI) += ((cpustate->DF) ? -1 : 1) * size;
+ if(m_address_size)
+ REG32(EDI) += ((m_DF) ? -1 : 1) * size;
else
- REG16(DI) += ((cpustate->DF) ? -1 : 1) * size;
- CYCLES(cpustate,CYCLES_INS); // TODO: Confirm this value
+ REG16(DI) += ((m_DF) ? -1 : 1) * size;
+ CYCLES(CYCLES_INS); // TODO: Confirm this value
}
-static void I386OP(insb)(i386_state *cpustate) // Opcode 0x6c
+void i386_device::i386_insb() // Opcode 0x6c
{
- I386OP(ins_generic)(cpustate, 1);
+ i386_ins_generic(1);
}
-static void I386OP(insw)(i386_state *cpustate) // Opcode 0x6d
+void i386_device::i386_insw() // Opcode 0x6d
{
- I386OP(ins_generic)(cpustate, 2);
+ i386_ins_generic(2);
}
-static void I386OP(insd)(i386_state *cpustate) // Opcode 0x6d
+void i386_device::i386_insd() // Opcode 0x6d
{
- I386OP(ins_generic)(cpustate, 4);
+ i386_ins_generic(4);
}
-static void I386OP(outs_generic)(i386_state *cpustate, int size)
+void i386_device::i386_outs_generic(int size)
{
UINT32 eas;
UINT8 vb;
UINT16 vw;
UINT32 vd;
- if( cpustate->segment_prefix ) {
- eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ if( m_segment_prefix ) {
+ eas = i386_translate(m_segment_override, m_address_size ? REG32(ESI) : REG16(SI), 0 );
} else {
- eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), 0 );
+ eas = i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), 0 );
}
switch(size) {
case 1:
- vb = READ8(cpustate,eas);
- WRITEPORT8(cpustate, REG16(DX), vb);
+ vb = READ8(eas);
+ WRITEPORT8(REG16(DX), vb);
break;
case 2:
- vw = READ16(cpustate,eas);
- WRITEPORT16(cpustate, REG16(DX), vw);
+ vw = READ16(eas);
+ WRITEPORT16(REG16(DX), vw);
break;
case 4:
- vd = READ32(cpustate,eas);
- WRITEPORT32(cpustate, REG16(DX), vd);
+ vd = READ32(eas);
+ WRITEPORT32(REG16(DX), vd);
break;
}
- if(cpustate->address_size)
- REG32(ESI) += ((cpustate->DF) ? -1 : 1) * size;
+ if(m_address_size)
+ REG32(ESI) += ((m_DF) ? -1 : 1) * size;
else
- REG16(SI) += ((cpustate->DF) ? -1 : 1) * size;
- CYCLES(cpustate,CYCLES_OUTS); // TODO: Confirm this value
+ REG16(SI) += ((m_DF) ? -1 : 1) * size;
+ CYCLES(CYCLES_OUTS); // TODO: Confirm this value
}
-static void I386OP(outsb)(i386_state *cpustate) // Opcode 0x6e
+void i386_device::i386_outsb() // Opcode 0x6e
{
- I386OP(outs_generic)(cpustate, 1);
+ i386_outs_generic(1);
}
-static void I386OP(outsw)(i386_state *cpustate) // Opcode 0x6f
+void i386_device::i386_outsw() // Opcode 0x6f
{
- I386OP(outs_generic)(cpustate, 2);
+ i386_outs_generic(2);
}
-static void I386OP(outsd)(i386_state *cpustate) // Opcode 0x6f
+void i386_device::i386_outsd() // Opcode 0x6f
{
- I386OP(outs_generic)(cpustate, 4);
+ i386_outs_generic(4);
}
-static void I386OP(repeat)(i386_state *cpustate, int invert_flag)
+void i386_device::i386_repeat(int invert_flag)
{
- UINT32 repeated_eip = cpustate->eip;
- UINT32 repeated_pc = cpustate->pc;
- UINT8 opcode; // = FETCH(cpustate);
+ UINT32 repeated_eip = m_eip;
+ UINT32 repeated_pc = m_pc;
+ UINT8 opcode; // = FETCH();
// UINT32 eas, ead;
UINT32 count;
INT32 cycle_base = 0, cycle_adjustment = 0;
@@ -1096,45 +1096,45 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag)
do {
- repeated_eip = cpustate->eip;
- repeated_pc = cpustate->pc;
- opcode = FETCH(cpustate);
+ repeated_eip = m_eip;
+ repeated_pc = m_pc;
+ opcode = FETCH();
switch(opcode) {
case 0x0f:
if (invert_flag == 0)
- I386OP(decode_three_bytef3)(cpustate); // sse f3 0f
+ i386_decode_three_bytef3(); // sse f3 0f
else
- I386OP(decode_three_bytef2)(cpustate); // sse f2 0f
+ i386_decode_three_bytef2(); // sse f2 0f
return;
case 0x26:
- cpustate->segment_override=ES;
- cpustate->segment_prefix=1;
+ m_segment_override=ES;
+ m_segment_prefix=1;
break;
case 0x2e:
- cpustate->segment_override=CS;
- cpustate->segment_prefix=1;
+ m_segment_override=CS;
+ m_segment_prefix=1;
break;
case 0x36:
- cpustate->segment_override=SS;
- cpustate->segment_prefix=1;
+ m_segment_override=SS;
+ m_segment_prefix=1;
break;
case 0x3e:
- cpustate->segment_override=DS;
- cpustate->segment_prefix=1;
+ m_segment_override=DS;
+ m_segment_prefix=1;
break;
case 0x64:
- cpustate->segment_override=FS;
- cpustate->segment_prefix=1;
+ m_segment_override=FS;
+ m_segment_prefix=1;
break;
case 0x65:
- cpustate->segment_override=GS;
- cpustate->segment_prefix=1;
+ m_segment_override=GS;
+ m_segment_prefix=1;
break;
case 0x66:
- cpustate->operand_size ^= 1;
+ m_operand_size ^= 1;
break;
case 0x67:
- cpustate->address_size ^= 1;
+ m_address_size ^= 1;
break;
default:
prefix_flag=0;
@@ -1142,14 +1142,14 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag)
} while (prefix_flag);
- if( cpustate->segment_prefix ) {
+ if( m_segment_prefix ) {
// FIXME: the following does not work if both address override and segment override are used
- i386_translate(cpustate, cpustate->segment_override, cpustate->sreg[cpustate->segment_prefix].d ? REG32(ESI) : REG16(SI), -1 );
+ i386_translate(m_segment_override, m_sreg[m_segment_prefix].d ? REG32(ESI) : REG16(SI), -1 );
} else {
//eas =
- i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI), -1 );
+ i386_translate(DS, m_address_size ? REG32(ESI) : REG16(SI), -1 );
}
- i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), -1 );
+ i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), -1 );
switch(opcode)
{
@@ -1184,7 +1184,7 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag)
/* CMPSB, CMPSW, CMPSD */
cycle_base = 5;
cycle_adjustment = -1;
- flag = &cpustate->ZF;
+ flag = &m_ZF;
break;
case 0xac:
@@ -1208,16 +1208,16 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag)
/* SCASB, SCASW, SCASD */
cycle_base = 5;
cycle_adjustment = 0;
- flag = &cpustate->ZF;
+ flag = &m_ZF;
break;
case 0x90:
- CYCLES(cpustate,CYCLES_NOP);
+ CYCLES(CYCLES_NOP);
return;
case 0xc2: // sigh
case 0xc3:
- cpustate->pc--;
+ m_pc--;
return;
default:
@@ -1225,7 +1225,7 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag)
break;
}
- if( cpustate->address_size ) {
+ if( m_address_size ) {
if( REG32(ECX) == 0 )
return;
} else {
@@ -1237,25 +1237,25 @@ static void I386OP(repeat)(i386_state *cpustate, int invert_flag)
CYCLES_NUM(cycle_base);
do
{
- cpustate->eip = repeated_eip;
- cpustate->pc = repeated_pc;
+ m_eip = repeated_eip;
+ m_pc = repeated_pc;
try
{
- I386OP(decode_opcode)(cpustate);
+ i386_decode_opcode();
}
catch (UINT64 e)
{
- cpustate->eip = cpustate->prev_eip;
+ m_eip = m_prev_eip;
throw e;
}
CYCLES_NUM(cycle_adjustment);
- if (cpustate->address_size)
+ if (m_address_size)
count = --REG32(ECX);
else
count = --REG16(CX);
- if (cpustate->cycles <= 0)
+ if (m_cycles <= 0)
goto outofcycles;
}
while( count && (!flag || (invert_flag ? !*flag : *flag)) );
@@ -1267,773 +1267,773 @@ outofcycles:
* time to execute cycles */
if(flag && (invert_flag ? *flag : !*flag))
return;
- cpustate->eip = cpustate->prev_eip;
- CHANGE_PC(cpustate,cpustate->eip);
+ m_eip = m_prev_eip;
+ CHANGE_PC(m_eip);
CYCLES_NUM(-cycle_base);
}
-static void I386OP(rep)(i386_state *cpustate) // Opcode 0xf3
+void i386_device::i386_rep() // Opcode 0xf3
{
- I386OP(repeat)(cpustate, 0);
+ i386_repeat(0);
}
-static void I386OP(repne)(i386_state *cpustate) // Opcode 0xf2
+void i386_device::i386_repne() // Opcode 0xf2
{
- I386OP(repeat)(cpustate, 1);
+ i386_repeat(1);
}
-static void I386OP(sahf)(i386_state *cpustate) // Opcode 0x9e
+void i386_device::i386_sahf() // Opcode 0x9e
{
- set_flags(cpustate, (get_flags(cpustate) & 0xffffff00) | (REG8(AH) & 0xd7) );
- CYCLES(cpustate,CYCLES_SAHF);
+ set_flags((get_flags() & 0xffffff00) | (REG8(AH) & 0xd7) );
+ CYCLES(CYCLES_SAHF);
}
-static void I386OP(sbb_rm8_r8)(i386_state *cpustate) // Opcode 0x18
+void i386_device::i386_sbb_rm8_r8() // Opcode 0x18
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
- dst = SBB8(cpustate, dst, src, cpustate->CF);
+ dst = SBB8(dst, src, m_CF);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
- dst = SBB8(cpustate, dst, src, cpustate->CF);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ8(ea);
+ dst = SBB8(dst, src, m_CF);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(sbb_r8_rm8)(i386_state *cpustate) // Opcode 0x1a
+void i386_device::i386_sbb_r8_rm8() // Opcode 0x1a
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
dst = LOAD_REG8(modrm);
- dst = SBB8(cpustate, dst, src, cpustate->CF);
+ dst = SBB8(dst, src, m_CF);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
dst = LOAD_REG8(modrm);
- dst = SBB8(cpustate, dst, src, cpustate->CF);
+ dst = SBB8(dst, src, m_CF);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(sbb_al_i8)(i386_state *cpustate) // Opcode 0x1c
+void i386_device::i386_sbb_al_i8() // Opcode 0x1c
{
UINT8 src, dst;
- src = FETCH(cpustate);
+ src = FETCH();
dst = REG8(AL);
- dst = SBB8(cpustate, dst, src, cpustate->CF);
+ dst = SBB8(dst, src, m_CF);
REG8(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(scasb)(i386_state *cpustate) // Opcode 0xae
+void i386_device::i386_scasb() // Opcode 0xae
{
UINT32 eas;
UINT8 src, dst;
- eas = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 0 );
- src = READ8(cpustate,eas);
+ eas = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 0 );
+ src = READ8(eas);
dst = REG8(AL);
- SUB8(cpustate,dst, src);
- BUMP_DI(cpustate,1);
- CYCLES(cpustate,CYCLES_SCAS);
+ SUB8(dst, src);
+ BUMP_DI(1);
+ CYCLES(CYCLES_SCAS);
}
-static void I386OP(setalc)(i386_state *cpustate) // Opcode 0xd6 (undocumented)
+void i386_device::i386_setalc() // Opcode 0xd6 (undocumented)
{
- if( cpustate->CF ) {
+ if( m_CF ) {
REG8(AL) = 0xff;
} else {
REG8(AL) = 0;
}
- CYCLES(cpustate,3);
+ CYCLES(3);
}
-static void I386OP(seta_rm8)(i386_state *cpustate) // Opcode 0x0f 97
+void i386_device::i386_seta_rm8() // Opcode 0x0f 97
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->CF == 0 && cpustate->ZF == 0 ) {
+ if( m_CF == 0 && m_ZF == 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setbe_rm8)(i386_state *cpustate) // Opcode 0x0f 96
+void i386_device::i386_setbe_rm8() // Opcode 0x0f 96
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->CF != 0 || cpustate->ZF != 0 ) {
+ if( m_CF != 0 || m_ZF != 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setc_rm8)(i386_state *cpustate) // Opcode 0x0f 92
+void i386_device::i386_setc_rm8() // Opcode 0x0f 92
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->CF != 0 ) {
+ if( m_CF != 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setg_rm8)(i386_state *cpustate) // Opcode 0x0f 9f
+void i386_device::i386_setg_rm8() // Opcode 0x0f 9f
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->ZF == 0 && (cpustate->SF == cpustate->OF) ) {
+ if( m_ZF == 0 && (m_SF == m_OF) ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setge_rm8)(i386_state *cpustate) // Opcode 0x0f 9d
+void i386_device::i386_setge_rm8() // Opcode 0x0f 9d
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if(cpustate->SF == cpustate->OF) {
+ if(m_SF == m_OF) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setl_rm8)(i386_state *cpustate) // Opcode 0x0f 9c
+void i386_device::i386_setl_rm8() // Opcode 0x0f 9c
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->SF != cpustate->OF ) {
+ if( m_SF != m_OF ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setle_rm8)(i386_state *cpustate) // Opcode 0x0f 9e
+void i386_device::i386_setle_rm8() // Opcode 0x0f 9e
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->ZF != 0 || (cpustate->SF != cpustate->OF) ) {
+ if( m_ZF != 0 || (m_SF != m_OF) ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setnc_rm8)(i386_state *cpustate) // Opcode 0x0f 93
+void i386_device::i386_setnc_rm8() // Opcode 0x0f 93
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->CF == 0 ) {
+ if( m_CF == 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setno_rm8)(i386_state *cpustate) // Opcode 0x0f 91
+void i386_device::i386_setno_rm8() // Opcode 0x0f 91
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->OF == 0 ) {
+ if( m_OF == 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setnp_rm8)(i386_state *cpustate) // Opcode 0x0f 9b
+void i386_device::i386_setnp_rm8() // Opcode 0x0f 9b
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->PF == 0 ) {
+ if( m_PF == 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setns_rm8)(i386_state *cpustate) // Opcode 0x0f 99
+void i386_device::i386_setns_rm8() // Opcode 0x0f 99
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->SF == 0 ) {
+ if( m_SF == 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setnz_rm8)(i386_state *cpustate) // Opcode 0x0f 95
+void i386_device::i386_setnz_rm8() // Opcode 0x0f 95
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->ZF == 0 ) {
+ if( m_ZF == 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(seto_rm8)(i386_state *cpustate) // Opcode 0x0f 90
+void i386_device::i386_seto_rm8() // Opcode 0x0f 90
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->OF != 0 ) {
+ if( m_OF != 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setp_rm8)(i386_state *cpustate) // Opcode 0x0f 9a
+void i386_device::i386_setp_rm8() // Opcode 0x0f 9a
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->PF != 0 ) {
+ if( m_PF != 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(sets_rm8)(i386_state *cpustate) // Opcode 0x0f 98
+void i386_device::i386_sets_rm8() // Opcode 0x0f 98
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->SF != 0 ) {
+ if( m_SF != 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(setz_rm8)(i386_state *cpustate) // Opcode 0x0f 94
+void i386_device::i386_setz_rm8() // Opcode 0x0f 94
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 value = 0;
- if( cpustate->ZF != 0 ) {
+ if( m_ZF != 0 ) {
value = 1;
}
if( modrm >= 0xc0 ) {
STORE_RM8(modrm, value);
- CYCLES(cpustate,CYCLES_SETCC_REG);
+ CYCLES(CYCLES_SETCC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- WRITE8(cpustate,ea, value);
- CYCLES(cpustate,CYCLES_SETCC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ WRITE8(ea, value);
+ CYCLES(CYCLES_SETCC_MEM);
}
}
-static void I386OP(stc)(i386_state *cpustate) // Opcode 0xf9
+void i386_device::i386_stc() // Opcode 0xf9
{
- cpustate->CF = 1;
- CYCLES(cpustate,CYCLES_STC);
+ m_CF = 1;
+ CYCLES(CYCLES_STC);
}
-static void I386OP(std)(i386_state *cpustate) // Opcode 0xfd
+void i386_device::i386_std() // Opcode 0xfd
{
- cpustate->DF = 1;
- CYCLES(cpustate,CYCLES_STD);
+ m_DF = 1;
+ CYCLES(CYCLES_STD);
}
-static void I386OP(sti)(i386_state *cpustate) // Opcode 0xfb
+void i386_device::i386_sti() // Opcode 0xfb
{
if(PROTECTED_MODE)
{
- UINT8 IOPL = cpustate->IOP1 | (cpustate->IOP2 << 1);
- if(cpustate->CPL > IOPL)
+ UINT8 IOPL = m_IOP1 | (m_IOP2 << 1);
+ if(m_CPL > IOPL)
FAULT(FAULT_GP,0);
}
- cpustate->delayed_interrupt_enable = 1; // IF is set after the next instruction.
- CYCLES(cpustate,CYCLES_STI);
+ m_delayed_interrupt_enable = 1; // IF is set after the next instruction.
+ CYCLES(CYCLES_STI);
}
-static void I386OP(stosb)(i386_state *cpustate) // Opcode 0xaa
+void i386_device::i386_stosb() // Opcode 0xaa
{
UINT32 ead;
- ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI), 1 );
- WRITE8(cpustate,ead, REG8(AL));
- BUMP_DI(cpustate,1);
- CYCLES(cpustate,CYCLES_STOS);
+ ead = i386_translate(ES, m_address_size ? REG32(EDI) : REG16(DI), 1 );
+ WRITE8(ead, REG8(AL));
+ BUMP_DI(1);
+ CYCLES(CYCLES_STOS);
}
-static void I386OP(sub_rm8_r8)(i386_state *cpustate) // Opcode 0x28
+void i386_device::i386_sub_rm8_r8() // Opcode 0x28
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
- dst = SUB8(cpustate,dst, src);
+ dst = SUB8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
- dst = SUB8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ8(ea);
+ dst = SUB8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(sub_r8_rm8)(i386_state *cpustate) // Opcode 0x2a
+void i386_device::i386_sub_r8_rm8() // Opcode 0x2a
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
dst = LOAD_REG8(modrm);
- dst = SUB8(cpustate,dst, src);
+ dst = SUB8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
dst = LOAD_REG8(modrm);
- dst = SUB8(cpustate,dst, src);
+ dst = SUB8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(sub_al_i8)(i386_state *cpustate) // Opcode 0x2c
+void i386_device::i386_sub_al_i8() // Opcode 0x2c
{
UINT8 src, dst;
- src = FETCH(cpustate);
+ src = FETCH();
dst = REG8(EAX);
- dst = SUB8(cpustate,dst, src);
+ dst = SUB8(dst, src);
REG8(EAX) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(test_al_i8)(i386_state *cpustate) // Opcode 0xa8
+void i386_device::i386_test_al_i8() // Opcode 0xa8
{
- UINT8 src = FETCH(cpustate);
+ UINT8 src = FETCH();
UINT8 dst = REG8(AL);
dst = src & dst;
SetSZPF8(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(test_rm8_r8)(i386_state *cpustate) // Opcode 0x84
+void i386_device::i386_test_rm8_r8() // Opcode 0x84
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
dst = src & dst;
SetSZPF8(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_TEST_REG_REG);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_TEST_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
+ UINT32 ea = GetEA(modrm,0);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
+ dst = READ8(ea);
dst = src & dst;
SetSZPF8(dst);
- cpustate->CF = 0;
- cpustate->OF = 0;
- CYCLES(cpustate,CYCLES_TEST_REG_MEM);
+ m_CF = 0;
+ m_OF = 0;
+ CYCLES(CYCLES_TEST_REG_MEM);
}
}
-static void I386OP(xchg_r8_rm8)(i386_state *cpustate) // Opcode 0x86
+void i386_device::i386_xchg_r8_rm8() // Opcode 0x86
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT8 src = LOAD_RM8(modrm);
UINT8 dst = LOAD_REG8(modrm);
STORE_REG8(modrm, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_XCHG_REG_REG);
+ CYCLES(CYCLES_XCHG_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT8 src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT8 src = READ8(ea);
UINT8 dst = LOAD_REG8(modrm);
- WRITE8(cpustate,ea, dst);
+ WRITE8(ea, dst);
STORE_REG8(modrm, src);
- CYCLES(cpustate,CYCLES_XCHG_REG_MEM);
+ CYCLES(CYCLES_XCHG_REG_MEM);
}
}
-static void I386OP(xor_rm8_r8)(i386_state *cpustate) // Opcode 0x30
+void i386_device::i386_xor_rm8_r8() // Opcode 0x30
{
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_REG8(modrm);
dst = LOAD_RM8(modrm);
- dst = XOR8(cpustate,dst, src);
+ dst = XOR8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
+ UINT32 ea = GetEA(modrm,1);
src = LOAD_REG8(modrm);
- dst = READ8(cpustate,ea);
- dst = XOR8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ dst = READ8(ea);
+ dst = XOR8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
}
-static void I386OP(xor_r8_rm8)(i386_state *cpustate) // Opcode 0x32
+void i386_device::i386_xor_r8_rm8() // Opcode 0x32
{
UINT32 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
dst = LOAD_REG8(modrm);
- dst = XOR8(cpustate,dst, src);
+ dst = XOR8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
dst = LOAD_REG8(modrm);
- dst = XOR8(cpustate,dst, src);
+ dst = XOR8(dst, src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_MEM_REG);
+ CYCLES(CYCLES_ALU_MEM_REG);
}
}
-static void I386OP(xor_al_i8)(i386_state *cpustate) // Opcode 0x34
+void i386_device::i386_xor_al_i8() // Opcode 0x34
{
UINT8 src, dst;
- src = FETCH(cpustate);
+ src = FETCH();
dst = REG8(AL);
- dst = XOR8(cpustate,dst, src);
+ dst = XOR8(dst, src);
REG8(AL) = dst;
- CYCLES(cpustate,CYCLES_ALU_IMM_ACC);
+ CYCLES(CYCLES_ALU_IMM_ACC);
}
-static void I386OP(group80_8)(i386_state *cpustate) // Opcode 0x80
+void i386_device::i386_group80_8() // Opcode 0x80
{
UINT32 ea;
UINT8 src, dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: // ADD Rm8, i8
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- src = FETCH(cpustate);
- dst = ADD8(cpustate,dst, src);
+ src = FETCH();
+ dst = ADD8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- dst = READ8(cpustate,ea);
- src = FETCH(cpustate);
- dst = ADD8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,0);
+ dst = READ8(ea);
+ src = FETCH();
+ dst = ADD8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 1: // OR Rm8, i8
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- src = FETCH(cpustate);
- dst = OR8(cpustate,dst, src);
+ src = FETCH();
+ dst = OR8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- src = FETCH(cpustate);
- dst = OR8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ src = FETCH();
+ dst = OR8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 2: // ADC Rm8, i8
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- src = FETCH(cpustate);
- dst = ADC8(cpustate, dst, src, cpustate->CF);
+ src = FETCH();
+ dst = ADC8(dst, src, m_CF);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- src = FETCH(cpustate);
- dst = ADC8(cpustate, dst, src, cpustate->CF);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ src = FETCH();
+ dst = ADC8(dst, src, m_CF);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 3: // SBB Rm8, i8
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- src = FETCH(cpustate);
- dst = SBB8(cpustate, dst, src, cpustate->CF);
+ src = FETCH();
+ dst = SBB8(dst, src, m_CF);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- src = FETCH(cpustate);
- dst = SBB8(cpustate, dst, src, cpustate->CF);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ src = FETCH();
+ dst = SBB8(dst, src, m_CF);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 4: // AND Rm8, i8
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- src = FETCH(cpustate);
- dst = AND8(cpustate,dst, src);
+ src = FETCH();
+ dst = AND8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- src = FETCH(cpustate);
- dst = AND8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ src = FETCH();
+ dst = AND8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 5: // SUB Rm8, i8
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- src = FETCH(cpustate);
- dst = SUB8(cpustate,dst, src);
+ src = FETCH();
+ dst = SUB8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- src = FETCH(cpustate);
- dst = SUB8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ src = FETCH();
+ dst = SUB8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 6: // XOR Rm8, i8
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- src = FETCH(cpustate);
- dst = XOR8(cpustate,dst, src);
+ src = FETCH();
+ dst = XOR8(dst, src);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_REG);
+ CYCLES(CYCLES_ALU_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- src = FETCH(cpustate);
- dst = XOR8(cpustate,dst, src);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_ALU_REG_MEM);
+ ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ src = FETCH();
+ dst = XOR8(dst, src);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_ALU_REG_MEM);
}
break;
case 7: // CMP Rm8, i8
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- src = FETCH(cpustate);
- SUB8(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_REG);
+ src = FETCH();
+ SUB8(dst, src);
+ CYCLES(CYCLES_CMP_REG_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- dst = READ8(cpustate,ea);
- src = FETCH(cpustate);
- SUB8(cpustate,dst, src);
- CYCLES(cpustate,CYCLES_CMP_REG_MEM);
+ ea = GetEA(modrm,0);
+ dst = READ8(ea);
+ src = FETCH();
+ SUB8(dst, src);
+ CYCLES(CYCLES_CMP_REG_MEM);
}
break;
}
}
-static void I386OP(groupC0_8)(i386_state *cpustate) // Opcode 0xc0
+void i386_device::i386_groupC0_8() // Opcode 0xc0
{
UINT8 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 shift;
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- shift = FETCH(cpustate) & 0x1f;
- dst = i386_shift_rotate8(cpustate, modrm, dst, shift);
+ shift = FETCH() & 0x1f;
+ dst = i386_shift_rotate8(modrm, dst, shift);
STORE_RM8(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- shift = FETCH(cpustate) & 0x1f;
- dst = i386_shift_rotate8(cpustate, modrm, dst, shift);
- WRITE8(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ shift = FETCH() & 0x1f;
+ dst = i386_shift_rotate8(modrm, dst, shift);
+ WRITE8(ea, dst);
}
}
-static void I386OP(groupD0_8)(i386_state *cpustate) // Opcode 0xd0
+void i386_device::i386_groupD0_8() // Opcode 0xd0
{
UINT8 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- dst = i386_shift_rotate8(cpustate, modrm, dst, 1);
+ dst = i386_shift_rotate8(modrm, dst, 1);
STORE_RM8(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- dst = i386_shift_rotate8(cpustate, modrm, dst, 1);
- WRITE8(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ dst = i386_shift_rotate8(modrm, dst, 1);
+ WRITE8(ea, dst);
}
}
-static void I386OP(groupD2_8)(i386_state *cpustate) // Opcode 0xd2
+void i386_device::i386_groupD2_8() // Opcode 0xd2
{
UINT8 dst;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
dst = LOAD_RM8(modrm);
- dst = i386_shift_rotate8(cpustate, modrm, dst, REG8(CL));
+ dst = i386_shift_rotate8(modrm, dst, REG8(CL));
STORE_RM8(modrm, dst);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- dst = READ8(cpustate,ea);
- dst = i386_shift_rotate8(cpustate, modrm, dst, REG8(CL));
- WRITE8(cpustate,ea, dst);
+ UINT32 ea = GetEA(modrm,1);
+ dst = READ8(ea);
+ dst = i386_shift_rotate8(modrm, dst, REG8(CL));
+ WRITE8(ea, dst);
}
}
-static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
+void i386_device::i386_groupF6_8() // Opcode 0xf6
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: /* TEST Rm8, i8 */
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
- UINT8 src = FETCH(cpustate);
+ UINT8 src = FETCH();
dst &= src;
- cpustate->CF = cpustate->OF = cpustate->AF = 0;
+ m_CF = m_OF = m_AF = 0;
SetSZPF8(dst);
- CYCLES(cpustate,CYCLES_TEST_IMM_REG);
+ CYCLES(CYCLES_TEST_IMM_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT8 dst = READ8(cpustate,ea);
- UINT8 src = FETCH(cpustate);
+ UINT32 ea = GetEA(modrm,0);
+ UINT8 dst = READ8(ea);
+ UINT8 src = FETCH();
dst &= src;
- cpustate->CF = cpustate->OF = cpustate->AF = 0;
+ m_CF = m_OF = m_AF = 0;
SetSZPF8(dst);
- CYCLES(cpustate,CYCLES_TEST_IMM_MEM);
+ CYCLES(CYCLES_TEST_IMM_MEM);
}
break;
case 2: /* NOT Rm8 */
@@ -2041,27 +2041,27 @@ static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
UINT8 dst = LOAD_RM8(modrm);
dst = ~dst;
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_NOT_REG);
+ CYCLES(CYCLES_NOT_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT8 dst = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT8 dst = READ8(ea);
dst = ~dst;
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_NOT_MEM);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_NOT_MEM);
}
break;
case 3: /* NEG Rm8 */
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
- dst = SUB8(cpustate, 0, dst );
+ dst = SUB8(0, dst );
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_NEG_REG);
+ CYCLES(CYCLES_NEG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT8 dst = READ8(cpustate,ea);
- dst = SUB8(cpustate, 0, dst );
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_NEG_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT8 dst = READ8(ea);
+ dst = SUB8(0, dst );
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_NEG_MEM);
}
break;
case 4: /* MUL AL, Rm8 */
@@ -2070,18 +2070,18 @@ static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
UINT8 src, dst;
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
- CYCLES(cpustate,CYCLES_MUL8_ACC_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_MUL8_ACC_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
- CYCLES(cpustate,CYCLES_MUL8_ACC_MEM); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
+ CYCLES(CYCLES_MUL8_ACC_MEM); /* TODO: Correct multiply timing */
}
dst = REG8(AL);
result = (UINT16)src * (UINT16)dst;
REG16(AX) = (UINT16)result;
- cpustate->CF = cpustate->OF = (REG16(AX) > 0xff);
+ m_CF = m_OF = (REG16(AX) > 0xff);
}
break;
case 5: /* IMUL AL, Rm8 */
@@ -2090,11 +2090,11 @@ static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
INT16 src, dst;
if( modrm >= 0xc0 ) {
src = (INT16)(INT8)LOAD_RM8(modrm);
- CYCLES(cpustate,CYCLES_IMUL8_ACC_REG); /* TODO: Correct multiply timing */
+ CYCLES(CYCLES_IMUL8_ACC_REG); /* TODO: Correct multiply timing */
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = (INT16)(INT8)READ8(cpustate,ea);
- CYCLES(cpustate,CYCLES_IMUL8_ACC_MEM); /* TODO: Correct multiply timing */
+ UINT32 ea = GetEA(modrm,0);
+ src = (INT16)(INT8)READ8(ea);
+ CYCLES(CYCLES_IMUL8_ACC_MEM); /* TODO: Correct multiply timing */
}
dst = (INT16)(INT8)REG8(AL);
@@ -2102,7 +2102,7 @@ static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
REG16(AX) = (UINT16)result;
- cpustate->CF = cpustate->OF = !(result == (INT16)(INT8)result);
+ m_CF = m_OF = !(result == (INT16)(INT8)result);
}
break;
case 6: /* DIV AL, Rm8 */
@@ -2111,11 +2111,11 @@ static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
UINT8 src;
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
- CYCLES(cpustate,CYCLES_DIV8_ACC_REG);
+ CYCLES(CYCLES_DIV8_ACC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
- CYCLES(cpustate,CYCLES_DIV8_ACC_MEM);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
+ CYCLES(CYCLES_DIV8_ACC_MEM);
}
quotient = (UINT16)REG16(AX);
@@ -2129,11 +2129,11 @@ static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
REG8(AL) = (UINT8)result & 0xff;
// this flag is actually undefined, enable on non-cyrix
- if (cpustate->cpuid_id0 != 0x69727943)
- cpustate->CF = 1;
+ if (m_cpuid_id0 != 0x69727943)
+ m_CF = 1;
}
} else {
- i386_trap(cpustate, 0, 0, 0);
+ i386_trap(0, 0, 0);
}
}
break;
@@ -2143,11 +2143,11 @@ static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
UINT8 src;
if( modrm >= 0xc0 ) {
src = LOAD_RM8(modrm);
- CYCLES(cpustate,CYCLES_IDIV8_ACC_REG);
+ CYCLES(CYCLES_IDIV8_ACC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ8(cpustate,ea);
- CYCLES(cpustate,CYCLES_IDIV8_ACC_MEM);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ8(ea);
+ CYCLES(CYCLES_IDIV8_ACC_MEM);
}
quotient = (INT16)REG16(AX);
@@ -2161,49 +2161,49 @@ static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6
REG8(AL) = (UINT8)result & 0xff;
// this flag is actually undefined, enable on non-cyrix
- if (cpustate->cpuid_id0 != 0x69727943)
- cpustate->CF = 1;
+ if (m_cpuid_id0 != 0x69727943)
+ m_CF = 1;
}
} else {
- i386_trap(cpustate, 0, 0, 0);
+ i386_trap(0, 0, 0);
}
}
break;
}
}
-static void I386OP(groupFE_8)(i386_state *cpustate) // Opcode 0xfe
+void i386_device::i386_groupFE_8() // Opcode 0xfe
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
switch( (modrm >> 3) & 0x7 )
{
case 0: /* INC Rm8 */
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
- dst = INC8(cpustate,dst);
+ dst = INC8(dst);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_INC_REG);
+ CYCLES(CYCLES_INC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT8 dst = READ8(cpustate,ea);
- dst = INC8(cpustate,dst);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_INC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT8 dst = READ8(ea);
+ dst = INC8(dst);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_INC_MEM);
}
break;
case 1: /* DEC Rm8 */
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
- dst = DEC8(cpustate,dst);
+ dst = DEC8(dst);
STORE_RM8(modrm, dst);
- CYCLES(cpustate,CYCLES_DEC_REG);
+ CYCLES(CYCLES_DEC_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT8 dst = READ8(cpustate,ea);
- dst = DEC8(cpustate,dst);
- WRITE8(cpustate,ea, dst);
- CYCLES(cpustate,CYCLES_DEC_MEM);
+ UINT32 ea = GetEA(modrm,1);
+ UINT8 dst = READ8(ea);
+ dst = DEC8(dst);
+ WRITE8(ea, dst);
+ CYCLES(CYCLES_DEC_MEM);
}
break;
case 6: /* PUSH Rm8*/
@@ -2212,172 +2212,172 @@ static void I386OP(groupFE_8)(i386_state *cpustate) // Opcode 0xfe
if( modrm >= 0xc0 ) {
value = LOAD_RM8(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- value = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ value = READ8(ea);
}
- if( cpustate->operand_size ) {
- PUSH32(cpustate,value);
+ if( m_operand_size ) {
+ PUSH32(value);
} else {
- PUSH16(cpustate,value);
+ PUSH16(value);
}
- CYCLES(cpustate,CYCLES_PUSH_RM);
+ CYCLES(CYCLES_PUSH_RM);
}
break;
default:
- report_invalid_modrm(cpustate, "groupFE_8", modrm);
+ report_invalid_modrm("groupFE_8", modrm);
break;
}
}
-static void I386OP(segment_CS)(i386_state *cpustate) // Opcode 0x2e
+void i386_device::i386_segment_CS() // Opcode 0x2e
{
- cpustate->segment_prefix = 1;
- cpustate->segment_override = CS;
+ m_segment_prefix = 1;
+ m_segment_override = CS;
- I386OP(decode_opcode)(cpustate);
+ i386_decode_opcode();
}
-static void I386OP(segment_DS)(i386_state *cpustate) // Opcode 0x3e
+void i386_device::i386_segment_DS() // Opcode 0x3e
{
- cpustate->segment_prefix = 1;
- cpustate->segment_override = DS;
- CYCLES(cpustate,0); // TODO: Specify cycle count
- I386OP(decode_opcode)(cpustate);
+ m_segment_prefix = 1;
+ m_segment_override = DS;
+ CYCLES(0); // TODO: Specify cycle count
+ i386_decode_opcode();
}
-static void I386OP(segment_ES)(i386_state *cpustate) // Opcode 0x26
+void i386_device::i386_segment_ES() // Opcode 0x26
{
- cpustate->segment_prefix = 1;
- cpustate->segment_override = ES;
- CYCLES(cpustate,0); // TODO: Specify cycle count
- I386OP(decode_opcode)(cpustate);
+ m_segment_prefix = 1;
+ m_segment_override = ES;
+ CYCLES(0); // TODO: Specify cycle count
+ i386_decode_opcode();
}
-static void I386OP(segment_FS)(i386_state *cpustate) // Opcode 0x64
+void i386_device::i386_segment_FS() // Opcode 0x64
{
- cpustate->segment_prefix = 1;
- cpustate->segment_override = FS;
- CYCLES(cpustate,1); // TODO: Specify cycle count
- I386OP(decode_opcode)(cpustate);
+ m_segment_prefix = 1;
+ m_segment_override = FS;
+ CYCLES(1); // TODO: Specify cycle count
+ i386_decode_opcode();
}
-static void I386OP(segment_GS)(i386_state *cpustate) // Opcode 0x65
+void i386_device::i386_segment_GS() // Opcode 0x65
{
- cpustate->segment_prefix = 1;
- cpustate->segment_override = GS;
- CYCLES(cpustate,1); // TODO: Specify cycle count
- I386OP(decode_opcode)(cpustate);
+ m_segment_prefix = 1;
+ m_segment_override = GS;
+ CYCLES(1); // TODO: Specify cycle count
+ i386_decode_opcode();
}
-static void I386OP(segment_SS)(i386_state *cpustate) // Opcode 0x36
+void i386_device::i386_segment_SS() // Opcode 0x36
{
- cpustate->segment_prefix = 1;
- cpustate->segment_override = SS;
- CYCLES(cpustate,0); // TODO: Specify cycle count
- I386OP(decode_opcode)(cpustate);
+ m_segment_prefix = 1;
+ m_segment_override = SS;
+ CYCLES(0); // TODO: Specify cycle count
+ i386_decode_opcode();
}
-static void I386OP(operand_size)(i386_state *cpustate) // Opcode prefix 0x66
+void i386_device::i386_operand_size() // Opcode prefix 0x66
{
- if(cpustate->operand_prefix == 0)
+ if(m_operand_prefix == 0)
{
- cpustate->operand_size ^= 1;
- cpustate->operand_prefix = 1;
+ m_operand_size ^= 1;
+ m_operand_prefix = 1;
}
- cpustate->opcode = FETCH(cpustate);
- if (cpustate->opcode == 0x0f)
- I386OP(decode_three_byte66)(cpustate);
+ m_opcode = FETCH();
+ if (m_opcode == 0x0f)
+ i386_decode_three_byte66();
else
{
- if( cpustate->operand_size )
- cpustate->opcode_table1_32[cpustate->opcode](cpustate);
+ if( m_operand_size )
+ (this->*m_opcode_table1_32[m_opcode])();
else
- cpustate->opcode_table1_16[cpustate->opcode](cpustate);
+ (this->*m_opcode_table1_16[m_opcode])();
}
}
-static void I386OP(address_size)(i386_state *cpustate) // Opcode 0x67
+void i386_device::i386_address_size() // Opcode 0x67
{
- if(cpustate->address_prefix == 0)
+ if(m_address_prefix == 0)
{
- cpustate->address_size ^= 1;
- cpustate->address_prefix = 1;
+ m_address_size ^= 1;
+ m_address_prefix = 1;
}
- I386OP(decode_opcode)(cpustate);
+ i386_decode_opcode();
}
-static void I386OP(nop)(i386_state *cpustate) // Opcode 0x90
+void i386_device::i386_nop() // Opcode 0x90
{
- CYCLES(cpustate,CYCLES_NOP);
+ CYCLES(CYCLES_NOP);
}
-static void I386OP(int3)(i386_state *cpustate) // Opcode 0xcc
+void i386_device::i386_int3() // Opcode 0xcc
{
- CYCLES(cpustate,CYCLES_INT3);
- cpustate->ext = 0; // not an external interrupt
- i386_trap(cpustate,3, 1, 0);
- cpustate->ext = 1;
+ CYCLES(CYCLES_INT3);
+ m_ext = 0; // not an external interrupt
+ i386_trap(3, 1, 0);
+ m_ext = 1;
}
-static void I386OP(int)(i386_state *cpustate) // Opcode 0xcd
+void i386_device::i386_int() // Opcode 0xcd
{
- int interrupt = FETCH(cpustate);
- CYCLES(cpustate,CYCLES_INT);
- cpustate->ext = 0; // not an external interrupt
- i386_trap(cpustate,interrupt, 1, 0);
- cpustate->ext = 1;
+ int interrupt = FETCH();
+ CYCLES(CYCLES_INT);
+ m_ext = 0; // not an external interrupt
+ i386_trap(interrupt, 1, 0);
+ m_ext = 1;
}
-static void I386OP(into)(i386_state *cpustate) // Opcode 0xce
+void i386_device::i386_into() // Opcode 0xce
{
- if( cpustate->OF ) {
- cpustate->ext = 0;
- i386_trap(cpustate,4, 1, 0);
- cpustate->ext = 1;
- CYCLES(cpustate,CYCLES_INTO_OF1);
+ if( m_OF ) {
+ m_ext = 0;
+ i386_trap(4, 1, 0);
+ m_ext = 1;
+ CYCLES(CYCLES_INTO_OF1);
}
else
{
- CYCLES(cpustate,CYCLES_INTO_OF0);
+ CYCLES(CYCLES_INTO_OF0);
}
}
static UINT32 i386_escape_ea; // hack around GCC 4.6 error because we need the side effects of GetEA()
-static void I386OP(escape)(i386_state *cpustate) // Opcodes 0xd8 - 0xdf
+void i386_device::i386_escape() // Opcodes 0xd8 - 0xdf
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if(modrm < 0xc0)
{
- i386_escape_ea = GetEA(cpustate,modrm,0);
+ i386_escape_ea = GetEA(modrm,0);
}
- CYCLES(cpustate,3); // TODO: confirm this
+ CYCLES(3); // TODO: confirm this
(void) LOAD_RM8(modrm);
}
-static void I386OP(hlt)(i386_state *cpustate) // Opcode 0xf4
+void i386_device::i386_hlt() // Opcode 0xf4
{
- if(PROTECTED_MODE && cpustate->CPL != 0)
+ if(PROTECTED_MODE && m_CPL != 0)
FAULT(FAULT_GP,0);
- cpustate->halted = 1;
- CYCLES(cpustate,CYCLES_HLT);
- if (cpustate->cycles > 0)
- cpustate->cycles = 0;
+ m_halted = 1;
+ CYCLES(CYCLES_HLT);
+ if (m_cycles > 0)
+ m_cycles = 0;
}
-static void I386OP(decimal_adjust)(i386_state *cpustate, int direction)
+void i386_device::i386_decimal_adjust(int direction)
{
UINT8 tmpAL = REG8(AL);
- UINT8 tmpCF = cpustate->CF;
+ UINT8 tmpCF = m_CF;
- if (cpustate->AF || ((REG8(AL) & 0xf) > 9))
+ if (m_AF || ((REG8(AL) & 0xf) > 9))
{
UINT16 t= (UINT16)REG8(AL) + (direction * 0x06);
REG8(AL) = (UINT8)t&0xff;
- cpustate->AF = 1;
+ m_AF = 1;
if (t & 0x100)
- cpustate->CF = 1;
+ m_CF = 1;
if (direction > 0)
tmpAL = REG8(AL);
}
@@ -2385,152 +2385,152 @@ static void I386OP(decimal_adjust)(i386_state *cpustate, int direction)
if (tmpCF || (tmpAL > 0x99))
{
REG8(AL) += (direction * 0x60);
- cpustate->CF = 1;
+ m_CF = 1;
}
SetSZPF8(REG8(AL));
}
-static void I386OP(daa)(i386_state *cpustate) // Opcode 0x27
+void i386_device::i386_daa() // Opcode 0x27
{
- I386OP(decimal_adjust)(cpustate, +1);
- CYCLES(cpustate,CYCLES_DAA);
+ i386_decimal_adjust(+1);
+ CYCLES(CYCLES_DAA);
}
-static void I386OP(das)(i386_state *cpustate) // Opcode 0x2f
+void i386_device::i386_das() // Opcode 0x2f
{
- I386OP(decimal_adjust)(cpustate, -1);
- CYCLES(cpustate,CYCLES_DAS);
+ i386_decimal_adjust(-1);
+ CYCLES(CYCLES_DAS);
}
-static void I386OP(aaa)(i386_state *cpustate) // Opcode 0x37
+void i386_device::i386_aaa() // Opcode 0x37
{
- if( ( (REG8(AL) & 0x0f) > 9) || (cpustate->AF != 0) ) {
+ if( ( (REG8(AL) & 0x0f) > 9) || (m_AF != 0) ) {
REG16(AX) = REG16(AX) + 6;
REG8(AH) = REG8(AH) + 1;
- cpustate->AF = 1;
- cpustate->CF = 1;
+ m_AF = 1;
+ m_CF = 1;
} else {
- cpustate->AF = 0;
- cpustate->CF = 0;
+ m_AF = 0;
+ m_CF = 0;
}
REG8(AL) = REG8(AL) & 0x0f;
- CYCLES(cpustate,CYCLES_AAA);
+ CYCLES(CYCLES_AAA);
}
-static void I386OP(aas)(i386_state *cpustate) // Opcode 0x3f
+void i386_device::i386_aas() // Opcode 0x3f
{
- if (cpustate->AF || ((REG8(AL) & 0xf) > 9))
+ if (m_AF || ((REG8(AL) & 0xf) > 9))
{
REG16(AX) -= 6;
REG8(AH) -= 1;
- cpustate->AF = 1;
- cpustate->CF = 1;
+ m_AF = 1;
+ m_CF = 1;
}
else
{
- cpustate->AF = 0;
- cpustate->CF = 0;
+ m_AF = 0;
+ m_CF = 0;
}
REG8(AL) &= 0x0f;
- CYCLES(cpustate,CYCLES_AAS);
+ CYCLES(CYCLES_AAS);
}
-static void I386OP(aad)(i386_state *cpustate) // Opcode 0xd5
+void i386_device::i386_aad() // Opcode 0xd5
{
UINT8 tempAL = REG8(AL);
UINT8 tempAH = REG8(AH);
- UINT8 i = FETCH(cpustate);
+ UINT8 i = FETCH();
REG8(AL) = (tempAL + (tempAH * i)) & 0xff;
REG8(AH) = 0;
SetSZPF8( REG8(AL) );
- CYCLES(cpustate,CYCLES_AAD);
+ CYCLES(CYCLES_AAD);
}
-static void I386OP(aam)(i386_state *cpustate) // Opcode 0xd4
+void i386_device::i386_aam() // Opcode 0xd4
{
UINT8 tempAL = REG8(AL);
- UINT8 i = FETCH(cpustate);
+ UINT8 i = FETCH();
if(!i)
{
- i386_trap(cpustate, 0, 0, 0);
+ i386_trap(0, 0, 0);
return;
}
REG8(AH) = tempAL / i;
REG8(AL) = tempAL % i;
SetSZPF8( REG8(AL) );
- CYCLES(cpustate,CYCLES_AAM);
+ CYCLES(CYCLES_AAM);
}
-static void I386OP(clts)(i386_state *cpustate) // Opcode 0x0f 0x06
+void i386_device::i386_clts() // Opcode 0x0f 0x06
{
// Privileged instruction, CPL must be zero. Can be used in real or v86 mode.
- if(PROTECTED_MODE && cpustate->CPL != 0)
+ if(PROTECTED_MODE && m_CPL != 0)
FAULT(FAULT_GP,0)
- cpustate->cr[0] &= ~0x08; /* clear TS bit */
- CYCLES(cpustate,CYCLES_CLTS);
+ m_cr[0] &= ~0x08; /* clear TS bit */
+ CYCLES(CYCLES_CLTS);
}
-static void I386OP(wait)(i386_state *cpustate) // Opcode 0x9B
+void i386_device::i386_wait() // Opcode 0x9B
{
// TODO
}
-static void I386OP(lock)(i386_state *cpustate) // Opcode 0xf0
+void i386_device::i386_lock() // Opcode 0xf0
{
// lock doesn't depend on iopl on 386
// TODO: lock causes UD on unlockable opcodes
- CYCLES(cpustate,CYCLES_LOCK); // TODO: Determine correct cycle count
- I386OP(decode_opcode)(cpustate);
+ CYCLES(CYCLES_LOCK); // TODO: Determine correct cycle count
+ i386_decode_opcode();
}
-static void I386OP(mov_r32_tr)(i386_state *cpustate) // Opcode 0x0f 24
+void i386_device::i386_mov_r32_tr() // Opcode 0x0f 24
{
- FETCH(cpustate);
- CYCLES(cpustate,1); // TODO: correct cycle count
+ FETCH();
+ CYCLES(1); // TODO: correct cycle count
}
-static void I386OP(mov_tr_r32)(i386_state *cpustate) // Opcode 0x0f 26
+void i386_device::i386_mov_tr_r32() // Opcode 0x0f 26
{
- FETCH(cpustate);
- CYCLES(cpustate,1); // TODO: correct cycle count
+ FETCH();
+ CYCLES(1); // TODO: correct cycle count
}
-static void I386OP(loadall)(i386_state *cpustate) // Opcode 0x0f 0x07 (0x0f 0x05 on 80286), undocumented
+void i386_device::i386_loadall() // Opcode 0x0f 0x07 (0x0f 0x05 on 80286), undocumented
{
- fatalerror("i386: LOADALL unimplemented at %08X\n", cpustate->pc - 1);
+ fatalerror("i386: LOADALL unimplemented at %08X\n", m_pc - 1);
}
-static void I386OP(invalid)(i386_state *cpustate)
+void i386_device::i386_invalid()
{
- report_invalid_opcode(cpustate);
- i386_trap(cpustate, 6, 0, 0);
+ report_invalid_opcode();
+ i386_trap(6, 0, 0);
}
-static void I386OP(xlat)(i386_state *cpustate) // Opcode 0xd7
+void i386_device::i386_xlat() // Opcode 0xd7
{
UINT32 ea;
- if( cpustate->segment_prefix ) {
- if(!cpustate->address_size)
+ if( m_segment_prefix ) {
+ if(!m_address_size)
{
- ea = i386_translate(cpustate, cpustate->segment_override, REG16(BX) + REG8(AL), 0 );
+ ea = i386_translate(m_segment_override, REG16(BX) + REG8(AL), 0 );
}
else
{
- ea = i386_translate(cpustate, cpustate->segment_override, REG32(EBX) + REG8(AL), 0 );
+ ea = i386_translate(m_segment_override, REG32(EBX) + REG8(AL), 0 );
}
} else {
- if(!cpustate->address_size)
+ if(!m_address_size)
{
- ea = i386_translate(cpustate, DS, REG16(BX) + REG8(AL), 0 );
+ ea = i386_translate(DS, REG16(BX) + REG8(AL), 0 );
}
else
{
- ea = i386_translate(cpustate, DS, REG32(EBX) + REG8(AL), 0 );
+ ea = i386_translate(DS, REG32(EBX) + REG8(AL), 0 );
}
}
- REG8(AL) = READ8(cpustate,ea);
- CYCLES(cpustate,CYCLES_XLAT);
+ REG8(AL) = READ8(ea);
+ CYCLES(CYCLES_XLAT);
}
diff --git a/src/emu/cpu/i386/i386ops.h b/src/emu/cpu/i386/i386ops.h
index 60996c6cd8b..a30124b3132 100644
--- a/src/emu/cpu/i386/i386ops.h
+++ b/src/emu/cpu/i386/i386ops.h
@@ -1,9 +1,3 @@
-struct X86_OPCODE {
- UINT8 opcode;
- UINT32 flags;
- void (*handler16)(i386_state *cpustate);
- void (*handler32)(i386_state *cpustate);
-};
#define OP_I386 0x1
#define OP_FPU 0x2
@@ -20,513 +14,513 @@ struct X86_OPCODE {
#define OP_3BYTEF2 0x20000000
#define OP_3BYTEF3 0x10000000
-static const X86_OPCODE x86_opcode_table[] =
+const i386_device::X86_OPCODE i386_device::s_x86_opcode_table[] =
{
// Opcode Flags 16-bit handler 32-bit handler
- { 0x00, OP_I386, I386OP(add_rm8_r8), I386OP(add_rm8_r8), },
- { 0x01, OP_I386, I386OP(add_rm16_r16), I386OP(add_rm32_r32), },
- { 0x02, OP_I386, I386OP(add_r8_rm8), I386OP(add_r8_rm8), },
- { 0x03, OP_I386, I386OP(add_r16_rm16), I386OP(add_r32_rm32), },
- { 0x04, OP_I386, I386OP(add_al_i8), I386OP(add_al_i8), },
- { 0x05, OP_I386, I386OP(add_ax_i16), I386OP(add_eax_i32), },
- { 0x06, OP_I386, I386OP(push_es16), I386OP(push_es32), },
- { 0x07, OP_I386, I386OP(pop_es16), I386OP(pop_es32), },
- { 0x08, OP_I386, I386OP(or_rm8_r8), I386OP(or_rm8_r8), },
- { 0x09, OP_I386, I386OP(or_rm16_r16), I386OP(or_rm32_r32), },
- { 0x0A, OP_I386, I386OP(or_r8_rm8), I386OP(or_r8_rm8), },
- { 0x0B, OP_I386, I386OP(or_r16_rm16), I386OP(or_r32_rm32), },
- { 0x0C, OP_I386, I386OP(or_al_i8), I386OP(or_al_i8), },
- { 0x0D, OP_I386, I386OP(or_ax_i16), I386OP(or_eax_i32), },
- { 0x0E, OP_I386, I386OP(push_cs16), I386OP(push_cs32), },
- { 0x0F, OP_I386, I386OP(decode_two_byte), I386OP(decode_two_byte), },
- { 0x10, OP_I386, I386OP(adc_rm8_r8), I386OP(adc_rm8_r8), },
- { 0x11, OP_I386, I386OP(adc_rm16_r16), I386OP(adc_rm32_r32), },
- { 0x12, OP_I386, I386OP(adc_r8_rm8), I386OP(adc_r8_rm8), },
- { 0x13, OP_I386, I386OP(adc_r16_rm16), I386OP(adc_r32_rm32), },
- { 0x14, OP_I386, I386OP(adc_al_i8), I386OP(adc_al_i8), },
- { 0x15, OP_I386, I386OP(adc_ax_i16), I386OP(adc_eax_i32), },
- { 0x16, OP_I386, I386OP(push_ss16), I386OP(push_ss32), },
- { 0x17, OP_I386, I386OP(pop_ss16), I386OP(pop_ss32), },
- { 0x18, OP_I386, I386OP(sbb_rm8_r8), I386OP(sbb_rm8_r8), },
- { 0x19, OP_I386, I386OP(sbb_rm16_r16), I386OP(sbb_rm32_r32), },
- { 0x1A, OP_I386, I386OP(sbb_r8_rm8), I386OP(sbb_r8_rm8), },
- { 0x1B, OP_I386, I386OP(sbb_r16_rm16), I386OP(sbb_r32_rm32), },
- { 0x1C, OP_I386, I386OP(sbb_al_i8), I386OP(sbb_al_i8), },
- { 0x1D, OP_I386, I386OP(sbb_ax_i16), I386OP(sbb_eax_i32), },
- { 0x1E, OP_I386, I386OP(push_ds16), I386OP(push_ds32), },
- { 0x1F, OP_I386, I386OP(pop_ds16), I386OP(pop_ds32), },
- { 0x20, OP_I386, I386OP(and_rm8_r8), I386OP(and_rm8_r8), },
- { 0x21, OP_I386, I386OP(and_rm16_r16), I386OP(and_rm32_r32), },
- { 0x22, OP_I386, I386OP(and_r8_rm8), I386OP(and_r8_rm8), },
- { 0x23, OP_I386, I386OP(and_r16_rm16), I386OP(and_r32_rm32), },
- { 0x24, OP_I386, I386OP(and_al_i8), I386OP(and_al_i8), },
- { 0x25, OP_I386, I386OP(and_ax_i16), I386OP(and_eax_i32), },
- { 0x26, OP_I386, I386OP(segment_ES), I386OP(segment_ES), },
- { 0x27, OP_I386, I386OP(daa), I386OP(daa), },
- { 0x28, OP_I386, I386OP(sub_rm8_r8), I386OP(sub_rm8_r8), },
- { 0x29, OP_I386, I386OP(sub_rm16_r16), I386OP(sub_rm32_r32), },
- { 0x2A, OP_I386, I386OP(sub_r8_rm8), I386OP(sub_r8_rm8), },
- { 0x2B, OP_I386, I386OP(sub_r16_rm16), I386OP(sub_r32_rm32), },
- { 0x2C, OP_I386, I386OP(sub_al_i8), I386OP(sub_al_i8), },
- { 0x2D, OP_I386, I386OP(sub_ax_i16), I386OP(sub_eax_i32), },
- { 0x2E, OP_I386, I386OP(segment_CS), I386OP(segment_CS), },
- { 0x2F, OP_I386, I386OP(das), I386OP(das), },
- { 0x30, OP_I386, I386OP(xor_rm8_r8), I386OP(xor_rm8_r8), },
- { 0x31, OP_I386, I386OP(xor_rm16_r16), I386OP(xor_rm32_r32), },
- { 0x32, OP_I386, I386OP(xor_r8_rm8), I386OP(xor_r8_rm8), },
- { 0x33, OP_I386, I386OP(xor_r16_rm16), I386OP(xor_r32_rm32), },
- { 0x34, OP_I386, I386OP(xor_al_i8), I386OP(xor_al_i8), },
- { 0x35, OP_I386, I386OP(xor_ax_i16), I386OP(xor_eax_i32), },
- { 0x36, OP_I386, I386OP(segment_SS), I386OP(segment_SS), },
- { 0x37, OP_I386, I386OP(aaa), I386OP(aaa), },
- { 0x38, OP_I386, I386OP(cmp_rm8_r8), I386OP(cmp_rm8_r8), },
- { 0x39, OP_I386, I386OP(cmp_rm16_r16), I386OP(cmp_rm32_r32), },
- { 0x3A, OP_I386, I386OP(cmp_r8_rm8), I386OP(cmp_r8_rm8), },
- { 0x3B, OP_I386, I386OP(cmp_r16_rm16), I386OP(cmp_r32_rm32), },
- { 0x3C, OP_I386, I386OP(cmp_al_i8), I386OP(cmp_al_i8), },
- { 0x3D, OP_I386, I386OP(cmp_ax_i16), I386OP(cmp_eax_i32), },
- { 0x3E, OP_I386, I386OP(segment_DS), I386OP(segment_DS), },
- { 0x3F, OP_I386, I386OP(aas), I386OP(aas), },
- { 0x40, OP_I386, I386OP(inc_ax), I386OP(inc_eax), },
- { 0x41, OP_I386, I386OP(inc_cx), I386OP(inc_ecx), },
- { 0x42, OP_I386, I386OP(inc_dx), I386OP(inc_edx), },
- { 0x43, OP_I386, I386OP(inc_bx), I386OP(inc_ebx), },
- { 0x44, OP_I386, I386OP(inc_sp), I386OP(inc_esp), },
- { 0x45, OP_I386, I386OP(inc_bp), I386OP(inc_ebp), },
- { 0x46, OP_I386, I386OP(inc_si), I386OP(inc_esi), },
- { 0x47, OP_I386, I386OP(inc_di), I386OP(inc_edi), },
- { 0x48, OP_I386, I386OP(dec_ax), I386OP(dec_eax), },
- { 0x49, OP_I386, I386OP(dec_cx), I386OP(dec_ecx), },
- { 0x4A, OP_I386, I386OP(dec_dx), I386OP(dec_edx), },
- { 0x4B, OP_I386, I386OP(dec_bx), I386OP(dec_ebx), },
- { 0x4C, OP_I386, I386OP(dec_sp), I386OP(dec_esp), },
- { 0x4D, OP_I386, I386OP(dec_bp), I386OP(dec_ebp), },
- { 0x4E, OP_I386, I386OP(dec_si), I386OP(dec_esi), },
- { 0x4F, OP_I386, I386OP(dec_di), I386OP(dec_edi), },
- { 0x50, OP_I386, I386OP(push_ax), I386OP(push_eax), },
- { 0x51, OP_I386, I386OP(push_cx), I386OP(push_ecx), },
- { 0x52, OP_I386, I386OP(push_dx), I386OP(push_edx), },
- { 0x53, OP_I386, I386OP(push_bx), I386OP(push_ebx), },
- { 0x54, OP_I386, I386OP(push_sp), I386OP(push_esp), },
- { 0x55, OP_I386, I386OP(push_bp), I386OP(push_ebp), },
- { 0x56, OP_I386, I386OP(push_si), I386OP(push_esi), },
- { 0x57, OP_I386, I386OP(push_di), I386OP(push_edi), },
- { 0x58, OP_I386, I386OP(pop_ax), I386OP(pop_eax), },
- { 0x59, OP_I386, I386OP(pop_cx), I386OP(pop_ecx), },
- { 0x5A, OP_I386, I386OP(pop_dx), I386OP(pop_edx), },
- { 0x5B, OP_I386, I386OP(pop_bx), I386OP(pop_ebx), },
- { 0x5C, OP_I386, I386OP(pop_sp), I386OP(pop_esp), },
- { 0x5D, OP_I386, I386OP(pop_bp), I386OP(pop_ebp), },
- { 0x5E, OP_I386, I386OP(pop_si), I386OP(pop_esi), },
- { 0x5F, OP_I386, I386OP(pop_di), I386OP(pop_edi), },
- { 0x60, OP_I386, I386OP(pusha), I386OP(pushad), },
- { 0x61, OP_I386, I386OP(popa), I386OP(popad), },
- { 0x62, OP_I386, I386OP(bound_r16_m16_m16), I386OP(bound_r32_m32_m32), },
- { 0x63, OP_I386, I386OP(arpl), I386OP(arpl), },
- { 0x64, OP_I386, I386OP(segment_FS), I386OP(segment_FS), },
- { 0x65, OP_I386, I386OP(segment_GS), I386OP(segment_GS), },
- { 0x66, OP_I386, I386OP(operand_size), I386OP(operand_size), },
- { 0x67, OP_I386, I386OP(address_size), I386OP(address_size), },
- { 0x68, OP_I386, I386OP(push_i16), I386OP(push_i32), },
- { 0x69, OP_I386, I386OP(imul_r16_rm16_i16), I386OP(imul_r32_rm32_i32), },
- { 0x6A, OP_I386, I386OP(push_i8), I386OP(push_i8), },
- { 0x6B, OP_I386, I386OP(imul_r16_rm16_i8), I386OP(imul_r32_rm32_i8), },
- { 0x6C, OP_I386, I386OP(insb), I386OP(insb), },
- { 0x6D, OP_I386, I386OP(insw), I386OP(insd), },
- { 0x6E, OP_I386, I386OP(outsb), I386OP(outsb), },
- { 0x6F, OP_I386, I386OP(outsw), I386OP(outsd), },
- { 0x70, OP_I386, I386OP(jo_rel8), I386OP(jo_rel8), },
- { 0x71, OP_I386, I386OP(jno_rel8), I386OP(jno_rel8), },
- { 0x72, OP_I386, I386OP(jc_rel8), I386OP(jc_rel8), },
- { 0x73, OP_I386, I386OP(jnc_rel8), I386OP(jnc_rel8), },
- { 0x74, OP_I386, I386OP(jz_rel8), I386OP(jz_rel8), },
- { 0x75, OP_I386, I386OP(jnz_rel8), I386OP(jnz_rel8), },
- { 0x76, OP_I386, I386OP(jbe_rel8), I386OP(jbe_rel8), },
- { 0x77, OP_I386, I386OP(ja_rel8), I386OP(ja_rel8), },
- { 0x78, OP_I386, I386OP(js_rel8), I386OP(js_rel8), },
- { 0x79, OP_I386, I386OP(jns_rel8), I386OP(jns_rel8), },
- { 0x7A, OP_I386, I386OP(jp_rel8), I386OP(jp_rel8), },
- { 0x7B, OP_I386, I386OP(jnp_rel8), I386OP(jnp_rel8), },
- { 0x7C, OP_I386, I386OP(jl_rel8), I386OP(jl_rel8), },
- { 0x7D, OP_I386, I386OP(jge_rel8), I386OP(jge_rel8), },
- { 0x7E, OP_I386, I386OP(jle_rel8), I386OP(jle_rel8), },
- { 0x7F, OP_I386, I386OP(jg_rel8), I386OP(jg_rel8), },
- { 0x80, OP_I386, I386OP(group80_8), I386OP(group80_8), },
- { 0x81, OP_I386, I386OP(group81_16), I386OP(group81_32), },
- { 0x82, OP_I386, I386OP(group80_8), I386OP(group80_8), },
- { 0x83, OP_I386, I386OP(group83_16), I386OP(group83_32), },
- { 0x84, OP_I386, I386OP(test_rm8_r8), I386OP(test_rm8_r8), },
- { 0x85, OP_I386, I386OP(test_rm16_r16), I386OP(test_rm32_r32), },
- { 0x86, OP_I386, I386OP(xchg_r8_rm8), I386OP(xchg_r8_rm8), },
- { 0x87, OP_I386, I386OP(xchg_r16_rm16), I386OP(xchg_r32_rm32), },
- { 0x88, OP_I386, I386OP(mov_rm8_r8), I386OP(mov_rm8_r8), },
- { 0x89, OP_I386, I386OP(mov_rm16_r16), I386OP(mov_rm32_r32), },
- { 0x8A, OP_I386, I386OP(mov_r8_rm8), I386OP(mov_r8_rm8), },
- { 0x8B, OP_I386, I386OP(mov_r16_rm16), I386OP(mov_r32_rm32), },
- { 0x8C, OP_I386, I386OP(mov_rm16_sreg), I386OP(mov_rm16_sreg), },
- { 0x8D, OP_I386, I386OP(lea16), I386OP(lea32), },
- { 0x8E, OP_I386, I386OP(mov_sreg_rm16), I386OP(mov_sreg_rm16), },
- { 0x8F, OP_I386, I386OP(pop_rm16), I386OP(pop_rm32), },
- { 0x90, OP_I386, I386OP(nop), I386OP(nop), },
- { 0x91, OP_I386, I386OP(xchg_ax_cx), I386OP(xchg_eax_ecx), },
- { 0x92, OP_I386, I386OP(xchg_ax_dx), I386OP(xchg_eax_edx), },
- { 0x93, OP_I386, I386OP(xchg_ax_bx), I386OP(xchg_eax_ebx), },
- { 0x94, OP_I386, I386OP(xchg_ax_sp), I386OP(xchg_eax_esp), },
- { 0x95, OP_I386, I386OP(xchg_ax_bp), I386OP(xchg_eax_ebp), },
- { 0x96, OP_I386, I386OP(xchg_ax_si), I386OP(xchg_eax_esi), },
- { 0x97, OP_I386, I386OP(xchg_ax_di), I386OP(xchg_eax_edi), },
- { 0x98, OP_I386, I386OP(cbw), I386OP(cwde), },
- { 0x99, OP_I386, I386OP(cwd), I386OP(cdq), },
- { 0x9A, OP_I386, I386OP(call_abs16), I386OP(call_abs32), },
- { 0x9B, OP_I386, I386OP(wait), I386OP(wait), },
- { 0x9C, OP_I386, I386OP(pushf), I386OP(pushfd), },
- { 0x9D, OP_I386, I386OP(popf), I386OP(popfd), },
- { 0x9E, OP_I386, I386OP(sahf), I386OP(sahf), },
- { 0x9F, OP_I386, I386OP(lahf), I386OP(lahf), },
- { 0xA0, OP_I386, I386OP(mov_al_m8), I386OP(mov_al_m8), },
- { 0xA1, OP_I386, I386OP(mov_ax_m16), I386OP(mov_eax_m32), },
- { 0xA2, OP_I386, I386OP(mov_m8_al), I386OP(mov_m8_al), },
- { 0xA3, OP_I386, I386OP(mov_m16_ax), I386OP(mov_m32_eax), },
- { 0xA4, OP_I386, I386OP(movsb), I386OP(movsb), },
- { 0xA5, OP_I386, I386OP(movsw), I386OP(movsd), },
- { 0xA6, OP_I386, I386OP(cmpsb), I386OP(cmpsb), },
- { 0xA7, OP_I386, I386OP(cmpsw), I386OP(cmpsd), },
- { 0xA8, OP_I386, I386OP(test_al_i8), I386OP(test_al_i8), },
- { 0xA9, OP_I386, I386OP(test_ax_i16), I386OP(test_eax_i32), },
- { 0xAA, OP_I386, I386OP(stosb), I386OP(stosb), },
- { 0xAB, OP_I386, I386OP(stosw), I386OP(stosd), },
- { 0xAC, OP_I386, I386OP(lodsb), I386OP(lodsb), },
- { 0xAD, OP_I386, I386OP(lodsw), I386OP(lodsd), },
- { 0xAE, OP_I386, I386OP(scasb), I386OP(scasb), },
- { 0xAF, OP_I386, I386OP(scasw), I386OP(scasd), },
- { 0xB0, OP_I386, I386OP(mov_al_i8), I386OP(mov_al_i8), },
- { 0xB1, OP_I386, I386OP(mov_cl_i8), I386OP(mov_cl_i8), },
- { 0xB2, OP_I386, I386OP(mov_dl_i8), I386OP(mov_dl_i8), },
- { 0xB3, OP_I386, I386OP(mov_bl_i8), I386OP(mov_bl_i8), },
- { 0xB4, OP_I386, I386OP(mov_ah_i8), I386OP(mov_ah_i8), },
- { 0xB5, OP_I386, I386OP(mov_ch_i8), I386OP(mov_ch_i8), },
- { 0xB6, OP_I386, I386OP(mov_dh_i8), I386OP(mov_dh_i8), },
- { 0xB7, OP_I386, I386OP(mov_bh_i8), I386OP(mov_bh_i8), },
- { 0xB8, OP_I386, I386OP(mov_ax_i16), I386OP(mov_eax_i32), },
- { 0xB9, OP_I386, I386OP(mov_cx_i16), I386OP(mov_ecx_i32), },
- { 0xBA, OP_I386, I386OP(mov_dx_i16), I386OP(mov_edx_i32), },
- { 0xBB, OP_I386, I386OP(mov_bx_i16), I386OP(mov_ebx_i32), },
- { 0xBC, OP_I386, I386OP(mov_sp_i16), I386OP(mov_esp_i32), },
- { 0xBD, OP_I386, I386OP(mov_bp_i16), I386OP(mov_ebp_i32), },
- { 0xBE, OP_I386, I386OP(mov_si_i16), I386OP(mov_esi_i32), },
- { 0xBF, OP_I386, I386OP(mov_di_i16), I386OP(mov_edi_i32), },
- { 0xC0, OP_I386, I386OP(groupC0_8), I386OP(groupC0_8), },
- { 0xC1, OP_I386, I386OP(groupC1_16), I386OP(groupC1_32), },
- { 0xC2, OP_I386, I386OP(ret_near16_i16), I386OP(ret_near32_i16), },
- { 0xC3, OP_I386, I386OP(ret_near16), I386OP(ret_near32), },
- { 0xC4, OP_I386, I386OP(les16), I386OP(les32), },
- { 0xC5, OP_I386, I386OP(lds16), I386OP(lds32), },
- { 0xC6, OP_I386, I386OP(mov_rm8_i8), I386OP(mov_rm8_i8), },
- { 0xC7, OP_I386, I386OP(mov_rm16_i16), I386OP(mov_rm32_i32), },
- { 0xC8, OP_I386, I386OP(enter16), I386OP(enter32), },
- { 0xC9, OP_I386, I386OP(leave16), I386OP(leave32), },
- { 0xCA, OP_I386, I386OP(retf_i16), I386OP(retf_i32), },
- { 0xCB, OP_I386, I386OP(retf16), I386OP(retf32), },
- { 0xCC, OP_I386, I386OP(int3), I386OP(int3), },
- { 0xCD, OP_I386, I386OP(int), I386OP(int), },
- { 0xCE, OP_I386, I386OP(into), I386OP(into), },
- { 0xCF, OP_I386, I386OP(iret16), I386OP(iret32), },
- { 0xD0, OP_I386, I386OP(groupD0_8), I386OP(groupD0_8), },
- { 0xD1, OP_I386, I386OP(groupD1_16), I386OP(groupD1_32), },
- { 0xD2, OP_I386, I386OP(groupD2_8), I386OP(groupD2_8), },
- { 0xD3, OP_I386, I386OP(groupD3_16), I386OP(groupD3_32), },
- { 0xD4, OP_I386, I386OP(aam), I386OP(aam), },
- { 0xD5, OP_I386, I386OP(aad), I386OP(aad), },
- { 0xD6, OP_I386, I386OP(setalc), I386OP(setalc), },
- { 0xD7, OP_I386, I386OP(xlat), I386OP(xlat), },
- { 0xD8, OP_I386, I386OP(escape), I386OP(escape), },
- { 0xD9, OP_I386, I386OP(escape), I386OP(escape), },
- { 0xDA, OP_I386, I386OP(escape), I386OP(escape), },
- { 0xDB, OP_I386, I386OP(escape), I386OP(escape), },
- { 0xDC, OP_I386, I386OP(escape), I386OP(escape), },
- { 0xDD, OP_I386, I386OP(escape), I386OP(escape), },
- { 0xDE, OP_I386, I386OP(escape), I386OP(escape), },
- { 0xDF, OP_I386, I386OP(escape), I386OP(escape), },
- { 0xD8, OP_FPU, I386OP(x87_group_d8), I386OP(x87_group_d8), },
- { 0xD9, OP_FPU, I386OP(x87_group_d9), I386OP(x87_group_d9), },
- { 0xDA, OP_FPU, I386OP(x87_group_da), I386OP(x87_group_da), },
- { 0xDB, OP_FPU, I386OP(x87_group_db), I386OP(x87_group_db), },
- { 0xDC, OP_FPU, I386OP(x87_group_dc), I386OP(x87_group_dc), },
- { 0xDD, OP_FPU, I386OP(x87_group_dd), I386OP(x87_group_dd), },
- { 0xDE, OP_FPU, I386OP(x87_group_de), I386OP(x87_group_de), },
- { 0xDF, OP_FPU, I386OP(x87_group_df), I386OP(x87_group_df), },
- { 0xE0, OP_I386, I386OP(loopne16), I386OP(loopne32), },
- { 0xE1, OP_I386, I386OP(loopz16), I386OP(loopz32), },
- { 0xE2, OP_I386, I386OP(loop16), I386OP(loop32), },
- { 0xE3, OP_I386, I386OP(jcxz16), I386OP(jcxz32), },
- { 0xE4, OP_I386, I386OP(in_al_i8), I386OP(in_al_i8), },
- { 0xE5, OP_I386, I386OP(in_ax_i8), I386OP(in_eax_i8), },
- { 0xE6, OP_I386, I386OP(out_al_i8), I386OP(out_al_i8), },
- { 0xE7, OP_I386, I386OP(out_ax_i8), I386OP(out_eax_i8), },
- { 0xE8, OP_I386, I386OP(call_rel16), I386OP(call_rel32), },
- { 0xE9, OP_I386, I386OP(jmp_rel16), I386OP(jmp_rel32), },
- { 0xEA, OP_I386, I386OP(jmp_abs16), I386OP(jmp_abs32), },
- { 0xEB, OP_I386, I386OP(jmp_rel8), I386OP(jmp_rel8), },
- { 0xEC, OP_I386, I386OP(in_al_dx), I386OP(in_al_dx), },
- { 0xED, OP_I386, I386OP(in_ax_dx), I386OP(in_eax_dx), },
- { 0xEE, OP_I386, I386OP(out_al_dx), I386OP(out_al_dx), },
- { 0xEF, OP_I386, I386OP(out_ax_dx), I386OP(out_eax_dx), },
- { 0xF0, OP_I386, I386OP(lock), I386OP(lock), },
- { 0xF1, OP_I386, I386OP(invalid), I386OP(invalid), },
- { 0xF2, OP_I386, I386OP(repne), I386OP(repne), },
- { 0xF3, OP_I386, I386OP(rep), I386OP(rep), },
- { 0xF4, OP_I386, I386OP(hlt), I386OP(hlt), },
- { 0xF5, OP_I386, I386OP(cmc), I386OP(cmc), },
- { 0xF6, OP_I386, I386OP(groupF6_8), I386OP(groupF6_8), },
- { 0xF7, OP_I386, I386OP(groupF7_16), I386OP(groupF7_32), },
- { 0xF8, OP_I386, I386OP(clc), I386OP(clc), },
- { 0xF9, OP_I386, I386OP(stc), I386OP(stc), },
- { 0xFA, OP_I386, I386OP(cli), I386OP(cli), },
- { 0xFB, OP_I386, I386OP(sti), I386OP(sti), },
- { 0xFC, OP_I386, I386OP(cld), I386OP(cld), },
- { 0xFD, OP_I386, I386OP(std), I386OP(std), },
- { 0xFE, OP_I386, I386OP(groupFE_8), I386OP(groupFE_8), },
- { 0xFF, OP_I386, I386OP(groupFF_16), I386OP(groupFF_32), },
+ { 0x00, OP_I386, &i386_device::i386_add_rm8_r8, &i386_device::i386_add_rm8_r8, },
+ { 0x01, OP_I386, &i386_device::i386_add_rm16_r16, &i386_device::i386_add_rm32_r32, },
+ { 0x02, OP_I386, &i386_device::i386_add_r8_rm8, &i386_device::i386_add_r8_rm8, },
+ { 0x03, OP_I386, &i386_device::i386_add_r16_rm16, &i386_device::i386_add_r32_rm32, },
+ { 0x04, OP_I386, &i386_device::i386_add_al_i8, &i386_device::i386_add_al_i8, },
+ { 0x05, OP_I386, &i386_device::i386_add_ax_i16, &i386_device::i386_add_eax_i32, },
+ { 0x06, OP_I386, &i386_device::i386_push_es16, &i386_device::i386_push_es32, },
+ { 0x07, OP_I386, &i386_device::i386_pop_es16, &i386_device::i386_pop_es32, },
+ { 0x08, OP_I386, &i386_device::i386_or_rm8_r8, &i386_device::i386_or_rm8_r8, },
+ { 0x09, OP_I386, &i386_device::i386_or_rm16_r16, &i386_device::i386_or_rm32_r32, },
+ { 0x0A, OP_I386, &i386_device::i386_or_r8_rm8, &i386_device::i386_or_r8_rm8, },
+ { 0x0B, OP_I386, &i386_device::i386_or_r16_rm16, &i386_device::i386_or_r32_rm32, },
+ { 0x0C, OP_I386, &i386_device::i386_or_al_i8, &i386_device::i386_or_al_i8, },
+ { 0x0D, OP_I386, &i386_device::i386_or_ax_i16, &i386_device::i386_or_eax_i32, },
+ { 0x0E, OP_I386, &i386_device::i386_push_cs16, &i386_device::i386_push_cs32, },
+ { 0x0F, OP_I386, &i386_device::i386_decode_two_byte, &i386_device::i386_decode_two_byte, },
+ { 0x10, OP_I386, &i386_device::i386_adc_rm8_r8, &i386_device::i386_adc_rm8_r8, },
+ { 0x11, OP_I386, &i386_device::i386_adc_rm16_r16, &i386_device::i386_adc_rm32_r32, },
+ { 0x12, OP_I386, &i386_device::i386_adc_r8_rm8, &i386_device::i386_adc_r8_rm8, },
+ { 0x13, OP_I386, &i386_device::i386_adc_r16_rm16, &i386_device::i386_adc_r32_rm32, },
+ { 0x14, OP_I386, &i386_device::i386_adc_al_i8, &i386_device::i386_adc_al_i8, },
+ { 0x15, OP_I386, &i386_device::i386_adc_ax_i16, &i386_device::i386_adc_eax_i32, },
+ { 0x16, OP_I386, &i386_device::i386_push_ss16, &i386_device::i386_push_ss32, },
+ { 0x17, OP_I386, &i386_device::i386_pop_ss16, &i386_device::i386_pop_ss32, },
+ { 0x18, OP_I386, &i386_device::i386_sbb_rm8_r8, &i386_device::i386_sbb_rm8_r8, },
+ { 0x19, OP_I386, &i386_device::i386_sbb_rm16_r16, &i386_device::i386_sbb_rm32_r32, },
+ { 0x1A, OP_I386, &i386_device::i386_sbb_r8_rm8, &i386_device::i386_sbb_r8_rm8, },
+ { 0x1B, OP_I386, &i386_device::i386_sbb_r16_rm16, &i386_device::i386_sbb_r32_rm32, },
+ { 0x1C, OP_I386, &i386_device::i386_sbb_al_i8, &i386_device::i386_sbb_al_i8, },
+ { 0x1D, OP_I386, &i386_device::i386_sbb_ax_i16, &i386_device::i386_sbb_eax_i32, },
+ { 0x1E, OP_I386, &i386_device::i386_push_ds16, &i386_device::i386_push_ds32, },
+ { 0x1F, OP_I386, &i386_device::i386_pop_ds16, &i386_device::i386_pop_ds32, },
+ { 0x20, OP_I386, &i386_device::i386_and_rm8_r8, &i386_device::i386_and_rm8_r8, },
+ { 0x21, OP_I386, &i386_device::i386_and_rm16_r16, &i386_device::i386_and_rm32_r32, },
+ { 0x22, OP_I386, &i386_device::i386_and_r8_rm8, &i386_device::i386_and_r8_rm8, },
+ { 0x23, OP_I386, &i386_device::i386_and_r16_rm16, &i386_device::i386_and_r32_rm32, },
+ { 0x24, OP_I386, &i386_device::i386_and_al_i8, &i386_device::i386_and_al_i8, },
+ { 0x25, OP_I386, &i386_device::i386_and_ax_i16, &i386_device::i386_and_eax_i32, },
+ { 0x26, OP_I386, &i386_device::i386_segment_ES, &i386_device::i386_segment_ES, },
+ { 0x27, OP_I386, &i386_device::i386_daa, &i386_device::i386_daa, },
+ { 0x28, OP_I386, &i386_device::i386_sub_rm8_r8, &i386_device::i386_sub_rm8_r8, },
+ { 0x29, OP_I386, &i386_device::i386_sub_rm16_r16, &i386_device::i386_sub_rm32_r32, },
+ { 0x2A, OP_I386, &i386_device::i386_sub_r8_rm8, &i386_device::i386_sub_r8_rm8, },
+ { 0x2B, OP_I386, &i386_device::i386_sub_r16_rm16, &i386_device::i386_sub_r32_rm32, },
+ { 0x2C, OP_I386, &i386_device::i386_sub_al_i8, &i386_device::i386_sub_al_i8, },
+ { 0x2D, OP_I386, &i386_device::i386_sub_ax_i16, &i386_device::i386_sub_eax_i32, },
+ { 0x2E, OP_I386, &i386_device::i386_segment_CS, &i386_device::i386_segment_CS, },
+ { 0x2F, OP_I386, &i386_device::i386_das, &i386_device::i386_das, },
+ { 0x30, OP_I386, &i386_device::i386_xor_rm8_r8, &i386_device::i386_xor_rm8_r8, },
+ { 0x31, OP_I386, &i386_device::i386_xor_rm16_r16, &i386_device::i386_xor_rm32_r32, },
+ { 0x32, OP_I386, &i386_device::i386_xor_r8_rm8, &i386_device::i386_xor_r8_rm8, },
+ { 0x33, OP_I386, &i386_device::i386_xor_r16_rm16, &i386_device::i386_xor_r32_rm32, },
+ { 0x34, OP_I386, &i386_device::i386_xor_al_i8, &i386_device::i386_xor_al_i8, },
+ { 0x35, OP_I386, &i386_device::i386_xor_ax_i16, &i386_device::i386_xor_eax_i32, },
+ { 0x36, OP_I386, &i386_device::i386_segment_SS, &i386_device::i386_segment_SS, },
+ { 0x37, OP_I386, &i386_device::i386_aaa, &i386_device::i386_aaa, },
+ { 0x38, OP_I386, &i386_device::i386_cmp_rm8_r8, &i386_device::i386_cmp_rm8_r8, },
+ { 0x39, OP_I386, &i386_device::i386_cmp_rm16_r16, &i386_device::i386_cmp_rm32_r32, },
+ { 0x3A, OP_I386, &i386_device::i386_cmp_r8_rm8, &i386_device::i386_cmp_r8_rm8, },
+ { 0x3B, OP_I386, &i386_device::i386_cmp_r16_rm16, &i386_device::i386_cmp_r32_rm32, },
+ { 0x3C, OP_I386, &i386_device::i386_cmp_al_i8, &i386_device::i386_cmp_al_i8, },
+ { 0x3D, OP_I386, &i386_device::i386_cmp_ax_i16, &i386_device::i386_cmp_eax_i32, },
+ { 0x3E, OP_I386, &i386_device::i386_segment_DS, &i386_device::i386_segment_DS, },
+ { 0x3F, OP_I386, &i386_device::i386_aas, &i386_device::i386_aas, },
+ { 0x40, OP_I386, &i386_device::i386_inc_ax, &i386_device::i386_inc_eax, },
+ { 0x41, OP_I386, &i386_device::i386_inc_cx, &i386_device::i386_inc_ecx, },
+ { 0x42, OP_I386, &i386_device::i386_inc_dx, &i386_device::i386_inc_edx, },
+ { 0x43, OP_I386, &i386_device::i386_inc_bx, &i386_device::i386_inc_ebx, },
+ { 0x44, OP_I386, &i386_device::i386_inc_sp, &i386_device::i386_inc_esp, },
+ { 0x45, OP_I386, &i386_device::i386_inc_bp, &i386_device::i386_inc_ebp, },
+ { 0x46, OP_I386, &i386_device::i386_inc_si, &i386_device::i386_inc_esi, },
+ { 0x47, OP_I386, &i386_device::i386_inc_di, &i386_device::i386_inc_edi, },
+ { 0x48, OP_I386, &i386_device::i386_dec_ax, &i386_device::i386_dec_eax, },
+ { 0x49, OP_I386, &i386_device::i386_dec_cx, &i386_device::i386_dec_ecx, },
+ { 0x4A, OP_I386, &i386_device::i386_dec_dx, &i386_device::i386_dec_edx, },
+ { 0x4B, OP_I386, &i386_device::i386_dec_bx, &i386_device::i386_dec_ebx, },
+ { 0x4C, OP_I386, &i386_device::i386_dec_sp, &i386_device::i386_dec_esp, },
+ { 0x4D, OP_I386, &i386_device::i386_dec_bp, &i386_device::i386_dec_ebp, },
+ { 0x4E, OP_I386, &i386_device::i386_dec_si, &i386_device::i386_dec_esi, },
+ { 0x4F, OP_I386, &i386_device::i386_dec_di, &i386_device::i386_dec_edi, },
+ { 0x50, OP_I386, &i386_device::i386_push_ax, &i386_device::i386_push_eax, },
+ { 0x51, OP_I386, &i386_device::i386_push_cx, &i386_device::i386_push_ecx, },
+ { 0x52, OP_I386, &i386_device::i386_push_dx, &i386_device::i386_push_edx, },
+ { 0x53, OP_I386, &i386_device::i386_push_bx, &i386_device::i386_push_ebx, },
+ { 0x54, OP_I386, &i386_device::i386_push_sp, &i386_device::i386_push_esp, },
+ { 0x55, OP_I386, &i386_device::i386_push_bp, &i386_device::i386_push_ebp, },
+ { 0x56, OP_I386, &i386_device::i386_push_si, &i386_device::i386_push_esi, },
+ { 0x57, OP_I386, &i386_device::i386_push_di, &i386_device::i386_push_edi, },
+ { 0x58, OP_I386, &i386_device::i386_pop_ax, &i386_device::i386_pop_eax, },
+ { 0x59, OP_I386, &i386_device::i386_pop_cx, &i386_device::i386_pop_ecx, },
+ { 0x5A, OP_I386, &i386_device::i386_pop_dx, &i386_device::i386_pop_edx, },
+ { 0x5B, OP_I386, &i386_device::i386_pop_bx, &i386_device::i386_pop_ebx, },
+ { 0x5C, OP_I386, &i386_device::i386_pop_sp, &i386_device::i386_pop_esp, },
+ { 0x5D, OP_I386, &i386_device::i386_pop_bp, &i386_device::i386_pop_ebp, },
+ { 0x5E, OP_I386, &i386_device::i386_pop_si, &i386_device::i386_pop_esi, },
+ { 0x5F, OP_I386, &i386_device::i386_pop_di, &i386_device::i386_pop_edi, },
+ { 0x60, OP_I386, &i386_device::i386_pusha, &i386_device::i386_pushad, },
+ { 0x61, OP_I386, &i386_device::i386_popa, &i386_device::i386_popad, },
+ { 0x62, OP_I386, &i386_device::i386_bound_r16_m16_m16, &i386_device::i386_bound_r32_m32_m32, },
+ { 0x63, OP_I386, &i386_device::i386_arpl, &i386_device::i386_arpl, },
+ { 0x64, OP_I386, &i386_device::i386_segment_FS, &i386_device::i386_segment_FS, },
+ { 0x65, OP_I386, &i386_device::i386_segment_GS, &i386_device::i386_segment_GS, },
+ { 0x66, OP_I386, &i386_device::i386_operand_size, &i386_device::i386_operand_size, },
+ { 0x67, OP_I386, &i386_device::i386_address_size, &i386_device::i386_address_size, },
+ { 0x68, OP_I386, &i386_device::i386_push_i16, &i386_device::i386_push_i32, },
+ { 0x69, OP_I386, &i386_device::i386_imul_r16_rm16_i16, &i386_device::i386_imul_r32_rm32_i32, },
+ { 0x6A, OP_I386, &i386_device::i386_push_i8, &i386_device::i386_push_i8, },
+ { 0x6B, OP_I386, &i386_device::i386_imul_r16_rm16_i8, &i386_device::i386_imul_r32_rm32_i8, },
+ { 0x6C, OP_I386, &i386_device::i386_insb, &i386_device::i386_insb, },
+ { 0x6D, OP_I386, &i386_device::i386_insw, &i386_device::i386_insd, },
+ { 0x6E, OP_I386, &i386_device::i386_outsb, &i386_device::i386_outsb, },
+ { 0x6F, OP_I386, &i386_device::i386_outsw, &i386_device::i386_outsd, },
+ { 0x70, OP_I386, &i386_device::i386_jo_rel8, &i386_device::i386_jo_rel8, },
+ { 0x71, OP_I386, &i386_device::i386_jno_rel8, &i386_device::i386_jno_rel8, },
+ { 0x72, OP_I386, &i386_device::i386_jc_rel8, &i386_device::i386_jc_rel8, },
+ { 0x73, OP_I386, &i386_device::i386_jnc_rel8, &i386_device::i386_jnc_rel8, },
+ { 0x74, OP_I386, &i386_device::i386_jz_rel8, &i386_device::i386_jz_rel8, },
+ { 0x75, OP_I386, &i386_device::i386_jnz_rel8, &i386_device::i386_jnz_rel8, },
+ { 0x76, OP_I386, &i386_device::i386_jbe_rel8, &i386_device::i386_jbe_rel8, },
+ { 0x77, OP_I386, &i386_device::i386_ja_rel8, &i386_device::i386_ja_rel8, },
+ { 0x78, OP_I386, &i386_device::i386_js_rel8, &i386_device::i386_js_rel8, },
+ { 0x79, OP_I386, &i386_device::i386_jns_rel8, &i386_device::i386_jns_rel8, },
+ { 0x7A, OP_I386, &i386_device::i386_jp_rel8, &i386_device::i386_jp_rel8, },
+ { 0x7B, OP_I386, &i386_device::i386_jnp_rel8, &i386_device::i386_jnp_rel8, },
+ { 0x7C, OP_I386, &i386_device::i386_jl_rel8, &i386_device::i386_jl_rel8, },
+ { 0x7D, OP_I386, &i386_device::i386_jge_rel8, &i386_device::i386_jge_rel8, },
+ { 0x7E, OP_I386, &i386_device::i386_jle_rel8, &i386_device::i386_jle_rel8, },
+ { 0x7F, OP_I386, &i386_device::i386_jg_rel8, &i386_device::i386_jg_rel8, },
+ { 0x80, OP_I386, &i386_device::i386_group80_8, &i386_device::i386_group80_8, },
+ { 0x81, OP_I386, &i386_device::i386_group81_16, &i386_device::i386_group81_32, },
+ { 0x82, OP_I386, &i386_device::i386_group80_8, &i386_device::i386_group80_8, },
+ { 0x83, OP_I386, &i386_device::i386_group83_16, &i386_device::i386_group83_32, },
+ { 0x84, OP_I386, &i386_device::i386_test_rm8_r8, &i386_device::i386_test_rm8_r8, },
+ { 0x85, OP_I386, &i386_device::i386_test_rm16_r16, &i386_device::i386_test_rm32_r32, },
+ { 0x86, OP_I386, &i386_device::i386_xchg_r8_rm8, &i386_device::i386_xchg_r8_rm8, },
+ { 0x87, OP_I386, &i386_device::i386_xchg_r16_rm16, &i386_device::i386_xchg_r32_rm32, },
+ { 0x88, OP_I386, &i386_device::i386_mov_rm8_r8, &i386_device::i386_mov_rm8_r8, },
+ { 0x89, OP_I386, &i386_device::i386_mov_rm16_r16, &i386_device::i386_mov_rm32_r32, },
+ { 0x8A, OP_I386, &i386_device::i386_mov_r8_rm8, &i386_device::i386_mov_r8_rm8, },
+ { 0x8B, OP_I386, &i386_device::i386_mov_r16_rm16, &i386_device::i386_mov_r32_rm32, },
+ { 0x8C, OP_I386, &i386_device::i386_mov_rm16_sreg, &i386_device::i386_mov_rm16_sreg, },
+ { 0x8D, OP_I386, &i386_device::i386_lea16, &i386_device::i386_lea32, },
+ { 0x8E, OP_I386, &i386_device::i386_mov_sreg_rm16, &i386_device::i386_mov_sreg_rm16, },
+ { 0x8F, OP_I386, &i386_device::i386_pop_rm16, &i386_device::i386_pop_rm32, },
+ { 0x90, OP_I386, &i386_device::i386_nop, &i386_device::i386_nop, },
+ { 0x91, OP_I386, &i386_device::i386_xchg_ax_cx, &i386_device::i386_xchg_eax_ecx, },
+ { 0x92, OP_I386, &i386_device::i386_xchg_ax_dx, &i386_device::i386_xchg_eax_edx, },
+ { 0x93, OP_I386, &i386_device::i386_xchg_ax_bx, &i386_device::i386_xchg_eax_ebx, },
+ { 0x94, OP_I386, &i386_device::i386_xchg_ax_sp, &i386_device::i386_xchg_eax_esp, },
+ { 0x95, OP_I386, &i386_device::i386_xchg_ax_bp, &i386_device::i386_xchg_eax_ebp, },
+ { 0x96, OP_I386, &i386_device::i386_xchg_ax_si, &i386_device::i386_xchg_eax_esi, },
+ { 0x97, OP_I386, &i386_device::i386_xchg_ax_di, &i386_device::i386_xchg_eax_edi, },
+ { 0x98, OP_I386, &i386_device::i386_cbw, &i386_device::i386_cwde, },
+ { 0x99, OP_I386, &i386_device::i386_cwd, &i386_device::i386_cdq, },
+ { 0x9A, OP_I386, &i386_device::i386_call_abs16, &i386_device::i386_call_abs32, },
+ { 0x9B, OP_I386, &i386_device::i386_wait, &i386_device::i386_wait, },
+ { 0x9C, OP_I386, &i386_device::i386_pushf, &i386_device::i386_pushfd, },
+ { 0x9D, OP_I386, &i386_device::i386_popf, &i386_device::i386_popfd, },
+ { 0x9E, OP_I386, &i386_device::i386_sahf, &i386_device::i386_sahf, },
+ { 0x9F, OP_I386, &i386_device::i386_lahf, &i386_device::i386_lahf, },
+ { 0xA0, OP_I386, &i386_device::i386_mov_al_m8, &i386_device::i386_mov_al_m8, },
+ { 0xA1, OP_I386, &i386_device::i386_mov_ax_m16, &i386_device::i386_mov_eax_m32, },
+ { 0xA2, OP_I386, &i386_device::i386_mov_m8_al, &i386_device::i386_mov_m8_al, },
+ { 0xA3, OP_I386, &i386_device::i386_mov_m16_ax, &i386_device::i386_mov_m32_eax, },
+ { 0xA4, OP_I386, &i386_device::i386_movsb, &i386_device::i386_movsb, },
+ { 0xA5, OP_I386, &i386_device::i386_movsw, &i386_device::i386_movsd, },
+ { 0xA6, OP_I386, &i386_device::i386_cmpsb, &i386_device::i386_cmpsb, },
+ { 0xA7, OP_I386, &i386_device::i386_cmpsw, &i386_device::i386_cmpsd, },
+ { 0xA8, OP_I386, &i386_device::i386_test_al_i8, &i386_device::i386_test_al_i8, },
+ { 0xA9, OP_I386, &i386_device::i386_test_ax_i16, &i386_device::i386_test_eax_i32, },
+ { 0xAA, OP_I386, &i386_device::i386_stosb, &i386_device::i386_stosb, },
+ { 0xAB, OP_I386, &i386_device::i386_stosw, &i386_device::i386_stosd, },
+ { 0xAC, OP_I386, &i386_device::i386_lodsb, &i386_device::i386_lodsb, },
+ { 0xAD, OP_I386, &i386_device::i386_lodsw, &i386_device::i386_lodsd, },
+ { 0xAE, OP_I386, &i386_device::i386_scasb, &i386_device::i386_scasb, },
+ { 0xAF, OP_I386, &i386_device::i386_scasw, &i386_device::i386_scasd, },
+ { 0xB0, OP_I386, &i386_device::i386_mov_al_i8, &i386_device::i386_mov_al_i8, },
+ { 0xB1, OP_I386, &i386_device::i386_mov_cl_i8, &i386_device::i386_mov_cl_i8, },
+ { 0xB2, OP_I386, &i386_device::i386_mov_dl_i8, &i386_device::i386_mov_dl_i8, },
+ { 0xB3, OP_I386, &i386_device::i386_mov_bl_i8, &i386_device::i386_mov_bl_i8, },
+ { 0xB4, OP_I386, &i386_device::i386_mov_ah_i8, &i386_device::i386_mov_ah_i8, },
+ { 0xB5, OP_I386, &i386_device::i386_mov_ch_i8, &i386_device::i386_mov_ch_i8, },
+ { 0xB6, OP_I386, &i386_device::i386_mov_dh_i8, &i386_device::i386_mov_dh_i8, },
+ { 0xB7, OP_I386, &i386_device::i386_mov_bh_i8, &i386_device::i386_mov_bh_i8, },
+ { 0xB8, OP_I386, &i386_device::i386_mov_ax_i16, &i386_device::i386_mov_eax_i32, },
+ { 0xB9, OP_I386, &i386_device::i386_mov_cx_i16, &i386_device::i386_mov_ecx_i32, },
+ { 0xBA, OP_I386, &i386_device::i386_mov_dx_i16, &i386_device::i386_mov_edx_i32, },
+ { 0xBB, OP_I386, &i386_device::i386_mov_bx_i16, &i386_device::i386_mov_ebx_i32, },
+ { 0xBC, OP_I386, &i386_device::i386_mov_sp_i16, &i386_device::i386_mov_esp_i32, },
+ { 0xBD, OP_I386, &i386_device::i386_mov_bp_i16, &i386_device::i386_mov_ebp_i32, },
+ { 0xBE, OP_I386, &i386_device::i386_mov_si_i16, &i386_device::i386_mov_esi_i32, },
+ { 0xBF, OP_I386, &i386_device::i386_mov_di_i16, &i386_device::i386_mov_edi_i32, },
+ { 0xC0, OP_I386, &i386_device::i386_groupC0_8, &i386_device::i386_groupC0_8, },
+ { 0xC1, OP_I386, &i386_device::i386_groupC1_16, &i386_device::i386_groupC1_32, },
+ { 0xC2, OP_I386, &i386_device::i386_ret_near16_i16, &i386_device::i386_ret_near32_i16, },
+ { 0xC3, OP_I386, &i386_device::i386_ret_near16, &i386_device::i386_ret_near32, },
+ { 0xC4, OP_I386, &i386_device::i386_les16, &i386_device::i386_les32, },
+ { 0xC5, OP_I386, &i386_device::i386_lds16, &i386_device::i386_lds32, },
+ { 0xC6, OP_I386, &i386_device::i386_mov_rm8_i8, &i386_device::i386_mov_rm8_i8, },
+ { 0xC7, OP_I386, &i386_device::i386_mov_rm16_i16, &i386_device::i386_mov_rm32_i32, },
+ { 0xC8, OP_I386, &i386_device::i386_enter16, &i386_device::i386_enter32, },
+ { 0xC9, OP_I386, &i386_device::i386_leave16, &i386_device::i386_leave32, },
+ { 0xCA, OP_I386, &i386_device::i386_retf_i16, &i386_device::i386_retf_i32, },
+ { 0xCB, OP_I386, &i386_device::i386_retf16, &i386_device::i386_retf32, },
+ { 0xCC, OP_I386, &i386_device::i386_int3, &i386_device::i386_int3, },
+ { 0xCD, OP_I386, &i386_device::i386_int, &i386_device::i386_int, },
+ { 0xCE, OP_I386, &i386_device::i386_into, &i386_device::i386_into, },
+ { 0xCF, OP_I386, &i386_device::i386_iret16, &i386_device::i386_iret32, },
+ { 0xD0, OP_I386, &i386_device::i386_groupD0_8, &i386_device::i386_groupD0_8, },
+ { 0xD1, OP_I386, &i386_device::i386_groupD1_16, &i386_device::i386_groupD1_32, },
+ { 0xD2, OP_I386, &i386_device::i386_groupD2_8, &i386_device::i386_groupD2_8, },
+ { 0xD3, OP_I386, &i386_device::i386_groupD3_16, &i386_device::i386_groupD3_32, },
+ { 0xD4, OP_I386, &i386_device::i386_aam, &i386_device::i386_aam, },
+ { 0xD5, OP_I386, &i386_device::i386_aad, &i386_device::i386_aad, },
+ { 0xD6, OP_I386, &i386_device::i386_setalc, &i386_device::i386_setalc, },
+ { 0xD7, OP_I386, &i386_device::i386_xlat, &i386_device::i386_xlat, },
+ { 0xD8, OP_I386, &i386_device::i386_escape, &i386_device::i386_escape, },
+ { 0xD9, OP_I386, &i386_device::i386_escape, &i386_device::i386_escape, },
+ { 0xDA, OP_I386, &i386_device::i386_escape, &i386_device::i386_escape, },
+ { 0xDB, OP_I386, &i386_device::i386_escape, &i386_device::i386_escape, },
+ { 0xDC, OP_I386, &i386_device::i386_escape, &i386_device::i386_escape, },
+ { 0xDD, OP_I386, &i386_device::i386_escape, &i386_device::i386_escape, },
+ { 0xDE, OP_I386, &i386_device::i386_escape, &i386_device::i386_escape, },
+ { 0xDF, OP_I386, &i386_device::i386_escape, &i386_device::i386_escape, },
+ { 0xD8, OP_FPU, &i386_device::i386_x87_group_d8, &i386_device::i386_x87_group_d8, },
+ { 0xD9, OP_FPU, &i386_device::i386_x87_group_d9, &i386_device::i386_x87_group_d9, },
+ { 0xDA, OP_FPU, &i386_device::i386_x87_group_da, &i386_device::i386_x87_group_da, },
+ { 0xDB, OP_FPU, &i386_device::i386_x87_group_db, &i386_device::i386_x87_group_db, },
+ { 0xDC, OP_FPU, &i386_device::i386_x87_group_dc, &i386_device::i386_x87_group_dc, },
+ { 0xDD, OP_FPU, &i386_device::i386_x87_group_dd, &i386_device::i386_x87_group_dd, },
+ { 0xDE, OP_FPU, &i386_device::i386_x87_group_de, &i386_device::i386_x87_group_de, },
+ { 0xDF, OP_FPU, &i386_device::i386_x87_group_df, &i386_device::i386_x87_group_df, },
+ { 0xE0, OP_I386, &i386_device::i386_loopne16, &i386_device::i386_loopne32, },
+ { 0xE1, OP_I386, &i386_device::i386_loopz16, &i386_device::i386_loopz32, },
+ { 0xE2, OP_I386, &i386_device::i386_loop16, &i386_device::i386_loop32, },
+ { 0xE3, OP_I386, &i386_device::i386_jcxz16, &i386_device::i386_jcxz32, },
+ { 0xE4, OP_I386, &i386_device::i386_in_al_i8, &i386_device::i386_in_al_i8, },
+ { 0xE5, OP_I386, &i386_device::i386_in_ax_i8, &i386_device::i386_in_eax_i8, },
+ { 0xE6, OP_I386, &i386_device::i386_out_al_i8, &i386_device::i386_out_al_i8, },
+ { 0xE7, OP_I386, &i386_device::i386_out_ax_i8, &i386_device::i386_out_eax_i8, },
+ { 0xE8, OP_I386, &i386_device::i386_call_rel16, &i386_device::i386_call_rel32, },
+ { 0xE9, OP_I386, &i386_device::i386_jmp_rel16, &i386_device::i386_jmp_rel32, },
+ { 0xEA, OP_I386, &i386_device::i386_jmp_abs16, &i386_device::i386_jmp_abs32, },
+ { 0xEB, OP_I386, &i386_device::i386_jmp_rel8, &i386_device::i386_jmp_rel8, },
+ { 0xEC, OP_I386, &i386_device::i386_in_al_dx, &i386_device::i386_in_al_dx, },
+ { 0xED, OP_I386, &i386_device::i386_in_ax_dx, &i386_device::i386_in_eax_dx, },
+ { 0xEE, OP_I386, &i386_device::i386_out_al_dx, &i386_device::i386_out_al_dx, },
+ { 0xEF, OP_I386, &i386_device::i386_out_ax_dx, &i386_device::i386_out_eax_dx, },
+ { 0xF0, OP_I386, &i386_device::i386_lock, &i386_device::i386_lock, },
+ { 0xF1, OP_I386, &i386_device::i386_invalid, &i386_device::i386_invalid, },
+ { 0xF2, OP_I386, &i386_device::i386_repne, &i386_device::i386_repne, },
+ { 0xF3, OP_I386, &i386_device::i386_rep, &i386_device::i386_rep, },
+ { 0xF4, OP_I386, &i386_device::i386_hlt, &i386_device::i386_hlt, },
+ { 0xF5, OP_I386, &i386_device::i386_cmc, &i386_device::i386_cmc, },
+ { 0xF6, OP_I386, &i386_device::i386_groupF6_8, &i386_device::i386_groupF6_8, },
+ { 0xF7, OP_I386, &i386_device::i386_groupF7_16, &i386_device::i386_groupF7_32, },
+ { 0xF8, OP_I386, &i386_device::i386_clc, &i386_device::i386_clc, },
+ { 0xF9, OP_I386, &i386_device::i386_stc, &i386_device::i386_stc, },
+ { 0xFA, OP_I386, &i386_device::i386_cli, &i386_device::i386_cli, },
+ { 0xFB, OP_I386, &i386_device::i386_sti, &i386_device::i386_sti, },
+ { 0xFC, OP_I386, &i386_device::i386_cld, &i386_device::i386_cld, },
+ { 0xFD, OP_I386, &i386_device::i386_std, &i386_device::i386_std, },
+ { 0xFE, OP_I386, &i386_device::i386_groupFE_8, &i386_device::i386_groupFE_8, },
+ { 0xFF, OP_I386, &i386_device::i386_groupFF_16, &i386_device::i386_groupFF_32, },
/* 0F ?? */
- { 0x00, OP_2BYTE|OP_I386, I386OP(group0F00_16), I386OP(group0F00_32), },
- { 0x01, OP_2BYTE|OP_I386, I386OP(group0F01_16), I386OP(group0F01_32), },
- { 0x01, OP_2BYTE|OP_I486, I486OP(group0F01_16), I486OP(group0F01_32), },
- { 0x02, OP_2BYTE|OP_I386, I386OP(lar_r16_rm16), I386OP(lar_r32_rm32), },
- { 0x03, OP_2BYTE|OP_I386, I386OP(lsl_r16_rm16), I386OP(lsl_r32_rm32), },
- { 0x06, OP_2BYTE|OP_I386, I386OP(clts), I386OP(clts), },
- { 0x07, OP_2BYTE|OP_I386, I386OP(loadall), I386OP(loadall), },
- { 0x08, OP_2BYTE|OP_I486, I486OP(invd), I486OP(invd), },
- { 0x09, OP_2BYTE|OP_I486, I486OP(wbinvd), I486OP(wbinvd), },
- { 0x0B, OP_2BYTE|OP_PENTIUM, PENTIUMOP(ud2), PENTIUMOP(ud2), },
- { 0x10, OP_2BYTE|OP_SSE, SSEOP(movups_r128_rm128), SSEOP(movups_r128_rm128), },
- { 0x11, OP_2BYTE|OP_SSE, SSEOP(movups_rm128_r128), SSEOP(movups_rm128_r128), },
- { 0x12, OP_2BYTE|OP_SSE, SSEOP(movlps_r128_m64), SSEOP(movlps_r128_m64), },
- { 0x13, OP_2BYTE|OP_SSE, SSEOP(movlps_m64_r128), SSEOP(movlps_m64_r128), },
- { 0x14, OP_2BYTE|OP_SSE, SSEOP(unpcklps_r128_rm128), SSEOP(unpcklps_r128_rm128), },
- { 0x15, OP_2BYTE|OP_SSE, SSEOP(unpckhps_r128_rm128), SSEOP(unpckhps_r128_rm128), },
- { 0x16, OP_2BYTE|OP_SSE, SSEOP(movhps_r128_m64), SSEOP(movhps_r128_m64), },
- { 0x17, OP_2BYTE|OP_SSE, SSEOP(movhps_m64_r128), SSEOP(movhps_m64_r128), },
- { 0x18, OP_2BYTE|OP_PENTIUM, PENTIUMOP(prefetch_m8), PENTIUMOP(prefetch_m8), },
- { 0x20, OP_2BYTE|OP_I386, I386OP(mov_r32_cr), I386OP(mov_r32_cr), },
- { 0x21, OP_2BYTE|OP_I386, I386OP(mov_r32_dr), I386OP(mov_r32_dr), },
- { 0x22, OP_2BYTE|OP_I386, I386OP(mov_cr_r32), I386OP(mov_cr_r32), },
- { 0x22, OP_2BYTE|OP_I486, I486OP(mov_cr_r32), I486OP(mov_cr_r32), },
- { 0x23, OP_2BYTE|OP_I386, I386OP(mov_dr_r32), I386OP(mov_dr_r32), },
- { 0x24, OP_2BYTE|OP_I386, I386OP(mov_r32_tr), I386OP(mov_r32_tr), },
- { 0x26, OP_2BYTE|OP_I386, I386OP(mov_tr_r32), I386OP(mov_tr_r32), },
- { 0x28, OP_2BYTE|OP_SSE, SSEOP(movaps_r128_rm128), SSEOP(movaps_r128_rm128), },
- { 0x29, OP_2BYTE|OP_SSE, SSEOP(movaps_rm128_r128), SSEOP(movaps_rm128_r128), },
- { 0x2a, OP_2BYTE|OP_SSE, SSEOP(cvtpi2ps_r128_rm64), SSEOP(cvtpi2ps_r128_rm64), },
- { 0x2b, OP_2BYTE|OP_SSE, SSEOP(movntps_m128_r128), SSEOP(movntps_m128_r128), },
- { 0x2c, OP_2BYTE|OP_SSE, SSEOP(cvttps2pi_r64_r128m64), SSEOP(cvttps2pi_r64_r128m64),},
- { 0x2d, OP_2BYTE|OP_SSE, SSEOP(cvtps2pi_r64_r128m64), SSEOP(cvtps2pi_r64_r128m64),},
- { 0x2e, OP_2BYTE|OP_SSE, SSEOP(ucomiss_r128_r128m32), SSEOP(ucomiss_r128_r128m32),},
- { 0x2f, OP_2BYTE|OP_SSE, SSEOP(comiss_r128_r128m32), SSEOP(comiss_r128_r128m32), },
- { 0x30, OP_2BYTE|OP_PENTIUM, PENTIUMOP(wrmsr), PENTIUMOP(wrmsr), },
- { 0x31, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdtsc), PENTIUMOP(rdtsc), },
- { 0x32, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdmsr), PENTIUMOP(rdmsr), },
- { 0x40, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovo_r16_rm16), PENTIUMOP(cmovo_r32_rm32), },
- { 0x41, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovno_r16_rm16), PENTIUMOP(cmovno_r32_rm32), },
- { 0x42, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovb_r16_rm16), PENTIUMOP(cmovb_r32_rm32), },
- { 0x43, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovae_r16_rm16), PENTIUMOP(cmovae_r32_rm32), },
- { 0x44, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmove_r16_rm16), PENTIUMOP(cmove_r32_rm32), },
- { 0x45, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovne_r16_rm16), PENTIUMOP(cmovne_r32_rm32), },
- { 0x46, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovbe_r16_rm16), PENTIUMOP(cmovbe_r32_rm32), },
- { 0x47, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmova_r16_rm16), PENTIUMOP(cmova_r32_rm32), },
- { 0x48, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovs_r16_rm16), PENTIUMOP(cmovs_r32_rm32), },
- { 0x49, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovns_r16_rm16), PENTIUMOP(cmovns_r32_rm32), },
- { 0x4a, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovp_r16_rm16), PENTIUMOP(cmovp_r32_rm32), },
- { 0x4b, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovnp_r16_rm16), PENTIUMOP(cmovnp_r32_rm32), },
- { 0x4c, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovl_r16_rm16), PENTIUMOP(cmovl_r32_rm32), },
- { 0x4d, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovge_r16_rm16), PENTIUMOP(cmovge_r32_rm32), },
- { 0x4e, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovle_r16_rm16), PENTIUMOP(cmovle_r32_rm32), },
- { 0x4f, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovg_r16_rm16), PENTIUMOP(cmovg_r32_rm32), },
- { 0x50, OP_2BYTE|OP_SSE, SSEOP(movmskps_r16_r128), SSEOP(movmskps_r32_r128), },
- { 0x51, OP_2BYTE|OP_SSE, SSEOP(sqrtps_r128_rm128), SSEOP(sqrtps_r128_rm128), },
- { 0x52, OP_2BYTE|OP_SSE, SSEOP(rsqrtps_r128_rm128), SSEOP(rsqrtps_r128_rm128), },
- { 0x53, OP_2BYTE|OP_SSE, SSEOP(rcpps_r128_rm128), SSEOP(rcpps_r128_rm128), },
- { 0x54, OP_2BYTE|OP_SSE, SSEOP(andps_r128_rm128), SSEOP(andps_r128_rm128), },
- { 0x55, OP_2BYTE|OP_SSE, SSEOP(andnps_r128_rm128), SSEOP(andnps_r128_rm128), },
- { 0x56, OP_2BYTE|OP_SSE, SSEOP(orps_r128_rm128), SSEOP(orps_r128_rm128), },
- { 0x57, OP_2BYTE|OP_SSE, SSEOP(xorps), SSEOP(xorps), },
- { 0x58, OP_2BYTE|OP_SSE, SSEOP(addps), SSEOP(addps), },
- { 0x59, OP_2BYTE|OP_SSE, SSEOP(mulps), SSEOP(mulps), },
- { 0x5a, OP_2BYTE|OP_SSE, SSEOP(cvtps2pd_r128_r128m64), SSEOP(cvtps2pd_r128_r128m64),},
- { 0x5b, OP_2BYTE|OP_SSE, SSEOP(cvtdq2ps_r128_rm128), SSEOP(cvtdq2ps_r128_rm128), },
- { 0x5c, OP_2BYTE|OP_SSE, SSEOP(subps), SSEOP(subps), },
- { 0x5d, OP_2BYTE|OP_SSE, SSEOP(minps), SSEOP(minps), },
- { 0x5e, OP_2BYTE|OP_SSE, SSEOP(divps), SSEOP(divps), },
- { 0x5f, OP_2BYTE|OP_SSE, SSEOP(maxps), SSEOP(maxps), },
- { 0x60, OP_2BYTE|OP_MMX, MMXOP(punpcklbw_r64_r64m32), MMXOP(punpcklbw_r64_r64m32),},
- { 0x61, OP_2BYTE|OP_MMX, MMXOP(punpcklwd_r64_r64m32), MMXOP(punpcklwd_r64_r64m32),},
- { 0x62, OP_2BYTE|OP_MMX, MMXOP(punpckldq_r64_r64m32), MMXOP(punpckldq_r64_r64m32),},
- { 0x63, OP_2BYTE|OP_MMX, MMXOP(packsswb_r64_rm64), MMXOP(packsswb_r64_rm64), },
- { 0x64, OP_2BYTE|OP_MMX, MMXOP(pcmpgtb_r64_rm64), MMXOP(pcmpgtb_r64_rm64), },
- { 0x65, OP_2BYTE|OP_MMX, MMXOP(pcmpgtw_r64_rm64), MMXOP(pcmpgtw_r64_rm64), },
- { 0x66, OP_2BYTE|OP_MMX, MMXOP(pcmpgtd_r64_rm64), MMXOP(pcmpgtd_r64_rm64), },
- { 0x67, OP_2BYTE|OP_MMX, MMXOP(packuswb_r64_rm64), MMXOP(packuswb_r64_rm64), },
- { 0x68, OP_2BYTE|OP_MMX, MMXOP(punpckhbw_r64_rm64), MMXOP(punpckhbw_r64_rm64), },
- { 0x69, OP_2BYTE|OP_MMX, MMXOP(punpckhwd_r64_rm64), MMXOP(punpckhwd_r64_rm64), },
- { 0x6a, OP_2BYTE|OP_MMX, MMXOP(punpckhdq_r64_rm64), MMXOP(punpckhdq_r64_rm64), },
- { 0x6b, OP_2BYTE|OP_MMX, MMXOP(packssdw_r64_rm64), MMXOP(packssdw_r64_rm64), },
- { 0x6e, OP_2BYTE|OP_MMX, MMXOP(movd_r64_rm32), MMXOP(movd_r64_rm32), },
- { 0x6f, OP_2BYTE|OP_MMX, MMXOP(movq_r64_rm64), MMXOP(movq_r64_rm64), },
- { 0x70, OP_2BYTE|OP_MMX, MMXOP(pshufw_r64_rm64_i8), MMXOP(pshufw_r64_rm64_i8), },
- { 0x71, OP_2BYTE|OP_MMX, MMXOP(group_0f71), MMXOP(group_0f71), },
- { 0x72, OP_2BYTE|OP_MMX, MMXOP(group_0f72), MMXOP(group_0f72), },
- { 0x73, OP_2BYTE|OP_MMX, MMXOP(group_0f73), MMXOP(group_0f73), },
- { 0x74, OP_2BYTE|OP_CYRIX, I386OP(cyrix_unknown), I386OP(cyrix_unknown), },
- { 0x74, OP_2BYTE|OP_MMX, MMXOP(pcmpeqb_r64_rm64), MMXOP(pcmpeqb_r64_rm64), },
- { 0x75, OP_2BYTE|OP_MMX, MMXOP(pcmpeqw_r64_rm64), MMXOP(pcmpeqw_r64_rm64), },
- { 0x76, OP_2BYTE|OP_MMX, MMXOP(pcmpeqd_r64_rm64), MMXOP(pcmpeqd_r64_rm64), },
- { 0x77, OP_2BYTE|OP_MMX, MMXOP(emms), MMXOP(emms), },
- { 0x7e, OP_2BYTE|OP_MMX, MMXOP(movd_rm32_r64), MMXOP(movd_rm32_r64), },
- { 0x7f, OP_2BYTE|OP_MMX, MMXOP(movq_rm64_r64), MMXOP(movq_rm64_r64), },
- { 0x80, OP_2BYTE|OP_I386, I386OP(jo_rel16), I386OP(jo_rel32), },
- { 0x81, OP_2BYTE|OP_I386, I386OP(jno_rel16), I386OP(jno_rel32), },
- { 0x82, OP_2BYTE|OP_I386, I386OP(jc_rel16), I386OP(jc_rel32), },
- { 0x83, OP_2BYTE|OP_I386, I386OP(jnc_rel16), I386OP(jnc_rel32), },
- { 0x84, OP_2BYTE|OP_I386, I386OP(jz_rel16), I386OP(jz_rel32), },
- { 0x85, OP_2BYTE|OP_I386, I386OP(jnz_rel16), I386OP(jnz_rel32), },
- { 0x86, OP_2BYTE|OP_I386, I386OP(jbe_rel16), I386OP(jbe_rel32), },
- { 0x87, OP_2BYTE|OP_I386, I386OP(ja_rel16), I386OP(ja_rel32), },
- { 0x88, OP_2BYTE|OP_I386, I386OP(js_rel16), I386OP(js_rel32), },
- { 0x89, OP_2BYTE|OP_I386, I386OP(jns_rel16), I386OP(jns_rel32), },
- { 0x8A, OP_2BYTE|OP_I386, I386OP(jp_rel16), I386OP(jp_rel32), },
- { 0x8B, OP_2BYTE|OP_I386, I386OP(jnp_rel16), I386OP(jnp_rel32), },
- { 0x8C, OP_2BYTE|OP_I386, I386OP(jl_rel16), I386OP(jl_rel32), },
- { 0x8D, OP_2BYTE|OP_I386, I386OP(jge_rel16), I386OP(jge_rel32), },
- { 0x8E, OP_2BYTE|OP_I386, I386OP(jle_rel16), I386OP(jle_rel32), },
- { 0x8F, OP_2BYTE|OP_I386, I386OP(jg_rel16), I386OP(jg_rel32), },
- { 0x90, OP_2BYTE|OP_I386, I386OP(seto_rm8), I386OP(seto_rm8), },
- { 0x91, OP_2BYTE|OP_I386, I386OP(setno_rm8), I386OP(setno_rm8), },
- { 0x92, OP_2BYTE|OP_I386, I386OP(setc_rm8), I386OP(setc_rm8), },
- { 0x93, OP_2BYTE|OP_I386, I386OP(setnc_rm8), I386OP(setnc_rm8), },
- { 0x94, OP_2BYTE|OP_I386, I386OP(setz_rm8), I386OP(setz_rm8), },
- { 0x95, OP_2BYTE|OP_I386, I386OP(setnz_rm8), I386OP(setnz_rm8), },
- { 0x96, OP_2BYTE|OP_I386, I386OP(setbe_rm8), I386OP(setbe_rm8), },
- { 0x97, OP_2BYTE|OP_I386, I386OP(seta_rm8), I386OP(seta_rm8), },
- { 0x98, OP_2BYTE|OP_I386, I386OP(sets_rm8), I386OP(sets_rm8), },
- { 0x99, OP_2BYTE|OP_I386, I386OP(setns_rm8), I386OP(setns_rm8), },
- { 0x9A, OP_2BYTE|OP_I386, I386OP(setp_rm8), I386OP(setp_rm8), },
- { 0x9B, OP_2BYTE|OP_I386, I386OP(setnp_rm8), I386OP(setnp_rm8), },
- { 0x9C, OP_2BYTE|OP_I386, I386OP(setl_rm8), I386OP(setl_rm8), },
- { 0x9D, OP_2BYTE|OP_I386, I386OP(setge_rm8), I386OP(setge_rm8), },
- { 0x9E, OP_2BYTE|OP_I386, I386OP(setle_rm8), I386OP(setle_rm8), },
- { 0x9F, OP_2BYTE|OP_I386, I386OP(setg_rm8), I386OP(setg_rm8), },
- { 0xA0, OP_2BYTE|OP_I386, I386OP(push_fs16), I386OP(push_fs32), },
- { 0xA1, OP_2BYTE|OP_I386, I386OP(pop_fs16), I386OP(pop_fs32), },
- { 0xA2, OP_2BYTE|OP_I486, I486OP(cpuid), I486OP(cpuid), },
- { 0xA3, OP_2BYTE|OP_I386, I386OP(bt_rm16_r16), I386OP(bt_rm32_r32), },
- { 0xA4, OP_2BYTE|OP_I386, I386OP(shld16_i8), I386OP(shld32_i8), },
- { 0xA5, OP_2BYTE|OP_I386, I386OP(shld16_cl), I386OP(shld32_cl), },
- { 0xA8, OP_2BYTE|OP_I386, I386OP(push_gs16), I386OP(push_gs32), },
- { 0xA9, OP_2BYTE|OP_I386, I386OP(pop_gs16), I386OP(pop_gs32), },
- { 0xAA, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rsm), PENTIUMOP(rsm), },
- { 0xAB, OP_2BYTE|OP_I386, I386OP(bts_rm16_r16), I386OP(bts_rm32_r32), },
- { 0xAC, OP_2BYTE|OP_I386, I386OP(shrd16_i8), I386OP(shrd32_i8), },
- { 0xAD, OP_2BYTE|OP_I386, I386OP(shrd16_cl), I386OP(shrd32_cl), },
- { 0xAE, OP_2BYTE|OP_SSE, SSEOP(sse_group0fae), SSEOP(sse_group0fae), },
- { 0xAF, OP_2BYTE|OP_I386, I386OP(imul_r16_rm16), I386OP(imul_r32_rm32), },
- { 0xB0, OP_2BYTE|OP_I486, I486OP(cmpxchg_rm8_r8), I486OP(cmpxchg_rm8_r8), },
- { 0xB1, OP_2BYTE|OP_I486, I486OP(cmpxchg_rm16_r16), I486OP(cmpxchg_rm32_r32), },
- { 0xB2, OP_2BYTE|OP_I386, I386OP(lss16), I386OP(lss32), },
- { 0xB3, OP_2BYTE|OP_I386, I386OP(btr_rm16_r16), I386OP(btr_rm32_r32), },
- { 0xB4, OP_2BYTE|OP_I386, I386OP(lfs16), I386OP(lfs32), },
- { 0xB5, OP_2BYTE|OP_I386, I386OP(lgs16), I386OP(lgs32), },
- { 0xB6, OP_2BYTE|OP_I386, I386OP(movzx_r16_rm8), I386OP(movzx_r32_rm8), },
- { 0xB7, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movzx_r32_rm16), },
- { 0xBA, OP_2BYTE|OP_I386, I386OP(group0FBA_16), I386OP(group0FBA_32), },
- { 0xBB, OP_2BYTE|OP_I386, I386OP(btc_rm16_r16), I386OP(btc_rm32_r32), },
- { 0xBC, OP_2BYTE|OP_I386, I386OP(bsf_r16_rm16), I386OP(bsf_r32_rm32), },
- { 0xBD, OP_2BYTE|OP_I386, I386OP(bsr_r16_rm16), I386OP(bsr_r32_rm32), },
- { 0xBE, OP_2BYTE|OP_I386, I386OP(movsx_r16_rm8), I386OP(movsx_r32_rm8), },
- { 0xBF, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movsx_r32_rm16), },
- { 0xC0, OP_2BYTE|OP_I486, I486OP(xadd_rm8_r8), I486OP(xadd_rm8_r8), },
- { 0xC1, OP_2BYTE|OP_I486, I486OP(xadd_rm16_r16), I486OP(xadd_rm32_r32), },
- { 0xC2, OP_2BYTE|OP_SSE, SSEOP(cmpps_r128_rm128_i8), SSEOP(cmpps_r128_rm128_i8), },
- { 0xC3, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movnti_m16_r16), PENTIUMOP(movnti_m32_r32), },
- { 0xC4, OP_2BYTE|OP_SSE, SSEOP(pinsrw_r64_r16m16_i8), SSEOP(pinsrw_r64_r32m16_i8),},
- { 0xC5, OP_2BYTE|OP_SSE, SSEOP(pextrw_r16_r64_i8), SSEOP(pextrw_r32_r64_i8), },
- { 0xC6, OP_2BYTE|OP_SSE, SSEOP(shufps), SSEOP(shufps), },
- { 0xC7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmpxchg8b_m64), PENTIUMOP(cmpxchg8b_m64), },
- { 0xC8, OP_2BYTE|OP_I486, I486OP(bswap_eax), I486OP(bswap_eax), },
- { 0xC9, OP_2BYTE|OP_I486, I486OP(bswap_ecx), I486OP(bswap_ecx), },
- { 0xCA, OP_2BYTE|OP_I486, I486OP(bswap_edx), I486OP(bswap_edx), },
- { 0xCB, OP_2BYTE|OP_I486, I486OP(bswap_ebx), I486OP(bswap_ebx), },
- { 0xCC, OP_2BYTE|OP_I486, I486OP(bswap_esp), I486OP(bswap_esp), },
- { 0xCD, OP_2BYTE|OP_I486, I486OP(bswap_ebp), I486OP(bswap_ebp), },
- { 0xCE, OP_2BYTE|OP_I486, I486OP(bswap_esi), I486OP(bswap_esi), },
- { 0xCF, OP_2BYTE|OP_I486, I486OP(bswap_edi), I486OP(bswap_edi), },
- { 0xD1, OP_2BYTE|OP_MMX, MMXOP(psrlw_r64_rm64), MMXOP(psrlw_r64_rm64), },
- { 0xD2, OP_2BYTE|OP_MMX, MMXOP(psrld_r64_rm64), MMXOP(psrld_r64_rm64), },
- { 0xD3, OP_2BYTE|OP_MMX, MMXOP(psrlq_r64_rm64), MMXOP(psrlq_r64_rm64), },
- { 0xD4, OP_2BYTE|OP_MMX, MMXOP(paddq_r64_rm64), MMXOP(paddq_r64_rm64), },
- { 0xD5, OP_2BYTE|OP_MMX, MMXOP(pmullw_r64_rm64), MMXOP(pmullw_r64_rm64), },
- { 0xD7, OP_2BYTE|OP_SSE, SSEOP(pmovmskb_r16_r64), SSEOP(pmovmskb_r32_r64), },
- { 0xD8, OP_2BYTE|OP_MMX, MMXOP(psubusb_r64_rm64), MMXOP(psubusb_r64_rm64), },
- { 0xD9, OP_2BYTE|OP_MMX, MMXOP(psubusw_r64_rm64), MMXOP(psubusw_r64_rm64), },
- { 0xDA, OP_2BYTE|OP_SSE, SSEOP(pminub_r64_rm64), SSEOP(pminub_r64_rm64), },
- { 0xDB, OP_2BYTE|OP_MMX, MMXOP(pand_r64_rm64), MMXOP(pand_r64_rm64), },
- { 0xDC, OP_2BYTE|OP_MMX, MMXOP(paddusb_r64_rm64), MMXOP(paddusb_r64_rm64), },
- { 0xDD, OP_2BYTE|OP_MMX, MMXOP(paddusw_r64_rm64), MMXOP(paddusw_r64_rm64), },
- { 0xDE, OP_2BYTE|OP_SSE, SSEOP(pmaxub_r64_rm64), SSEOP(pmaxub_r64_rm64), },
- { 0xDF, OP_2BYTE|OP_MMX, MMXOP(pandn_r64_rm64), MMXOP(pandn_r64_rm64), },
- { 0xE0, OP_2BYTE|OP_SSE, SSEOP(pavgb_r64_rm64), SSEOP(pavgb_r64_rm64), },
- { 0xE1, OP_2BYTE|OP_MMX, MMXOP(psraw_r64_rm64), MMXOP(psraw_r64_rm64), },
- { 0xE2, OP_2BYTE|OP_MMX, MMXOP(psrad_r64_rm64), MMXOP(psrad_r64_rm64), },
- { 0xE3, OP_2BYTE|OP_SSE, SSEOP(pavgw_r64_rm64), SSEOP(pavgw_r64_rm64), },
- { 0xE4, OP_2BYTE|OP_SSE, SSEOP(pmulhuw_r64_rm64), SSEOP(pmulhuw_r64_rm64), },
- { 0xE5, OP_2BYTE|OP_MMX, MMXOP(pmulhw_r64_rm64), MMXOP(pmulhw_r64_rm64), },
- { 0xE7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movntq_m64_r64), PENTIUMOP(movntq_m64_r64), },
- { 0xE8, OP_2BYTE|OP_MMX, MMXOP(psubsb_r64_rm64), MMXOP(psubsb_r64_rm64), },
- { 0xE9, OP_2BYTE|OP_MMX, MMXOP(psubsw_r64_rm64), MMXOP(psubsw_r64_rm64), },
- { 0xEA, OP_2BYTE|OP_SSE, SSEOP(pminsw_r64_rm64), SSEOP(pminsw_r64_rm64), },
- { 0xEB, OP_2BYTE|OP_MMX, MMXOP(por_r64_rm64), MMXOP(por_r64_rm64), },
- { 0xEC, OP_2BYTE|OP_MMX, MMXOP(paddsb_r64_rm64), MMXOP(paddsb_r64_rm64), },
- { 0xED, OP_2BYTE|OP_MMX, MMXOP(paddsw_r64_rm64), MMXOP(paddsw_r64_rm64), },
- { 0xEE, OP_2BYTE|OP_SSE, SSEOP(pmaxsw_r64_rm64), SSEOP(pmaxsw_r64_rm64), },
- { 0xEF, OP_2BYTE|OP_MMX, MMXOP(pxor_r64_rm64), MMXOP(pxor_r64_rm64), },
- { 0xF1, OP_2BYTE|OP_MMX, MMXOP(psllw_r64_rm64), MMXOP(psllw_r64_rm64), },
- { 0xF2, OP_2BYTE|OP_MMX, MMXOP(pslld_r64_rm64), MMXOP(pslld_r64_rm64), },
- { 0xF3, OP_2BYTE|OP_MMX, MMXOP(psllq_r64_rm64), MMXOP(psllq_r64_rm64), },
- { 0xF4, OP_2BYTE|OP_SSE, SSEOP(pmuludq_r64_rm64), SSEOP(pmuludq_r64_rm64), },
- { 0xF5, OP_2BYTE|OP_MMX, MMXOP(pmaddwd_r64_rm64), MMXOP(pmaddwd_r64_rm64), },
- { 0xF6, OP_2BYTE|OP_SSE, SSEOP(psadbw_r64_rm64), SSEOP(psadbw_r64_rm64), },
- { 0xf7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(maskmovq_r64_r64), PENTIUMOP(maskmovq_r64_r64),},
- { 0xF8, OP_2BYTE|OP_MMX, MMXOP(psubb_r64_rm64), MMXOP(psubb_r64_rm64), },
- { 0xF9, OP_2BYTE|OP_MMX, MMXOP(psubw_r64_rm64), MMXOP(psubw_r64_rm64), },
- { 0xFA, OP_2BYTE|OP_MMX, MMXOP(psubd_r64_rm64), MMXOP(psubd_r64_rm64), },
- { 0xFB, OP_2BYTE|OP_SSE, SSEOP(psubq_r64_rm64), SSEOP(psubq_r64_rm64), },
- { 0xFC, OP_2BYTE|OP_MMX, MMXOP(paddb_r64_rm64), MMXOP(paddb_r64_rm64), },
- { 0xFD, OP_2BYTE|OP_MMX, MMXOP(paddw_r64_rm64), MMXOP(paddw_r64_rm64), },
- { 0xFE, OP_2BYTE|OP_MMX, MMXOP(paddd_r64_rm64), MMXOP(paddd_r64_rm64), },
+ { 0x00, OP_2BYTE|OP_I386, &i386_device::i386_group0F00_16, &i386_device::i386_group0F00_32, },
+ { 0x01, OP_2BYTE|OP_I386, &i386_device::i386_group0F01_16, &i386_device::i386_group0F01_32, },
+ { 0x01, OP_2BYTE|OP_I486, &i386_device::i486_group0F01_16, &i386_device::i486_group0F01_32, },
+ { 0x02, OP_2BYTE|OP_I386, &i386_device::i386_lar_r16_rm16, &i386_device::i386_lar_r32_rm32, },
+ { 0x03, OP_2BYTE|OP_I386, &i386_device::i386_lsl_r16_rm16, &i386_device::i386_lsl_r32_rm32, },
+ { 0x06, OP_2BYTE|OP_I386, &i386_device::i386_clts, &i386_device::i386_clts, },
+ { 0x07, OP_2BYTE|OP_I386, &i386_device::i386_loadall, &i386_device::i386_loadall, },
+ { 0x08, OP_2BYTE|OP_I486, &i386_device::i486_invd, &i386_device::i486_invd, },
+ { 0x09, OP_2BYTE|OP_I486, &i386_device::i486_wbinvd, &i386_device::i486_wbinvd, },
+ { 0x0B, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_ud2, &i386_device::pentium_ud2, },
+ { 0x10, OP_2BYTE|OP_SSE, &i386_device::sse_movups_r128_rm128, &i386_device::sse_movups_r128_rm128, },
+ { 0x11, OP_2BYTE|OP_SSE, &i386_device::sse_movups_rm128_r128, &i386_device::sse_movups_rm128_r128, },
+ { 0x12, OP_2BYTE|OP_SSE, &i386_device::sse_movlps_r128_m64, &i386_device::sse_movlps_r128_m64, },
+ { 0x13, OP_2BYTE|OP_SSE, &i386_device::sse_movlps_m64_r128, &i386_device::sse_movlps_m64_r128, },
+ { 0x14, OP_2BYTE|OP_SSE, &i386_device::sse_unpcklps_r128_rm128, &i386_device::sse_unpcklps_r128_rm128, },
+ { 0x15, OP_2BYTE|OP_SSE, &i386_device::sse_unpckhps_r128_rm128, &i386_device::sse_unpckhps_r128_rm128, },
+ { 0x16, OP_2BYTE|OP_SSE, &i386_device::sse_movhps_r128_m64, &i386_device::sse_movhps_r128_m64, },
+ { 0x17, OP_2BYTE|OP_SSE, &i386_device::sse_movhps_m64_r128, &i386_device::sse_movhps_m64_r128, },
+ { 0x18, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_prefetch_m8, &i386_device::pentium_prefetch_m8, },
+ { 0x20, OP_2BYTE|OP_I386, &i386_device::i386_mov_r32_cr, &i386_device::i386_mov_r32_cr, },
+ { 0x21, OP_2BYTE|OP_I386, &i386_device::i386_mov_r32_dr, &i386_device::i386_mov_r32_dr, },
+ { 0x22, OP_2BYTE|OP_I386, &i386_device::i386_mov_cr_r32, &i386_device::i386_mov_cr_r32, },
+ { 0x22, OP_2BYTE|OP_I486, &i386_device::i486_mov_cr_r32, &i386_device::i486_mov_cr_r32, },
+ { 0x23, OP_2BYTE|OP_I386, &i386_device::i386_mov_dr_r32, &i386_device::i386_mov_dr_r32, },
+ { 0x24, OP_2BYTE|OP_I386, &i386_device::i386_mov_r32_tr, &i386_device::i386_mov_r32_tr, },
+ { 0x26, OP_2BYTE|OP_I386, &i386_device::i386_mov_tr_r32, &i386_device::i386_mov_tr_r32, },
+ { 0x28, OP_2BYTE|OP_SSE, &i386_device::sse_movaps_r128_rm128, &i386_device::sse_movaps_r128_rm128, },
+ { 0x29, OP_2BYTE|OP_SSE, &i386_device::sse_movaps_rm128_r128, &i386_device::sse_movaps_rm128_r128, },
+ { 0x2a, OP_2BYTE|OP_SSE, &i386_device::sse_cvtpi2ps_r128_rm64, &i386_device::sse_cvtpi2ps_r128_rm64, },
+ { 0x2b, OP_2BYTE|OP_SSE, &i386_device::sse_movntps_m128_r128, &i386_device::sse_movntps_m128_r128, },
+ { 0x2c, OP_2BYTE|OP_SSE, &i386_device::sse_cvttps2pi_r64_r128m64, &i386_device::sse_cvttps2pi_r64_r128m64,},
+ { 0x2d, OP_2BYTE|OP_SSE, &i386_device::sse_cvtps2pi_r64_r128m64, &i386_device::sse_cvtps2pi_r64_r128m64,},
+ { 0x2e, OP_2BYTE|OP_SSE, &i386_device::sse_ucomiss_r128_r128m32, &i386_device::sse_ucomiss_r128_r128m32,},
+ { 0x2f, OP_2BYTE|OP_SSE, &i386_device::sse_comiss_r128_r128m32, &i386_device::sse_comiss_r128_r128m32, },
+ { 0x30, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_wrmsr, &i386_device::pentium_wrmsr, },
+ { 0x31, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_rdtsc, &i386_device::pentium_rdtsc, },
+ { 0x32, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_rdmsr, &i386_device::pentium_rdmsr, },
+ { 0x40, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, },
+ { 0x41, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovno_r16_rm16, &i386_device::pentium_cmovno_r32_rm32, },
+ { 0x42, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovb_r16_rm16, &i386_device::pentium_cmovb_r32_rm32, },
+ { 0x43, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovae_r16_rm16, &i386_device::pentium_cmovae_r32_rm32, },
+ { 0x44, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmove_r16_rm16, &i386_device::pentium_cmove_r32_rm32, },
+ { 0x45, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovne_r16_rm16, &i386_device::pentium_cmovne_r32_rm32, },
+ { 0x46, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovbe_r16_rm16, &i386_device::pentium_cmovbe_r32_rm32, },
+ { 0x47, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmova_r16_rm16, &i386_device::pentium_cmova_r32_rm32, },
+ { 0x48, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovs_r16_rm16, &i386_device::pentium_cmovs_r32_rm32, },
+ { 0x49, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovns_r16_rm16, &i386_device::pentium_cmovns_r32_rm32, },
+ { 0x4a, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovp_r16_rm16, &i386_device::pentium_cmovp_r32_rm32, },
+ { 0x4b, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovnp_r16_rm16, &i386_device::pentium_cmovnp_r32_rm32, },
+ { 0x4c, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovl_r16_rm16, &i386_device::pentium_cmovl_r32_rm32, },
+ { 0x4d, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovge_r16_rm16, &i386_device::pentium_cmovge_r32_rm32, },
+ { 0x4e, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovle_r16_rm16, &i386_device::pentium_cmovle_r32_rm32, },
+ { 0x4f, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovg_r16_rm16, &i386_device::pentium_cmovg_r32_rm32, },
+ { 0x50, OP_2BYTE|OP_SSE, &i386_device::sse_movmskps_r16_r128, &i386_device::sse_movmskps_r32_r128, },
+ { 0x51, OP_2BYTE|OP_SSE, &i386_device::sse_sqrtps_r128_rm128, &i386_device::sse_sqrtps_r128_rm128, },
+ { 0x52, OP_2BYTE|OP_SSE, &i386_device::sse_rsqrtps_r128_rm128, &i386_device::sse_rsqrtps_r128_rm128, },
+ { 0x53, OP_2BYTE|OP_SSE, &i386_device::sse_rcpps_r128_rm128, &i386_device::sse_rcpps_r128_rm128, },
+ { 0x54, OP_2BYTE|OP_SSE, &i386_device::sse_andps_r128_rm128, &i386_device::sse_andps_r128_rm128, },
+ { 0x55, OP_2BYTE|OP_SSE, &i386_device::sse_andnps_r128_rm128, &i386_device::sse_andnps_r128_rm128, },
+ { 0x56, OP_2BYTE|OP_SSE, &i386_device::sse_orps_r128_rm128, &i386_device::sse_orps_r128_rm128, },
+ { 0x57, OP_2BYTE|OP_SSE, &i386_device::sse_xorps, &i386_device::sse_xorps, },
+ { 0x58, OP_2BYTE|OP_SSE, &i386_device::sse_addps, &i386_device::sse_addps, },
+ { 0x59, OP_2BYTE|OP_SSE, &i386_device::sse_mulps, &i386_device::sse_mulps, },
+ { 0x5a, OP_2BYTE|OP_SSE, &i386_device::sse_cvtps2pd_r128_r128m64, &i386_device::sse_cvtps2pd_r128_r128m64,},
+ { 0x5b, OP_2BYTE|OP_SSE, &i386_device::sse_cvtdq2ps_r128_rm128, &i386_device::sse_cvtdq2ps_r128_rm128, },
+ { 0x5c, OP_2BYTE|OP_SSE, &i386_device::sse_subps, &i386_device::sse_subps, },
+ { 0x5d, OP_2BYTE|OP_SSE, &i386_device::sse_minps, &i386_device::sse_minps, },
+ { 0x5e, OP_2BYTE|OP_SSE, &i386_device::sse_divps, &i386_device::sse_divps, },
+ { 0x5f, OP_2BYTE|OP_SSE, &i386_device::sse_maxps, &i386_device::sse_maxps, },
+ { 0x60, OP_2BYTE|OP_MMX, &i386_device::mmx_punpcklbw_r64_r64m32, &i386_device::mmx_punpcklbw_r64_r64m32,},
+ { 0x61, OP_2BYTE|OP_MMX, &i386_device::mmx_punpcklwd_r64_r64m32, &i386_device::mmx_punpcklwd_r64_r64m32,},
+ { 0x62, OP_2BYTE|OP_MMX, &i386_device::mmx_punpckldq_r64_r64m32, &i386_device::mmx_punpckldq_r64_r64m32,},
+ { 0x63, OP_2BYTE|OP_MMX, &i386_device::mmx_packsswb_r64_rm64, &i386_device::mmx_packsswb_r64_rm64, },
+ { 0x64, OP_2BYTE|OP_MMX, &i386_device::mmx_pcmpgtb_r64_rm64, &i386_device::mmx_pcmpgtb_r64_rm64, },
+ { 0x65, OP_2BYTE|OP_MMX, &i386_device::mmx_pcmpgtw_r64_rm64, &i386_device::mmx_pcmpgtw_r64_rm64, },
+ { 0x66, OP_2BYTE|OP_MMX, &i386_device::mmx_pcmpgtd_r64_rm64, &i386_device::mmx_pcmpgtd_r64_rm64, },
+ { 0x67, OP_2BYTE|OP_MMX, &i386_device::mmx_packuswb_r64_rm64, &i386_device::mmx_packuswb_r64_rm64, },
+ { 0x68, OP_2BYTE|OP_MMX, &i386_device::mmx_punpckhbw_r64_rm64, &i386_device::mmx_punpckhbw_r64_rm64, },
+ { 0x69, OP_2BYTE|OP_MMX, &i386_device::mmx_punpckhwd_r64_rm64, &i386_device::mmx_punpckhwd_r64_rm64, },
+ { 0x6a, OP_2BYTE|OP_MMX, &i386_device::mmx_punpckhdq_r64_rm64, &i386_device::mmx_punpckhdq_r64_rm64, },
+ { 0x6b, OP_2BYTE|OP_MMX, &i386_device::mmx_packssdw_r64_rm64, &i386_device::mmx_packssdw_r64_rm64, },
+ { 0x6e, OP_2BYTE|OP_MMX, &i386_device::mmx_movd_r64_rm32, &i386_device::mmx_movd_r64_rm32, },
+ { 0x6f, OP_2BYTE|OP_MMX, &i386_device::mmx_movq_r64_rm64, &i386_device::mmx_movq_r64_rm64, },
+ { 0x70, OP_2BYTE|OP_MMX, &i386_device::mmx_pshufw_r64_rm64_i8, &i386_device::mmx_pshufw_r64_rm64_i8, },
+ { 0x71, OP_2BYTE|OP_MMX, &i386_device::mmx_group_0f71, &i386_device::mmx_group_0f71, },
+ { 0x72, OP_2BYTE|OP_MMX, &i386_device::mmx_group_0f72, &i386_device::mmx_group_0f72, },
+ { 0x73, OP_2BYTE|OP_MMX, &i386_device::mmx_group_0f73, &i386_device::mmx_group_0f73, },
+ { 0x74, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_unknown, &i386_device::i386_cyrix_unknown, },
+ { 0x74, OP_2BYTE|OP_MMX, &i386_device::mmx_pcmpeqb_r64_rm64, &i386_device::mmx_pcmpeqb_r64_rm64, },
+ { 0x75, OP_2BYTE|OP_MMX, &i386_device::mmx_pcmpeqw_r64_rm64, &i386_device::mmx_pcmpeqw_r64_rm64, },
+ { 0x76, OP_2BYTE|OP_MMX, &i386_device::mmx_pcmpeqd_r64_rm64, &i386_device::mmx_pcmpeqd_r64_rm64, },
+ { 0x77, OP_2BYTE|OP_MMX, &i386_device::mmx_emms, &i386_device::mmx_emms, },
+ { 0x7e, OP_2BYTE|OP_MMX, &i386_device::mmx_movd_rm32_r64, &i386_device::mmx_movd_rm32_r64, },
+ { 0x7f, OP_2BYTE|OP_MMX, &i386_device::mmx_movq_rm64_r64, &i386_device::mmx_movq_rm64_r64, },
+ { 0x80, OP_2BYTE|OP_I386, &i386_device::i386_jo_rel16, &i386_device::i386_jo_rel32, },
+ { 0x81, OP_2BYTE|OP_I386, &i386_device::i386_jno_rel16, &i386_device::i386_jno_rel32, },
+ { 0x82, OP_2BYTE|OP_I386, &i386_device::i386_jc_rel16, &i386_device::i386_jc_rel32, },
+ { 0x83, OP_2BYTE|OP_I386, &i386_device::i386_jnc_rel16, &i386_device::i386_jnc_rel32, },
+ { 0x84, OP_2BYTE|OP_I386, &i386_device::i386_jz_rel16, &i386_device::i386_jz_rel32, },
+ { 0x85, OP_2BYTE|OP_I386, &i386_device::i386_jnz_rel16, &i386_device::i386_jnz_rel32, },
+ { 0x86, OP_2BYTE|OP_I386, &i386_device::i386_jbe_rel16, &i386_device::i386_jbe_rel32, },
+ { 0x87, OP_2BYTE|OP_I386, &i386_device::i386_ja_rel16, &i386_device::i386_ja_rel32, },
+ { 0x88, OP_2BYTE|OP_I386, &i386_device::i386_js_rel16, &i386_device::i386_js_rel32, },
+ { 0x89, OP_2BYTE|OP_I386, &i386_device::i386_jns_rel16, &i386_device::i386_jns_rel32, },
+ { 0x8A, OP_2BYTE|OP_I386, &i386_device::i386_jp_rel16, &i386_device::i386_jp_rel32, },
+ { 0x8B, OP_2BYTE|OP_I386, &i386_device::i386_jnp_rel16, &i386_device::i386_jnp_rel32, },
+ { 0x8C, OP_2BYTE|OP_I386, &i386_device::i386_jl_rel16, &i386_device::i386_jl_rel32, },
+ { 0x8D, OP_2BYTE|OP_I386, &i386_device::i386_jge_rel16, &i386_device::i386_jge_rel32, },
+ { 0x8E, OP_2BYTE|OP_I386, &i386_device::i386_jle_rel16, &i386_device::i386_jle_rel32, },
+ { 0x8F, OP_2BYTE|OP_I386, &i386_device::i386_jg_rel16, &i386_device::i386_jg_rel32, },
+ { 0x90, OP_2BYTE|OP_I386, &i386_device::i386_seto_rm8, &i386_device::i386_seto_rm8, },
+ { 0x91, OP_2BYTE|OP_I386, &i386_device::i386_setno_rm8, &i386_device::i386_setno_rm8, },
+ { 0x92, OP_2BYTE|OP_I386, &i386_device::i386_setc_rm8, &i386_device::i386_setc_rm8, },
+ { 0x93, OP_2BYTE|OP_I386, &i386_device::i386_setnc_rm8, &i386_device::i386_setnc_rm8, },
+ { 0x94, OP_2BYTE|OP_I386, &i386_device::i386_setz_rm8, &i386_device::i386_setz_rm8, },
+ { 0x95, OP_2BYTE|OP_I386, &i386_device::i386_setnz_rm8, &i386_device::i386_setnz_rm8, },
+ { 0x96, OP_2BYTE|OP_I386, &i386_device::i386_setbe_rm8, &i386_device::i386_setbe_rm8, },
+ { 0x97, OP_2BYTE|OP_I386, &i386_device::i386_seta_rm8, &i386_device::i386_seta_rm8, },
+ { 0x98, OP_2BYTE|OP_I386, &i386_device::i386_sets_rm8, &i386_device::i386_sets_rm8, },
+ { 0x99, OP_2BYTE|OP_I386, &i386_device::i386_setns_rm8, &i386_device::i386_setns_rm8, },
+ { 0x9A, OP_2BYTE|OP_I386, &i386_device::i386_setp_rm8, &i386_device::i386_setp_rm8, },
+ { 0x9B, OP_2BYTE|OP_I386, &i386_device::i386_setnp_rm8, &i386_device::i386_setnp_rm8, },
+ { 0x9C, OP_2BYTE|OP_I386, &i386_device::i386_setl_rm8, &i386_device::i386_setl_rm8, },
+ { 0x9D, OP_2BYTE|OP_I386, &i386_device::i386_setge_rm8, &i386_device::i386_setge_rm8, },
+ { 0x9E, OP_2BYTE|OP_I386, &i386_device::i386_setle_rm8, &i386_device::i386_setle_rm8, },
+ { 0x9F, OP_2BYTE|OP_I386, &i386_device::i386_setg_rm8, &i386_device::i386_setg_rm8, },
+ { 0xA0, OP_2BYTE|OP_I386, &i386_device::i386_push_fs16, &i386_device::i386_push_fs32, },
+ { 0xA1, OP_2BYTE|OP_I386, &i386_device::i386_pop_fs16, &i386_device::i386_pop_fs32, },
+ { 0xA2, OP_2BYTE|OP_I486, &i386_device::i486_cpuid, &i386_device::i486_cpuid, },
+ { 0xA3, OP_2BYTE|OP_I386, &i386_device::i386_bt_rm16_r16, &i386_device::i386_bt_rm32_r32, },
+ { 0xA4, OP_2BYTE|OP_I386, &i386_device::i386_shld16_i8, &i386_device::i386_shld32_i8, },
+ { 0xA5, OP_2BYTE|OP_I386, &i386_device::i386_shld16_cl, &i386_device::i386_shld32_cl, },
+ { 0xA8, OP_2BYTE|OP_I386, &i386_device::i386_push_gs16, &i386_device::i386_push_gs32, },
+ { 0xA9, OP_2BYTE|OP_I386, &i386_device::i386_pop_gs16, &i386_device::i386_pop_gs32, },
+ { 0xAA, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_rsm, &i386_device::pentium_rsm, },
+ { 0xAB, OP_2BYTE|OP_I386, &i386_device::i386_bts_rm16_r16, &i386_device::i386_bts_rm32_r32, },
+ { 0xAC, OP_2BYTE|OP_I386, &i386_device::i386_shrd16_i8, &i386_device::i386_shrd32_i8, },
+ { 0xAD, OP_2BYTE|OP_I386, &i386_device::i386_shrd16_cl, &i386_device::i386_shrd32_cl, },
+ { 0xAE, OP_2BYTE|OP_SSE, &i386_device::sse_sse_group0fae, &i386_device::sse_sse_group0fae, },
+ { 0xAF, OP_2BYTE|OP_I386, &i386_device::i386_imul_r16_rm16, &i386_device::i386_imul_r32_rm32, },
+ { 0xB0, OP_2BYTE|OP_I486, &i386_device::i486_cmpxchg_rm8_r8, &i386_device::i486_cmpxchg_rm8_r8, },
+ { 0xB1, OP_2BYTE|OP_I486, &i386_device::i486_cmpxchg_rm16_r16, &i386_device::i486_cmpxchg_rm32_r32, },
+ { 0xB2, OP_2BYTE|OP_I386, &i386_device::i386_lss16, &i386_device::i386_lss32, },
+ { 0xB3, OP_2BYTE|OP_I386, &i386_device::i386_btr_rm16_r16, &i386_device::i386_btr_rm32_r32, },
+ { 0xB4, OP_2BYTE|OP_I386, &i386_device::i386_lfs16, &i386_device::i386_lfs32, },
+ { 0xB5, OP_2BYTE|OP_I386, &i386_device::i386_lgs16, &i386_device::i386_lgs32, },
+ { 0xB6, OP_2BYTE|OP_I386, &i386_device::i386_movzx_r16_rm8, &i386_device::i386_movzx_r32_rm8, },
+ { 0xB7, OP_2BYTE|OP_I386, &i386_device::i386_invalid, &i386_device::i386_movzx_r32_rm16, },
+ { 0xBA, OP_2BYTE|OP_I386, &i386_device::i386_group0FBA_16, &i386_device::i386_group0FBA_32, },
+ { 0xBB, OP_2BYTE|OP_I386, &i386_device::i386_btc_rm16_r16, &i386_device::i386_btc_rm32_r32, },
+ { 0xBC, OP_2BYTE|OP_I386, &i386_device::i386_bsf_r16_rm16, &i386_device::i386_bsf_r32_rm32, },
+ { 0xBD, OP_2BYTE|OP_I386, &i386_device::i386_bsr_r16_rm16, &i386_device::i386_bsr_r32_rm32, },
+ { 0xBE, OP_2BYTE|OP_I386, &i386_device::i386_movsx_r16_rm8, &i386_device::i386_movsx_r32_rm8, },
+ { 0xBF, OP_2BYTE|OP_I386, &i386_device::i386_invalid, &i386_device::i386_movsx_r32_rm16, },
+ { 0xC0, OP_2BYTE|OP_I486, &i386_device::i486_xadd_rm8_r8, &i386_device::i486_xadd_rm8_r8, },
+ { 0xC1, OP_2BYTE|OP_I486, &i386_device::i486_xadd_rm16_r16, &i386_device::i486_xadd_rm32_r32, },
+ { 0xC2, OP_2BYTE|OP_SSE, &i386_device::sse_cmpps_r128_rm128_i8, &i386_device::sse_cmpps_r128_rm128_i8, },
+ { 0xC3, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_movnti_m16_r16, &i386_device::pentium_movnti_m32_r32, },
+ { 0xC4, OP_2BYTE|OP_SSE, &i386_device::sse_pinsrw_r64_r16m16_i8, &i386_device::sse_pinsrw_r64_r32m16_i8,},
+ { 0xC5, OP_2BYTE|OP_SSE, &i386_device::sse_pextrw_r16_r64_i8, &i386_device::sse_pextrw_r32_r64_i8, },
+ { 0xC6, OP_2BYTE|OP_SSE, &i386_device::sse_shufps, &i386_device::sse_shufps, },
+ { 0xC7, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmpxchg8b_m64, &i386_device::pentium_cmpxchg8b_m64, },
+ { 0xC8, OP_2BYTE|OP_I486, &i386_device::i486_bswap_eax, &i386_device::i486_bswap_eax, },
+ { 0xC9, OP_2BYTE|OP_I486, &i386_device::i486_bswap_ecx, &i386_device::i486_bswap_ecx, },
+ { 0xCA, OP_2BYTE|OP_I486, &i386_device::i486_bswap_edx, &i386_device::i486_bswap_edx, },
+ { 0xCB, OP_2BYTE|OP_I486, &i386_device::i486_bswap_ebx, &i386_device::i486_bswap_ebx, },
+ { 0xCC, OP_2BYTE|OP_I486, &i386_device::i486_bswap_esp, &i386_device::i486_bswap_esp, },
+ { 0xCD, OP_2BYTE|OP_I486, &i386_device::i486_bswap_ebp, &i386_device::i486_bswap_ebp, },
+ { 0xCE, OP_2BYTE|OP_I486, &i386_device::i486_bswap_esi, &i386_device::i486_bswap_esi, },
+ { 0xCF, OP_2BYTE|OP_I486, &i386_device::i486_bswap_edi, &i386_device::i486_bswap_edi, },
+ { 0xD1, OP_2BYTE|OP_MMX, &i386_device::mmx_psrlw_r64_rm64, &i386_device::mmx_psrlw_r64_rm64, },
+ { 0xD2, OP_2BYTE|OP_MMX, &i386_device::mmx_psrld_r64_rm64, &i386_device::mmx_psrld_r64_rm64, },
+ { 0xD3, OP_2BYTE|OP_MMX, &i386_device::mmx_psrlq_r64_rm64, &i386_device::mmx_psrlq_r64_rm64, },
+ { 0xD4, OP_2BYTE|OP_MMX, &i386_device::mmx_paddq_r64_rm64, &i386_device::mmx_paddq_r64_rm64, },
+ { 0xD5, OP_2BYTE|OP_MMX, &i386_device::mmx_pmullw_r64_rm64, &i386_device::mmx_pmullw_r64_rm64, },
+ { 0xD7, OP_2BYTE|OP_SSE, &i386_device::sse_pmovmskb_r16_r64, &i386_device::sse_pmovmskb_r32_r64, },
+ { 0xD8, OP_2BYTE|OP_MMX, &i386_device::mmx_psubusb_r64_rm64, &i386_device::mmx_psubusb_r64_rm64, },
+ { 0xD9, OP_2BYTE|OP_MMX, &i386_device::mmx_psubusw_r64_rm64, &i386_device::mmx_psubusw_r64_rm64, },
+ { 0xDA, OP_2BYTE|OP_SSE, &i386_device::sse_pminub_r64_rm64, &i386_device::sse_pminub_r64_rm64, },
+ { 0xDB, OP_2BYTE|OP_MMX, &i386_device::mmx_pand_r64_rm64, &i386_device::mmx_pand_r64_rm64, },
+ { 0xDC, OP_2BYTE|OP_MMX, &i386_device::mmx_paddusb_r64_rm64, &i386_device::mmx_paddusb_r64_rm64, },
+ { 0xDD, OP_2BYTE|OP_MMX, &i386_device::mmx_paddusw_r64_rm64, &i386_device::mmx_paddusw_r64_rm64, },
+ { 0xDE, OP_2BYTE|OP_SSE, &i386_device::sse_pmaxub_r64_rm64, &i386_device::sse_pmaxub_r64_rm64, },
+ { 0xDF, OP_2BYTE|OP_MMX, &i386_device::mmx_pandn_r64_rm64, &i386_device::mmx_pandn_r64_rm64, },
+ { 0xE0, OP_2BYTE|OP_SSE, &i386_device::sse_pavgb_r64_rm64, &i386_device::sse_pavgb_r64_rm64, },
+ { 0xE1, OP_2BYTE|OP_MMX, &i386_device::mmx_psraw_r64_rm64, &i386_device::mmx_psraw_r64_rm64, },
+ { 0xE2, OP_2BYTE|OP_MMX, &i386_device::mmx_psrad_r64_rm64, &i386_device::mmx_psrad_r64_rm64, },
+ { 0xE3, OP_2BYTE|OP_SSE, &i386_device::sse_pavgw_r64_rm64, &i386_device::sse_pavgw_r64_rm64, },
+ { 0xE4, OP_2BYTE|OP_SSE, &i386_device::sse_pmulhuw_r64_rm64, &i386_device::sse_pmulhuw_r64_rm64, },
+ { 0xE5, OP_2BYTE|OP_MMX, &i386_device::mmx_pmulhw_r64_rm64, &i386_device::mmx_pmulhw_r64_rm64, },
+ { 0xE7, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_movntq_m64_r64, &i386_device::pentium_movntq_m64_r64, },
+ { 0xE8, OP_2BYTE|OP_MMX, &i386_device::mmx_psubsb_r64_rm64, &i386_device::mmx_psubsb_r64_rm64, },
+ { 0xE9, OP_2BYTE|OP_MMX, &i386_device::mmx_psubsw_r64_rm64, &i386_device::mmx_psubsw_r64_rm64, },
+ { 0xEA, OP_2BYTE|OP_SSE, &i386_device::sse_pminsw_r64_rm64, &i386_device::sse_pminsw_r64_rm64, },
+ { 0xEB, OP_2BYTE|OP_MMX, &i386_device::mmx_por_r64_rm64, &i386_device::mmx_por_r64_rm64, },
+ { 0xEC, OP_2BYTE|OP_MMX, &i386_device::mmx_paddsb_r64_rm64, &i386_device::mmx_paddsb_r64_rm64, },
+ { 0xED, OP_2BYTE|OP_MMX, &i386_device::mmx_paddsw_r64_rm64, &i386_device::mmx_paddsw_r64_rm64, },
+ { 0xEE, OP_2BYTE|OP_SSE, &i386_device::sse_pmaxsw_r64_rm64, &i386_device::sse_pmaxsw_r64_rm64, },
+ { 0xEF, OP_2BYTE|OP_MMX, &i386_device::mmx_pxor_r64_rm64, &i386_device::mmx_pxor_r64_rm64, },
+ { 0xF1, OP_2BYTE|OP_MMX, &i386_device::mmx_psllw_r64_rm64, &i386_device::mmx_psllw_r64_rm64, },
+ { 0xF2, OP_2BYTE|OP_MMX, &i386_device::mmx_pslld_r64_rm64, &i386_device::mmx_pslld_r64_rm64, },
+ { 0xF3, OP_2BYTE|OP_MMX, &i386_device::mmx_psllq_r64_rm64, &i386_device::mmx_psllq_r64_rm64, },
+ { 0xF4, OP_2BYTE|OP_SSE, &i386_device::sse_pmuludq_r64_rm64, &i386_device::sse_pmuludq_r64_rm64, },
+ { 0xF5, OP_2BYTE|OP_MMX, &i386_device::mmx_pmaddwd_r64_rm64, &i386_device::mmx_pmaddwd_r64_rm64, },
+ { 0xF6, OP_2BYTE|OP_SSE, &i386_device::sse_psadbw_r64_rm64, &i386_device::sse_psadbw_r64_rm64, },
+ { 0xf7, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_maskmovq_r64_r64, &i386_device::pentium_maskmovq_r64_r64,},
+ { 0xF8, OP_2BYTE|OP_MMX, &i386_device::mmx_psubb_r64_rm64, &i386_device::mmx_psubb_r64_rm64, },
+ { 0xF9, OP_2BYTE|OP_MMX, &i386_device::mmx_psubw_r64_rm64, &i386_device::mmx_psubw_r64_rm64, },
+ { 0xFA, OP_2BYTE|OP_MMX, &i386_device::mmx_psubd_r64_rm64, &i386_device::mmx_psubd_r64_rm64, },
+ { 0xFB, OP_2BYTE|OP_SSE, &i386_device::sse_psubq_r64_rm64, &i386_device::sse_psubq_r64_rm64, },
+ { 0xFC, OP_2BYTE|OP_MMX, &i386_device::mmx_paddb_r64_rm64, &i386_device::mmx_paddb_r64_rm64, },
+ { 0xFD, OP_2BYTE|OP_MMX, &i386_device::mmx_paddw_r64_rm64, &i386_device::mmx_paddw_r64_rm64, },
+ { 0xFE, OP_2BYTE|OP_MMX, &i386_device::mmx_paddd_r64_rm64, &i386_device::mmx_paddd_r64_rm64, },
/* F3 0F ?? */
- { 0x10, OP_3BYTEF3|OP_SSE, SSEOP(movss_r128_rm128), SSEOP(movss_r128_rm128), },
- { 0x11, OP_3BYTEF3|OP_SSE, SSEOP(movss_rm128_r128), SSEOP(movss_rm128_r128), },
- { 0x12, OP_3BYTEF3|OP_SSE, SSEOP(movsldup_r128_rm128), SSEOP(movsldup_r128_rm128), },
- { 0x16, OP_3BYTEF3|OP_SSE, SSEOP(movshdup_r128_rm128), SSEOP(movshdup_r128_rm128), },
- { 0x2A, OP_3BYTEF3|OP_SSE, SSEOP(cvtsi2ss_r128_rm32), SSEOP(cvtsi2ss_r128_rm32), },
- { 0x2C, OP_3BYTEF3|OP_SSE, SSEOP(cvttss2si_r32_r128m32), SSEOP(cvttss2si_r32_r128m32),},
- { 0x2D, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2si_r32_r128m32), SSEOP(cvtss2si_r32_r128m32),},
- { 0x51, OP_3BYTEF3|OP_SSE, SSEOP(sqrtss_r128_r128m32), SSEOP(sqrtss_r128_r128m32), },
- { 0x52, OP_3BYTEF3|OP_SSE, SSEOP(rsqrtss_r128_r128m32), SSEOP(rsqrtss_r128_r128m32),},
- { 0x53, OP_3BYTEF3|OP_SSE, SSEOP(rcpss_r128_r128m32), SSEOP(rcpss_r128_r128m32), },
- { 0x58, OP_3BYTEF3|OP_SSE, SSEOP(addss), SSEOP(addss), },
- { 0x59, OP_3BYTEF3|OP_SSE, SSEOP(mulss), SSEOP(mulss), },
- { 0x5A, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2sd_r128_r128m32), SSEOP(cvtss2sd_r128_r128m32),},
- { 0x5B, OP_3BYTEF3|OP_SSE, SSEOP(cvttps2dq_r128_rm128), SSEOP(cvttps2dq_r128_rm128),},
- { 0x5C, OP_3BYTEF3|OP_SSE, SSEOP(subss), SSEOP(subss), },
- { 0x5D, OP_3BYTEF3|OP_SSE, SSEOP(minss_r128_r128m32), SSEOP(minss_r128_r128m32), },
- { 0x5E, OP_3BYTEF3|OP_SSE, SSEOP(divss), SSEOP(divss), },
- { 0x5F, OP_3BYTEF3|OP_SSE, SSEOP(maxss_r128_r128m32), SSEOP(maxss_r128_r128m32), },
- { 0x6F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_r128_rm128), SSEOP(movdqu_r128_rm128), },
- { 0x70, OP_3BYTEF3|OP_SSE, SSEOP(pshufhw_r128_rm128_i8), SSEOP(pshufhw_r128_rm128_i8),},
- { 0x7E, OP_3BYTEF3|OP_SSE, SSEOP(movq_r128_r128m64), SSEOP(movq_r128_r128m64), },
- { 0x7F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_rm128_r128), SSEOP(movdqu_rm128_r128), },
- { 0xB8, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(popcnt_r16_rm16), PENTIUMOP(popcnt_r32_rm32), },
- { 0xBC, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(tzcnt_r16_rm16), PENTIUMOP(tzcnt_r32_rm32), },
- { 0xC2, OP_3BYTEF3|OP_SSE, SSEOP(cmpss_r128_r128m32_i8), SSEOP(cmpss_r128_r128m32_i8),},
- { 0xD6, OP_3BYTEF3|OP_SSE, SSEOP(movq2dq_r128_r64), SSEOP(movq2dq_r128_r64), },
- { 0xE6, OP_3BYTEF3|OP_SSE, SSEOP(cvtdq2pd_r128_r128m64), SSEOP(cvtdq2pd_r128_r128m64)}
+ { 0x10, OP_3BYTEF3|OP_SSE, &i386_device::sse_movss_r128_rm128, &i386_device::sse_movss_r128_rm128, },
+ { 0x11, OP_3BYTEF3|OP_SSE, &i386_device::sse_movss_rm128_r128, &i386_device::sse_movss_rm128_r128, },
+ { 0x12, OP_3BYTEF3|OP_SSE, &i386_device::sse_movsldup_r128_rm128, &i386_device::sse_movsldup_r128_rm128, },
+ { 0x16, OP_3BYTEF3|OP_SSE, &i386_device::sse_movshdup_r128_rm128, &i386_device::sse_movshdup_r128_rm128, },
+ { 0x2A, OP_3BYTEF3|OP_SSE, &i386_device::sse_cvtsi2ss_r128_rm32, &i386_device::sse_cvtsi2ss_r128_rm32, },
+ { 0x2C, OP_3BYTEF3|OP_SSE, &i386_device::sse_cvttss2si_r32_r128m32, &i386_device::sse_cvttss2si_r32_r128m32,},
+ { 0x2D, OP_3BYTEF3|OP_SSE, &i386_device::sse_cvtss2si_r32_r128m32, &i386_device::sse_cvtss2si_r32_r128m32,},
+ { 0x51, OP_3BYTEF3|OP_SSE, &i386_device::sse_sqrtss_r128_r128m32, &i386_device::sse_sqrtss_r128_r128m32, },
+ { 0x52, OP_3BYTEF3|OP_SSE, &i386_device::sse_rsqrtss_r128_r128m32, &i386_device::sse_rsqrtss_r128_r128m32,},
+ { 0x53, OP_3BYTEF3|OP_SSE, &i386_device::sse_rcpss_r128_r128m32, &i386_device::sse_rcpss_r128_r128m32, },
+ { 0x58, OP_3BYTEF3|OP_SSE, &i386_device::sse_addss, &i386_device::sse_addss, },
+ { 0x59, OP_3BYTEF3|OP_SSE, &i386_device::sse_mulss, &i386_device::sse_mulss, },
+ { 0x5A, OP_3BYTEF3|OP_SSE, &i386_device::sse_cvtss2sd_r128_r128m32, &i386_device::sse_cvtss2sd_r128_r128m32,},
+ { 0x5B, OP_3BYTEF3|OP_SSE, &i386_device::sse_cvttps2dq_r128_rm128, &i386_device::sse_cvttps2dq_r128_rm128,},
+ { 0x5C, OP_3BYTEF3|OP_SSE, &i386_device::sse_subss, &i386_device::sse_subss, },
+ { 0x5D, OP_3BYTEF3|OP_SSE, &i386_device::sse_minss_r128_r128m32, &i386_device::sse_minss_r128_r128m32, },
+ { 0x5E, OP_3BYTEF3|OP_SSE, &i386_device::sse_divss, &i386_device::sse_divss, },
+ { 0x5F, OP_3BYTEF3|OP_SSE, &i386_device::sse_maxss_r128_r128m32, &i386_device::sse_maxss_r128_r128m32, },
+ { 0x6F, OP_3BYTEF3|OP_SSE, &i386_device::sse_movdqu_r128_rm128, &i386_device::sse_movdqu_r128_rm128, },
+ { 0x70, OP_3BYTEF3|OP_SSE, &i386_device::sse_pshufhw_r128_rm128_i8, &i386_device::sse_pshufhw_r128_rm128_i8,},
+ { 0x7E, OP_3BYTEF3|OP_SSE, &i386_device::sse_movq_r128_r128m64, &i386_device::sse_movq_r128_r128m64, },
+ { 0x7F, OP_3BYTEF3|OP_SSE, &i386_device::sse_movdqu_rm128_r128, &i386_device::sse_movdqu_rm128_r128, },
+ { 0xB8, OP_3BYTEF3|OP_PENTIUM, &i386_device::pentium_popcnt_r16_rm16, &i386_device::pentium_popcnt_r32_rm32, },
+ { 0xBC, OP_3BYTEF3|OP_PENTIUM, &i386_device::pentium_tzcnt_r16_rm16, &i386_device::pentium_tzcnt_r32_rm32, },
+ { 0xC2, OP_3BYTEF3|OP_SSE, &i386_device::sse_cmpss_r128_r128m32_i8, &i386_device::sse_cmpss_r128_r128m32_i8,},
+ { 0xD6, OP_3BYTEF3|OP_SSE, &i386_device::sse_movq2dq_r128_r64, &i386_device::sse_movq2dq_r128_r64, },
+ { 0xE6, OP_3BYTEF3|OP_SSE, &i386_device::sse_cvtdq2pd_r128_r128m64, &i386_device::sse_cvtdq2pd_r128_r128m64}
};
diff --git a/src/emu/cpu/i386/i386priv.h b/src/emu/cpu/i386/i386priv.h
index 2178518f8a9..37b3c46927d 100644
--- a/src/emu/cpu/i386/i386priv.h
+++ b/src/emu/cpu/i386/i386priv.h
@@ -4,9 +4,6 @@
#define __I386_H__
#include "i386.h"
-#include "../../../lib/softfloat/milieu.h"
-#include "../../../lib/softfloat/softfloat.h"
-#include "cpu/vtlb.h"
//#define DEBUG_MISSING_OPCODE
@@ -268,44 +265,6 @@ enum smram_intel_p5
#define MXCSR_RC (3<<13) // Rounding Control
#define MXCSR_FZ (1<<15) // Flush to Zero
-struct I386_SREG {
- UINT16 selector;
- UINT16 flags;
- UINT32 base;
- UINT32 limit;
- int d; // Operand size
- bool valid;
-};
-
-struct I386_CALL_GATE
-{
- UINT16 segment;
- UINT16 selector;
- UINT32 offset;
- UINT8 ar; // access rights
- UINT8 dpl;
- UINT8 dword_count;
- UINT8 present;
-};
-
-struct I386_SYS_TABLE {
- UINT32 base;
- UINT16 limit;
-};
-
-struct I386_SEG_DESC {
- UINT16 segment;
- UINT16 flags;
- UINT32 base;
- UINT32 limit;
-};
-
-union I386_GPR {
- UINT32 d[8];
- UINT16 w[16];
- UINT8 b[32];
-};
-
union MMX_REG {
UINT32 d[2];
INT32 i[2];
@@ -318,198 +277,40 @@ union MMX_REG {
INT64 l;
};
-union XMM_REG {
- UINT8 b[16];
- UINT16 w[8];
- UINT32 d[4];
- UINT64 q[2];
- INT8 c[16];
- INT16 s[8];
- INT32 i[4];
- INT64 l[2];
- float f[4];
- double f64[2];
-};
-
-struct i386_state
-{
- I386_GPR reg;
- I386_SREG sreg[6];
- UINT32 eip;
- UINT32 pc;
- UINT32 prev_eip;
- UINT32 eflags;
- UINT32 eflags_mask;
- UINT8 CF;
- UINT8 DF;
- UINT8 SF;
- UINT8 OF;
- UINT8 ZF;
- UINT8 PF;
- UINT8 AF;
- UINT8 IF;
- UINT8 TF;
- UINT8 IOP1;
- UINT8 IOP2;
- UINT8 NT;
- UINT8 RF;
- UINT8 VM;
- UINT8 AC;
- UINT8 VIF;
- UINT8 VIP;
- UINT8 ID;
-
- UINT8 CPL; // current privilege level
-
- UINT8 performed_intersegment_jump;
- UINT8 delayed_interrupt_enable;
-
- UINT32 cr[5]; // Control registers
- UINT32 dr[8]; // Debug registers
- UINT32 tr[8]; // Test registers
-
- I386_SYS_TABLE gdtr; // Global Descriptor Table Register
- I386_SYS_TABLE idtr; // Interrupt Descriptor Table Register
- I386_SEG_DESC task; // Task register
- I386_SEG_DESC ldtr; // Local Descriptor Table Register
-
- UINT8 ext; // external interrupt
-
- int halted;
-
- int operand_size;
- int address_size;
- int operand_prefix;
- int address_prefix;
-
- int segment_prefix;
- int segment_override;
-
- int cycles;
- int base_cycles;
- UINT8 opcode;
-
- UINT8 irq_state;
- device_irq_acknowledge_callback irq_callback;
- legacy_cpu_device *device;
- address_space *program;
- direct_read_data *direct;
- address_space *io;
- UINT32 a20_mask;
-
- int cpuid_max_input_value_eax;
- UINT32 cpuid_id0, cpuid_id1, cpuid_id2;
- UINT32 cpu_version;
- UINT32 feature_flags;
- UINT64 tsc;
- UINT64 perfctr[2];
-
- // FPU
- floatx80 x87_reg[8];
-
- UINT16 x87_cw;
- UINT16 x87_sw;
- UINT16 x87_tw;
- UINT64 x87_data_ptr;
- UINT64 x87_inst_ptr;
- UINT16 x87_opcode;
-
- void (*opcode_table_x87_d8[256])(i386_state *cpustate, UINT8 modrm);
- void (*opcode_table_x87_d9[256])(i386_state *cpustate, UINT8 modrm);
- void (*opcode_table_x87_da[256])(i386_state *cpustate, UINT8 modrm);
- void (*opcode_table_x87_db[256])(i386_state *cpustate, UINT8 modrm);
- void (*opcode_table_x87_dc[256])(i386_state *cpustate, UINT8 modrm);
- void (*opcode_table_x87_dd[256])(i386_state *cpustate, UINT8 modrm);
- void (*opcode_table_x87_de[256])(i386_state *cpustate, UINT8 modrm);
- void (*opcode_table_x87_df[256])(i386_state *cpustate, UINT8 modrm);
-
- // SSE
- XMM_REG sse_reg[8];
- UINT32 mxcsr;
-
- void (*opcode_table1_16[256])(i386_state *cpustate);
- void (*opcode_table1_32[256])(i386_state *cpustate);
- void (*opcode_table2_16[256])(i386_state *cpustate);
- void (*opcode_table2_32[256])(i386_state *cpustate);
- void (*opcode_table366_16[256])(i386_state *cpustate);
- void (*opcode_table366_32[256])(i386_state *cpustate);
- void (*opcode_table3f2_16[256])(i386_state *cpustate);
- void (*opcode_table3f2_32[256])(i386_state *cpustate);
- void (*opcode_table3f3_16[256])(i386_state *cpustate);
- void (*opcode_table3f3_32[256])(i386_state *cpustate);
-
- UINT8 *cycle_table_pm;
- UINT8 *cycle_table_rm;
-
- vtlb_state *vtlb;
-
- bool smm;
- bool smi;
- bool smi_latched;
- bool nmi_masked;
- bool nmi_latched;
- UINT32 smbase;
- devcb_resolved_write_line smiact;
-
- // bytes in current opcode, debug only
-#ifdef DEBUG_MISSING_OPCODE
- UINT8 opcode_bytes[16];
- UINT32 opcode_pc;
- int opcode_bytes_length;
-#endif
-};
-
-INLINE i386_state *get_safe_token(device_t *device)
-{
- assert(device != NULL);
- assert(device->type() == I386 ||
- device->type() == I386SX ||
- device->type() == I486 ||
- device->type() == PENTIUM ||
- device->type() == MEDIAGX ||
- device->type() == PENTIUM_PRO ||
- device->type() == PENTIUM_MMX ||
- device->type() == PENTIUM2 ||
- device->type() == PENTIUM3 ||
- device->type() == PENTIUM4);
- return (i386_state *)downcast<legacy_cpu_device *>(device)->token();
-}
-
extern int i386_parity_table[256];
-static int i386_limit_check(i386_state *cpustate, int seg, UINT32 offset);
#define FAULT_THROW(fault,error) { throw (UINT64)(fault | (UINT64)error << 32); }
-#define PF_THROW(error) { cpustate->cr[2] = address; FAULT_THROW(FAULT_PF,error); }
+#define PF_THROW(error) { m_cr[2] = address; FAULT_THROW(FAULT_PF,error); }
-#define PROTECTED_MODE (cpustate->cr[0] & 0x1)
-#define STACK_32BIT (cpustate->sreg[SS].d)
-#define V8086_MODE (cpustate->VM)
-#define NESTED_TASK (cpustate->NT)
-#define WP (cpustate->cr[0] & 0x10000)
+#define PROTECTED_MODE (m_cr[0] & 0x1)
+#define STACK_32BIT (m_sreg[SS].d)
+#define V8086_MODE (m_VM)
+#define NESTED_TASK (m_NT)
+#define WP (m_cr[0] & 0x10000)
-#define SetOF_Add32(r,s,d) (cpustate->OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80000000) ? 1: 0)
-#define SetOF_Add16(r,s,d) (cpustate->OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? 1 : 0)
-#define SetOF_Add8(r,s,d) (cpustate->OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? 1 : 0)
+#define SetOF_Add32(r,s,d) (m_OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80000000) ? 1: 0)
+#define SetOF_Add16(r,s,d) (m_OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? 1 : 0)
+#define SetOF_Add8(r,s,d) (m_OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? 1 : 0)
-#define SetOF_Sub32(r,s,d) (cpustate->OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80000000) ? 1 : 0)
-#define SetOF_Sub16(r,s,d) (cpustate->OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? 1 : 0)
-#define SetOF_Sub8(r,s,d) (cpustate->OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? 1 : 0)
+#define SetOF_Sub32(r,s,d) (m_OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80000000) ? 1 : 0)
+#define SetOF_Sub16(r,s,d) (m_OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? 1 : 0)
+#define SetOF_Sub8(r,s,d) (m_OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? 1 : 0)
-#define SetCF8(x) {cpustate->CF = ((x) & 0x100) ? 1 : 0; }
-#define SetCF16(x) {cpustate->CF = ((x) & 0x10000) ? 1 : 0; }
-#define SetCF32(x) {cpustate->CF = ((x) & (((UINT64)1) << 32)) ? 1 : 0; }
+#define SetCF8(x) {m_CF = ((x) & 0x100) ? 1 : 0; }
+#define SetCF16(x) {m_CF = ((x) & 0x10000) ? 1 : 0; }
+#define SetCF32(x) {m_CF = ((x) & (((UINT64)1) << 32)) ? 1 : 0; }
-#define SetSF(x) (cpustate->SF = (x))
-#define SetZF(x) (cpustate->ZF = (x))
-#define SetAF(x,y,z) (cpustate->AF = (((x) ^ ((y) ^ (z))) & 0x10) ? 1 : 0)
-#define SetPF(x) (cpustate->PF = i386_parity_table[(x) & 0xFF])
+#define SetSF(x) (m_SF = (x))
+#define SetZF(x) (m_ZF = (x))
+#define SetAF(x,y,z) (m_AF = (((x) ^ ((y) ^ (z))) & 0x10) ? 1 : 0)
+#define SetPF(x) (m_PF = i386_parity_table[(x) & 0xFF])
-#define SetSZPF8(x) {cpustate->ZF = ((UINT8)(x)==0); cpustate->SF = ((x)&0x80) ? 1 : 0; cpustate->PF = i386_parity_table[x & 0xFF]; }
-#define SetSZPF16(x) {cpustate->ZF = ((UINT16)(x)==0); cpustate->SF = ((x)&0x8000) ? 1 : 0; cpustate->PF = i386_parity_table[x & 0xFF]; }
-#define SetSZPF32(x) {cpustate->ZF = ((UINT32)(x)==0); cpustate->SF = ((x)&0x80000000) ? 1 : 0; cpustate->PF = i386_parity_table[x & 0xFF]; }
+#define SetSZPF8(x) {m_ZF = ((UINT8)(x)==0); m_SF = ((x)&0x80) ? 1 : 0; m_PF = i386_parity_table[x & 0xFF]; }
+#define SetSZPF16(x) {m_ZF = ((UINT16)(x)==0); m_SF = ((x)&0x8000) ? 1 : 0; m_PF = i386_parity_table[x & 0xFF]; }
+#define SetSZPF32(x) {m_ZF = ((UINT32)(x)==0); m_SF = ((x)&0x80000000) ? 1 : 0; m_PF = i386_parity_table[x & 0xFF]; }
-#define MMX(n) (*((MMX_REG *)(&cpustate->x87_reg[(n)].low)))
-#define XMM(n) cpustate->sse_reg[(n)]
+#define MMX(n) (*((MMX_REG *)(&m_x87_reg[(n)].low)))
+#define XMM(n) m_sse_reg[(n)]
/***********************************************************************************/
@@ -528,9 +329,9 @@ struct MODRM_TABLE {
extern MODRM_TABLE i386_MODRM_table[256];
-#define REG8(x) (cpustate->reg.b[x])
-#define REG16(x) (cpustate->reg.w[x])
-#define REG32(x) (cpustate->reg.d[x])
+#define REG8(x) (m_reg.b[x])
+#define REG16(x) (m_reg.w[x])
+#define REG32(x) (m_reg.d[x])
#define LOAD_REG8(x) (REG8(i386_MODRM_table[x].reg.b))
#define LOAD_REG16(x) (REG16(i386_MODRM_table[x].reg.w))
@@ -550,26 +351,26 @@ extern MODRM_TABLE i386_MODRM_table[256];
/***********************************************************************************/
-INLINE UINT32 i386_translate(i386_state *cpustate, int segment, UINT32 ip, int rwn)
+UINT32 i386_device::i386_translate(int segment, UINT32 ip, int rwn)
{
// TODO: segment limit access size, execution permission, handle exception thrown from exception handler
if(PROTECTED_MODE && !V8086_MODE && (rwn != -1))
{
- if(!(cpustate->sreg[segment].valid))
+ if(!(m_sreg[segment].valid))
FAULT_THROW((segment==SS)?FAULT_SS:FAULT_GP, 0);
- if(i386_limit_check(cpustate, segment, ip))
+ if(i386_limit_check(segment, ip))
FAULT_THROW((segment==SS)?FAULT_SS:FAULT_GP, 0);
- if((rwn == 0) && ((cpustate->sreg[segment].flags & 8) && !(cpustate->sreg[segment].flags & 2)))
+ if((rwn == 0) && ((m_sreg[segment].flags & 8) && !(m_sreg[segment].flags & 2)))
FAULT_THROW(FAULT_GP, 0);
- if((rwn == 1) && ((cpustate->sreg[segment].flags & 8) || !(cpustate->sreg[segment].flags & 2)))
+ if((rwn == 1) && ((m_sreg[segment].flags & 8) || !(m_sreg[segment].flags & 2)))
FAULT_THROW(FAULT_GP, 0);
}
- return cpustate->sreg[segment].base + ip;
+ return m_sreg[segment].base + ip;
}
#define VTLB_FLAG_DIRTY 0x100
-INLINE vtlb_entry get_permissions(UINT32 pte, int wp)
+vtlb_entry i386_device::get_permissions(UINT32 pte, int wp)
{
vtlb_entry ret = VTLB_READ_ALLOWED | ((pte & 4) ? VTLB_USER_READ_ALLOWED : 0);
if(!wp)
@@ -579,87 +380,87 @@ INLINE vtlb_entry get_permissions(UINT32 pte, int wp)
return ret;
}
-static int i386_translate_address(i386_state *cpustate, int intention, offs_t *address, vtlb_entry *entry)
+bool i386_device::i386_translate_address(int intention, offs_t *address, vtlb_entry *entry)
{
UINT32 a = *address;
- UINT32 pdbr = cpustate->cr[3] & 0xfffff000;
+ UINT32 pdbr = m_cr[3] & 0xfffff000;
UINT32 directory = (a >> 22) & 0x3ff;
UINT32 table = (a >> 12) & 0x3ff;
vtlb_entry perm = 0;
- int ret = FALSE;
+ bool ret = false;
bool user = (intention & TRANSLATE_USER_MASK) ? true : false;
bool write = (intention & TRANSLATE_WRITE) ? true : false;
bool debug = (intention & TRANSLATE_DEBUG_MASK) ? true : false;
- if(!(cpustate->cr[0] & 0x80000000))
+ if(!(m_cr[0] & 0x80000000))
{
if(entry)
*entry = 0x77;
- return TRUE;
+ return true;
}
- UINT32 page_dir = cpustate->program->read_dword(pdbr + directory * 4);
+ UINT32 page_dir = m_program->read_dword(pdbr + directory * 4);
if(page_dir & 1)
{
- if ((page_dir & 0x80) && (cpustate->cr[4] & 0x10))
+ if ((page_dir & 0x80) && (m_cr[4] & 0x10))
{
a = (page_dir & 0xffc00000) | (a & 0x003fffff);
if(debug)
{
*address = a;
- return TRUE;
+ return true;
}
perm = get_permissions(page_dir, WP);
if(write && (!(perm & VTLB_WRITE_ALLOWED) || (user && !(perm & VTLB_USER_WRITE_ALLOWED))))
- ret = FALSE;
+ ret = false;
else if(user && !(perm & VTLB_USER_READ_ALLOWED))
- ret = FALSE;
+ ret = false;
else
{
if(write)
perm |= VTLB_FLAG_DIRTY;
if(!(page_dir & 0x40) && write)
- cpustate->program->write_dword(pdbr + directory * 4, page_dir | 0x60);
+ m_program->write_dword(pdbr + directory * 4, page_dir | 0x60);
else if(!(page_dir & 0x20))
- cpustate->program->write_dword(pdbr + directory * 4, page_dir | 0x20);
- ret = TRUE;
+ m_program->write_dword(pdbr + directory * 4, page_dir | 0x20);
+ ret = true;
}
}
else
{
- UINT32 page_entry = cpustate->program->read_dword((page_dir & 0xfffff000) + (table * 4));
+ UINT32 page_entry = m_program->read_dword((page_dir & 0xfffff000) + (table * 4));
if(!(page_entry & 1))
- ret = FALSE;
+ ret = false;
else
{
a = (page_entry & 0xfffff000) | (a & 0xfff);
if(debug)
{
*address = a;
- return TRUE;
+ return true;
}
perm = get_permissions(page_entry, WP);
if(write && (!(perm & VTLB_WRITE_ALLOWED) || (user && !(perm & VTLB_USER_WRITE_ALLOWED))))
- ret = FALSE;
+ ret = false;
else if(user && !(perm & VTLB_USER_READ_ALLOWED))
- ret = FALSE;
+ ret = false;
else
{
if(write)
perm |= VTLB_FLAG_DIRTY;
if(!(page_dir & 0x20))
- cpustate->program->write_dword(pdbr + directory * 4, page_dir | 0x20);
+ m_program->write_dword(pdbr + directory * 4, page_dir | 0x20);
if(!(page_entry & 0x40) && write)
- cpustate->program->write_dword((page_dir & 0xfffff000) + (table * 4), page_entry | 0x60);
+ m_program->write_dword((page_dir & 0xfffff000) + (table * 4), page_entry | 0x60);
else if(!(page_entry & 0x20))
- cpustate->program->write_dword((page_dir & 0xfffff000) + (table * 4), page_entry | 0x20);
- ret = TRUE;
+ m_program->write_dword((page_dir & 0xfffff000) + (table * 4), page_entry | 0x20);
+ ret = true;
}
}
}
}
else
- ret = FALSE;
+ ret = false;
if(entry)
*entry = perm;
if(ret)
@@ -669,12 +470,12 @@ static int i386_translate_address(i386_state *cpustate, int intention, offs_t *a
//#define TEST_TLB
-INLINE int translate_address(i386_state *cpustate, int pl, int type, UINT32 *address, UINT32 *error)
+int i386_device::translate_address(int pl, int type, UINT32 *address, UINT32 *error)
{
- if(!(cpustate->cr[0] & 0x80000000)) // Some (very few) old OS's won't work with this
+ if(!(m_cr[0] & 0x80000000)) // Some (very few) old OS's won't work with this
return TRUE;
- const vtlb_entry *table = vtlb_table(cpustate->vtlb);
+ const vtlb_entry *table = vtlb_table(m_vtlb);
UINT32 index = *address >> 12;
vtlb_entry entry = table[index];
if(type == TRANSLATE_FETCH)
@@ -687,361 +488,361 @@ INLINE int translate_address(i386_state *cpustate, int pl, int type, UINT32 *add
if(!(entry & VTLB_FLAG_VALID) || ((type & TRANSLATE_WRITE) && !(entry & VTLB_FLAG_DIRTY)))
{
- if(!i386_translate_address(cpustate, type, address, &entry))
+ if(!i386_translate_address(type, address, &entry))
{
- *error = ((type & TRANSLATE_WRITE) ? 2 : 0) | ((cpustate->CPL == 3) ? 4 : 0);
+ *error = ((type & TRANSLATE_WRITE) ? 2 : 0) | ((m_CPL == 3) ? 4 : 0);
if(entry)
*error |= 1;
return FALSE;
}
- vtlb_dynload(cpustate->vtlb, index, *address, entry);
+ vtlb_dynload(m_vtlb, index, *address, entry);
return TRUE;
}
if(!(entry & (1 << type)))
{
- *error = ((type & TRANSLATE_WRITE) ? 2 : 0) | ((cpustate->CPL == 3) ? 4 : 0) | 1;
+ *error = ((type & TRANSLATE_WRITE) ? 2 : 0) | ((m_CPL == 3) ? 4 : 0) | 1;
return FALSE;
}
*address = (entry & 0xfffff000) | (*address & 0xfff);
#ifdef TEST_TLB
- int test_ret = i386_translate_address(cpustate, type | TRANSLATE_DEBUG_MASK, &test_addr, NULL);
+ int test_ret = i386_translate_address(type | TRANSLATE_DEBUG_MASK, &test_addr, NULL);
if(!test_ret || (test_addr != *address))
- logerror("TLB-PTE mismatch! %06X %06X %06x\n", *address, test_addr, cpustate->pc);
+ logerror("TLB-PTE mismatch! %06X %06X %06x\n", *address, test_addr, m_pc);
#endif
return TRUE;
}
-INLINE void CHANGE_PC(i386_state *cpustate, UINT32 pc)
+void i386_device::CHANGE_PC(UINT32 pc)
{
- cpustate->pc = i386_translate(cpustate, CS, pc, -1 );
+ m_pc = i386_translate(CS, pc, -1 );
}
-INLINE void NEAR_BRANCH(i386_state *cpustate, INT32 offs)
+void i386_device::NEAR_BRANCH(INT32 offs)
{
/* TODO: limit */
- cpustate->eip += offs;
- cpustate->pc += offs;
+ m_eip += offs;
+ m_pc += offs;
}
-INLINE UINT8 FETCH(i386_state *cpustate)
+UINT8 i386_device::FETCH()
{
UINT8 value;
- UINT32 address = cpustate->pc, error;
+ UINT32 address = m_pc, error;
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_FETCH,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_FETCH,&address,&error))
PF_THROW(error);
- value = cpustate->direct->read_decrypted_byte(address & cpustate->a20_mask);
+ value = m_direct->read_decrypted_byte(address & m_a20_mask);
#ifdef DEBUG_MISSING_OPCODE
- cpustate->opcode_bytes[cpustate->opcode_bytes_length] = value;
- cpustate->opcode_bytes_length = (cpustate->opcode_bytes_length + 1) & 15;
+ m_opcode_bytes[m_opcode_bytes_length] = value;
+ m_opcode_bytes_length = (m_opcode_bytes_length + 1) & 15;
#endif
- cpustate->eip++;
- cpustate->pc++;
+ m_eip++;
+ m_pc++;
return value;
}
-INLINE UINT16 FETCH16(i386_state *cpustate)
+UINT16 i386_device::FETCH16()
{
UINT16 value;
- UINT32 address = cpustate->pc, error;
+ UINT32 address = m_pc, error;
if( address & 0x1 ) { /* Unaligned read */
- value = (FETCH(cpustate) << 0);
- value |= (FETCH(cpustate) << 8);
+ value = (FETCH() << 0);
+ value |= (FETCH() << 8);
} else {
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_FETCH,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_FETCH,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- value = cpustate->direct->read_decrypted_word(address);
- cpustate->eip += 2;
- cpustate->pc += 2;
+ address &= m_a20_mask;
+ value = m_direct->read_decrypted_word(address);
+ m_eip += 2;
+ m_pc += 2;
}
return value;
}
-INLINE UINT32 FETCH32(i386_state *cpustate)
+UINT32 i386_device::FETCH32()
{
UINT32 value;
- UINT32 address = cpustate->pc, error;
+ UINT32 address = m_pc, error;
- if( cpustate->pc & 0x3 ) { /* Unaligned read */
- value = (FETCH(cpustate) << 0);
- value |= (FETCH(cpustate) << 8);
- value |= (FETCH(cpustate) << 16);
- value |= (FETCH(cpustate) << 24);
+ if( m_pc & 0x3 ) { /* Unaligned read */
+ value = (FETCH() << 0);
+ value |= (FETCH() << 8);
+ value |= (FETCH() << 16);
+ value |= (FETCH() << 24);
} else {
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_FETCH,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_FETCH,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- value = cpustate->direct->read_decrypted_dword(address);
- cpustate->eip += 4;
- cpustate->pc += 4;
+ address &= m_a20_mask;
+ value = m_direct->read_decrypted_dword(address);
+ m_eip += 4;
+ m_pc += 4;
}
return value;
}
-INLINE UINT8 READ8(i386_state *cpustate,UINT32 ea)
+UINT8 i386_device::READ8(UINT32 ea)
{
UINT32 address = ea, error;
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_READ,&address, &error))
+ if(!translate_address(m_CPL,TRANSLATE_READ,&address, &error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- return cpustate->program->read_byte(address);
+ address &= m_a20_mask;
+ return m_program->read_byte(address);
}
-INLINE UINT16 READ16(i386_state *cpustate,UINT32 ea)
+UINT16 i386_device::READ16(UINT32 ea)
{
UINT16 value;
UINT32 address = ea, error;
if( ea & 0x1 ) { /* Unaligned read */
- value = (READ8( cpustate, address+0 ) << 0);
- value |= (READ8( cpustate, address+1 ) << 8);
+ value = (READ8( address+0 ) << 0);
+ value |= (READ8( address+1 ) << 8);
} else {
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_READ,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_READ,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- value = cpustate->program->read_word( address );
+ address &= m_a20_mask;
+ value = m_program->read_word( address );
}
return value;
}
-INLINE UINT32 READ32(i386_state *cpustate,UINT32 ea)
+UINT32 i386_device::READ32(UINT32 ea)
{
UINT32 value;
UINT32 address = ea, error;
if( ea & 0x3 ) { /* Unaligned read */
- value = (READ8( cpustate, address+0 ) << 0);
- value |= (READ8( cpustate, address+1 ) << 8);
- value |= (READ8( cpustate, address+2 ) << 16),
- value |= (READ8( cpustate, address+3 ) << 24);
+ value = (READ8( address+0 ) << 0);
+ value |= (READ8( address+1 ) << 8);
+ value |= (READ8( address+2 ) << 16),
+ value |= (READ8( address+3 ) << 24);
} else {
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_READ,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_READ,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- value = cpustate->program->read_dword( address );
+ address &= m_a20_mask;
+ value = m_program->read_dword( address );
}
return value;
}
-INLINE UINT64 READ64(i386_state *cpustate,UINT32 ea)
+UINT64 i386_device::READ64(UINT32 ea)
{
UINT64 value;
UINT32 address = ea, error;
if( ea & 0x7 ) { /* Unaligned read */
- value = (((UINT64) READ8( cpustate, address+0 )) << 0);
- value |= (((UINT64) READ8( cpustate, address+1 )) << 8);
- value |= (((UINT64) READ8( cpustate, address+2 )) << 16);
- value |= (((UINT64) READ8( cpustate, address+3 )) << 24);
- value |= (((UINT64) READ8( cpustate, address+4 )) << 32);
- value |= (((UINT64) READ8( cpustate, address+5 )) << 40);
- value |= (((UINT64) READ8( cpustate, address+6 )) << 48);
- value |= (((UINT64) READ8( cpustate, address+7 )) << 56);
+ value = (((UINT64) READ8( address+0 )) << 0);
+ value |= (((UINT64) READ8( address+1 )) << 8);
+ value |= (((UINT64) READ8( address+2 )) << 16);
+ value |= (((UINT64) READ8( address+3 )) << 24);
+ value |= (((UINT64) READ8( address+4 )) << 32);
+ value |= (((UINT64) READ8( address+5 )) << 40);
+ value |= (((UINT64) READ8( address+6 )) << 48);
+ value |= (((UINT64) READ8( address+7 )) << 56);
} else {
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_READ,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_READ,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- value = (((UINT64) cpustate->program->read_dword( address+0 )) << 0);
- value |= (((UINT64) cpustate->program->read_dword( address+4 )) << 32);
+ address &= m_a20_mask;
+ value = (((UINT64) m_program->read_dword( address+0 )) << 0);
+ value |= (((UINT64) m_program->read_dword( address+4 )) << 32);
}
return value;
}
-INLINE UINT8 READ8PL0(i386_state *cpustate,UINT32 ea)
+UINT8 i386_device::READ8PL0(UINT32 ea)
{
UINT32 address = ea, error;
- if(!translate_address(cpustate,0,TRANSLATE_READ,&address,&error))
+ if(!translate_address(0,TRANSLATE_READ,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- return cpustate->program->read_byte(address);
+ address &= m_a20_mask;
+ return m_program->read_byte(address);
}
-INLINE UINT16 READ16PL0(i386_state *cpustate,UINT32 ea)
+UINT16 i386_device::READ16PL0(UINT32 ea)
{
UINT16 value;
UINT32 address = ea, error;
if( ea & 0x1 ) { /* Unaligned read */
- value = (READ8PL0( cpustate, address+0 ) << 0);
- value |= (READ8PL0( cpustate, address+1 ) << 8);
+ value = (READ8PL0( address+0 ) << 0);
+ value |= (READ8PL0( address+1 ) << 8);
} else {
- if(!translate_address(cpustate,0,TRANSLATE_READ,&address,&error))
+ if(!translate_address(0,TRANSLATE_READ,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- value = cpustate->program->read_word( address );
+ address &= m_a20_mask;
+ value = m_program->read_word( address );
}
return value;
}
-INLINE UINT32 READ32PL0(i386_state *cpustate,UINT32 ea)
+UINT32 i386_device::READ32PL0(UINT32 ea)
{
UINT32 value;
UINT32 address = ea, error;
if( ea & 0x3 ) { /* Unaligned read */
- value = (READ8PL0( cpustate, address+0 ) << 0);
- value |= (READ8PL0( cpustate, address+1 ) << 8);
- value |= (READ8PL0( cpustate, address+2 ) << 16);
- value |= (READ8PL0( cpustate, address+3 ) << 24);
+ value = (READ8PL0( address+0 ) << 0);
+ value |= (READ8PL0( address+1 ) << 8);
+ value |= (READ8PL0( address+2 ) << 16);
+ value |= (READ8PL0( address+3 ) << 24);
} else {
- if(!translate_address(cpustate,0,TRANSLATE_READ,&address,&error))
+ if(!translate_address(0,TRANSLATE_READ,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- value = cpustate->program->read_dword( address );
+ address &= m_a20_mask;
+ value = m_program->read_dword( address );
}
return value;
}
-INLINE void WRITE_TEST(i386_state *cpustate,UINT32 ea)
+void i386_device::WRITE_TEST(UINT32 ea)
{
UINT32 address = ea, error;
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_WRITE,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_WRITE,&address,&error))
PF_THROW(error);
}
-INLINE void WRITE8(i386_state *cpustate,UINT32 ea, UINT8 value)
+void i386_device::WRITE8(UINT32 ea, UINT8 value)
{
UINT32 address = ea, error;
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_WRITE,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_WRITE,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- cpustate->program->write_byte(address, value);
+ address &= m_a20_mask;
+ m_program->write_byte(address, value);
}
-INLINE void WRITE16(i386_state *cpustate,UINT32 ea, UINT16 value)
+void i386_device::WRITE16(UINT32 ea, UINT16 value)
{
UINT32 address = ea, error;
if( ea & 0x1 ) { /* Unaligned write */
- WRITE8( cpustate, address+0, value & 0xff );
- WRITE8( cpustate, address+1, (value >> 8) & 0xff );
+ WRITE8( address+0, value & 0xff );
+ WRITE8( address+1, (value >> 8) & 0xff );
} else {
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_WRITE,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_WRITE,&address,&error))
PF_THROW(error);
- address &= cpustate->a20_mask;
- cpustate->program->write_word(address, value);
+ address &= m_a20_mask;
+ m_program->write_word(address, value);
}
}
-INLINE void WRITE32(i386_state *cpustate,UINT32 ea, UINT32 value)
+void i386_device::WRITE32(UINT32 ea, UINT32 value)
{
UINT32 address = ea, error;
if( ea & 0x3 ) { /* Unaligned write */
- WRITE8( cpustate, address+0, value & 0xff );
- WRITE8( cpustate, address+1, (value >> 8) & 0xff );
- WRITE8( cpustate, address+2, (value >> 16) & 0xff );
- WRITE8( cpustate, address+3, (value >> 24) & 0xff );
+ WRITE8( address+0, value & 0xff );
+ WRITE8( address+1, (value >> 8) & 0xff );
+ WRITE8( address+2, (value >> 16) & 0xff );
+ WRITE8( address+3, (value >> 24) & 0xff );
} else {
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_WRITE,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_WRITE,&address,&error))
PF_THROW(error);
- ea &= cpustate->a20_mask;
- cpustate->program->write_dword(address, value);
+ ea &= m_a20_mask;
+ m_program->write_dword(address, value);
}
}
-INLINE void WRITE64(i386_state *cpustate,UINT32 ea, UINT64 value)
+void i386_device::WRITE64(UINT32 ea, UINT64 value)
{
UINT32 address = ea, error;
if( ea & 0x7 ) { /* Unaligned write */
- WRITE8( cpustate, address+0, value & 0xff );
- WRITE8( cpustate, address+1, (value >> 8) & 0xff );
- WRITE8( cpustate, address+2, (value >> 16) & 0xff );
- WRITE8( cpustate, address+3, (value >> 24) & 0xff );
- WRITE8( cpustate, address+4, (value >> 32) & 0xff );
- WRITE8( cpustate, address+5, (value >> 40) & 0xff );
- WRITE8( cpustate, address+6, (value >> 48) & 0xff );
- WRITE8( cpustate, address+7, (value >> 56) & 0xff );
+ WRITE8( address+0, value & 0xff );
+ WRITE8( address+1, (value >> 8) & 0xff );
+ WRITE8( address+2, (value >> 16) & 0xff );
+ WRITE8( address+3, (value >> 24) & 0xff );
+ WRITE8( address+4, (value >> 32) & 0xff );
+ WRITE8( address+5, (value >> 40) & 0xff );
+ WRITE8( address+6, (value >> 48) & 0xff );
+ WRITE8( address+7, (value >> 56) & 0xff );
} else {
- if(!translate_address(cpustate,cpustate->CPL,TRANSLATE_WRITE,&address,&error))
+ if(!translate_address(m_CPL,TRANSLATE_WRITE,&address,&error))
PF_THROW(error);
- ea &= cpustate->a20_mask;
- cpustate->program->write_dword(address+0, value & 0xffffffff);
- cpustate->program->write_dword(address+4, (value >> 32) & 0xffffffff);
+ ea &= m_a20_mask;
+ m_program->write_dword(address+0, value & 0xffffffff);
+ m_program->write_dword(address+4, (value >> 32) & 0xffffffff);
}
}
/***********************************************************************************/
-INLINE UINT8 OR8(i386_state *cpustate,UINT8 dst, UINT8 src)
+UINT8 i386_device::OR8(UINT8 dst, UINT8 src)
{
UINT8 res = dst | src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF8(res);
return res;
}
-INLINE UINT16 OR16(i386_state *cpustate,UINT16 dst, UINT16 src)
+UINT16 i386_device::OR16(UINT16 dst, UINT16 src)
{
UINT16 res = dst | src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF16(res);
return res;
}
-INLINE UINT32 OR32(i386_state *cpustate,UINT32 dst, UINT32 src)
+UINT32 i386_device::OR32(UINT32 dst, UINT32 src)
{
UINT32 res = dst | src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF32(res);
return res;
}
-INLINE UINT8 AND8(i386_state *cpustate,UINT8 dst, UINT8 src)
+UINT8 i386_device::AND8(UINT8 dst, UINT8 src)
{
UINT8 res = dst & src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF8(res);
return res;
}
-INLINE UINT16 AND16(i386_state *cpustate,UINT16 dst, UINT16 src)
+UINT16 i386_device::AND16(UINT16 dst, UINT16 src)
{
UINT16 res = dst & src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF16(res);
return res;
}
-INLINE UINT32 AND32(i386_state *cpustate,UINT32 dst, UINT32 src)
+UINT32 i386_device::AND32(UINT32 dst, UINT32 src)
{
UINT32 res = dst & src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF32(res);
return res;
}
-INLINE UINT8 XOR8(i386_state *cpustate,UINT8 dst, UINT8 src)
+UINT8 i386_device::XOR8(UINT8 dst, UINT8 src)
{
UINT8 res = dst ^ src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF8(res);
return res;
}
-INLINE UINT16 XOR16(i386_state *cpustate,UINT16 dst, UINT16 src)
+UINT16 i386_device::XOR16(UINT16 dst, UINT16 src)
{
UINT16 res = dst ^ src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF16(res);
return res;
}
-INLINE UINT32 XOR32(i386_state *cpustate,UINT32 dst, UINT32 src)
+UINT32 i386_device::XOR32(UINT32 dst, UINT32 src)
{
UINT32 res = dst ^ src;
- cpustate->CF = cpustate->OF = 0;
+ m_CF = m_OF = 0;
SetSZPF32(res);
return res;
}
-#define SUB8(cpu, dst, src) SBB8(cpu, dst, src, 0)
-INLINE UINT8 SBB8(i386_state *cpustate,UINT8 dst, UINT8 src, UINT8 b)
+#define SUB8(dst, src) SBB8(dst, src, 0)
+UINT8 i386_device::SBB8(UINT8 dst, UINT8 src, UINT8 b)
{
UINT16 res = (UINT16)dst - (UINT16)src - (UINT8)b;
SetCF8(res);
@@ -1051,8 +852,8 @@ INLINE UINT8 SBB8(i386_state *cpustate,UINT8 dst, UINT8 src, UINT8 b)
return (UINT8)res;
}
-#define SUB16(cpu, dst, src) SBB16(cpu, dst, src, 0)
-INLINE UINT16 SBB16(i386_state *cpustate,UINT16 dst, UINT16 src, UINT16 b)
+#define SUB16(dst, src) SBB16(dst, src, 0)
+UINT16 i386_device::SBB16(UINT16 dst, UINT16 src, UINT16 b)
{
UINT32 res = (UINT32)dst - (UINT32)src - (UINT32)b;
SetCF16(res);
@@ -1062,8 +863,8 @@ INLINE UINT16 SBB16(i386_state *cpustate,UINT16 dst, UINT16 src, UINT16 b)
return (UINT16)res;
}
-#define SUB32(cpu, dst, src) SBB32(cpu, dst, src, 0)
-INLINE UINT32 SBB32(i386_state *cpustate,UINT32 dst, UINT32 src, UINT32 b)
+#define SUB32(dst, src) SBB32(dst, src, 0)
+UINT32 i386_device::SBB32(UINT32 dst, UINT32 src, UINT32 b)
{
UINT64 res = (UINT64)dst - (UINT64)src - (UINT64) b;
SetCF32(res);
@@ -1073,8 +874,8 @@ INLINE UINT32 SBB32(i386_state *cpustate,UINT32 dst, UINT32 src, UINT32 b)
return (UINT32)res;
}
-#define ADD8(cpu, dst, src) ADC8(cpu, dst, src, 0)
-INLINE UINT8 ADC8(i386_state *cpustate,UINT8 dst, UINT8 src, UINT8 c)
+#define ADD8(dst, src) ADC8(dst, src, 0)
+UINT8 i386_device::ADC8(UINT8 dst, UINT8 src, UINT8 c)
{
UINT16 res = (UINT16)dst + (UINT16)src + (UINT16)c;
SetCF8(res);
@@ -1084,8 +885,8 @@ INLINE UINT8 ADC8(i386_state *cpustate,UINT8 dst, UINT8 src, UINT8 c)
return (UINT8)res;
}
-#define ADD16(cpu, dst, src) ADC16(cpu, dst, src, 0)
-INLINE UINT16 ADC16(i386_state *cpustate,UINT16 dst, UINT16 src, UINT8 c)
+#define ADD16(dst, src) ADC16(dst, src, 0)
+UINT16 i386_device::ADC16(UINT16 dst, UINT16 src, UINT8 c)
{
UINT32 res = (UINT32)dst + (UINT32)src + (UINT32)c;
SetCF16(res);
@@ -1095,8 +896,8 @@ INLINE UINT16 ADC16(i386_state *cpustate,UINT16 dst, UINT16 src, UINT8 c)
return (UINT16)res;
}
-#define ADD32(cpu, dst, src) ADC32(cpu, dst, src, 0)
-INLINE UINT32 ADC32(i386_state *cpustate,UINT32 dst, UINT32 src, UINT32 c)
+#define ADD32(dst, src) ADC32(dst, src, 0)
+UINT32 i386_device::ADC32(UINT32 dst, UINT32 src, UINT32 c)
{
UINT64 res = (UINT64)dst + (UINT64)src + (UINT64) c;
SetCF32(res);
@@ -1106,7 +907,7 @@ INLINE UINT32 ADC32(i386_state *cpustate,UINT32 dst, UINT32 src, UINT32 c)
return (UINT32)res;
}
-INLINE UINT8 INC8(i386_state *cpustate,UINT8 dst)
+UINT8 i386_device::INC8(UINT8 dst)
{
UINT16 res = (UINT16)dst + 1;
SetOF_Add8(res,1,dst);
@@ -1114,7 +915,7 @@ INLINE UINT8 INC8(i386_state *cpustate,UINT8 dst)
SetSZPF8(res);
return (UINT8)res;
}
-INLINE UINT16 INC16(i386_state *cpustate,UINT16 dst)
+UINT16 i386_device::INC16(UINT16 dst)
{
UINT32 res = (UINT32)dst + 1;
SetOF_Add16(res,1,dst);
@@ -1122,7 +923,7 @@ INLINE UINT16 INC16(i386_state *cpustate,UINT16 dst)
SetSZPF16(res);
return (UINT16)res;
}
-INLINE UINT32 INC32(i386_state *cpustate,UINT32 dst)
+UINT32 i386_device::INC32(UINT32 dst)
{
UINT64 res = (UINT64)dst + 1;
SetOF_Add32(res,1,dst);
@@ -1131,7 +932,7 @@ INLINE UINT32 INC32(i386_state *cpustate,UINT32 dst)
return (UINT32)res;
}
-INLINE UINT8 DEC8(i386_state *cpustate,UINT8 dst)
+UINT8 i386_device::DEC8(UINT8 dst)
{
UINT16 res = (UINT16)dst - 1;
SetOF_Sub8(res,1,dst);
@@ -1139,7 +940,7 @@ INLINE UINT8 DEC8(i386_state *cpustate,UINT8 dst)
SetSZPF8(res);
return (UINT8)res;
}
-INLINE UINT16 DEC16(i386_state *cpustate,UINT16 dst)
+UINT16 i386_device::DEC16(UINT16 dst)
{
UINT32 res = (UINT32)dst - 1;
SetOF_Sub16(res,1,dst);
@@ -1147,7 +948,7 @@ INLINE UINT16 DEC16(i386_state *cpustate,UINT16 dst)
SetSZPF16(res);
return (UINT16)res;
}
-INLINE UINT32 DEC32(i386_state *cpustate,UINT32 dst)
+UINT32 i386_device::DEC32(UINT32 dst)
{
UINT64 res = (UINT64)dst - 1;
SetOF_Sub32(res,1,dst);
@@ -1158,111 +959,111 @@ INLINE UINT32 DEC32(i386_state *cpustate,UINT32 dst)
-INLINE void PUSH16(i386_state *cpustate,UINT16 value)
+void i386_device::PUSH16(UINT16 value)
{
UINT32 ea, new_esp;
if( STACK_32BIT ) {
new_esp = REG32(ESP) - 2;
- ea = i386_translate(cpustate, SS, new_esp, 1);
- WRITE16(cpustate, ea, value );
+ ea = i386_translate(SS, new_esp, 1);
+ WRITE16(ea, value );
REG32(ESP) = new_esp;
} else {
new_esp = (REG16(SP) - 2) & 0xffff;
- ea = i386_translate(cpustate, SS, new_esp, 1);
- WRITE16(cpustate, ea, value );
+ ea = i386_translate(SS, new_esp, 1);
+ WRITE16(ea, value );
REG16(SP) = new_esp;
}
}
-INLINE void PUSH32(i386_state *cpustate,UINT32 value)
+void i386_device::PUSH32(UINT32 value)
{
UINT32 ea, new_esp;
if( STACK_32BIT ) {
new_esp = REG32(ESP) - 4;
- ea = i386_translate(cpustate, SS, new_esp, 1);
- WRITE32(cpustate, ea, value );
+ ea = i386_translate(SS, new_esp, 1);
+ WRITE32(ea, value );
REG32(ESP) = new_esp;
} else {
new_esp = (REG16(SP) - 4) & 0xffff;
- ea = i386_translate(cpustate, SS, new_esp, 1);
- WRITE32(cpustate, ea, value );
+ ea = i386_translate(SS, new_esp, 1);
+ WRITE32(ea, value );
REG16(SP) = new_esp;
}
}
-INLINE void PUSH8(i386_state *cpustate,UINT8 value)
+void i386_device::PUSH8(UINT8 value)
{
- if( cpustate->operand_size ) {
- PUSH32(cpustate,(INT32)(INT8)value);
+ if( m_operand_size ) {
+ PUSH32((INT32)(INT8)value);
} else {
- PUSH16(cpustate,(INT16)(INT8)value);
+ PUSH16((INT16)(INT8)value);
}
}
-INLINE UINT8 POP8(i386_state *cpustate)
+UINT8 i386_device::POP8()
{
UINT8 value;
UINT32 ea, new_esp;
if( STACK_32BIT ) {
new_esp = REG32(ESP) + 1;
- ea = i386_translate(cpustate, SS, new_esp - 1, 0);
- value = READ8(cpustate, ea );
+ ea = i386_translate(SS, new_esp - 1, 0);
+ value = READ8(ea );
REG32(ESP) = new_esp;
} else {
new_esp = REG16(SP) + 1;
- ea = i386_translate(cpustate, SS, (new_esp - 1) & 0xffff, 0);
- value = READ8(cpustate, ea );
+ ea = i386_translate(SS, (new_esp - 1) & 0xffff, 0);
+ value = READ8(ea );
REG16(SP) = new_esp;
}
return value;
}
-INLINE UINT16 POP16(i386_state *cpustate)
+UINT16 i386_device::POP16()
{
UINT16 value;
UINT32 ea, new_esp;
if( STACK_32BIT ) {
new_esp = REG32(ESP) + 2;
- ea = i386_translate(cpustate, SS, new_esp - 2, 0);
- value = READ16(cpustate, ea );
+ ea = i386_translate(SS, new_esp - 2, 0);
+ value = READ16(ea );
REG32(ESP) = new_esp;
} else {
new_esp = REG16(SP) + 2;
- ea = i386_translate(cpustate, SS, (new_esp - 2) & 0xffff, 0);
- value = READ16(cpustate, ea );
+ ea = i386_translate(SS, (new_esp - 2) & 0xffff, 0);
+ value = READ16(ea );
REG16(SP) = new_esp;
}
return value;
}
-INLINE UINT32 POP32(i386_state *cpustate)
+UINT32 i386_device::POP32()
{
UINT32 value;
UINT32 ea, new_esp;
if( STACK_32BIT ) {
new_esp = REG32(ESP) + 4;
- ea = i386_translate(cpustate, SS, new_esp - 4, 0);
- value = READ32(cpustate, ea );
+ ea = i386_translate(SS, new_esp - 4, 0);
+ value = READ32(ea );
REG32(ESP) = new_esp;
} else {
new_esp = REG16(SP) + 4;
- ea = i386_translate(cpustate, SS, (new_esp - 4) & 0xffff, 0);
- value = READ32(cpustate, ea );
+ ea = i386_translate(SS, (new_esp - 4) & 0xffff, 0);
+ value = READ32(ea );
REG16(SP) = new_esp;
}
return value;
}
-INLINE void BUMP_SI(i386_state *cpustate,int adjustment)
+void i386_device::BUMP_SI(int adjustment)
{
- if ( cpustate->address_size )
- REG32(ESI) += ((cpustate->DF) ? -adjustment : +adjustment);
+ if ( m_address_size )
+ REG32(ESI) += ((m_DF) ? -adjustment : +adjustment);
else
- REG16(SI) += ((cpustate->DF) ? -adjustment : +adjustment);
+ REG16(SI) += ((m_DF) ? -adjustment : +adjustment);
}
-INLINE void BUMP_DI(i386_state *cpustate,int adjustment)
+void i386_device::BUMP_DI(int adjustment)
{
- if ( cpustate->address_size )
- REG32(EDI) += ((cpustate->DF) ? -adjustment : +adjustment);
+ if ( m_address_size )
+ REG32(EDI) += ((m_DF) ? -adjustment : +adjustment);
else
- REG16(DI) += ((cpustate->DF) ? -adjustment : +adjustment);
+ REG16(DI) += ((m_DF) ? -adjustment : +adjustment);
}
@@ -1271,7 +1072,7 @@ INLINE void BUMP_DI(i386_state *cpustate,int adjustment)
I/O ACCESS
***********************************************************************************/
-INLINE void check_ioperm(i386_state *cpustate, offs_t port, UINT8 mask)
+void i386_device::check_ioperm(offs_t port, UINT8 mask)
{
UINT8 IOPL, map;
UINT16 IOPB;
@@ -1280,95 +1081,95 @@ INLINE void check_ioperm(i386_state *cpustate, offs_t port, UINT8 mask)
if(!PROTECTED_MODE)
return;
- IOPL = cpustate->IOP1 | (cpustate->IOP2 << 1);
- if(!V8086_MODE && (cpustate->CPL <= IOPL))
+ IOPL = m_IOP1 | (m_IOP2 << 1);
+ if(!V8086_MODE && (m_CPL <= IOPL))
return;
- if((cpustate->task.limit < 0x67) || ((cpustate->task.flags & 0xd) != 9))
+ if((m_task.limit < 0x67) || ((m_task.flags & 0xd) != 9))
FAULT_THROW(FAULT_GP,0);
- address = cpustate->task.base;
- IOPB = READ16PL0(cpustate, address+0x66);
- if((IOPB+(port/8)) > cpustate->task.limit)
+ address = m_task.base;
+ IOPB = READ16PL0(address+0x66);
+ if((IOPB+(port/8)) > m_task.limit)
FAULT_THROW(FAULT_GP,0);
- map = READ8PL0(cpustate, address+IOPB+(port/8));
+ map = READ8PL0(address+IOPB+(port/8));
map >>= (port%8);
if(map & mask)
FAULT_THROW(FAULT_GP,0);
}
-INLINE UINT8 READPORT8(i386_state *cpustate, offs_t port)
+UINT8 i386_device::READPORT8(offs_t port)
{
- check_ioperm(cpustate, port, 1);
- return cpustate->io->read_byte(port);
+ check_ioperm(port, 1);
+ return m_io->read_byte(port);
}
-INLINE void WRITEPORT8(i386_state *cpustate, offs_t port, UINT8 value)
+void i386_device::WRITEPORT8(offs_t port, UINT8 value)
{
- check_ioperm(cpustate, port, 1);
- cpustate->io->write_byte(port, value);
+ check_ioperm(port, 1);
+ m_io->write_byte(port, value);
}
-INLINE UINT16 READPORT16(i386_state *cpustate, offs_t port)
+UINT16 i386_device::READPORT16(offs_t port)
{
if (port & 1)
{
- UINT16 value = READPORT8(cpustate, port);
- value |= (READPORT8(cpustate, port + 1) << 8);
+ UINT16 value = READPORT8(port);
+ value |= (READPORT8(port + 1) << 8);
return value;
}
else
{
- check_ioperm(cpustate, port, 3);
- return cpustate->io->read_word(port);
+ check_ioperm(port, 3);
+ return m_io->read_word(port);
}
}
-INLINE void WRITEPORT16(i386_state *cpustate, offs_t port, UINT16 value)
+void i386_device::WRITEPORT16(offs_t port, UINT16 value)
{
if (port & 1)
{
- WRITEPORT8(cpustate, port, value & 0xff);
- WRITEPORT8(cpustate, port + 1, (value >> 8) & 0xff);
+ WRITEPORT8(port, value & 0xff);
+ WRITEPORT8(port + 1, (value >> 8) & 0xff);
}
else
{
- check_ioperm(cpustate, port, 3);
- cpustate->io->write_word(port, value);
+ check_ioperm(port, 3);
+ m_io->write_word(port, value);
}
}
-INLINE UINT32 READPORT32(i386_state *cpustate, offs_t port)
+UINT32 i386_device::READPORT32(offs_t port)
{
if (port & 3)
{
- UINT32 value = READPORT8(cpustate, port);
- value |= (READPORT8(cpustate, port + 1) << 8);
- value |= (READPORT8(cpustate, port + 2) << 16);
- value |= (READPORT8(cpustate, port + 3) << 24);
+ UINT32 value = READPORT8(port);
+ value |= (READPORT8(port + 1) << 8);
+ value |= (READPORT8(port + 2) << 16);
+ value |= (READPORT8(port + 3) << 24);
return value;
}
else
{
- check_ioperm(cpustate, port, 0xf);
- return cpustate->io->read_dword(port);
+ check_ioperm(port, 0xf);
+ return m_io->read_dword(port);
}
}
-INLINE void WRITEPORT32(i386_state *cpustate, offs_t port, UINT32 value)
+void i386_device::WRITEPORT32(offs_t port, UINT32 value)
{
if (port & 3)
{
- WRITEPORT8(cpustate, port, value & 0xff);
- WRITEPORT8(cpustate, port + 1, (value >> 8) & 0xff);
- WRITEPORT8(cpustate, port + 2, (value >> 16) & 0xff);
- WRITEPORT8(cpustate, port + 3, (value >> 24) & 0xff);
+ WRITEPORT8(port, value & 0xff);
+ WRITEPORT8(port + 1, (value >> 8) & 0xff);
+ WRITEPORT8(port + 2, (value >> 16) & 0xff);
+ WRITEPORT8(port + 3, (value >> 24) & 0xff);
}
else
{
- check_ioperm(cpustate, port, 0xf);
- cpustate->io->write_dword(port, value);
+ check_ioperm(port, 0xf);
+ m_io->write_dword(port, value);
}
}
@@ -1377,7 +1178,7 @@ INLINE void WRITEPORT32(i386_state *cpustate, offs_t port, UINT32 value)
***********************************************************************************/
// Pentium MSR handling
-UINT64 pentium_msr_read(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
+UINT64 i386_device::pentium_msr_read(UINT32 offset,UINT8 *valid_msr)
{
switch(offset)
{
@@ -1394,7 +1195,7 @@ UINT64 pentium_msr_read(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
case 0x10:
*valid_msr = 1;
popmessage("RDMSR: Reading TSC");
- return cpustate->tsc;
+ return m_tsc;
// Event Counters (TODO)
case 0x11: // CESR
*valid_msr = 1;
@@ -1402,10 +1203,10 @@ UINT64 pentium_msr_read(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
return 0;
case 0x12: // CTR0
*valid_msr = 1;
- return cpustate->perfctr[0];
+ return m_perfctr[0];
case 0x13: // CTR1
*valid_msr = 1;
- return cpustate->perfctr[1];
+ return m_perfctr[1];
default:
if(!(offset & ~0xf)) // 2-f are test registers
{
@@ -1413,14 +1214,14 @@ UINT64 pentium_msr_read(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
logerror("RDMSR: Reading test MSR %x", offset);
return 0;
}
- logerror("RDMSR: invalid P5 MSR read %08x at %08x\n",offset,cpustate->pc-2);
+ logerror("RDMSR: invalid P5 MSR read %08x at %08x\n",offset,m_pc-2);
*valid_msr = 0;
return 0;
}
return -1;
}
-void pentium_msr_write(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *valid_msr)
+void i386_device::pentium_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr)
{
switch(offset)
{
@@ -1435,7 +1236,7 @@ void pentium_msr_write(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *
break;
// Time Stamp Counter
case 0x10:
- cpustate->tsc = data;
+ m_tsc = data;
popmessage("WRMSR: Writing to TSC");
*valid_msr = 1;
break;
@@ -1445,11 +1246,11 @@ void pentium_msr_write(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *
*valid_msr = 1;
break;
case 0x12: // CTR0
- cpustate->perfctr[0] = data;
+ m_perfctr[0] = data;
*valid_msr = 1;
break;
case 0x13: // CTR1
- cpustate->perfctr[1] = data;
+ m_perfctr[1] = data;
*valid_msr = 1;
break;
default:
@@ -1459,14 +1260,14 @@ void pentium_msr_write(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *
logerror("WRMSR: Writing test MSR %x", offset);
break;
}
- logerror("WRMSR: invalid MSR write %08x (%08x%08x) at %08x\n",offset,(UINT32)(data >> 32),(UINT32)data,cpustate->pc-2);
+ logerror("WRMSR: invalid MSR write %08x (%08x%08x) at %08x\n",offset,(UINT32)(data >> 32),(UINT32)data,m_pc-2);
*valid_msr = 0;
break;
}
}
// P6 (Pentium Pro, Pentium II, Pentium III) MSR handling
-UINT64 p6_msr_read(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
+UINT64 i386_device::p6_msr_read(UINT32 offset,UINT8 *valid_msr)
{
switch(offset)
{
@@ -1483,62 +1284,62 @@ UINT64 p6_msr_read(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
case 0x10:
*valid_msr = 1;
popmessage("RDMSR: Reading TSC");
- return cpustate->tsc;
+ return m_tsc;
// Performance Counters (TODO)
case 0xc1: // PerfCtr0
*valid_msr = 1;
- return cpustate->perfctr[0];
+ return m_perfctr[0];
case 0xc2: // PerfCtr1
*valid_msr = 1;
- return cpustate->perfctr[1];
+ return m_perfctr[1];
default:
- logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,cpustate->pc-2);
+ logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,m_pc-2);
*valid_msr = 1;
return 0;
}
return -1;
}
-void p6_msr_write(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *valid_msr)
+void i386_device::p6_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr)
{
switch(offset)
{
// Time Stamp Counter
case 0x10:
- cpustate->tsc = data;
+ m_tsc = data;
popmessage("WRMSR: Writing to TSC");
*valid_msr = 1;
break;
// Performance Counters (TODO)
case 0xc1: // PerfCtr0
- cpustate->perfctr[0] = data;
+ m_perfctr[0] = data;
*valid_msr = 1;
break;
case 0xc2: // PerfCtr1
- cpustate->perfctr[1] = data;
+ m_perfctr[1] = data;
*valid_msr = 1;
break;
default:
- logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(UINT32)(data >> 32),(UINT32)data,cpustate->pc-2);
+ logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(UINT32)(data >> 32),(UINT32)data,m_pc-2);
*valid_msr = 1;
break;
}
}
-INLINE UINT64 MSR_READ(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
+UINT64 i386_device::MSR_READ(UINT32 offset,UINT8 *valid_msr)
{
UINT64 res;
- UINT8 cpu_type = (cpustate->cpu_version >> 8) & 0x0f;
+ UINT8 cpu_type = (m_cpu_version >> 8) & 0x0f;
*valid_msr = 0;
switch(cpu_type)
{
case 5: // Pentium
- res = pentium_msr_read(cpustate,offset,valid_msr);
+ res = pentium_msr_read(offset,valid_msr);
break;
case 6: // Pentium Pro, Pentium II, Pentium III
- res = p6_msr_read(cpustate,offset,valid_msr);
+ res = p6_msr_read(offset,valid_msr);
break;
default:
res = 0;
@@ -1548,18 +1349,18 @@ INLINE UINT64 MSR_READ(i386_state *cpustate, UINT32 offset,UINT8 *valid_msr)
return res;
}
-INLINE void MSR_WRITE(i386_state *cpustate, UINT32 offset, UINT64 data, UINT8 *valid_msr)
+void i386_device::MSR_WRITE(UINT32 offset, UINT64 data, UINT8 *valid_msr)
{
*valid_msr = 0;
- UINT8 cpu_type = (cpustate->cpu_version >> 8) & 0x0f;
+ UINT8 cpu_type = (m_cpu_version >> 8) & 0x0f;
switch(cpu_type)
{
case 5: // Pentium
- pentium_msr_write(cpustate,offset,data,valid_msr);
+ pentium_msr_write(offset,data,valid_msr);
break;
case 6: // Pentium Pro, Pentium II, Pentium III
- p6_msr_write(cpustate,offset,data,valid_msr);
+ p6_msr_write(offset,data,valid_msr);
break;
}
}
diff --git a/src/emu/cpu/i386/i486ops.c b/src/emu/cpu/i386/i486ops.c
index b3bfcebe05f..81d310b2c66 100644
--- a/src/emu/cpu/i386/i486ops.c
+++ b/src/emu/cpu/i386/i486ops.c
@@ -1,12 +1,12 @@
// Intel 486+ specific opcodes
-static void I486OP(cpuid)(i386_state *cpustate) // Opcode 0x0F A2
+void i386_device::i486_cpuid() // Opcode 0x0F A2
{
- if (cpustate->cpuid_id0 == 0)
+ if (m_cpuid_id0 == 0)
{
// this 486 doesn't support the CPUID instruction
- logerror("CPUID not supported at %08x!\n", cpustate->eip);
- i386_trap(cpustate, 6, 0, 0);
+ logerror("CPUID not supported at %08x!\n", m_eip);
+ i386_trap(6, 0, 0);
}
else
{
@@ -14,196 +14,196 @@ static void I486OP(cpuid)(i386_state *cpustate) // Opcode 0x0F A2
{
case 0:
{
- REG32(EAX) = cpustate->cpuid_max_input_value_eax;
- REG32(EBX) = cpustate->cpuid_id0;
- REG32(ECX) = cpustate->cpuid_id2;
- REG32(EDX) = cpustate->cpuid_id1;
- CYCLES(cpustate,CYCLES_CPUID);
+ REG32(EAX) = m_cpuid_max_input_value_eax;
+ REG32(EBX) = m_cpuid_id0;
+ REG32(ECX) = m_cpuid_id2;
+ REG32(EDX) = m_cpuid_id1;
+ CYCLES(CYCLES_CPUID);
break;
}
case 1:
{
- REG32(EAX) = cpustate->cpu_version;
- REG32(EDX) = cpustate->feature_flags;
- CYCLES(cpustate,CYCLES_CPUID_EAX1);
+ REG32(EAX) = m_cpu_version;
+ REG32(EDX) = m_feature_flags;
+ CYCLES(CYCLES_CPUID_EAX1);
break;
}
}
}
}
-static void I486OP(invd)(i386_state *cpustate) // Opcode 0x0f 08
+void i386_device::i486_invd() // Opcode 0x0f 08
{
// Nothing to do ?
- CYCLES(cpustate,CYCLES_INVD);
+ CYCLES(CYCLES_INVD);
}
-static void I486OP(wbinvd)(i386_state *cpustate) // Opcode 0x0f 09
+void i386_device::i486_wbinvd() // Opcode 0x0f 09
{
// Nothing to do ?
}
-static void I486OP(cmpxchg_rm8_r8)(i386_state *cpustate) // Opcode 0x0f b0
+void i386_device::i486_cmpxchg_rm8_r8() // Opcode 0x0f b0
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
UINT8 src = LOAD_REG8(modrm);
if( REG8(AL) == dst ) {
STORE_RM8(modrm, src);
- cpustate->ZF = 1;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
+ m_ZF = 1;
+ CYCLES(CYCLES_CMPXCHG_REG_REG_T);
} else {
REG8(AL) = dst;
- cpustate->ZF = 0;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
+ m_ZF = 0;
+ CYCLES(CYCLES_CMPXCHG_REG_REG_F);
}
} else {
// TODO: Check write if needed
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT8 dst = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ UINT8 dst = READ8(ea);
UINT8 src = LOAD_REG8(modrm);
if( REG8(AL) == dst ) {
- WRITE8(cpustate,ea, src);
- cpustate->ZF = 1;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
+ WRITE8(ea, src);
+ m_ZF = 1;
+ CYCLES(CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG8(AL) = dst;
- cpustate->ZF = 0;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
+ m_ZF = 0;
+ CYCLES(CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
-static void I486OP(cmpxchg_rm16_r16)(i386_state *cpustate) // Opcode 0x0f b1
+void i386_device::i486_cmpxchg_rm16_r16() // Opcode 0x0f b1
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 src = LOAD_REG16(modrm);
if( REG16(AX) == dst ) {
STORE_RM16(modrm, src);
- cpustate->ZF = 1;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
+ m_ZF = 1;
+ CYCLES(CYCLES_CMPXCHG_REG_REG_T);
} else {
REG16(AX) = dst;
- cpustate->ZF = 0;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
+ m_ZF = 0;
+ CYCLES(CYCLES_CMPXCHG_REG_REG_F);
}
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT16 dst = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ UINT16 dst = READ16(ea);
UINT16 src = LOAD_REG16(modrm);
if( REG16(AX) == dst ) {
- WRITE16(cpustate,ea, src);
- cpustate->ZF = 1;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
+ WRITE16(ea, src);
+ m_ZF = 1;
+ CYCLES(CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG16(AX) = dst;
- cpustate->ZF = 0;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
+ m_ZF = 0;
+ CYCLES(CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
-static void I486OP(cmpxchg_rm32_r32)(i386_state *cpustate) // Opcode 0x0f b1
+void i386_device::i486_cmpxchg_rm32_r32() // Opcode 0x0f b1
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
STORE_RM32(modrm, src);
- cpustate->ZF = 1;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
+ m_ZF = 1;
+ CYCLES(CYCLES_CMPXCHG_REG_REG_T);
} else {
REG32(EAX) = dst;
- cpustate->ZF = 0;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
+ m_ZF = 0;
+ CYCLES(CYCLES_CMPXCHG_REG_REG_F);
}
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ UINT32 dst = READ32(ea);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
- WRITE32(cpustate,ea, src);
- cpustate->ZF = 1;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
+ WRITE32(ea, src);
+ m_ZF = 1;
+ CYCLES(CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EAX) = dst;
- cpustate->ZF = 0;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
+ m_ZF = 0;
+ CYCLES(CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
-static void I486OP(xadd_rm8_r8)(i386_state *cpustate) // Opcode 0x0f c0
+void i386_device::i486_xadd_rm8_r8() // Opcode 0x0f c0
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT8 dst = LOAD_RM8(modrm);
UINT8 src = LOAD_REG8(modrm);
STORE_REG8(modrm, dst);
STORE_RM8(modrm, dst + src);
- CYCLES(cpustate,CYCLES_XADD_REG_REG);
+ CYCLES(CYCLES_XADD_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT8 dst = READ8(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT8 dst = READ8(ea);
UINT8 src = LOAD_REG8(modrm);
- WRITE8(cpustate,ea, dst + src);
+ WRITE8(ea, dst + src);
STORE_REG8(modrm, dst);
- CYCLES(cpustate,CYCLES_XADD_REG_MEM);
+ CYCLES(CYCLES_XADD_REG_MEM);
}
}
-static void I486OP(xadd_rm16_r16)(i386_state *cpustate) // Opcode 0x0f c1
+void i386_device::i486_xadd_rm16_r16() // Opcode 0x0f c1
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 dst = LOAD_RM16(modrm);
UINT16 src = LOAD_REG16(modrm);
STORE_REG16(modrm, dst);
STORE_RM16(modrm, dst + src);
- CYCLES(cpustate,CYCLES_XADD_REG_REG);
+ CYCLES(CYCLES_XADD_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT16 dst = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT16 dst = READ16(ea);
UINT16 src = LOAD_REG16(modrm);
- WRITE16(cpustate,ea, dst + src);
+ WRITE16(ea, dst + src);
STORE_REG16(modrm, dst);
- CYCLES(cpustate,CYCLES_XADD_REG_MEM);
+ CYCLES(CYCLES_XADD_REG_MEM);
}
}
-static void I486OP(xadd_rm32_r32)(i386_state *cpustate) // Opcode 0x0f c1
+void i386_device::i486_xadd_rm32_r32() // Opcode 0x0f c1
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
STORE_REG32(modrm, dst);
STORE_RM32(modrm, dst + src);
- CYCLES(cpustate,CYCLES_XADD_REG_REG);
+ CYCLES(CYCLES_XADD_REG_REG);
} else {
- UINT32 ea = GetEA(cpustate,modrm,1);
- UINT32 dst = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,1);
+ UINT32 dst = READ32(ea);
UINT32 src = LOAD_REG32(modrm);
- WRITE32(cpustate,ea, dst + src);
+ WRITE32(ea, dst + src);
STORE_REG32(modrm, dst);
- CYCLES(cpustate,CYCLES_XADD_REG_MEM);
+ CYCLES(CYCLES_XADD_REG_MEM);
}
}
-static void I486OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01
+void i386_device::i486_group0F01_16() // Opcode 0x0f 01
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT16 address;
UINT32 ea;
@@ -213,13 +213,13 @@ static void I486OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01
{
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- ea = i386_translate( cpustate, CS, address, 1 );
+ ea = i386_translate( CS, address, 1 );
} else {
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
}
- WRITE16(cpustate,ea, cpustate->gdtr.limit);
- WRITE32(cpustate,ea + 2, cpustate->gdtr.base & 0xffffff);
- CYCLES(cpustate,CYCLES_SGDT);
+ WRITE16(ea, m_gdtr.limit);
+ WRITE32(ea + 2, m_gdtr.base & 0xffffff);
+ CYCLES(CYCLES_SGDT);
break;
}
case 1: /* SIDT */
@@ -227,101 +227,101 @@ static void I486OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01
if (modrm >= 0xc0)
{
address = LOAD_RM16(modrm);
- ea = i386_translate( cpustate, CS, address, 1 );
+ ea = i386_translate( CS, address, 1 );
}
else
{
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
}
- WRITE16(cpustate,ea, cpustate->idtr.limit);
- WRITE32(cpustate,ea + 2, cpustate->idtr.base & 0xffffff);
- CYCLES(cpustate,CYCLES_SIDT);
+ WRITE16(ea, m_idtr.limit);
+ WRITE32(ea + 2, m_idtr.base & 0xffffff);
+ CYCLES(CYCLES_SIDT);
break;
}
case 2: /* LGDT */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- ea = i386_translate( cpustate, CS, address, 0 );
+ ea = i386_translate( CS, address, 0 );
} else {
- ea = GetEA(cpustate,modrm,0);
+ ea = GetEA(modrm,0);
}
- cpustate->gdtr.limit = READ16(cpustate,ea);
- cpustate->gdtr.base = READ32(cpustate,ea + 2) & 0xffffff;
- CYCLES(cpustate,CYCLES_LGDT);
+ m_gdtr.limit = READ16(ea);
+ m_gdtr.base = READ32(ea + 2) & 0xffffff;
+ CYCLES(CYCLES_LGDT);
break;
}
case 3: /* LIDT */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM16(modrm);
- ea = i386_translate( cpustate, CS, address, 0 );
+ ea = i386_translate( CS, address, 0 );
} else {
- ea = GetEA(cpustate,modrm,0);
+ ea = GetEA(modrm,0);
}
- cpustate->idtr.limit = READ16(cpustate,ea);
- cpustate->idtr.base = READ32(cpustate,ea + 2) & 0xffffff;
- CYCLES(cpustate,CYCLES_LIDT);
+ m_idtr.limit = READ16(ea);
+ m_idtr.base = READ32(ea + 2) & 0xffffff;
+ CYCLES(CYCLES_LIDT);
break;
}
case 4: /* SMSW */
{
if( modrm >= 0xc0 ) {
- STORE_RM16(modrm, cpustate->cr[0]);
- CYCLES(cpustate,CYCLES_SMSW_REG);
+ STORE_RM16(modrm, m_cr[0]);
+ CYCLES(CYCLES_SMSW_REG);
} else {
- ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate,ea, cpustate->cr[0]);
- CYCLES(cpustate,CYCLES_SMSW_MEM);
+ ea = GetEA(modrm,1);
+ WRITE16(ea, m_cr[0]);
+ CYCLES(CYCLES_SMSW_MEM);
}
break;
}
case 6: /* LMSW */
{
UINT16 b;
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
b = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_LMSW_REG);
+ CYCLES(CYCLES_LMSW_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- CYCLES(cpustate,CYCLES_LMSW_MEM);
- b = READ16(cpustate,ea);
+ ea = GetEA(modrm,0);
+ CYCLES(CYCLES_LMSW_MEM);
+ b = READ16(ea);
}
if(PROTECTED_MODE)
b |= 0x0001; // cannot return to real mode using this instruction.
- cpustate->cr[0] &= ~0x0000000f;
- cpustate->cr[0] |= b & 0x0000000f;
+ m_cr[0] &= ~0x0000000f;
+ m_cr[0] |= b & 0x0000000f;
break;
}
case 7: /* INVLPG */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if(modrm >= 0xc0)
{
logerror("i486: invlpg with modrm %02X\n", modrm);
FAULT(FAULT_UD,0)
}
- ea = GetEA(cpustate,modrm,-1);
- CYCLES(cpustate,25); // TODO: add to cycles.h
- vtlb_flush_address(cpustate->vtlb, ea);
+ ea = GetEA(modrm,-1);
+ CYCLES(25); // TODO: add to cycles.h
+ vtlb_flush_address(m_vtlb, ea);
break;
}
default:
- report_invalid_modrm(cpustate, "group0F01_16", modrm);
+ report_invalid_modrm("group0F01_16", modrm);
break;
}
}
-static void I486OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01
+void i386_device::i486_group0F01_32() // Opcode 0x0f 01
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT32 address, ea;
switch( (modrm >> 3) & 0x7 )
@@ -330,13 +330,13 @@ static void I486OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01
{
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- ea = i386_translate( cpustate, CS, address, 1 );
+ ea = i386_translate( CS, address, 1 );
} else {
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
}
- WRITE16(cpustate,ea, cpustate->gdtr.limit);
- WRITE32(cpustate,ea + 2, cpustate->gdtr.base);
- CYCLES(cpustate,CYCLES_SGDT);
+ WRITE16(ea, m_gdtr.limit);
+ WRITE32(ea + 2, m_gdtr.base);
+ CYCLES(CYCLES_SGDT);
break;
}
case 1: /* SIDT */
@@ -344,171 +344,171 @@ static void I486OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01
if (modrm >= 0xc0)
{
address = LOAD_RM32(modrm);
- ea = i386_translate( cpustate, CS, address, 1 );
+ ea = i386_translate( CS, address, 1 );
}
else
{
- ea = GetEA(cpustate,modrm,1);
+ ea = GetEA(modrm,1);
}
- WRITE16(cpustate,ea, cpustate->idtr.limit);
- WRITE32(cpustate,ea + 2, cpustate->idtr.base);
- CYCLES(cpustate,CYCLES_SIDT);
+ WRITE16(ea, m_idtr.limit);
+ WRITE32(ea + 2, m_idtr.base);
+ CYCLES(CYCLES_SIDT);
break;
}
case 2: /* LGDT */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- ea = i386_translate( cpustate, CS, address, 0 );
+ ea = i386_translate( CS, address, 0 );
} else {
- ea = GetEA(cpustate,modrm,0);
+ ea = GetEA(modrm,0);
}
- cpustate->gdtr.limit = READ16(cpustate,ea);
- cpustate->gdtr.base = READ32(cpustate,ea + 2);
- CYCLES(cpustate,CYCLES_LGDT);
+ m_gdtr.limit = READ16(ea);
+ m_gdtr.base = READ32(ea + 2);
+ CYCLES(CYCLES_LGDT);
break;
}
case 3: /* LIDT */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if( modrm >= 0xc0 ) {
address = LOAD_RM32(modrm);
- ea = i386_translate( cpustate, CS, address, 0 );
+ ea = i386_translate( CS, address, 0 );
} else {
- ea = GetEA(cpustate,modrm,0);
+ ea = GetEA(modrm,0);
}
- cpustate->idtr.limit = READ16(cpustate,ea);
- cpustate->idtr.base = READ32(cpustate,ea + 2);
- CYCLES(cpustate,CYCLES_LIDT);
+ m_idtr.limit = READ16(ea);
+ m_idtr.base = READ32(ea + 2);
+ CYCLES(CYCLES_LIDT);
break;
}
case 4: /* SMSW */
{
if( modrm >= 0xc0 ) {
- STORE_RM32(modrm, cpustate->cr[0] & 0xffff);
- CYCLES(cpustate,CYCLES_SMSW_REG);
+ STORE_RM32(modrm, m_cr[0] & 0xffff);
+ CYCLES(CYCLES_SMSW_REG);
} else {
/* always 16-bit memory operand */
- ea = GetEA(cpustate,modrm,1);
- WRITE16(cpustate,ea, cpustate->cr[0]);
- CYCLES(cpustate,CYCLES_SMSW_MEM);
+ ea = GetEA(modrm,1);
+ WRITE16(ea, m_cr[0]);
+ CYCLES(CYCLES_SMSW_MEM);
}
break;
}
case 6: /* LMSW */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
UINT16 b;
if( modrm >= 0xc0 ) {
b = LOAD_RM16(modrm);
- CYCLES(cpustate,CYCLES_LMSW_REG);
+ CYCLES(CYCLES_LMSW_REG);
} else {
- ea = GetEA(cpustate,modrm,0);
- CYCLES(cpustate,CYCLES_LMSW_MEM);
- b = READ16(cpustate,ea);
+ ea = GetEA(modrm,0);
+ CYCLES(CYCLES_LMSW_MEM);
+ b = READ16(ea);
}
if(PROTECTED_MODE)
b |= 0x0001; // cannot return to real mode using this instruction.
- cpustate->cr[0] &= ~0x0000000f;
- cpustate->cr[0] |= b & 0x0000000f;
+ m_cr[0] &= ~0x0000000f;
+ m_cr[0] |= b & 0x0000000f;
break;
}
case 7: /* INVLPG */
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP,0)
if(modrm >= 0xc0)
{
logerror("i486: invlpg with modrm %02X\n", modrm);
FAULT(FAULT_UD,0)
}
- ea = GetEA(cpustate,modrm,-1);
- CYCLES(cpustate,25); // TODO: add to cycles.h
- vtlb_flush_address(cpustate->vtlb, ea);
+ ea = GetEA(modrm,-1);
+ CYCLES(25); // TODO: add to cycles.h
+ vtlb_flush_address(m_vtlb, ea);
break;
}
default:
- report_invalid_modrm(cpustate, "group0F01_32", modrm);
+ report_invalid_modrm("group0F01_32", modrm);
break;
}
}
-static void I486OP(bswap_eax)(i386_state *cpustate) // Opcode 0x0f 38
+void i386_device::i486_bswap_eax() // Opcode 0x0f 38
{
REG32(EAX) = SWITCH_ENDIAN_32(REG32(EAX));
- CYCLES(cpustate,1); // TODO
+ CYCLES(1); // TODO
}
-static void I486OP(bswap_ecx)(i386_state *cpustate) // Opcode 0x0f 39
+void i386_device::i486_bswap_ecx() // Opcode 0x0f 39
{
REG32(ECX) = SWITCH_ENDIAN_32(REG32(ECX));
- CYCLES(cpustate,1); // TODO
+ CYCLES(1); // TODO
}
-static void I486OP(bswap_edx)(i386_state *cpustate) // Opcode 0x0f 3A
+void i386_device::i486_bswap_edx() // Opcode 0x0f 3A
{
REG32(EDX) = SWITCH_ENDIAN_32(REG32(EDX));
- CYCLES(cpustate,1); // TODO
+ CYCLES(1); // TODO
}
-static void I486OP(bswap_ebx)(i386_state *cpustate) // Opcode 0x0f 3B
+void i386_device::i486_bswap_ebx() // Opcode 0x0f 3B
{
REG32(EBX) = SWITCH_ENDIAN_32(REG32(EBX));
- CYCLES(cpustate,1); // TODO
+ CYCLES(1); // TODO
}
-static void I486OP(bswap_esp)(i386_state *cpustate) // Opcode 0x0f 3C
+void i386_device::i486_bswap_esp() // Opcode 0x0f 3C
{
REG32(ESP) = SWITCH_ENDIAN_32(REG32(ESP));
- CYCLES(cpustate,1); // TODO
+ CYCLES(1); // TODO
}
-static void I486OP(bswap_ebp)(i386_state *cpustate) // Opcode 0x0f 3D
+void i386_device::i486_bswap_ebp() // Opcode 0x0f 3D
{
REG32(EBP) = SWITCH_ENDIAN_32(REG32(EBP));
- CYCLES(cpustate,1); // TODO
+ CYCLES(1); // TODO
}
-static void I486OP(bswap_esi)(i386_state *cpustate) // Opcode 0x0f 3E
+void i386_device::i486_bswap_esi() // Opcode 0x0f 3E
{
REG32(ESI) = SWITCH_ENDIAN_32(REG32(ESI));
- CYCLES(cpustate,1); // TODO
+ CYCLES(1); // TODO
}
-static void I486OP(bswap_edi)(i386_state *cpustate) // Opcode 0x0f 3F
+void i386_device::i486_bswap_edi() // Opcode 0x0f 3F
{
REG32(EDI) = SWITCH_ENDIAN_32(REG32(EDI));
- CYCLES(cpustate,1); // TODO
+ CYCLES(1); // TODO
}
-static void I486OP(mov_cr_r32)(i386_state *cpustate) // Opcode 0x0f 22
+void i386_device::i486_mov_cr_r32() // Opcode 0x0f 22
{
- if(PROTECTED_MODE && cpustate->CPL)
+ if(PROTECTED_MODE && m_CPL)
FAULT(FAULT_GP, 0);
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
UINT8 cr = (modrm >> 3) & 0x7;
- UINT32 oldcr = cpustate->cr[cr];
+ UINT32 oldcr = m_cr[cr];
UINT32 data = LOAD_RM32(modrm);
switch(cr)
{
case 0:
- CYCLES(cpustate,CYCLES_MOV_REG_CR0);
- if((oldcr ^ cpustate->cr[cr]) & 0x80010000)
- vtlb_flush_dynamic(cpustate->vtlb);
+ CYCLES(CYCLES_MOV_REG_CR0);
+ if((oldcr ^ m_cr[cr]) & 0x80010000)
+ vtlb_flush_dynamic(m_vtlb);
break;
- case 2: CYCLES(cpustate,CYCLES_MOV_REG_CR2); break;
+ case 2: CYCLES(CYCLES_MOV_REG_CR2); break;
case 3:
- CYCLES(cpustate,CYCLES_MOV_REG_CR3);
- vtlb_flush_dynamic(cpustate->vtlb);
+ CYCLES(CYCLES_MOV_REG_CR3);
+ vtlb_flush_dynamic(m_vtlb);
break;
- case 4: CYCLES(cpustate,1); break; // TODO
+ case 4: CYCLES(1); break; // TODO
default:
logerror("i386: mov_cr_r32 CR%d!\n", cr);
return;
}
- cpustate->cr[cr] = data;
+ m_cr[cr] = data;
}
diff --git a/src/emu/cpu/i386/pentops.c b/src/emu/cpu/i386/pentops.c
index aac1409c7dc..b64e0d663af 100644
--- a/src/emu/cpu/i386/pentops.c
+++ b/src/emu/cpu/i386/pentops.c
@@ -2,70 +2,70 @@
extern flag float32_is_nan( float32 a ); // since its not defined in softfloat.h
-INLINE void MMXPROLOG(i386_state *cpustate)
+void i386_device::MMXPROLOG()
{
- //cpustate->x87_sw &= ~(X87_SW_TOP_MASK << X87_SW_TOP_SHIFT); // top = 0
- cpustate->x87_tw = 0; // tag word = 0
+ //m_x87_sw &= ~(X87_SW_TOP_MASK << X87_SW_TOP_SHIFT); // top = 0
+ m_x87_tw = 0; // tag word = 0
}
-INLINE void READMMX(i386_state *cpustate,UINT32 ea,MMX_REG &r)
+void i386_device::READMMX(UINT32 ea,MMX_REG &r)
{
- r.q=READ64(cpustate, ea);
+ r.q=READ64(ea);
}
-INLINE void WRITEMMX(i386_state *cpustate,UINT32 ea,MMX_REG &r)
+void i386_device::WRITEMMX(UINT32 ea,MMX_REG &r)
{
- WRITE64(cpustate, ea, r.q);
+ WRITE64(ea, r.q);
}
-INLINE void READXMM(i386_state *cpustate,UINT32 ea,XMM_REG &r)
+void i386_device::READXMM(UINT32 ea,XMM_REG &r)
{
- r.q[0]=READ64(cpustate, ea);
- r.q[1]=READ64(cpustate, ea+8);
+ r.q[0]=READ64(ea);
+ r.q[1]=READ64(ea+8);
}
-INLINE void WRITEXMM(i386_state *cpustate,UINT32 ea,XMM_REG &r)
+void i386_device::WRITEXMM(UINT32 ea,i386_device::XMM_REG &r)
{
- WRITE64(cpustate, ea, r.q[0]);
- WRITE64(cpustate, ea+8, r.q[1]);
+ WRITE64(ea, r.q[0]);
+ WRITE64(ea+8, r.q[1]);
}
-INLINE void READXMM_LO64(i386_state *cpustate,UINT32 ea,XMM_REG &r)
+void i386_device::READXMM_LO64(UINT32 ea,i386_device::XMM_REG &r)
{
- r.q[0]=READ64(cpustate, ea);
+ r.q[0]=READ64(ea);
}
-INLINE void WRITEXMM_LO64(i386_state *cpustate,UINT32 ea,XMM_REG &r)
+void i386_device::WRITEXMM_LO64(UINT32 ea,i386_device::XMM_REG &r)
{
- WRITE64(cpustate, ea, r.q[0]);
+ WRITE64(ea, r.q[0]);
}
-INLINE void READXMM_HI64(i386_state *cpustate,UINT32 ea,XMM_REG &r)
+void i386_device::READXMM_HI64(UINT32 ea,i386_device::XMM_REG &r)
{
- r.q[1]=READ64(cpustate, ea);
+ r.q[1]=READ64(ea);
}
-INLINE void WRITEXMM_HI64(i386_state *cpustate,UINT32 ea,XMM_REG &r)
+void i386_device::WRITEXMM_HI64(UINT32 ea,i386_device::XMM_REG &r)
{
- WRITE64(cpustate, ea, r.q[1]);
+ WRITE64(ea, r.q[1]);
}
-static void PENTIUMOP(rdmsr)(i386_state *cpustate) // Opcode 0x0f 32
+void i386_device::pentium_rdmsr() // Opcode 0x0f 32
{
UINT64 data;
UINT8 valid_msr = 0;
- data = MSR_READ(cpustate,REG32(ECX),&valid_msr);
+ data = MSR_READ(REG32(ECX),&valid_msr);
REG32(EDX) = data >> 32;
REG32(EAX) = data & 0xffffffff;
- if(cpustate->CPL != 0 || valid_msr == 0) // if current privilege level isn't 0 or the register isn't recognized ...
+ if(m_CPL != 0 || valid_msr == 0) // if current privilege level isn't 0 or the register isn't recognized ...
FAULT(FAULT_GP,0) // ... throw a general exception fault
- CYCLES(cpustate,CYCLES_RDMSR);
+ CYCLES(CYCLES_RDMSR);
}
-static void PENTIUMOP(wrmsr)(i386_state *cpustate) // Opcode 0x0f 30
+void i386_device::pentium_wrmsr() // Opcode 0x0f 30
{
UINT64 data;
UINT8 valid_msr = 0;
@@ -73,1061 +73,1061 @@ static void PENTIUMOP(wrmsr)(i386_state *cpustate) // Opcode 0x0f 30
data = (UINT64)REG32(EAX);
data |= (UINT64)(REG32(EDX)) << 32;
- MSR_WRITE(cpustate,REG32(ECX),data,&valid_msr);
+ MSR_WRITE(REG32(ECX),data,&valid_msr);
- if(cpustate->CPL != 0 || valid_msr == 0) // if current privilege level isn't 0 or the register isn't recognized
+ if(m_CPL != 0 || valid_msr == 0) // if current privilege level isn't 0 or the register isn't recognized
FAULT(FAULT_GP,0) // ... throw a general exception fault
- CYCLES(cpustate,1); // TODO: correct cycle count (~30-45)
+ CYCLES(1); // TODO: correct cycle count (~30-45)
}
-static void PENTIUMOP(rdtsc)(i386_state *cpustate) // Opcode 0x0f 31
+void i386_device::pentium_rdtsc() // Opcode 0x0f 31
{
- UINT64 ts = cpustate->tsc + (cpustate->base_cycles - cpustate->cycles);
+ UINT64 ts = m_tsc + (m_base_cycles - m_cycles);
REG32(EAX) = (UINT32)(ts);
REG32(EDX) = (UINT32)(ts >> 32);
- CYCLES(cpustate,CYCLES_RDTSC);
+ CYCLES(CYCLES_RDTSC);
}
-static void PENTIUMOP(ud2)(i386_state *cpustate) // Opcode 0x0f 0b
+void i386_device::pentium_ud2() // Opcode 0x0f 0b
{
- i386_trap(cpustate, 6, 0, 0);
+ i386_trap(6, 0, 0);
}
-static void PENTIUMOP(rsm)(i386_state *cpustate)
+void i386_device::pentium_rsm()
{
- UINT32 smram_state = cpustate->smbase + 0xfe00;
- if(!cpustate->smm)
+ UINT32 smram_state = m_smbase + 0xfe00;
+ if(!m_smm)
{
- logerror("i386: Invalid RSM outside SMM at %08X\n", cpustate->pc - 1);
- i386_trap(cpustate, 6, 0, 0);
+ logerror("i386: Invalid RSM outside SMM at %08X\n", m_pc - 1);
+ i386_trap(6, 0, 0);
return;
}
// load state, no sanity checks anywhere
- cpustate->smbase = READ32(cpustate, smram_state+SMRAM_SMBASE);
- cpustate->cr[4] = READ32(cpustate, smram_state+SMRAM_IP5_CR4);
- cpustate->sreg[ES].limit = READ32(cpustate, smram_state+SMRAM_IP5_ESLIM);
- cpustate->sreg[ES].base = READ32(cpustate, smram_state+SMRAM_IP5_ESBASE);
- cpustate->sreg[ES].flags = READ32(cpustate, smram_state+SMRAM_IP5_ESACC);
- cpustate->sreg[CS].limit = READ32(cpustate, smram_state+SMRAM_IP5_CSLIM);
- cpustate->sreg[CS].base = READ32(cpustate, smram_state+SMRAM_IP5_CSBASE);
- cpustate->sreg[CS].flags = READ32(cpustate, smram_state+SMRAM_IP5_CSACC);
- cpustate->sreg[SS].limit = READ32(cpustate, smram_state+SMRAM_IP5_SSLIM);
- cpustate->sreg[SS].base = READ32(cpustate, smram_state+SMRAM_IP5_SSBASE);
- cpustate->sreg[SS].flags = READ32(cpustate, smram_state+SMRAM_IP5_SSACC);
- cpustate->sreg[DS].limit = READ32(cpustate, smram_state+SMRAM_IP5_DSLIM);
- cpustate->sreg[DS].base = READ32(cpustate, smram_state+SMRAM_IP5_DSBASE);
- cpustate->sreg[DS].flags = READ32(cpustate, smram_state+SMRAM_IP5_DSACC);
- cpustate->sreg[FS].limit = READ32(cpustate, smram_state+SMRAM_IP5_FSLIM);
- cpustate->sreg[FS].base = READ32(cpustate, smram_state+SMRAM_IP5_FSBASE);
- cpustate->sreg[FS].flags = READ32(cpustate, smram_state+SMRAM_IP5_FSACC);
- cpustate->sreg[GS].limit = READ32(cpustate, smram_state+SMRAM_IP5_GSLIM);
- cpustate->sreg[GS].base = READ32(cpustate, smram_state+SMRAM_IP5_GSBASE);
- cpustate->sreg[GS].flags = READ32(cpustate, smram_state+SMRAM_IP5_GSACC);
- cpustate->ldtr.flags = READ32(cpustate, smram_state+SMRAM_IP5_LDTACC);
- cpustate->ldtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_LDTLIM);
- cpustate->ldtr.base = READ32(cpustate, smram_state+SMRAM_IP5_LDTBASE);
- cpustate->gdtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_GDTLIM);
- cpustate->gdtr.base = READ32(cpustate, smram_state+SMRAM_IP5_GDTBASE);
- cpustate->idtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_IDTLIM);
- cpustate->idtr.base = READ32(cpustate, smram_state+SMRAM_IP5_IDTBASE);
- cpustate->task.limit = READ32(cpustate, smram_state+SMRAM_IP5_TRLIM);
- cpustate->task.base = READ32(cpustate, smram_state+SMRAM_IP5_TRBASE);
- cpustate->task.flags = READ32(cpustate, smram_state+SMRAM_IP5_TRACC);
-
- cpustate->sreg[ES].selector = READ32(cpustate, smram_state+SMRAM_ES);
- cpustate->sreg[CS].selector = READ32(cpustate, smram_state+SMRAM_CS);
- cpustate->sreg[SS].selector = READ32(cpustate, smram_state+SMRAM_SS);
- cpustate->sreg[DS].selector = READ32(cpustate, smram_state+SMRAM_DS);
- cpustate->sreg[FS].selector = READ32(cpustate, smram_state+SMRAM_FS);
- cpustate->sreg[GS].selector = READ32(cpustate, smram_state+SMRAM_GS);
- cpustate->ldtr.segment = READ32(cpustate, smram_state+SMRAM_LDTR);
- cpustate->task.segment = READ32(cpustate, smram_state+SMRAM_TR);
-
- cpustate->dr[7] = READ32(cpustate, smram_state+SMRAM_DR7);
- cpustate->dr[6] = READ32(cpustate, smram_state+SMRAM_DR6);
- REG32(EAX) = READ32(cpustate, smram_state+SMRAM_EAX);
- REG32(ECX) = READ32(cpustate, smram_state+SMRAM_ECX);
- REG32(EDX) = READ32(cpustate, smram_state+SMRAM_EDX);
- REG32(EBX) = READ32(cpustate, smram_state+SMRAM_EBX);
- REG32(ESP) = READ32(cpustate, smram_state+SMRAM_ESP);
- REG32(EBP) = READ32(cpustate, smram_state+SMRAM_EBP);
- REG32(ESI) = READ32(cpustate, smram_state+SMRAM_ESI);
- REG32(EDI) = READ32(cpustate, smram_state+SMRAM_EDI);
- cpustate->eip = READ32(cpustate, smram_state+SMRAM_EIP);
- cpustate->eflags = READ32(cpustate, smram_state+SMRAM_EAX);
- cpustate->cr[3] = READ32(cpustate, smram_state+SMRAM_CR3);
- cpustate->cr[0] = READ32(cpustate, smram_state+SMRAM_CR0);
-
- cpustate->CPL = (cpustate->sreg[SS].flags >> 13) & 3; // cpl == dpl of ss
+ m_smbase = READ32(smram_state+SMRAM_SMBASE);
+ m_cr[4] = READ32(smram_state+SMRAM_IP5_CR4);
+ m_sreg[ES].limit = READ32(smram_state+SMRAM_IP5_ESLIM);
+ m_sreg[ES].base = READ32(smram_state+SMRAM_IP5_ESBASE);
+ m_sreg[ES].flags = READ32(smram_state+SMRAM_IP5_ESACC);
+ m_sreg[CS].limit = READ32(smram_state+SMRAM_IP5_CSLIM);
+ m_sreg[CS].base = READ32(smram_state+SMRAM_IP5_CSBASE);
+ m_sreg[CS].flags = READ32(smram_state+SMRAM_IP5_CSACC);
+ m_sreg[SS].limit = READ32(smram_state+SMRAM_IP5_SSLIM);
+ m_sreg[SS].base = READ32(smram_state+SMRAM_IP5_SSBASE);
+ m_sreg[SS].flags = READ32(smram_state+SMRAM_IP5_SSACC);
+ m_sreg[DS].limit = READ32(smram_state+SMRAM_IP5_DSLIM);
+ m_sreg[DS].base = READ32(smram_state+SMRAM_IP5_DSBASE);
+ m_sreg[DS].flags = READ32(smram_state+SMRAM_IP5_DSACC);
+ m_sreg[FS].limit = READ32(smram_state+SMRAM_IP5_FSLIM);
+ m_sreg[FS].base = READ32(smram_state+SMRAM_IP5_FSBASE);
+ m_sreg[FS].flags = READ32(smram_state+SMRAM_IP5_FSACC);
+ m_sreg[GS].limit = READ32(smram_state+SMRAM_IP5_GSLIM);
+ m_sreg[GS].base = READ32(smram_state+SMRAM_IP5_GSBASE);
+ m_sreg[GS].flags = READ32(smram_state+SMRAM_IP5_GSACC);
+ m_ldtr.flags = READ32(smram_state+SMRAM_IP5_LDTACC);
+ m_ldtr.limit = READ32(smram_state+SMRAM_IP5_LDTLIM);
+ m_ldtr.base = READ32(smram_state+SMRAM_IP5_LDTBASE);
+ m_gdtr.limit = READ32(smram_state+SMRAM_IP5_GDTLIM);
+ m_gdtr.base = READ32(smram_state+SMRAM_IP5_GDTBASE);
+ m_idtr.limit = READ32(smram_state+SMRAM_IP5_IDTLIM);
+ m_idtr.base = READ32(smram_state+SMRAM_IP5_IDTBASE);
+ m_task.limit = READ32(smram_state+SMRAM_IP5_TRLIM);
+ m_task.base = READ32(smram_state+SMRAM_IP5_TRBASE);
+ m_task.flags = READ32(smram_state+SMRAM_IP5_TRACC);
+
+ m_sreg[ES].selector = READ32(smram_state+SMRAM_ES);
+ m_sreg[CS].selector = READ32(smram_state+SMRAM_CS);
+ m_sreg[SS].selector = READ32(smram_state+SMRAM_SS);
+ m_sreg[DS].selector = READ32(smram_state+SMRAM_DS);
+ m_sreg[FS].selector = READ32(smram_state+SMRAM_FS);
+ m_sreg[GS].selector = READ32(smram_state+SMRAM_GS);
+ m_ldtr.segment = READ32(smram_state+SMRAM_LDTR);
+ m_task.segment = READ32(smram_state+SMRAM_TR);
+
+ m_dr[7] = READ32(smram_state+SMRAM_DR7);
+ m_dr[6] = READ32(smram_state+SMRAM_DR6);
+ REG32(EAX) = READ32(smram_state+SMRAM_EAX);
+ REG32(ECX) = READ32(smram_state+SMRAM_ECX);
+ REG32(EDX) = READ32(smram_state+SMRAM_EDX);
+ REG32(EBX) = READ32(smram_state+SMRAM_EBX);
+ REG32(ESP) = READ32(smram_state+SMRAM_ESP);
+ REG32(EBP) = READ32(smram_state+SMRAM_EBP);
+ REG32(ESI) = READ32(smram_state+SMRAM_ESI);
+ REG32(EDI) = READ32(smram_state+SMRAM_EDI);
+ m_eip = READ32(smram_state+SMRAM_EIP);
+ m_eflags = READ32(smram_state+SMRAM_EAX);
+ m_cr[3] = READ32(smram_state+SMRAM_CR3);
+ m_cr[0] = READ32(smram_state+SMRAM_CR0);
+
+ m_CPL = (m_sreg[SS].flags >> 13) & 3; // cpl == dpl of ss
for(int i = 0; i < GS; i++)
{
if(PROTECTED_MODE && !V8086_MODE)
{
- cpustate->sreg[i].valid = cpustate->sreg[i].selector ? true : false;
- cpustate->sreg[i].d = (cpustate->sreg[i].flags & 0x4000) ? 1 : 0;
+ m_sreg[i].valid = m_sreg[i].selector ? true : false;
+ m_sreg[i].d = (m_sreg[i].flags & 0x4000) ? 1 : 0;
}
else
- cpustate->sreg[i].valid = true;
+ m_sreg[i].valid = true;
}
- if(!cpustate->smiact.isnull())
- cpustate->smiact(false);
- cpustate->smm = false;
+ if(!m_smiact.isnull())
+ m_smiact(false);
+ m_smm = false;
- CHANGE_PC(cpustate,cpustate->eip);
- cpustate->nmi_masked = false;
- if(cpustate->smi_latched)
+ CHANGE_PC(m_eip);
+ m_nmi_masked = false;
+ if(m_smi_latched)
{
- pentium_smi(cpustate);
+ pentium_smi();
return;
}
- if(cpustate->nmi_latched)
+ if(m_nmi_latched)
{
- cpustate->nmi_latched = false;
- i386_trap(cpustate, 2, 1, 0);
+ m_nmi_latched = false;
+ i386_trap(2, 1, 0);
}
}
-static void PENTIUMOP(prefetch_m8)(i386_state *cpustate) // Opcode 0x0f 18
+void i386_device::pentium_prefetch_m8() // Opcode 0x0f 18
{
- UINT8 modrm = FETCH(cpustate);
- UINT32 ea = GetEA(cpustate,modrm,0);
- CYCLES(cpustate,1+(ea & 1)); // TODO: correct cycle count
+ UINT8 modrm = FETCH();
+ UINT32 ea = GetEA(modrm,0);
+ CYCLES(1+(ea & 1)); // TODO: correct cycle count
}
-static void PENTIUMOP(cmovo_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 40
+void i386_device::pentium_cmovo_r16_rm16() // Opcode 0x0f 40
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->OF == 1)
+ if (m_OF == 1)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->OF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_OF == 1)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovo_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 40
+void i386_device::pentium_cmovo_r32_rm32() // Opcode 0x0f 40
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->OF == 1)
+ if (m_OF == 1)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->OF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_OF == 1)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovno_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 41
+void i386_device::pentium_cmovno_r16_rm16() // Opcode 0x0f 41
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->OF == 0)
+ if (m_OF == 0)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->OF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_OF == 0)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovno_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 41
+void i386_device::pentium_cmovno_r32_rm32() // Opcode 0x0f 41
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->OF == 0)
+ if (m_OF == 0)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->OF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_OF == 0)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovb_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 42
+void i386_device::pentium_cmovb_r16_rm16() // Opcode 0x0f 42
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->CF == 1)
+ if (m_CF == 1)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->CF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_CF == 1)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovb_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 42
+void i386_device::pentium_cmovb_r32_rm32() // Opcode 0x0f 42
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->CF == 1)
+ if (m_CF == 1)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->CF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_CF == 1)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovae_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 43
+void i386_device::pentium_cmovae_r16_rm16() // Opcode 0x0f 43
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->CF == 0)
+ if (m_CF == 0)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->CF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_CF == 0)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovae_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 43
+void i386_device::pentium_cmovae_r32_rm32() // Opcode 0x0f 43
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->CF == 0)
+ if (m_CF == 0)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->CF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_CF == 0)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmove_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 44
+void i386_device::pentium_cmove_r16_rm16() // Opcode 0x0f 44
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->ZF == 1)
+ if (m_ZF == 1)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->ZF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_ZF == 1)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmove_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 44
+void i386_device::pentium_cmove_r32_rm32() // Opcode 0x0f 44
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->ZF == 1)
+ if (m_ZF == 1)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->ZF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_ZF == 1)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovne_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 45
+void i386_device::pentium_cmovne_r16_rm16() // Opcode 0x0f 45
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->ZF == 0)
+ if (m_ZF == 0)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->ZF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_ZF == 0)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovne_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 45
+void i386_device::pentium_cmovne_r32_rm32() // Opcode 0x0f 45
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->ZF == 0)
+ if (m_ZF == 0)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->ZF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_ZF == 0)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovbe_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 46
+void i386_device::pentium_cmovbe_r16_rm16() // Opcode 0x0f 46
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if ((cpustate->CF == 1) || (cpustate->ZF == 1))
+ if ((m_CF == 1) || (m_ZF == 1))
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if ((cpustate->CF == 1) || (cpustate->ZF == 1))
+ UINT32 ea = GetEA(modrm,0);
+ if ((m_CF == 1) || (m_ZF == 1))
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovbe_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 46
+void i386_device::pentium_cmovbe_r32_rm32() // Opcode 0x0f 46
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if ((cpustate->CF == 1) || (cpustate->ZF == 1))
+ if ((m_CF == 1) || (m_ZF == 1))
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if ((cpustate->CF == 1) || (cpustate->ZF == 1))
+ UINT32 ea = GetEA(modrm,0);
+ if ((m_CF == 1) || (m_ZF == 1))
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmova_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 47
+void i386_device::pentium_cmova_r16_rm16() // Opcode 0x0f 47
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if ((cpustate->CF == 0) && (cpustate->ZF == 0))
+ if ((m_CF == 0) && (m_ZF == 0))
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if ((cpustate->CF == 0) && (cpustate->ZF == 0))
+ UINT32 ea = GetEA(modrm,0);
+ if ((m_CF == 0) && (m_ZF == 0))
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmova_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 47
+void i386_device::pentium_cmova_r32_rm32() // Opcode 0x0f 47
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if ((cpustate->CF == 0) && (cpustate->ZF == 0))
+ if ((m_CF == 0) && (m_ZF == 0))
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if ((cpustate->CF == 0) && (cpustate->ZF == 0))
+ UINT32 ea = GetEA(modrm,0);
+ if ((m_CF == 0) && (m_ZF == 0))
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovs_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 48
+void i386_device::pentium_cmovs_r16_rm16() // Opcode 0x0f 48
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->SF == 1)
+ if (m_SF == 1)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->SF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_SF == 1)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovs_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 48
+void i386_device::pentium_cmovs_r32_rm32() // Opcode 0x0f 48
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->SF == 1)
+ if (m_SF == 1)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->SF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_SF == 1)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovns_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 49
+void i386_device::pentium_cmovns_r16_rm16() // Opcode 0x0f 49
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->SF == 0)
+ if (m_SF == 0)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->SF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_SF == 0)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovns_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 49
+void i386_device::pentium_cmovns_r32_rm32() // Opcode 0x0f 49
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->SF == 0)
+ if (m_SF == 0)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->SF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_SF == 0)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovp_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 4a
+void i386_device::pentium_cmovp_r16_rm16() // Opcode 0x0f 4a
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->PF == 1)
+ if (m_PF == 1)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->PF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_PF == 1)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovp_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 4a
+void i386_device::pentium_cmovp_r32_rm32() // Opcode 0x0f 4a
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->PF == 1)
+ if (m_PF == 1)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->PF == 1)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_PF == 1)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovnp_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 4b
+void i386_device::pentium_cmovnp_r16_rm16() // Opcode 0x0f 4b
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->PF == 0)
+ if (m_PF == 0)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->PF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_PF == 0)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovnp_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 4b
+void i386_device::pentium_cmovnp_r32_rm32() // Opcode 0x0f 4b
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->PF == 0)
+ if (m_PF == 0)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->PF == 0)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_PF == 0)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovl_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 4c
+void i386_device::pentium_cmovl_r16_rm16() // Opcode 0x0f 4c
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->SF != cpustate->OF)
+ if (m_SF != m_OF)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->SF != cpustate->OF)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_SF != m_OF)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovl_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 4c
+void i386_device::pentium_cmovl_r32_rm32() // Opcode 0x0f 4c
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->SF != cpustate->OF)
+ if (m_SF != m_OF)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->SF != cpustate->OF)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_SF != m_OF)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovge_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 4d
+void i386_device::pentium_cmovge_r16_rm16() // Opcode 0x0f 4d
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->SF == cpustate->OF)
+ if (m_SF == m_OF)
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->SF == cpustate->OF)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_SF == m_OF)
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovge_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 4d
+void i386_device::pentium_cmovge_r32_rm32() // Opcode 0x0f 4d
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if (cpustate->SF == cpustate->OF)
+ if (m_SF == m_OF)
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if (cpustate->SF == cpustate->OF)
+ UINT32 ea = GetEA(modrm,0);
+ if (m_SF == m_OF)
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovle_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 4e
+void i386_device::pentium_cmovle_r16_rm16() // Opcode 0x0f 4e
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if ((cpustate->ZF == 1) || (cpustate->SF != cpustate->OF))
+ if ((m_ZF == 1) || (m_SF != m_OF))
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if ((cpustate->ZF == 1) || (cpustate->SF != cpustate->OF))
+ UINT32 ea = GetEA(modrm,0);
+ if ((m_ZF == 1) || (m_SF != m_OF))
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovle_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 4e
+void i386_device::pentium_cmovle_r32_rm32() // Opcode 0x0f 4e
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if ((cpustate->ZF == 1) || (cpustate->SF != cpustate->OF))
+ if ((m_ZF == 1) || (m_SF != m_OF))
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if ((cpustate->ZF == 1) || (cpustate->SF != cpustate->OF))
+ UINT32 ea = GetEA(modrm,0);
+ if ((m_ZF == 1) || (m_SF != m_OF))
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovg_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 4f
+void i386_device::pentium_cmovg_r16_rm16() // Opcode 0x0f 4f
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if ((cpustate->ZF == 0) && (cpustate->SF == cpustate->OF))
+ if ((m_ZF == 0) && (m_SF == m_OF))
{
src = LOAD_RM16(modrm);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if ((cpustate->ZF == 0) && (cpustate->SF == cpustate->OF))
+ UINT32 ea = GetEA(modrm,0);
+ if ((m_ZF == 0) && (m_SF == m_OF))
{
- src = READ16(cpustate,ea);
+ src = READ16(ea);
STORE_REG16(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(cmovg_r32_rm32)(i386_state *cpustate) // Opcode 0x0f 4f
+void i386_device::pentium_cmovg_r32_rm32() // Opcode 0x0f 4f
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 )
{
- if ((cpustate->ZF == 0) && (cpustate->SF == cpustate->OF))
+ if ((m_ZF == 0) && (m_SF == m_OF))
{
src = LOAD_RM32(modrm);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
else
{
- UINT32 ea = GetEA(cpustate,modrm,0);
- if ((cpustate->ZF == 0) && (cpustate->SF == cpustate->OF))
+ UINT32 ea = GetEA(modrm,0);
+ if ((m_ZF == 0) && (m_SF == m_OF))
{
- src = READ32(cpustate,ea);
+ src = READ32(ea);
STORE_REG32(modrm, src);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(movnti_m16_r16)(i386_state *cpustate) // Opcode 0f c3
+void i386_device::pentium_movnti_m16_r16() // Opcode 0f c3
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
// unsupported by cpu
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
} else {
// since cache is not implemented
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITE16(cpustate,ea,LOAD_RM16(modrm));
- CYCLES(cpustate,1); // TODO: correct cycle count
+ UINT32 ea = GetEA(modrm, 0);
+ WRITE16(ea,LOAD_RM16(modrm));
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(movnti_m32_r32)(i386_state *cpustate) // Opcode 0f c3
+void i386_device::pentium_movnti_m32_r32() // Opcode 0f c3
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
// unsupported by cpu
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
} else {
// since cache is not implemented
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITE32(cpustate,ea,LOAD_RM32(modrm));
- CYCLES(cpustate,1); // TODO: correct cycle count
+ UINT32 ea = GetEA(modrm, 0);
+ WRITE32(ea,LOAD_RM32(modrm));
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void I386OP(cyrix_unknown)(i386_state *cpustate) // Opcode 0x0f 74
+void i386_device::i386_cyrix_unknown() // Opcode 0x0f 74
{
logerror("Unemulated 0x0f 0x74 opcode called\n");
- CYCLES(cpustate,1);
+ CYCLES(1);
}
-static void PENTIUMOP(cmpxchg8b_m64)(i386_state *cpustate) // Opcode 0x0f c7
+void i386_device::pentium_cmpxchg8b_m64() // Opcode 0x0f c7
{
- UINT8 modm = FETCH(cpustate);
+ UINT8 modm = FETCH();
if( modm >= 0xc0 ) {
- report_invalid_modrm(cpustate, "cmpxchg8b_m64", modm);
+ report_invalid_modrm("cmpxchg8b_m64", modm);
} else {
- UINT32 ea = GetEA(cpustate, modm, 0);
- UINT64 value = READ64(cpustate,ea);
+ UINT32 ea = GetEA(modm, 0);
+ UINT64 value = READ64(ea);
UINT64 edx_eax = (((UINT64) REG32(EDX)) << 32) | REG32(EAX);
UINT64 ecx_ebx = (((UINT64) REG32(ECX)) << 32) | REG32(EBX);
if( value == edx_eax ) {
- WRITE64(cpustate,ea, ecx_ebx);
- cpustate->ZF = 1;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
+ WRITE64(ea, ecx_ebx);
+ m_ZF = 1;
+ CYCLES(CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EDX) = (UINT32) (value >> 32);
REG32(EAX) = (UINT32) (value >> 0);
- cpustate->ZF = 0;
- CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
+ m_ZF = 0;
+ CYCLES(CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
-static void PENTIUMOP(movntq_m64_r64)(i386_state *cpustate) // Opcode 0f e7
+void i386_device::pentium_movntq_m64_r64() // Opcode 0f e7
{
- //MMXPROLOG(cpustate); // TODO: check if needed
- UINT8 modrm = FETCH(cpustate);
+ //MMXPROLOG(); // TODO: check if needed
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
- CYCLES(cpustate,1); // unsupported
+ CYCLES(1); // unsupported
} else {
// since cache is not implemented
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITEMMX(cpustate, ea, MMX((modrm >> 3) & 0x7));
- CYCLES(cpustate,1); // TODO: correct cycle count
+ UINT32 ea = GetEA(modrm, 0);
+ WRITEMMX(ea, MMX((modrm >> 3) & 0x7));
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void PENTIUMOP(maskmovq_r64_r64)(i386_state *cpustate) // Opcode 0f f7
+void i386_device::pentium_maskmovq_r64_r64() // Opcode 0f f7
{
int s,m,n;
- UINT8 modm = FETCH(cpustate);
- UINT32 ea = GetEA(cpustate, 7, 0); // ds:di/edi/rdi register
- MMXPROLOG(cpustate);
+ UINT8 modm = FETCH();
+ UINT32 ea = GetEA(7, 0); // ds:di/edi/rdi register
+ MMXPROLOG();
s=(modm >> 3) & 7;
m=modm & 7;
for (n=0;n <= 7;n++)
if (MMX(m).b[n] & 127)
- WRITE8(cpustate, ea+n, MMX(s).b[n]);
+ WRITE8(ea+n, MMX(s).b[n]);
}
-static void PENTIUMOP(popcnt_r16_rm16)(i386_state *cpustate) // Opcode f3 0f b8
+void i386_device::pentium_popcnt_r16_rm16() // Opcode f3 0f b8
{
UINT16 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
int n,count;
if( modrm >= 0xc0 ) {
src = LOAD_RM16(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ16(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ16(ea);
}
count=0;
for (n=0;n < 16;n++) {
@@ -1135,20 +1135,20 @@ static void PENTIUMOP(popcnt_r16_rm16)(i386_state *cpustate) // Opcode f3 0f
src=src >> 1;
}
STORE_REG16(modrm, count);
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void PENTIUMOP(popcnt_r32_rm32)(i386_state *cpustate) // Opcode f3 0f b8
+void i386_device::pentium_popcnt_r32_rm32() // Opcode f3 0f b8
{
UINT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
int n,count;
if( modrm >= 0xc0 ) {
src = LOAD_RM32(modrm);
} else {
- UINT32 ea = GetEA(cpustate,modrm,0);
- src = READ32(cpustate,ea);
+ UINT32 ea = GetEA(modrm,0);
+ src = READ32(ea);
}
count=0;
for (n=0;n < 32;n++) {
@@ -1156,20 +1156,20 @@ static void PENTIUMOP(popcnt_r32_rm32)(i386_state *cpustate) // Opcode f3 0f
src=src >> 1;
}
STORE_REG32(modrm, count);
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void PENTIUMOP(tzcnt_r16_rm16)(i386_state *cpustate)
+void i386_device::pentium_tzcnt_r16_rm16()
{
// for CPUs that don't support TZCNT, fall back to BSF
- i386_bsf_r16_rm16(cpustate);
+ i386_bsf_r16_rm16();
// TODO: actually implement TZCNT
}
-static void PENTIUMOP(tzcnt_r32_rm32)(i386_state *cpustate)
+void i386_device::pentium_tzcnt_r32_rm32()
{
// for CPUs that don't support TZCNT, fall back to BSF
- i386_bsf_r32_rm32(cpustate);
+ i386_bsf_r32_rm32();
// TODO: actually implement TZCNT
}
@@ -1200,11 +1200,11 @@ INLINE INT16 SaturatedSignedDwordToSignedWord(INT32 dword)
return (INT16)dword;
}
-static void MMXOP(group_0f71)(i386_state *cpustate) // Opcode 0f 71
+void i386_device::mmx_group_0f71() // Opcode 0f 71
{
- UINT8 modm = FETCH(cpustate);
- UINT8 imm8 = FETCH(cpustate);
- MMXPROLOG(cpustate);
+ UINT8 modm = FETCH();
+ UINT8 imm8 = FETCH();
+ MMXPROLOG();
if( modm >= 0xc0 ) {
switch ( (modm & 0x38) >> 3 )
{
@@ -1227,16 +1227,16 @@ static void MMXOP(group_0f71)(i386_state *cpustate) // Opcode 0f 71
MMX(modm & 7).w[3]=MMX(modm & 7).w[3] << imm8;
break;
default:
- report_invalid_modrm(cpustate, "mmx_group0f71", modm);
+ report_invalid_modrm("mmx_group0f71", modm);
}
}
}
-static void MMXOP(group_0f72)(i386_state *cpustate) // Opcode 0f 72
+void i386_device::mmx_group_0f72() // Opcode 0f 72
{
- UINT8 modm = FETCH(cpustate);
- UINT8 imm8 = FETCH(cpustate);
- MMXPROLOG(cpustate);
+ UINT8 modm = FETCH();
+ UINT8 imm8 = FETCH();
+ MMXPROLOG();
if( modm >= 0xc0 ) {
switch ( (modm & 0x38) >> 3 )
{
@@ -1253,16 +1253,16 @@ static void MMXOP(group_0f72)(i386_state *cpustate) // Opcode 0f 72
MMX(modm & 7).d[1]=MMX(modm & 7).d[1] << imm8;
break;
default:
- report_invalid_modrm(cpustate, "mmx_group0f72", modm);
+ report_invalid_modrm("mmx_group0f72", modm);
}
}
}
-static void MMXOP(group_0f73)(i386_state *cpustate) // Opcode 0f 73
+void i386_device::mmx_group_0f73() // Opcode 0f 73
{
- UINT8 modm = FETCH(cpustate);
- UINT8 imm8 = FETCH(cpustate);
- MMXPROLOG(cpustate);
+ UINT8 modm = FETCH();
+ UINT8 imm8 = FETCH();
+ MMXPROLOG();
if( modm >= 0xc0 ) {
switch ( (modm & 0x38) >> 3 )
{
@@ -1273,15 +1273,15 @@ static void MMXOP(group_0f73)(i386_state *cpustate) // Opcode 0f 73
MMX(modm & 7).q=MMX(modm & 7).q << imm8;
break;
default:
- report_invalid_modrm(cpustate, "mmx_group0f73", modm);
+ report_invalid_modrm("mmx_group0f73", modm);
}
}
}
-static void MMXOP(psrlw_r64_rm64)(i386_state *cpustate) // Opcode 0f d1
+void i386_device::mmx_psrlw_r64_rm64() // Opcode 0f d1
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int count=(int)MMX(modrm & 7).q;
MMX((modrm >> 3) & 0x7).w[0]=MMX((modrm >> 3) & 0x7).w[0] >> count;
@@ -1290,72 +1290,72 @@ static void MMXOP(psrlw_r64_rm64)(i386_state *cpustate) // Opcode 0f d1
MMX((modrm >> 3) & 0x7).w[3]=MMX((modrm >> 3) & 0x7).w[3] >> count;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
int count=(int)src.q;
MMX((modrm >> 3) & 0x7).w[0]=MMX((modrm >> 3) & 0x7).w[0] >> count;
MMX((modrm >> 3) & 0x7).w[1]=MMX((modrm >> 3) & 0x7).w[1] >> count;
MMX((modrm >> 3) & 0x7).w[2]=MMX((modrm >> 3) & 0x7).w[2] >> count;
MMX((modrm >> 3) & 0x7).w[3]=MMX((modrm >> 3) & 0x7).w[3] >> count;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psrld_r64_rm64)(i386_state *cpustate) // Opcode 0f d2
+void i386_device::mmx_psrld_r64_rm64() // Opcode 0f d2
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int count=(int)MMX(modrm & 7).q;
MMX((modrm >> 3) & 0x7).d[0]=MMX((modrm >> 3) & 0x7).d[0] >> count;
MMX((modrm >> 3) & 0x7).d[1]=MMX((modrm >> 3) & 0x7).d[1] >> count;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
int count=(int)src.q;
MMX((modrm >> 3) & 0x7).d[0]=MMX((modrm >> 3) & 0x7).d[0] >> count;
MMX((modrm >> 3) & 0x7).d[1]=MMX((modrm >> 3) & 0x7).d[1] >> count;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psrlq_r64_rm64)(i386_state *cpustate) // Opcode 0f d3
+void i386_device::mmx_psrlq_r64_rm64() // Opcode 0f d3
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int count=(int)MMX(modrm & 7).q;
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q >> count;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
int count=(int)src.q;
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q >> count;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(paddq_r64_rm64)(i386_state *cpustate) // Opcode 0f d4
+void i386_device::mmx_paddq_r64_rm64() // Opcode 0f d4
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q+MMX(modrm & 7).q;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q+src.q;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pmullw_r64_rm64)(i386_state *cpustate) // Opcode 0f d5
+void i386_device::mmx_pmullw_r64_rm64() // Opcode 0f d5
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).w[0]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[0]*(INT32)MMX(modrm & 7).s[0]) & 0xffff;
MMX((modrm >> 3) & 0x7).w[1]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)MMX(modrm & 7).s[1]) & 0xffff;
@@ -1363,122 +1363,122 @@ static void MMXOP(pmullw_r64_rm64)(i386_state *cpustate) // Opcode 0f d5
MMX((modrm >> 3) & 0x7).w[3]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)MMX(modrm & 7).s[3]) & 0xffff;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
MMX((modrm >> 3) & 0x7).w[0]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[0]*(INT32)src.s[0]) & 0xffff;
MMX((modrm >> 3) & 0x7).w[1]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)src.s[1]) & 0xffff;
MMX((modrm >> 3) & 0x7).w[2]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[2]*(INT32)src.s[2]) & 0xffff;
MMX((modrm >> 3) & 0x7).w[3]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)src.s[3]) & 0xffff;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psubusb_r64_rm64)(i386_state *cpustate) // Opcode 0f d8
+void i386_device::mmx_psubusb_r64_rm64() // Opcode 0f d8
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n]=MMX((modrm >> 3) & 0x7).b[n] < MMX(modrm & 7).b[n] ? 0 : MMX((modrm >> 3) & 0x7).b[n]-MMX(modrm & 7).b[n];
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n]=MMX((modrm >> 3) & 0x7).b[n] < src.b[n] ? 0 : MMX((modrm >> 3) & 0x7).b[n]-src.b[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psubusw_r64_rm64)(i386_state *cpustate) // Opcode 0f d9
+void i386_device::mmx_psubusw_r64_rm64() // Opcode 0f d9
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n]=MMX((modrm >> 3) & 0x7).w[n] < MMX(modrm & 7).w[n] ? 0 : MMX((modrm >> 3) & 0x7).w[n]-MMX(modrm & 7).w[n];
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n]=MMX((modrm >> 3) & 0x7).w[n] < src.w[n] ? 0 : MMX((modrm >> 3) & 0x7).w[n]-src.w[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pand_r64_rm64)(i386_state *cpustate) // Opcode 0f db
+void i386_device::mmx_pand_r64_rm64() // Opcode 0f db
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q & MMX(modrm & 7).q;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q & src.q;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(paddusb_r64_rm64)(i386_state *cpustate) // Opcode 0f dc
+void i386_device::mmx_paddusb_r64_rm64() // Opcode 0f dc
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n]=MMX((modrm >> 3) & 0x7).b[n] > (0xff-MMX(modrm & 7).b[n]) ? 0xff : MMX((modrm >> 3) & 0x7).b[n]+MMX(modrm & 7).b[n];
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n]=MMX((modrm >> 3) & 0x7).b[n] > (0xff-src.b[n]) ? 0xff : MMX((modrm >> 3) & 0x7).b[n]+src.b[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(paddusw_r64_rm64)(i386_state *cpustate) // Opcode 0f dd
+void i386_device::mmx_paddusw_r64_rm64() // Opcode 0f dd
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n]=MMX((modrm >> 3) & 0x7).w[n] > (0xffff-MMX(modrm & 7).w[n]) ? 0xffff : MMX((modrm >> 3) & 0x7).w[n]+MMX(modrm & 7).w[n];
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n]=MMX((modrm >> 3) & 0x7).w[n] > (0xffff-src.w[n]) ? 0xffff : MMX((modrm >> 3) & 0x7).w[n]+src.w[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pandn_r64_rm64)(i386_state *cpustate) // Opcode 0f df
+void i386_device::mmx_pandn_r64_rm64() // Opcode 0f df
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).q=(~MMX((modrm >> 3) & 0x7).q) & MMX(modrm & 7).q;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
MMX((modrm >> 3) & 0x7).q=(~MMX((modrm >> 3) & 0x7).q) & src.q;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psraw_r64_rm64)(i386_state *cpustate) // Opcode 0f e1
+void i386_device::mmx_psraw_r64_rm64() // Opcode 0f e1
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int count=(int)MMX(modrm & 7).q;
MMX((modrm >> 3) & 0x7).s[0]=MMX((modrm >> 3) & 0x7).s[0] >> count;
@@ -1487,40 +1487,40 @@ static void MMXOP(psraw_r64_rm64)(i386_state *cpustate) // Opcode 0f e1
MMX((modrm >> 3) & 0x7).s[3]=MMX((modrm >> 3) & 0x7).s[3] >> count;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
int count=(int)src.q;
MMX((modrm >> 3) & 0x7).s[0]=MMX((modrm >> 3) & 0x7).s[0] >> count;
MMX((modrm >> 3) & 0x7).s[1]=MMX((modrm >> 3) & 0x7).s[1] >> count;
MMX((modrm >> 3) & 0x7).s[2]=MMX((modrm >> 3) & 0x7).s[2] >> count;
MMX((modrm >> 3) & 0x7).s[3]=MMX((modrm >> 3) & 0x7).s[3] >> count;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psrad_r64_rm64)(i386_state *cpustate) // Opcode 0f e2
+void i386_device::mmx_psrad_r64_rm64() // Opcode 0f e2
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int count=(int)MMX(modrm & 7).q;
MMX((modrm >> 3) & 0x7).i[0]=MMX((modrm >> 3) & 0x7).i[0] >> count;
MMX((modrm >> 3) & 0x7).i[1]=MMX((modrm >> 3) & 0x7).i[1] >> count;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
int count=(int)src.q;
MMX((modrm >> 3) & 0x7).i[0]=MMX((modrm >> 3) & 0x7).i[0] >> count;
MMX((modrm >> 3) & 0x7).i[1]=MMX((modrm >> 3) & 0x7).i[1] >> count;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pmulhw_r64_rm64)(i386_state *cpustate) // Opcode 0f e5
+void i386_device::mmx_pmulhw_r64_rm64() // Opcode 0f e5
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).w[0]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[0]*(INT32)MMX(modrm & 7).s[0]) >> 16;
MMX((modrm >> 3) & 0x7).w[1]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)MMX(modrm & 7).s[1]) >> 16;
@@ -1528,122 +1528,122 @@ static void MMXOP(pmulhw_r64_rm64)(i386_state *cpustate) // Opcode 0f e5
MMX((modrm >> 3) & 0x7).w[3]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)MMX(modrm & 7).s[3]) >> 16;
} else {
MMX_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, src);
MMX((modrm >> 3) & 0x7).w[0]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[0]*(INT32)src.s[0]) >> 16;
MMX((modrm >> 3) & 0x7).w[1]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)src.s[1]) >> 16;
MMX((modrm >> 3) & 0x7).w[2]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[2]*(INT32)src.s[2]) >> 16;
MMX((modrm >> 3) & 0x7).w[3]=(UINT32)((INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)src.s[3]) >> 16;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psubsb_r64_rm64)(i386_state *cpustate) // Opcode 0f e8
+void i386_device::mmx_psubsb_r64_rm64() // Opcode 0f e8
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).c[n]=SaturatedSignedWordToSignedByte((INT16)MMX((modrm >> 3) & 0x7).c[n] - (INT16)MMX(modrm & 7).c[n]);
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).c[n]=SaturatedSignedWordToSignedByte((INT16)MMX((modrm >> 3) & 0x7).c[n] - (INT16)s.c[n]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psubsw_r64_rm64)(i386_state *cpustate) // Opcode 0f e9
+void i386_device::mmx_psubsw_r64_rm64() // Opcode 0f e9
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).s[n]=SaturatedSignedDwordToSignedWord((INT32)MMX((modrm >> 3) & 0x7).s[n] - (INT32)MMX(modrm & 7).s[n]);
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).s[n]=SaturatedSignedDwordToSignedWord((INT32)MMX((modrm >> 3) & 0x7).s[n] - (INT32)s.s[n]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(por_r64_rm64)(i386_state *cpustate) // Opcode 0f eb
+void i386_device::mmx_por_r64_rm64() // Opcode 0f eb
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q | MMX(modrm & 7).q;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q | s.q;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(paddsb_r64_rm64)(i386_state *cpustate) // Opcode 0f ec
+void i386_device::mmx_paddsb_r64_rm64() // Opcode 0f ec
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).c[n]=SaturatedSignedWordToSignedByte((INT16)MMX((modrm >> 3) & 0x7).c[n] + (INT16)MMX(modrm & 7).c[n]);
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).c[n]=SaturatedSignedWordToSignedByte((INT16)MMX((modrm >> 3) & 0x7).c[n] + (INT16)s.c[n]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(paddsw_r64_rm64)(i386_state *cpustate) // Opcode 0f ed
+void i386_device::mmx_paddsw_r64_rm64() // Opcode 0f ed
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).s[n]=SaturatedSignedDwordToSignedWord((INT32)MMX((modrm >> 3) & 0x7).s[n] + (INT32)MMX(modrm & 7).s[n]);
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).s[n]=SaturatedSignedDwordToSignedWord((INT32)MMX((modrm >> 3) & 0x7).s[n] + (INT32)s.s[n]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pxor_r64_rm64)(i386_state *cpustate) // Opcode 0f ef
+void i386_device::mmx_pxor_r64_rm64() // Opcode 0f ef
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q ^ MMX(modrm & 7).q;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q ^ s.q;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psllw_r64_rm64)(i386_state *cpustate) // Opcode 0f f1
+void i386_device::mmx_psllw_r64_rm64() // Opcode 0f f1
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int count=(int)MMX(modrm & 7).q;
MMX((modrm >> 3) & 0x7).w[0]=MMX((modrm >> 3) & 0x7).w[0] << count;
@@ -1652,57 +1652,57 @@ static void MMXOP(psllw_r64_rm64)(i386_state *cpustate) // Opcode 0f f1
MMX((modrm >> 3) & 0x7).w[3]=MMX((modrm >> 3) & 0x7).w[3] << count;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
int count=(int)s.q;
MMX((modrm >> 3) & 0x7).w[0]=MMX((modrm >> 3) & 0x7).w[0] << count;
MMX((modrm >> 3) & 0x7).w[1]=MMX((modrm >> 3) & 0x7).w[1] << count;
MMX((modrm >> 3) & 0x7).w[2]=MMX((modrm >> 3) & 0x7).w[2] << count;
MMX((modrm >> 3) & 0x7).w[3]=MMX((modrm >> 3) & 0x7).w[3] << count;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pslld_r64_rm64)(i386_state *cpustate) // Opcode 0f f2
+void i386_device::mmx_pslld_r64_rm64() // Opcode 0f f2
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int count=(int)MMX(modrm & 7).q;
MMX((modrm >> 3) & 0x7).d[0]=MMX((modrm >> 3) & 0x7).d[0] << count;
MMX((modrm >> 3) & 0x7).d[1]=MMX((modrm >> 3) & 0x7).d[1] << count;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
int count=(int)s.q;
MMX((modrm >> 3) & 0x7).d[0]=MMX((modrm >> 3) & 0x7).d[0] << count;
MMX((modrm >> 3) & 0x7).d[1]=MMX((modrm >> 3) & 0x7).d[1] << count;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psllq_r64_rm64)(i386_state *cpustate) // Opcode 0f f3
+void i386_device::mmx_psllq_r64_rm64() // Opcode 0f f3
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int count=(int)MMX(modrm & 7).q;
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q << count;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
int count=(int)s.q;
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q << count;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pmaddwd_r64_rm64)(i386_state *cpustate) // Opcode 0f f5
+void i386_device::mmx_pmaddwd_r64_rm64() // Opcode 0f f5
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).i[0]=(INT32)MMX((modrm >> 3) & 0x7).s[0]*(INT32)MMX(modrm & 7).s[0]+
(INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)MMX(modrm & 7).s[1];
@@ -1710,189 +1710,189 @@ static void MMXOP(pmaddwd_r64_rm64)(i386_state *cpustate) // Opcode 0f f5
(INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)MMX(modrm & 7).s[3];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX((modrm >> 3) & 0x7).i[0]=(INT32)MMX((modrm >> 3) & 0x7).s[0]*(INT32)s.s[0]+
(INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)s.s[1];
MMX((modrm >> 3) & 0x7).i[1]=(INT32)MMX((modrm >> 3) & 0x7).s[2]*(INT32)s.s[2]+
(INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)s.s[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psubb_r64_rm64)(i386_state *cpustate) // Opcode 0f f8
+void i386_device::mmx_psubb_r64_rm64() // Opcode 0f f8
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n]=MMX((modrm >> 3) & 0x7).b[n] - MMX(modrm & 7).b[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n]=MMX((modrm >> 3) & 0x7).b[n] - s.b[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psubw_r64_rm64)(i386_state *cpustate) // Opcode 0f f9
+void i386_device::mmx_psubw_r64_rm64() // Opcode 0f f9
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n]=MMX((modrm >> 3) & 0x7).w[n] - MMX(modrm & 7).w[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n]=MMX((modrm >> 3) & 0x7).w[n] - s.w[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(psubd_r64_rm64)(i386_state *cpustate) // Opcode 0f fa
+void i386_device::mmx_psubd_r64_rm64() // Opcode 0f fa
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 2;n++)
MMX((modrm >> 3) & 0x7).d[n]=MMX((modrm >> 3) & 0x7).d[n] - MMX(modrm & 7).d[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 2;n++)
MMX((modrm >> 3) & 0x7).d[n]=MMX((modrm >> 3) & 0x7).d[n] - s.d[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(paddb_r64_rm64)(i386_state *cpustate) // Opcode 0f fc
+void i386_device::mmx_paddb_r64_rm64() // Opcode 0f fc
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n]=MMX((modrm >> 3) & 0x7).b[n] + MMX(modrm & 7).b[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n]=MMX((modrm >> 3) & 0x7).b[n] + s.b[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(paddw_r64_rm64)(i386_state *cpustate) // Opcode 0f fd
+void i386_device::mmx_paddw_r64_rm64() // Opcode 0f fd
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n]=MMX((modrm >> 3) & 0x7).w[n] + MMX(modrm & 7).w[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n]=MMX((modrm >> 3) & 0x7).w[n] + s.w[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(paddd_r64_rm64)(i386_state *cpustate) // Opcode 0f fe
+void i386_device::mmx_paddd_r64_rm64() // Opcode 0f fe
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 2;n++)
MMX((modrm >> 3) & 0x7).d[n]=MMX((modrm >> 3) & 0x7).d[n] + MMX(modrm & 7).d[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 2;n++)
MMX((modrm >> 3) & 0x7).d[n]=MMX((modrm >> 3) & 0x7).d[n] + s.d[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(emms)(i386_state *cpustate) // Opcode 0f 77
+void i386_device::mmx_emms() // Opcode 0f 77
{
- cpustate->x87_tw = 0xffff; // tag word = 0xffff
+ m_x87_tw = 0xffff; // tag word = 0xffff
// TODO
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(movd_r64_rm32)(i386_state *cpustate) // Opcode 0f 6e
+void i386_device::mmx_movd_r64_rm32() // Opcode 0f 6e
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).d[0]=LOAD_RM32(modrm);
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- MMX((modrm >> 3) & 0x7).d[0]=READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ MMX((modrm >> 3) & 0x7).d[0]=READ32(ea);
}
MMX((modrm >> 3) & 0x7).d[1]=0;
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(movq_r64_rm64)(i386_state *cpustate) // Opcode 0f 6f
+void i386_device::mmx_movq_r64_rm64() // Opcode 0f 6f
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).l=MMX(modrm & 0x7).l;
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, MMX((modrm >> 3) & 0x7));
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, MMX((modrm >> 3) & 0x7));
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(movd_rm32_r64)(i386_state *cpustate) // Opcode 0f 7e
+void i386_device::mmx_movd_rm32_r64() // Opcode 0f 7e
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
STORE_RM32(modrm, MMX((modrm >> 3) & 0x7).d[0]);
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITE32(cpustate, ea, MMX((modrm >> 3) & 0x7).d[0]);
+ UINT32 ea = GetEA(modrm, 0);
+ WRITE32(ea, MMX((modrm >> 3) & 0x7).d[0]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(movq_rm64_r64)(i386_state *cpustate) // Opcode 0f 7f
+void i386_device::mmx_movq_rm64_r64() // Opcode 0f 7f
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX(modrm & 0x7)=MMX((modrm >> 3) & 0x7);
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITEMMX(cpustate, ea, MMX((modrm >> 3) & 0x7));
+ UINT32 ea = GetEA(modrm, 0);
+ WRITEMMX(ea, MMX((modrm >> 3) & 0x7));
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pcmpeqb_r64_rm64)(i386_state *cpustate) // Opcode 0f 74
+void i386_device::mmx_pcmpeqb_r64_rm64() // Opcode 0f 74
{
int c;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -1902,18 +1902,18 @@ static void MMXOP(pcmpeqb_r64_rm64)(i386_state *cpustate) // Opcode 0f 74
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (c=0;c <= 7;c++)
MMX(d).b[c]=(MMX(d).b[c] == s.b[c]) ? 0xff : 0;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pcmpeqw_r64_rm64)(i386_state *cpustate) // Opcode 0f 75
+void i386_device::mmx_pcmpeqw_r64_rm64() // Opcode 0f 75
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -1925,20 +1925,20 @@ static void MMXOP(pcmpeqw_r64_rm64)(i386_state *cpustate) // Opcode 0f 75
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX(d).w[0]=(MMX(d).w[0] == s.w[0]) ? 0xffff : 0;
MMX(d).w[1]=(MMX(d).w[1] == s.w[1]) ? 0xffff : 0;
MMX(d).w[2]=(MMX(d).w[2] == s.w[2]) ? 0xffff : 0;
MMX(d).w[3]=(MMX(d).w[3] == s.w[3]) ? 0xffff : 0;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pcmpeqd_r64_rm64)(i386_state *cpustate) // Opcode 0f 76
+void i386_device::mmx_pcmpeqd_r64_rm64() // Opcode 0f 76
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -1948,22 +1948,22 @@ static void MMXOP(pcmpeqd_r64_rm64)(i386_state *cpustate) // Opcode 0f 76
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX(d).d[0]=(MMX(d).d[0] == s.d[0]) ? 0xffffffff : 0;
MMX(d).d[1]=(MMX(d).d[1] == s.d[1]) ? 0xffffffff : 0;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pshufw_r64_rm64_i8)(i386_state *cpustate) // Opcode 0f 70
+void i386_device::mmx_pshufw_r64_rm64_i8() // Opcode 0f 70
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX_REG t;
int s,d;
- UINT8 imm8 = FETCH(cpustate);
+ UINT8 imm8 = FETCH();
s=modrm & 0x7;
d=(modrm >> 3) & 0x7;
t.q=MMX(s).q;
@@ -1974,21 +1974,21 @@ static void MMXOP(pshufw_r64_rm64_i8)(i386_state *cpustate) // Opcode 0f 70
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- UINT8 imm8 = FETCH(cpustate);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ UINT8 imm8 = FETCH();
+ READMMX(ea, s);
MMX(d).w[0]=s.w[imm8 & 3];
MMX(d).w[1]=s.w[(imm8 >> 2) & 3];
MMX(d).w[2]=s.w[(imm8 >> 4) & 3];
MMX(d).w[3]=s.w[(imm8 >> 6) & 3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(punpcklbw_r64_r64m32)(i386_state *cpustate) // Opcode 0f 60
+void i386_device::mmx_punpcklbw_r64_r64m32() // Opcode 0f 60
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 t;
int s,d;
@@ -2006,8 +2006,8 @@ static void MMXOP(punpcklbw_r64_r64m32)(i386_state *cpustate) // Opcode 0f 60
} else {
UINT32 s,t;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- s = READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ s = READ32(ea);
t=MMX(d).d[0];
MMX(d).b[0]=t & 0xff;
MMX(d).b[1]=s & 0xff;
@@ -2018,13 +2018,13 @@ static void MMXOP(punpcklbw_r64_r64m32)(i386_state *cpustate) // Opcode 0f 60
MMX(d).b[6]=(t >> 24) & 0xff;
MMX(d).b[7]=(s >> 24) & 0xff;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(punpcklwd_r64_r64m32)(i386_state *cpustate) // Opcode 0f 61
+void i386_device::mmx_punpcklwd_r64_r64m32() // Opcode 0f 61
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT16 t;
int s,d;
@@ -2039,21 +2039,21 @@ static void MMXOP(punpcklwd_r64_r64m32)(i386_state *cpustate) // Opcode 0f 61
UINT32 s;
UINT16 t;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- s = READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ s = READ32(ea);
t=MMX(d).w[1];
MMX(d).w[0]=MMX(d).w[0];
MMX(d).w[1]=s & 0xffff;
MMX(d).w[2]=t;
MMX(d).w[3]=(s >> 16) & 0xffff;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(punpckldq_r64_r64m32)(i386_state *cpustate) // Opcode 0f 62
+void i386_device::mmx_punpckldq_r64_r64m32() // Opcode 0f 62
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2063,18 +2063,18 @@ static void MMXOP(punpckldq_r64_r64m32)(i386_state *cpustate) // Opcode 0f 62
} else {
UINT32 s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- s = READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ s = READ32(ea);
MMX(d).d[0]=MMX(d).d[0];
MMX(d).d[1]=s;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(packsswb_r64_rm64)(i386_state *cpustate) // Opcode 0f 63
+void i386_device::mmx_packsswb_r64_rm64() // Opcode 0f 63
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2090,8 +2090,8 @@ static void MMXOP(packsswb_r64_rm64)(i386_state *cpustate) // Opcode 0f 63
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX(d).c[0]=SaturatedSignedWordToSignedByte(MMX(d).s[0]);
MMX(d).c[1]=SaturatedSignedWordToSignedByte(MMX(d).s[1]);
MMX(d).c[2]=SaturatedSignedWordToSignedByte(MMX(d).s[2]);
@@ -2101,14 +2101,14 @@ static void MMXOP(packsswb_r64_rm64)(i386_state *cpustate) // Opcode 0f 63
MMX(d).c[6]=SaturatedSignedWordToSignedByte(s.s[2]);
MMX(d).c[7]=SaturatedSignedWordToSignedByte(s.s[3]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pcmpgtb_r64_rm64)(i386_state *cpustate) // Opcode 0f 64
+void i386_device::mmx_pcmpgtb_r64_rm64() // Opcode 0f 64
{
int c;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2118,19 +2118,19 @@ static void MMXOP(pcmpgtb_r64_rm64)(i386_state *cpustate) // Opcode 0f 64
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (c=0;c <= 7;c++)
MMX(d).b[c]=(MMX(d).c[c] > s.c[c]) ? 0xff : 0;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pcmpgtw_r64_rm64)(i386_state *cpustate) // Opcode 0f 65
+void i386_device::mmx_pcmpgtw_r64_rm64() // Opcode 0f 65
{
int c;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2140,19 +2140,19 @@ static void MMXOP(pcmpgtw_r64_rm64)(i386_state *cpustate) // Opcode 0f 65
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (c=0;c <= 3;c++)
MMX(d).w[c]=(MMX(d).s[c] > s.s[c]) ? 0xffff : 0;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(pcmpgtd_r64_rm64)(i386_state *cpustate) // Opcode 0f 66
+void i386_device::mmx_pcmpgtd_r64_rm64() // Opcode 0f 66
{
int c;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2162,18 +2162,18 @@ static void MMXOP(pcmpgtd_r64_rm64)(i386_state *cpustate) // Opcode 0f 66
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (c=0;c <= 1;c++)
MMX(d).d[c]=(MMX(d).i[c] > s.i[c]) ? 0xffffffff : 0;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(packuswb_r64_rm64)(i386_state *cpustate) // Opcode 0f 67
+void i386_device::mmx_packuswb_r64_rm64() // Opcode 0f 67
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2189,8 +2189,8 @@ static void MMXOP(packuswb_r64_rm64)(i386_state *cpustate) // Opcode 0f 67
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX(d).b[0]=SaturatedSignedWordToUnsignedByte(MMX(d).s[0]);
MMX(d).b[1]=SaturatedSignedWordToUnsignedByte(MMX(d).s[1]);
MMX(d).b[2]=SaturatedSignedWordToUnsignedByte(MMX(d).s[2]);
@@ -2200,13 +2200,13 @@ static void MMXOP(packuswb_r64_rm64)(i386_state *cpustate) // Opcode 0f 67
MMX(d).b[6]=SaturatedSignedWordToUnsignedByte(s.s[2]);
MMX(d).b[7]=SaturatedSignedWordToUnsignedByte(s.s[3]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(punpckhbw_r64_rm64)(i386_state *cpustate) // Opcode 0f 68
+void i386_device::mmx_punpckhbw_r64_rm64() // Opcode 0f 68
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2222,8 +2222,8 @@ static void MMXOP(punpckhbw_r64_rm64)(i386_state *cpustate) // Opcode 0f 68
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX(d).b[0]=MMX(d).b[4];
MMX(d).b[1]=s.b[4];
MMX(d).b[2]=MMX(d).b[5];
@@ -2233,13 +2233,13 @@ static void MMXOP(punpckhbw_r64_rm64)(i386_state *cpustate) // Opcode 0f 68
MMX(d).b[6]=MMX(d).b[7];
MMX(d).b[7]=s.b[7];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(punpckhwd_r64_rm64)(i386_state *cpustate) // Opcode 0f 69
+void i386_device::mmx_punpckhwd_r64_rm64() // Opcode 0f 69
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2251,20 +2251,20 @@ static void MMXOP(punpckhwd_r64_rm64)(i386_state *cpustate) // Opcode 0f 69
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX(d).w[0]=MMX(d).w[2];
MMX(d).w[1]=s.w[2];
MMX(d).w[2]=MMX(d).w[3];
MMX(d).w[3]=s.w[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(punpckhdq_r64_rm64)(i386_state *cpustate) // Opcode 0f 6a
+void i386_device::mmx_punpckhdq_r64_rm64() // Opcode 0f 6a
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2274,18 +2274,18 @@ static void MMXOP(punpckhdq_r64_rm64)(i386_state *cpustate) // Opcode 0f 6a
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX(d).d[0]=MMX(d).d[1];
MMX(d).d[1]=s.d[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void MMXOP(packssdw_r64_rm64)(i386_state *cpustate) // Opcode 0f 6b
+void i386_device::mmx_packssdw_r64_rm64() // Opcode 0f 6b
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
s=modrm & 0x7;
@@ -2297,52 +2297,52 @@ static void MMXOP(packssdw_r64_rm64)(i386_state *cpustate) // Opcode 0f 6b
} else {
MMX_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX(d).s[0]=SaturatedSignedDwordToSignedWord(MMX(d).i[0]);
MMX(d).s[1]=SaturatedSignedDwordToSignedWord(MMX(d).i[1]);
MMX(d).s[2]=SaturatedSignedDwordToSignedWord(s.i[0]);
MMX(d).s[3]=SaturatedSignedDwordToSignedWord(s.i[1]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(sse_group0fae)(i386_state *cpustate) // Opcode 0f ae
+void i386_device::sse_sse_group0fae() // Opcode 0f ae
{
- UINT8 modm = FETCH(cpustate);
+ UINT8 modm = FETCH();
if( modm == 0xf8 ) {
logerror("Unemulated SFENCE opcode called\n");
- CYCLES(cpustate,1); // sfence instruction
+ CYCLES(1); // sfence instruction
} else if( modm == 0xf0 ) {
- CYCLES(cpustate,1); // mfence instruction
+ CYCLES(1); // mfence instruction
} else if( modm == 0xe8 ) {
- CYCLES(cpustate,1); // lfence instruction
+ CYCLES(1); // lfence instruction
} else if( modm < 0xc0 ) {
UINT32 ea;
switch ( (modm & 0x38) >> 3 )
{
case 2: // ldmxcsr m32
- ea = GetEA(cpustate, modm, 0);
- cpustate->mxcsr = READ32(cpustate, ea);
+ ea = GetEA(modm, 0);
+ m_mxcsr = READ32(ea);
break;
case 3: // stmxcsr m32
- ea = GetEA(cpustate, modm, 0);
- WRITE32(cpustate, ea, cpustate->mxcsr);
+ ea = GetEA(modm, 0);
+ WRITE32(ea, m_mxcsr);
break;
case 7: // clflush m8
- GetNonTranslatedEA(cpustate, modm, NULL);
+ GetNonTranslatedEA(modm, NULL);
break;
default:
- report_invalid_modrm(cpustate, "sse_group0fae", modm);
+ report_invalid_modrm("sse_group0fae", modm);
}
} else {
- report_invalid_modrm(cpustate, "sse_group0fae", modm);
+ report_invalid_modrm("sse_group0fae", modm);
}
}
-static void SSEOP(cvttps2dq_r128_rm128)(i386_state *cpustate) // Opcode f3 0f 5b
+void i386_device::sse_cvttps2dq_r128_rm128() // Opcode f3 0f 5b
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).i[0]=(INT32)XMM(modrm & 0x7).f[0];
XMM((modrm >> 3) & 0x7).i[1]=(INT32)XMM(modrm & 0x7).f[1];
@@ -2350,144 +2350,144 @@ static void SSEOP(cvttps2dq_r128_rm128)(i386_state *cpustate) // Opcode f3 0f 5b
XMM((modrm >> 3) & 0x7).i[3]=(INT32)XMM(modrm & 0x7).f[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).i[0]=(INT32)src.f[0];
XMM((modrm >> 3) & 0x7).i[1]=(INT32)src.f[1];
XMM((modrm >> 3) & 0x7).i[2]=(INT32)src.f[2];
XMM((modrm >> 3) & 0x7).i[3]=(INT32)src.f[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvtss2sd_r128_r128m32)(i386_state *cpustate) // Opcode f3 0f 5a
+void i386_device::sse_cvtss2sd_r128_r128m32() // Opcode f3 0f 5a
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f64[0] = XMM(modrm & 0x7).f[0];
} else {
XMM_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- s.d[0] = READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ s.d[0] = READ32(ea);
XMM((modrm >> 3) & 0x7).f64[0] = s.f[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvttss2si_r32_r128m32)(i386_state *cpustate) // Opcode f3 0f 2c
+void i386_device::sse_cvttss2si_r32_r128m32() // Opcode f3 0f 2c
{
INT32 src;
- UINT8 modrm = FETCH(cpustate); // get mordm byte
+ UINT8 modrm = FETCH(); // get mordm byte
if( modrm >= 0xc0 ) { // if bits 7-6 are 11 the source is a xmm register (low doubleword)
src = (INT32)XMM(modrm & 0x7).f[0^NATIVE_ENDIAN_VALUE_LE_BE(0,1)];
} else { // otherwise is a memory address
XMM_REG t;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- t.d[0] = READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ t.d[0] = READ32(ea);
src = (INT32)t.f[0];
}
STORE_REG32(modrm, (UINT32)src);
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvtss2si_r32_r128m32)(i386_state *cpustate) // Opcode f3 0f 2d
+void i386_device::sse_cvtss2si_r32_r128m32() // Opcode f3 0f 2d
{
INT32 src;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
src = (INT32)XMM(modrm & 0x7).f[0];
} else {
XMM_REG t;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- t.d[0] = READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ t.d[0] = READ32(ea);
src = (INT32)t.f[0];
}
STORE_REG32(modrm, (UINT32)src);
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvtsi2ss_r128_rm32)(i386_state *cpustate) // Opcode f3 0f 2a
+void i386_device::sse_cvtsi2ss_r128_rm32() // Opcode f3 0f 2a
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = (INT32)LOAD_RM32(modrm);
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- XMM((modrm >> 3) & 0x7).f[0] = (INT32)READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ XMM((modrm >> 3) & 0x7).f[0] = (INT32)READ32(ea);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvtpi2ps_r128_rm64)(i386_state *cpustate) // Opcode 0f 2a
+void i386_device::sse_cvtpi2ps_r128_rm64() // Opcode 0f 2a
{
- UINT8 modrm = FETCH(cpustate);
- MMXPROLOG(cpustate);
+ UINT8 modrm = FETCH();
+ MMXPROLOG();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = MMX(modrm & 0x7).i[0];
XMM((modrm >> 3) & 0x7).f[1] = MMX(modrm & 0x7).i[1];
} else {
MMX_REG r;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, r);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, r);
XMM((modrm >> 3) & 0x7).f[0] = r.i[0];
XMM((modrm >> 3) & 0x7).f[1] = r.i[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvttps2pi_r64_r128m64)(i386_state *cpustate) // Opcode 0f 2c
+void i386_device::sse_cvttps2pi_r64_r128m64() // Opcode 0f 2c
{
- UINT8 modrm = FETCH(cpustate);
- MMXPROLOG(cpustate);
+ UINT8 modrm = FETCH();
+ MMXPROLOG();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).i[0] = XMM(modrm & 0x7).f[0];
MMX((modrm >> 3) & 0x7).i[1] = XMM(modrm & 0x7).f[1];
} else {
XMM_REG r;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, r);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, r);
XMM((modrm >> 3) & 0x7).i[0] = r.f[0];
XMM((modrm >> 3) & 0x7).i[1] = r.f[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvtps2pi_r64_r128m64)(i386_state *cpustate) // Opcode 0f 2d
+void i386_device::sse_cvtps2pi_r64_r128m64() // Opcode 0f 2d
{
- UINT8 modrm = FETCH(cpustate);
- MMXPROLOG(cpustate);
+ UINT8 modrm = FETCH();
+ MMXPROLOG();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).i[0] = XMM(modrm & 0x7).f[0];
MMX((modrm >> 3) & 0x7).i[1] = XMM(modrm & 0x7).f[1];
} else {
XMM_REG r;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, r);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, r);
XMM((modrm >> 3) & 0x7).i[0] = r.f[0];
XMM((modrm >> 3) & 0x7).i[1] = r.f[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvtps2pd_r128_r128m64)(i386_state *cpustate) // Opcode 0f 5a
+void i386_device::sse_cvtps2pd_r128_r128m64() // Opcode 0f 5a
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f64[0] = (double)XMM(modrm & 0x7).f[0];
XMM((modrm >> 3) & 0x7).f64[1] = (double)XMM(modrm & 0x7).f[1];
} else {
MMX_REG r;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, r);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, r);
XMM((modrm >> 3) & 0x7).f64[0] = (double)r.f[0];
XMM((modrm >> 3) & 0x7).f64[1] = (double)r.f[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvtdq2ps_r128_rm128)(i386_state *cpustate) // Opcode 0f 5b
+void i386_device::sse_cvtdq2ps_r128_rm128() // Opcode 0f 5b
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = (float)XMM(modrm & 0x7).i[0];
XMM((modrm >> 3) & 0x7).f[1] = (float)XMM(modrm & 0x7).i[1];
@@ -2495,59 +2495,59 @@ static void SSEOP(cvtdq2ps_r128_rm128)(i386_state *cpustate) // Opcode 0f 5b
XMM((modrm >> 3) & 0x7).f[3] = (float)XMM(modrm & 0x7).i[3];
} else {
XMM_REG r;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, r);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, r);
XMM((modrm >> 3) & 0x7).f[0] = (float)r.i[0];
XMM((modrm >> 3) & 0x7).f[1] = (float)r.i[1];
XMM((modrm >> 3) & 0x7).f[2] = (float)r.i[2];
XMM((modrm >> 3) & 0x7).f[3] = (float)r.i[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cvtdq2pd_r128_r128m64)(i386_state *cpustate) // Opcode f3 0f e6
+void i386_device::sse_cvtdq2pd_r128_r128m64() // Opcode f3 0f e6
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f64[0] = (double)XMM(modrm & 0x7).i[0];
XMM((modrm >> 3) & 0x7).f64[1] = (double)XMM(modrm & 0x7).i[1];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
XMM((modrm >> 3) & 0x7).f64[0] = (double)s.i[0];
XMM((modrm >> 3) & 0x7).f64[1] = (double)s.i[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movss_r128_rm128)(i386_state *cpustate) // Opcode f3 0f 10
+void i386_device::sse_movss_r128_rm128() // Opcode f3 0f 10
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).d[0] = XMM(modrm & 0x7).d[0];
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- XMM((modrm >> 3) & 0x7).d[0] = READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ XMM((modrm >> 3) & 0x7).d[0] = READ32(ea);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movss_rm128_r128)(i386_state *cpustate) // Opcode f3 0f 11
+void i386_device::sse_movss_rm128_r128() // Opcode f3 0f 11
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM(modrm & 0x7).d[0] = XMM((modrm >> 3) & 0x7).d[0];
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITE32(cpustate, ea, XMM((modrm >> 3) & 0x7).d[0]);
+ UINT32 ea = GetEA(modrm, 0);
+ WRITE32(ea, XMM((modrm >> 3) & 0x7).d[0]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movsldup_r128_rm128)(i386_state *cpustate) // Opcode f3 0f 12
+void i386_device::sse_movsldup_r128_rm128() // Opcode f3 0f 12
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).d[0] = XMM(modrm & 0x7).d[0];
XMM((modrm >> 3) & 0x7).d[1] = XMM(modrm & 0x7).d[0];
@@ -2555,19 +2555,19 @@ static void SSEOP(movsldup_r128_rm128)(i386_state *cpustate) // Opcode f3 0f 12
XMM((modrm >> 3) & 0x7).d[3] = XMM(modrm & 0x7).d[2];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).d[0] = src.d[0];
XMM((modrm >> 3) & 0x7).d[1] = src.d[0];
XMM((modrm >> 3) & 0x7).d[2] = src.d[2];
XMM((modrm >> 3) & 0x7).d[3] = src.d[2];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movshdup_r128_rm128)(i386_state *cpustate) // Opcode f3 0f 16
+void i386_device::sse_movshdup_r128_rm128() // Opcode f3 0f 16
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).d[0] = XMM(modrm & 0x7).d[1];
XMM((modrm >> 3) & 0x7).d[1] = XMM(modrm & 0x7).d[1];
@@ -2575,133 +2575,133 @@ static void SSEOP(movshdup_r128_rm128)(i386_state *cpustate) // Opcode f3 0f 16
XMM((modrm >> 3) & 0x7).d[3] = XMM(modrm & 0x7).d[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).d[0] = src.d[1];
XMM((modrm >> 3) & 0x7).d[1] = src.d[1];
XMM((modrm >> 3) & 0x7).d[2] = src.d[3];
XMM((modrm >> 3) & 0x7).d[3] = src.d[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movaps_r128_rm128)(i386_state *cpustate) // Opcode 0f 28
+void i386_device::sse_movaps_r128_rm128() // Opcode 0f 28
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7) = XMM(modrm & 0x7);
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, XMM((modrm >> 3) & 0x7));
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, XMM((modrm >> 3) & 0x7));
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movaps_rm128_r128)(i386_state *cpustate) // Opcode 0f 29
+void i386_device::sse_movaps_rm128_r128() // Opcode 0f 29
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM(modrm & 0x7) = XMM((modrm >> 3) & 0x7);
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITEXMM(cpustate, ea, XMM((modrm >> 3) & 0x7));
+ UINT32 ea = GetEA(modrm, 0);
+ WRITEXMM(ea, XMM((modrm >> 3) & 0x7));
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movups_r128_rm128)(i386_state *cpustate) // Opcode 0f 10
+void i386_device::sse_movups_r128_rm128() // Opcode 0f 10
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7) = XMM(modrm & 0x7);
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, XMM((modrm >> 3) & 0x7)); // address does not need to be 16-byte aligned
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, XMM((modrm >> 3) & 0x7)); // address does not need to be 16-byte aligned
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movups_rm128_r128)(i386_state *cpustate) // Opcode 0f 11
+void i386_device::sse_movups_rm128_r128() // Opcode 0f 11
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM(modrm & 0x7) = XMM((modrm >> 3) & 0x7);
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITEXMM(cpustate, ea, XMM((modrm >> 3) & 0x7)); // address does not need to be 16-byte aligned
+ UINT32 ea = GetEA(modrm, 0);
+ WRITEXMM(ea, XMM((modrm >> 3) & 0x7)); // address does not need to be 16-byte aligned
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movlps_r128_m64)(i386_state *cpustate) // Opcode 0f 12
+void i386_device::sse_movlps_r128_m64() // Opcode 0f 12
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
// unsupported by cpu
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM_LO64(cpustate, ea, XMM((modrm >> 3) & 0x7));
- CYCLES(cpustate,1); // TODO: correct cycle count
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM_LO64(ea, XMM((modrm >> 3) & 0x7));
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void SSEOP(movlps_m64_r128)(i386_state *cpustate) // Opcode 0f 13
+void i386_device::sse_movlps_m64_r128() // Opcode 0f 13
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
// unsupported by cpu
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITEXMM_LO64(cpustate, ea, XMM((modrm >> 3) & 0x7));
- CYCLES(cpustate,1); // TODO: correct cycle count
+ UINT32 ea = GetEA(modrm, 0);
+ WRITEXMM_LO64(ea, XMM((modrm >> 3) & 0x7));
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void SSEOP(movhps_r128_m64)(i386_state *cpustate) // Opcode 0f 16
+void i386_device::sse_movhps_r128_m64() // Opcode 0f 16
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
// unsupported by cpu
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM_HI64(cpustate, ea, XMM((modrm >> 3) & 0x7));
- CYCLES(cpustate,1); // TODO: correct cycle count
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM_HI64(ea, XMM((modrm >> 3) & 0x7));
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void SSEOP(movhps_m64_r128)(i386_state *cpustate) // Opcode 0f 17
+void i386_device::sse_movhps_m64_r128() // Opcode 0f 17
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
// unsupported by cpu
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITEXMM_HI64(cpustate,ea, XMM((modrm >> 3) & 0x7));
- CYCLES(cpustate,1); // TODO: correct cycle count
+ UINT32 ea = GetEA(modrm, 0);
+ WRITEXMM_HI64(ea, XMM((modrm >> 3) & 0x7));
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void SSEOP(movntps_m128_r128)(i386_state *cpustate) // Opcode 0f 2b
+void i386_device::sse_movntps_m128_r128() // Opcode 0f 2b
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
// unsupported by cpu
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
} else {
// since cache is not implemented
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITEXMM(cpustate, ea, XMM((modrm >> 3) & 0x7));
- CYCLES(cpustate,1); // TODO: correct cycle count
+ UINT32 ea = GetEA(modrm, 0);
+ WRITEXMM(ea, XMM((modrm >> 3) & 0x7));
+ CYCLES(1); // TODO: correct cycle count
}
}
-static void SSEOP(movmskps_r16_r128)(i386_state *cpustate) // Opcode 0f 50
+void i386_device::sse_movmskps_r16_r128() // Opcode 0f 50
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int b;
b=(XMM(modrm & 0x7).d[0] >> 31) & 1;
@@ -2710,12 +2710,12 @@ static void SSEOP(movmskps_r16_r128)(i386_state *cpustate) // Opcode 0f 50
b=b | ((XMM(modrm & 0x7).d[3] >> 28) & 8);
STORE_REG16(modrm, b);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movmskps_r32_r128)(i386_state *cpustate) // Opcode 0f 50
+void i386_device::sse_movmskps_r32_r128() // Opcode 0f 50
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int b;
b=(XMM(modrm & 0x7).d[0] >> 31) & 1;
@@ -2724,67 +2724,67 @@ static void SSEOP(movmskps_r32_r128)(i386_state *cpustate) // Opcode 0f 50
b=b | ((XMM(modrm & 0x7).d[3] >> 28) & 8);
STORE_REG32(modrm, b);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movq2dq_r128_r64)(i386_state *cpustate) // Opcode f3 0f d6
+void i386_device::sse_movq2dq_r128_r64() // Opcode f3 0f d6
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).q[0] = MMX(modrm & 7).q;
XMM((modrm >> 3) & 0x7).q[1] = 0;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movdqu_r128_rm128)(i386_state *cpustate) // Opcode f3 0f 6f
+void i386_device::sse_movdqu_r128_rm128() // Opcode f3 0f 6f
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).q[0] = XMM(modrm & 0x7).q[0];
XMM((modrm >> 3) & 0x7).q[1] = XMM(modrm & 0x7).q[1];
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, XMM((modrm >> 3) & 0x7));
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, XMM((modrm >> 3) & 0x7));
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movdqu_rm128_r128)(i386_state *cpustate) // Opcode f3 0f 7f
+void i386_device::sse_movdqu_rm128_r128() // Opcode f3 0f 7f
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM(modrm & 0x7).q[0] = XMM((modrm >> 3) & 0x7).q[0];
XMM(modrm & 0x7).q[1] = XMM((modrm >> 3) & 0x7).q[1];
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- WRITEXMM(cpustate, ea, XMM((modrm >> 3) & 0x7));
+ UINT32 ea = GetEA(modrm, 0);
+ WRITEXMM(ea, XMM((modrm >> 3) & 0x7));
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(movq_r128_r128m64)(i386_state *cpustate) // Opcode f3 0f 7e
+void i386_device::sse_movq_r128_r128m64() // Opcode f3 0f 7e
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).q[0] = XMM(modrm & 0x7).q[0];
XMM((modrm >> 3) & 0x7).q[1] = 0;
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- XMM((modrm >> 3) & 0x7).q[0] = READ64(cpustate,ea);
+ UINT32 ea = GetEA(modrm, 0);
+ XMM((modrm >> 3) & 0x7).q[0] = READ64(ea);
XMM((modrm >> 3) & 0x7).q[1] = 0;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pmovmskb_r16_r64)(i386_state *cpustate) // Opcode 0f d7
+void i386_device::sse_pmovmskb_r16_r64() // Opcode 0f d7
{
- //MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ //MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int b;
b=(MMX(modrm & 0x7).b[0] >> 7) & 1;
@@ -2797,13 +2797,13 @@ static void SSEOP(pmovmskb_r16_r64)(i386_state *cpustate) // Opcode 0f d7
b=b | ((MMX(modrm & 0x7).b[7] >> 0) & 128);
STORE_REG16(modrm, b);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pmovmskb_r32_r64)(i386_state *cpustate) // Opcode 0f d7
+void i386_device::sse_pmovmskb_r32_r64() // Opcode 0f d7
{
- //MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ //MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int b;
b=(MMX(modrm & 0x7).b[0] >> 7) & 1;
@@ -2816,12 +2816,12 @@ static void SSEOP(pmovmskb_r32_r64)(i386_state *cpustate) // Opcode 0f d7
b=b | ((MMX(modrm & 0x7).b[7] >> 0) & 128);
STORE_REG32(modrm, b);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(xorps)(i386_state *cpustate) // Opcode 0f 57
+void i386_device::sse_xorps() // Opcode 0f 57
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).d[0] = XMM((modrm >> 3) & 0x7).d[0] ^ XMM(modrm & 0x7).d[0];
XMM((modrm >> 3) & 0x7).d[1] = XMM((modrm >> 3) & 0x7).d[1] ^ XMM(modrm & 0x7).d[1];
@@ -2829,19 +2829,19 @@ static void SSEOP(xorps)(i386_state *cpustate) // Opcode 0f 57
XMM((modrm >> 3) & 0x7).d[3] = XMM((modrm >> 3) & 0x7).d[3] ^ XMM(modrm & 0x7).d[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).d[0] = XMM((modrm >> 3) & 0x7).d[0] ^ src.d[0];
XMM((modrm >> 3) & 0x7).d[1] = XMM((modrm >> 3) & 0x7).d[1] ^ src.d[1];
XMM((modrm >> 3) & 0x7).d[2] = XMM((modrm >> 3) & 0x7).d[2] ^ src.d[2];
XMM((modrm >> 3) & 0x7).d[3] = XMM((modrm >> 3) & 0x7).d[3] ^ src.d[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(addps)(i386_state *cpustate) // Opcode 0f 58
+void i386_device::sse_addps() // Opcode 0f 58
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] + XMM(modrm & 0x7).f[0];
XMM((modrm >> 3) & 0x7).f[1] = XMM((modrm >> 3) & 0x7).f[1] + XMM(modrm & 0x7).f[1];
@@ -2849,19 +2849,19 @@ static void SSEOP(addps)(i386_state *cpustate) // Opcode 0f 58
XMM((modrm >> 3) & 0x7).f[3] = XMM((modrm >> 3) & 0x7).f[3] + XMM(modrm & 0x7).f[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] + src.f[0];
XMM((modrm >> 3) & 0x7).f[1] = XMM((modrm >> 3) & 0x7).f[1] + src.f[1];
XMM((modrm >> 3) & 0x7).f[2] = XMM((modrm >> 3) & 0x7).f[2] + src.f[2];
XMM((modrm >> 3) & 0x7).f[3] = XMM((modrm >> 3) & 0x7).f[3] + src.f[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(sqrtps_r128_rm128)(i386_state *cpustate) // Opcode 0f 51
+void i386_device::sse_sqrtps_r128_rm128() // Opcode 0f 51
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = sqrt(XMM(modrm & 0x7).f[0]);
XMM((modrm >> 3) & 0x7).f[1] = sqrt(XMM(modrm & 0x7).f[1]);
@@ -2869,19 +2869,19 @@ static void SSEOP(sqrtps_r128_rm128)(i386_state *cpustate) // Opcode 0f 51
XMM((modrm >> 3) & 0x7).f[3] = sqrt(XMM(modrm & 0x7).f[3]);
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = sqrt(src.f[0]);
XMM((modrm >> 3) & 0x7).f[1] = sqrt(src.f[1]);
XMM((modrm >> 3) & 0x7).f[2] = sqrt(src.f[2]);
XMM((modrm >> 3) & 0x7).f[3] = sqrt(src.f[3]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(rsqrtps_r128_rm128)(i386_state *cpustate) // Opcode 0f 52
+void i386_device::sse_rsqrtps_r128_rm128() // Opcode 0f 52
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = 1.0 / sqrt(XMM(modrm & 0x7).f[0]);
XMM((modrm >> 3) & 0x7).f[1] = 1.0 / sqrt(XMM(modrm & 0x7).f[1]);
@@ -2889,19 +2889,19 @@ static void SSEOP(rsqrtps_r128_rm128)(i386_state *cpustate) // Opcode 0f 52
XMM((modrm >> 3) & 0x7).f[3] = 1.0 / sqrt(XMM(modrm & 0x7).f[3]);
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = 1.0 / sqrt(src.f[0]);
XMM((modrm >> 3) & 0x7).f[1] = 1.0 / sqrt(src.f[1]);
XMM((modrm >> 3) & 0x7).f[2] = 1.0 / sqrt(src.f[2]);
XMM((modrm >> 3) & 0x7).f[3] = 1.0 / sqrt(src.f[3]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(rcpps_r128_rm128)(i386_state *cpustate) // Opcode 0f 53
+void i386_device::sse_rcpps_r128_rm128() // Opcode 0f 53
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = 1.0 / XMM(modrm & 0x7).f[0];
XMM((modrm >> 3) & 0x7).f[1] = 1.0 / XMM(modrm & 0x7).f[1];
@@ -2909,67 +2909,67 @@ static void SSEOP(rcpps_r128_rm128)(i386_state *cpustate) // Opcode 0f 53
XMM((modrm >> 3) & 0x7).f[3] = 1.0 / XMM(modrm & 0x7).f[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = 1.0 / src.f[0];
XMM((modrm >> 3) & 0x7).f[1] = 1.0 / src.f[1];
XMM((modrm >> 3) & 0x7).f[2] = 1.0 / src.f[2];
XMM((modrm >> 3) & 0x7).f[3] = 1.0 / src.f[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(andps_r128_rm128)(i386_state *cpustate) // Opcode 0f 54
+void i386_device::sse_andps_r128_rm128() // Opcode 0f 54
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).q[0] = XMM((modrm >> 3) & 0x7).q[0] & XMM(modrm & 0x7).q[0];
XMM((modrm >> 3) & 0x7).q[1] = XMM((modrm >> 3) & 0x7).q[1] & XMM(modrm & 0x7).q[1];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).q[0] = XMM((modrm >> 3) & 0x7).q[0] & src.q[0];
XMM((modrm >> 3) & 0x7).q[1] = XMM((modrm >> 3) & 0x7).q[1] & src.q[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(andnps_r128_rm128)(i386_state *cpustate) // Opcode 0f 55
+void i386_device::sse_andnps_r128_rm128() // Opcode 0f 55
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).q[0] = ~(XMM((modrm >> 3) & 0x7).q[0]) & XMM(modrm & 0x7).q[0];
XMM((modrm >> 3) & 0x7).q[1] = ~(XMM((modrm >> 3) & 0x7).q[1]) & XMM(modrm & 0x7).q[1];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).q[0] = ~(XMM((modrm >> 3) & 0x7).q[0]) & src.q[0];
XMM((modrm >> 3) & 0x7).q[1] = ~(XMM((modrm >> 3) & 0x7).q[1]) & src.q[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(orps_r128_rm128)(i386_state *cpustate) // Opcode 0f 56
+void i386_device::sse_orps_r128_rm128() // Opcode 0f 56
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).q[0] = XMM((modrm >> 3) & 0x7).q[0] | XMM(modrm & 0x7).q[0];
XMM((modrm >> 3) & 0x7).q[1] = XMM((modrm >> 3) & 0x7).q[1] | XMM(modrm & 0x7).q[1];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).q[0] = XMM((modrm >> 3) & 0x7).q[0] | src.q[0];
XMM((modrm >> 3) & 0x7).q[1] = XMM((modrm >> 3) & 0x7).q[1] | src.q[1];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(mulps)(i386_state *cpustate) // Opcode 0f 59 ????
+void i386_device::sse_mulps() // Opcode 0f 59 ????
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] * XMM(modrm & 0x7).f[0];
XMM((modrm >> 3) & 0x7).f[1] = XMM((modrm >> 3) & 0x7).f[1] * XMM(modrm & 0x7).f[1];
@@ -2977,19 +2977,19 @@ static void SSEOP(mulps)(i386_state *cpustate) // Opcode 0f 59 ????
XMM((modrm >> 3) & 0x7).f[3] = XMM((modrm >> 3) & 0x7).f[3] * XMM(modrm & 0x7).f[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] * src.f[0];
XMM((modrm >> 3) & 0x7).f[1] = XMM((modrm >> 3) & 0x7).f[1] * src.f[1];
XMM((modrm >> 3) & 0x7).f[2] = XMM((modrm >> 3) & 0x7).f[2] * src.f[2];
XMM((modrm >> 3) & 0x7).f[3] = XMM((modrm >> 3) & 0x7).f[3] * src.f[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(subps)(i386_state *cpustate) // Opcode 0f 5c
+void i386_device::sse_subps() // Opcode 0f 5c
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] - XMM(modrm & 0x7).f[0];
XMM((modrm >> 3) & 0x7).f[1] = XMM((modrm >> 3) & 0x7).f[1] - XMM(modrm & 0x7).f[1];
@@ -2997,14 +2997,14 @@ static void SSEOP(subps)(i386_state *cpustate) // Opcode 0f 5c
XMM((modrm >> 3) & 0x7).f[3] = XMM((modrm >> 3) & 0x7).f[3] - XMM(modrm & 0x7).f[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] - src.f[0];
XMM((modrm >> 3) & 0x7).f[1] = XMM((modrm >> 3) & 0x7).f[1] - src.f[1];
XMM((modrm >> 3) & 0x7).f[2] = XMM((modrm >> 3) & 0x7).f[2] - src.f[2];
XMM((modrm >> 3) & 0x7).f[3] = XMM((modrm >> 3) & 0x7).f[3] - src.f[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
INLINE float sse_min_single(float src1, float src2)
@@ -3020,9 +3020,9 @@ INLINE float sse_min_single(float src1, float src2)
return src2;
}
-static void SSEOP(minps)(i386_state *cpustate) // Opcode 0f 5d
+void i386_device::sse_minps() // Opcode 0f 5d
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = sse_min_single(XMM((modrm >> 3) & 0x7).f[0], XMM(modrm & 0x7).f[0]);
XMM((modrm >> 3) & 0x7).f[1] = sse_min_single(XMM((modrm >> 3) & 0x7).f[1], XMM(modrm & 0x7).f[1]);
@@ -3030,19 +3030,19 @@ static void SSEOP(minps)(i386_state *cpustate) // Opcode 0f 5d
XMM((modrm >> 3) & 0x7).f[3] = sse_min_single(XMM((modrm >> 3) & 0x7).f[3], XMM(modrm & 0x7).f[3]);
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = sse_min_single(XMM((modrm >> 3) & 0x7).f[0], src.f[0]);
XMM((modrm >> 3) & 0x7).f[1] = sse_min_single(XMM((modrm >> 3) & 0x7).f[1], src.f[1]);
XMM((modrm >> 3) & 0x7).f[2] = sse_min_single(XMM((modrm >> 3) & 0x7).f[2], src.f[2]);
XMM((modrm >> 3) & 0x7).f[3] = sse_min_single(XMM((modrm >> 3) & 0x7).f[3], src.f[3]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(divps)(i386_state *cpustate) // Opcode 0f 5e
+void i386_device::sse_divps() // Opcode 0f 5e
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] / XMM(modrm & 0x7).f[0];
XMM((modrm >> 3) & 0x7).f[1] = XMM((modrm >> 3) & 0x7).f[1] / XMM(modrm & 0x7).f[1];
@@ -3050,14 +3050,14 @@ static void SSEOP(divps)(i386_state *cpustate) // Opcode 0f 5e
XMM((modrm >> 3) & 0x7).f[3] = XMM((modrm >> 3) & 0x7).f[3] / XMM(modrm & 0x7).f[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] / src.f[0];
XMM((modrm >> 3) & 0x7).f[1] = XMM((modrm >> 3) & 0x7).f[1] / src.f[1];
XMM((modrm >> 3) & 0x7).f[2] = XMM((modrm >> 3) & 0x7).f[2] / src.f[2];
XMM((modrm >> 3) & 0x7).f[3] = XMM((modrm >> 3) & 0x7).f[3] / src.f[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
INLINE float sse_max_single(float src1, float src2)
@@ -3073,9 +3073,9 @@ INLINE float sse_max_single(float src1, float src2)
return src2;
}
-static void SSEOP(maxps)(i386_state *cpustate) // Opcode 0f 5f
+void i386_device::sse_maxps() // Opcode 0f 5f
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = sse_max_single(XMM((modrm >> 3) & 0x7).f[0], XMM(modrm & 0x7).f[0]);
XMM((modrm >> 3) & 0x7).f[1] = sse_max_single(XMM((modrm >> 3) & 0x7).f[1], XMM(modrm & 0x7).f[1]);
@@ -3083,220 +3083,220 @@ static void SSEOP(maxps)(i386_state *cpustate) // Opcode 0f 5f
XMM((modrm >> 3) & 0x7).f[3] = sse_max_single(XMM((modrm >> 3) & 0x7).f[3], XMM(modrm & 0x7).f[3]);
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = sse_max_single(XMM((modrm >> 3) & 0x7).f[0], src.f[0]);
XMM((modrm >> 3) & 0x7).f[1] = sse_max_single(XMM((modrm >> 3) & 0x7).f[1], src.f[1]);
XMM((modrm >> 3) & 0x7).f[2] = sse_max_single(XMM((modrm >> 3) & 0x7).f[2], src.f[2]);
XMM((modrm >> 3) & 0x7).f[3] = sse_max_single(XMM((modrm >> 3) & 0x7).f[3], src.f[3]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(maxss_r128_r128m32)(i386_state *cpustate) // Opcode f3 0f 5f
+void i386_device::sse_maxss_r128_r128m32() // Opcode f3 0f 5f
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = sse_max_single(XMM((modrm >> 3) & 0x7).f[0], XMM(modrm & 0x7).f[0]);
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- src.d[0]=READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ src.d[0]=READ32(ea);
XMM((modrm >> 3) & 0x7).f[0] = sse_max_single(XMM((modrm >> 3) & 0x7).f[0], src.f[0]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(addss)(i386_state *cpustate) // Opcode f3 0f 58
+void i386_device::sse_addss() // Opcode f3 0f 58
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] + XMM(modrm & 0x7).f[0];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] + src.f[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(subss)(i386_state *cpustate) // Opcode f3 0f 5c
+void i386_device::sse_subss() // Opcode f3 0f 5c
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] - XMM(modrm & 0x7).f[0];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] - src.f[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(mulss)(i386_state *cpustate) // Opcode f3 0f 5e
+void i386_device::sse_mulss() // Opcode f3 0f 5e
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] * XMM(modrm & 0x7).f[0];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] * src.f[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(divss)(i386_state *cpustate) // Opcode 0f 59
+void i386_device::sse_divss() // Opcode 0f 59
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] / XMM(modrm & 0x7).f[0];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] / src.f[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(rcpss_r128_r128m32)(i386_state *cpustate) // Opcode f3 0f 53
+void i386_device::sse_rcpss_r128_r128m32() // Opcode f3 0f 53
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = 1.0 / XMM(modrm & 0x7).f[0];
} else {
XMM_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- s.d[0]=READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ s.d[0]=READ32(ea);
XMM((modrm >> 3) & 0x7).f[0] = 1.0 / s.f[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(sqrtss_r128_r128m32)(i386_state *cpustate) // Opcode f3 0f 51
+void i386_device::sse_sqrtss_r128_r128m32() // Opcode f3 0f 51
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = sqrt(XMM(modrm & 0x7).f[0]);
} else {
XMM_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- s.d[0]=READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ s.d[0]=READ32(ea);
XMM((modrm >> 3) & 0x7).f[0] = sqrt(s.f[0]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(rsqrtss_r128_r128m32)(i386_state *cpustate) // Opcode f3 0f 52
+void i386_device::sse_rsqrtss_r128_r128m32() // Opcode f3 0f 52
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = 1.0 / sqrt(XMM(modrm & 0x7).f[0]);
} else {
XMM_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- s.d[0]=READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ s.d[0]=READ32(ea);
XMM((modrm >> 3) & 0x7).f[0] = 1.0 / sqrt(s.f[0]);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(minss_r128_r128m32)(i386_state *cpustate) // Opcode f3 0f 5d
+void i386_device::sse_minss_r128_r128m32() // Opcode f3 0f 5d
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] < XMM(modrm & 0x7).f[0] ? XMM((modrm >> 3) & 0x7).f[0] : XMM(modrm & 0x7).f[0];
} else {
XMM_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- s.d[0] = READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ s.d[0] = READ32(ea);
XMM((modrm >> 3) & 0x7).f[0] = XMM((modrm >> 3) & 0x7).f[0] < s.f[0] ? XMM((modrm >> 3) & 0x7).f[0] : s.f[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(comiss_r128_r128m32)(i386_state *cpustate) // Opcode 0f 2f
+void i386_device::sse_comiss_r128_r128m32() // Opcode 0f 2f
{
float32 a,b;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
a = XMM((modrm >> 3) & 0x7).d[0];
b = XMM(modrm & 0x7).d[0];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
a = XMM((modrm >> 3) & 0x7).d[0];
b = src.d[0];
}
- cpustate->OF=0;
- cpustate->SF=0;
- cpustate->AF=0;
+ m_OF=0;
+ m_SF=0;
+ m_AF=0;
if (float32_is_nan(a) || float32_is_nan(b))
{
- cpustate->ZF = 1;
- cpustate->PF = 1;
- cpustate->CF = 1;
+ m_ZF = 1;
+ m_PF = 1;
+ m_CF = 1;
}
else
{
- cpustate->ZF = 0;
- cpustate->PF = 0;
- cpustate->CF = 0;
+ m_ZF = 0;
+ m_PF = 0;
+ m_CF = 0;
if (float32_eq(a, b))
- cpustate->ZF = 1;
+ m_ZF = 1;
if (float32_lt(a, b))
- cpustate->CF = 1;
+ m_CF = 1;
}
// should generate exception when at least one of the operands is either QNaN or SNaN
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(ucomiss_r128_r128m32)(i386_state *cpustate) // Opcode 0f 2e
+void i386_device::sse_ucomiss_r128_r128m32() // Opcode 0f 2e
{
float32 a,b;
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
a = XMM((modrm >> 3) & 0x7).d[0];
b = XMM(modrm & 0x7).d[0];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
a = XMM((modrm >> 3) & 0x7).d[0];
b = src.d[0];
}
- cpustate->OF=0;
- cpustate->SF=0;
- cpustate->AF=0;
+ m_OF=0;
+ m_SF=0;
+ m_AF=0;
if (float32_is_nan(a) || float32_is_nan(b))
{
- cpustate->ZF = 1;
- cpustate->PF = 1;
- cpustate->CF = 1;
+ m_ZF = 1;
+ m_PF = 1;
+ m_CF = 1;
}
else
{
- cpustate->ZF = 0;
- cpustate->PF = 0;
- cpustate->CF = 0;
+ m_ZF = 0;
+ m_PF = 0;
+ m_CF = 0;
if (float32_eq(a, b))
- cpustate->ZF = 1;
+ m_ZF = 1;
if (float32_lt(a, b))
- cpustate->CF = 1;
+ m_CF = 1;
}
// should generate exception when at least one of the operands is SNaN
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(shufps)(i386_state *cpustate) // Opcode 0f 67
+void i386_device::sse_shufps() // Opcode 0f 67
{
- UINT8 modrm = FETCH(cpustate);
- UINT8 sel = FETCH(cpustate);
+ UINT8 modrm = FETCH();
+ UINT8 sel = FETCH();
int m1,m2,m3,m4;
int s,d;
m1=sel & 3;
@@ -3315,20 +3315,20 @@ static void SSEOP(shufps)(i386_state *cpustate) // Opcode 0f 67
} else {
UINT32 t;
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
t=XMM(d).d[m1];
XMM(d).d[1]=XMM(d).d[m2];
XMM(d).d[0]=t;
XMM(d).d[2]=src.d[m3];
XMM(d).d[3]=src.d[m4];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(unpcklps_r128_rm128)(i386_state *cpustate) // Opcode 0f 14
+void i386_device::sse_unpcklps_r128_rm128() // Opcode 0f 14
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
int s,d;
s=modrm & 0x7;
d=(modrm >> 3) & 0x7;
@@ -3339,18 +3339,18 @@ static void SSEOP(unpcklps_r128_rm128)(i386_state *cpustate) // Opcode 0f 14
//XMM(d).d[0]=XMM(d).d[0];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM(d).d[3]=src.d[1];
XMM(d).d[2]=XMM(d).d[1];
XMM(d).d[1]=src.d[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(unpckhps_r128_rm128)(i386_state *cpustate) // Opcode 0f 15
+void i386_device::sse_unpckhps_r128_rm128() // Opcode 0f 15
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
int s,d;
s=modrm & 0x7;
d=(modrm >> 3) & 0x7;
@@ -3361,14 +3361,14 @@ static void SSEOP(unpckhps_r128_rm128)(i386_state *cpustate) // Opcode 0f 15
XMM(d).d[3]=XMM(s).d[3];
} else {
XMM_REG src;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READXMM(cpustate, ea, src);
+ UINT32 ea = GetEA(modrm, 0);
+ READXMM(ea, src);
XMM(d).d[0]=XMM(d).d[2];
XMM(d).d[1]=src.d[2];
XMM(d).d[2]=XMM(d).d[3];
XMM(d).d[3]=src.d[3];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
INLINE bool sse_issingleordered(float op1, float op2)
@@ -3383,7 +3383,7 @@ INLINE bool sse_issingleunordered(float op1, float op2)
return !((op1 != op1) || (op1 != op2));
}
-INLINE void sse_predicate_compare_single(UINT8 imm8, XMM_REG d, XMM_REG s)
+void i386_device::sse_predicate_compare_single(UINT8 imm8, XMM_REG d, XMM_REG s)
{
switch (imm8 & 7)
{
@@ -3438,7 +3438,7 @@ INLINE void sse_predicate_compare_single(UINT8 imm8, XMM_REG d, XMM_REG s)
}
}
-INLINE void sse_predicate_compare_single_scalar(UINT8 imm8, XMM_REG d, XMM_REG s)
+void i386_device::sse_predicate_compare_single_scalar(UINT8 imm8, XMM_REG d, XMM_REG s)
{
switch (imm8 & 7)
{
@@ -3469,186 +3469,186 @@ INLINE void sse_predicate_compare_single_scalar(UINT8 imm8, XMM_REG d, XMM_REG s
}
}
-static void SSEOP(cmpps_r128_rm128_i8)(i386_state *cpustate) // Opcode 0f c2
+void i386_device::sse_cmpps_r128_rm128_i8() // Opcode 0f c2
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
- UINT8 imm8 = FETCH(cpustate);
+ UINT8 imm8 = FETCH();
s=modrm & 0x7;
d=(modrm >> 3) & 0x7;
sse_predicate_compare_single(imm8, XMM(d), XMM(s));
} else {
int d;
XMM_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- UINT8 imm8 = FETCH(cpustate);
- READXMM(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ UINT8 imm8 = FETCH();
+ READXMM(ea, s);
d=(modrm >> 3) & 0x7;
sse_predicate_compare_single(imm8, XMM(d), s);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(cmpss_r128_r128m32_i8)(i386_state *cpustate) // Opcode f3 0f c2
+void i386_device::sse_cmpss_r128_r128m32_i8() // Opcode f3 0f c2
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
int s,d;
- UINT8 imm8 = FETCH(cpustate);
+ UINT8 imm8 = FETCH();
s=modrm & 0x7;
d=(modrm >> 3) & 0x7;
sse_predicate_compare_single_scalar(imm8, XMM(d), XMM(s));
} else {
int d;
XMM_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- UINT8 imm8 = FETCH(cpustate);
- s.d[0]=READ32(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ UINT8 imm8 = FETCH();
+ s.d[0]=READ32(ea);
d=(modrm >> 3) & 0x7;
sse_predicate_compare_single_scalar(imm8, XMM(d), s);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pinsrw_r64_r16m16_i8)(i386_state *cpustate) // Opcode 0f c4
+void i386_device::sse_pinsrw_r64_r16m16_i8() // Opcode 0f c4
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
- UINT8 imm8 = FETCH(cpustate);
+ UINT8 imm8 = FETCH();
UINT16 v = LOAD_RM16(modrm);
MMX((modrm >> 3) & 0x7).w[imm8 & 3] = v;
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- UINT8 imm8 = FETCH(cpustate);
- UINT16 v = READ16(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ UINT8 imm8 = FETCH();
+ UINT16 v = READ16(ea);
MMX((modrm >> 3) & 0x7).w[imm8 & 3] = v;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pinsrw_r64_r32m16_i8)(i386_state *cpustate) // Opcode 0f c4
+void i386_device::sse_pinsrw_r64_r32m16_i8() // Opcode 0f c4
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
- UINT8 imm8 = FETCH(cpustate);
+ UINT8 imm8 = FETCH();
UINT16 v = (UINT16)LOAD_RM32(modrm);
MMX((modrm >> 3) & 0x7).w[imm8 & 3] = v;
} else {
- UINT32 ea = GetEA(cpustate, modrm, 0);
- UINT8 imm8 = FETCH(cpustate);
- UINT16 v = READ16(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ UINT8 imm8 = FETCH();
+ UINT16 v = READ16(ea);
MMX((modrm >> 3) & 0x7).w[imm8 & 3] = v;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pextrw_r16_r64_i8)(i386_state *cpustate) // Opcode 0f c5
+void i386_device::sse_pextrw_r16_r64_i8() // Opcode 0f c5
{
- //MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ //MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
- UINT8 imm8 = FETCH(cpustate);
+ UINT8 imm8 = FETCH();
STORE_REG16(modrm, MMX(modrm & 0x7).w[imm8 & 3]);
} else {
- //UINT8 imm8 = FETCH(cpustate);
- report_invalid_modrm(cpustate, "pextrw_r16_r64_i8", modrm);
+ //UINT8 imm8 = FETCH();
+ report_invalid_modrm("pextrw_r16_r64_i8", modrm);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pextrw_r32_r64_i8)(i386_state *cpustate) // Opcode 0f c5
+void i386_device::sse_pextrw_r32_r64_i8() // Opcode 0f c5
{
- //MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ //MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
- UINT8 imm8 = FETCH(cpustate);
+ UINT8 imm8 = FETCH();
STORE_REG32(modrm, MMX(modrm & 0x7).w[imm8 & 3]);
} else {
- //UINT8 imm8 = FETCH(cpustate);
- report_invalid_modrm(cpustate, "pextrw_r32_r64_i8", modrm);
+ //UINT8 imm8 = FETCH();
+ report_invalid_modrm("pextrw_r32_r64_i8", modrm);
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pminub_r64_rm64)(i386_state *cpustate) // Opcode 0f da
+void i386_device::sse_pminub_r64_rm64() // Opcode 0f da
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n] = MMX((modrm >> 3) & 0x7).b[n] < MMX(modrm & 0x7).b[n] ? MMX((modrm >> 3) & 0x7).b[n] : MMX(modrm & 0x7).b[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n] = MMX((modrm >> 3) & 0x7).b[n] < s.b[n] ? MMX((modrm >> 3) & 0x7).b[n] : s.b[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pmaxub_r64_rm64)(i386_state *cpustate) // Opcode 0f de
+void i386_device::sse_pmaxub_r64_rm64() // Opcode 0f de
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n] = MMX((modrm >> 3) & 0x7).b[n] > MMX(modrm & 0x7).b[n] ? MMX((modrm >> 3) & 0x7).b[n] : MMX(modrm & 0x7).b[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n] = MMX((modrm >> 3) & 0x7).b[n] > s.b[n] ? MMX((modrm >> 3) & 0x7).b[n] : s.b[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pavgb_r64_rm64)(i386_state *cpustate) // Opcode 0f e0
+void i386_device::sse_pavgb_r64_rm64() // Opcode 0f e0
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n] = ((UINT16)MMX((modrm >> 3) & 0x7).b[n] + (UINT16)MMX(modrm & 0x7).b[n] + 1) >> 1;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 8;n++)
MMX((modrm >> 3) & 0x7).b[n] = ((UINT16)MMX((modrm >> 3) & 0x7).b[n] + (UINT16)s.b[n] + 1) >> 1;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pavgw_r64_rm64)(i386_state *cpustate) // Opcode 0f e3
+void i386_device::sse_pavgw_r64_rm64() // Opcode 0f e3
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n] = ((UINT32)MMX((modrm >> 3) & 0x7).w[n] + (UINT32)MMX(modrm & 0x7).w[n] + 1) >> 1;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).w[n] = ((UINT32)MMX((modrm >> 3) & 0x7).w[n] + (UINT32)s.w[n] + 1) >> 1;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pmulhuw_r64_rm64)(i386_state *cpustate) // Opcode 0f e4
+void i386_device::sse_pmulhuw_r64_rm64() // Opcode 0f e4
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).w[0]=((UINT32)MMX((modrm >> 3) & 0x7).w[0]*(UINT32)MMX(modrm & 7).w[0]) >> 16;
MMX((modrm >> 3) & 0x7).w[1]=((UINT32)MMX((modrm >> 3) & 0x7).w[1]*(UINT32)MMX(modrm & 7).w[1]) >> 16;
@@ -3656,73 +3656,73 @@ static void SSEOP(pmulhuw_r64_rm64)(i386_state *cpustate) // Opcode 0f e4
MMX((modrm >> 3) & 0x7).w[3]=((UINT32)MMX((modrm >> 3) & 0x7).w[3]*(UINT32)MMX(modrm & 7).w[3]) >> 16;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX((modrm >> 3) & 0x7).w[0]=((UINT32)MMX((modrm >> 3) & 0x7).w[0]*(UINT32)s.w[0]) >> 16;
MMX((modrm >> 3) & 0x7).w[1]=((UINT32)MMX((modrm >> 3) & 0x7).w[1]*(UINT32)s.w[1]) >> 16;
MMX((modrm >> 3) & 0x7).w[2]=((UINT32)MMX((modrm >> 3) & 0x7).w[2]*(UINT32)s.w[2]) >> 16;
MMX((modrm >> 3) & 0x7).w[3]=((UINT32)MMX((modrm >> 3) & 0x7).w[3]*(UINT32)s.w[3]) >> 16;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pminsw_r64_rm64)(i386_state *cpustate) // Opcode 0f ea
+void i386_device::sse_pminsw_r64_rm64() // Opcode 0f ea
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).s[n] = MMX((modrm >> 3) & 0x7).s[n] < MMX(modrm & 0x7).s[n] ? MMX((modrm >> 3) & 0x7).s[n] : MMX(modrm & 0x7).s[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).s[n] = MMX((modrm >> 3) & 0x7).s[n] < s.s[n] ? MMX((modrm >> 3) & 0x7).s[n] : s.s[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pmaxsw_r64_rm64)(i386_state *cpustate) // Opcode 0f ee
+void i386_device::sse_pmaxsw_r64_rm64() // Opcode 0f ee
{
int n;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).s[n] = MMX((modrm >> 3) & 0x7).s[n] > MMX(modrm & 0x7).s[n] ? MMX((modrm >> 3) & 0x7).s[n] : MMX(modrm & 0x7).s[n];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
for (n=0;n < 4;n++)
MMX((modrm >> 3) & 0x7).s[n] = MMX((modrm >> 3) & 0x7).s[n] > s.s[n] ? MMX((modrm >> 3) & 0x7).s[n] : s.s[n];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pmuludq_r64_rm64)(i386_state *cpustate) // Opcode 0f f4
+void i386_device::sse_pmuludq_r64_rm64() // Opcode 0f f4
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).q = (UINT64)MMX((modrm >> 3) & 0x7).d[0] * (UINT64)MMX(modrm & 0x7).d[0];
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX((modrm >> 3) & 0x7).q = (UINT64)MMX((modrm >> 3) & 0x7).d[0] * (UINT64)s.d[0];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(psadbw_r64_rm64)(i386_state *cpustate) // Opcode 0f f6
+void i386_device::sse_psadbw_r64_rm64() // Opcode 0f f6
{
int n;
INT32 temp;
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
temp=0;
for (n=0;n < 8;n++)
@@ -3730,38 +3730,38 @@ static void SSEOP(psadbw_r64_rm64)(i386_state *cpustate) // Opcode 0f f6
MMX((modrm >> 3) & 0x7).l=(UINT64)temp & 0xffff;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
temp=0;
for (n=0;n < 8;n++)
temp += abs((INT32)MMX((modrm >> 3) & 0x7).b[n] - (INT32)s.b[n]);
MMX((modrm >> 3) & 0x7).l=(UINT64)temp & 0xffff;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(psubq_r64_rm64)(i386_state *cpustate) // Opcode 0f fb
+void i386_device::sse_psubq_r64_rm64() // Opcode 0f fb
{
- MMXPROLOG(cpustate);
- UINT8 modrm = FETCH(cpustate);
+ MMXPROLOG();
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q - MMX(modrm & 7).q;
} else {
MMX_REG s;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- READMMX(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ READMMX(ea, s);
MMX((modrm >> 3) & 0x7).q=MMX((modrm >> 3) & 0x7).q - s.q;
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
-static void SSEOP(pshufhw_r128_rm128_i8)(i386_state *cpustate) // Opcode f3 0f 70
+void i386_device::sse_pshufhw_r128_rm128_i8() // Opcode f3 0f 70
{
- UINT8 modrm = FETCH(cpustate);
+ UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
XMM_REG t;
int s,d;
- UINT8 imm8 = FETCH(cpustate);
+ UINT8 imm8 = FETCH();
s=modrm & 0x7;
d=(modrm >> 3) & 0x7;
t.q[0]=XMM(s).q[1];
@@ -3773,14 +3773,14 @@ static void SSEOP(pshufhw_r128_rm128_i8)(i386_state *cpustate) // Opcode f3 0f 7
} else {
XMM_REG s;
int d=(modrm >> 3) & 0x7;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- UINT8 imm8 = FETCH(cpustate);
- READXMM(cpustate, ea, s);
+ UINT32 ea = GetEA(modrm, 0);
+ UINT8 imm8 = FETCH();
+ READXMM(ea, s);
XMM(d).q[0]=s.q[0];
XMM(d).w[4]=s.w[4 + (imm8 & 3)];
XMM(d).w[5]=s.w[4 + ((imm8 >> 2) & 3)];
XMM(d).w[6]=s.w[4 + ((imm8 >> 4) & 3)];
XMM(d).w[7]=s.w[4 + ((imm8 >> 6) & 3)];
}
- CYCLES(cpustate,1); // TODO: correct cycle count
+ CYCLES(1); // TODO: correct cycle count
}
diff --git a/src/emu/cpu/i386/x87ops.c b/src/emu/cpu/i386/x87ops.c
index 8ab1c7b1c56..eee11fa7156 100644
--- a/src/emu/cpu/i386/x87ops.c
+++ b/src/emu/cpu/i386/x87ops.c
@@ -72,15 +72,15 @@
*
*************************************/
-#define ST_TO_PHYS(x) (((cpustate->x87_sw >> X87_SW_TOP_SHIFT) + (x)) & X87_SW_TOP_MASK)
-#define ST(x) (cpustate->x87_reg[ST_TO_PHYS(x)])
+#define ST_TO_PHYS(x) (((m_x87_sw >> X87_SW_TOP_SHIFT) + (x)) & X87_SW_TOP_MASK)
+#define ST(x) (m_x87_reg[ST_TO_PHYS(x)])
#define X87_TW_FIELD_SHIFT(x) ((x) << 1)
-#define X87_TAG(x) ((cpustate->x87_tw >> X87_TW_FIELD_SHIFT(x)) & X87_TW_MASK)
-#define X87_RC ((cpustate->x87_cw >> X87_CW_RC_SHIFT) & X87_CW_RC_MASK)
+#define X87_TAG(x) ((m_x87_tw >> X87_TW_FIELD_SHIFT(x)) & X87_TW_MASK)
+#define X87_RC ((m_x87_cw >> X87_CW_RC_SHIFT) & X87_CW_RC_MASK)
#define X87_IS_ST_EMPTY(x) (X87_TAG(ST_TO_PHYS(x)) == X87_TW_EMPTY)
#define X87_SW_C3_0 X87_SW_C0
-#define UNIMPLEMENTED fatalerror("Unimplemented x87 op: %s (PC:%x)\n", __FUNCTION__, cpustate->pc)
+#define UNIMPLEMENTED fatalerror("Unimplemented x87 op: %s (PC:%x)\n", __FUNCTION__, m_pc)
/*************************************
@@ -147,20 +147,20 @@ INLINE floatx80 double_to_fx80(double in)
return float64_to_floatx80(*(UINT64*)&in);
}
-INLINE floatx80 READ80(i386_state *cpustate, UINT32 ea)
+floatx80 i386_device::READ80(UINT32 ea)
{
floatx80 t;
- t.low = READ64(cpustate, ea);
- t.high = READ16(cpustate, ea + 8);
+ t.low = READ64(ea);
+ t.high = READ16(ea + 8);
return t;
}
-INLINE void WRITE80(i386_state *cpustate, UINT32 ea, floatx80 t)
+void i386_device::WRITE80(UINT32 ea, floatx80 t)
{
- WRITE64(cpustate, ea, t.low);
- WRITE16(cpustate, ea + 8, t.high);
+ WRITE64(ea, t.low);
+ WRITE16(ea + 8, t.high);
}
@@ -170,21 +170,21 @@ INLINE void WRITE80(i386_state *cpustate, UINT32 ea, floatx80 t)
*
*************************************/
-INLINE void x87_set_stack_top(i386_state *cpustate, int top)
+void i386_device::x87_set_stack_top(int top)
{
- cpustate->x87_sw &= ~(X87_SW_TOP_MASK << X87_SW_TOP_SHIFT);
- cpustate->x87_sw |= (top << X87_SW_TOP_SHIFT);
+ m_x87_sw &= ~(X87_SW_TOP_MASK << X87_SW_TOP_SHIFT);
+ m_x87_sw |= (top << X87_SW_TOP_SHIFT);
}
-INLINE void x87_set_tag(i386_state *cpustate, int reg, int tag)
+void i386_device::x87_set_tag(int reg, int tag)
{
int shift = X87_TW_FIELD_SHIFT(reg);
- cpustate->x87_tw &= ~(X87_TW_MASK << shift);
- cpustate->x87_tw |= (tag << shift);
+ m_x87_tw &= ~(X87_TW_MASK << shift);
+ m_x87_tw |= (tag << shift);
}
-void x87_write_stack(i386_state *cpustate, int i, floatx80 value, int update_tag)
+void i386_device::x87_write_stack(int i, floatx80 value, int update_tag)
{
ST(i) = value;
@@ -205,22 +205,22 @@ void x87_write_stack(i386_state *cpustate, int i, floatx80 value, int update_tag
tag = X87_TW_VALID;
}
- x87_set_tag(cpustate, ST_TO_PHYS(i), tag);
+ x87_set_tag(ST_TO_PHYS(i), tag);
}
}
-INLINE void x87_set_stack_underflow(i386_state *cpustate)
+void i386_device::x87_set_stack_underflow()
{
- cpustate->x87_sw |= X87_SW_C1 | X87_SW_IE | X87_SW_SF;
+ m_x87_sw |= X87_SW_C1 | X87_SW_IE | X87_SW_SF;
}
-INLINE void x87_set_stack_overflow(i386_state *cpustate)
+void i386_device::x87_set_stack_overflow()
{
- cpustate->x87_sw &= ~X87_SW_C1;
- cpustate->x87_sw |= X87_SW_IE | X87_SW_SF;
+ m_x87_sw &= ~X87_SW_C1;
+ m_x87_sw |= X87_SW_IE | X87_SW_SF;
}
-int x87_inc_stack(i386_state *cpustate)
+int i386_device::x87_inc_stack()
{
int ret = 1;
@@ -228,19 +228,19 @@ int x87_inc_stack(i386_state *cpustate)
if (X87_IS_ST_EMPTY(0))
{
ret = 0;
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
// Don't update the stack if the exception is unmasked
- if (~cpustate->x87_cw & X87_CW_IM)
+ if (~m_x87_cw & X87_CW_IM)
return ret;
}
- x87_set_tag(cpustate, ST_TO_PHYS(0), X87_TW_EMPTY);
- x87_set_stack_top(cpustate, ST_TO_PHYS(1));
+ x87_set_tag(ST_TO_PHYS(0), X87_TW_EMPTY);
+ x87_set_stack_top(ST_TO_PHYS(1));
return ret;
}
-int x87_dec_stack(i386_state *cpustate)
+int i386_device::x87_dec_stack()
{
int ret = 1;
@@ -248,14 +248,14 @@ int x87_dec_stack(i386_state *cpustate)
if (!X87_IS_ST_EMPTY(7))
{
ret = 0;
- x87_set_stack_overflow(cpustate);
+ x87_set_stack_overflow();
// Don't update the stack if the exception is unmasked
- if (~cpustate->x87_cw & X87_CW_IM)
+ if (~m_x87_cw & X87_CW_IM)
return ret;
}
- x87_set_stack_top(cpustate, ST_TO_PHYS(7));
+ x87_set_stack_top(ST_TO_PHYS(7));
return ret;
}
@@ -266,38 +266,38 @@ int x87_dec_stack(i386_state *cpustate)
*
*************************************/
-int x87_check_exceptions(i386_state *cpustate)
+int i386_device::x87_check_exceptions()
{
/* Update the exceptions from SoftFloat */
if (float_exception_flags & float_flag_invalid)
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
float_exception_flags &= ~float_flag_invalid;
}
if (float_exception_flags & float_flag_overflow)
{
- cpustate->x87_sw |= X87_SW_OE;
+ m_x87_sw |= X87_SW_OE;
float_exception_flags &= ~float_flag_overflow;
}
if (float_exception_flags & float_flag_underflow)
{
- cpustate->x87_sw |= X87_SW_UE;
+ m_x87_sw |= X87_SW_UE;
float_exception_flags &= ~float_flag_underflow;
}
if (float_exception_flags & float_flag_inexact)
{
- cpustate->x87_sw |= X87_SW_PE;
+ m_x87_sw |= X87_SW_PE;
float_exception_flags &= ~float_flag_inexact;
}
- if ((cpustate->x87_sw & ~cpustate->x87_cw) & 0x3f)
+ if ((m_x87_sw & ~m_x87_cw) & 0x3f)
{
- // cpustate->device->execute().set_input_line(INPUT_LINE_FERR, RAISE_LINE);
- logerror("Unmasked x87 exception (CW:%.4x, SW:%.4x)\n", cpustate->x87_cw, cpustate->x87_sw);
- if (cpustate->cr[0] & 0x20) // FIXME: 486 and up only
+ // m_device->execute().set_input_line(INPUT_LINE_FERR, RAISE_LINE);
+ logerror("Unmasked x87 exception (CW:%.4x, SW:%.4x)\n", m_x87_cw, m_x87_sw);
+ if (m_cr[0] & 0x20) // FIXME: 486 and up only
{
- cpustate->ext = 1;
- i386_trap(cpustate, FAULT_MF, 0, 0);
+ m_ext = 1;
+ i386_trap(FAULT_MF, 0, 0);
}
return 0;
}
@@ -305,25 +305,25 @@ int x87_check_exceptions(i386_state *cpustate)
return 1;
}
-INLINE void x87_write_cw(i386_state *cpustate, UINT16 cw)
+void i386_device::x87_write_cw(UINT16 cw)
{
- cpustate->x87_cw = cw;
+ m_x87_cw = cw;
/* Update the SoftFloat rounding mode */
- float_rounding_mode = x87_to_sf_rc[(cpustate->x87_cw >> X87_CW_RC_SHIFT) & X87_CW_RC_MASK];
+ float_rounding_mode = x87_to_sf_rc[(m_x87_cw >> X87_CW_RC_SHIFT) & X87_CW_RC_MASK];
}
-void x87_reset(i386_state *cpustate)
+void i386_device::x87_reset()
{
- x87_write_cw(cpustate, 0x0037f);
+ x87_write_cw(0x0037f);
- cpustate->x87_sw = 0;
- cpustate->x87_tw = 0xffff;
+ m_x87_sw = 0;
+ m_x87_tw = 0xffff;
// TODO: FEA=0, FDS=0, FIP=0 FOP=0 FCS=0
- cpustate->x87_data_ptr = 0;
- cpustate->x87_inst_ptr = 0;
- cpustate->x87_opcode = 0;
+ m_x87_data_ptr = 0;
+ m_x87_inst_ptr = 0;
+ m_x87_opcode = 0;
}
@@ -333,11 +333,11 @@ void x87_reset(i386_state *cpustate)
*
*************************************/
-static floatx80 x87_add(i386_state *cpustate, floatx80 a, floatx80 b)
+floatx80 i386_device::x87_add(floatx80 a, floatx80 b)
{
floatx80 result = { 0 };
- switch ((cpustate->x87_cw >> X87_CW_PC_SHIFT) & X87_CW_PC_MASK)
+ switch ((m_x87_cw >> X87_CW_PC_SHIFT) & X87_CW_PC_MASK)
{
case X87_CW_PC_SINGLE:
{
@@ -363,11 +363,11 @@ static floatx80 x87_add(i386_state *cpustate, floatx80 a, floatx80 b)
return result;
}
-static floatx80 x87_sub(i386_state *cpustate, floatx80 a, floatx80 b)
+floatx80 i386_device::x87_sub(floatx80 a, floatx80 b)
{
floatx80 result = { 0 };
- switch ((cpustate->x87_cw >> X87_CW_PC_SHIFT) & X87_CW_PC_MASK)
+ switch ((m_x87_cw >> X87_CW_PC_SHIFT) & X87_CW_PC_MASK)
{
case X87_CW_PC_SINGLE:
{
@@ -393,11 +393,11 @@ static floatx80 x87_sub(i386_state *cpustate, floatx80 a, floatx80 b)
return result;
}
-static floatx80 x87_mul(i386_state *cpustate, floatx80 a, floatx80 b)
+floatx80 i386_device::x87_mul(floatx80 a, floatx80 b)
{
floatx80 val = { 0 };
- switch ((cpustate->x87_cw >> X87_CW_PC_SHIFT) & X87_CW_PC_MASK)
+ switch ((m_x87_cw >> X87_CW_PC_SHIFT) & X87_CW_PC_MASK)
{
case X87_CW_PC_SINGLE:
{
@@ -424,11 +424,11 @@ static floatx80 x87_mul(i386_state *cpustate, floatx80 a, floatx80 b)
}
-static floatx80 x87_div(i386_state *cpustate, floatx80 a, floatx80 b)
+floatx80 i386_device::x87_div(floatx80 a, floatx80 b)
{
floatx80 val = { 0 };
- switch ((cpustate->x87_cw >> X87_CW_PC_SHIFT) & X87_CW_PC_MASK)
+ switch ((m_x87_cw >> X87_CW_PC_SHIFT) & X87_CW_PC_MASK)
{
case X87_CW_PC_SINGLE:
{
@@ -466,19 +466,19 @@ static floatx80 x87_div(i386_state *cpustate, floatx80 a, floatx80 b)
*
*************************************/
-void x87_fadd_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fadd_m32real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
floatx80 a = ST(0);
floatx80 b = float32_to_floatx80(m32real);
@@ -486,34 +486,34 @@ void x87_fadd_m32real(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_add(cpustate, a, b);
+ result = x87_add(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fadd_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fadd_m64real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
floatx80 a = ST(0);
floatx80 b = float64_to_floatx80(m64real);
@@ -521,29 +521,29 @@ void x87_fadd_m64real(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_add(cpustate, a, b);
+ result = x87_add(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fadd_st_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fadd_st_sti(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -554,29 +554,29 @@ void x87_fadd_st_sti(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_add(cpustate, a, b);
+ result = x87_add(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fadd_sti_st(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fadd_sti_st(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -587,29 +587,29 @@ void x87_fadd_sti_st(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_add(cpustate, a, b);
+ result = x87_add(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, i, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(i, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_faddp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_faddp(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -620,37 +620,37 @@ void x87_faddp(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_add(cpustate, a, b);
+ result = x87_add(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(i, result, TRUE);
+ x87_inc_stack();
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fiadd_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fiadd_m32int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m32int);
@@ -658,34 +658,34 @@ void x87_fiadd_m32int(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_add(cpustate, a, b);
+ result = x87_add(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 19);
+ CYCLES(19);
}
-void x87_fiadd_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fiadd_m16int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT16 m16int = READ16(cpustate, ea);
+ INT16 m16int = READ16(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m16int);
@@ -693,19 +693,19 @@ void x87_fiadd_m16int(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_add(cpustate, a, b);
+ result = x87_add(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 20);
+ CYCLES(20);
}
@@ -715,19 +715,19 @@ void x87_fiadd_m16int(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fsub_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsub_m32real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
floatx80 a = ST(0);
floatx80 b = float32_to_floatx80(m32real);
@@ -735,34 +735,34 @@ void x87_fsub_m32real(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fsub_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsub_m64real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
floatx80 a = ST(0);
floatx80 b = float64_to_floatx80(m64real);
@@ -770,29 +770,29 @@ void x87_fsub_m64real(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fsub_st_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsub_st_sti(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -803,29 +803,29 @@ void x87_fsub_st_sti(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fsub_sti_st(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsub_sti_st(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -836,29 +836,29 @@ void x87_fsub_sti_st(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, i, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(i, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fsubp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsubp(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -869,37 +869,37 @@ void x87_fsubp(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(i, result, TRUE);
+ x87_inc_stack();
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fisub_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fisub_m32int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m32int);
@@ -907,34 +907,34 @@ void x87_fisub_m32int(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 19);
+ CYCLES(19);
}
-void x87_fisub_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fisub_m16int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT16 m16int = READ16(cpustate, ea);
+ INT16 m16int = READ16(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m16int);
@@ -942,19 +942,19 @@ void x87_fisub_m16int(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 20);
+ CYCLES(20);
}
@@ -964,19 +964,19 @@ void x87_fisub_m16int(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fsubr_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsubr_m32real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
floatx80 a = float32_to_floatx80(m32real);
floatx80 b = ST(0);
@@ -984,34 +984,34 @@ void x87_fsubr_m32real(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fsubr_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsubr_m64real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
floatx80 a = float64_to_floatx80(m64real);
floatx80 b = ST(0);
@@ -1019,29 +1019,29 @@ void x87_fsubr_m64real(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fsubr_st_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsubr_st_sti(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1052,29 +1052,29 @@ void x87_fsubr_st_sti(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fsubr_sti_st(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsubr_sti_st(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1085,29 +1085,29 @@ void x87_fsubr_sti_st(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, i, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(i, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fsubrp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsubrp(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1118,37 +1118,37 @@ void x87_fsubrp(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(i, result, TRUE);
+ x87_inc_stack();
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fisubr_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fisubr_m32int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
floatx80 a = int32_to_floatx80(m32int);
floatx80 b = ST(0);
@@ -1156,34 +1156,34 @@ void x87_fisubr_m32int(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 19);
+ CYCLES(19);
}
-void x87_fisubr_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fisubr_m16int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT16 m16int = READ16(cpustate, ea);
+ INT16 m16int = READ16(ea);
floatx80 a = int32_to_floatx80(m16int);
floatx80 b = ST(0);
@@ -1191,19 +1191,19 @@ void x87_fisubr_m16int(i386_state *cpustate, UINT8 modrm)
if ((floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
|| (floatx80_is_inf(a) && floatx80_is_inf(b) && ((a.high ^ b.high) & 0x8000)))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_sub(cpustate, a, b);
+ result = x87_sub(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 20);
+ CYCLES(20);
}
@@ -1213,84 +1213,84 @@ void x87_fisubr_m16int(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fdiv_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdiv_m32real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
floatx80 a = ST(0);
floatx80 b = float32_to_floatx80(m32real);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fdiv_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdiv_m64real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
floatx80 a = ST(0);
floatx80 b = float64_to_floatx80(m64real);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fdiv_st_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdiv_st_sti(UINT8 modrm)
{
int i = modrm & 7;
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1300,32 +1300,32 @@ void x87_fdiv_st_sti(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 0, result, TRUE);
+ x87_write_stack(0, result, TRUE);
}
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fdiv_sti_st(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdiv_sti_st(UINT8 modrm)
{
int i = modrm & 7;
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1335,32 +1335,32 @@ void x87_fdiv_sti_st(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, result, TRUE);
+ x87_write_stack(i, result, TRUE);
}
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fdivp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdivp(UINT8 modrm)
{
int i = modrm & 7;
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1370,93 +1370,93 @@ void x87_fdivp(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(i, result, TRUE);
+ x87_inc_stack();
}
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fidiv_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fidiv_m32int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m32int);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fidiv_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fidiv_m16int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT16 m16int = READ32(cpustate, ea);
+ INT16 m16int = READ32(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m16int);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
@@ -1466,84 +1466,84 @@ void x87_fidiv_m16int(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fdivr_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdivr_m32real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
floatx80 a = float32_to_floatx80(m32real);
floatx80 b = ST(0);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fdivr_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdivr_m64real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
floatx80 a = float64_to_floatx80(m64real);
floatx80 b = ST(0);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fdivr_st_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdivr_st_sti(UINT8 modrm)
{
int i = modrm & 7;
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1553,32 +1553,32 @@ void x87_fdivr_st_sti(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 0, result, TRUE);
+ x87_write_stack(0, result, TRUE);
}
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fdivr_sti_st(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdivr_sti_st(UINT8 modrm)
{
int i = modrm & 7;
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1588,32 +1588,32 @@ void x87_fdivr_sti_st(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, result, TRUE);
+ x87_write_stack(i, result, TRUE);
}
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fdivrp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdivrp(UINT8 modrm)
{
int i = modrm & 7;
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1623,94 +1623,94 @@ void x87_fdivrp(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(i, result, TRUE);
+ x87_inc_stack();
}
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fidivr_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fidivr_m32int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
floatx80 a = int32_to_floatx80(m32int);
floatx80 b = ST(0);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
-void x87_fidivr_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fidivr_m16int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT16 m16int = READ32(cpustate, ea);
+ INT16 m16int = READ32(ea);
floatx80 a = int32_to_floatx80(m16int);
floatx80 b = ST(0);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_div(cpustate, a, b);
+ result = x87_div(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
// 73, 62, 35
- CYCLES(cpustate, 73);
+ CYCLES(73);
}
@@ -1720,82 +1720,82 @@ void x87_fidivr_m16int(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fmul_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fmul_m32real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
floatx80 a = ST(0);
floatx80 b = float32_to_floatx80(m32real);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_mul(cpustate, a, b);
+ result = x87_mul(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 11);
+ CYCLES(11);
}
-void x87_fmul_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fmul_m64real(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
floatx80 a = ST(0);
floatx80 b = float64_to_floatx80(m64real);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_mul(cpustate, a, b);
+ result = x87_mul(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 14);
+ CYCLES(14);
}
-void x87_fmul_st_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fmul_st_sti(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1805,29 +1805,29 @@ void x87_fmul_st_sti(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_mul(cpustate, a, b);
+ result = x87_mul(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 16);
+ CYCLES(16);
}
-void x87_fmul_sti_st(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fmul_sti_st(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1837,29 +1837,29 @@ void x87_fmul_sti_st(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_mul(cpustate, a, b);
+ result = x87_mul(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, i, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(i, result, TRUE);
- CYCLES(cpustate, 16);
+ CYCLES(16);
}
-void x87_fmulp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fmulp(UINT8 modrm)
{
floatx80 result;
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1869,90 +1869,90 @@ void x87_fmulp(i386_state *cpustate, UINT8 modrm)
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_mul(cpustate, a, b);
+ result = x87_mul(a, b);
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(i, result, TRUE);
+ x87_inc_stack();
}
- CYCLES(cpustate, 16);
+ CYCLES(16);
}
-void x87_fimul_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fimul_m32int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m32int);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_mul(cpustate, a, b);
+ result = x87_mul(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 22);
+ CYCLES(22);
}
-void x87_fimul_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fimul_m16int(UINT8 modrm)
{
floatx80 result;
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
{
- INT16 m16int = READ16(cpustate, ea);
+ INT16 m16int = READ16(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m16int);
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
{
- result = x87_mul(cpustate, a, b);
+ result = x87_mul(a, b);
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 22);
+ CYCLES(22);
}
@@ -1962,13 +1962,13 @@ void x87_fimul_m16int(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fprem(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fprem(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -1976,25 +1976,25 @@ void x87_fprem(i386_state *cpustate, UINT8 modrm)
floatx80 a = ST(0);
floatx80 b = ST(1);
- cpustate->x87_sw &= ~X87_SW_C0;
+ m_x87_sw &= ~X87_SW_C0;
// TODO: Implement Cx bits
result = floatx80_rem(a, b);
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 84);
+ CYCLES(84);
}
-void x87_fprem1(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fprem1(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2002,25 +2002,25 @@ void x87_fprem1(i386_state *cpustate, UINT8 modrm)
floatx80 a = ST(0);
floatx80 b = ST(1);
- cpustate->x87_sw &= ~X87_SW_C0;
+ m_x87_sw &= ~X87_SW_C0;
// TODO: Implement Cx bits
result = floatx80_rem(a, b);
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 94);
+ CYCLES(94);
}
-void x87_fsqrt(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsqrt(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2030,7 +2030,7 @@ void x87_fsqrt(i386_state *cpustate, UINT8 modrm)
if ((!floatx80_is_zero(value) && (value.high & 0x8000)) ||
floatx80_is_denormal(value))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
@@ -2039,10 +2039,10 @@ void x87_fsqrt(i386_state *cpustate, UINT8 modrm)
}
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
/*************************************
@@ -2051,13 +2051,13 @@ void x87_fsqrt(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_f2xm1(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_f2xm1(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2068,21 +2068,21 @@ void x87_f2xm1(i386_state *cpustate, UINT8 modrm)
result = double_to_fx80(res);
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 0, result, TRUE);
+ x87_write_stack(0, result, TRUE);
}
- CYCLES(cpustate, 242);
+ CYCLES(242);
}
-void x87_fyl2x(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fyl2x(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2092,7 +2092,7 @@ void x87_fyl2x(i386_state *cpustate, UINT8 modrm)
if (x.high & 0x8000)
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
result = fx80_inan;
}
else
@@ -2104,22 +2104,22 @@ void x87_fyl2x(i386_state *cpustate, UINT8 modrm)
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 1, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(1, result, TRUE);
+ x87_inc_stack();
}
- CYCLES(cpustate, 250);
+ CYCLES(250);
}
-void x87_fyl2xp1(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fyl2xp1(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2133,28 +2133,28 @@ void x87_fyl2xp1(i386_state *cpustate, UINT8 modrm)
result = floatx80_mul(double_to_fx80(l2x1), y);
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 1, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(1, result, TRUE);
+ x87_inc_stack();
}
- CYCLES(cpustate, 313);
+ CYCLES(313);
}
-void x87_fptan(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fptan(UINT8 modrm)
{
floatx80 result1, result2;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result1 = fx80_inan;
result2 = fx80_inan;
}
else if (!X87_IS_ST_EMPTY(7))
{
- x87_set_stack_overflow(cpustate);
+ x87_set_stack_overflow();
result1 = fx80_inan;
result2 = fx80_inan;
}
@@ -2165,35 +2165,35 @@ void x87_fptan(i386_state *cpustate, UINT8 modrm)
#if 0 // TODO: Function produces bad values
if (floatx80_ftan(result1) != -1)
- cpustate->x87_sw &= ~X87_SW_C2;
+ m_x87_sw &= ~X87_SW_C2;
else
- cpustate->x87_sw |= X87_SW_C2;
+ m_x87_sw |= X87_SW_C2;
#else
double x = fx80_to_double(result1);
x = tan(x);
result1 = double_to_fx80(x);
- cpustate->x87_sw &= ~X87_SW_C2;
+ m_x87_sw &= ~X87_SW_C2;
#endif
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 0, result1, TRUE);
- x87_dec_stack(cpustate);
- x87_write_stack(cpustate, 0, result2, TRUE);
+ x87_write_stack(0, result1, TRUE);
+ x87_dec_stack();
+ x87_write_stack(0, result2, TRUE);
}
- CYCLES(cpustate, 244);
+ CYCLES(244);
}
-void x87_fpatan(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fpatan(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2203,22 +2203,22 @@ void x87_fpatan(i386_state *cpustate, UINT8 modrm)
result = double_to_fx80(val);
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 1, result, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(1, result, TRUE);
+ x87_inc_stack();
}
- CYCLES(cpustate, 289);
+ CYCLES(289);
}
-void x87_fsin(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsin(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2227,31 +2227,31 @@ void x87_fsin(i386_state *cpustate, UINT8 modrm)
#if 0 // TODO: Function produces bad values
if (floatx80_fsin(result) != -1)
- cpustate->x87_sw &= ~X87_SW_C2;
+ m_x87_sw &= ~X87_SW_C2;
else
- cpustate->x87_sw |= X87_SW_C2;
+ m_x87_sw |= X87_SW_C2;
#else
double x = fx80_to_double(result);
x = sin(x);
result = double_to_fx80(x);
- cpustate->x87_sw &= ~X87_SW_C2;
+ m_x87_sw &= ~X87_SW_C2;
#endif
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 241);
+ CYCLES(241);
}
-void x87_fcos(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcos(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2260,36 +2260,36 @@ void x87_fcos(i386_state *cpustate, UINT8 modrm)
#if 0 // TODO: Function produces bad values
if (floatx80_fcos(result) != -1)
- cpustate->x87_sw &= ~X87_SW_C2;
+ m_x87_sw &= ~X87_SW_C2;
else
- cpustate->x87_sw |= X87_SW_C2;
+ m_x87_sw |= X87_SW_C2;
#else
double x = fx80_to_double(result);
x = cos(x);
result = double_to_fx80(x);
- cpustate->x87_sw &= ~X87_SW_C2;
+ m_x87_sw &= ~X87_SW_C2;
#endif
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, result, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, result, TRUE);
- CYCLES(cpustate, 241);
+ CYCLES(241);
}
-void x87_fsincos(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsincos(UINT8 modrm)
{
floatx80 s_result, c_result;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
s_result = c_result = fx80_inan;
}
else if (!X87_IS_ST_EMPTY(7))
{
- x87_set_stack_overflow(cpustate);
+ x87_set_stack_overflow();
s_result = c_result = fx80_inan;
}
else
@@ -2300,9 +2300,9 @@ void x87_fsincos(i386_state *cpustate, UINT8 modrm)
#if 0 // TODO: Function produces bad values
if (sf_fsincos(s_result, &s_result, &c_result) != -1)
- cpustate->x87_sw &= ~X87_SW_C2;
+ m_x87_sw &= ~X87_SW_C2;
else
- cpustate->x87_sw |= X87_SW_C2;
+ m_x87_sw |= X87_SW_C2;
#else
double s = fx80_to_double(s_result);
double c = fx80_to_double(c_result);
@@ -2312,18 +2312,18 @@ void x87_fsincos(i386_state *cpustate, UINT8 modrm)
s_result = double_to_fx80(s);
c_result = double_to_fx80(c);
- cpustate->x87_sw &= ~X87_SW_C2;
+ m_x87_sw &= ~X87_SW_C2;
#endif
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 0, s_result, TRUE);
- x87_dec_stack(cpustate);
- x87_write_stack(cpustate, 0, c_result, TRUE);
+ x87_write_stack(0, s_result, TRUE);
+ x87_dec_stack();
+ x87_write_stack(0, c_result, TRUE);
}
- CYCLES(cpustate, 291);
+ CYCLES(291);
}
@@ -2333,22 +2333,22 @@ void x87_fsincos(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fld_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fld_m32real(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- if (x87_dec_stack(cpustate))
+ UINT32 ea = GetEA(modrm, 0);
+ if (x87_dec_stack())
{
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
value = float32_to_floatx80(m32real);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
if (floatx80_is_signaling_nan(value) || floatx80_is_denormal(value))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
value = fx80_inan;
}
}
@@ -2357,28 +2357,28 @@ void x87_fld_m32real(i386_state *cpustate, UINT8 modrm)
value = fx80_inan;
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fld_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fld_m64real(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- if (x87_dec_stack(cpustate))
+ UINT32 ea = GetEA(modrm, 0);
+ if (x87_dec_stack())
{
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
value = float64_to_floatx80(m64real);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
if (floatx80_is_signaling_nan(value) || floatx80_is_denormal(value))
{
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
value = fx80_inan;
}
}
@@ -2387,40 +2387,40 @@ void x87_fld_m64real(i386_state *cpustate, UINT8 modrm)
value = fx80_inan;
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fld_m80real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fld_m80real(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- if (x87_dec_stack(cpustate))
+ UINT32 ea = GetEA(modrm, 0);
+ if (x87_dec_stack())
{
- cpustate->x87_sw &= ~X87_SW_C1;
- value = READ80(cpustate, ea);
+ m_x87_sw &= ~X87_SW_C1;
+ value = READ80(ea);
}
else
{
value = fx80_inan;
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 6);
+ CYCLES(6);
}
-void x87_fld_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fld_sti(UINT8 modrm)
{
floatx80 value;
- if (x87_dec_stack(cpustate))
+ if (x87_dec_stack())
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST((modrm + 1) & 7);
}
else
@@ -2428,98 +2428,98 @@ void x87_fld_sti(i386_state *cpustate, UINT8 modrm)
value = fx80_inan;
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fild_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fild_m16int(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- if (!x87_dec_stack(cpustate))
+ UINT32 ea = GetEA(modrm, 0);
+ if (!x87_dec_stack())
{
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
- INT16 m16int = READ16(cpustate, ea);
+ INT16 m16int = READ16(ea);
value = int32_to_floatx80(m16int);
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 13);
+ CYCLES(13);
}
-void x87_fild_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fild_m32int(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- if (!x87_dec_stack(cpustate))
+ UINT32 ea = GetEA(modrm, 0);
+ if (!x87_dec_stack())
{
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
value = int32_to_floatx80(m32int);
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 9);
+ CYCLES(9);
}
-void x87_fild_m64int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fild_m64int(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- if (!x87_dec_stack(cpustate))
+ UINT32 ea = GetEA(modrm, 0);
+ if (!x87_dec_stack())
{
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
- INT64 m64int = READ64(cpustate, ea);
+ INT64 m64int = READ64(ea);
value = int64_to_floatx80(m64int);
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 10);
+ CYCLES(10);
}
-void x87_fbld(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fbld(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 0);
- if (!x87_dec_stack(cpustate))
+ UINT32 ea = GetEA(modrm, 0);
+ if (!x87_dec_stack())
{
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
UINT64 m64val = 0;
UINT16 sign;
- value = READ80(cpustate, ea);
+ value = READ80(ea);
sign = value.high & 0x8000;
m64val += ((value.high >> 4) & 0xf) * 10;
@@ -2535,10 +2535,10 @@ void x87_fbld(i386_state *cpustate, UINT8 modrm)
value.high |= sign;
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 75);
+ CYCLES(75);
}
@@ -2548,188 +2548,188 @@ void x87_fbld(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fst_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fst_m32real(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 1);
+ UINT32 ea = GetEA(modrm, 1);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
UINT32 m32real = floatx80_to_float32(value);
- WRITE32(cpustate, ea, m32real);
+ WRITE32(ea, m32real);
}
- CYCLES(cpustate, 7);
+ CYCLES(7);
}
-void x87_fst_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fst_m64real(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 1);
+ UINT32 ea = GetEA(modrm, 1);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
UINT64 m64real = floatx80_to_float64(value);
- WRITE64(cpustate, ea, m64real);
+ WRITE64(ea, m64real);
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fst_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fst_sti(UINT8 modrm)
{
int i = modrm & 7;
floatx80 value;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, i, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(i, value, TRUE);
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fstp_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fstp_m32real(UINT8 modrm)
{
floatx80 value;
- UINT32 ea = GetEA(cpustate, modrm, 1);
+ UINT32 ea = GetEA(modrm, 1);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
UINT32 m32real = floatx80_to_float32(value);
- WRITE32(cpustate, ea, m32real);
- x87_inc_stack(cpustate);
+ WRITE32(ea, m32real);
+ x87_inc_stack();
}
- CYCLES(cpustate, 7);
+ CYCLES(7);
}
-void x87_fstp_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fstp_m64real(UINT8 modrm)
{
floatx80 value;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
}
- UINT32 ea = GetEA(cpustate, modrm, 1);
- if (x87_check_exceptions(cpustate))
+ UINT32 ea = GetEA(modrm, 1);
+ if (x87_check_exceptions())
{
UINT64 m64real = floatx80_to_float64(value);
- WRITE64(cpustate, ea, m64real);
- x87_inc_stack(cpustate);
+ WRITE64(ea, m64real);
+ x87_inc_stack();
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fstp_m80real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fstp_m80real(UINT8 modrm)
{
floatx80 value;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
}
- UINT32 ea = GetEA(cpustate, modrm, 1);
- if (x87_check_exceptions(cpustate))
+ UINT32 ea = GetEA(modrm, 1);
+ if (x87_check_exceptions())
{
- WRITE80(cpustate, ea, value);
- x87_inc_stack(cpustate);
+ WRITE80(ea, value);
+ x87_inc_stack();
}
- CYCLES(cpustate, 6);
+ CYCLES(6);
}
-void x87_fstp_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fstp_sti(UINT8 modrm)
{
int i = modrm & 7;
floatx80 value;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, i, value, TRUE);
- x87_inc_stack(cpustate);
+ x87_write_stack(i, value, TRUE);
+ x87_inc_stack();
}
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fist_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fist_m16int(UINT8 modrm)
{
INT16 m16int;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
m16int = -32768;
}
else
@@ -2739,7 +2739,7 @@ void x87_fist_m16int(i386_state *cpustate, UINT8 modrm)
floatx80 lowerLim = int32_to_floatx80(-32768);
floatx80 upperLim = int32_to_floatx80(32767);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
if (!floatx80_lt(fx80, lowerLim) && floatx80_le(fx80, upperLim))
m16int = floatx80_to_int32(fx80);
@@ -2747,22 +2747,22 @@ void x87_fist_m16int(i386_state *cpustate, UINT8 modrm)
m16int = -32768;
}
- UINT32 ea = GetEA(cpustate, modrm, 1);
- if (x87_check_exceptions(cpustate))
+ UINT32 ea = GetEA(modrm, 1);
+ if (x87_check_exceptions())
{
- WRITE16(cpustate, ea, m16int);
+ WRITE16(ea, m16int);
}
- CYCLES(cpustate, 29);
+ CYCLES(29);
}
-void x87_fist_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fist_m32int(UINT8 modrm)
{
INT32 m32int;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
m32int = 0x80000000;
}
else
@@ -2772,7 +2772,7 @@ void x87_fist_m32int(i386_state *cpustate, UINT8 modrm)
floatx80 lowerLim = int32_to_floatx80(0x80000000);
floatx80 upperLim = int32_to_floatx80(0x7fffffff);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
if (!floatx80_lt(fx80, lowerLim) && floatx80_le(fx80, upperLim))
m32int = floatx80_to_int32(fx80);
@@ -2780,22 +2780,22 @@ void x87_fist_m32int(i386_state *cpustate, UINT8 modrm)
m32int = 0x80000000;
}
- UINT32 ea = GetEA(cpustate, modrm, 1);
- if (x87_check_exceptions(cpustate))
+ UINT32 ea = GetEA(modrm, 1);
+ if (x87_check_exceptions())
{
- WRITE32(cpustate, ea, m32int);
+ WRITE32(ea, m32int);
}
- CYCLES(cpustate, 28);
+ CYCLES(28);
}
-void x87_fistp_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fistp_m16int(UINT8 modrm)
{
INT16 m16int;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
m16int = (UINT16)0x8000;
}
else
@@ -2805,7 +2805,7 @@ void x87_fistp_m16int(i386_state *cpustate, UINT8 modrm)
floatx80 lowerLim = int32_to_floatx80(-32768);
floatx80 upperLim = int32_to_floatx80(32767);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
if (!floatx80_lt(fx80, lowerLim) && floatx80_le(fx80, upperLim))
m16int = floatx80_to_int32(fx80);
@@ -2813,23 +2813,23 @@ void x87_fistp_m16int(i386_state *cpustate, UINT8 modrm)
m16int = (UINT16)0x8000;
}
- UINT32 ea = GetEA(cpustate, modrm, 1);
- if (x87_check_exceptions(cpustate))
+ UINT32 ea = GetEA(modrm, 1);
+ if (x87_check_exceptions())
{
- WRITE16(cpustate, ea, m16int);
- x87_inc_stack(cpustate);
+ WRITE16(ea, m16int);
+ x87_inc_stack();
}
- CYCLES(cpustate, 29);
+ CYCLES(29);
}
-void x87_fistp_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fistp_m32int(UINT8 modrm)
{
INT32 m32int;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
m32int = 0x80000000;
}
else
@@ -2839,7 +2839,7 @@ void x87_fistp_m32int(i386_state *cpustate, UINT8 modrm)
floatx80 lowerLim = int32_to_floatx80(0x80000000);
floatx80 upperLim = int32_to_floatx80(0x7fffffff);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
if (!floatx80_lt(fx80, lowerLim) && floatx80_le(fx80, upperLim))
m32int = floatx80_to_int32(fx80);
@@ -2847,23 +2847,23 @@ void x87_fistp_m32int(i386_state *cpustate, UINT8 modrm)
m32int = 0x80000000;
}
- UINT32 ea = GetEA(cpustate, modrm, 1);
- if (x87_check_exceptions(cpustate))
+ UINT32 ea = GetEA(modrm, 1);
+ if (x87_check_exceptions())
{
- WRITE32(cpustate, ea, m32int);
- x87_inc_stack(cpustate);
+ WRITE32(ea, m32int);
+ x87_inc_stack();
}
- CYCLES(cpustate, 29);
+ CYCLES(29);
}
-void x87_fistp_m64int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fistp_m64int(UINT8 modrm)
{
INT64 m64int;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
m64int = U64(0x8000000000000000);
}
else
@@ -2873,7 +2873,7 @@ void x87_fistp_m64int(i386_state *cpustate, UINT8 modrm)
floatx80 lowerLim = int64_to_floatx80(U64(0x8000000000000000));
floatx80 upperLim = int64_to_floatx80(U64(0x7fffffffffffffff));
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
if (!floatx80_lt(fx80, lowerLim) && floatx80_le(fx80, upperLim))
m64int = floatx80_to_int64(fx80);
@@ -2881,23 +2881,23 @@ void x87_fistp_m64int(i386_state *cpustate, UINT8 modrm)
m64int = U64(0x8000000000000000);
}
- UINT32 ea = GetEA(cpustate, modrm, 1);
- if (x87_check_exceptions(cpustate))
+ UINT32 ea = GetEA(modrm, 1);
+ if (x87_check_exceptions())
{
- WRITE64(cpustate, ea, m64int);
- x87_inc_stack(cpustate);
+ WRITE64(ea, m64int);
+ x87_inc_stack();
}
- CYCLES(cpustate, 29);
+ CYCLES(29);
}
-void x87_fbstp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fbstp(UINT8 modrm)
{
floatx80 result;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
result = fx80_inan;
}
else
@@ -2916,14 +2916,14 @@ void x87_fbstp(i386_state *cpustate, UINT8 modrm)
result.high |= ST(0).high & 0x8000;
}
- UINT32 ea = GetEA(cpustate, modrm, 1);
- if (x87_check_exceptions(cpustate))
+ UINT32 ea = GetEA(modrm, 1);
+ if (x87_check_exceptions())
{
- WRITE80(cpustate, ea, result);
- x87_inc_stack(cpustate);
+ WRITE80(ea, result);
+ x87_inc_stack();
}
- CYCLES(cpustate, 175);
+ CYCLES(175);
}
@@ -2933,14 +2933,14 @@ void x87_fbstp(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fld1(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fld1(UINT8 modrm)
{
floatx80 value;
int tag;
- if (x87_dec_stack(cpustate))
+ if (x87_dec_stack())
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = fx80_one;
tag = X87_TW_VALID;
}
@@ -2950,21 +2950,21 @@ void x87_fld1(i386_state *cpustate, UINT8 modrm)
tag = X87_TW_SPECIAL;
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_set_tag(cpustate, ST_TO_PHYS(0), tag);
- x87_write_stack(cpustate, 0, value, FALSE);
+ x87_set_tag(ST_TO_PHYS(0), tag);
+ x87_write_stack(0, value, FALSE);
}
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fldl2t(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fldl2t(UINT8 modrm)
{
floatx80 value;
int tag;
- if (x87_dec_stack(cpustate))
+ if (x87_dec_stack())
{
tag = X87_TW_VALID;
value.high = 0x4000;
@@ -2974,7 +2974,7 @@ void x87_fldl2t(i386_state *cpustate, UINT8 modrm)
else
value.low = U64(0xd49a784bcd1b8afe);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
}
else
{
@@ -2982,21 +2982,21 @@ void x87_fldl2t(i386_state *cpustate, UINT8 modrm)
tag = X87_TW_SPECIAL;
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_set_tag(cpustate, ST_TO_PHYS(0), tag);
- x87_write_stack(cpustate, 0, value, FALSE);
+ x87_set_tag(ST_TO_PHYS(0), tag);
+ x87_write_stack(0, value, FALSE);
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fldl2e(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fldl2e(UINT8 modrm)
{
floatx80 value;
int tag;
- if (x87_dec_stack(cpustate))
+ if (x87_dec_stack())
{
int rc = X87_RC;
tag = X87_TW_VALID;
@@ -3007,7 +3007,7 @@ void x87_fldl2e(i386_state *cpustate, UINT8 modrm)
else
value.low = U64(0xb8aa3b295c17f0bb);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
}
else
{
@@ -3015,21 +3015,21 @@ void x87_fldl2e(i386_state *cpustate, UINT8 modrm)
tag = X87_TW_SPECIAL;
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_set_tag(cpustate, ST_TO_PHYS(0), tag);
- x87_write_stack(cpustate, 0, value, FALSE);
+ x87_set_tag(ST_TO_PHYS(0), tag);
+ x87_write_stack(0, value, FALSE);
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fldpi(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fldpi(UINT8 modrm)
{
floatx80 value;
int tag;
- if (x87_dec_stack(cpustate))
+ if (x87_dec_stack())
{
int rc = X87_RC;
tag = X87_TW_VALID;
@@ -3040,7 +3040,7 @@ void x87_fldpi(i386_state *cpustate, UINT8 modrm)
else
value.low = U64(0xc90fdaa22168c234);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
}
else
{
@@ -3048,21 +3048,21 @@ void x87_fldpi(i386_state *cpustate, UINT8 modrm)
tag = X87_TW_SPECIAL;
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_set_tag(cpustate, ST_TO_PHYS(0), tag);
- x87_write_stack(cpustate, 0, value, FALSE);
+ x87_set_tag(ST_TO_PHYS(0), tag);
+ x87_write_stack(0, value, FALSE);
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fldlg2(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fldlg2(UINT8 modrm)
{
floatx80 value;
int tag;
- if (x87_dec_stack(cpustate))
+ if (x87_dec_stack())
{
int rc = X87_RC;
tag = X87_TW_VALID;
@@ -3073,7 +3073,7 @@ void x87_fldlg2(i386_state *cpustate, UINT8 modrm)
else
value.low = U64(0x9a209a84fbcff798);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
}
else
{
@@ -3081,21 +3081,21 @@ void x87_fldlg2(i386_state *cpustate, UINT8 modrm)
tag = X87_TW_SPECIAL;
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_set_tag(cpustate, ST_TO_PHYS(0), tag);
- x87_write_stack(cpustate, 0, value, FALSE);
+ x87_set_tag(ST_TO_PHYS(0), tag);
+ x87_write_stack(0, value, FALSE);
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fldln2(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fldln2(UINT8 modrm)
{
floatx80 value;
int tag;
- if (x87_dec_stack(cpustate))
+ if (x87_dec_stack())
{
int rc = X87_RC;
tag = X87_TW_VALID;
@@ -3106,7 +3106,7 @@ void x87_fldln2(i386_state *cpustate, UINT8 modrm)
else
value.low = U64(0xb17217f7d1cf79ab);
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
}
else
{
@@ -3114,25 +3114,25 @@ void x87_fldln2(i386_state *cpustate, UINT8 modrm)
tag = X87_TW_SPECIAL;
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_set_tag(cpustate, ST_TO_PHYS(0), tag);
- x87_write_stack(cpustate, 0, value, FALSE);
+ x87_set_tag(ST_TO_PHYS(0), tag);
+ x87_write_stack(0, value, FALSE);
}
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_fldz(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fldz(UINT8 modrm)
{
floatx80 value;
int tag;
- if (x87_dec_stack(cpustate))
+ if (x87_dec_stack())
{
value = fx80_zero;
tag = X87_TW_ZERO;
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
}
else
{
@@ -3140,13 +3140,13 @@ void x87_fldz(i386_state *cpustate, UINT8 modrm)
tag = X87_TW_SPECIAL;
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_set_tag(cpustate, ST_TO_PHYS(0), tag);
- x87_write_stack(cpustate, 0, value, FALSE);
+ x87_set_tag(ST_TO_PHYS(0), tag);
+ x87_write_stack(0, value, FALSE);
}
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
@@ -3156,81 +3156,81 @@ void x87_fldz(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fnop(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fnop(UINT8 modrm)
{
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fchs(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fchs(UINT8 modrm)
{
floatx80 value;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
value.high ^= 0x8000;
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, FALSE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, FALSE);
- CYCLES(cpustate, 6);
+ CYCLES(6);
}
-void x87_fabs(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fabs(UINT8 modrm)
{
floatx80 value;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
value.high &= 0x7fff;
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, FALSE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, FALSE);
- CYCLES(cpustate, 6);
+ CYCLES(6);
}
-void x87_fscale(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fscale(UINT8 modrm)
{
floatx80 value;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = ST(0);
// Set the rounding mode to truncate
- UINT16 old_cw = cpustate->x87_cw;
+ UINT16 old_cw = m_x87_cw;
UINT16 new_cw = (old_cw & ~(X87_CW_RC_MASK << X87_CW_RC_SHIFT)) | (X87_CW_RC_ZERO << X87_CW_RC_SHIFT);
- x87_write_cw(cpustate, new_cw);
+ x87_write_cw(new_cw);
// Interpret ST(1) as an integer
UINT32 st1 = floatx80_to_int32(floatx80_round_to_int(ST(1)));
// Restore the rounding mode
- x87_write_cw(cpustate, old_cw);
+ x87_write_cw(old_cw);
// Get the unbiased exponent of ST(0)
INT16 exp = (ST(0).high & 0x7fff) - 0x3fff;
@@ -3242,46 +3242,46 @@ void x87_fscale(i386_state *cpustate, UINT8 modrm)
value.high = (value.high & ~0x7fff) + exp;
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, FALSE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, FALSE);
- CYCLES(cpustate, 31);
+ CYCLES(31);
}
-void x87_frndint(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_frndint(UINT8 modrm)
{
floatx80 value;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
value = fx80_inan;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
value = floatx80_round_to_int(ST(0));
}
- if (x87_check_exceptions(cpustate))
- x87_write_stack(cpustate, 0, value, TRUE);
+ if (x87_check_exceptions())
+ x87_write_stack(0, value, TRUE);
- CYCLES(cpustate, 21);
+ CYCLES(21);
}
-void x87_fxtract(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fxtract(UINT8 modrm)
{
floatx80 sig80, exp80;
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
sig80 = exp80 = fx80_inan;
}
else if (!X87_IS_ST_EMPTY(7))
{
- x87_set_stack_overflow(cpustate);
+ x87_set_stack_overflow();
sig80 = exp80 = fx80_inan;
}
else
@@ -3290,7 +3290,7 @@ void x87_fxtract(i386_state *cpustate, UINT8 modrm)
if (floatx80_eq(value, fx80_zero))
{
- cpustate->x87_sw |= X87_SW_ZE;
+ m_x87_sw |= X87_SW_ZE;
exp80 = fx80_ninf;
sig80 = fx80_zero;
@@ -3307,14 +3307,14 @@ void x87_fxtract(i386_state *cpustate, UINT8 modrm)
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_write_stack(cpustate, 0, exp80, TRUE);
- x87_dec_stack(cpustate);
- x87_write_stack(cpustate, 0, sig80, TRUE);
+ x87_write_stack(0, exp80, TRUE);
+ x87_dec_stack();
+ x87_write_stack(0, sig80, TRUE);
}
- CYCLES(cpustate, 21);
+ CYCLES(21);
}
/*************************************
@@ -3323,526 +3323,526 @@ void x87_fxtract(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_ftst(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_ftst(UINT8 modrm)
{
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
if (floatx80_is_nan(ST(0)))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(ST(0), fx80_zero))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(ST(0), fx80_zero))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fxam(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fxam(UINT8 modrm)
{
floatx80 value = ST(0);
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
// TODO: Unsupported and denormal values
if (X87_IS_ST_EMPTY(0))
{
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C0;
+ m_x87_sw |= X87_SW_C3 | X87_SW_C0;
}
else if (floatx80_is_zero(value))
{
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
}
if (floatx80_is_nan(value))
{
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
else if (floatx80_is_inf(value))
{
- cpustate->x87_sw |= X87_SW_C2 | X87_SW_C0;
+ m_x87_sw |= X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw |= X87_SW_C2;
+ m_x87_sw |= X87_SW_C2;
}
if (value.high & 0x8000)
- cpustate->x87_sw |= X87_SW_C1;
+ m_x87_sw |= X87_SW_C1;
- CYCLES(cpustate, 8);
+ CYCLES(8);
}
-void x87_ficom_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_ficom_m16int(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
- INT16 m16int = READ16(cpustate, ea);
+ INT16 m16int = READ16(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m16int);
if (floatx80_is_nan(a))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate, 16);
+ CYCLES(16);
}
-void x87_ficom_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_ficom_m32int(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m32int);
if (floatx80_is_nan(a))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate, 15);
+ CYCLES(15);
}
-void x87_ficomp_m16int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_ficomp_m16int(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
- INT16 m16int = READ16(cpustate, ea);
+ INT16 m16int = READ16(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m16int);
if (floatx80_is_nan(a))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- if (x87_check_exceptions(cpustate))
- x87_inc_stack(cpustate);
+ if (x87_check_exceptions())
+ x87_inc_stack();
- CYCLES(cpustate, 16);
+ CYCLES(16);
}
-void x87_ficomp_m32int(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_ficomp_m32int(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
- INT32 m32int = READ32(cpustate, ea);
+ INT32 m32int = READ32(ea);
floatx80 a = ST(0);
floatx80 b = int32_to_floatx80(m32int);
if (floatx80_is_nan(a))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- if (x87_check_exceptions(cpustate))
- x87_inc_stack(cpustate);
+ if (x87_check_exceptions())
+ x87_inc_stack();
- CYCLES(cpustate, 15);
+ CYCLES(15);
}
-void x87_fcom_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcom_m32real(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
floatx80 a = ST(0);
floatx80 b = float32_to_floatx80(m32real);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fcom_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcom_m64real(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
floatx80 a = ST(0);
floatx80 b = float64_to_floatx80(m64real);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fcom_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcom_sti(UINT8 modrm)
{
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
floatx80 a = ST(0);
floatx80 b = ST(i);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fcomp_m32real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcomp_m32real(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
- UINT32 m32real = READ32(cpustate, ea);
+ UINT32 m32real = READ32(ea);
floatx80 a = ST(0);
floatx80 b = float32_to_floatx80(m32real);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- if (x87_check_exceptions(cpustate))
- x87_inc_stack(cpustate);
+ if (x87_check_exceptions())
+ x87_inc_stack();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fcomp_m64real(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcomp_m64real(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
if (X87_IS_ST_EMPTY(0))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
- UINT64 m64real = READ64(cpustate, ea);
+ UINT64 m64real = READ64(ea);
floatx80 a = ST(0);
floatx80 b = float64_to_floatx80(m64real);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- if (x87_check_exceptions(cpustate))
- x87_inc_stack(cpustate);
+ if (x87_check_exceptions())
+ x87_inc_stack();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fcomp_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcomp_sti(UINT8 modrm)
{
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
floatx80 a = ST(0);
floatx80 b = ST(i);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- if (x87_check_exceptions(cpustate))
- x87_inc_stack(cpustate);
+ if (x87_check_exceptions())
+ x87_inc_stack();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fcomip_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcomip_sti(UINT8 modrm)
{
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
- cpustate->ZF = 1;
- cpustate->PF = 1;
- cpustate->CF = 1;
+ x87_set_stack_underflow();
+ m_ZF = 1;
+ m_PF = 1;
+ m_CF = 1;
}
else
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
floatx80 a = ST(0);
floatx80 b = ST(i);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->ZF = 1;
- cpustate->PF = 1;
- cpustate->CF = 1;
- cpustate->x87_sw |= X87_SW_IE;
+ m_ZF = 1;
+ m_PF = 1;
+ m_CF = 1;
+ m_x87_sw |= X87_SW_IE;
}
else
{
- cpustate->ZF = 0;
- cpustate->PF = 0;
- cpustate->CF = 0;
+ m_ZF = 0;
+ m_PF = 0;
+ m_CF = 0;
if (floatx80_eq(a, b))
- cpustate->ZF = 1;
+ m_ZF = 1;
if (floatx80_lt(a, b))
- cpustate->CF = 1;
+ m_CF = 1;
}
}
- if (x87_check_exceptions(cpustate))
- x87_inc_stack(cpustate);
+ if (x87_check_exceptions())
+ x87_inc_stack();
- CYCLES(cpustate, 4); // TODO: correct cycle count
+ CYCLES(4); // TODO: correct cycle count
}
-void x87_fcompp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fcompp(UINT8 modrm)
{
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
floatx80 a = ST(0);
floatx80 b = ST(1);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_inc_stack(cpustate);
- x87_inc_stack(cpustate);
+ x87_inc_stack();
+ x87_inc_stack();
}
- CYCLES(cpustate, 5);
+ CYCLES(5);
}
@@ -3852,121 +3852,121 @@ void x87_fcompp(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fucom_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fucom_sti(UINT8 modrm)
{
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
floatx80 a = ST(0);
floatx80 b = ST(i);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fucomp_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fucomp_sti(UINT8 modrm)
{
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(i))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
floatx80 a = ST(0);
floatx80 b = ST(i);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- if (x87_check_exceptions(cpustate))
- x87_inc_stack(cpustate);
+ if (x87_check_exceptions())
+ x87_inc_stack();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fucompp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fucompp(UINT8 modrm)
{
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
{
- x87_set_stack_underflow(cpustate);
- cpustate->x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
+ x87_set_stack_underflow();
+ m_x87_sw |= X87_SW_C3 | X87_SW_C2 | X87_SW_C0;
}
else
{
- cpustate->x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
+ m_x87_sw &= ~(X87_SW_C3 | X87_SW_C2 | X87_SW_C1 | X87_SW_C0);
floatx80 a = ST(0);
floatx80 b = ST(1);
if (floatx80_is_nan(a) || floatx80_is_nan(b))
{
- cpustate->x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
+ m_x87_sw |= X87_SW_C0 | X87_SW_C2 | X87_SW_C3;
if (floatx80_is_signaling_nan(a) || floatx80_is_signaling_nan(b))
- cpustate->x87_sw |= X87_SW_IE;
+ m_x87_sw |= X87_SW_IE;
}
else
{
if (floatx80_eq(a, b))
- cpustate->x87_sw |= X87_SW_C3;
+ m_x87_sw |= X87_SW_C3;
if (floatx80_lt(a, b))
- cpustate->x87_sw |= X87_SW_C0;
+ m_x87_sw |= X87_SW_C0;
}
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
- x87_inc_stack(cpustate);
- x87_inc_stack(cpustate);
+ x87_inc_stack();
+ x87_inc_stack();
}
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
@@ -3976,259 +3976,259 @@ void x87_fucompp(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-void x87_fdecstp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fdecstp(UINT8 modrm)
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
- x87_dec_stack(cpustate);
- x87_check_exceptions(cpustate);
+ x87_dec_stack();
+ x87_check_exceptions();
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fincstp(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fincstp(UINT8 modrm)
{
- cpustate->x87_sw &= ~X87_SW_C1;
+ m_x87_sw &= ~X87_SW_C1;
- x87_inc_stack(cpustate);
- x87_check_exceptions(cpustate);
+ x87_inc_stack();
+ x87_check_exceptions();
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fclex(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fclex(UINT8 modrm)
{
- cpustate->x87_sw &= ~0x80ff;
+ m_x87_sw &= ~0x80ff;
- CYCLES(cpustate, 7);
+ CYCLES(7);
}
-void x87_ffree(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_ffree(UINT8 modrm)
{
- x87_set_tag(cpustate, ST_TO_PHYS(modrm & 7), X87_TW_EMPTY);
+ x87_set_tag(ST_TO_PHYS(modrm & 7), X87_TW_EMPTY);
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_finit(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_finit(UINT8 modrm)
{
- x87_reset(cpustate);
+ x87_reset();
- CYCLES(cpustate, 17);
+ CYCLES(17);
}
-void x87_fldcw(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fldcw(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
- UINT16 cw = READ16(cpustate, ea);
+ UINT32 ea = GetEA(modrm, 0);
+ UINT16 cw = READ16(ea);
- x87_write_cw(cpustate, cw);
+ x87_write_cw(cw);
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fstcw(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fstcw(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 1);
- WRITE16(cpustate, ea, cpustate->x87_cw);
+ UINT32 ea = GetEA(modrm, 1);
+ WRITE16(ea, m_x87_cw);
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fldenv(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fldenv(UINT8 modrm)
{
// TODO: Pointers and selectors
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
- if (cpustate->operand_size)
+ if (m_operand_size)
{
// 32-bit real/protected mode
- x87_write_cw(cpustate, READ16(cpustate, ea));
- cpustate->x87_sw = READ16(cpustate, ea + 4);
- cpustate->x87_tw = READ16(cpustate, ea + 8);
+ x87_write_cw(READ16(ea));
+ m_x87_sw = READ16(ea + 4);
+ m_x87_tw = READ16(ea + 8);
}
else
{
// 16-bit real/protected mode
- x87_write_cw(cpustate, READ16(cpustate, ea));
- cpustate->x87_sw = READ16(cpustate, ea + 2);
- cpustate->x87_tw = READ16(cpustate, ea + 4);
+ x87_write_cw(READ16(ea));
+ m_x87_sw = READ16(ea + 2);
+ m_x87_tw = READ16(ea + 4);
}
- x87_check_exceptions(cpustate);
+ x87_check_exceptions();
- CYCLES(cpustate,(cpustate->cr[0] & 1) ? 34 : 44);
+ CYCLES((m_cr[0] & 1) ? 34 : 44);
}
-void x87_fstenv(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fstenv(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 1);
+ UINT32 ea = GetEA(modrm, 1);
// TODO: Pointers and selectors
- switch((cpustate->cr[0] & 1)|(cpustate->operand_size & 1)<<1)
+ switch((m_cr[0] & 1)|(m_operand_size & 1)<<1)
{
case 0: // 16-bit real mode
- WRITE16(cpustate, ea + 0, cpustate->x87_cw);
- WRITE16(cpustate, ea + 2, cpustate->x87_sw);
- WRITE16(cpustate, ea + 4, cpustate->x87_tw);
-// WRITE16(cpustate, ea + 6, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate, ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate, ea + 10, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate, ea + 12, (cpustate->fpu_inst_ptr & 0x0f0000) >> 4);
+ WRITE16(ea + 0, m_x87_cw);
+ WRITE16(ea + 2, m_x87_sw);
+ WRITE16(ea + 4, m_x87_tw);
+// WRITE16(ea + 6, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 10, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, (m_fpu_inst_ptr & 0x0f0000) >> 4);
break;
case 1: // 16-bit protected mode
- WRITE16(cpustate,ea + 0, cpustate->x87_cw);
- WRITE16(cpustate,ea + 2, cpustate->x87_sw);
- WRITE16(cpustate,ea + 4, cpustate->x87_tw);
-// WRITE16(cpustate,ea + 6, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate,ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate,ea + 10, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate,ea + 12, (cpustate->fpu_inst_ptr & 0x0f0000) >> 4);
+ WRITE16(ea + 0, m_x87_cw);
+ WRITE16(ea + 2, m_x87_sw);
+ WRITE16(ea + 4, m_x87_tw);
+// WRITE16(ea + 6, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 10, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, (m_fpu_inst_ptr & 0x0f0000) >> 4);
break;
case 2: // 32-bit real mode
- WRITE16(cpustate, ea + 0, cpustate->x87_cw);
- WRITE16(cpustate, ea + 4, cpustate->x87_sw);
- WRITE16(cpustate, ea + 8, cpustate->x87_tw);
-// WRITE16(cpustate, ea + 12, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate, ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate, ea + 20, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate, ea + 12, ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE32(cpustate, ea + 24, (cpustate->fpu_data_ptr >> 16) << 12);
+ WRITE16(ea + 0, m_x87_cw);
+ WRITE16(ea + 4, m_x87_sw);
+ WRITE16(ea + 8, m_x87_tw);
+// WRITE16(ea + 12, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 20, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE32(ea + 24, (m_fpu_data_ptr >> 16) << 12);
break;
case 3: // 32-bit protected mode
- WRITE16(cpustate, ea + 0, cpustate->x87_cw);
- WRITE16(cpustate, ea + 4, cpustate->x87_sw);
- WRITE16(cpustate, ea + 8, cpustate->x87_tw);
-// WRITE32(cpustate, ea + 12, cpustate->fpu_inst_ptr);
-// WRITE32(cpustate, ea + 16, cpustate->fpu_opcode);
-// WRITE32(cpustate, ea + 20, cpustate->fpu_data_ptr);
-// WRITE32(cpustate, ea + 24, cpustate->fpu_inst_ptr);
+ WRITE16(ea + 0, m_x87_cw);
+ WRITE16(ea + 4, m_x87_sw);
+ WRITE16(ea + 8, m_x87_tw);
+// WRITE32(ea + 12, m_fpu_inst_ptr);
+// WRITE32(ea + 16, m_fpu_opcode);
+// WRITE32(ea + 20, m_fpu_data_ptr);
+// WRITE32(ea + 24, m_fpu_inst_ptr);
break;
}
- CYCLES(cpustate,(cpustate->cr[0] & 1) ? 56 : 67);
+ CYCLES((m_cr[0] & 1) ? 56 : 67);
}
-void x87_fsave(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fsave(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 1);
+ UINT32 ea = GetEA(modrm, 1);
// TODO: Pointers and selectors
- switch((cpustate->cr[0] & 1)|(cpustate->operand_size & 1)<<1)
+ switch((m_cr[0] & 1)|(m_operand_size & 1)<<1)
{
case 0: // 16-bit real mode
- WRITE16(cpustate, ea + 0, cpustate->x87_cw);
- WRITE16(cpustate, ea + 2, cpustate->x87_sw);
- WRITE16(cpustate, ea + 4, cpustate->x87_tw);
-// WRITE16(cpustate, ea + 6, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate, ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate, ea + 10, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate, ea + 12, (cpustate->fpu_inst_ptr & 0x0f0000) >> 4);
+ WRITE16(ea + 0, m_x87_cw);
+ WRITE16(ea + 2, m_x87_sw);
+ WRITE16(ea + 4, m_x87_tw);
+// WRITE16(ea + 6, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 10, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, (m_fpu_inst_ptr & 0x0f0000) >> 4);
ea += 14;
break;
case 1: // 16-bit protected mode
- WRITE16(cpustate,ea + 0, cpustate->x87_cw);
- WRITE16(cpustate,ea + 2, cpustate->x87_sw);
- WRITE16(cpustate,ea + 4, cpustate->x87_tw);
-// WRITE16(cpustate,ea + 6, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate,ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate,ea + 10, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate,ea + 12, (cpustate->fpu_inst_ptr & 0x0f0000) >> 4);
+ WRITE16(ea + 0, m_x87_cw);
+ WRITE16(ea + 2, m_x87_sw);
+ WRITE16(ea + 4, m_x87_tw);
+// WRITE16(ea + 6, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 10, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, (m_fpu_inst_ptr & 0x0f0000) >> 4);
ea += 14;
break;
case 2: // 32-bit real mode
- WRITE16(cpustate, ea + 0, cpustate->x87_cw);
- WRITE16(cpustate, ea + 4, cpustate->x87_sw);
- WRITE16(cpustate, ea + 8, cpustate->x87_tw);
-// WRITE16(cpustate, ea + 12, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate, ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate, ea + 20, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate, ea + 12, ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE32(cpustate, ea + 24, (cpustate->fpu_data_ptr >> 16) << 12);
+ WRITE16(ea + 0, m_x87_cw);
+ WRITE16(ea + 4, m_x87_sw);
+ WRITE16(ea + 8, m_x87_tw);
+// WRITE16(ea + 12, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 20, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE32(ea + 24, (m_fpu_data_ptr >> 16) << 12);
ea += 28;
break;
case 3: // 32-bit protected mode
- WRITE16(cpustate, ea + 0, cpustate->x87_cw);
- WRITE16(cpustate, ea + 4, cpustate->x87_sw);
- WRITE16(cpustate, ea + 8, cpustate->x87_tw);
-// WRITE32(cpustate, ea + 12, cpustate->fpu_inst_ptr);
-// WRITE32(cpustate, ea + 16, cpustate->fpu_opcode);
-// WRITE32(cpustate, ea + 20, cpustate->fpu_data_ptr);
-// WRITE32(cpustate, ea + 24, cpustate->fpu_inst_ptr);
+ WRITE16(ea + 0, m_x87_cw);
+ WRITE16(ea + 4, m_x87_sw);
+ WRITE16(ea + 8, m_x87_tw);
+// WRITE32(ea + 12, m_fpu_inst_ptr);
+// WRITE32(ea + 16, m_fpu_opcode);
+// WRITE32(ea + 20, m_fpu_data_ptr);
+// WRITE32(ea + 24, m_fpu_inst_ptr);
ea += 28;
break;
}
for (int i = 0; i < 8; ++i)
- x87_write_stack(cpustate, i, READ80(cpustate, ea + i*10), FALSE);
+ x87_write_stack(i, READ80(ea + i*10), FALSE);
- CYCLES(cpustate,(cpustate->cr[0] & 1) ? 56 : 67);
+ CYCLES((m_cr[0] & 1) ? 56 : 67);
}
-void x87_frstor(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_frstor(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 0);
+ UINT32 ea = GetEA(modrm, 0);
// TODO: Pointers and selectors
- switch((cpustate->cr[0] & 1)|(cpustate->operand_size & 1)<<1)
+ switch((m_cr[0] & 1)|(m_operand_size & 1)<<1)
{
case 0: // 16-bit real mode
- x87_write_cw(cpustate, READ16(cpustate, ea));
- cpustate->x87_sw = READ16(cpustate, ea + 2);
- cpustate->x87_tw = READ16(cpustate, ea + 4);
-// WRITE16(cpustate, ea + 6, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate, ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate, ea + 10, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate, ea + 12, (cpustate->fpu_inst_ptr & 0x0f0000) >> 4);
+ x87_write_cw(READ16(ea));
+ m_x87_sw = READ16(ea + 2);
+ m_x87_tw = READ16(ea + 4);
+// WRITE16(ea + 6, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 10, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, (m_fpu_inst_ptr & 0x0f0000) >> 4);
ea += 14;
break;
case 1: // 16-bit protected mode
- x87_write_cw(cpustate, READ16(cpustate, ea));
- cpustate->x87_sw = READ16(cpustate, ea + 2);
- cpustate->x87_tw = READ16(cpustate, ea + 4);
-// WRITE16(cpustate,ea + 6, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate,ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate,ea + 10, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate,ea + 12, (cpustate->fpu_inst_ptr & 0x0f0000) >> 4);
+ x87_write_cw(READ16(ea));
+ m_x87_sw = READ16(ea + 2);
+ m_x87_tw = READ16(ea + 4);
+// WRITE16(ea + 6, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 10, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, (m_fpu_inst_ptr & 0x0f0000) >> 4);
ea += 14;
break;
case 2: // 32-bit real mode
- x87_write_cw(cpustate, READ16(cpustate, ea));
- cpustate->x87_sw = READ16(cpustate, ea + 4);
- cpustate->x87_tw = READ16(cpustate, ea + 8);
-// WRITE16(cpustate, ea + 12, cpustate->fpu_inst_ptr & 0xffff);
-// WRITE16(cpustate, ea + 8, (cpustate->fpu_opcode & 0x07ff) | ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE16(cpustate, ea + 20, cpustate->fpu_data_ptr & 0xffff);
-// WRITE16(cpustate, ea + 12, ((cpustate->fpu_inst_ptr & 0x0f0000) >> 4));
-// WRITE32(cpustate, ea + 24, (cpustate->fpu_data_ptr >> 16) << 12);
+ x87_write_cw(READ16(ea));
+ m_x87_sw = READ16(ea + 4);
+ m_x87_tw = READ16(ea + 8);
+// WRITE16(ea + 12, m_fpu_inst_ptr & 0xffff);
+// WRITE16(ea + 8, (m_fpu_opcode & 0x07ff) | ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE16(ea + 20, m_fpu_data_ptr & 0xffff);
+// WRITE16(ea + 12, ((m_fpu_inst_ptr & 0x0f0000) >> 4));
+// WRITE32(ea + 24, (m_fpu_data_ptr >> 16) << 12);
ea += 28;
break;
case 3: // 32-bit protected mode
- x87_write_cw(cpustate, READ16(cpustate, ea));
- cpustate->x87_sw = READ16(cpustate, ea + 4);
- cpustate->x87_tw = READ16(cpustate, ea + 8);
-// WRITE32(cpustate, ea + 12, cpustate->fpu_inst_ptr);
-// WRITE32(cpustate, ea + 16, cpustate->fpu_opcode);
-// WRITE32(cpustate, ea + 20, cpustate->fpu_data_ptr);
-// WRITE32(cpustate, ea + 24, cpustate->fpu_inst_ptr);
+ x87_write_cw(READ16(ea));
+ m_x87_sw = READ16(ea + 4);
+ m_x87_tw = READ16(ea + 8);
+// WRITE32(ea + 12, m_fpu_inst_ptr);
+// WRITE32(ea + 16, m_fpu_opcode);
+// WRITE32(ea + 20, m_fpu_data_ptr);
+// WRITE32(ea + 24, m_fpu_inst_ptr);
ea += 28;
break;
}
for (int i = 0; i < 8; ++i)
- WRITE80(cpustate, ea + i*10, ST(i));
+ WRITE80(ea + i*10, ST(i));
- CYCLES(cpustate,(cpustate->cr[0] & 1) ? 34 : 44);
+ CYCLES((m_cr[0] & 1) ? 34 : 44);
}
-void x87_fxch(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fxch(UINT8 modrm)
{
if (X87_IS_ST_EMPTY(0) || X87_IS_ST_EMPTY(1))
- x87_set_stack_underflow(cpustate);
+ x87_set_stack_underflow();
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
floatx80 tmp = ST(0);
ST(0) = ST(1);
@@ -4236,31 +4236,31 @@ void x87_fxch(i386_state *cpustate, UINT8 modrm)
// Swap the tags
int tag0 = X87_TAG(ST_TO_PHYS(0));
- x87_set_tag(cpustate, ST_TO_PHYS(0), X87_TAG(ST_TO_PHYS(1)));
- x87_set_tag(cpustate, ST_TO_PHYS(1), tag0);
+ x87_set_tag(ST_TO_PHYS(0), X87_TAG(ST_TO_PHYS(1)));
+ x87_set_tag(ST_TO_PHYS(1), tag0);
}
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fxch_sti(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fxch_sti(UINT8 modrm)
{
int i = modrm & 7;
if (X87_IS_ST_EMPTY(0))
{
ST(0) = fx80_inan;
- x87_set_tag(cpustate, ST_TO_PHYS(0), X87_TW_SPECIAL);
- x87_set_stack_underflow(cpustate);
+ x87_set_tag(ST_TO_PHYS(0), X87_TW_SPECIAL);
+ x87_set_stack_underflow();
}
if (X87_IS_ST_EMPTY(i))
{
ST(i) = fx80_inan;
- x87_set_tag(cpustate, ST_TO_PHYS(i), X87_TW_SPECIAL);
- x87_set_stack_underflow(cpustate);
+ x87_set_tag(ST_TO_PHYS(i), X87_TW_SPECIAL);
+ x87_set_stack_underflow();
}
- if (x87_check_exceptions(cpustate))
+ if (x87_check_exceptions())
{
floatx80 tmp = ST(0);
ST(0) = ST(i);
@@ -4268,33 +4268,33 @@ void x87_fxch_sti(i386_state *cpustate, UINT8 modrm)
// Swap the tags
int tag0 = X87_TAG(ST_TO_PHYS(0));
- x87_set_tag(cpustate, ST_TO_PHYS(0), X87_TAG(ST_TO_PHYS(i)));
- x87_set_tag(cpustate, ST_TO_PHYS(i), tag0);
+ x87_set_tag(ST_TO_PHYS(0), X87_TAG(ST_TO_PHYS(i)));
+ x87_set_tag(ST_TO_PHYS(i), tag0);
}
- CYCLES(cpustate, 4);
+ CYCLES(4);
}
-void x87_fstsw_ax(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fstsw_ax(UINT8 modrm)
{
- REG16(AX) = cpustate->x87_sw;
+ REG16(AX) = m_x87_sw;
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_fstsw_m2byte(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_fstsw_m2byte(UINT8 modrm)
{
- UINT32 ea = GetEA(cpustate, modrm, 1);
+ UINT32 ea = GetEA(modrm, 1);
- WRITE16(cpustate, ea, cpustate->x87_sw);
+ WRITE16(ea, m_x87_sw);
- CYCLES(cpustate, 3);
+ CYCLES(3);
}
-void x87_invalid(i386_state *cpustate, UINT8 modrm)
+void i386_device::x87_invalid(UINT8 modrm)
{
// TODO
- fatalerror("x87 invalid instruction (PC:%.4x)\n", cpustate->pc);
+ fatalerror("x87 invalid instruction (PC:%.4x)\n", m_pc);
}
@@ -4305,52 +4305,52 @@ void x87_invalid(i386_state *cpustate, UINT8 modrm)
*
*************************************/
-static void I386OP(x87_group_d8)(i386_state *cpustate)
+void i386_device::i386_x87_group_d8()
{
- UINT8 modrm = FETCH(cpustate);
- cpustate->opcode_table_x87_d8[modrm](cpustate, modrm);
+ UINT8 modrm = FETCH();
+ (this->*m_opcode_table_x87_d8[modrm])(modrm);
}
-static void I386OP(x87_group_d9)(i386_state *cpustate)
+void i386_device::i386_x87_group_d9()
{
- UINT8 modrm = FETCH(cpustate);
- cpustate->opcode_table_x87_d9[modrm](cpustate, modrm);
+ UINT8 modrm = FETCH();
+ (this->*m_opcode_table_x87_d9[modrm])(modrm);
}
-static void I386OP(x87_group_da)(i386_state *cpustate)
+void i386_device::i386_x87_group_da()
{
- UINT8 modrm = FETCH(cpustate);
- cpustate->opcode_table_x87_da[modrm](cpustate, modrm);
+ UINT8 modrm = FETCH();
+ (this->*m_opcode_table_x87_da[modrm])(modrm);
}
-static void I386OP(x87_group_db)(i386_state *cpustate)
+void i386_device::i386_x87_group_db()
{
- UINT8 modrm = FETCH(cpustate);
- cpustate->opcode_table_x87_db[modrm](cpustate, modrm);
+ UINT8 modrm = FETCH();
+ (this->*m_opcode_table_x87_db[modrm])(modrm);
}
-static void I386OP(x87_group_dc)(i386_state *cpustate)
+void i386_device::i386_x87_group_dc()
{
- UINT8 modrm = FETCH(cpustate);
- cpustate->opcode_table_x87_dc[modrm](cpustate, modrm);
+ UINT8 modrm = FETCH();
+ (this->*m_opcode_table_x87_dc[modrm])(modrm);
}
-static void I386OP(x87_group_dd)(i386_state *cpustate)
+void i386_device::i386_x87_group_dd()
{
- UINT8 modrm = FETCH(cpustate);
- cpustate->opcode_table_x87_dd[modrm](cpustate, modrm);
+ UINT8 modrm = FETCH();
+ (this->*m_opcode_table_x87_dd[modrm])(modrm);
}
-static void I386OP(x87_group_de)(i386_state *cpustate)
+void i386_device::i386_x87_group_de()
{
- UINT8 modrm = FETCH(cpustate);
- cpustate->opcode_table_x87_de[modrm](cpustate, modrm);
+ UINT8 modrm = FETCH();
+ (this->*m_opcode_table_x87_de[modrm])(modrm);
}
-static void I386OP(x87_group_df)(i386_state *cpustate)
+void i386_device::i386_x87_group_df()
{
- UINT8 modrm = FETCH(cpustate);
- cpustate->opcode_table_x87_df[modrm](cpustate, modrm);
+ UINT8 modrm = FETCH();
+ (this->*m_opcode_table_x87_df[modrm])(modrm);
}
@@ -4360,67 +4360,67 @@ static void I386OP(x87_group_df)(i386_state *cpustate)
*
*************************************/
-void build_x87_opcode_table_d8(i386_state *cpustate)
+void i386_device::build_x87_opcode_table_d8()
{
int modrm = 0;
for (modrm = 0; modrm < 0x100; ++modrm)
{
- void (*ptr)(i386_state *cpustate, UINT8 modrm) = x87_invalid;
+ i386_modrm_func ptr = &i386_device::x87_invalid;
if (modrm < 0xc0)
{
switch ((modrm >> 3) & 0x7)
{
- case 0x00: ptr = x87_fadd_m32real; break;
- case 0x01: ptr = x87_fmul_m32real; break;
- case 0x02: ptr = x87_fcom_m32real; break;
- case 0x03: ptr = x87_fcomp_m32real; break;
- case 0x04: ptr = x87_fsub_m32real; break;
- case 0x05: ptr = x87_fsubr_m32real; break;
- case 0x06: ptr = x87_fdiv_m32real; break;
- case 0x07: ptr = x87_fdivr_m32real; break;
+ case 0x00: ptr = &i386_device::x87_fadd_m32real; break;
+ case 0x01: ptr = &i386_device::x87_fmul_m32real; break;
+ case 0x02: ptr = &i386_device::x87_fcom_m32real; break;
+ case 0x03: ptr = &i386_device::x87_fcomp_m32real; break;
+ case 0x04: ptr = &i386_device::x87_fsub_m32real; break;
+ case 0x05: ptr = &i386_device::x87_fsubr_m32real; break;
+ case 0x06: ptr = &i386_device::x87_fdiv_m32real; break;
+ case 0x07: ptr = &i386_device::x87_fdivr_m32real; break;
}
}
else
{
switch (modrm)
{
- case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: ptr = x87_fadd_st_sti; break;
- case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: ptr = x87_fmul_st_sti; break;
- case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7: ptr = x87_fcom_sti; break;
- case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf: ptr = x87_fcomp_sti; break;
- case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: ptr = x87_fsub_st_sti; break;
- case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: ptr = x87_fsubr_st_sti; break;
- case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = x87_fdiv_st_sti; break;
- case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: ptr = x87_fdivr_st_sti; break;
+ case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: ptr = &i386_device::x87_fadd_st_sti; break;
+ case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: ptr = &i386_device::x87_fmul_st_sti; break;
+ case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7: ptr = &i386_device::x87_fcom_sti; break;
+ case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf: ptr = &i386_device::x87_fcomp_sti; break;
+ case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: ptr = &i386_device::x87_fsub_st_sti; break;
+ case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: ptr = &i386_device::x87_fsubr_st_sti; break;
+ case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = &i386_device::x87_fdiv_st_sti; break;
+ case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: ptr = &i386_device::x87_fdivr_st_sti; break;
}
}
- cpustate->opcode_table_x87_d8[modrm] = ptr;
+ m_opcode_table_x87_d8[modrm] = ptr;
}
}
-void build_x87_opcode_table_d9(i386_state *cpustate)
+void i386_device::build_x87_opcode_table_d9()
{
int modrm = 0;
for (modrm = 0; modrm < 0x100; ++modrm)
{
- void (*ptr)(i386_state *cpustate, UINT8 modrm) = x87_invalid;
+ i386_modrm_func ptr = &i386_device::x87_invalid;
if (modrm < 0xc0)
{
switch ((modrm >> 3) & 0x7)
{
- case 0x00: ptr = x87_fld_m32real; break;
- case 0x02: ptr = x87_fst_m32real; break;
- case 0x03: ptr = x87_fstp_m32real; break;
- case 0x04: ptr = x87_fldenv; break;
- case 0x05: ptr = x87_fldcw; break;
- case 0x06: ptr = x87_fstenv; break;
- case 0x07: ptr = x87_fstcw; break;
+ case 0x00: ptr = &i386_device::x87_fld_m32real; break;
+ case 0x02: ptr = &i386_device::x87_fst_m32real; break;
+ case 0x03: ptr = &i386_device::x87_fstp_m32real; break;
+ case 0x04: ptr = &i386_device::x87_fldenv; break;
+ case 0x05: ptr = &i386_device::x87_fldcw; break;
+ case 0x06: ptr = &i386_device::x87_fstenv; break;
+ case 0x07: ptr = &i386_device::x87_fstcw; break;
}
}
else
@@ -4434,7 +4434,7 @@ void build_x87_opcode_table_d9(i386_state *cpustate)
case 0xc4:
case 0xc5:
case 0xc6:
- case 0xc7: ptr = x87_fld_sti; break;
+ case 0xc7: ptr = &i386_device::x87_fld_sti; break;
case 0xc8:
case 0xc9:
@@ -4443,275 +4443,275 @@ void build_x87_opcode_table_d9(i386_state *cpustate)
case 0xcc:
case 0xcd:
case 0xce:
- case 0xcf: ptr = x87_fxch_sti; break;
-
- case 0xd0: ptr = x87_fnop; break;
- case 0xe0: ptr = x87_fchs; break;
- case 0xe1: ptr = x87_fabs; break;
- case 0xe4: ptr = x87_ftst; break;
- case 0xe5: ptr = x87_fxam; break;
- case 0xe8: ptr = x87_fld1; break;
- case 0xe9: ptr = x87_fldl2t; break;
- case 0xea: ptr = x87_fldl2e; break;
- case 0xeb: ptr = x87_fldpi; break;
- case 0xec: ptr = x87_fldlg2; break;
- case 0xed: ptr = x87_fldln2; break;
- case 0xee: ptr = x87_fldz; break;
- case 0xf0: ptr = x87_f2xm1; break;
- case 0xf1: ptr = x87_fyl2x; break;
- case 0xf2: ptr = x87_fptan; break;
- case 0xf3: ptr = x87_fpatan; break;
- case 0xf4: ptr = x87_fxtract; break;
- case 0xf5: ptr = x87_fprem1; break;
- case 0xf6: ptr = x87_fdecstp; break;
- case 0xf7: ptr = x87_fincstp; break;
- case 0xf8: ptr = x87_fprem; break;
- case 0xf9: ptr = x87_fyl2xp1; break;
- case 0xfa: ptr = x87_fsqrt; break;
- case 0xfb: ptr = x87_fsincos; break;
- case 0xfc: ptr = x87_frndint; break;
- case 0xfd: ptr = x87_fscale; break;
- case 0xfe: ptr = x87_fsin; break;
- case 0xff: ptr = x87_fcos; break;
+ case 0xcf: ptr = &i386_device::x87_fxch_sti; break;
+
+ case 0xd0: ptr = &i386_device::x87_fnop; break;
+ case 0xe0: ptr = &i386_device::x87_fchs; break;
+ case 0xe1: ptr = &i386_device::x87_fabs; break;
+ case 0xe4: ptr = &i386_device::x87_ftst; break;
+ case 0xe5: ptr = &i386_device::x87_fxam; break;
+ case 0xe8: ptr = &i386_device::x87_fld1; break;
+ case 0xe9: ptr = &i386_device::x87_fldl2t; break;
+ case 0xea: ptr = &i386_device::x87_fldl2e; break;
+ case 0xeb: ptr = &i386_device::x87_fldpi; break;
+ case 0xec: ptr = &i386_device::x87_fldlg2; break;
+ case 0xed: ptr = &i386_device::x87_fldln2; break;
+ case 0xee: ptr = &i386_device::x87_fldz; break;
+ case 0xf0: ptr = &i386_device::x87_f2xm1; break;
+ case 0xf1: ptr = &i386_device::x87_fyl2x; break;
+ case 0xf2: ptr = &i386_device::x87_fptan; break;
+ case 0xf3: ptr = &i386_device::x87_fpatan; break;
+ case 0xf4: ptr = &i386_device::x87_fxtract; break;
+ case 0xf5: ptr = &i386_device::x87_fprem1; break;
+ case 0xf6: ptr = &i386_device::x87_fdecstp; break;
+ case 0xf7: ptr = &i386_device::x87_fincstp; break;
+ case 0xf8: ptr = &i386_device::x87_fprem; break;
+ case 0xf9: ptr = &i386_device::x87_fyl2xp1; break;
+ case 0xfa: ptr = &i386_device::x87_fsqrt; break;
+ case 0xfb: ptr = &i386_device::x87_fsincos; break;
+ case 0xfc: ptr = &i386_device::x87_frndint; break;
+ case 0xfd: ptr = &i386_device::x87_fscale; break;
+ case 0xfe: ptr = &i386_device::x87_fsin; break;
+ case 0xff: ptr = &i386_device::x87_fcos; break;
}
}
- cpustate->opcode_table_x87_d9[modrm] = ptr;
+ m_opcode_table_x87_d9[modrm] = ptr;
}
}
-void build_x87_opcode_table_da(i386_state *cpustate)
+void i386_device::build_x87_opcode_table_da()
{
int modrm = 0;
for (modrm = 0; modrm < 0x100; ++modrm)
{
- void (*ptr)(i386_state *cpustate, UINT8 modrm) = x87_invalid;
+ i386_modrm_func ptr = &i386_device::x87_invalid;
if (modrm < 0xc0)
{
switch ((modrm >> 3) & 0x7)
{
- case 0x00: ptr = x87_fiadd_m32int; break;
- case 0x01: ptr = x87_fimul_m32int; break;
- case 0x02: ptr = x87_ficom_m32int; break;
- case 0x03: ptr = x87_ficomp_m32int; break;
- case 0x04: ptr = x87_fisub_m32int; break;
- case 0x05: ptr = x87_fisubr_m32int; break;
- case 0x06: ptr = x87_fidiv_m32int; break;
- case 0x07: ptr = x87_fidivr_m32int; break;
+ case 0x00: ptr = &i386_device::x87_fiadd_m32int; break;
+ case 0x01: ptr = &i386_device::x87_fimul_m32int; break;
+ case 0x02: ptr = &i386_device::x87_ficom_m32int; break;
+ case 0x03: ptr = &i386_device::x87_ficomp_m32int; break;
+ case 0x04: ptr = &i386_device::x87_fisub_m32int; break;
+ case 0x05: ptr = &i386_device::x87_fisubr_m32int; break;
+ case 0x06: ptr = &i386_device::x87_fidiv_m32int; break;
+ case 0x07: ptr = &i386_device::x87_fidivr_m32int; break;
}
}
else
{
switch (modrm)
{
- case 0xe9: ptr = x87_fucompp; break;
+ case 0xe9: ptr = &i386_device::x87_fucompp; break;
}
}
- cpustate->opcode_table_x87_da[modrm] = ptr;
+ m_opcode_table_x87_da[modrm] = ptr;
}
}
-void build_x87_opcode_table_db(i386_state *cpustate)
+void i386_device::build_x87_opcode_table_db()
{
int modrm = 0;
for (modrm = 0; modrm < 0x100; ++modrm)
{
- void (*ptr)(i386_state *cpustate, UINT8 modrm) = x87_invalid;
+ i386_modrm_func ptr = &i386_device::x87_invalid;
if (modrm < 0xc0)
{
switch ((modrm >> 3) & 0x7)
{
- case 0x00: ptr = x87_fild_m32int; break;
- case 0x02: ptr = x87_fist_m32int; break;
- case 0x03: ptr = x87_fistp_m32int; break;
- case 0x05: ptr = x87_fld_m80real; break;
- case 0x07: ptr = x87_fstp_m80real; break;
+ case 0x00: ptr = &i386_device::x87_fild_m32int; break;
+ case 0x02: ptr = &i386_device::x87_fist_m32int; break;
+ case 0x03: ptr = &i386_device::x87_fistp_m32int; break;
+ case 0x05: ptr = &i386_device::x87_fld_m80real; break;
+ case 0x07: ptr = &i386_device::x87_fstp_m80real; break;
}
}
else
{
switch (modrm)
{
- case 0xe0: ptr = x87_fnop; break; /* FENI */
- case 0xe1: ptr = x87_fnop; break; /* FDISI */
- case 0xe2: ptr = x87_fclex; break;
- case 0xe3: ptr = x87_finit; break;
- case 0xe4: ptr = x87_fnop; break; /* FSETPM */
+ case 0xe0: ptr = &i386_device::x87_fnop; break; /* FENI */
+ case 0xe1: ptr = &i386_device::x87_fnop; break; /* FDISI */
+ case 0xe2: ptr = &i386_device::x87_fclex; break;
+ case 0xe3: ptr = &i386_device::x87_finit; break;
+ case 0xe4: ptr = &i386_device::x87_fnop; break; /* FSETPM */
}
}
- cpustate->opcode_table_x87_db[modrm] = ptr;
+ m_opcode_table_x87_db[modrm] = ptr;
}
}
-void build_x87_opcode_table_dc(i386_state *cpustate)
+void i386_device::build_x87_opcode_table_dc()
{
int modrm = 0;
for (modrm = 0; modrm < 0x100; ++modrm)
{
- void (*ptr)(i386_state *cpustate, UINT8 modrm) = x87_invalid;
+ i386_modrm_func ptr = &i386_device::x87_invalid;
if (modrm < 0xc0)
{
switch ((modrm >> 3) & 0x7)
{
- case 0x00: ptr = x87_fadd_m64real; break;
- case 0x01: ptr = x87_fmul_m64real; break;
- case 0x02: ptr = x87_fcom_m64real; break;
- case 0x03: ptr = x87_fcomp_m64real; break;
- case 0x04: ptr = x87_fsub_m64real; break;
- case 0x05: ptr = x87_fsubr_m64real; break;
- case 0x06: ptr = x87_fdiv_m64real; break;
- case 0x07: ptr = x87_fdivr_m64real; break;
+ case 0x00: ptr = &i386_device::x87_fadd_m64real; break;
+ case 0x01: ptr = &i386_device::x87_fmul_m64real; break;
+ case 0x02: ptr = &i386_device::x87_fcom_m64real; break;
+ case 0x03: ptr = &i386_device::x87_fcomp_m64real; break;
+ case 0x04: ptr = &i386_device::x87_fsub_m64real; break;
+ case 0x05: ptr = &i386_device::x87_fsubr_m64real; break;
+ case 0x06: ptr = &i386_device::x87_fdiv_m64real; break;
+ case 0x07: ptr = &i386_device::x87_fdivr_m64real; break;
}
}
else
{
switch (modrm)
{
- case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: ptr = x87_fadd_sti_st; break;
- case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: ptr = x87_fmul_sti_st; break;
- case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: ptr = x87_fsubr_sti_st; break;
- case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: ptr = x87_fsub_sti_st; break;
- case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = x87_fdivr_sti_st; break;
- case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: ptr = x87_fdiv_sti_st; break;
+ case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: ptr = &i386_device::x87_fadd_sti_st; break;
+ case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: ptr = &i386_device::x87_fmul_sti_st; break;
+ case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: ptr = &i386_device::x87_fsubr_sti_st; break;
+ case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: ptr = &i386_device::x87_fsub_sti_st; break;
+ case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = &i386_device::x87_fdivr_sti_st; break;
+ case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: ptr = &i386_device::x87_fdiv_sti_st; break;
}
}
- cpustate->opcode_table_x87_dc[modrm] = ptr;
+ m_opcode_table_x87_dc[modrm] = ptr;
}
}
-void build_x87_opcode_table_dd(i386_state *cpustate)
+void i386_device::build_x87_opcode_table_dd()
{
int modrm = 0;
for (modrm = 0; modrm < 0x100; ++modrm)
{
- void (*ptr)(i386_state *cpustate, UINT8 modrm) = x87_invalid;
+ i386_modrm_func ptr = &i386_device::x87_invalid;
if (modrm < 0xc0)
{
switch ((modrm >> 3) & 0x7)
{
- case 0x00: ptr = x87_fld_m64real; break;
- case 0x02: ptr = x87_fst_m64real; break;
- case 0x03: ptr = x87_fstp_m64real; break;
- case 0x04: ptr = x87_frstor; break;
- case 0x06: ptr = x87_fsave; break;
- case 0x07: ptr = x87_fstsw_m2byte; break;
+ case 0x00: ptr = &i386_device::x87_fld_m64real; break;
+ case 0x02: ptr = &i386_device::x87_fst_m64real; break;
+ case 0x03: ptr = &i386_device::x87_fstp_m64real; break;
+ case 0x04: ptr = &i386_device::x87_frstor; break;
+ case 0x06: ptr = &i386_device::x87_fsave; break;
+ case 0x07: ptr = &i386_device::x87_fstsw_m2byte; break;
}
}
else
{
switch (modrm)
{
- case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: ptr = x87_ffree; break;
- case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: ptr = x87_fxch_sti; break;
- case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7: ptr = x87_fst_sti; break;
- case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf: ptr = x87_fstp_sti; break;
- case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: ptr = x87_fucom_sti; break;
- case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: ptr = x87_fucomp_sti; break;
+ case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: ptr = &i386_device::x87_ffree; break;
+ case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: ptr = &i386_device::x87_fxch_sti; break;
+ case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7: ptr = &i386_device::x87_fst_sti; break;
+ case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf: ptr = &i386_device::x87_fstp_sti; break;
+ case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: ptr = &i386_device::x87_fucom_sti; break;
+ case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: ptr = &i386_device::x87_fucomp_sti; break;
}
}
- cpustate->opcode_table_x87_dd[modrm] = ptr;
+ m_opcode_table_x87_dd[modrm] = ptr;
}
}
-void build_x87_opcode_table_de(i386_state *cpustate)
+void i386_device::build_x87_opcode_table_de()
{
int modrm = 0;
for (modrm = 0; modrm < 0x100; ++modrm)
{
- void (*ptr)(i386_state *cpustate, UINT8 modrm) = x87_invalid;
+ i386_modrm_func ptr = &i386_device::x87_invalid;
if (modrm < 0xc0)
{
switch ((modrm >> 3) & 0x7)
{
- case 0x00: ptr = x87_fiadd_m16int; break;
- case 0x01: ptr = x87_fimul_m16int; break;
- case 0x02: ptr = x87_ficom_m16int; break;
- case 0x03: ptr = x87_ficomp_m16int; break;
- case 0x04: ptr = x87_fisub_m16int; break;
- case 0x05: ptr = x87_fisubr_m16int; break;
- case 0x06: ptr = x87_fidiv_m16int; break;
- case 0x07: ptr = x87_fidivr_m16int; break;
+ case 0x00: ptr = &i386_device::x87_fiadd_m16int; break;
+ case 0x01: ptr = &i386_device::x87_fimul_m16int; break;
+ case 0x02: ptr = &i386_device::x87_ficom_m16int; break;
+ case 0x03: ptr = &i386_device::x87_ficomp_m16int; break;
+ case 0x04: ptr = &i386_device::x87_fisub_m16int; break;
+ case 0x05: ptr = &i386_device::x87_fisubr_m16int; break;
+ case 0x06: ptr = &i386_device::x87_fidiv_m16int; break;
+ case 0x07: ptr = &i386_device::x87_fidivr_m16int; break;
}
}
else
{
switch (modrm)
{
- case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: ptr = x87_faddp; break;
- case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: ptr = x87_fmulp; break;
- case 0xd9: ptr = x87_fcompp; break;
- case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: ptr = x87_fsubrp; break;
- case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: ptr = x87_fsubp; break;
- case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = x87_fdivrp; break;
- case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: ptr = x87_fdivp; break;
+ case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7: ptr = &i386_device::x87_faddp; break;
+ case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: ptr = &i386_device::x87_fmulp; break;
+ case 0xd9: ptr = &i386_device::x87_fcompp; break;
+ case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7: ptr = &i386_device::x87_fsubrp; break;
+ case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: ptr = &i386_device::x87_fsubp; break;
+ case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = &i386_device::x87_fdivrp; break;
+ case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: ptr = &i386_device::x87_fdivp; break;
}
}
- cpustate->opcode_table_x87_de[modrm] = ptr;
+ m_opcode_table_x87_de[modrm] = ptr;
}
}
-void build_x87_opcode_table_df(i386_state *cpustate)
+void i386_device::build_x87_opcode_table_df()
{
int modrm = 0;
for (modrm = 0; modrm < 0x100; ++modrm)
{
- void (*ptr)(i386_state *cpustate, UINT8 modrm) = x87_invalid;
+ i386_modrm_func ptr = &i386_device::x87_invalid;
if (modrm < 0xc0)
{
switch ((modrm >> 3) & 0x7)
{
- case 0x00: ptr = x87_fild_m16int; break;
- case 0x02: ptr = x87_fist_m16int; break;
- case 0x03: ptr = x87_fistp_m16int; break;
- case 0x04: ptr = x87_fbld; break;
- case 0x05: ptr = x87_fild_m64int; break;
- case 0x06: ptr = x87_fbstp; break;
- case 0x07: ptr = x87_fistp_m64int; break;
+ case 0x00: ptr = &i386_device::x87_fild_m16int; break;
+ case 0x02: ptr = &i386_device::x87_fist_m16int; break;
+ case 0x03: ptr = &i386_device::x87_fistp_m16int; break;
+ case 0x04: ptr = &i386_device::x87_fbld; break;
+ case 0x05: ptr = &i386_device::x87_fild_m64int; break;
+ case 0x06: ptr = &i386_device::x87_fbstp; break;
+ case 0x07: ptr = &i386_device::x87_fistp_m64int; break;
}
}
else
{
switch (modrm)
{
- case 0xe0: ptr = x87_fstsw_ax; break;
- case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = x87_fcomip_sti; break;
+ case 0xe0: ptr = &i386_device::x87_fstsw_ax; break;
+ case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7: ptr = &i386_device::x87_fcomip_sti; break;
}
}
- cpustate->opcode_table_x87_df[modrm] = ptr;
+ m_opcode_table_x87_df[modrm] = ptr;
}
}
-void build_x87_opcode_table(i386_state *cpustate)
+void i386_device::build_x87_opcode_table()
{
- build_x87_opcode_table_d8(cpustate);
- build_x87_opcode_table_d9(cpustate);
- build_x87_opcode_table_da(cpustate);
- build_x87_opcode_table_db(cpustate);
- build_x87_opcode_table_dc(cpustate);
- build_x87_opcode_table_dd(cpustate);
- build_x87_opcode_table_de(cpustate);
- build_x87_opcode_table_df(cpustate);
+ build_x87_opcode_table_d8();
+ build_x87_opcode_table_d9();
+ build_x87_opcode_table_da();
+ build_x87_opcode_table_db();
+ build_x87_opcode_table_dc();
+ build_x87_opcode_table_dd();
+ build_x87_opcode_table_de();
+ build_x87_opcode_table_df();
}