diff options
author | Aaron Giles <aaron@aarongiles.com> | 2009-01-14 06:10:30 +0000 |
---|---|---|
committer | Aaron Giles <aaron@aarongiles.com> | 2009-01-14 06:10:30 +0000 |
commit | 2a780fc07d40ec3cded1f4320e4daca5d9d37b24 (patch) | |
tree | 801f20a62affe3e5aad1aed4c4db62a7f4aa1de4 /src | |
parent | 62bddb4fe6de8a4b8a14c247aaa2689dba25b6f4 (diff) |
From: Oliver Stoeneberg [mailto:oliverst@online.de]
Sent: Sunday, January 11, 2009 5:52 AM
To: submit@mamedev.org
Subject: unreachable code cleanup
This patch cleans up the usage of unreachable code (mostly
unnecessary breaks after returns in switch - case). A few case of
really unused code were also discovered. I marked thos with FIXME
comments.
I based this cleanup on teh output of cppcheck. It does still missing
a few cases of unreachable code, so there might be future patches to
address more cases.
Diffstat (limited to 'src')
60 files changed, 74 insertions, 546 deletions
diff --git a/src/emu/cpu/arm/arm.c b/src/emu/cpu/arm/arm.c index f9bce799cc5..6246f8db31c 100644 --- a/src/emu/cpu/arm/arm.c +++ b/src/emu/cpu/arm/arm.c @@ -1200,7 +1200,6 @@ static UINT32 decodeShift( ARM_REGS* cpustate, UINT32 insn, UINT32 *pCarry) *pCarry = k ? (rm & (1 << (32 - k))) : (R15 & C_MASK); } return k ? LSL(rm, k) : rm; - break; case 1: /* LSR */ if (k == 0 || k == 32) diff --git a/src/emu/cpu/dsp56k/dsp56dsm.c b/src/emu/cpu/dsp56k/dsp56dsm.c index 6ba798a8e3f..7173b517acf 100644 --- a/src/emu/cpu/dsp56k/dsp56dsm.c +++ b/src/emu/cpu/dsp56k/dsp56dsm.c @@ -2659,9 +2659,9 @@ static int decode_BBB_table(UINT16 BBB) { switch(BBB) { - case 0x4: return BBB_UPPER ; break; - case 0x2: return BBB_MIDDLE; break; - case 0x1: return BBB_LOWER ; break; + case 0x4: return BBB_UPPER; + case 0x2: return BBB_MIDDLE; + case 0x1: return BBB_LOWER; } return BBB_LOWER; /* Not really safe... */ diff --git a/src/emu/cpu/dsp56k/dsp56mem.c b/src/emu/cpu/dsp56k/dsp56mem.c index 695dc7149bb..b3375aaaf06 100644 --- a/src/emu/cpu/dsp56k/dsp56mem.c +++ b/src/emu/cpu/dsp56k/dsp56mem.c @@ -721,27 +721,22 @@ UINT8 dsp56k_host_interface_read(device_config* device, UINT8 offset) // Interrupt Control Register (ICR) case 0x00: return ICR; - break; // Command Vector Register (CVR) case 0x01: return CVR; - break; // Interrupt status register (ISR) case 0x02: return ISR; - break; // Interrupt vector register (IVR) case 0x03: return IVR; - break; // Read zeroes case 0x04: return 0x00; - break; // Reserved case 0x05: diff --git a/src/emu/cpu/dsp56k/dsp56ops.c b/src/emu/cpu/dsp56k/dsp56ops.c index 167f8f287fe..fd8d25abdcd 100644 --- a/src/emu/cpu/dsp56k/dsp56ops.c +++ b/src/emu/cpu/dsp56k/dsp56ops.c @@ -4345,8 +4345,8 @@ static UINT16 execute_q_table(dsp56k_core* cpustate, int RR, UINT16 q) switch(q) { - case 0x0: /* No permanent changes */ ; return (*rX)+(*nX); break; - case 0x1: (*rX)--; return (*rX); break; // This one is special - it's a *PRE-decrement*! + case 0x0: /* No permanent changes */ ; return (*rX)+(*nX); + case 0x1: (*rX)--; return (*rX); // This one is special - it's a *PRE-decrement*! } /* Should not get here */ diff --git a/src/emu/cpu/h6280/h6280.c b/src/emu/cpu/h6280/h6280.c index 4cb2af5db97..57a7ca0a867 100644 --- a/src/emu/cpu/h6280/h6280.c +++ b/src/emu/cpu/h6280/h6280.c @@ -289,7 +289,7 @@ READ8_HANDLER( h6280_irq_status_r ) switch (offset&3) { - default: return cpustate->io_buffer; break; + default: return cpustate->io_buffer; case 3: { status=0; @@ -298,7 +298,7 @@ READ8_HANDLER( h6280_irq_status_r ) if(cpustate->irq_state[2]!=CLEAR_LINE) status|=4; /* TIMER */ return status|(cpustate->io_buffer&(~H6280_IRQ_MASK)); } - case 2: return cpustate->irq_mask|(cpustate->io_buffer&(~H6280_IRQ_MASK));break; + case 2: return cpustate->irq_mask|(cpustate->io_buffer&(~H6280_IRQ_MASK)); } } diff --git a/src/emu/cpu/hd6309/6309ops.c b/src/emu/cpu/hd6309/6309ops.c index 5cd2c921099..85b336159ca 100644 --- a/src/emu/cpu/hd6309/6309ops.c +++ b/src/emu/cpu/hd6309/6309ops.c @@ -945,7 +945,7 @@ OP_HANDLER( tfmpp ) case 2: srcValue = RM(Y++); break; case 3: srcValue = RM(U++); break; case 4: srcValue = RM(S++); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } switch(tb&15) { @@ -954,7 +954,7 @@ OP_HANDLER( tfmpp ) case 2: WM(Y++, srcValue); break; case 3: WM(U++, srcValue); break; case 4: WM(S++, srcValue); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } PCD = PCD - 3; @@ -979,7 +979,7 @@ OP_HANDLER( tfmmm ) case 2: srcValue = RM(Y--); break; case 3: srcValue = RM(U--); break; case 4: srcValue = RM(S--); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } switch(tb&15) { @@ -988,7 +988,7 @@ OP_HANDLER( tfmmm ) case 2: WM(Y--, srcValue); break; case 3: WM(U--, srcValue); break; case 4: WM(S--, srcValue); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } PCD = PCD - 3; @@ -1013,7 +1013,7 @@ OP_HANDLER( tfmpc ) case 2: srcValue = RM(Y++); break; case 3: srcValue = RM(U++); break; case 4: srcValue = RM(S++); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } switch(tb&15) { @@ -1022,7 +1022,7 @@ OP_HANDLER( tfmpc ) case 2: WM(Y, srcValue); break; case 3: WM(U, srcValue); break; case 4: WM(S, srcValue); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } PCD = PCD - 3; @@ -1047,7 +1047,7 @@ OP_HANDLER( tfmcp ) case 2: srcValue = RM(Y); break; case 3: srcValue = RM(U); break; case 4: srcValue = RM(S); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } switch(tb&15) { @@ -1056,7 +1056,7 @@ OP_HANDLER( tfmcp ) case 2: WM(Y++, srcValue); break; case 3: WM(U++, srcValue); break; case 4: WM(S++, srcValue); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } PCD = PCD - 3; diff --git a/src/emu/cpu/m37710/m37710.c b/src/emu/cpu/m37710/m37710.c index 012289ce5c2..67e3f4e44d9 100644 --- a/src/emu/cpu/m37710/m37710.c +++ b/src/emu/cpu/m37710/m37710.c @@ -404,87 +404,60 @@ static UINT8 m37710_internal_r(m37710i_cpu_struct *cpustate, int offset) { case 2: // p0 return memory_read_byte_8le(cpustate->io, M37710_PORT0); - break; case 3: // p1 return memory_read_byte_8le(cpustate->io, M37710_PORT1); - break; case 6: // p2 return memory_read_byte_8le(cpustate->io, M37710_PORT2); - break; case 7: // p3 return memory_read_byte_8le(cpustate->io, M37710_PORT3); - break; case 0xa: // p4 return memory_read_byte_8le(cpustate->io, M37710_PORT4); - break; case 0xb: // p5 return memory_read_byte_8le(cpustate->io, M37710_PORT5); - break; case 0xe: // p6 return memory_read_byte_8le(cpustate->io, M37710_PORT6); - break; case 0xf: // p7 return memory_read_byte_8le(cpustate->io, M37710_PORT7); - break; case 0x12: // p8 return memory_read_byte_8le(cpustate->io, M37710_PORT8); - break; case 0x20: return memory_read_byte_8le(cpustate->io, M37710_ADC0_L); - break; case 0x21: return memory_read_byte_8le(cpustate->io, M37710_ADC0_H); - break; case 0x22: return memory_read_byte_8le(cpustate->io, M37710_ADC1_L); - break; case 0x23: return memory_read_byte_8le(cpustate->io, M37710_ADC1_H); - break; case 0x24: return memory_read_byte_8le(cpustate->io, M37710_ADC2_L); - break; case 0x25: return memory_read_byte_8le(cpustate->io, M37710_ADC2_H); - break; case 0x26: return memory_read_byte_8le(cpustate->io, M37710_ADC3_L); - break; case 0x27: return memory_read_byte_8le(cpustate->io, M37710_ADC3_H); - break; case 0x28: return memory_read_byte_8le(cpustate->io, M37710_ADC4_L); - break; case 0x29: return memory_read_byte_8le(cpustate->io, M37710_ADC4_H); - break; case 0x2a: return memory_read_byte_8le(cpustate->io, M37710_ADC5_L); - break; case 0x2b: return memory_read_byte_8le(cpustate->io, M37710_ADC5_H); - break; case 0x2c: return memory_read_byte_8le(cpustate->io, M37710_ADC6_L); - break; case 0x2d: return memory_read_byte_8le(cpustate->io, M37710_ADC6_H); - break; case 0x2e: return memory_read_byte_8le(cpustate->io, M37710_ADC7_L); - break; case 0x2f: return memory_read_byte_8le(cpustate->io, M37710_ADC7_H); - break; case 0x35: return 0xff; // UART control - break; case 0x70: // A/D IRQ control return cpustate->m37710_regs[offset] | 8; - break; } return cpustate->m37710_regs[offset]; @@ -499,39 +472,30 @@ static void m37710_internal_w(m37710i_cpu_struct *cpustate, int offset, UINT8 da case 2: // p0 memory_write_byte_8le(cpustate->io, M37710_PORT0, data); return; - break; case 3: // p1 memory_write_byte_8le(cpustate->io, M37710_PORT1, data); return; - break; case 6: // p2 memory_write_byte_8le(cpustate->io, M37710_PORT2, data); return; - break; case 7: // p3 memory_write_byte_8le(cpustate->io, M37710_PORT3, data); return; - break; case 0xa: // p4 memory_write_byte_8le(cpustate->io, M37710_PORT4, data); return; - break; case 0xb: // p5 memory_write_byte_8le(cpustate->io, M37710_PORT5, data); return; - break; case 0xe: // p6 memory_write_byte_8le(cpustate->io, M37710_PORT6, data); return; - break; case 0xf: // p7 memory_write_byte_8le(cpustate->io, M37710_PORT7, data); return; - break; case 0x12: // p8 memory_write_byte_8le(cpustate->io, M37710_PORT8, data); return; - break; case 0x40: // count start for (i = 0; i < 8; i++) @@ -546,11 +510,9 @@ static void m37710_internal_w(m37710i_cpu_struct *cpustate, int offset, UINT8 da cpustate->m37710_regs[offset] = data; return; - break; case 0x60: // watchdog reset return; - break; } cpustate->m37710_regs[offset] = data; diff --git a/src/emu/cpu/m37710/m37710op.h b/src/emu/cpu/m37710/m37710op.h index 5e84c6ceba6..22d901c557e 100644 --- a/src/emu/cpu/m37710/m37710op.h +++ b/src/emu/cpu/m37710/m37710op.h @@ -2862,7 +2862,6 @@ TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *cpustate, int line, int stat cpustate->m37710_regs[m37710_irq_levels[line]] |= 8; } return; - break; case ASSERT_LINE: case PULSE_LINE: case HOLD_LINE: diff --git a/src/emu/cpu/mb86233/mb86233.c b/src/emu/cpu/mb86233/mb86233.c index abe4e2bf65a..102df4b1434 100644 --- a/src/emu/cpu/mb86233/mb86233.c +++ b/src/emu/cpu/mb86233/mb86233.c @@ -204,7 +204,6 @@ static int COND( mb86233_state *cpustate, UINT32 cond ) case 0x16: /* always */ return 1; - break; default: logerror( "TGP: Unknown condition code (cc=%d) at PC:%x\n", cond, GETPC()); @@ -594,60 +593,46 @@ static UINT32 GETREGS( mb86233_state *cpustate, UINT32 reg, int source ) { case 0x10: /* A */ return GETA().u; - break; case 0x11: /* A.e */ return (GETA().u >> 23) & 0xff; - break; case 0x12: /* A.m */ return (GETA().u & 0x7fffff) | ((GETA().u&0x80000000) >> 8); - break; case 0x13: /* B */ return GETB().u; - break; case 0x14: /* B.e */ return (GETB().u >> 23) & 0xff; - break; case 0x15: /* B.m */ return (GETB().u & 0x7fffff) | ((GETB().u&0x80000000) >> 8); - break; case 0x19: /* D */ return GETD().u; - break; case 0x1A: /* D.e */ return (GETD().u >> 23) & 0xff; - break; case 0x1B: /* D.m */ return (GETD().u & 0x7fffff) | ((GETD().u&0x80000000) >> 8); - break; case 0x1C: /* P */ return GETP().u; - break; case 0x1D: /* P.e */ return (GETP().u >> 23) & 0xff; - break; case 0x1E: /* P.m */ return (GETP().u & 0x7fffff) | ((GETP().u&0x80000000) >> 8); - break; case 0x1F: /* Shift */ return GETSHIFT(); - break; case 0x20: /* Parallel Port */ logerror( "TGP: Parallel port read at PC:%04x\n", GETPC() ); return 0; - break; case 0x21: /* FIn */ { @@ -664,19 +649,15 @@ static UINT32 GETREGS( mb86233_state *cpustate, UINT32 reg, int source ) GETFIFOWAIT() = 1; return 0; } - break; case 0x22: /* FOut */ return 0; - break; case 0x23: /* EB */ return GETEB(); - break; case 0x34: return GETREPCNT(); - break; default: logerror( "TGP: Unknown GETREG (%d) at PC=%04x\n", reg, GETPC() ); diff --git a/src/emu/cpu/se3208/se3208.c b/src/emu/cpu/se3208/se3208.c index c9f5cc23a5b..d033df93958 100644 --- a/src/emu/cpu/se3208/se3208.c +++ b/src/emu/cpu/se3208/se3208.c @@ -1464,7 +1464,6 @@ static _OP DecodeOp(UINT16 Opcode) break; case 0x1: return LERI; - break; case 0x2: { switch(EXTRACT(Opcode,11,13)) diff --git a/src/emu/cpu/se3208/se3208dis.c b/src/emu/cpu/se3208/se3208dis.c index 8bff0d59470..66563ffcf5a 100644 --- a/src/emu/cpu/se3208/se3208dis.c +++ b/src/emu/cpu/se3208/se3208dis.c @@ -1171,7 +1171,6 @@ static _OP DecodeOp(UINT16 Opcode) break; case 0x1: return LERI; - break; case 0x2: { switch(EXTRACT(Opcode,11,13)) diff --git a/src/emu/cpu/sh2/sh2drc.c b/src/emu/cpu/sh2/sh2drc.c index 386399d92a5..5b4b1f022c6 100644 --- a/src/emu/cpu/sh2/sh2drc.c +++ b/src/emu/cpu/sh2/sh2drc.c @@ -1661,7 +1661,6 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil { case 0: return generate_group_0(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 1: // MOVLS4 scratch = (opcode & 0x0f) * 4; @@ -1673,17 +1672,13 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2: return generate_group_2(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 3: return generate_group_3(sh2, block, compiler, desc, opcode); - break; case 4: return generate_group_4(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 5: // MOVLL4 scratch = (opcode & 0x0f) * 4; @@ -1695,22 +1690,18 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 6: return generate_group_6(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 7: // ADDI scratch = opcode & 0xff; scratch2 = (UINT32)(INT32)(INT16)(INT8)scratch; UML_ADD(block, R32(Rn), R32(Rn), IMM(scratch2)); // add Rn, Rn, scratch2 return TRUE; - break; case 8: return generate_group_8(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 9: // MOVWI scratch = (desc->pc + 2) + ((opcode & 0xff) * 2) + 2; @@ -1731,7 +1722,6 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 10: // BRA generate_delay_slot(sh2, block, compiler, desc); @@ -1743,7 +1733,6 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // hashjmp sh2->ea return TRUE; - break; case 11: // BSR // panicstr @ 403da22 relies on the delay slot clobbering the PR set by a BSR, so @@ -1758,11 +1747,9 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // hashjmp sh2->ea return TRUE; - break; case 12: return generate_group_12(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 13: // MOVLI scratch = ((desc->pc + 4) & ~3) + ((opcode & 0xff) * 4); @@ -1782,18 +1769,15 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 14: // MOVI scratch = opcode & 0xff; scratch2 = (UINT32)(INT32)(INT16)(INT8)scratch; UML_MOV(block, R32(Rn), IMM(scratch2)); return TRUE; - break; case 15: // NOP return TRUE; - break; } return FALSE; @@ -1820,12 +1804,10 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi case 0x3a: // NOP(); case 0x3b: // NOP(); return TRUE; - break; case 0x02: // STCSR(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->sr)); return TRUE; - break; case 0x03: // BSRF(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -1855,7 +1837,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x05: // MOVWS0(Rm, Rn); case 0x15: // MOVWS0(Rm, Rn); @@ -1869,7 +1850,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x06: // MOVLS0(Rm, Rn); case 0x16: // MOVLS0(Rm, Rn); @@ -1882,7 +1862,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x07: // MULL(Rm, Rn); case 0x17: // MULL(Rm, Rn); @@ -1898,12 +1877,10 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi case 0x08: // CLRT(); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) return TRUE; - break; case 0x0a: // STSMACH(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->mach)); // mov Rn, mach return TRUE; - break; case 0x0b: // RTS(); UML_MOV(block, MEM(&sh2->target), MEM(&sh2->pr)); // mov target, pr (in case of d-slot shenanigans) @@ -1913,7 +1890,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); return TRUE; - break; case 0x0c: // MOVBL0(Rm, Rn); case 0x1c: // MOVBL0(Rm, Rn); @@ -1926,7 +1902,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x0d: // MOVWL0(Rm, Rn); case 0x1d: // MOVWL0(Rm, Rn); @@ -1939,7 +1914,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x0e: // MOVLL0(Rm, Rn); case 0x1e: // MOVLL0(Rm, Rn); @@ -1952,7 +1926,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x0f: // MAC_L(Rm, Rn); case 0x1f: // MAC_L(Rm, Rn); @@ -1971,22 +1944,18 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi case 0x12: // STCGBR(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->gbr)); // mov Rn, gbr return TRUE; - break; case 0x18: // SETT(); UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T return TRUE; - break; case 0x19: // DIV0U(); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~(M|Q|T))); // and sr, sr, ~(M|Q|T) return TRUE; - break; case 0x1a: // STSMACL(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->macl)); // mov Rn, macl return TRUE; - break; case 0x1b: // SLEEP(); // inlined special version of generate_update_cycles here @@ -2024,12 +1993,10 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi } return TRUE; - break; case 0x22: // STCVBR(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->vbr)); // mov Rn, vbr return TRUE; - break; case 0x23: // BRAF(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -2048,17 +2015,14 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_MOV(block, MEM(&sh2->macl), IMM(0)); // mov macl, #0 UML_MOV(block, MEM(&sh2->mach), IMM(0)); // mov mach, #0 return TRUE; - break; case 0x29: // MOVT(Rn); UML_AND(block, R32(Rn), MEM(&sh2->sr), IMM(T)); // and Rn, sr, T return TRUE; - break; case 0x2a: // STSPR(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->pr)); // mov Rn, pr return TRUE; - break; case 0x2b: // RTE(); generate_delay_slot(sh2, block, compiler, desc); @@ -2079,7 +2043,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_HASHJMP(block, IMM(0), MEM(&sh2->pc), sh2->nocode); // and jump to the "resume PC" return TRUE; - break; } return FALSE; @@ -2098,7 +2061,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 1: // MOVWS(Rm, Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2109,7 +2071,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2: // MOVLS(Rm, Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2119,11 +2080,9 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 3: // NOP(); return TRUE; - break; case 4: // MOVBM(Rm, Rn); UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm @@ -2134,7 +2093,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 5: // MOVWM(Rm, Rn); UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm @@ -2145,7 +2103,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 6: // MOVLM(Rm, Rn); UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm @@ -2156,7 +2113,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 13: // XTRCT(Rm, Rn); UML_SHL(block, IREG(0), R32(Rm), IMM(16)); // shl r0, Rm, #16 @@ -2167,7 +2123,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_OR(block, R32(Rn), IREG(0), IREG(1)); // or Rn, r0, r1 return TRUE; - break; case 7: // DIV0S(Rm, Rn); UML_MOV(block, IREG(0), MEM(&sh2->sr)); // move r0, sr @@ -2193,7 +2148,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sr, r0 return TRUE; - break; case 8: // TST(Rm, Rn); UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) @@ -2205,7 +2159,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 return TRUE; - break; case 12: // CMPSTR(Rm, Rn); UML_XOR(block, IREG(0), R32(Rn), R32(Rm)); // xor r0, Rn, Rm (temp) @@ -2237,36 +2190,30 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum+1: return TRUE; - break; case 9: // AND(Rm, Rn); UML_AND(block, R32(Rn), R32(Rn), R32(Rm)); // and Rn, Rn, Rm return TRUE; - break; case 10: // XOR(Rm, Rn); UML_XOR(block, R32(Rn), R32(Rn), R32(Rm)); // xor Rn, Rn, Rm return TRUE; - break; case 11: // OR(Rm, Rn); UML_OR(block, R32(Rn), R32(Rn), R32(Rm)); // or Rn, Rn, Rm return TRUE; - break; case 14: // MULU(Rm, Rn); UML_AND(block, IREG(0), R32(Rm), IMM(0xffff)); // and r0, Rm, 0xffff UML_AND(block, IREG(1), R32(Rn), IMM(0xffff)); // and r1, Rn, 0xffff UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->ea), IREG(0), IREG(1)); // mulu macl, ea, r0, r1 return TRUE; - break; case 15: // MULS(Rm, Rn); UML_SEXT(block, IREG(0), R32(Rm), WORD); // sext r0, Rm UML_SEXT(block, IREG(1), R32(Rn), WORD); // sext r1, Rn UML_MULS(block, MEM(&sh2->macl), MEM(&sh2->ea), IREG(0), IREG(1)); // muls macl, ea, r0, r1 return TRUE; - break; } return FALSE; @@ -2281,40 +2228,34 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_E, IREG(0)); // set E, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 2: // CMPHS(Rm, Rn); (unsigned greater than or equal) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm UML_SETc(block, IF_AE, IREG(0)); // set AE, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 3: // CMPGE(Rm, Rn); (signed greater than or equal) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm UML_SETc(block, IF_GE, IREG(0)); // set GE, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 6: // CMPHI(Rm, Rn); (unsigned greater than) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm UML_SETc(block, IF_A, IREG(0)); // set A, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 7: // CMPGT(Rm, Rn); (signed greater than) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm UML_SETc(block, IF_G, IREG(0)); // set G, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 1: // NOP(); case 9: // NOP(); return TRUE; - break; case 4: // DIV1(Rm, Rn); save_fast_iregs(sh2, block); @@ -2322,7 +2263,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_CALLC(block, cfunc_DIV1, sh2); load_fast_iregs(sh2, block); return TRUE; - break; case 5: // DMULU(Rm, Rn); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -2343,12 +2283,10 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi case 8: // SUB(Rm, Rn); UML_SUB(block, R32(Rn), R32(Rn), R32(Rm)); // sub Rn, Rn, Rm return TRUE; - break; case 12: // ADD(Rm, Rn); UML_ADD(block, R32(Rn), R32(Rn), R32(Rm)); // add Rn, Rn, Rm return TRUE; - break; case 10: // SUBC(Rm, Rn); UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry = T (T is bit 0 of SR) @@ -2356,7 +2294,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // setc i0, C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T return TRUE; - break; case 11: // SUBV(Rm, Rn); #if ADDSUBV_DIRECT @@ -2370,7 +2307,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi load_fast_iregs(sh2, block); #endif return TRUE; - break; case 14: // ADDC(Rm, Rn); UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry = T (T is bit 0 of SR) @@ -2378,7 +2314,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // setc i0, C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T return TRUE; - break; case 15: // ADDV(Rm, Rn); #if ADDSUBV_DIRECT @@ -2392,7 +2327,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi load_fast_iregs(sh2, block); #endif return TRUE; - break; } return FALSE; } @@ -2406,28 +2340,24 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T return TRUE; - break; case 0x01: // SHLR(Rn); UML_SHR(block, R32(Rn), R32(Rn), IMM(1)); // shr Rn, Rn, 1 UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T return TRUE; - break; case 0x04: // ROTL(Rn); UML_ROL(block, R32(Rn), R32(Rn), IMM(1)); // rol Rn, Rn, 1 UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T return TRUE; - break; case 0x05: // ROTR(Rn); UML_ROR(block, R32(Rn), R32(Rn), IMM(1)); // ror Rn, Rn, 1 UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T return TRUE; - break; case 0x02: // STSMMACH(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 @@ -2439,7 +2369,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x03: // STCMSR(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 @@ -2451,7 +2380,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x06: // LDSMMACH(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2463,7 +2391,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x07: // LDCMSR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2476,42 +2403,35 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; + case 0x08: // SHLL2(Rn); UML_SHL(block, R32(Rn), R32(Rn), IMM(2)); return TRUE; - break; case 0x09: // SHLR2(Rn); UML_SHR(block, R32(Rn), R32(Rn), IMM(2)); return TRUE; - break; case 0x18: // SHLL8(Rn); UML_SHL(block, R32(Rn), R32(Rn), IMM(8)); return TRUE; - break; case 0x19: // SHLR8(Rn); UML_SHR(block, R32(Rn), R32(Rn), IMM(8)); return TRUE; - break; case 0x28: // SHLL16(Rn); UML_SHL(block, R32(Rn), R32(Rn), IMM(16)); return TRUE; - break; case 0x29: // SHLR16(Rn); UML_SHR(block, R32(Rn), R32(Rn), IMM(16)); return TRUE; - break; case 0x0a: // LDSMACH(Rn); UML_MOV(block, MEM(&sh2->mach), R32(Rn)); // mov mach, Rn return TRUE; - break; case 0x0b: // JSR(Rn); UML_MOV(block, MEM(&sh2->target), R32(Rn)); // mov target, Rn @@ -2523,7 +2443,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // and do the jump return TRUE; - break; case 0x0e: // LDCSR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2532,7 +2451,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi compiler->checkints = TRUE; return TRUE; - break; case 0x0f: // MAC_W(Rm, Rn); case 0x1f: // MAC_W(Rm, Rn); @@ -2543,7 +2461,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_CALLC(block, cfunc_MAC_W, sh2); load_fast_iregs(sh2, block); return TRUE; - break; case 0x10: // DT(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -2571,7 +2488,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 return TRUE; - break; case 0x15: // CMPPL(Rn); UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) @@ -2586,7 +2502,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // desc->pc: UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 return TRUE; - break; case 0x12: // STSMMACL(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 @@ -2598,7 +2513,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x13: // STCMGBR(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 @@ -2610,7 +2524,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x16: // LDSMMACL(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2622,7 +2535,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x17: // LDCMGBR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2634,12 +2546,10 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x1a: // LDSMACL(Rn); UML_MOV(block, MEM(&sh2->macl), R32(Rn)); // mov macl, Rn return TRUE; - break; case 0x1b: // TAS(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2663,12 +2573,10 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x1e: // LDCGBR(Rn); UML_MOV(block, MEM(&sh2->gbr), R32(Rn)); // mov gbr, Rn return TRUE; - break; case 0x20: // SHAL(Rn); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T @@ -2677,7 +2585,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IREG(0)); // or sr, sr, r0 UML_SHL(block, R32(Rn), R32(Rn), IMM(1)); // shl Rn, Rn, 1 return TRUE; - break; case 0x21: // SHAR(Rn); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T @@ -2685,7 +2592,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IREG(0)); // or sr, sr, r0 UML_SAR(block, R32(Rn), R32(Rn), IMM(1)); // sar Rn, Rn, 1 return TRUE; - break; case 0x22: // STSMPR(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, 4 @@ -2697,7 +2603,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x23: // STCMVBR(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, 4 @@ -2709,7 +2614,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x24: // ROTCL(Rn); UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry sr,0 @@ -2717,7 +2621,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T return TRUE; - break; case 0x25: // ROTCR(Rn); UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry sr,0 @@ -2725,7 +2628,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T return TRUE; - break; case 0x26: // LDSMPR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2737,7 +2639,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x27: // LDCMVBR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2749,12 +2650,10 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x2a: // LDSPR(Rn); UML_MOV(block, MEM(&sh2->pr), R32(Rn)); // mov sh2->pr, Rn return TRUE; - break; case 0x2b: // JMP(Rn); UML_MOV(block, MEM(&sh2->target), R32(Rn)); // mov target, Rn @@ -2764,12 +2663,10 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp (target) return TRUE; - break; case 0x2e: // LDCVBR(Rn); UML_MOV(block, MEM(&sh2->vbr), R32(Rn)); // mov vbr, Rn return TRUE; - break; case 0x0c: // NOP(); case 0x0d: // NOP(); @@ -2794,8 +2691,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi case 0x3d: // NOP(); case 0x3e: // NOP(); return TRUE; - break; - } return FALSE; @@ -2814,7 +2709,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 1: // MOVWL(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2825,7 +2719,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2: // MOVLL(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2836,47 +2729,38 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 3: // MOV(Rm, Rn); UML_MOV(block, R32(Rn), R32(Rm)); // mov Rn, Rm return TRUE; - break; case 7: // NOT(Rm, Rn); UML_XOR(block, R32(Rn), R32(Rm), IMM(0xffffffff)); // xor Rn, Rm, 0xffffffff return TRUE; - break; case 9: // SWAPW(Rm, Rn); UML_ROL(block, R32(Rn), R32(Rm), IMM(16)); // rol Rn, Rm, 16 return TRUE; - break; case 11: // NEG(Rm, Rn); UML_SUB(block, R32(Rn), IMM(0), R32(Rm)); // sub Rn, 0, Rm return TRUE; - break; case 12: // EXTUB(Rm, Rn); UML_AND(block, R32(Rn), R32(Rm), IMM(0x000000ff)); // and Rn, Rm, 0xff return TRUE; - break; case 13: // EXTUW(Rm, Rn); UML_AND(block, R32(Rn), R32(Rm), IMM(0x0000ffff)); // and Rn, Rm, 0xffff return TRUE; - break; case 14: // EXTSB(Rm, Rn); UML_SEXT(block, R32(Rn), R32(Rm), BYTE); // sext Rn, Rm, BYTE return TRUE; - break; case 15: // EXTSW(Rm, Rn); UML_SEXT(block, R32(Rn), R32(Rm), WORD); // sext Rn, Rm, WORD return TRUE; - break; case 4: // MOVBP(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2893,7 +2777,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 5: // MOVWP(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2910,7 +2793,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 6: // MOVLP(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2927,7 +2809,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 8: // SWAPB(Rm, Rn); UML_AND(block, IREG(0), R32(Rm), IMM(0xffff0000)); // and r0, Rm, #0xffff0000 @@ -2938,7 +2819,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_OR(block, IREG(0), IREG(0), IREG(1)); // or r0, r0, r1 UML_OR(block, R32(Rn), IREG(0), IREG(2)); // or Rn, r0, r2 return TRUE; - break; case 10: // NEGC(Rm, Rn); UML_MOV(block, IREG(0), MEM(&sh2->sr)); // mov r0, sr (save SR) @@ -2953,7 +2833,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; } return FALSE; @@ -2976,7 +2855,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 1 << 8: // MOVWS4(opcode & 0x0f, Rm); udisp = (opcode & 0x0f) * 2; @@ -2987,7 +2865,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2<< 8: // NOP(); case 3<< 8: // NOP(); @@ -2997,7 +2874,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi case 12<< 8: // NOP(); case 14<< 8: // NOP(); return TRUE; - break; case 4<< 8: // MOVBL4(Rm, opcode & 0x0f); udisp = opcode & 0x0f; @@ -3009,7 +2885,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 5<< 8: // MOVWL4(Rm, opcode & 0x0f); udisp = (opcode & 0x0f)*2; @@ -3021,7 +2896,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 8<< 8: // CMPIM(opcode & 0xff); UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) @@ -3035,7 +2909,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 return TRUE; - break; case 9<< 8: // BT(opcode & 0xff); UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T @@ -3049,7 +2922,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; case 11<< 8: // BF(opcode & 0xff); UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T @@ -3063,7 +2935,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; case 13<< 8: // BTS(opcode & 0xff); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -3126,7 +2997,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 1<<8: // MOVWSG(opcode & 0xff); scratch = (opcode & 0xff) * 2; @@ -3137,7 +3007,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2<<8: // MOVLSG(opcode & 0xff); scratch = (opcode & 0xff) * 4; @@ -3148,7 +3017,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 3<<8: // TRAPA(opcode & 0xff); scratch = (opcode & 0xff) * 4; @@ -3169,7 +3037,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp UML_HASHJMP(block, IMM(0), IREG(0), sh2->nocode); // jmp (r0) return TRUE; - break; case 4<<8: // MOVBLG(opcode & 0xff); scratch = (opcode & 0xff); @@ -3180,7 +3047,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 5<<8: // MOVWLG(opcode & 0xff); scratch = (opcode & 0xff) * 2; @@ -3191,7 +3057,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 6<<8: // MOVLLG(opcode & 0xff); scratch = (opcode & 0xff) * 4; @@ -3202,7 +3067,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 7<<8: // MOVA(opcode & 0xff); scratch = (opcode & 0xff) * 4; @@ -3210,7 +3074,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp UML_MOV(block, R32(0), IMM(scratch)); // mov R0, scratch return TRUE; - break; case 8<<8: // TSTI(opcode & 0xff); scratch = opcode & 0xff; @@ -3224,22 +3087,18 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; case 9<<8: // ANDI(opcode & 0xff); UML_AND(block, R32(0), R32(0), IMM(opcode & 0xff)); // and r0, r0, opcode & 0xff return TRUE; - break; case 10<<8: // XORI(opcode & 0xff); UML_XOR(block, R32(0), R32(0), IMM(opcode & 0xff)); // xor r0, r0, opcode & 0xff return TRUE; - break; case 11<<8: // ORI(opcode & 0xff); UML_OR(block, R32(0), R32(0), IMM(opcode & 0xff)); // or r0, r0, opcode & 0xff return TRUE; - break; case 12<<8: // TSTM(opcode & 0xff); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T (clear the T bit) @@ -3253,7 +3112,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; case 13<<8: // ANDM(opcode & 0xff); UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr @@ -3264,7 +3122,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp SETEA(0); UML_CALLH(block, sh2->write8); // write8 return TRUE; - break; case 14<<8: // XORM(opcode & 0xff); UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr @@ -3275,7 +3132,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp SETEA(0); UML_CALLH(block, sh2->write8); // write8 return TRUE; - break; case 15<<8: // ORM(opcode & 0xff); UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr @@ -3286,7 +3142,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp SETEA(0); UML_CALLH(block, sh2->write8); // write8 return TRUE; - break; } return FALSE; diff --git a/src/emu/cpu/sh2/sh2fe.c b/src/emu/cpu/sh2/sh2fe.c index 22fc9c2c47b..402c13dae26 100644 --- a/src/emu/cpu/sh2/sh2fe.c +++ b/src/emu/cpu/sh2/sh2fe.c @@ -48,52 +48,42 @@ int sh2_describe(void *param, opcode_desc *desc, const opcode_desc *prev) { case 0: return describe_group_0(context, desc, prev, opcode); - break; case 1: // MOVLS4 desc->regin[0] |= REGFLAG_R(Rn) | REGFLAG_R(Rm); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 2: return describe_group_2(context, desc, prev, opcode); - break; case 3: return describe_group_3(context, desc, prev, opcode); - break; case 4: return describe_group_4(context, desc, prev, opcode); - break; case 5: // MOVLL4 desc->regin[0] |= REGFLAG_R(Rm); desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 6: return describe_group_6(context, desc, prev, opcode); - break; case 7: // ADDI desc->regin[0] |= REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 8: return describe_group_8(context, desc, prev, opcode); - break; case 9: // MOVWI desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 11: // BSR desc->regout[1] |= REGFLAG_PR; @@ -108,26 +98,21 @@ int sh2_describe(void *param, opcode_desc *desc, const opcode_desc *prev) desc->cycles = 2; return TRUE; } - break; case 12: return describe_group_12(context, desc, prev, opcode); - break; case 13: // MOVLI desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 14: // MOVI desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 15: // NOP return TRUE; - break; } return FALSE; @@ -154,12 +139,10 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * case 0x3a: // NOP(); case 0x3b: // NOP(); return TRUE; - break; case 0x02: // STCSR(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x03: // BSRF(Rn); desc->regout[1] |= REGFLAG_PR; @@ -169,7 +152,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->delayslots = 1; return TRUE; - break; case 0x04: // MOVBS0(Rm, Rn); case 0x05: // MOVWS0(Rm, Rn); @@ -186,7 +168,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn) | REGFLAG_R(0); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x07: // MULL(Rm, Rn); case 0x17: // MULL(Rm, Rn); @@ -196,18 +177,15 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL; desc->cycles = 2; return TRUE; - break; case 0x08: // CLRT(); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x0a: // STSMACH(Rn); desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_MACH; return TRUE; - break; case 0x0b: // RTS(); desc->regin[1] |= REGFLAG_PR; @@ -218,7 +196,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 2; return TRUE; - break; case 0x0c: // MOVBL0(Rm, Rn); case 0x0d: // MOVWL0(Rm, Rn); @@ -236,7 +213,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x0f: // MAC_L(Rm, Rn); case 0x1f: // MAC_L(Rm, Rn); @@ -246,40 +222,33 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; desc->cycles = 3; return TRUE; - break; case 0x12: // STCGBR(Rn); desc->regout[0] |= REGFLAG_R(Rn); desc->regin[1] |= REGFLAG_GBR; return TRUE; - break; case 0x18: // SETT(); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x19: // DIV0U(); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x1a: // STSMACL(Rn); desc->regin[1] |= REGFLAG_MACL; desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x1b: // SLEEP(); desc->cycles = 3; return TRUE; - break; case 0x22: // STCVBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_VBR; return TRUE; - break; case 0x23: // BRAF(Rn); desc->regin[0] |= REGFLAG_R(Rm); @@ -288,24 +257,20 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->delayslots = 1; desc->cycles = 2; return TRUE; - break; case 0x28: // CLRMAC(); desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; return TRUE; - break; case 0x29: // MOVT(Rn); desc->regin[1] |= REGFLAG_SR; desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x2a: // STSPR(Rn); desc->regin[1] |= REGFLAG_PR; desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x2b: // RTE(); desc->regin[0] |= REGFLAG_R(15); @@ -317,7 +282,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 4; return TRUE; - break; } return FALSE; @@ -333,11 +297,9 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 3: // NOP(); return TRUE; - break; case 4: // MOVBM(Rm, Rn); case 5: // MOVWM(Rm, Rn); @@ -347,7 +309,6 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 7: // DIV0S(Rm, Rn); case 8: // TST(Rm, Rn); @@ -355,7 +316,6 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 9: // AND(Rm, Rn); case 10: // XOR(Rm, Rn); @@ -363,7 +323,6 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 14: // MULU(Rm, Rn); case 15: // MULS(Rm, Rn); @@ -371,7 +330,6 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; desc->cycles = 2; return TRUE; - break; } return FALSE; @@ -389,19 +347,16 @@ static int describe_group_3(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 1: // NOP(); case 9: // NOP(); return TRUE; - break; case 4: // DIV1(Rm, Rn); desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 5: // DMULU(Rm, Rn); case 13: // DMULS(Rm, Rn); @@ -409,14 +364,12 @@ static int describe_group_3(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; desc->cycles = 2; return TRUE; - break; case 8: // SUB(Rm, Rn); case 12: // ADD(Rm, Rn); desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 10: // SUBC(Rm, Rn); case 11: // SUBV(Rm, Rn); @@ -427,7 +380,6 @@ static int describe_group_3(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; } return FALSE; } @@ -444,7 +396,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x02: // STSMMACH(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -452,7 +403,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x03: // STCMSR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -460,7 +410,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 2; desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x06: // LDSMMACH(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -468,7 +417,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACH; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x07: // LDCMSR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -477,7 +425,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 3; desc->flags |= OPFLAG_READS_MEMORY | OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE; return TRUE; - break; case 0x08: // SHLL2(Rn); case 0x09: // SHLR2(Rn); @@ -488,13 +435,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x0a: // LDSMACH(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_MACH; return TRUE; - break; case 0x0b: // JSR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -503,14 +448,12 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->targetpc = BRANCH_TARGET_DYNAMIC; desc->delayslots = 1; return TRUE; - break; case 0x0e: // LDCSR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; desc->flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE; return TRUE; - break; case 0x0f: // MAC_W(Rm, Rn); case 0x1f: // MAC_W(Rm, Rn); @@ -522,7 +465,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; desc->cycles = 3; return TRUE; - break; case 0x10: // DT(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -530,7 +472,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x11: // CMPPZ(Rn); case 0x15: // CMPPL(Rn); @@ -538,7 +479,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[1] |= REGFLAG_SR; desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x12: // STSMMACL(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -546,7 +486,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x13: // STCMGBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -554,7 +493,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x16: // LDSMMACL(Rn); desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); @@ -562,7 +500,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x17: // LDCMGBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -570,13 +507,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_GBR; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x1a: // LDSMACL(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_MACL; return TRUE; - break; case 0x1b: // TAS(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -585,13 +520,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 4; desc->flags |= OPFLAG_READS_MEMORY | OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x1e: // LDCGBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_GBR; return TRUE; - break; case 0x20: // SHAL(Rn); case 0x21: // SHAR(Rn); @@ -599,7 +532,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x22: // STSMPR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -607,7 +539,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x23: // STCMVBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -615,7 +546,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x24: // ROTCL(Rn); case 0x25: // ROTCR(Rn); @@ -624,7 +554,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x26: // LDSMPR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -632,7 +561,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_PR; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x27: // LDCMVBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -640,13 +568,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_VBR; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x2a: // LDSPR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_PR; return TRUE; - break; case 0x2b: // JMP(Rm); desc->regin[0] |= REGFLAG_R(Rm); @@ -654,13 +580,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->targetpc = BRANCH_TARGET_DYNAMIC; desc->delayslots = 1; return TRUE; - break; case 0x2e: // LDCVBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_VBR; return TRUE; - break; case 0x0c: // NOP(); case 0x0d: // NOP(); @@ -685,8 +609,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * case 0x3d: // NOP(); case 0x3e: // NOP(); return TRUE; - break; - } return FALSE; @@ -710,7 +632,6 @@ static int describe_group_6(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 4: // MOVBP(Rm, Rn); case 5: // MOVWP(Rm, Rn); @@ -719,20 +640,17 @@ static int describe_group_6(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 8: // SWAPB(Rm, Rn); desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 10: // NEGC(Rm, Rn); desc->regin[0] |= REGFLAG_R(Rm); desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; } return FALSE; } @@ -748,7 +666,6 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(0); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 2<< 8: // NOP(); case 3<< 8: // NOP(); @@ -758,7 +675,6 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * case 12<< 8: // NOP(); case 14<< 8: // NOP(); return TRUE; - break; case 4<< 8: // MOVBL4(Rm, opcode & 0x0f); case 5<< 8: // MOVWL4(Rm, opcode & 0x0f); @@ -766,14 +682,12 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(0); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 8<< 8: // CMPIM(opcode & 0xff); desc->regin[0] |= REGFLAG_R(Rm); desc->regin[1] |= REGFLAG_SR; desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 9<< 8: // BT(opcode & 0xff); case 11<< 8: // BF(opcode & 0xff); @@ -782,7 +696,6 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * disp = ((INT32)opcode << 24) >> 24; desc->targetpc = (desc->pc + 2) + disp * 2 + 2; return TRUE; - break; case 13<< 8: // BTS(opcode & 0xff); case 15<< 8: // BFS(opcode & 0xff); @@ -792,7 +705,6 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * desc->targetpc = (desc->pc + 2) + disp * 2 + 2; desc->delayslots = 1; return TRUE; - break; } return FALSE; @@ -808,7 +720,6 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->regin[0] |= REGFLAG_R(0); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 3<<8: // TRAPA(opcode & 0xff); desc->regin[0] |= REGFLAG_R(15); @@ -818,7 +729,6 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->targetpc = BRANCH_TARGET_DYNAMIC; desc->flags |= OPFLAG_READS_MEMORY | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE; return TRUE; - break; case 4<<8: // MOVBLG(opcode & 0xff); case 5<<8: // MOVWLG(opcode & 0xff); @@ -827,14 +737,12 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->regout[0] |= REGFLAG_R(0); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 8<<8: // TSTI(opcode & 0xff); desc->regin[0] |= REGFLAG_R(0); desc->regin[1] |= REGFLAG_SR; desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 9<<8: // ANDI(opcode & 0xff); case 10<<8: // XORI(opcode & 0xff); @@ -842,7 +750,6 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->regin[0] |= REGFLAG_R(0); desc->regout[0] |= REGFLAG_R(0); return TRUE; - break; case 12<<8: // TSTM(opcode & 0xff); case 13<<8: // ANDM(opcode & 0xff); @@ -853,7 +760,6 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->regout[1] |= REGFLAG_SR; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; } return FALSE; diff --git a/src/emu/cpu/tms9900/9900dasm.c b/src/emu/cpu/tms9900/9900dasm.c index 3c7b787d3c9..c4dc1d1d2d1 100644 --- a/src/emu/cpu/tms9900/9900dasm.c +++ b/src/emu/cpu/tms9900/9900dasm.c @@ -325,10 +325,8 @@ static int print_arg (char *dest, int mode, int arg, const UINT8 *opram, unsigne { case 0x0: /* workspace register */ return sprintf (dest, "R%d", arg); - break; case 0x1: /* workspace register indirect */ return sprintf (dest, "*R%d", arg); - break; case 0x2: /* symbolic|indexed */ base = readop_arg(opram, pc); if (arg) /* indexed */ @@ -338,7 +336,6 @@ static int print_arg (char *dest, int mode, int arg, const UINT8 *opram, unsigne break; case 0x3: /* workspace register indirect auto increment */ return sprintf (dest, "*R%d+", arg); - break; } return 0; diff --git a/src/emu/cpu/v60/am1.c b/src/emu/cpu/v60/am1.c index 77fb8137dec..de69fd9779b 100644 --- a/src/emu/cpu/v60/am1.c +++ b/src/emu/cpu/v60/am1.c @@ -1058,17 +1058,14 @@ static UINT32 am1Immediate(v60_state *cpustate) case 0: cpustate->amout = OpRead8(cpustate->program, cpustate->modadd + 1); return 2; - break; case 1: cpustate->amout = OpRead16(cpustate->program, cpustate->modadd + 1); return 3; - break; case 2: cpustate->amout = OpRead32(cpustate->program, cpustate->modadd + 1); return 5; - break; } // It should not be here! Written to avoid warning diff --git a/src/emu/sound/es5503.c b/src/emu/sound/es5503.c index 79d1fb80346..8e1fa24060d 100644 --- a/src/emu/sound/es5503.c +++ b/src/emu/sound/es5503.c @@ -287,27 +287,21 @@ READ8_HANDLER(es5503_reg_0_r) { case 0: // freq lo return (chip->oscillators[osc].freq & 0xff); - break; case 0x20: // freq hi return (chip->oscillators[osc].freq >> 8); - break; case 0x40: // volume return chip->oscillators[osc].vol; - break; case 0x60: // data return chip->oscillators[osc].data; - break; case 0x80: // wavetable pointer return (chip->oscillators[osc].wavetblpointer>>8) & 0xff; - break; case 0xa0: // oscillator control return chip->oscillators[osc].control; - break; case 0xc0: // bank select / wavetable size / resolution retval = 0; @@ -319,7 +313,6 @@ READ8_HANDLER(es5503_reg_0_r) retval |= (chip->oscillators[osc].wavetblsize<<3); retval |= chip->oscillators[osc].resolution; return retval; - break; } } else // global registers @@ -364,11 +357,9 @@ READ8_HANDLER(es5503_reg_0_r) } return retval; - break; case 0xe1: // oscillator enable return chip->oscsenabled<<1; - break; case 0xe2: // A/D converter if (chip->adc_read) diff --git a/src/emu/sound/iremga20.c b/src/emu/sound/iremga20.c index a5f5a52b392..1a1e04078f6 100644 --- a/src/emu/sound/iremga20.c +++ b/src/emu/sound/iremga20.c @@ -195,7 +195,6 @@ READ16_HANDLER( irem_ga20_r ) { case 7: // voice status. bit 0 is 1 if active. (routine around 0xccc in rtypeleo) return chip->channel[channel].play ? 1 : 0; - break; default: logerror("GA20: read unk. register %d, channel %d\n", offset & 0xf, channel); diff --git a/src/emu/sound/ymf262.c b/src/emu/sound/ymf262.c index c699cda7eac..9980e0a3701 100644 --- a/src/emu/sound/ymf262.c +++ b/src/emu/sound/ymf262.c @@ -1635,7 +1635,7 @@ static void OPL3WriteReg(OPL3 *chip, int r, int v) { case 0x101: /* test register */ return; - break; + case 0x104: /* 6 channels enable */ { UINT8 prev; @@ -1675,7 +1675,7 @@ static void OPL3WriteReg(OPL3 *chip, int r, int v) } return; - break; + case 0x105: /* OPL3 extensions enable register */ chip->OPL3_mode = v&0x01; /* OPL3 mode when bit0=1 otherwise it is OPL2 mode */ @@ -1689,7 +1689,6 @@ static void OPL3WriteReg(OPL3 *chip, int r, int v) */ return; - break; default: if (r < 0x120) diff --git a/src/mame/audio/taitosnd.c b/src/mame/audio/taitosnd.c index 953b3c48fa2..56c514affcc 100644 --- a/src/mame/audio/taitosnd.c +++ b/src/mame/audio/taitosnd.c @@ -119,29 +119,24 @@ READ8_HANDLER( taitosound_comm_r ) case 0x00: // mode #0 //logerror("taitosnd: Master cpu read portdata %01x\n", tc0140syt.masterdata[0]); return tc0140syt.masterdata[tc0140syt.mainmode ++]; - break; case 0x01: // mode #1 //logerror("taitosnd: Master cpu receives 0/1 : %01x%01x\n", tc0140syt.masterdata[1],tc0140syt.masterdata[0]); tc0140syt.status &= ~TC0140SYT_PORT01_FULL_MASTER; return tc0140syt.masterdata[tc0140syt.mainmode ++]; - break; case 0x02: // mode #2 //logerror("taitosnd: Master cpu read masterdata %01x\n", tc0140syt.masterdata[2]); return tc0140syt.masterdata[tc0140syt.mainmode ++]; - break; case 0x03: // mode #3 //logerror("taitosnd: Master cpu receives 2/3 : %01x%01x\n", tc0140syt.masterdata[3],tc0140syt.masterdata[2]); tc0140syt.status &= ~TC0140SYT_PORT23_FULL_MASTER; return tc0140syt.masterdata[tc0140syt.mainmode ++]; - break; case 0x04: // port status //logerror("tc0140syt : Master cpu read status : %02x\n", tc0140syt.status); return tc0140syt.status; - break; default: logerror("tc0140syt : Master cpu read in mode [%02x]\n", tc0140syt.mainmode); diff --git a/src/mame/drivers/adp.c b/src/mame/drivers/adp.c index c1cf955a0bd..5f317d8e3a1 100644 --- a/src/mame/drivers/adp.c +++ b/src/mame/drivers/adp.c @@ -350,6 +350,8 @@ return 0x4; if (input_code_pressed(KEYCODE_8)) return 0x0080 ^ 0xffff; return 0x0004 ^ 0xffff; // 0x0004 + + // FIXME: this code is never executed switch (mame_rand(space->machine) & 3) { case 0: diff --git a/src/mame/drivers/baraduke.c b/src/mame/drivers/baraduke.c index 2cd3850300c..6b074341add 100644 --- a/src/mame/drivers/baraduke.c +++ b/src/mame/drivers/baraduke.c @@ -144,19 +144,19 @@ static READ8_HANDLER( inputport_r ) switch (inputport_selected) { case 0x00: /* DSW A (bits 0-4) */ - return (input_port_read(space->machine, "DSWA") & 0xf8) >> 3; break; + return (input_port_read(space->machine, "DSWA") & 0xf8) >> 3; case 0x01: /* DSW A (bits 5-7), DSW B (bits 0-1) */ - return ((input_port_read(space->machine, "DSWA") & 0x07) << 2) | ((input_port_read(space->machine, "DSWB") & 0xc0) >> 6); break; + return ((input_port_read(space->machine, "DSWA") & 0x07) << 2) | ((input_port_read(space->machine, "DSWB") & 0xc0) >> 6); case 0x02: /* DSW B (bits 2-6) */ - return (input_port_read(space->machine, "DSWB") & 0x3e) >> 1; break; + return (input_port_read(space->machine, "DSWB") & 0x3e) >> 1; case 0x03: /* DSW B (bit 7), DSW C (bits 0-3) */ - return ((input_port_read(space->machine, "DSWB") & 0x01) << 4) | (input_port_read(space->machine, "EDGE") & 0x0f); break; + return ((input_port_read(space->machine, "DSWB") & 0x01) << 4) | (input_port_read(space->machine, "EDGE") & 0x0f); case 0x04: /* coins, start */ - return input_port_read(space->machine, "IN0"); break; + return input_port_read(space->machine, "IN0"); case 0x05: /* 2P controls */ - return input_port_read(space->machine, "IN2"); break; + return input_port_read(space->machine, "IN2"); case 0x06: /* 1P controls */ - return input_port_read(space->machine, "IN1"); break; + return input_port_read(space->machine, "IN1"); default: return 0xff; } diff --git a/src/mame/drivers/cowrace.c b/src/mame/drivers/cowrace.c index a4576aba09c..b6f75c46907 100644 --- a/src/mame/drivers/cowrace.c +++ b/src/mame/drivers/cowrace.c @@ -75,8 +75,8 @@ static READ8_HANDLER( cowrace_30c3_r ) { switch( cowrace_38c2 ) { - case 0x02: return 0x03; break; - case 0x04: return 0x00; break; + case 0x02: return 0x03; + case 0x04: return 0x00; } return 0xff; diff --git a/src/mame/drivers/deco32.c b/src/mame/drivers/deco32.c index a5ee8c4a063..dde7f5555f4 100644 --- a/src/mame/drivers/deco32.c +++ b/src/mame/drivers/deco32.c @@ -410,10 +410,10 @@ static READ32_HANDLER( dragngun_lightgun_r ) { /* Ports 0-3 are read, but seem unused */ switch (dragngun_lightgun_port) { - case 4: return input_port_read(space->machine, "LIGHT0_X"); break; - case 5: return input_port_read(space->machine, "LIGHT1_X"); break; - case 6: return input_port_read(space->machine, "LIGHT0_Y"); break; - case 7: return input_port_read(space->machine, "LIGHT1_Y"); break; + case 4: return input_port_read(space->machine, "LIGHT0_X"); + case 5: return input_port_read(space->machine, "LIGHT1_X"); + case 6: return input_port_read(space->machine, "LIGHT0_Y"); + case 7: return input_port_read(space->machine, "LIGHT1_Y"); } // logerror("Illegal lightgun port %d read \n",dragngun_lightgun_port); diff --git a/src/mame/drivers/deco_mlc.c b/src/mame/drivers/deco_mlc.c index 297773cebb9..1b5fc11ff45 100644 --- a/src/mame/drivers/deco_mlc.c +++ b/src/mame/drivers/deco_mlc.c @@ -214,12 +214,10 @@ static WRITE32_HANDLER( mlc_irq_w ) case 0x10: /* IRQ ack. Value written doesn't matter */ cpu_set_input_line(space->machine->cpu[0], mainCpuIsArm ? ARM_IRQ_LINE : 1, CLEAR_LINE); return; - break; case 0x14: /* Prepare scanline interrupt */ timer_adjust_oneshot(raster_irq_timer,video_screen_get_time_until_pos(space->machine->primary_screen, irq_ram[0x14/4], 0),0); //logerror("prepare scanline to fire at %d (currently on %d)\n", irq_ram[0x14/4], video_screen_get_vpos(space->machine->primary_screen)); return; - break; case 0x18: case 0x1c: case 0x20: diff --git a/src/mame/drivers/gcpinbal.c b/src/mame/drivers/gcpinbal.c index 53a12abd5a5..6b76a6edc16 100644 --- a/src/mame/drivers/gcpinbal.c +++ b/src/mame/drivers/gcpinbal.c @@ -92,7 +92,6 @@ static READ16_HANDLER( ioc_r ) case 0x50: case 0x51: return okim6295_status_0_r(space,0)<<8; - break; } diff --git a/src/mame/drivers/genesis.c b/src/mame/drivers/genesis.c index 6880bd18fb7..8fa7010b52e 100644 --- a/src/mame/drivers/genesis.c +++ b/src/mame/drivers/genesis.c @@ -180,14 +180,11 @@ READ16_HANDLER(genesis_ctrl_r) { case 0: /* DRAM mode is write only */ return 0xffff; - break; case 0x80: /* return Z80 CPU Function Stop Accessible or not */ /* logerror("Returning z80 state\n"); */ return (z80running ? 0x0100 : 0x0); - break; case 0x100: /* Z80 CPU Reset - write only */ return 0xffff; - break; } return 0x00; @@ -204,7 +201,6 @@ WRITE16_HANDLER(genesis_ctrl_w) { case 0: /* set DRAM mode... we have to ignore this for production cartridges */ return; - break; case 0x80: /* Z80 BusReq */ if (data == 0x100) { @@ -221,7 +217,6 @@ WRITE16_HANDLER(genesis_ctrl_w) /* logerror("z80 started, BusReq ends\n"); */ } return; - break; case 0x100: /* Z80 CPU Reset */ if (data == 0x00) { @@ -238,8 +233,6 @@ WRITE16_HANDLER(genesis_ctrl_w) /* logerror("z80 out of reset\n"); */ } return; - - break; } } diff --git a/src/mame/drivers/kaneko16.c b/src/mame/drivers/kaneko16.c index 3bf6c9f40f9..0b5f27b2a34 100644 --- a/src/mame/drivers/kaneko16.c +++ b/src/mame/drivers/kaneko16.c @@ -605,15 +605,11 @@ static READ16_HANDLER( gtmr_wheel_r ) { case 0x0000: // 'Both Sides' = 270deg Wheel return (input_port_read(space->machine, "WHEEL0")); - break; - case 0x1000: // '1P Side' = 360' Wheel return (input_port_read(space->machine, "WHEEL1")); - break; default: return (0); - break; - } + } } static WRITE16_HANDLER( gtmr_oki_0_bank_w ) @@ -719,17 +715,13 @@ static READ16_HANDLER( gtmr2_wheel_r ) { case 0x0000: // 270' A. Wheel return (input_port_read(space->machine, "WHEEL0")); - break; case 0x1000: // 270' D. Wheel return (input_port_read(space->machine, "WHEEL1") << 8); - break; case 0x0800: // 360' Wheel return (input_port_read(space->machine, "WHEEL2") << 8); - break; default: logerror("gtmr2_wheel_r : read at %06x with joystick\n", cpu_get_pc(space->cpu)); return (~0); - break; } } diff --git a/src/mame/drivers/lemmings.c b/src/mame/drivers/lemmings.c index 2bd22a63b8a..f5a0dd8475b 100644 --- a/src/mame/drivers/lemmings.c +++ b/src/mame/drivers/lemmings.c @@ -34,10 +34,10 @@ static WRITE16_HANDLER( lemmings_control_w ) static READ16_HANDLER( lemmings_trackball_r ) { switch (offset) { - case 0: return input_port_read(space->machine, "AN0"); break; - case 1: return input_port_read(space->machine, "AN1"); break; - case 4: return input_port_read(space->machine, "AN2"); break; - case 5: return input_port_read(space->machine, "AN3"); break; + case 0: return input_port_read(space->machine, "AN0"); + case 1: return input_port_read(space->machine, "AN1"); + case 4: return input_port_read(space->machine, "AN2"); + case 5: return input_port_read(space->machine, "AN3"); } return 0; } diff --git a/src/mame/drivers/lethal.c b/src/mame/drivers/lethal.c index 6134bd357ac..dd0953491a6 100644 --- a/src/mame/drivers/lethal.c +++ b/src/mame/drivers/lethal.c @@ -299,7 +299,6 @@ static READ8_HANDLER( le_4800_r ) case 0x45: case 0x46: return K053244_r(space,offset-0x40); - break; case 0x80: case 0x81: @@ -334,11 +333,9 @@ static READ8_HANDLER( le_4800_r ) case 0x9e: case 0x9f: return K054000_r(space,offset-0x80); - break; case 0xca: return sound_status_r(space,0); - break; } } else if (offset < 0x1800) @@ -454,7 +451,6 @@ static READ8_HANDLER(guns_r) { case 0: return GUNX(1)>>1; - break; case 1: if ((240-GUNY(1)) == 7) return 0; @@ -463,7 +459,6 @@ static READ8_HANDLER(guns_r) break; case 2: return GUNX(2)>>1; - break; case 3: if ((240-GUNY(2)) == 7) return 0; diff --git a/src/mame/drivers/magicfly.c b/src/mame/drivers/magicfly.c index b6fcec21725..49dbe810dc5 100644 --- a/src/mame/drivers/magicfly.c +++ b/src/mame/drivers/magicfly.c @@ -518,11 +518,11 @@ static READ8_HANDLER( mux_port_r ) { switch( input_selector ) { - case 0x01: return input_port_read(space->machine, "IN0-0"); break; - case 0x02: return input_port_read(space->machine, "IN0-1"); break; - case 0x04: return input_port_read(space->machine, "IN0-2"); break; - case 0x08: return input_port_read(space->machine, "IN0-3"); break; - case 0x00: return input_port_read(space->machine, "DSW0"); break; + case 0x01: return input_port_read(space->machine, "IN0-0"); + case 0x02: return input_port_read(space->machine, "IN0-1"); + case 0x04: return input_port_read(space->machine, "IN0-2"); + case 0x08: return input_port_read(space->machine, "IN0-3"); + case 0x00: return input_port_read(space->machine, "DSW0"); } return 0xff; } diff --git a/src/mame/drivers/megasys1.c b/src/mame/drivers/megasys1.c index b64cd66e979..bbebad2e280 100644 --- a/src/mame/drivers/megasys1.c +++ b/src/mame/drivers/megasys1.c @@ -248,11 +248,11 @@ static READ16_HANDLER( ip_select_r ) switch (i) { - case 0 : return input_port_read(space->machine, "SYSTEM"); break; - case 1 : return input_port_read(space->machine, "P1"); break; - case 2 : return input_port_read(space->machine, "P2"); break; - case 3 : return input_port_read(space->machine, "DSW1"); break; - case 4 : return input_port_read(space->machine, "DSW2"); break; + case 0 : return input_port_read(space->machine, "SYSTEM"); + case 1 : return input_port_read(space->machine, "P1"); + case 2 : return input_port_read(space->machine, "P2"); + case 3 : return input_port_read(space->machine, "DSW1"); + case 4 : return input_port_read(space->machine, "DSW2"); default : return 0x0006; } } diff --git a/src/mame/drivers/mitchell.c b/src/mame/drivers/mitchell.c index 8a306daa79e..b43141702d6 100644 --- a/src/mame/drivers/mitchell.c +++ b/src/mame/drivers/mitchell.c @@ -303,7 +303,6 @@ static READ8_HANDLER( input_r ) case 0: default: return input_port_read(space->machine, portnames[offset]); - break; case 1: /* Mahjong games */ if (offset) return mahjong_input_r(space, offset-1); else return input_port_read(space->machine, "IN0"); diff --git a/src/mame/drivers/model3.c b/src/mame/drivers/model3.c index 946338bba6a..d79f7aac89f 100644 --- a/src/mame/drivers/model3.c +++ b/src/mame/drivers/model3.c @@ -867,7 +867,6 @@ static WRITE64_HANDLER( real3d_dma_w ) return; } return; - break; } fatalerror("real3d_dma_w: %08X, %08X%08X, %08X%08X", offset, (UINT32)(data >> 32), (UINT32)(data), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask)); } diff --git a/src/mame/drivers/msisaac.c b/src/mame/drivers/msisaac.c index 21adbb687cc..1f55bffe673 100644 --- a/src/mame/drivers/msisaac.c +++ b/src/mame/drivers/msisaac.c @@ -129,7 +129,6 @@ MCU simulation TODO: case 0x41: case 0x42: return 0; - break; /*With this command the MCU controls body direction */ case 0x02: @@ -167,17 +166,14 @@ MCU simulation TODO: return direction; } - break; /*This controls the arms when they return to the player. */ case 0x07: return 0x45; - break; default: logerror("CPU#0 read from MCU pc=%4x, mcu_val=%2x\n", cpu_get_pc(space->cpu), mcu_val ); return mcu_val; - break; } #endif } diff --git a/src/mame/drivers/namcona1.c b/src/mame/drivers/namcona1.c index 620da8831c7..75e1aec2076 100644 --- a/src/mame/drivers/namcona1.c +++ b/src/mame/drivers/namcona1.c @@ -885,19 +885,15 @@ static READ8_HANDLER( port7_r ) { case 0x40: return input_port_read(space->machine, "P1"); - break; case 0x60: return input_port_read(space->machine, "P2"); - break; case 0x20: return input_port_read(space->machine, "DSW"); - break; case 0x00: return input_port_read(space->machine, "P4"); - break; } return 0xff; diff --git a/src/mame/drivers/namconb1.c b/src/mame/drivers/namconb1.c index 79a98b53b0e..23a94b45596 100644 --- a/src/mame/drivers/namconb1.c +++ b/src/mame/drivers/namconb1.c @@ -923,19 +923,15 @@ static READ8_HANDLER( port7_r ) { case 0x00: return input_port_read_safe(space->machine, "P4", 0xff); - break; case 0x20: return input_port_read(space->machine, "MISC"); - break; case 0x40: return input_port_read(space->machine, "P1"); - break; case 0x60: return input_port_read(space->machine, "P2"); - break; default: break; diff --git a/src/mame/drivers/namcos22.c b/src/mame/drivers/namcos22.c index 5d9f39b5955..c2703d96256 100644 --- a/src/mame/drivers/namcos22.c +++ b/src/mame/drivers/namcos22.c @@ -2606,19 +2606,14 @@ static READ8_HANDLER( propcycle_mcu_adc_r ) } return (ddx & 0xff); - break; case 1: return (ddx>>8); - break; case 2: return (ddy & 0xff); - break; case 3: return (ddy>>8); - break; default: return 0; - break; } } @@ -2636,23 +2631,18 @@ static READ8_HANDLER( alpineracer_mcu_adc_r ) { case 0: return swing & 0xff; - break; case 1: return (swing>>8); - break; case 2: return edge & 0xff; - break; case 3: return (edge>>8); - break; default: return 0; - break; } } @@ -2669,31 +2659,24 @@ static READ8_HANDLER( cybrcycc_mcu_adc_r ) { case 0: return steer & 0xff; - break; case 1: return (steer>>8); - break; case 2: return gas & 0xff; - break; case 3: return (gas>>8); - break; case 4: return brake & 0xff; - break; case 5: return (brake>>8); - break; default: return 0; - break; } } @@ -2710,31 +2693,24 @@ static READ8_HANDLER( airco22_mcu_adc_r ) { case 0: return x & 0xff; - break; case 1: return (x>>8); - break; case 2: return y & 0xff; - break; case 3: return (y>>8); - break; case 4: return pedal & 0xff; - break; case 5: return (pedal>>8); - break; default: return 0; - break; } } diff --git a/src/mame/drivers/punchout.c b/src/mame/drivers/punchout.c index e31aa4a1182..28ac3c2b56b 100644 --- a/src/mame/drivers/punchout.c +++ b/src/mame/drivers/punchout.c @@ -180,7 +180,6 @@ static READ8_HANDLER( spunchout_prot_r ) { return memory_read_byte(space, 0xd7c1); return prot_mem[offset]; - break; case 0x01: if ( prot_mode_sel == 0x08 ) /* PC = 0x0b6a */ @@ -236,7 +235,6 @@ static READ8_HANDLER( spunchout_prot_r ) { return 0x00; case 0x0d: return prot_mode_sel; - break; } logerror("Read from unknown protection? port %02x ( selector = %02x )\n", offset, prot_mode_sel ); @@ -260,7 +258,6 @@ static WRITE8_HANDLER( spunchout_prot_w ) { prot_mem[offset] = data; return; - break; case 0x02: if ( prot_mode_sel == 0x09 ) { /* PC = 0x20f7, 0x22d7 */ @@ -294,6 +291,7 @@ static WRITE8_HANDLER( spunchout_prot_w ) { case 0x0d: /* PC = all over the code */ prot_mode_sel = data; return; + case 0x0f: prot_mem[offset] = data; return; diff --git a/src/mame/drivers/rungun.c b/src/mame/drivers/rungun.c index 03aa940e25f..0348f932363 100644 --- a/src/mame/drivers/rungun.c +++ b/src/mame/drivers/rungun.c @@ -100,7 +100,6 @@ static READ16_HANDLER( rng_sysregs_r ) data = input_port_read(space->machine, "P1") & input_port_read(space->machine, "P3"); return(data<<8 | data); } - break; case 0x02/2: if (input_port_read(space->machine, "DSW") & 0x20) @@ -110,7 +109,6 @@ static READ16_HANDLER( rng_sysregs_r ) data = input_port_read(space->machine, "P2") & input_port_read(space->machine, "P4"); return(data<<8 | data); } - break; case 0x04/2: /* @@ -119,7 +117,6 @@ static READ16_HANDLER( rng_sysregs_r ) bit9 : joysticks layout(auto detect???) */ return input_port_read(space->machine, "SYSTEM"); - break; case 0x06/2: if (ACCESSING_BITS_0_7) @@ -133,7 +130,6 @@ static READ16_HANDLER( rng_sysregs_r ) } } return((rng_sysreg[0x06/2] & 0xff00) | data); - break; } return(rng_sysreg[offset]); diff --git a/src/mame/drivers/skykid.c b/src/mame/drivers/skykid.c index dd49e408f6b..eef7390eded 100644 --- a/src/mame/drivers/skykid.c +++ b/src/mame/drivers/skykid.c @@ -53,19 +53,19 @@ static READ8_HANDLER( inputport_r ) switch (inputport_selected) { case 0x00: /* DSW B (bits 0-4) */ - return (input_port_read(space->machine, "DSWB") & 0xf8) >> 3; break; + return (input_port_read(space->machine, "DSWB") & 0xf8) >> 3; case 0x01: /* DSW B (bits 5-7), DSW A (bits 0-1) */ - return ((input_port_read(space->machine, "DSWB") & 0x07) << 2) | ((input_port_read(space->machine, "DSWA") & 0xc0) >> 6); break; + return ((input_port_read(space->machine, "DSWB") & 0x07) << 2) | ((input_port_read(space->machine, "DSWA") & 0xc0) >> 6); case 0x02: /* DSW A (bits 2-6) */ - return (input_port_read(space->machine, "DSWA") & 0x3e) >> 1; break; + return (input_port_read(space->machine, "DSWA") & 0x3e) >> 1; case 0x03: /* DSW A (bit 7), DSW C (bits 0-3) */ - return ((input_port_read(space->machine, "DSWA") & 0x01) << 4) | (input_port_read(space->machine, "BUTTON2") & 0x0f); break; + return ((input_port_read(space->machine, "DSWA") & 0x01) << 4) | (input_port_read(space->machine, "BUTTON2") & 0x0f); case 0x04: /* coins, start */ - return input_port_read(space->machine, "SYSTEM"); break; + return input_port_read(space->machine, "SYSTEM"); case 0x05: /* 2P controls */ - return input_port_read(space->machine, "P2"); break; + return input_port_read(space->machine, "P2"); case 0x06: /* 1P controls */ - return input_port_read(space->machine, "P1"); break; + return input_port_read(space->machine, "P1"); default: return 0xff; } diff --git a/src/mame/drivers/spaceg.c b/src/mame/drivers/spaceg.c index fe382cdfc2f..cafb2774418 100644 --- a/src/mame/drivers/spaceg.c +++ b/src/mame/drivers/spaceg.c @@ -228,7 +228,6 @@ static WRITE8_HANDLER( zvideoram_w ) logerror("mode =%02x pc=%04x\n",*io9401,cpu_get_pc(space->cpu) ); popmessage("mode =%02x pc=%04x\n",*io9401,cpu_get_pc(space->cpu) ); return; - break; } diff --git a/src/mame/drivers/ssfindo.c b/src/mame/drivers/ssfindo.c index 6a90feeedd0..db0121d2841 100644 --- a/src/mame/drivers/ssfindo.c +++ b/src/mame/drivers/ssfindo.c @@ -316,7 +316,6 @@ static READ32_HANDLER(PS7500_IO_r) { case MSECR: return mame_rand(space->machine); - break; case IOLINES: //TODO: eeprom 24c01 #if 0 diff --git a/src/mame/drivers/xyonix.c b/src/mame/drivers/xyonix.c index 556d24fb645..8f3e3f1f675 100644 --- a/src/mame/drivers/xyonix.c +++ b/src/mame/drivers/xyonix.c @@ -99,10 +99,8 @@ static READ8_HANDLER ( xyonix_io_r ) { case 0x81 : return input_port_read(space->machine, "P1") & 0x7f; - break; case 0x82 : return input_port_read(space->machine, "P2") & 0x7f; - break; case 0x91: /* check coin inputs */ coin = ((input_port_read(space->machine, "P1") & 0x80) >> 7) | ((input_port_read(space->machine, "P2") & 0x80) >> 6); @@ -112,25 +110,19 @@ static READ8_HANDLER ( xyonix_io_r ) } prev_coin = coin; return credits; - break; case 0x92: return ((input_port_read(space->machine, "P1") & 0x80) >> 7) | ((input_port_read(space->machine, "P2") & 0x80) >> 6); - break; case 0xe0: /* reset? */ coins = 0; credits = 0; return 0xff; - break; case 0xe1: credits--; return 0xff; - break; case 0xfe: /* Dip Switches 1 to 4 */ return input_port_read(space->machine, "DSW") & 0x0f; - break; case 0xff: /* Dip Switches 5 to 8 */ return input_port_read(space->machine, "DSW") >> 4; - break; } } diff --git a/src/mame/drivers/zn.c b/src/mame/drivers/zn.c index 160555d5bc7..ed875f4d176 100644 --- a/src/mame/drivers/zn.c +++ b/src/mame/drivers/zn.c @@ -1955,11 +1955,9 @@ static READ32_HANDLER( bam2_mcu_r ) case 0x7f: // first drive check case 0x1c: // second drive check (causes HDD detected) return 1; // return error - break; } return 4; // return OK - break; } return 0; diff --git a/src/mame/machine/amiga.c b/src/mame/machine/amiga.c index 421772b9059..fb108c22f1d 100644 --- a/src/mame/machine/amiga.c +++ b/src/mame/machine/amiga.c @@ -1221,7 +1221,6 @@ READ16_HANDLER( amiga_custom_r ) case REG_DENISEID: return CUSTOM_REG(REG_DENISEID); - break; } if (LOG_CUSTOM) diff --git a/src/mame/machine/gaplus.c b/src/mame/machine/gaplus.c index 602e6ff97f4..e080483a66a 100644 --- a/src/mame/machine/gaplus.c +++ b/src/mame/machine/gaplus.c @@ -36,16 +36,12 @@ READ8_HANDLER( gaplus_customio_3_r ) { case 0: return input_port_read(space->machine, "IN2"); /* cabinet & test mode */ - break; case 1: return (mode == 2) ? gaplus_customio_3[offset] : 0x0f; - break; case 2: return (mode == 2) ? 0x0f : 0x0e; - break; case 3: return (mode == 2) ? gaplus_customio_3[offset] : 0x01; - break; default: return gaplus_customio_3[offset]; } diff --git a/src/mame/machine/midyunit.c b/src/mame/machine/midyunit.c index b9c2955cd38..91ec4b04320 100644 --- a/src/mame/machine/midyunit.c +++ b/src/mame/machine/midyunit.c @@ -164,10 +164,10 @@ static READ16_HANDLER( term2_input_r ) switch (term2_analog_select) { default: - case 0: return input_port_read(space->machine, "STICK0_X"); break; - case 1: return input_port_read(space->machine, "STICK0_Y"); break; - case 2: return input_port_read(space->machine, "STICK1_X"); break; - case 3: return input_port_read(space->machine, "STICK1_Y"); break; + case 0: return input_port_read(space->machine, "STICK0_X"); + case 1: return input_port_read(space->machine, "STICK0_Y"); + case 2: return input_port_read(space->machine, "STICK1_X"); + case 3: return input_port_read(space->machine, "STICK1_Y"); } } diff --git a/src/mame/machine/namcoio.c b/src/mame/machine/namcoio.c index 7e2157d5d74..67107cf09c2 100644 --- a/src/mame/machine/namcoio.c +++ b/src/mame/machine/namcoio.c @@ -967,10 +967,10 @@ static UINT8 namco_06xx_data_r(running_machine *machine,int chip,int offset) switch (customio_command[chip] & 0xf) { - case 0x1: return namco_06xx_data_read(machine, 4*chip + 0); break; - case 0x2: return namco_06xx_data_read(machine, 4*chip + 1); break; - case 0x4: return namco_06xx_data_read(machine, 4*chip + 2); break; - case 0x8: return namco_06xx_data_read(machine, 4*chip + 3); break; + case 0x1: return namco_06xx_data_read(machine, 4*chip + 0); + case 0x2: return namco_06xx_data_read(machine, 4*chip + 1); + case 0x4: return namco_06xx_data_read(machine, 4*chip + 2); + case 0x8: return namco_06xx_data_read(machine, 4*chip + 3); default: logerror("%s: 06XX #%d read in unsupported mode %02x\n",cpuexec_describe_context(machine),chip,customio_command[chip]); return 0xff; diff --git a/src/mame/machine/nb1413m3.c b/src/mame/machine/nb1413m3.c index 8035bbb3b90..aa50dce0d1e 100644 --- a/src/mame/machine/nb1413m3.c +++ b/src/mame/machine/nb1413m3.c @@ -432,7 +432,6 @@ READ8_HANDLER( nb1413m3_inputport1_r ) case NB1413M3_PAIRSNB: case NB1413M3_PAIRSTEN: return input_port_read(space->machine, "P1"); - break; default: switch ((nb1413m3_inputport ^ 0xff) & 0x1f) { @@ -482,7 +481,6 @@ READ8_HANDLER( nb1413m3_inputport2_r ) case NB1413M3_PAIRSNB: case NB1413M3_PAIRSTEN: return input_port_read(space->machine, "P2"); - break; default: switch ((nb1413m3_inputport ^ 0xff) & 0x1f) { @@ -516,10 +514,8 @@ READ8_HANDLER( nb1413m3_inputport3_r ) case NB1413M3_FINALBNY: case NB1413M3_MMSIKAKU: return ((nb1413m3_outcoin_flag & 0x01) << 1); - break; default: return 0xff; - break; } } @@ -530,16 +526,13 @@ READ8_HANDLER( nb1413m3_dipsw1_r ) case NB1413M3_KANATUEN: case NB1413M3_KYUHITO: return input_port_read(space->machine, "DSWB"); - break; case NB1413M3_TAIWANMB: return ((input_port_read(space->machine, "DSWA") & 0xf0) | ((input_port_read(space->machine, "DSWB") & 0xf0) >> 4)); - break; case NB1413M3_OTONANO: case NB1413M3_MJCAMERA: case NB1413M3_IDHIMITU: case NB1413M3_KAGUYA2: return (((input_port_read(space->machine, "DSWA") & 0x0f) << 4) | (input_port_read(space->machine, "DSWB") & 0x0f)); - break; case NB1413M3_SCANDAL: case NB1413M3_SCANDALM: case NB1413M3_MJFOCUSM: @@ -551,7 +544,6 @@ READ8_HANDLER( nb1413m3_dipsw1_r ) case NB1413M3_TOKIMBSJ: case NB1413M3_TOKYOGAL: return ((input_port_read(space->machine, "DSWA") & 0x0f) | ((input_port_read(space->machine, "DSWB") & 0x0f) << 4)); - break; case NB1413M3_TRIPLEW1: case NB1413M3_NTOPSTAR: case NB1413M3_PSTADIUM: @@ -565,10 +557,8 @@ READ8_HANDLER( nb1413m3_dipsw1_r ) ((input_port_read(space->machine, "DSWB") & 0x10) >> 2) | ((input_port_read(space->machine, "DSWB") & 0x40) >> 3) | ((input_port_read(space->machine, "DSWA") & 0x01) << 4) | ((input_port_read(space->machine, "DSWA") & 0x04) << 3) | ((input_port_read(space->machine, "DSWA") & 0x10) << 2) | ((input_port_read(space->machine, "DSWA") & 0x40) << 1)); - break; default: return input_port_read(space->machine, "DSWA"); - break; } } @@ -579,16 +569,13 @@ READ8_HANDLER( nb1413m3_dipsw2_r ) case NB1413M3_KANATUEN: case NB1413M3_KYUHITO: return input_port_read(space->machine, "DSWA"); - break; case NB1413M3_TAIWANMB: return (((input_port_read(space->machine, "DSWA") & 0x0f) << 4) | (input_port_read(space->machine, "DSWB") & 0x0f)); - break; case NB1413M3_OTONANO: case NB1413M3_MJCAMERA: case NB1413M3_IDHIMITU: case NB1413M3_KAGUYA2: return ((input_port_read(space->machine, "DSWA") & 0xf0) | ((input_port_read(space->machine, "DSWB") & 0xf0) >> 4)); - break; case NB1413M3_SCANDAL: case NB1413M3_SCANDALM: case NB1413M3_MJFOCUSM: @@ -600,7 +587,6 @@ READ8_HANDLER( nb1413m3_dipsw2_r ) case NB1413M3_TOKIMBSJ: case NB1413M3_TOKYOGAL: return (((input_port_read(space->machine, "DSWA") & 0xf0) >> 4) | (input_port_read(space->machine, "DSWB") & 0xf0)); - break; case NB1413M3_TRIPLEW1: case NB1413M3_NTOPSTAR: case NB1413M3_PSTADIUM: @@ -614,10 +600,8 @@ READ8_HANDLER( nb1413m3_dipsw2_r ) ((input_port_read(space->machine, "DSWB") & 0x20) >> 3) | ((input_port_read(space->machine, "DSWB") & 0x80) >> 4) | ((input_port_read(space->machine, "DSWA") & 0x02) << 3) | ((input_port_read(space->machine, "DSWA") & 0x08) << 2) | ((input_port_read(space->machine, "DSWA") & 0x20) << 1) | ((input_port_read(space->machine, "DSWA") & 0x80) << 0)); - break; default: return input_port_read(space->machine, "DSWB"); - break; } } diff --git a/src/mame/machine/segas32.c b/src/mame/machine/segas32.c index 2d7be16d09d..cd4d2fcd0f5 100644 --- a/src/mame/machine/segas32.c +++ b/src/mame/machine/segas32.c @@ -165,7 +165,6 @@ READ16_HANDLER(brival_protection_r) case 2: case 3: return 0; - break; } } @@ -212,7 +211,6 @@ WRITE16_HANDLER(brival_protection_w) return; logerror("brival_protection_w: UNKNOWN WRITE: offset %x value %x\n", offset, data); return; - break; } memcpy(ret, &ROM[protAddress[curProtType][0]], 16); diff --git a/src/mame/machine/seicop.c b/src/mame/machine/seicop.c index fb4f535f056..774a9248c40 100644 --- a/src/mame/machine/seicop.c +++ b/src/mame/machine/seicop.c @@ -1125,7 +1125,6 @@ static READ16_HANDLER( generic_cop_r ) default: seibu_cop_log("%06x: COPX unhandled read returning %04x from offset %04x\n", cpu_get_pc(space->cpu), retvalue, offset*2); return retvalue; - break; /* BCD protection reads */ case (0x190/2): { return ((prot_bcd[0] & 0x0000ffff) >> 0 ) + 0x3030; } @@ -1292,7 +1291,6 @@ READ16_HANDLER( heatbrl_mcu_r ) { default: return generic_cop_r(space, offset, mem_mask); - break; /********************************************************************* 400-5ff - Protection reads @@ -1319,7 +1317,6 @@ READ16_HANDLER( heatbrl_mcu_r ) case (0x344/2): return input_port_read(space->machine, "PLAYERS12"); case (0x348/2): return input_port_read(space->machine, "PLAYERS34"); case (0x34c/2): return input_port_read(space->machine, "SYSTEM"); - } } @@ -1412,7 +1409,6 @@ READ16_HANDLER( cupsoc_mcu_r ) { default: return generic_cop_r(space, offset, mem_mask); - break; //case (0x07e/2): //case (0x1b0/2): @@ -1565,7 +1561,6 @@ READ16_HANDLER( godzilla_mcu_r ) { default: return generic_cop_r(space, offset, mem_mask); - break; /* Non-protection reads */ case (0x308/2): return seibu_main_word_r(space,2,0xffff); @@ -1615,7 +1610,6 @@ READ16_HANDLER( denjinmk_mcu_r ) { default: return generic_cop_r(space, offset, mem_mask); - break; /* Non-protection reads */ @@ -1675,13 +1669,13 @@ READ16_HANDLER( sdgndmrb_mcu_r ) { default: return generic_cop_r(space, offset, mem_mask); - break; /*hit protection*/ case (0x180/2): { return xy_check; } case (0x1b0/2): return 2; + // FIXME: this code is never reached /*check if the DMA has been finished*/ if(dma_status == 1) { @@ -1882,7 +1876,6 @@ READ16_HANDLER( legionna_mcu_r ) { default: return generic_cop_r(space, offset, mem_mask); - break; /********************************************************************* 400-5ff - Protection reads @@ -1984,7 +1977,6 @@ READ16_HANDLER( raiden2_mcu_r ) { default: return generic_cop_r(space, offset, mem_mask); - break; case (0x340/2): return input_port_read(space->machine, "DSWA") | (input_port_read(space->machine, "DSWB") << 8); case (0x344/2): return input_port_read(space->machine, "P1") | (input_port_read(space->machine, "P2") << 8); diff --git a/src/mame/machine/snes.c b/src/mame/machine/snes.c index 6d403ab29e3..c967c95eb44 100644 --- a/src/mame/machine/snes.c +++ b/src/mame/machine/snes.c @@ -514,7 +514,6 @@ READ8_HANDLER( snes_r_io ) return snes_ram[offset]; case RDIO: /* Programmable I/O port - echos back what's written to WRIO */ return snes_ram[WRIO]; - break; case RDDIVL: /* Quotient of divide result (low) */ case RDDIVH: /* Quotient of divide result (high) */ case RDMPYL: /* Product/Remainder of mult/div result (low) */ diff --git a/src/mame/machine/stvcd.c b/src/mame/machine/stvcd.c index 6a7060c19db..03f39a36dc9 100644 --- a/src/mame/machine/stvcd.c +++ b/src/mame/machine/stvcd.c @@ -383,37 +383,31 @@ static UINT16 cd_readWord(UINT32 addr) // CDROM_LOG(("%s:RW HIRQ: %04x\n", cpuexec_describe_context(Machine), rv)) return rv; - break; case 0x000c: case 0x000e: CDROM_LOG(("RW HIRM: %04x\n", hirqmask)) return hirqmask; - break; case 0x0018: case 0x001a: // CDROM_LOG(("RW CR1: %04x\n", cr1)) return cr1; - break; case 0x001c: case 0x001e: // CDROM_LOG(("RW CR2: %04x\n", cr2)) return cr2; - break; case 0x0020: case 0x0022: // CDROM_LOG(("RW CR3: %04x\n", cr3)) return cr3; - break; case 0x0024: case 0x0026: // CDROM_LOG(("RW CR4: %04x\n", cr4)) return cr4; - break; case 0x8000: rv = 0xffff; @@ -450,12 +444,10 @@ static UINT16 cd_readWord(UINT32 addr) } return rv; - break; default: CDROM_LOG(("%s:CD: RW %08x\n", cpuexec_describe_context(machine), addr)) return 0xffff; - break; } } @@ -526,12 +518,10 @@ static UINT32 cd_readLong(UINT32 addr) } return rv; - break; default: CDROM_LOG(("%s:CD: RL %08x\n", cpuexec_describe_context(machine), addr)) return 0xffff; - break; } } @@ -566,7 +556,7 @@ static void cd_writeWord(UINT32 addr, UINT16 data) case 0x0022: // CDROM_LOG(("WW CR3: %04x\n", data)) cr3 = data; - break; + break; case 0x0024: case 0x0026: // CDROM_LOG(("WW CR4: %04x\n", data)) @@ -1348,7 +1338,6 @@ READ32_HANDLER( stvcd_r ) case 0x90026: rv = cd_readWord(offset); return rv<<16; - break; case 0x98000: case 0x18000: diff --git a/src/mame/machine/tnzs.c b/src/mame/machine/tnzs.c index 45f97b46a47..51cd63b3062 100644 --- a/src/mame/machine/tnzs.c +++ b/src/mame/machine/tnzs.c @@ -242,7 +242,6 @@ static READ8_HANDLER( mcu_arknoid2_r ) logerror("error, unknown mcu command\n"); /* should not happen */ return 0xff; - break; } } else @@ -370,7 +369,6 @@ static READ8_HANDLER( mcu_extrmatn_r ) logerror("error, unknown mcu command\n"); /* should not happen */ return 0xff; - break; } } else @@ -573,18 +571,14 @@ READ8_HANDLER( tnzs_mcu_r ) case MCU_TNZS: case MCU_CHUKATAI: return mcu_tnzs_r(space,offset); - break; case MCU_ARKANOID: return mcu_arknoid2_r(space,offset); - break; case MCU_EXTRMATN: case MCU_DRTOPPEL: case MCU_PLUMPOP: return mcu_extrmatn_r(space,offset); - break; default: return 0xff; - break; } } diff --git a/src/mame/machine/vsnes.c b/src/mame/machine/vsnes.c index f4a5cef362c..734f1ab8cf3 100644 --- a/src/mame/machine/vsnes.c +++ b/src/mame/machine/vsnes.c @@ -1000,15 +1000,12 @@ static READ8_HANDLER( rbi_hack_r) { case 9: return 0x6F; - break; case 14: return 0x94; - break; default: return 0xB4; - break; } } } diff --git a/src/mame/machine/williams.c b/src/mame/machine/williams.c index b99dfc59af8..723bcf007f0 100644 --- a/src/mame/machine/williams.c +++ b/src/mame/machine/williams.c @@ -951,6 +951,7 @@ static READ8_DEVICE_HANDLER( tshoot_input_port_0_3_r ) int gun = (data & 0x3f) ^ ((data & 0x3f) >> 1); return (data & 0xc0) | gun; + // FIXME: this code is never reached return 0; } diff --git a/src/mame/video/konamiic.c b/src/mame/video/konamiic.c index 7f23949373f..0ebe4c0deff 100644 --- a/src/mame/video/konamiic.c +++ b/src/mame/video/konamiic.c @@ -4031,26 +4031,20 @@ READ16_HANDLER( K055673_rom_word_r ) // 5bpp { case 0: // 20k / 36u return ROM[romofs+2]; - break; case 1: // 17k / 36y return ROM[romofs+3]; - break; case 2: // 10k / 32y case 3: romofs /= 2; - return ROM8[romofs+1]; - break; + return ROM8[romofs+1]; case 4: // 22k / 34u return ROM[romofs]; - break; case 5: // 19k / 34y return ROM[romofs+1]; - break; case 6: // 12k / 29y case 7: romofs /= 2; - return ROM8[romofs]; - break; + return ROM8[romofs]; default: LOG(("55673_rom_word_r: Unknown read offset %x\n", offset)); break; @@ -4073,24 +4067,18 @@ READ16_HANDLER( K055673_GX6bpp_rom_word_r ) { case 0: return ROM[romofs+3]; - break; case 1: return ROM[romofs+4]; - break; case 2: case 3: - return ROM[romofs+5]; - break; + return ROM[romofs+5]; case 4: return ROM[romofs]; - break; case 5: return ROM[romofs+1]; - break; case 6: case 7: - return ROM[romofs+2]; - break; + return ROM[romofs+2]; default: LOG(("55673_rom_word_r: Unknown read offset %x (PC=%x)\n", offset, cpu_get_pc(space->cpu))); break; diff --git a/src/mame/video/phoenix.c b/src/mame/video/phoenix.c index 5096ca2e3c3..0b07cc91479 100644 --- a/src/mame/video/phoenix.c +++ b/src/mame/video/phoenix.c @@ -327,12 +327,10 @@ CUSTOM_INPUT( pleiads_protection_r ) case 0x20: /* Bit 3 is 0 */ return 0; - break; case 0x0c: case 0x30: /* Bit 3 is 1 */ return 1; - break; default: logerror("%s:Unknown protection question %02X\n", cpuexec_describe_context(field->port->machine), pleiads_protection_question); return 0; diff --git a/src/mame/video/twincobr.c b/src/mame/video/twincobr.c index 536bf2eb6f0..523f91c6482 100644 --- a/src/mame/video/twincobr.c +++ b/src/mame/video/twincobr.c @@ -338,9 +338,9 @@ READ8_HANDLER( wardner_videoram_r ) { int shift = 8 * (offset & 1); switch (offset/2) { - case 0: return twincobr_txram_r(space,0,0xffff) >> shift; break; - case 1: return twincobr_bgram_r(space,0,0xffff) >> shift; break; - case 2: return twincobr_fgram_r(space,0,0xffff) >> shift; break; + case 0: return twincobr_txram_r(space,0,0xffff) >> shift; + case 1: return twincobr_bgram_r(space,0,0xffff) >> shift; + case 2: return twincobr_fgram_r(space,0,0xffff) >> shift; } return 0; } diff --git a/src/mame/video/ygv608.c b/src/mame/video/ygv608.c index c877c4079c9..b3d8f257506 100644 --- a/src/mame/video/ygv608.c +++ b/src/mame/video/ygv608.c @@ -1043,7 +1043,6 @@ READ16_HANDLER( ygv608_r ) if (ygv608.regs.s.r2 & r2_saar) ygv608.regs.s.saa++; return (data << 8); - break; case 0x02: /* P#2 - scroll data port */ data = ygv608.scroll_data_table[(ygv608.regs.s.r2 & r2_b_a) >> 4][ygv608.regs.s.sca]; @@ -1055,7 +1054,6 @@ READ16_HANDLER( ygv608_r ) ygv608.regs.s.r2 ^= r2_b_a; } return( data << 8 ); - break; case 0x03: /* P#3 - color palette data port */ data = ygv608.colour_palette[ygv608.regs.s.cc][p3_state]; @@ -1066,7 +1064,6 @@ READ16_HANDLER( ygv608_r ) ygv608.regs.s.cc++; } return( data << 8 ); - break; case 0x04: /* P#4 - register data port */ { |