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authorGravatarGravatar Scott Stone <tafoid@users.noreply.github.com>2012-12-04 04:37:49 +0000
committerGravatarGravatar Scott Stone <tafoid@users.noreply.github.com>2012-12-04 04:37:49 +0000
commitebc6b1857c356fbaa837bdde70a483cd0db8834c (patch) (github)
tree9c02a88037ce7f1341afa5e134aca0c2199e903e /src/regtests/jedutil
parent1bac4085966986e8636cfd4abf01ee07378e97e6 (diff)
downloadmame-ebc6b1857c356fbaa837bdde70a483cd0db8834c.tar.bz2
mame-ebc6b1857c356fbaa837bdde70a483cd0db8834c.zip
Added the ability to view peel18cv8 jed files to the jedutil. [Kevin Eshbach)
Diffstat (limited to 'src/regtests/jedutil')
-rw-r--r--src/regtests/jedutil/baseline/18cv8/18cv8_combinatorial_feedback.txt35
-rw-r--r--src/regtests/jedutil/baseline/18cv8/18cv8_register_feedback.txt35
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal10h8-to-peel18cv8.txt49
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal10l8-to-peel18cv8.txt49
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal12h6-to-peel18cv8.txt43
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal12l6-to-peel18cv8.txt43
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal14h4-to-peel18cv8.txt37
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal14l4-to-peel18cv8.txt37
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal16h2-to-peel18cv8.txt31
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal16l2-to-peel18cv8.txt31
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal16l8-to-peel18cv8.txt89
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal16r4-to-peel18cv8.txt93
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal16r6-to-peel18cv8.txt95
-rw-r--r--src/regtests/jedutil/baseline/18cv8/pal16r8-to-peel18cv8.txt97
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal10h8-to-gal16v8.txt17
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal10l8-to-gal16v8.txt17
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal12h6-to-gal16v8.txt15
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal12l6-to-gal16v8.txt15
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal14h4-to-gal16v8.txt13
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal14l4-to-gal16v8.txt13
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal16h2-to-gal16v8.txt11
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal16l2-to-gal16v8.txt11
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal16l8-to-gal16v8.txt17
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal16r4-to-gal16v8.txt17
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal16r6-to-gal16v8.txt17
-rw-r--r--src/regtests/jedutil/baseline/gal16v8/pal16r8-to-gal16v8.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal10h8/pal10h8.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal10l8/pal10l8.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal12h6/pal12h6.txt15
-rw-r--r--src/regtests/jedutil/baseline/pal12l6/pal12l6.txt15
-rw-r--r--src/regtests/jedutil/baseline/pal14h4/pal14h4.txt13
-rw-r--r--src/regtests/jedutil/baseline/pal14l4/pal14l4.txt13
-rw-r--r--src/regtests/jedutil/baseline/pal16c1/pal16c1.txt11
-rw-r--r--src/regtests/jedutil/baseline/pal16h2/pal16h2.txt11
-rw-r--r--src/regtests/jedutil/baseline/pal16l2/pal16l2.txt11
-rw-r--r--src/regtests/jedutil/baseline/pal16l8/pal16l8.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal16r4/pal16r4.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal16r6/pal16r6.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal16r8/pal16r8.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal20l10/pal20l10.txt19
-rw-r--r--src/regtests/jedutil/baseline/pal20l8/pal20l8.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal20r4/pal20r4.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal20r6/pal20r6.txt17
-rw-r--r--src/regtests/jedutil/baseline/pal20r8/pal20r8.txt17
-rw-r--r--src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_bi-directional_io.psf64
-rw-r--r--src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_combinatorial_feedback.psf62
-rw-r--r--src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_register_feedback.psf62
-rw-r--r--src/regtests/jedutil/eqns/ICT_Place/readme.txt1
-rw-r--r--src/regtests/jedutil/eqns/Opal_Jr/readme.txt1
-rw-r--r--src/regtests/jedutil/eqns/pal10l8/pal10l8.eqn30
-rw-r--r--src/regtests/jedutil/eqns/pal12h6/pal12h6.eqn28
-rw-r--r--src/regtests/jedutil/eqns/pal12l6/pal12l6.eqn28
-rw-r--r--src/regtests/jedutil/eqns/pal14h4/pal14h4.eqn26
-rw-r--r--src/regtests/jedutil/eqns/pal14l4/pal14l4.eqn26
-rw-r--r--src/regtests/jedutil/eqns/pal16c1/pal16c1.eqn23
-rw-r--r--src/regtests/jedutil/eqns/pal16h2/pal16h2.eqn24
-rw-r--r--src/regtests/jedutil/eqns/pal16l2/pal16l2.eqn24
-rw-r--r--src/regtests/jedutil/eqns/pal16l8/pal16l8.eqn79
-rw-r--r--src/regtests/jedutil/eqns/pal16r4/pal16r4.eqn82
-rw-r--r--src/regtests/jedutil/eqns/pal16r6/pal16r6.eqn84
-rw-r--r--src/regtests/jedutil/eqns/pal16r8/pal16r8.eqn86
-rw-r--r--src/regtests/jedutil/eqns/pal20l10/pal20l10.eqn56
-rw-r--r--src/regtests/jedutil/eqns/pal20l8/pal20l8.eqn78
-rw-r--r--src/regtests/jedutil/eqns/pal20r4/pal20r4.eqn82
-rw-r--r--src/regtests/jedutil/eqns/pal20r6/pal20r6.eqn84
-rw-r--r--src/regtests/jedutil/eqns/pal20r8/pal20r8.eqn86
-rw-r--r--src/regtests/jedutil/eqns/readme.txt1
-rw-r--r--src/regtests/jedutil/jeds/18cv8/18cv8_combinatorial_feedback.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/18cv8_register_feedback.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal10h8-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal12h6-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal12l6-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal14h4-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal14l4-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal16h2-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal16l2-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal16r4-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal16r6-to-peel18cv8.jed104
-rw-r--r--src/regtests/jedutil/jeds/18cv8/pal16r8-to-peel18cv8.jed104
79 files changed, 2660 insertions, 927 deletions
diff --git a/src/regtests/jedutil/baseline/18cv8/18cv8_combinatorial_feedback.txt b/src/regtests/jedutil/baseline/18cv8/18cv8_combinatorial_feedback.txt
new file mode 100644
index 00000000000..c75377415fc
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/18cv8_combinatorial_feedback.txt
@@ -0,0 +1,35 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+13 (Registered, Output feedback combinatorial, Active low)
+15 (Registered, Output feedback combinatorial, Active high)
+17 (Combinatorial, Output feedback combinatorial, Active high)
+19 (Combinatorial, Output feedback combinatorial, Active low)
+
+Equations:
+
+/rf13 := /i3 & /i4 & /i5 & i6 +
+ i1 & /i2 & of19 +
+ /of17 & /of19 +
+ i14 & of15 +
+ i12 & /of15
+rf13.oe = of17
+
+rf15 := of17 & of19 +
+ /of19 +
+ i11 & /i12 & of13 & /of17
+rf15.oe = /of13
+
+o17 = /of19 +
+ /of13 & of15 & i16 & of19 +
+ of13 & /of15
+o17.oe = vcc
+
+/o19 = of13 & i16 & /of17 & /i18 +
+ /i9 & /i11 & of15 +
+ /i7 & i8 & /of13 & /of15
+o19.oe = of17
+
diff --git a/src/regtests/jedutil/baseline/18cv8/18cv8_register_feedback.txt b/src/regtests/jedutil/baseline/18cv8/18cv8_register_feedback.txt
new file mode 100644
index 00000000000..64346cb15bd
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/18cv8_register_feedback.txt
@@ -0,0 +1,35 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+13 (Combinatorial, Output feedback registered, Active high)
+15 (Registered, Output feedback registered, Active low)
+17 (Combinatorial, Output feedback registered, Active low)
+19 (Registered, Output feedback registered, Active high)
+
+Equations:
+
+o13 = i3 & rf17 +
+ /i12 & rf15 +
+ /rf15 & /rf17 +
+ i7 & rf19 +
+ /i9 & /rf19
+o13.oe = vcc
+
+/rf15 := /rf17 +
+ /rf13 & rf19 +
+ rf13 & rf17 & /rf19
+rf15.oe = rf17
+
+/o17 = rf13 +
+ i1 & /rf13 & /rf15 & i16 +
+ rf15 & rf19
+o17.oe = /rf19
+
+rf19 := rf13 & /rf17 +
+ i8 & rf15 & rf17 +
+ i1 & i2 & /rf15
+rf19.oe = /rf13
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal10h8-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal10h8-to-peel18cv8.txt
new file mode 100644
index 00000000000..72374ae185e
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal10h8-to-peel18cv8.txt
@@ -0,0 +1,49 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active high)
+13 (Combinatorial, Output feedback output, Active high)
+14 (Combinatorial, Output feedback output, Active high)
+15 (Combinatorial, Output feedback output, Active high)
+16 (Combinatorial, Output feedback output, Active high)
+17 (Combinatorial, Output feedback output, Active high)
+18 (Combinatorial, Output feedback output, Active high)
+19 (Combinatorial, Output feedback output, Active high)
+
+Equations:
+
+o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & i11
+o12.oe = vcc
+
+o13 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ /i9 & i11
+o13.oe = vcc
+
+o14 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & /i11
+o14.oe = vcc
+
+o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
+ /i9 & /i11
+o15.oe = vcc
+
+o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
+ /i9 & /i11
+o16.oe = vcc
+
+o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
+ i9 & /i11
+o17.oe = vcc
+
+o18 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
+ /i9 & i11
+o18.oe = vcc
+
+o19 = i1 & i2 & i3 & i4 & i5 & i6 & i7 & /i8 +
+ i11
+o19.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal10l8-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal10l8-to-peel18cv8.txt
new file mode 100644
index 00000000000..eb0d1bd88c0
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal10l8-to-peel18cv8.txt
@@ -0,0 +1,49 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Combinatorial, Output feedback output, Active low)
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
+/o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & i11
+o12.oe = vcc
+
+/o13 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ /i9 & i11
+o13.oe = vcc
+
+/o14 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & /i11
+o14.oe = vcc
+
+/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
+ /i9 & /i11
+o15.oe = vcc
+
+/o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
+ /i9 & /i11
+o16.oe = vcc
+
+/o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
+ i9 & /i11
+o17.oe = vcc
+
+/o18 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
+ i11
+o18.oe = vcc
+
+/o19 = i1 & i2 & i3 & i4 & i5 & i6 & i7 & /i8 +
+ /i9
+o19.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal12h6-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal12h6-to-peel18cv8.txt
new file mode 100644
index 00000000000..2669b8e2e1b
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal12h6-to-peel18cv8.txt
@@ -0,0 +1,43 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+13 (Combinatorial, Output feedback output, Active high)
+14 (Combinatorial, Output feedback output, Active high)
+15 (Combinatorial, Output feedback output, Active high)
+16 (Combinatorial, Output feedback output, Active high)
+17 (Combinatorial, Output feedback output, Active high)
+18 (Combinatorial, Output feedback output, Active high)
+
+Equations:
+
+o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & i11 +
+ /i19 +
+ i12
+o13.oe = vcc
+
+o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ /i9 & i11
+o14.oe = vcc
+
+o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
+ /i9 & /i11
+o15.oe = vcc
+
+o16 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
+ i9 & /i11
+o16.oe = vcc
+
+o17 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
+ /i9 & /i11
+o17.oe = vcc
+
+o18 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
+ /i9 & i11 +
+ i19 +
+ /i12
+o18.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal12l6-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal12l6-to-peel18cv8.txt
new file mode 100644
index 00000000000..317521b8dec
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal12l6-to-peel18cv8.txt
@@ -0,0 +1,43 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+13 (Combinatorial, Output feedback output, Active low)
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
+/o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & i11 +
+ /i19 +
+ i12
+o13.oe = vcc
+
+/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ /i9 & i11
+o14.oe = vcc
+
+/o15 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & i11
+o15.oe = vcc
+
+/o16 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
+ /i9 & /i11
+o16.oe = vcc
+
+/o17 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
+ /i9 & /i11
+o17.oe = vcc
+
+/o18 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
+ /i9 & i11 +
+ i19 +
+ /i12
+o18.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal14h4-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal14h4-to-peel18cv8.txt
new file mode 100644
index 00000000000..36c44bf7b5e
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal14h4-to-peel18cv8.txt
@@ -0,0 +1,37 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+14 (Combinatorial, Output feedback output, Active high)
+15 (Combinatorial, Output feedback output, Active high)
+16 (Combinatorial, Output feedback output, Active high)
+17 (Combinatorial, Output feedback output, Active high)
+
+Equations:
+
+o14 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & i11 +
+ /i12 & /i13 +
+ i18 & /i19
+o14.oe = vcc
+
+o15 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ i9 & /i11 +
+ i12 & i13 +
+ /i18 & i19
+o15.oe = vcc
+
+o16 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
+ /i9 & i11 +
+ i12 & /i13 +
+ /i18 & /i19
+o16.oe = vcc
+
+o17 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
+ i9 & i11 +
+ /i12 & i13 +
+ i18 & i19
+o17.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal14l4-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal14l4-to-peel18cv8.txt
new file mode 100644
index 00000000000..ddbae1bd871
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal14l4-to-peel18cv8.txt
@@ -0,0 +1,37 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
+/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
+ /i9 & i11 +
+ i12 & /i13 +
+ i18 & i19
+o14.oe = vcc
+
+/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
+ /i9 & /i11 +
+ /i12 & i13 +
+ /i18 & i19
+o15.oe = vcc
+
+/o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
+ /i9 & /i11 +
+ i12 & i13 +
+ i18 & /i19
+o16.oe = vcc
+
+/o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
+ /i9 & i11 +
+ /i12 & /i13 +
+ /i18 & /i19
+o17.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal16h2-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal16h2-to-peel18cv8.txt
new file mode 100644
index 00000000000..8be12b5d9e7
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal16h2-to-peel18cv8.txt
@@ -0,0 +1,31 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+15 (Combinatorial, Output feedback output, Active high)
+16 (Combinatorial, Output feedback output, Active high)
+
+Equations:
+
+o15 = i1 & i2 & i3 & /i4 & i5 & /i6 & i7 & i8 +
+ i9 +
+ /i11 +
+ i12 +
+ /i13 +
+ i14 +
+ /i17 +
+ i18 & /i19
+o15.oe = vcc
+
+o16 = i1 & i2 & /i3 & i4 & /i5 & i6 & i7 & i8 +
+ /i9 +
+ i11 +
+ /i12 +
+ i13 +
+ /i14 +
+ i17 +
+ /i18 & i19
+o16.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal16l2-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal16l2-to-peel18cv8.txt
new file mode 100644
index 00000000000..f49e147580e
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal16l2-to-peel18cv8.txt
@@ -0,0 +1,31 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
+/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
+ /i9 +
+ /i11 +
+ /i12 +
+ i13 +
+ i14 +
+ i17 +
+ i18 & i19
+o15.oe = vcc
+
+/o16 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
+ i9 +
+ i11 +
+ i12 +
+ /i13 +
+ /i14 +
+ /i17 +
+ /i18 & /i19
+o16.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal16l8-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal16l8-to-peel18cv8.txt
new file mode 100644
index 00000000000..36a1304f807
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal16l8-to-peel18cv8.txt
@@ -0,0 +1,89 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Combinatorial, Output feedback output, Active low)
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
+/o12 = i3 & i7 & /i9 +
+ i1 & o13 +
+ i3 +
+ /i6 +
+ i8 +
+ /i9 +
+ i7 & /o13
+o12.oe = vcc
+
+/o13 = i11 & /o14 +
+ /i9 +
+ i8 +
+ /i7 +
+ /i6 & o14 +
+ i5 +
+ i4
+o13.oe = i2 & o14
+
+/o14 = i1 & /o15 +
+ /i8 +
+ i1 & /i8 +
+ i1 & /i2 & /o15 +
+ /i2 +
+ i2 & /i8 & o15 +
+ i3
+o14.oe = vcc
+
+/o15 = i3 & i6 & i7 & /i11 +
+ i6 & o16 +
+ i3 & /o16 +
+ i7 +
+ /i11 +
+ i6 & i7 +
+ i7 & /i11
+o15.oe = vcc
+
+/o16 = /i3 & /o17 +
+ /i4 & /i11 +
+ /i3 & /i4 +
+ /i3 & i4 +
+ /i7 & o17 +
+ /i7 & /i11 +
+ i4
+o16.oe = vcc
+
+/o17 = i2 & i5 & i6 & /i7 +
+ i2 & /o18 +
+ i5 +
+ i6 +
+ /i7 & o18 +
+ i2 & /i7 +
+ i5 & i6
+o17.oe = /o16
+
+/o18 = /i2 & i5 & i6 & /i7 +
+ i3 & i6 & i7 & i11 +
+ i3 +
+ /i2 & /i7 +
+ i3 & i11 +
+ i5 & i6 & /i7 +
+ i7 & i11
+o18.oe = vcc
+
+/o19 = i5 & i6 & /i7 & i11 +
+ i3 & i6 & i7 +
+ i5 +
+ i6 +
+ i7 +
+ i11 +
+ /i7
+o19.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal16r4-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal16r4-to-peel18cv8.txt
new file mode 100644
index 00000000000..7db8ff85b13
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal16r4-to-peel18cv8.txt
@@ -0,0 +1,93 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Combinatorial, Output feedback output, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
+/o12 = /i2 & /i3 +
+ i4 & o13 +
+ i3 +
+ /i6 +
+ i8 +
+ /i9 +
+ i7 & /o13
+o12.oe = rf14
+
+/o13 = /rf14 +
+ /i9 +
+ i8 +
+ /i7 +
+ /i6 & /rf14 +
+ i5 +
+ i4
+o13.oe = i2 & rf14
+
+/rf14 := /rf15 +
+ /i8 +
+ i8 +
+ /i2 & /rf15 +
+ /i2 +
+ i2 & /i8 & rf15 +
+ /i4 +
+ i3
+rf14.oe = /i11
+
+/rf15 := i3 & i6 & i7 +
+ i6 & rf16 +
+ i3 & /rf16 +
+ i7 +
+ /i4 +
+ i6 & i7 +
+ i4 & i7 +
+ /i2 & /i7
+rf15.oe = /i11
+
+/rf16 := /i3 & /rf17 +
+ /i4 +
+ /i3 +
+ /i3 & i4 +
+ /i7 & rf17 +
+ /i7 +
+ i4 +
+ i2 & i3
+rf16.oe = /i11
+
+/rf17 := i2 & i5 & i6 & /i7 +
+ i2 & /o18 +
+ i5 +
+ i6 +
+ /i7 & o18 +
+ i2 & /i7 +
+ i5 & i6 +
+ /i3
+rf17.oe = /i11
+
+/o18 = /i2 & i5 & i6 & /i7 +
+ i3 & i6 & i7 +
+ i3 +
+ /i2 & /i7 +
+ /i3 +
+ i5 & i6 & /i7 +
+ i7
+o18.oe = vcc
+
+/o19 = i5 & i6 & /i7 +
+ i3 & i6 & i7 +
+ i5 +
+ i6 +
+ i7 +
+ /i4 +
+ /i7
+o19.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal16r6-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal16r6-to-peel18cv8.txt
new file mode 100644
index 00000000000..7c88b6176a1
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal16r6-to-peel18cv8.txt
@@ -0,0 +1,95 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Registered, Output feedback registered, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
+/o12 = /i2 & /i3 +
+ i4 & rf13 +
+ i3 +
+ /i6 +
+ i8 +
+ /i9 +
+ i7 & /rf13
+o12.oe = rf14
+
+/rf13 := /rf14 +
+ /i9 +
+ i8 +
+ /i7 +
+ /i6 & /rf14 +
+ i5 & rf14 +
+ i4 +
+ /i2
+rf13.oe = /i11
+
+/rf14 := /rf15 +
+ /i8 +
+ i8 +
+ /i2 & /rf15 +
+ /i2 +
+ i2 & /i8 & rf15 +
+ /i4 +
+ i3
+rf14.oe = /i11
+
+/rf15 := i3 & i6 & i7 +
+ i6 & rf16 +
+ i3 & /rf16 +
+ i7 +
+ /i4 +
+ i6 & i7 +
+ i4 & i7 +
+ /i2 & /i7
+rf15.oe = /i11
+
+/rf16 := /i3 & /rf17 +
+ /i4 +
+ /i3 +
+ /i3 & i4 +
+ /i7 & rf17 +
+ /i7 +
+ i4 +
+ i2 & i3
+rf16.oe = /i11
+
+/rf17 := i2 & i5 & i6 & /i7 +
+ i2 & /rf18 +
+ i5 +
+ i6 +
+ /i7 & rf18 +
+ i2 & /i7 +
+ i5 & i6 +
+ /i3
+rf17.oe = /i11
+
+/rf18 := /i2 & i5 & i6 & /i7 +
+ i3 & i6 & i7 +
+ i3 +
+ /i2 & /i7 +
+ /i3 +
+ i5 & i6 & /i7 +
+ i7 +
+ i4
+rf18.oe = /i11
+
+/o19 = i5 & i6 & /i7 +
+ i3 & i6 & i7 +
+ i5 +
+ i6 +
+ i7 +
+ /i4 +
+ /i7
+o19.oe = vcc
+
diff --git a/src/regtests/jedutil/baseline/18cv8/pal16r8-to-peel18cv8.txt b/src/regtests/jedutil/baseline/18cv8/pal16r8-to-peel18cv8.txt
new file mode 100644
index 00000000000..cd37e419c00
--- /dev/null
+++ b/src/regtests/jedutil/baseline/18cv8/pal16r8-to-peel18cv8.txt
@@ -0,0 +1,97 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Registered, Output feedback registered, Active low)
+13 (Registered, Output feedback registered, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Registered, Output feedback registered, Active low)
+
+Equations:
+
+/rf12 := /i2 & /i3 +
+ i4 & rf13 +
+ i3 +
+ /i6 +
+ i8 +
+ /i9 +
+ i7 & /rf13 +
+ i5
+rf12.oe = /i11
+
+/rf13 := /rf14 +
+ /i9 +
+ i8 +
+ /i7 +
+ /i6 & rf14 +
+ i5 +
+ i4 +
+ /i3
+rf13.oe = /i11
+
+/rf14 := /rf15 +
+ /i8 +
+ i8 +
+ /i2 & /rf15 +
+ /i2 +
+ i2 & /i8 & rf15 +
+ /i4 +
+ i3
+rf14.oe = /i11
+
+/rf15 := i3 & i6 & i7 +
+ i6 & rf16 +
+ i3 & /rf16 +
+ i7 +
+ /i4 +
+ i6 & i7 +
+ i4 & i7 +
+ /i2 & /i7
+rf15.oe = /i11
+
+/rf16 := /i3 & /rf17 +
+ /i4 +
+ /i3 +
+ /i3 & i4 +
+ /i7 & rf17 +
+ /i7 +
+ i4 +
+ i2 & i3
+rf16.oe = /i11
+
+/rf17 := i2 & i5 & i6 & /i7 +
+ i2 & /rf18 +
+ i5 +
+ i6 +
+ /i7 & rf18 +
+ i2 & /i7 +
+ i5 & i6 +
+ /i3
+rf17.oe = /i11
+
+/rf18 := /i2 & i5 & i6 & /i7 +
+ i3 & i6 & i7 +
+ i3 & rf19 +
+ /i2 & /i7 +
+ /i3 & /rf19 +
+ i5 & i6 & /i7 +
+ i7 +
+ /i4
+rf18.oe = /i11
+
+/rf19 := i5 & i6 & /i7 +
+ i3 & i6 & i7 +
+ i5 & rf12 +
+ i6 +
+ i7 +
+ /i4 & /rf12 +
+ /i7 +
+ i2
+rf19.oe = /i11
+
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal10h8-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal10h8-to-gal16v8.txt
index ee5a96c35dc..7b49c5e8a42 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal10h8-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal10h8-to-gal16v8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active high)
+13 (Combinatorial, Output feedback output, Active high)
+14 (Combinatorial, Output feedback output, Active high)
+15 (Combinatorial, No output feedback, Active high)
+16 (Combinatorial, No output feedback, Active high)
+17 (Combinatorial, Output feedback output, Active high)
+18 (Combinatorial, Output feedback output, Active high)
+19 (Combinatorial, Output feedback output, Active high)
+
+Equations:
+
o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11
o12.oe = vcc
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal10l8-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal10l8-to-gal16v8.txt
index eb5b456f150..6a014ee5bb1 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal10l8-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal10l8-to-gal16v8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Combinatorial, Output feedback output, Active low)
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11
o12.oe = vcc
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal12h6-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal12h6-to-gal16v8.txt
index 35bc596f5f8..beff18b6149 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal12h6-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal12h6-to-gal16v8.txt
@@ -1,3 +1,18 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+13 (Combinatorial, Output feedback output, Active high)
+14 (Combinatorial, Output feedback output, Active high)
+15 (Combinatorial, No output feedback, Active high)
+16 (Combinatorial, No output feedback, Active high)
+17 (Combinatorial, Output feedback output, Active high)
+18 (Combinatorial, Output feedback output, Active high)
+
+Equations:
+
o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11 +
/i19 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal12l6-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal12l6-to-gal16v8.txt
index 361c3178972..2dbd6579d0a 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal12l6-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal12l6-to-gal16v8.txt
@@ -1,3 +1,18 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+13 (Combinatorial, Output feedback output, Active low)
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11 +
/i19 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal14h4-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal14h4-to-gal16v8.txt
index 52ce0d9bfc2..70bea92edd5 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal14h4-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal14h4-to-gal16v8.txt
@@ -1,3 +1,16 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+14 (Combinatorial, Output feedback output, Active high)
+15 (Combinatorial, No output feedback, Active high)
+16 (Combinatorial, No output feedback, Active high)
+17 (Combinatorial, Output feedback output, Active high)
+
+Equations:
+
o14 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11 +
/i12 & /i13 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal14l4-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal14l4-to-gal16v8.txt
index c17cae37706..a094121bdbd 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal14l4-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal14l4-to-gal16v8.txt
@@ -1,3 +1,16 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
/i9 & i11 +
i12 & /i13 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal16h2-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal16h2-to-gal16v8.txt
index 61cbfcbbeac..3ad2680c48f 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal16h2-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal16h2-to-gal16v8.txt
@@ -1,3 +1,14 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+15 (Combinatorial, No output feedback, Active high)
+16 (Combinatorial, No output feedback, Active high)
+
+Equations:
+
o15 = i1 & i2 & i3 & /i4 & i5 & /i6 & i7 & i8 +
i9 +
/i11 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal16l2-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal16l2-to-gal16v8.txt
index 26c0052e20b..7d19f691192 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal16l2-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal16l2-to-gal16v8.txt
@@ -1,3 +1,14 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active low)
+
+Equations:
+
/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
/i9 +
/i11 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal16l8-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal16l8-to-gal16v8.txt
index c6cf49bc84d..5d7e5a5df94 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal16l8-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal16l8-to-gal16v8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14, 15, 16, 17, 18
+
+Outputs:
+
+12 (Combinatorial, No output feedback, Active low)
+13 (Combinatorial, Output feedback output, Active low)
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, No output feedback, Active low)
+
+Equations:
+
/o12 = i3 & i7 & /i9 +
i1 & o13 +
i3 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal16r4-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal16r4-to-gal16v8.txt
index 601701c2d4d..dcc158eb61b 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal16r4-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal16r4-to-gal16v8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Combinatorial, Output feedback output, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o12 = /i2 & /i3 +
i4 & o13 +
i3 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal16r6-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal16r6-to-gal16v8.txt
index 15c0373dbdf..ecbb979cdc1 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal16r6-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal16r6-to-gal16v8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Registered, Output feedback registered, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o12 = /i2 & /i3 +
i4 & rf13 +
i3 +
diff --git a/src/regtests/jedutil/baseline/gal16v8/pal16r8-to-gal16v8.txt b/src/regtests/jedutil/baseline/gal16v8/pal16r8-to-gal16v8.txt
index 0e6570d3a63..99beae32944 100644
--- a/src/regtests/jedutil/baseline/gal16v8/pal16r8-to-gal16v8.txt
+++ b/src/regtests/jedutil/baseline/gal16v8/pal16r8-to-gal16v8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Registered, Output feedback registered, Active low)
+13 (Registered, Output feedback registered, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Registered, Output feedback registered, Active low)
+
+Equations:
+
/rf12 := /i2 & /i3 +
i4 & rf13 +
i3 +
diff --git a/src/regtests/jedutil/baseline/pal10h8/pal10h8.txt b/src/regtests/jedutil/baseline/pal10h8/pal10h8.txt
index ee5a96c35dc..936491ce36e 100644
--- a/src/regtests/jedutil/baseline/pal10h8/pal10h8.txt
+++ b/src/regtests/jedutil/baseline/pal10h8/pal10h8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11
+
+Outputs:
+
+12 (Combinatorial, No output feedback, Active high)
+13 (Combinatorial, No output feedback, Active high)
+14 (Combinatorial, No output feedback, Active high)
+15 (Combinatorial, No output feedback, Active high)
+16 (Combinatorial, No output feedback, Active high)
+17 (Combinatorial, No output feedback, Active high)
+18 (Combinatorial, No output feedback, Active high)
+19 (Combinatorial, No output feedback, Active high)
+
+Equations:
+
o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11
o12.oe = vcc
diff --git a/src/regtests/jedutil/baseline/pal10l8/pal10l8.txt b/src/regtests/jedutil/baseline/pal10l8/pal10l8.txt
index eb5b456f150..30587b97217 100644
--- a/src/regtests/jedutil/baseline/pal10l8/pal10l8.txt
+++ b/src/regtests/jedutil/baseline/pal10l8/pal10l8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11
+
+Outputs:
+
+12 (Combinatorial, No output feedback, Active low)
+13 (Combinatorial, No output feedback, Active low)
+14 (Combinatorial, No output feedback, Active low)
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active low)
+17 (Combinatorial, No output feedback, Active low)
+18 (Combinatorial, No output feedback, Active low)
+19 (Combinatorial, No output feedback, Active low)
+
+Equations:
+
/o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11
o12.oe = vcc
diff --git a/src/regtests/jedutil/baseline/pal12h6/pal12h6.txt b/src/regtests/jedutil/baseline/pal12h6/pal12h6.txt
index 35bc596f5f8..7e658cd29ec 100644
--- a/src/regtests/jedutil/baseline/pal12h6/pal12h6.txt
+++ b/src/regtests/jedutil/baseline/pal12h6/pal12h6.txt
@@ -1,3 +1,18 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 19
+
+Outputs:
+
+13 (Combinatorial, No output feedback, Active high)
+14 (Combinatorial, No output feedback, Active high)
+15 (Combinatorial, No output feedback, Active high)
+16 (Combinatorial, No output feedback, Active high)
+17 (Combinatorial, No output feedback, Active high)
+18 (Combinatorial, No output feedback, Active high)
+
+Equations:
+
o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11 +
/i19 +
diff --git a/src/regtests/jedutil/baseline/pal12l6/pal12l6.txt b/src/regtests/jedutil/baseline/pal12l6/pal12l6.txt
index 361c3178972..16b2aafcf89 100644
--- a/src/regtests/jedutil/baseline/pal12l6/pal12l6.txt
+++ b/src/regtests/jedutil/baseline/pal12l6/pal12l6.txt
@@ -1,3 +1,18 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 19
+
+Outputs:
+
+13 (Combinatorial, No output feedback, Active low)
+14 (Combinatorial, No output feedback, Active low)
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active low)
+17 (Combinatorial, No output feedback, Active low)
+18 (Combinatorial, No output feedback, Active low)
+
+Equations:
+
/o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11 +
/i19 +
diff --git a/src/regtests/jedutil/baseline/pal14h4/pal14h4.txt b/src/regtests/jedutil/baseline/pal14h4/pal14h4.txt
index 52ce0d9bfc2..93e7efa3d4f 100644
--- a/src/regtests/jedutil/baseline/pal14h4/pal14h4.txt
+++ b/src/regtests/jedutil/baseline/pal14h4/pal14h4.txt
@@ -1,3 +1,16 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 18, 19
+
+Outputs:
+
+14 (Combinatorial, No output feedback, Active high)
+15 (Combinatorial, No output feedback, Active high)
+16 (Combinatorial, No output feedback, Active high)
+17 (Combinatorial, No output feedback, Active high)
+
+Equations:
+
o14 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
i9 & i11 +
/i12 & /i13 +
diff --git a/src/regtests/jedutil/baseline/pal14l4/pal14l4.txt b/src/regtests/jedutil/baseline/pal14l4/pal14l4.txt
index c17cae37706..faa13e4cbea 100644
--- a/src/regtests/jedutil/baseline/pal14l4/pal14l4.txt
+++ b/src/regtests/jedutil/baseline/pal14l4/pal14l4.txt
@@ -1,3 +1,16 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 18, 19
+
+Outputs:
+
+14 (Combinatorial, No output feedback, Active low)
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active low)
+17 (Combinatorial, No output feedback, Active low)
+
+Equations:
+
/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
/i9 & i11 +
i12 & /i13 +
diff --git a/src/regtests/jedutil/baseline/pal16c1/pal16c1.txt b/src/regtests/jedutil/baseline/pal16c1/pal16c1.txt
index 9b5918d3bbe..7a439cb0c72 100644
--- a/src/regtests/jedutil/baseline/pal16c1/pal16c1.txt
+++ b/src/regtests/jedutil/baseline/pal16c1/pal16c1.txt
@@ -1,3 +1,14 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active high)
+
+Equations:
+
/o15 = i1 & i2 +
i3 & i4 +
i5 & i6 +
diff --git a/src/regtests/jedutil/baseline/pal16h2/pal16h2.txt b/src/regtests/jedutil/baseline/pal16h2/pal16h2.txt
index 61cbfcbbeac..3ad2680c48f 100644
--- a/src/regtests/jedutil/baseline/pal16h2/pal16h2.txt
+++ b/src/regtests/jedutil/baseline/pal16h2/pal16h2.txt
@@ -1,3 +1,14 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+15 (Combinatorial, No output feedback, Active high)
+16 (Combinatorial, No output feedback, Active high)
+
+Equations:
+
o15 = i1 & i2 & i3 & /i4 & i5 & /i6 & i7 & i8 +
i9 +
/i11 +
diff --git a/src/regtests/jedutil/baseline/pal16l2/pal16l2.txt b/src/regtests/jedutil/baseline/pal16l2/pal16l2.txt
index 26c0052e20b..7d19f691192 100644
--- a/src/regtests/jedutil/baseline/pal16l2/pal16l2.txt
+++ b/src/regtests/jedutil/baseline/pal16l2/pal16l2.txt
@@ -1,3 +1,14 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 17, 18, 19
+
+Outputs:
+
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, No output feedback, Active low)
+
+Equations:
+
/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
/i9 +
/i11 +
diff --git a/src/regtests/jedutil/baseline/pal16l8/pal16l8.txt b/src/regtests/jedutil/baseline/pal16l8/pal16l8.txt
index c6cf49bc84d..9a95fea0e51 100644
--- a/src/regtests/jedutil/baseline/pal16l8/pal16l8.txt
+++ b/src/regtests/jedutil/baseline/pal16l8/pal16l8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14, 15, 16, 17, 18
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Combinatorial, Output feedback output, Active low)
+14 (Combinatorial, Output feedback output, Active low)
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o12 = i3 & i7 & /i9 +
i1 & o13 +
i3 +
diff --git a/src/regtests/jedutil/baseline/pal16r4/pal16r4.txt b/src/regtests/jedutil/baseline/pal16r4/pal16r4.txt
index 601701c2d4d..dcc158eb61b 100644
--- a/src/regtests/jedutil/baseline/pal16r4/pal16r4.txt
+++ b/src/regtests/jedutil/baseline/pal16r4/pal16r4.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Combinatorial, Output feedback output, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o12 = /i2 & /i3 +
i4 & o13 +
i3 +
diff --git a/src/regtests/jedutil/baseline/pal16r6/pal16r6.txt b/src/regtests/jedutil/baseline/pal16r6/pal16r6.txt
index 15c0373dbdf..ecbb979cdc1 100644
--- a/src/regtests/jedutil/baseline/pal16r6/pal16r6.txt
+++ b/src/regtests/jedutil/baseline/pal16r6/pal16r6.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Combinatorial, Output feedback output, Active low)
+13 (Registered, Output feedback registered, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o12 = /i2 & /i3 +
i4 & rf13 +
i3 +
diff --git a/src/regtests/jedutil/baseline/pal16r8/pal16r8.txt b/src/regtests/jedutil/baseline/pal16r8/pal16r8.txt
index 0e6570d3a63..99beae32944 100644
--- a/src/regtests/jedutil/baseline/pal16r8/pal16r8.txt
+++ b/src/regtests/jedutil/baseline/pal16r8/pal16r8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19
+
+Outputs:
+
+12 (Registered, Output feedback registered, Active low)
+13 (Registered, Output feedback registered, Active low)
+14 (Registered, Output feedback registered, Active low)
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Registered, Output feedback registered, Active low)
+
+Equations:
+
/rf12 := /i2 & /i3 +
i4 & rf13 +
i3 +
diff --git a/src/regtests/jedutil/baseline/pal20l10/pal20l10.txt b/src/regtests/jedutil/baseline/pal20l10/pal20l10.txt
index 3dbc917c1ee..a5a34c825a0 100644
--- a/src/regtests/jedutil/baseline/pal20l10/pal20l10.txt
+++ b/src/regtests/jedutil/baseline/pal20l10/pal20l10.txt
@@ -1,3 +1,22 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 16, 17, 18, 19, 20, 21, 22
+
+Outputs:
+
+14 (Combinatorial, No output feedback, Active low)
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+20 (Combinatorial, Output feedback output, Active low)
+21 (Combinatorial, Output feedback output, Active low)
+22 (Combinatorial, Output feedback output, Active low)
+23 (Combinatorial, No output feedback, Active low)
+
+Equations:
+
/o14 = /i11 +
i10 +
i9 & /o15
diff --git a/src/regtests/jedutil/baseline/pal20l8/pal20l8.txt b/src/regtests/jedutil/baseline/pal20l8/pal20l8.txt
index 6cf68531f5b..3db690d615b 100644
--- a/src/regtests/jedutil/baseline/pal20l8/pal20l8.txt
+++ b/src/regtests/jedutil/baseline/pal20l8/pal20l8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 16, 17, 18, 19, 20, 21, 23
+
+Outputs:
+
+15 (Combinatorial, No output feedback, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Combinatorial, Output feedback output, Active low)
+18 (Combinatorial, Output feedback output, Active low)
+19 (Combinatorial, Output feedback output, Active low)
+20 (Combinatorial, Output feedback output, Active low)
+21 (Combinatorial, Output feedback output, Active low)
+22 (Combinatorial, No output feedback, Active low)
+
+Equations:
+
/o15 = /i1 & i2 & /i3 & i4 & i11 +
/i1 & i2 & /i3 & /i5 & /i13 +
/i1 & i2 & /i3 & i6 & i14 +
diff --git a/src/regtests/jedutil/baseline/pal20r4/pal20r4.txt b/src/regtests/jedutil/baseline/pal20r4/pal20r4.txt
index b1eb4620277..eaf9bca00c6 100644
--- a/src/regtests/jedutil/baseline/pal20r4/pal20r4.txt
+++ b/src/regtests/jedutil/baseline/pal20r4/pal20r4.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23
+
+Outputs:
+
+15 (Combinatorial, Output feedback output, Active low)
+16 (Combinatorial, Output feedback output, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Registered, Output feedback registered, Active low)
+20 (Registered, Output feedback registered, Active low)
+21 (Combinatorial, Output feedback output, Active low)
+22 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o15 = i2 & i6 & i7 +
i6 & o16 +
i3 & /o16 +
diff --git a/src/regtests/jedutil/baseline/pal20r6/pal20r6.txt b/src/regtests/jedutil/baseline/pal20r6/pal20r6.txt
index 4a468c30935..c89257c22cd 100644
--- a/src/regtests/jedutil/baseline/pal20r6/pal20r6.txt
+++ b/src/regtests/jedutil/baseline/pal20r6/pal20r6.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23
+
+Outputs:
+
+15 (Combinatorial, Output feedback output, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Registered, Output feedback registered, Active low)
+20 (Registered, Output feedback registered, Active low)
+21 (Registered, Output feedback registered, Active low)
+22 (Combinatorial, Output feedback output, Active low)
+
+Equations:
+
/o15 = i2 & i6 & i7 +
i6 & rf16 +
i3 & /rf16 +
diff --git a/src/regtests/jedutil/baseline/pal20r8/pal20r8.txt b/src/regtests/jedutil/baseline/pal20r8/pal20r8.txt
index 732e3f89044..a5ed5d22cfe 100644
--- a/src/regtests/jedutil/baseline/pal20r8/pal20r8.txt
+++ b/src/regtests/jedutil/baseline/pal20r8/pal20r8.txt
@@ -1,3 +1,20 @@
+Inputs:
+
+2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23
+
+Outputs:
+
+15 (Registered, Output feedback registered, Active low)
+16 (Registered, Output feedback registered, Active low)
+17 (Registered, Output feedback registered, Active low)
+18 (Registered, Output feedback registered, Active low)
+19 (Registered, Output feedback registered, Active low)
+20 (Registered, Output feedback registered, Active low)
+21 (Registered, Output feedback registered, Active low)
+22 (Registered, Output feedback registered, Active low)
+
+Equations:
+
/rf15 := i2 & i6 & i7 +
i6 & rf16 +
i3 & /rf16 +
diff --git a/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_bi-directional_io.psf b/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_bi-directional_io.psf
new file mode 100644
index 00000000000..6c1ed922165
--- /dev/null
+++ b/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_bi-directional_io.psf
@@ -0,0 +1,64 @@
+Title 'PEEL18CV8 Test Data'
+Designer 'MAMEDev'
+Date '10-7-2012'
+
+Description
+ Determine Bi-directional IO fuses.
+End_Desc;
+
+PEEL18CV8
+
+I1 PIN 1
+I2 PIN 2
+I3 PIN 3
+I4 PIN 4
+I5 PIN 5
+I6 PIN 6
+I7 PIN 7
+I8 PIN 8
+I9 PIN 9
+I11 PIN 11
+
+IOC (12 'O12' POS OUTCOM FEED_PIN)
+IOC (13 'I13' POS IN FEED_PIN)
+IOC (14 'RF14' POS REG FEED_PIN)
+IOC (15 'I15' NEG IN FEED_PIN)
+IOC (16 'RF16' NEG REG FEED_PIN)
+IOC (17 'I17' POS IN FEED_PIN)
+IOC (18 'O18' NEG OUTCOM FEED_PIN)
+IOC (19 'I19' POS IN FEED_PIN)
+
+
+AR NODE 21; " Asynchronous reset
+SP NODE 22; " Synchronous reset
+
+Define
+
+EQUATIONS
+
+AR = 0;
+SP = 0;
+
+O12.COM = I1 & /I2 #
+ I13 & /RF14 & RF16 #
+ /I3 & /I4 & /I5 & I6 #
+ I15 & RF14 & /RF16 #
+ /O18;
+O12.OE = O18;
+
+RF14.REG = I11 & /RF14 #
+ O12 & /RF16 & O18 #
+ RF16 & /O18;
+RF14.OE = /O12;
+
+RF16.REG = I13 & RF16 #
+ /O12 & /RF14 & /O18 #
+ O12 & RF14;
+RF16.OE = O18;
+
+O18.COM = /I7 & I8 & O12 #
+ /I9 & /I11 & RF14 #
+ I19 & /I15 & RF16 #
+ /O12 #
+ /RF14 & /RF16;
+O18.OE = 1; " output always enabled
diff --git a/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_combinatorial_feedback.psf b/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_combinatorial_feedback.psf
new file mode 100644
index 00000000000..4b01591b423
--- /dev/null
+++ b/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_combinatorial_feedback.psf
@@ -0,0 +1,62 @@
+Title 'PEEL18CV8 Combinatorial Feedback Test Data'
+Designer 'MAMEDev'
+Date '11-11-2012'
+
+Description
+ Determine Combinatorial Feedback fuses.
+End_Desc;
+
+PEEL18CV8
+
+I1 PIN 1
+I2 PIN 2
+I3 PIN 3
+I4 PIN 4
+I5 PIN 5
+I6 PIN 6
+I7 PIN 7
+I8 PIN 8
+I9 PIN 9
+I11 PIN 11
+
+IOC (12 'I12' POS IN FEED_PIN)
+IOC (13 'RF13' NEG REG FEED_OR)
+IOC (14 'I14' POS IN FEED_PIN)
+IOC (15 'RF15' POS REG FEED_OR)
+IOC (16 'I16' NEG IN FEED_PIN)
+IOC (17 'O17' POS COM FEED_OR)
+IOC (18 'I18' NEG IN FEED_PIN)
+IOC (19 'O19' NEG COM FEED_OR)
+
+
+AR NODE 21; " Asynchronous reset
+SP NODE 22; " Synchronous reset
+
+Define
+
+EQUATIONS
+
+AR = 0;
+SP = 0;
+
+RF13.REG = I1 & /I2 & O19 #
+ I12 & /RF15 #
+ /I3 & /I4 & /I5 & I6 #
+ I14 & RF15 #
+ /O17 & /O19;
+RF13.OE = O17;
+
+RF15.REG = I11 & /I12 & RF13 & /O17 #
+ /O19 #
+ O17 & O19;
+RF15.OE = /RF13;
+
+O17.COM = /RF13 & RF15 & I16 & O19 #
+ RF13 & /RF15 #
+ /O19;
+O17.OE = 1;
+
+O19.COM = /I7 & I8 & /RF13 & /RF15 #
+ /I9 & /I11 & RF15 #
+ RF13 & I16 & /O17 & /I18;
+O19.OE = O17;
diff --git a/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_register_feedback.psf b/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_register_feedback.psf
new file mode 100644
index 00000000000..7757dd94166
--- /dev/null
+++ b/src/regtests/jedutil/eqns/ICT_Place/PEEL18CV8/18cv8_register_feedback.psf
@@ -0,0 +1,62 @@
+Title 'PEEL18CV8 Register Feedback Test Data'
+Designer 'MAMEDev'
+Date '11-25-2012'
+
+Description
+ Determine Register Feedback fuses.
+End_Desc;
+
+PEEL18CV8
+
+I1 PIN 1
+I2 PIN 2
+I3 PIN 3
+I4 PIN 4
+I5 PIN 5
+I6 PIN 6
+I7 PIN 7
+I8 PIN 8
+I9 PIN 9
+I11 PIN 11
+
+IOC (12 'I12' POS IN FEED_PIN)
+IOC (13 'O13' POS COM FEED_REG)
+IOC (14 'I14' POS IN FEED_PIN)
+IOC (15 'RF15' NEG REG FEED_REG)
+IOC (16 'I16' NEG IN FEED_PIN)
+IOC (17 'O17' NEG COM FEED_REG)
+IOC (18 'I18' NEG IN FEED_PIN)
+IOC (19 'RF19' POS REG FEED_REG)
+
+
+AR NODE 21; " Asynchronous reset
+SP NODE 22; " Synchronous reset
+
+Define
+
+EQUATIONS
+
+AR = 0;
+SP = 0;
+
+O13.COM = I3 & O17 #
+ /I9 & /RF19 #
+ I7 & RF19 #
+ /I12 & RF15 #
+ /RF15 & /O17;
+O13.OE = 1;
+
+RF15.REG = /O13 & RF19 #
+ /O17 #
+ O13 & O17 & /RF19;
+RF15.OE = O17;
+
+O17.COM = I1 & /O13 & I16 & /RF15 #
+ RF15 & RF19 #
+ O13;
+O17.OE = /RF19;
+
+RF19.REG = I8 & RF15 & O17 #
+ I1 & I2 & /RF15 #
+ O13 & /O17;
+RF19.OE = /O13;
diff --git a/src/regtests/jedutil/eqns/ICT_Place/readme.txt b/src/regtests/jedutil/eqns/ICT_Place/readme.txt
new file mode 100644
index 00000000000..a234666e26d
--- /dev/null
+++ b/src/regtests/jedutil/eqns/ICT_Place/readme.txt
@@ -0,0 +1 @@
+These files are for use with the utilities place and plcom which are included with ICT Place. The place tool was used to configure the pins and the plcom tool was used to create the jed files. (Under Windows 7 64-bit the place tool will not run under the Windows XP VM downloadable for free with Windows 7, but will run under DOSBox.)
diff --git a/src/regtests/jedutil/eqns/Opal_Jr/readme.txt b/src/regtests/jedutil/eqns/Opal_Jr/readme.txt
new file mode 100644
index 00000000000..94dcdf6ab46
--- /dev/null
+++ b/src/regtests/jedutil/eqns/Opal_Jr/readme.txt
@@ -0,0 +1 @@
+This files are for use with the utility eqn2jed which is a tool included with Opal Jr. The tools takes this equation files and automatically creates a jed file.
diff --git a/src/regtests/jedutil/eqns/pal10l8/pal10l8.eqn b/src/regtests/jedutil/eqns/pal10l8/pal10l8.eqn
index b316ec32d26..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal10l8/pal10l8.eqn
+++ b/src/regtests/jedutil/eqns/pal10l8/pal10l8.eqn
@@ -1,30 +0,0 @@
-chip 2000 PAL10L8
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
-o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20
-
-equations
-
-/o12 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- i9 & i11
-
-/o13 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- /i9 & i11
-
-/o14 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
- i9 & /i11
-
-/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
- /i9 & /i11
-
-/o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
- /i9 & /i11
-
-/o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
- i9 & /i11
-
-/o18 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
- i11
-
-/o19 = i1 & i2 & i3 & i4 & i5 & i6 & i7 & /i8 +
- /i9
diff --git a/src/regtests/jedutil/eqns/pal12h6/pal12h6.eqn b/src/regtests/jedutil/eqns/pal12h6/pal12h6.eqn
index 43b72ca6dc3..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal12h6/pal12h6.eqn
+++ b/src/regtests/jedutil/eqns/pal12h6/pal12h6.eqn
@@ -1,28 +0,0 @@
-chip 2000 PAL12H6
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
-i12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 i19=19 VCC=20
-
-equations
-
-o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- i9 & i11 +
- /i19 +
- i12
-
-o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- /i9 & i11
-
-o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
- /i9 & /i11
-
-o16 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
- i9 & /i11
-
-o17 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
- /i9 & /i11
-
-o18 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
- /i9 & i11 +
- i19 +
- /i12
diff --git a/src/regtests/jedutil/eqns/pal12l6/pal12l6.eqn b/src/regtests/jedutil/eqns/pal12l6/pal12l6.eqn
index a1867dd827a..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal12l6/pal12l6.eqn
+++ b/src/regtests/jedutil/eqns/pal12l6/pal12l6.eqn
@@ -1,28 +0,0 @@
-chip 2000 PAL12L6
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
-i12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 i19=19 VCC=20
-
-equations
-
-/o13 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- i9 & i11 +
- /i19 +
- i12
-
-/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- /i9 & i11
-
-/o15 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
- i9 & i11
-
-/o16 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
- /i9 & /i11
-
-/o17 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
- /i9 & /i11
-
-/o18 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
- /i9 & i11 +
- i19 +
- /i12
diff --git a/src/regtests/jedutil/eqns/pal14h4/pal14h4.eqn b/src/regtests/jedutil/eqns/pal14h4/pal14h4.eqn
index 7db1b42ee27..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal14h4/pal14h4.eqn
+++ b/src/regtests/jedutil/eqns/pal14h4/pal14h4.eqn
@@ -1,26 +0,0 @@
-chip 2000 PAL14H4
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
-i12=12 i13=13 o14=14 o15=15 o16=16 o17=17 i18=18 i19=19 VCC=20
-
-equations
-
-o14 = /i1 & i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- i9 & i11 +
- /i12 & /i13 +
- i18 & /i19
-
-o15 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- i9 & /i11 +
- i12 & i13 +
- /i18 & i19
-
-o16 = i1 & i2 & /i3 & i4 & i5 & i6 & i7 & i8 +
- /i9 & i11 +
- i12 & /i13 +
- /i18 & /i19
-
-o17 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
- i9 & i11 +
- /i12 & i13 +
- i18 & i19
diff --git a/src/regtests/jedutil/eqns/pal14l4/pal14l4.eqn b/src/regtests/jedutil/eqns/pal14l4/pal14l4.eqn
index 0e63b68c612..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal14l4/pal14l4.eqn
+++ b/src/regtests/jedutil/eqns/pal14l4/pal14l4.eqn
@@ -1,26 +0,0 @@
-chip 2000 PAL14L4
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
-i12=12 i13=13 o14=14 o15=15 o16=16 o17=17 i18=18 i19=19 VCC=20
-
-equations
-
-/o14 = i1 & /i2 & i3 & i4 & i5 & i6 & i7 & i8 +
- /i9 & i11 +
- i12 & /i13 +
- i18 & i19
-
-/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
- /i9 & /i11 +
- /i12 & i13 +
- /i18 & i19
-
-/o16 = i1 & i2 & i3 & i4 & /i5 & i6 & i7 & i8 +
- /i9 & /i11 +
- i12 & i13 +
- i18 & /i19
-
-/o17 = i1 & i2 & i3 & i4 & i5 & /i6 & i7 & i8 +
- /i9 & i11 +
- /i12 & /i13 +
- /i18 & /i19
diff --git a/src/regtests/jedutil/eqns/pal16c1/pal16c1.eqn b/src/regtests/jedutil/eqns/pal16c1/pal16c1.eqn
index d2566d34cb4..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal16c1/pal16c1.eqn
+++ b/src/regtests/jedutil/eqns/pal16c1/pal16c1.eqn
@@ -1,23 +0,0 @@
-chip 2000 PAL16C1
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
-i12=12 i13=13 i14=14 o15=15 o16=16 i17=17 i18=18 i19=19 VCC=20
-
-equations
-
-/o15 = i1 & i2 +
- i3 & i4 +
- i5 & i6 +
- i7 & i8 +
- i9 & i11 +
- i12 & i13 +
- i14 & i17 +
- i18 & i19 +
- /i1 & /i2 +
- /i3 & /i4 +
- /i5 & /i6 +
- /i7 & /i8 +
- /i9 & /i11 +
- /i12 & /i13 +
- /i14 & /i17 +
- /i18 & /i19
diff --git a/src/regtests/jedutil/eqns/pal16h2/pal16h2.eqn b/src/regtests/jedutil/eqns/pal16h2/pal16h2.eqn
index cd597b209c2..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal16h2/pal16h2.eqn
+++ b/src/regtests/jedutil/eqns/pal16h2/pal16h2.eqn
@@ -1,24 +0,0 @@
-chip 2000 PAL16H2
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
-i12=12 i13=13 i14=14 o15=15 o16=16 i17=17 i18=18 i19=19 VCC=20
-
-equations
-
-o15 = i1 & i2 & i3 & /i4 & i5 & /i6 & i7 & i8 +
- i9 +
- /i11 +
- i12 +
- /i13 +
- i14 +
- /i17 +
- i18 & /i19
-
-o16 = i1 & i2 & /i3 & i4 & /i5 & i6 & i7 & i8 +
- /i9 +
- i11 +
- /i12 +
- i13 +
- /i14 +
- i17 +
- /i18 & i19
diff --git a/src/regtests/jedutil/eqns/pal16l2/pal16l2.eqn b/src/regtests/jedutil/eqns/pal16l2/pal16l2.eqn
index d68a83e9173..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal16l2/pal16l2.eqn
+++ b/src/regtests/jedutil/eqns/pal16l2/pal16l2.eqn
@@ -1,24 +0,0 @@
-chip 2000 PAL16L2
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11
-i12=12 i13=13 i14=14 o15=15 o16=16 i17=17 i18=18 i19=19 VCC=20
-
-equations
-
-/o15 = i1 & i2 & i3 & /i4 & i5 & i6 & i7 & i8 +
- /i9 +
- /i11 +
- /i12 +
- i13 +
- i14 +
- i17 +
- i18 & i19
-
-/o16 = i1 & i2 & i3 & i4 & i5 & i6 & /i7 & i8 +
- i9 +
- i11 +
- i12 +
- /i13 +
- /i14 +
- /i17 +
- /i18 & /i19
diff --git a/src/regtests/jedutil/eqns/pal16l8/pal16l8.eqn b/src/regtests/jedutil/eqns/pal16l8/pal16l8.eqn
index 6daddee92dd..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal16l8/pal16l8.eqn
+++ b/src/regtests/jedutil/eqns/pal16l8/pal16l8.eqn
@@ -1,79 +0,0 @@
-md
-chip 2000 PAL16L8
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10
-i11=11 o12=12 o13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 VCC=20
-
-equations
-
-/o12 = i3 & i7 & /i9 +
- i1 & o13 +
- i3 +
- /i6 +
- i8 +
- /i9 +
- i7 & /o13
-o12.oe = vcc
-
-/o13 = i11 & /o14 +
- /i9 +
- i8 +
- /i7 +
- /i6 & o14 +
- i5 +
- i4
-o13.oe = i2 & o14
-
-/o14 = i1 & /o15 +
- /i8 +
- i1 & /i8 +
- i1 & /i2 & /o15 +
- /i2 +
- i2 & /i8 & o15 +
- i3
-o14.oe = vcc
-
-/o15 = i3 & i6 & i7 & /i11 +
- i6 & o16 +
- i3 & /o16 +
- i7 +
- /i11 +
- i6 & i7 +
- i7 & /i11
-o15.oe = vcc
-
-/o16 = /i3 & /o17 +
- /i4 & /i11 +
- /i4 & /i3 +
- /i3 & i4 +
- /i7 & o17 +
- /i7 & /i11 +
- i4
-o16.oe = vcc
-
-/o17 = i2 & i5 & i6 & /i7 +
- i2 & /o18 +
- i5 +
- i6 +
- /i7 & o18 +
- i2 & /i7 +
- i5 & i6
-o17.oe = /o16
-
-/o18 = /i2 & i5 & i6 & /i7 +
- i3 & i6 & i7 & i11 +
- i3 +
- /i2 & /i7 +
- i3 & i11 +
- i5 & i6 & /i7 +
- i7 & i11
-o18.oe = vcc
-
-/o19 = i5 & i6 & /i7 & i11 +
- i3 & i6 & i7 +
- i5 +
- i6 +
- i7 +
- i11 +
- /i7
-o19.oe = vcc
diff --git a/src/regtests/jedutil/eqns/pal16r4/pal16r4.eqn b/src/regtests/jedutil/eqns/pal16r4/pal16r4.eqn
index 9a62f9ec02a..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal16r4/pal16r4.eqn
+++ b/src/regtests/jedutil/eqns/pal16r4/pal16r4.eqn
@@ -1,82 +0,0 @@
-chip pal16r4 PAL16R4
-
-CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10
-/OE=11 o12=12 o13=13 rf14=14 rf15=15 rf16=16 rf17=17 o18=18 o19=19 VCC=20
-
-equations
-
-/o12 = /i2 & /i3 +
- i4 & o13 +
- i3 +
- /i6 +
- i8 +
- /i9 +
- i7 & /o13
-o12.oe = rf14
-
-/o13 = /rf14 +
- /i9 +
- i8 +
- /i7 +
- /i6 & /rf14 +
- i5 +
- i4
-o13.oe = i2 & rf14
-
-/rf14 := /rf15 +
- /i8 +
- i8 +
- /i2 & /rf15 +
- /i2 +
- i2 & /i8 & rf15 +
- /i4 +
- i3
-rf14.oe = OE
-
-/rf15 := i3 & i6 & i7 +
- i6 & rf16 +
- i3 & /rf16 +
- i7 +
- /i4 +
- i6 & i7 +
- i4 & i7 +
- /i2 & /i7
-rf15.oe = OE
-
-/rf16 := /i3 & /rf17 +
- /i4 +
- /i3 & /i3 +
- /i3 & i4 +
- /i7 & rf17 +
- /i7 +
- i4 +
- i2 & i3
-rf16.oe = OE
-
-/rf17 := i2 & i5 & i6 & /i7 +
- i2 & /o18 +
- i5 +
- i6 +
- /i7 & o18 +
- i2 & /i7 +
- i5 & i6 +
- /i3
-rf17.oe = OE
-
-/o18 = /i2 & i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i3 +
- /i2 & /i7 +
- /i3 +
- i5 & i6 & /i7 +
- i7
-o18.oe = vcc
-
-/o19 = i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i5 +
- i6 +
- i7 +
- /i4 +
- /i7
-o19.oe = vcc
diff --git a/src/regtests/jedutil/eqns/pal16r6/pal16r6.eqn b/src/regtests/jedutil/eqns/pal16r6/pal16r6.eqn
index 42f444f5e24..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal16r6/pal16r6.eqn
+++ b/src/regtests/jedutil/eqns/pal16r6/pal16r6.eqn
@@ -1,84 +0,0 @@
-chip pal16r6 PAL16R6
-
-CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10
-/OE=11 o12=12 rf13=13 rf14=14 rf15=15 rf16=16 rf17=17 rf18=18 o19=19 VCC=20
-
-equations
-
-/o12 = /i2 & /i3 +
- i4 & rf13 +
- i3 +
- /i6 +
- i8 +
- /i9 +
- i7 & /rf13
-o12.oe = rf14
-
-/rf13 := /rf14 +
- /i9 +
- i8 +
- /i7 +
- /i6 & /rf14 +
- i5 & rf14 +
- i4 +
- /i2
-rf13.oe = OE
-
-/rf14 := /rf15 +
- /i8 +
- i8 +
- /i2 & /rf15 +
- /i2 +
- i2 & /i8 & rf15 +
- /i4 +
- i3
-rf14.oe = OE
-
-/rf15 := i3 & i6 & i7 +
- i6 & rf16 +
- i3 & /rf16 +
- i7 +
- /i4 +
- i6 & i7 +
- i4 & i7 +
- /i2 & /i7
-rf15.oe = OE
-
-/rf16 := /i3 & /rf17 +
- /i4 +
- /i3 +
- /i3 & i4 +
- /i7 & rf17 +
- /i7 +
- i4 +
- i2 & i3
-rf16.oe = OE
-
-/rf17 := i2 & i5 & i6 & /i7 +
- i2 & /rf18 +
- i5 +
- i6 +
- /i7 & rf18 +
- i2 & /i7 +
- i5 & i6 +
- /i3
-rf17.oe = OE
-
-/rf18 := /i2 & i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i3 +
- /i2 & /i7 +
- /i3 +
- i5 & i6 & /i7 +
- i7 +
- i4
-rf18.oe = OE
-
-/o19 = i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i5 +
- i6 +
- i7 +
- /i4 +
- /i7
-o19.oe = vcc
diff --git a/src/regtests/jedutil/eqns/pal16r8/pal16r8.eqn b/src/regtests/jedutil/eqns/pal16r8/pal16r8.eqn
index 5987e81c2dc..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal16r8/pal16r8.eqn
+++ b/src/regtests/jedutil/eqns/pal16r8/pal16r8.eqn
@@ -1,86 +0,0 @@
-chip pal16r8 PAL16R8
-
-CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10
-/OE=11 rf12=12 rf13=13 rf14=14 rf15=15 rf16=16 rf17=17 rf18=18 rf19=19 VCC=20
-
-equations
-
-/rf12 := /i2 & /i3 +
- i4 & rf13 +
- i3 +
- /i6 +
- i8 +
- /i9 +
- i7 & /rf13 +
- i5
-rf12.oe = OE
-
-/rf13 := /rf14 +
- /i9 +
- i8 +
- /i7 +
- /i6 & rf14 +
- i5 +
- i4 +
- /i3
-rf13.oe = OE
-
-/rf14 := /rf15 +
- /i8 +
- i8 +
- /i2 & /rf15 +
- /i2 +
- i2 & /i8 & rf15 +
- /i4 +
- i3
-rf14.oe = OE
-
-/rf15 := i3 & i6 & i7 +
- i6 & rf16 +
- i3 & /rf16 +
- i7 +
- /i4 +
- i6 & i7 +
- i4 & i7 +
- /i2 & /i7
-rf15.oe = OE
-
-/rf16 := /i3 & /rf17 +
- /i4 +
- /i3 +
- /i3 & i4 +
- /i7 & rf17 +
- /i7 +
- i4 +
- i2 & i3
-rf16.oe = OE
-
-/rf17 := i2 & i5 & i6 & /i7 +
- i2 & /rf18 +
- i5 +
- i6 +
- /i7 & rf18 +
- i2 & /i7 +
- i5 & i6 +
- /i3
-rf17.oe = OE
-
-/rf18 := /i2 & i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i3 & rf19 +
- /i2 & /i7 +
- /i3 & /rf19 +
- i5 & i6 & /i7 +
- i7 +
- /i4
-rf18.oe = OE
-
-/rf19 := i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i5 & rf12 +
- i6 +
- i7 +
- /i4 & /rf12 +
- /i7 +
- i2
-rf19.oe = OE
diff --git a/src/regtests/jedutil/eqns/pal20l10/pal20l10.eqn b/src/regtests/jedutil/eqns/pal20l10/pal20l10.eqn
index d6639bdf9f4..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal20l10/pal20l10.eqn
+++ b/src/regtests/jedutil/eqns/pal20l10/pal20l10.eqn
@@ -1,56 +0,0 @@
-chip 2000 PAL20L10
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
-i13=13 o14=14 o15=15 o16=16 o17=17 o18=18 o19=19 o20=20 o21=21 o22=22 o23=23 VCC=24
-
-equations
-
-/o14 = /i11 +
- i10 +
- i9 & /o15
-o14.oe = o15
-
-/o15 = /i1 & i2 & /i3 & i4 & i11 +
- /i1 & i2 & /i3 & /i5 & /i13 & o16 +
- /i1 & i2 & /i3 & i6
-o15.oe = /o16
-
-/o16 = i1 & /i2 & /o17 +
- i3 & /i4 +
- i3 & i9 & o17
-o16.oe = vcc
-
-/o17 = /o18 +
- i10 & o18 +
- i9
-o17.oe = i4 & i5
-
-/o18 = i1 & /i2 & i3 & /i4 & /i8 +
- /i6 & i7 & i8 & i9 & i10 & /o19 +
- i1 & i2 & i3 & /i4 & /i5 & o19
-o18.oe = i1 & i10
-
-/o19 = i11 & o20 +
- i2 & /i10 +
- i9 & i11
-o19.oe = i8 & /o20
-
-/o20 = o21 +
- /i6 +
- /i7 & /o21
-o20.oe = vcc
-
-/o21 = i1 & i8 +
- /i4 & /o22 +
- o22
-o21.oe = i5 & i6
-
-/o22 = i1 & /i8 +
- /i8 +
- i1
-o22.oe = i3 & /i7
-
-/o23 = i7 +
- i11 +
- /i13
-o23.oe = vcc
diff --git a/src/regtests/jedutil/eqns/pal20l8/pal20l8.eqn b/src/regtests/jedutil/eqns/pal20l8/pal20l8.eqn
index f7280b6150f..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal20l8/pal20l8.eqn
+++ b/src/regtests/jedutil/eqns/pal20l8/pal20l8.eqn
@@ -1,78 +0,0 @@
-chip 2000 PAL20L8
-
-i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
-i13=13 i14=14 o15=15 o16=16 o17=17 o18=18 o19=19 o20=20 o21=21 o22=22 i23=23 VCC=24
-
-equations
-
-/o15 = /i1 & i2 & /i3 & i4 & i11 +
- /i1 & i2 & /i3 & /i5 & /i13 +
- /i1 & i2 & /i3 & i6 & i14 +
- /i1 & i2 & /i3 & /i7 & /i23 +
- /i1 & i2 & /i3 & i8 & /i11 +
- /i1 & i2 & /i3 & /i9 & i13 +
- /o16
-o15.oe = o16
-
-/o16 = i1 & /i2 & /o17 +
- i3 & /i4 +
- i5 & /i6 +
- i7 & /i8 +
- i3 & i9 & o17 +
- i1 & /i2 & i3 & /i4 & i5 & /i6 & i7 & /i8 & /i9 +
- /i8 & /i9
-o16.oe = vcc
-
-/o17 = /i23 & /o18 +
- i10 & o18 +
- i9 +
- i8 +
- /i7 +
- /i6 +
- i5
-o17.oe = i4 & i5
-
-/o18 = i1 & /i2 & i3 & /i4 & /i8 & i23 +
- i1 & i2 & i3 & /i4 & /i5 +
- /i6 & i7 & i8 & i9 & i10 & /o19 +
- i11 & i13 & i14 & i23 +
- /i6 & i7 & i8 & i9 & i10 +
- i3 & i13 & i14 & i23 +
- i1 & i2 & i3 & /i4 & /i5 & o19
-o18.oe = i1 & i10 & i23
-
-/o19 = i9 & /i10 & i11 & i23 +
- i9 +
- /i10 +
- i11 & o20 +
- i23 +
- i2 & /i10 & i23 +
- i9 & i11
-o19.oe = i8 & /o20
-
-/o20 = o21 +
- /i2 +
- /i3 +
- /i4 +
- /i5 +
- /i6 +
- /i7 & /o21
-o20.oe = vcc
-
-/o21 = i1 & i8 +
- /i14 +
- i1 & /i5 & i8 +
- i23 +
- i1 & i8 & /i14 +
- i13 +
- i1 & i11
-o21.oe = i5 & i6
-
-/o22 = i1 & /i8 +
- /i8 +
- i1 +
- /i10 +
- /i23 +
- i8 & /i13 +
- /i11
-o22.oe = i3 & /i7
diff --git a/src/regtests/jedutil/eqns/pal20r4/pal20r4.eqn b/src/regtests/jedutil/eqns/pal20r4/pal20r4.eqn
index ace68eae24f..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal20r4/pal20r4.eqn
+++ b/src/regtests/jedutil/eqns/pal20r4/pal20r4.eqn
@@ -1,82 +0,0 @@
-chip pal20r4 PAL20R4
-
-CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
-/OE=13 i14=14 o15=15 o16=16 rf17=17 rf18=18 rf19=19 rf20=20 o21=21 o22=22 i23=23 VCC=24
-
-equations
-
-/o15 = i2 & i6 & i7 +
- i6 & o16 +
- i3 & /o16 +
- i7 +
- /i4 +
- i6 & i7 +
- i4 & i7
-o15.oe = /i23
-
-/o16 = /i3 & /rf17 +
- /i4 +
- /i3 +
- /i3 & i4 +
- /i7 & rf17 +
- /i7 +
- i4
-o16.oe = i23
-
-/rf17 := /i2 +
- /rf18 +
- i5 +
- i6 +
- rf18 +
- i4 +
- /i10 +
- /i23
-rf17.oe = OE
-
-/rf18 := /i2 & i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i3 & rf19 +
- /i2 & /i7 +
- /i3 & /rf19 +
- i5 & i6 & /i7 +
- i7 +
- /i11
-rf18.oe = OE
-
-/rf19 := i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i5 & rf20 +
- i6 +
- i7 +
- /i4 & /rf20 +
- /i7 +
- i10
-rf19.oe = OE
-
-/rf20 := i10 & rf17 +
- /i11 +
- i4 & /rf17 +
- i2 +
- /i6 & /i7 +
- i8 +
- /i9 +
- o22
-rf20.oe = OE
-
-/o21 = /i8 +
- /i2 & rf17 +
- i11 +
- /i10 +
- o15 +
- /i14 +
- /i3
-o21.oe = i8 & i9 & /o22
-
-/o22 = i14 +
- /o15 +
- i3 & /o21 +
- i7 +
- /i8 & o21 +
- i10 +
- /i9
-o22.oe = i14 & /o15 \ No newline at end of file
diff --git a/src/regtests/jedutil/eqns/pal20r6/pal20r6.eqn b/src/regtests/jedutil/eqns/pal20r6/pal20r6.eqn
index dca4b545ee4..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal20r6/pal20r6.eqn
+++ b/src/regtests/jedutil/eqns/pal20r6/pal20r6.eqn
@@ -1,84 +0,0 @@
-chip pal20r6 PAL20R6
-
-CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
-/OE=13 i14=14 o15=15 rf16=16 rf17=17 rf18=18 rf19=19 rf20=20 rf21=21 o22=22 i23=23 VCC=24
-
-equations
-
-/o15 = i2 & i6 & i7 +
- i6 & rf16 +
- i3 & /rf16 +
- i7 +
- /i4 +
- i6 & i7 +
- i4 & i7
-o15.oe = /i23
-
-/rf16 := /i3 & /rf17 +
- /i4 & /i23 +
- /i3 +
- /i3 & i4 +
- /i7 & rf17 +
- /i7 +
- i4 +
- i23
-rf16.oe = OE
-
-/rf17 := /i2 +
- /rf18 +
- i5 +
- i6 +
- rf18 +
- i4 +
- /i10 +
- /i23
-rf17.oe = OE
-
-/rf18 := /i2 & i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i3 & rf19 +
- /i2 & /i7 +
- /i3 & /rf19 +
- i5 & i6 & /i7 +
- i7 +
- /i11
-rf18.oe = OE
-
-/rf19 := i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i5 & rf20 +
- i6 +
- i7 +
- /i4 & /rf20 +
- /i7 +
- i10
-rf19.oe = OE
-
-/rf20 := i10 & rf17 +
- /i11 +
- i4 & /rf17 +
- i2 +
- /i6 & /i7 +
- i8 +
- /i9 +
- o22
-rf20.oe = OE
-
-/rf21 := /i8 +
- /i2 & rf17 +
- i11 +
- /i10 +
- o15 +
- /i14 & /o22 +
- /i3 +
- /i5
-rf21.oe = OE
-
-/o22 = i14 +
- /o15 +
- i3 & /rf21 +
- i7 +
- /i8 & rf21 +
- i10 +
- /i9
-o22.oe = i14 & /o15 \ No newline at end of file
diff --git a/src/regtests/jedutil/eqns/pal20r8/pal20r8.eqn b/src/regtests/jedutil/eqns/pal20r8/pal20r8.eqn
index c777a21d495..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/pal20r8/pal20r8.eqn
+++ b/src/regtests/jedutil/eqns/pal20r8/pal20r8.eqn
@@ -1,86 +0,0 @@
-chip pal20r8 PAL20R8
-
-CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 i10=10 i11=11 GND=12
-/OE=13 i14=14 rf15=15 rf16=16 rf17=17 rf18=18 rf19=19 rf20=20 rf21=21 rf22=22 i23=23 VCC=24
-
-equations
-
-/rf15 := i2 & i6 & i7 +
- i6 & rf16 +
- i3 & /rf16 +
- i7 +
- /i4 +
- i6 & i7 +
- i4 & i7 +
- /i23
-rf15.oe = OE
-
-/rf16 := /i3 & /rf17 +
- /i4 +
- /i3 +
- /i3 & i4 +
- /i7 & rf17 +
- /i7 +
- i4 +
- i23
-rf16.oe = OE
-
-/rf17 := /i2 +
- /rf18 +
- i5 +
- i6 +
- rf18 +
- i4 +
- /i10 +
- /i23
-rf17.oe = OE
-
-/rf18 := /i2 & i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i3 & rf19 +
- /i2 & /i7 +
- /i3 & /rf19 +
- i5 & i6 & /i7 +
- i7 +
- /i11
-rf18.oe = OE
-
-/rf19 := i5 & i6 & /i7 +
- i3 & i6 & i7 +
- i5 & rf20 +
- i6 +
- i7 +
- /i4 & /rf20 +
- /i7 +
- i10
-rf19.oe = OE
-
-/rf20 := i10 & rf17 +
- /i11 +
- i4 & /rf17 +
- i2 +
- /i6 & /i7 +
- i8 +
- /i9 +
- rf22
-rf20.oe = OE
-
-/rf21 := /i8 +
- /i2 & rf17 +
- i11 +
- /i10 +
- rf15 +
- /i14 +
- /i3 +
- i8 & i9 & /rf22
-rf21.oe = OE
-
-/rf22 := i14 +
- /rf15 +
- i3 & /rf21 +
- i7 +
- /i8 & rf21 +
- i10 +
- /i9 +
- i14 & /rf15
-rf22.oe = OE \ No newline at end of file
diff --git a/src/regtests/jedutil/eqns/readme.txt b/src/regtests/jedutil/eqns/readme.txt
index 94dcdf6ab46..e69de29bb2d 100644
--- a/src/regtests/jedutil/eqns/readme.txt
+++ b/src/regtests/jedutil/eqns/readme.txt
@@ -1 +0,0 @@
-This files are for use with the utility eqn2jed which is a tool included with Opal Jr. The tools takes this equation files and automatically creates a jed file.
diff --git a/src/regtests/jedutil/jeds/18cv8/18cv8_combinatorial_feedback.jed b/src/regtests/jedutil/jeds/18cv8/18cv8_combinatorial_feedback.jed
new file mode 100644
index 00000000000..cc0f33be6ac
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/18cv8_combinatorial_feedback.jed
@@ -0,0 +1,104 @@
+JEDEC PLD file 18CV8_~1.JED created on Sun 11-25-2012 21:36:51
+Place Compile Version: 3.0.0
+PEEL18CV8 Combinatorial Feedback Test Data
+*QP20
+*QF2696
+*F0
+*
+N Output Pin 19*
+L0000 1111 1111 1110 1110 1101 1111 1111 1110 1111 *
+L0036 1110 1111 1111 1111 1111 1101 1111 1111 1011 *
+L0072 1111 1111 1111 1111 1111 1110 1011 0101 1111 *
+L0108 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0144 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0180 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0216 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0252 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 18*
+L0288 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0324 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0360 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0396 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0432 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0468 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0504 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0540 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 17*
+L0576 1111 1101 1111 1111 1111 1111 1111 1111 1111 *
+L0612 1111 1110 1111 1111 1101 1101 1111 1101 1111 *
+L0648 1111 1111 1111 1111 1111 1110 1111 1110 1111 *
+L0684 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0720 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0756 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0792 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0828 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 16*
+L0864 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0900 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0936 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0972 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1008 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1044 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1080 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1116 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 15*
+L1152 1111 1110 1111 1101 1111 1111 1111 1111 1111 *
+L1188 1111 1101 1111 1111 1111 1111 1111 1111 1111 *
+L1224 1101 1111 1111 1110 1111 1111 1111 1110 1110 *
+L1260 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1296 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1332 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1368 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1404 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 14*
+L1440 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1476 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1512 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1548 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1584 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1620 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1656 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1692 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 13*
+L1728 1111 1111 1011 1011 1011 0111 1111 1111 1111 *
+L1764 0111 1010 1111 1111 1111 1111 1111 1111 1111 *
+L1800 1111 1101 1111 1110 1111 1111 1111 1111 1111 *
+L1836 1111 1111 1111 1111 1111 1101 1101 1111 1111 *
+L1872 1111 1111 1111 1111 1111 1110 1111 1111 1101 *
+L1908 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1944 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1980 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 12*
+L2016 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2052 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2088 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2124 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2160 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2196 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2232 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2268 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Enable 19,18,...12*
+L2304 1111 1111 1111 1101 1111 1111 1111 1111 1111 *
+L2340 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1111 1111 1111 1111 1101 1111 *
+L2484 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 1111 1111 1111 1101 1111 1111 1111 1111 1111 *
+L2556 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12*
+L2592 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2628 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2664 1010 1011 0010 1011 0110 0011 1110 0011 *
+
+C2709*
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/18cv8_register_feedback.jed b/src/regtests/jedutil/jeds/18cv8/18cv8_register_feedback.jed
new file mode 100644
index 00000000000..db960d48723
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/18cv8_register_feedback.jed
@@ -0,0 +1,104 @@
+JEDEC PLD file 18CV8_~1.JED created on Mon 11-26-2012 22:21:12
+Place Compile Version: 3.0.0
+PEEL18CV8 Register Feedback Test Data
+*QP20
+*QF2696
+*F0
+*
+N Output Pin 19*
+L0000 1111 1111 1111 1101 1111 1111 1111 1101 1111 *
+L0036 1111 1111 1111 1110 1111 1110 1111 0111 1111 *
+L0072 0111 0111 1111 1111 1111 1101 1111 1111 1111 *
+L0108 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0144 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0180 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0216 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0252 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 18*
+L0288 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0324 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0360 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0396 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0432 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0468 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0504 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0540 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 17*
+L0576 1111 1111 1111 1111 1111 1111 1111 1101 1111 *
+L0612 0111 1111 1111 1111 1101 1101 1111 1110 1111 *
+L0648 1111 1101 1111 1111 1111 1110 1111 1111 1111 *
+L0684 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0720 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0756 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0792 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0828 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 16*
+L0864 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0900 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0936 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0972 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1008 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1044 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1080 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1116 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 15*
+L1152 1111 1111 1111 1101 1111 1111 1111 1111 1111 *
+L1188 1111 1101 1111 1111 1111 1111 1111 1110 1111 *
+L1224 1111 1110 1111 1110 1111 1111 1111 1101 1111 *
+L1260 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1296 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1332 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1368 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1404 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 14*
+L1440 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1476 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1512 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1548 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1584 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1620 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1656 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1692 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 13*
+L1728 1111 1111 0111 1110 1111 1111 1111 1111 1111 *
+L1764 1111 1111 1111 1111 1111 1110 1111 1111 1110 *
+L1800 1111 1111 1111 1101 1111 1101 1111 1111 1111 *
+L1836 1111 1101 1111 1111 1111 1111 0111 1111 1111 *
+L1872 1111 1110 1111 1111 1111 1111 1111 1111 1011 *
+L1908 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1944 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1980 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 12*
+L2016 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2052 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2088 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2124 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2160 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2196 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2232 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2268 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Enable 19,18,...12*
+L2304 1111 1111 1111 1111 1111 1111 1111 1110 1111 *
+L2340 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2376 1111 1110 1111 1111 1111 1111 1111 1111 1111 *
+L2412 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1110 1111 1111 1111 1111 1111 *
+L2484 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2556 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12*
+L2592 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2628 0000 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2664 0100 1011 1000 1011 1100 0011 0000 0011 *
+
+C2808*
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal10h8-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal10h8-to-peel18cv8.jed
new file mode 100644
index 00000000000..e62b251efcf
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal10h8-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL10H8 Mon 10-8-2012 22:35:56
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0111 0111 0111 0111 0111 0111 0111 1011 1111 *
+L0036 1101 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 18 *
+L0288 0111 0111 0111 0111 0111 0111 1011 0111 1111 *
+L0324 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 17 *
+L0576 0111 0111 0111 0111 0111 1011 0111 0111 1111 *
+L0612 1110 1111 1111 1111 1111 1111 1111 1111 0111 *
+L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 16 *
+L0864 0111 0111 0111 0111 1011 0111 0111 0111 1111 *
+L0900 1110 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0936 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0972 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 15 *
+L1152 0111 0111 0111 1011 0111 0111 0111 0111 1111 *
+L1188 1110 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1224 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1260 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 14 *
+L1440 0111 0111 1011 0111 0111 0111 0111 0111 1111 *
+L1476 1110 1111 1111 1111 1111 1111 1111 1111 0111 *
+L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 13 *
+L1728 0111 1011 0111 0111 0111 0111 0111 0111 1111 *
+L1764 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 12 *
+L2016 1011 0111 0111 0111 0111 0111 0111 0111 1111 *
+L2052 1101 1111 1111 1111 1111 1111 1111 1111 0111 *
+L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Enable 19,18,...12 *
+L2304 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2340 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2556 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 0011 0011 0011 0011 0011 0011 0011 0011 *
+
+C68B0 *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal12h6-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal12h6-to-peel18cv8.jed
new file mode 100644
index 00000000000..5231d4d4085
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal12h6-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL12H6 Mon 10-8-2012 22:39:42
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 18 *
+L0288 0111 0111 0111 0111 0111 1011 0111 0111 1111 *
+L0324 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0360 1111 1101 1111 1111 1111 1111 1111 1111 1111 *
+L0396 1111 1111 1111 1111 1111 1111 1111 1111 1110 *
+L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 17 *
+L0576 0111 0111 0111 0111 1011 0111 0111 0111 1111 *
+L0612 1110 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 16 *
+L0864 0111 0111 0111 0111 0111 0111 1011 0111 1111 *
+L0900 1110 1111 1111 1111 1111 1111 1111 1111 0111 *
+L0936 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0972 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 15 *
+L1152 0111 0111 0111 1011 0111 0111 0111 0111 1111 *
+L1188 1110 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1224 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1260 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 14 *
+L1440 0111 1011 0111 0111 0111 0111 0111 0111 1111 *
+L1476 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 13 *
+L1728 1011 0111 0111 0111 0111 0111 0111 0111 1111 *
+L1764 1101 1111 1111 1111 1111 1111 1111 1111 0111 *
+L1800 1111 1110 1111 1111 1111 1111 1111 1111 1111 *
+L1836 1111 1111 1111 1111 1111 1111 1111 1111 1101 *
+L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 12 *
+L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Enable 19,18,...12 *
+L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2340 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 0011 0011 0011 0011 0011 0011 0011 0011 *
+
+C5FA2 *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal12l6-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal12l6-to-peel18cv8.jed
new file mode 100644
index 00000000000..e390f1ed250
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal12l6-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL12L6 Mon 10-8-2012 22:40:14
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 18 *
+L0288 0111 0111 0111 0111 0111 1011 0111 0111 1111 *
+L0324 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0360 1111 1101 1111 1111 1111 1111 1111 1111 1111 *
+L0396 1111 1111 1111 1111 1111 1111 1111 1111 1110 *
+L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 17 *
+L0576 0111 0111 0111 0111 1011 0111 0111 0111 1111 *
+L0612 1110 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 16 *
+L0864 0111 0111 0111 1011 0111 0111 0111 0111 1111 *
+L0900 1110 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0936 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0972 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 15 *
+L1152 0111 0111 1011 0111 0111 0111 0111 0111 1111 *
+L1188 1101 1111 1111 1111 1111 1111 1111 1111 0111 *
+L1224 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1260 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 14 *
+L1440 0111 1011 0111 0111 0111 0111 0111 0111 1111 *
+L1476 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 13 *
+L1728 1011 0111 0111 0111 0111 0111 0111 0111 1111 *
+L1764 1101 1111 1111 1111 1111 1111 1111 1111 0111 *
+L1800 1111 1110 1111 1111 1111 1111 1111 1111 1111 *
+L1836 1111 1111 1111 1111 1111 1111 1111 1111 1101 *
+L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 12 *
+L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Enable 19,18,...12 *
+L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2340 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 1011 1011 1011 1011 1011 1011 1011 1011 *
+
+C6026 *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal14h4-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal14h4-to-peel18cv8.jed
new file mode 100644
index 00000000000..eed675d61d8
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal14h4-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL14H4 Mon 10-8-2012 22:40:43
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 18 *
+L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0324 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 17 *
+L0576 0111 0111 0111 1011 0111 0111 0111 0111 1111 *
+L0612 1101 1111 1111 1111 1111 1111 1111 1111 0111 *
+L0648 1111 1111 1111 1111 1111 1111 1111 1101 1110 *
+L0684 1111 1101 1101 1111 1111 1111 1111 1111 1111 *
+L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 16 *
+L0864 0111 0111 1011 0111 0111 0111 0111 0111 1111 *
+L0900 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0936 1111 1111 1111 1111 1111 1111 1111 1110 1101 *
+L0972 1111 1110 1110 1111 1111 1111 1111 1111 1111 *
+L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 15 *
+L1152 0111 1011 0111 0111 0111 0111 0111 0111 1111 *
+L1188 1110 1111 1111 1111 1111 1111 1111 1111 0111 *
+L1224 1111 1111 1111 1111 1111 1111 1111 1101 1101 *
+L1260 1111 1101 1110 1111 1111 1111 1111 1111 1111 *
+L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 14 *
+L1440 1011 0111 0111 0111 0111 0111 0111 0111 1111 *
+L1476 1101 1111 1111 1111 1111 1111 1111 1111 0111 *
+L1512 1111 1111 1111 1111 1111 1111 1111 1110 1110 *
+L1548 1111 1110 1101 1111 1111 1111 1111 1111 1111 *
+L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 13 *
+L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1764 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 12 *
+L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Enable 19,18,...12 *
+L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2340 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 0011 0011 0011 0011 0011 0011 0011 0011 *
+
+C56E4 *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal14l4-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal14l4-to-peel18cv8.jed
new file mode 100644
index 00000000000..4035a7c74ee
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal14l4-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL14L4 Mon 10-8-2012 22:41:22
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 18 *
+L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0324 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 17 *
+L0576 0111 0111 0111 0111 0111 1011 0111 0111 1111 *
+L0612 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0648 1111 1111 1111 1111 1111 1111 1111 1110 1110 *
+L0684 1111 1110 1110 1111 1111 1111 1111 1111 1111 *
+L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 16 *
+L0864 0111 0111 0111 0111 1011 0111 0111 0111 1111 *
+L0900 1110 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0936 1111 1111 1111 1111 1111 1111 1111 1101 1101 *
+L0972 1111 1110 1101 1111 1111 1111 1111 1111 1111 *
+L1008 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1044 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1080 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1116 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 15 *
+L1152 0111 0111 0111 1011 0111 0111 0111 0111 1111 *
+L1188 1110 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1224 1111 1111 1111 1111 1111 1111 1111 1101 1110 *
+L1260 1111 1101 1110 1111 1111 1111 1111 1111 1111 *
+L1296 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1332 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1368 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1404 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 14 *
+L1440 0111 1011 0111 0111 0111 0111 0111 0111 1111 *
+L1476 1101 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1512 1111 1111 1111 1111 1111 1111 1111 1110 1101 *
+L1548 1111 1101 1101 1111 1111 1111 1111 1111 1111 *
+L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 13 *
+L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1764 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 12 *
+L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Enable 19,18,...12 *
+L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2340 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2376 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 1011 1011 1011 1011 1011 1011 1011 1011 *
+
+C56A9 *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal16h2-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal16h2-to-peel18cv8.jed
new file mode 100644
index 00000000000..77254be3ca1
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal16h2-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL16H2 Mon 10-8-2012 22:42:12
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 18 *
+L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0324 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 17 *
+L0576 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0612 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 16 *
+L0864 0111 0111 1011 0111 1011 0111 0111 0111 1111 *
+L0900 1111 1111 1111 1111 1111 1111 1111 1111 1011 *
+L0936 1101 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0972 1111 1111 1111 1111 1111 1111 1111 1111 1110 *
+L1008 1111 1111 1111 1111 1111 1111 1111 1101 1111 *
+L1044 1111 1111 1111 1111 1111 1111 1110 1111 1111 *
+L1080 1111 1111 1111 1101 1111 1111 1111 1111 1111 *
+L1116 1111 1101 1110 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 15 *
+L1152 0111 0111 0111 1011 0111 1011 0111 0111 1111 *
+L1188 1111 1111 1111 1111 1111 1111 1111 1111 0111 *
+L1224 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1260 1111 1111 1111 1111 1111 1111 1111 1111 1101 *
+L1296 1111 1111 1111 1111 1111 1111 1111 1110 1111 *
+L1332 1111 1111 1111 1111 1111 1111 1101 1111 1111 *
+L1368 1111 1111 1111 1110 1111 1111 1111 1111 1111 *
+L1404 1111 1110 1101 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 14 *
+L1440 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1476 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 13 *
+L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1764 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 12 *
+L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Enable 19,18,...12 *
+L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2340 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2376 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2520 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 0011 0011 0011 0011 0011 0011 0011 0011 *
+
+C4F2D *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal16l2-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal16l2-to-peel18cv8.jed
new file mode 100644
index 00000000000..e4aba1f1378
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal16l2-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL16L2 Mon 10-8-2012 22:42:40
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0036 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0072 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0108 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0144 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0180 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0216 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0252 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 18 *
+L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0324 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0360 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0396 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0432 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0468 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0504 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0540 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 17 *
+L0576 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0612 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0648 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0684 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0720 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0756 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0792 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0828 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 16 *
+L0864 0111 0111 0111 0111 0111 0111 1011 0111 1111 *
+L0900 1111 1111 1111 1111 1111 1111 1111 1111 0111 *
+L0936 1101 1111 1111 1111 1111 1111 1111 1111 1111 *
+L0972 1111 1111 1111 1111 1111 1111 1111 1111 1101 *
+L1008 1111 1111 1111 1111 1111 1111 1111 1110 1111 *
+L1044 1111 1111 1111 1111 1111 1111 1110 1111 1111 *
+L1080 1111 1111 1111 1110 1111 1111 1111 1111 1111 *
+L1116 1111 1110 1110 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 15 *
+L1152 0111 0111 0111 1011 0111 0111 0111 0111 1111 *
+L1188 1111 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1224 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L1260 1111 1111 1111 1111 1111 1111 1111 1111 1110 *
+L1296 1111 1111 1111 1111 1111 1111 1111 1101 1111 *
+L1332 1111 1111 1111 1111 1111 1111 1101 1111 1111 *
+L1368 1111 1111 1111 1101 1111 1111 1111 1111 1111 *
+L1404 1111 1101 1101 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 14 *
+L1440 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1476 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1512 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1548 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1584 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1620 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1656 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1692 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 13 *
+L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1764 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1800 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1836 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1872 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1908 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1944 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1980 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Pin 12 *
+L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2052 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2088 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2124 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2160 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2196 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2232 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2268 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Output Enable 19,18,...12 *
+L2304 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2340 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2376 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2412 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2520 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2556 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 1011 1011 1011 1011 1011 1011 1011 1011 *
+
+C4F82 *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal16r4-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal16r4-to-peel18cv8.jed
new file mode 100644
index 00000000000..7f5684e02e7
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal16r4-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL16R4 Mon 10-8-2012 22:43:51
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0036 1111 1111 1111 1111 0111 0111 1011 1111 1111 *
+L0072 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L0108 1111 1111 1111 1111 0111 1111 1111 1111 1111 *
+L0144 1111 1111 1111 1111 1111 0111 1111 1111 1111 *
+L0180 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+L0216 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L0252 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+
+N Output Pin 18 *
+L0288 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0324 1111 1011 1111 1111 0111 0111 1011 1111 1111 *
+L0360 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L0396 1111 1111 0111 1111 1111 1111 1111 1111 1111 *
+L0432 1111 1011 1111 1111 1111 1111 1011 1111 1111 *
+L0468 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+L0504 1111 1111 1111 1111 0111 0111 1011 1111 1111 *
+L0540 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+
+N Output Pin 17 *
+L0576 1111 0111 1111 1111 0111 0111 1011 1111 1111 *
+L0612 1111 0111 1110 1111 1111 1111 1111 1111 1111 *
+L0648 1111 1111 1111 1111 0111 1111 1111 1111 1111 *
+L0684 1111 1111 1111 1111 1111 0111 1111 1111 1111 *
+L0720 1111 1111 1101 1111 1111 1111 1011 1111 1111 *
+L0756 1111 0111 1111 1111 1111 1111 1011 1111 1111 *
+L0792 1111 1111 1111 1111 0111 0111 1111 1111 1111 *
+L0828 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 16 *
+L0864 1111 1111 1011 1101 1111 1111 1111 1111 1111 *
+L0900 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L0936 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+L0972 1111 1111 1011 0111 1111 1111 1111 1111 1111 *
+L1008 1111 1111 1111 1110 1111 1111 1011 1111 1111 *
+L1044 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+L1080 1111 1111 1111 0111 1111 1111 1111 1111 1111 *
+L1116 1111 0111 0111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 15 *
+L1152 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L1188 1111 1111 1111 1111 1110 0111 1111 1111 1111 *
+L1224 1111 1111 0111 1111 1101 1111 1111 1111 1111 *
+L1260 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+L1296 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L1332 1111 1111 1111 1111 1111 0111 0111 1111 1111 *
+L1368 1111 1111 1111 0111 1111 1111 0111 1111 1111 *
+L1404 1111 1011 1111 1111 1111 1111 1011 1111 1111 *
+
+N Output Pin 14 *
+L1440 1111 1111 1111 1111 1111 1101 1111 1111 1111 *
+L1476 1111 1111 1111 1111 1111 1111 1111 1011 1111 *
+L1512 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L1548 1111 1011 1111 1111 1111 1101 1111 1111 1111 *
+L1584 1111 1011 1111 1111 1111 1111 1111 1111 1111 *
+L1620 1111 0111 1111 1111 1111 1110 1111 1011 1111 *
+L1656 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L1692 1111 1111 0111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 13 *
+L1728 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L1764 1111 1111 1111 1111 1111 1111 1101 1111 1111 *
+L1800 1111 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1836 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L1872 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+L1908 1111 1111 1111 1111 1111 1011 1101 1111 1111 *
+L1944 1111 1111 1111 1111 0111 1111 1111 1111 1111 *
+L1980 1111 1111 1111 0111 1111 1111 1111 1111 1111 *
+
+N Output Pin 12 *
+L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2052 1111 1011 1011 1111 1111 1111 1111 1111 1111 *
+L2088 1111 1111 1111 0111 1111 1111 1111 1101 1111 *
+L2124 1111 1111 0111 1111 1111 1111 1111 1111 1111 *
+L2160 1111 1111 1111 1111 1111 1011 1111 1111 1111 *
+L2196 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L2232 1111 1111 1111 1111 1111 1111 1111 1111 1011 *
+L2268 1111 1111 1111 1111 1111 1111 0111 1110 1111 *
+
+N Output Enable 19,18,...12 *
+L2304 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2340 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2376 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 1111 0111 1111 1111 1111 1111 1110 1111 1111 *
+L2556 1111 1111 1111 1111 1111 1111 1110 1111 1111 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 1011 1011 1100 1100 1100 1100 1011 1011 *
+
+C2C6E *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal16r6-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal16r6-to-peel18cv8.jed
new file mode 100644
index 00000000000..8f1e9064d69
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal16r6-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL16R6 Mon 10-8-2012 22:44:19
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L0036 1111 1111 1111 1111 0111 0111 1011 1111 1111 *
+L0072 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L0108 1111 1111 1111 1111 0111 1111 1111 1111 1111 *
+L0144 1111 1111 1111 1111 1111 0111 1111 1111 1111 *
+L0180 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+L0216 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L0252 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+
+N Output Pin 18 *
+L0288 1111 1011 1111 1111 0111 0111 1011 1111 1111 *
+L0324 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L0360 1111 1111 0111 1111 1111 1111 1111 1111 1111 *
+L0396 1111 1011 1111 1111 1111 1111 1011 1111 1111 *
+L0432 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+L0468 1111 1111 1111 1111 0111 0111 1011 1111 1111 *
+L0504 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+L0540 1111 1111 1111 0111 1111 1111 1111 1111 1111 *
+
+N Output Pin 17 *
+L0576 1111 0111 1111 1111 0111 0111 1011 1111 1111 *
+L0612 1111 0111 1101 1111 1111 1111 1111 1111 1111 *
+L0648 1111 1111 1111 1111 0111 1111 1111 1111 1111 *
+L0684 1111 1111 1111 1111 1111 0111 1111 1111 1111 *
+L0720 1111 1111 1110 1111 1111 1111 1011 1111 1111 *
+L0756 1111 0111 1111 1111 1111 1111 1011 1111 1111 *
+L0792 1111 1111 1111 1111 0111 0111 1111 1111 1111 *
+L0828 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 16 *
+L0864 1111 1111 1011 1101 1111 1111 1111 1111 1111 *
+L0900 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L0936 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+L0972 1111 1111 1011 0111 1111 1111 1111 1111 1111 *
+L1008 1111 1111 1111 1110 1111 1111 1011 1111 1111 *
+L1044 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+L1080 1111 1111 1111 0111 1111 1111 1111 1111 1111 *
+L1116 1111 0111 0111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 15 *
+L1152 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L1188 1111 1111 1111 1111 1110 0111 1111 1111 1111 *
+L1224 1111 1111 0111 1111 1101 1111 1111 1111 1111 *
+L1260 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+L1296 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L1332 1111 1111 1111 1111 1111 0111 0111 1111 1111 *
+L1368 1111 1111 1111 0111 1111 1111 0111 1111 1111 *
+L1404 1111 1011 1111 1111 1111 1111 1011 1111 1111 *
+
+N Output Pin 14 *
+L1440 1111 1111 1111 1111 1111 1101 1111 1111 1111 *
+L1476 1111 1111 1111 1111 1111 1111 1111 1011 1111 *
+L1512 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L1548 1111 1011 1111 1111 1111 1101 1111 1111 1111 *
+L1584 1111 1011 1111 1111 1111 1111 1111 1111 1111 *
+L1620 1111 0111 1111 1111 1111 1110 1111 1011 1111 *
+L1656 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L1692 1111 1111 0111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 13 *
+L1728 1111 1111 1111 1111 1111 1111 1101 1111 1111 *
+L1764 1111 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1800 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L1836 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+L1872 1111 1111 1111 1111 1111 1011 1101 1111 1111 *
+L1908 1111 1111 1111 1111 0111 1111 1110 1111 1111 *
+L1944 1111 1111 1111 0111 1111 1111 1111 1111 1111 *
+L1980 1111 1011 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 12 *
+L2016 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2052 1111 1011 1011 1111 1111 1111 1111 1111 1111 *
+L2088 1111 1111 1111 0111 1111 1111 1111 1110 1111 *
+L2124 1111 1111 0111 1111 1111 1111 1111 1111 1111 *
+L2160 1111 1111 1111 1111 1111 1011 1111 1111 1111 *
+L2196 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L2232 1111 1111 1111 1111 1111 1111 1111 1111 1011 *
+L2268 1111 1111 1111 1111 1111 1111 0111 1101 1111 *
+
+N Output Enable 19,18,...12 *
+L2304 1111 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2340 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2376 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2556 1111 1111 1111 1111 1111 1111 1110 1111 1111 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 1011 1100 1100 1100 1100 1100 1100 1011 *
+
+C32E7 *
+0000
diff --git a/src/regtests/jedutil/jeds/18cv8/pal16r8-to-peel18cv8.jed b/src/regtests/jedutil/jeds/18cv8/pal16r8-to-peel18cv8.jed
new file mode 100644
index 00000000000..211255912ce
--- /dev/null
+++ b/src/regtests/jedutil/jeds/18cv8/pal16r8-to-peel18cv8.jed
@@ -0,0 +1,104 @@
+
+ JEDEC PEEL file Translated from: PAL16R8 Mon 10-8-2012 22:46:06
+ PA
+*QP20
+*QF2696
+*F0
+ *
+N Output Pin 19 *
+L0000 1111 1111 1111 1111 0111 0111 1011 1111 1111 *
+L0036 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L0072 1111 1111 1111 1111 0111 1111 1111 1111 1110 *
+L0108 1111 1111 1111 1111 1111 0111 1111 1111 1111 *
+L0144 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+L0180 1111 1111 1111 1011 1111 1111 1111 1111 1101 *
+L0216 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+L0252 1111 0111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 18 *
+L0288 1111 1011 1111 1111 0111 0111 1011 1111 1111 *
+L0324 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L0360 1111 1110 0111 1111 1111 1111 1111 1111 1111 *
+L0396 1111 1011 1111 1111 1111 1111 1011 1111 1111 *
+L0432 1111 1101 1011 1111 1111 1111 1111 1111 1111 *
+L0468 1111 1111 1111 1111 0111 0111 1011 1111 1111 *
+L0504 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+L0540 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+
+N Output Pin 17 *
+L0576 1111 0111 1111 1111 0111 0111 1011 1111 1111 *
+L0612 1111 0111 1101 1111 1111 1111 1111 1111 1111 *
+L0648 1111 1111 1111 1111 0111 1111 1111 1111 1111 *
+L0684 1111 1111 1111 1111 1111 0111 1111 1111 1111 *
+L0720 1111 1111 1110 1111 1111 1111 1011 1111 1111 *
+L0756 1111 0111 1111 1111 1111 1111 1011 1111 1111 *
+L0792 1111 1111 1111 1111 0111 0111 1111 1111 1111 *
+L0828 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 16 *
+L0864 1111 1111 1011 1101 1111 1111 1111 1111 1111 *
+L0900 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L0936 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+L0972 1111 1111 1011 0111 1111 1111 1111 1111 1111 *
+L1008 1111 1111 1111 1110 1111 1111 1011 1111 1111 *
+L1044 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+L1080 1111 1111 1111 0111 1111 1111 1111 1111 1111 *
+L1116 1111 0111 0111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 15 *
+L1152 1111 1111 0111 1111 1111 0111 0111 1111 1111 *
+L1188 1111 1111 1111 1111 1110 0111 1111 1111 1111 *
+L1224 1111 1111 0111 1111 1101 1111 1111 1111 1111 *
+L1260 1111 1111 1111 1111 1111 1111 0111 1111 1111 *
+L1296 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L1332 1111 1111 1111 1111 1111 0111 0111 1111 1111 *
+L1368 1111 1111 1111 0111 1111 1111 0111 1111 1111 *
+L1404 1111 1011 1111 1111 1111 1111 1011 1111 1111 *
+
+N Output Pin 14 *
+L1440 1111 1111 1111 1111 1111 1101 1111 1111 1111 *
+L1476 1111 1111 1111 1111 1111 1111 1111 1011 1111 *
+L1512 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L1548 1111 1011 1111 1111 1111 1101 1111 1111 1111 *
+L1584 1111 1011 1111 1111 1111 1111 1111 1111 1111 *
+L1620 1111 0111 1111 1111 1111 1110 1111 1011 1111 *
+L1656 1111 1111 1111 1011 1111 1111 1111 1111 1111 *
+L1692 1111 1111 0111 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 13 *
+L1728 1111 1111 1111 1111 1111 1111 1101 1111 1111 *
+L1764 1111 1111 1111 1111 1111 1111 1111 1111 1011 *
+L1800 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L1836 1111 1111 1111 1111 1111 1111 1011 1111 1111 *
+L1872 1111 1111 1111 1111 1111 1011 1110 1111 1111 *
+L1908 1111 1111 1111 1111 0111 1111 1111 1111 1111 *
+L1944 1111 1111 1111 0111 1111 1111 1111 1111 1111 *
+L1980 1111 1111 1011 1111 1111 1111 1111 1111 1111 *
+
+N Output Pin 12 *
+L2016 1111 1011 1011 1111 1111 1111 1111 1111 1111 *
+L2052 1111 1111 1111 0111 1111 1111 1111 1110 1111 *
+L2088 1111 1111 0111 1111 1111 1111 1111 1111 1111 *
+L2124 1111 1111 1111 1111 1111 1011 1111 1111 1111 *
+L2160 1111 1111 1111 1111 1111 1111 1111 0111 1111 *
+L2196 1111 1111 1111 1111 1111 1111 1111 1111 1011 *
+L2232 1111 1111 1111 1111 1111 1111 0111 1101 1111 *
+L2268 1111 1111 1111 1111 0111 1111 1111 1111 1111 *
+
+N Output Enable 19,18,...12 *
+L2304 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2340 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2376 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2412 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2448 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2484 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2520 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+L2556 1110 1111 1111 1111 1111 1111 1111 1111 1111 *
+
+N Sync Preset, Async Clear, Macrocell 19,18,...12 *
+L2592 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2628 0000 0000 0000 0000 0000 0000 0000 0000 0000 *
+L2664 1100 1100 1100 1100 1100 1100 1100 1100 *
+
+C3A61 *
+0000