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author Curt Coder <curtcoder@mail.com>2014-03-18 11:46:44 +0000
committer Curt Coder <curtcoder@mail.com>2014-03-18 11:46:44 +0000
commitf65e037141714318cfd32ecf988a7993f6cd9b3f (patch)
tree4c9a58e4b763733d3e2e80a409da026626978cc7 /src/mess/machine
parent15b2c80c62e9eddad3a6322fdef9c22039ce1eaa (diff)
(MESS) Moved common machine and video chips to emu. (nw)
Diffstat (limited to 'src/mess/machine')
-rw-r--r--src/mess/machine/68561mpcc.c486
-rw-r--r--src/mess/machine/68561mpcc.h100
-rw-r--r--src/mess/machine/8530scc.c675
-rw-r--r--src/mess/machine/8530scc.h101
-rw-r--r--src/mess/machine/cs4031.c993
-rw-r--r--src/mess/machine/cs4031.h291
-rw-r--r--src/mess/machine/cs8221.c165
-rw-r--r--src/mess/machine/cs8221.h86
-rw-r--r--src/mess/machine/hd63450.c495
-rw-r--r--src/mess/machine/hd63450.h51
-rw-r--r--src/mess/machine/hd64610.c366
-rw-r--r--src/mess/machine/hd64610.h105
-rw-r--r--src/mess/machine/i8271.c1543
-rw-r--r--src/mess/machine/i8271.h164
-rw-r--r--src/mess/machine/kb3600.c221
-rw-r--r--src/mess/machine/kb3600.h152
-rw-r--r--src/mess/machine/kr2376.c369
-rw-r--r--src/mess/machine/kr2376.h123
-rw-r--r--src/mess/machine/lh5810.c192
-rw-r--r--src/mess/machine/lh5810.h99
-rw-r--r--src/mess/machine/mb8795.c327
-rw-r--r--src/mess/machine/mb8795.h108
-rw-r--r--src/mess/machine/mb89352.c652
-rw-r--r--src/mess/machine/mb89352.h123
-rw-r--r--src/mess/machine/mc68328.c2907
-rw-r--r--src/mess/machine/mc68328.h725
-rw-r--r--src/mess/machine/ncr5380.c477
-rw-r--r--src/mess/machine/ncr5380.h78
-rw-r--r--src/mess/machine/ncr5390.c850
-rw-r--r--src/mess/machine/ncr5390.h230
-rw-r--r--src/mess/machine/s3c44b0.c2065
-rw-r--r--src/mess/machine/s3c44b0.h825
-rw-r--r--src/mess/machine/upd71071.c447
-rw-r--r--src/mess/machine/upd71071.h84
34 files changed, 0 insertions, 16675 deletions
diff --git a/src/mess/machine/68561mpcc.c b/src/mess/machine/68561mpcc.c
deleted file mode 100644
index 8d2734b2a4e..00000000000
--- a/src/mess/machine/68561mpcc.c
+++ /dev/null
@@ -1,486 +0,0 @@
-/*********************************************************************
-
- 68561mpcc.c
-
- Rockwell 68561 MPCC (Multi Protocol Communications Controller)
-
- skeleton driver, just enough for besta.c console to work
-
-*********************************************************************/
-
-
-#include "emu.h"
-#include "68561mpcc.h"
-
-const device_type MPCC68561 = &device_creator<mpcc68561_t>;
-
-
-/***************************************************************************
- PARAMETERS
-***************************************************************************/
-
-#define LOG_MPCC (1)
-
-#if 0 // future
-
-/***************************************************************************
- IMPLEMENTATION
-***************************************************************************/
-
-mpcc68561_t::mpcc68561_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, MPCC68561, "Rockwell 68561 MPCC", tag, owner, clock, "mpcc68561", __FILE__)
-{
-}
-
-void mpcc68561_t::set_intrq_cb(line_cb_t cb)
-{
- intrq_cb = cb;
-}
-
-/*-------------------------------------------------
- mpcc_updateirqs
--------------------------------------------------*/
-
-void mpcc68561_t::updateirqs()
-{
- int irqstat;
-
- irqstat = 0;
- if (MasterIRQEnable)
- {
- if ((channel[0].txIRQEnable) && (channel[0].txIRQPending))
- {
- IRQType = IRQ_B_TX;
- irqstat = 1;
- }
- else if ((channel[1].txIRQEnable) && (channel[1].txIRQPending))
- {
- IRQType = IRQ_A_TX;
- irqstat = 1;
- }
- else if ((channel[0].extIRQEnable) && (channel[0].extIRQPending))
- {
- IRQType = IRQ_B_EXT;
- irqstat = 1;
- }
- else if ((channel[1].extIRQEnable) && (channel[1].extIRQPending))
- {
- IRQType = IRQ_A_EXT;
- irqstat = 1;
- }
- }
- else
- {
- IRQType = IRQ_NONE;
- }
-
-// printf("mpcc: irqstat %d, last %d\n", irqstat, lastIRQStat);
-// printf("ch0: en %d pd %d ch1: en %d pd %d\n", channel[0].txIRQEnable, channel[0].txIRQPending, channel[1].txIRQEnable, channel[1].txIRQPending);
-
- // don't spam the driver with unnecessary transitions
- if (irqstat != lastIRQStat)
- {
- lastIRQStat = irqstat;
-
- // tell the driver the new IRQ line status if possible
-#if LOG_MPCC
- printf("mpcc68561 IRQ status => %d\n", irqstat);
-#endif
- if(!intrq_cb.isnull())
- intrq_cb(irqstat);
- }
-}
-
-/*-------------------------------------------------
- mpcc_initchannel
--------------------------------------------------*/
-void mpcc68561_t::initchannel(int ch)
-{
- channel[ch].syncHunt = 1;
-}
-
-/*-------------------------------------------------
- mpcc_resetchannel
--------------------------------------------------*/
-void mpcc68561_t::resetchannel(int ch)
-{
- emu_timer *timersave = channel[ch].baudtimer;
-
- memset(&channel[ch], 0, sizeof(Chan));
-
- channel[ch].txUnderrun = 1;
- channel[ch].baudtimer = timersave;
-
- channel[ch].baudtimer->adjust(attotime::never, ch);
-}
-
-/*-------------------------------------------------
- mpcc68561_baud_expire - baud rate timer expiry
--------------------------------------------------*/
-
-void mpcc68561_t::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- Chan *pChan = &channel[id];
- int brconst = pChan->reg_val[13]<<8 | pChan->reg_val[14];
- int rate;
-
- if (brconst)
- {
- rate = clock() / brconst;
- }
- else
- {
- rate = 0;
- }
-
- // is baud counter IRQ enabled on this channel?
- // always flag pending in case it's enabled after this
- pChan->baudIRQPending = 1;
- if (pChan->baudIRQEnable)
- {
- if (pChan->extIRQEnable)
- {
- pChan->extIRQPending = 1;
- pChan->baudIRQPending = 0;
- updateirqs();
- }
- }
-
- // reset timer according to current register values
- if (rate)
- {
- timer.adjust(attotime::from_hz(rate), 0, attotime::from_hz(rate));
- }
- else
- {
- timer.adjust(attotime::never, 0, attotime::never);
- }
-}
-
-/*-------------------------------------------------
- device_start - device-specific startup
--------------------------------------------------*/
-
-void mpcc68561_t::device_start()
-{
- memset(channel, 0, sizeof(channel));
-
- mode = 0;
- reg = 0;
- status = 0;
- IRQV = 0;
- MasterIRQEnable = 0;
- lastIRQStat = 0;
- IRQType = IRQ_NONE;
-
- channel[0].baudtimer = timer_alloc(0);
-}
-
-
-/*-------------------------------------------------
- device_reset - device-specific reset
--------------------------------------------------*/
-void mpcc68561_t::device_reset()
-{
- IRQType = IRQ_NONE;
- MasterIRQEnable = 0;
- IRQV = 0;
-
- initchannel(0);
- resetchannel(0);
-}
-
-/*-------------------------------------------------
- mpcc_set_status
--------------------------------------------------*/
-
-void mpcc68561_t::set_status(int _status)
-{
- status = _status;
-}
-
-/*-------------------------------------------------
- mpcc_acknowledge
--------------------------------------------------*/
-
-void mpcc68561_t::acknowledge()
-{
- if(!intrq_cb.isnull())
- intrq_cb(0);
-}
-
-/*-------------------------------------------------
- mpcc_getreg
--------------------------------------------------*/
-
-UINT8 mpcc68561_t::getreg()
-{
- /* Not yet implemented */
- #if LOG_MPCC
- printf("mpcc: port A reg %d read 0x%02x\n", reg, channel[0].reg_val[reg]);
- #endif
-
- if (reg == 0)
- {
- UINT8 rv = 0;
-
- Chan *ourCh = &channel[0];
-
- rv |= (ourCh->txUnderrun) ? 0x40 : 0;
- rv |= (ourCh->syncHunt) ? 0x10 : 0;
- rv |= channel[0].reg_val[0] & 0x05; // pick up TXBE and RXBF bits
-
- return rv;
- }
- else if (reg == 10)
- {
- return 0;
- }
- return channel[0].reg_val[reg];
-}
-
-/*-------------------------------------------------
- mpcc_putreg
--------------------------------------------------*/
-
-void mpcc68561_t::putreg(int ch, UINT8 data)
-{
- Chan *pChan = &channel[ch];
-
- channel[ch].reg_val[reg] = data;
- #if LOG_MPCC
- printf("mpcc: port %c reg %d write 0x%02x\n", 'A'+ch, reg, data);
- #endif
-
- switch (reg)
- {
- case 0: // command register
- switch ((data >> 3) & 7)
- {
- case 1: // select high registers (handled elsewhere)
- break;
-
- case 2: // reset external and status IRQs
- pChan->syncHunt = 0;
- break;
-
- case 5: // ack Tx IRQ
- pChan->txIRQPending = 0;
- updateirqs();
- break;
-
- case 0: // nothing
- case 3: // send SDLC abort
- case 4: // enable IRQ on next Rx byte
- case 6: // reset errors
- case 7: // reset highest IUS
- // we don't handle these yet
- break;
-
- }
- break;
-
- case 1: // Tx/Rx IRQ and data transfer mode defintion
- pChan->extIRQEnable = (data & 1);
- pChan->txIRQEnable = (data & 2) ? 1 : 0;
- pChan->rxIRQEnable = (data >> 3) & 3;
- updateirqs();
- break;
-
- case 2: // IRQ vector
- IRQV = data;
- break;
-
- case 3: // Rx parameters and controls
- pChan->rxEnable = (data & 1);
- pChan->syncHunt = (data & 0x10) ? 1 : 0;
- break;
-
- case 5: // Tx parameters and controls
-// printf("ch %d TxEnable = %d [%02x]\n", ch, data & 8, data);
- pChan->txEnable = data & 8;
-
- if (pChan->txEnable)
- {
- pChan->reg_val[0] |= 0x04; // Tx empty
- }
- break;
-
- case 4: // Tx/Rx misc parameters and modes
- case 6: // sync chars/SDLC address field
- case 7: // sync char/SDLC flag
- break;
-
- case 9: // master IRQ control
- MasterIRQEnable = (data & 8) ? 1 : 0;
- updateirqs();
-
- // channel reset command
- switch ((data>>6) & 3)
- {
- case 0: // do nothing
- break;
-
- case 1: // reset channel B
- resetchannel(0);
- break;
-
- case 3: // force h/w reset (entire chip)
- IRQType = IRQ_NONE;
- MasterIRQEnable = 0;
- IRQV = 0;
-
- initchannel(0);
- resetchannel(0);
-
- // make sure we stop yanking the IRQ line if we were
- updateirqs();
- break;
-
- }
- break;
-
- case 10: // misc transmitter/receiver control bits
- case 11: // clock mode control
- case 12: // lower byte of baud rate gen
- case 13: // upper byte of baud rate gen
- break;
-
- case 14: // misc control bits
- if (data & 0x01) // baud rate generator enable?
- {
- int brconst = pChan->reg_val[13]<<8 | pChan->reg_val[14];
- int rate = clock() / brconst;
-
- pChan->baudtimer->adjust(attotime::from_hz(rate), 0, attotime::from_hz(rate));
- }
- break;
-
- case 15: // external/status interrupt control
- pChan->baudIRQEnable = (data & 2) ? 1 : 0;
- pChan->DCDEnable = (data & 8) ? 1 : 0;
- pChan->CTSEnable = (data & 0x20) ? 1 : 0;
- pChan->txUnderrunEnable = (data & 0x40) ? 1 : 0;
- break;
- }
-}
-
-/*-------------------------------------------------
- mpcc68561_get_reg_a
--------------------------------------------------*/
-
-UINT8 mpcc68561_t::get_reg_a(int reg)
-{
- return channel[0].reg_val[reg];
-}
-
-
-
-/*-------------------------------------------------
- mpcc68561_set_reg_a
--------------------------------------------------*/
-
-void mpcc68561_t::set_reg_a(int reg, UINT8 data)
-{
- channel[0].reg_val[reg] = data;
-}
-
-
-
-/*-------------------------------------------------
- mpcc68561_r
--------------------------------------------------*/
-
-READ8_MEMBER( mpcc68561_t::reg_r)
-{
- UINT8 result = 0;
-
- offset %= 4;
-
- switch(offset)
- {
- case 1:
- /* Channel A (Modem Port) Control */
- if (mode == 1)
- mode = 0;
- else
- reg = 0;
-
- result = getreg();
- break;
-
- case 3:
- /* Channel A (Modem Port) Data */
- return channel[0].rxData;
- break;
- }
- return result;
-}
-
-
-
-/*-------------------------------------------------
- mpcc68561_w
--------------------------------------------------*/
-
-WRITE8_MEMBER( mpcc68561_t::reg_w )
-{
- Chan *pChan;
-
- offset &= 3;
-
-// printf(" mode %d data %x offset %d \n", mode, data, offset);
-
- switch(offset)
- {
- case 1:
- /* Channel A (Modem Port) Control */
- if (mode == 0)
- {
- if((data & 0xf0) == 0) // not a reset command
- {
- mode = 1;
- reg = data & 0x0f;
-// putareg(data & 0xf0);
- }
- else if (data == 0x10)
- {
- pChan = &channel[0];
- // clear ext. interrupts
- pChan->extIRQPending = 0;
- pChan->baudIRQPending = 0;
- updateirqs();
- }
- }
- else
- {
- mode = 0;
- putreg(0, data);
- }
- break;
-
- case 3:
- /* Channel A (Modem Port) Data */
- pChan = &channel[0];
-
- if (pChan->txEnable)
- {
- pChan->txData = data;
- // local loopback?
- if (pChan->reg_val[14] & 0x10)
- {
- pChan->rxData = data;
- pChan->reg_val[0] |= 0x01; // Rx character available
- }
- pChan->reg_val[1] |= 0x01; // All sent
- pChan->reg_val[0] |= 0x04; // Tx empty
- pChan->txUnderrun = 1;
- pChan->txIRQPending = 1;
- updateirqs();
- }
- break;
- }
-}
-
-#else
-
-#endif
diff --git a/src/mess/machine/68561mpcc.h b/src/mess/machine/68561mpcc.h
deleted file mode 100644
index 2d446a5ab5b..00000000000
--- a/src/mess/machine/68561mpcc.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*********************************************************************
-
- 68561mpcc.h
-
- Rockwell 68561 MPCC (Multi Protocol Communications Controller)
-
- skeleton driver
-
-*********************************************************************/
-
-#ifndef __68561MPCC_H__
-#define __68561MPCC_H__
-
-#define MCFG_MPCC68561_ADD(_tag, _clock, _intrq_cb) \
- MCFG_DEVICE_ADD(_tag, MPCC68561, _clock) \
- downcast<mpcc68561_t *>(device)->set_intrq_cb(_intrq_cb);
-
-class mpcc68561_t : public device_t
-{
-public:
- enum IRQType_t {
- IRQ_NONE,
- IRQ_A_RX,
- IRQ_A_RX_SPECIAL,
- IRQ_B_RX,
- IRQ_B_RX_SPECIAL,
- IRQ_A_TX,
- IRQ_B_TX,
- IRQ_A_EXT,
- IRQ_B_EXT,
- };
-
- mpcc68561_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
- void set_intrq_cb(line_cb_t cb);
-
- UINT8 get_reg_a(int reg);
- void set_reg_a(int reg, UINT8 data);
-
- void set_status(int status);
-
- DECLARE_READ8_MEMBER(reg_r);
- DECLARE_WRITE8_MEMBER(reg_w);
-
-protected:
- virtual void device_start();
- virtual void device_reset();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
-
-private:
- struct Chan {
- bool txIRQEnable;
- bool rxIRQEnable;
- bool extIRQEnable;
- bool baudIRQEnable;
- bool txIRQPending;
- bool rxIRQPending;
- bool extIRQPending;
- bool baudIRQPending;
- bool txEnable;
- bool rxEnable;
- bool txUnderrun;
- bool txUnderrunEnable;
- bool syncHunt;
- bool DCDEnable;
- bool CTSEnable;
- UINT8 rxData;
- UINT8 txData;
-
- emu_timer *baudtimer;
-
- UINT8 reg_val[22];
- };
-
- int mode;
- int reg;
- int status;
- int IRQV;
- int MasterIRQEnable;
- int lastIRQStat;
- IRQType_t IRQType;
-
- Chan channel[1];
-
- line_cb_t intrq_cb;
-
- void updateirqs();
- void initchannel(int ch);
- void resetchannel(int ch);
- void acknowledge();
- UINT8 getreg();
- void putreg(int ch, UINT8 data);
-};
-
-/***************************************************************************
- MACROS
-***************************************************************************/
-
-extern const device_type MPCC68561;
-
-#endif /* __68561MPCC_H__ */
diff --git a/src/mess/machine/8530scc.c b/src/mess/machine/8530scc.c
deleted file mode 100644
index 56ffbd30365..00000000000
--- a/src/mess/machine/8530scc.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*********************************************************************
-
- 8530scc.c
-
- Zilog 8530 SCC (Serial Control Chip) code
-
-*********************************************************************/
-
-
-#include "emu.h"
-#include "8530scc.h"
-
-const device_type SCC8530 = &device_creator<scc8530_t>;
-
-
-/***************************************************************************
- PARAMETERS
-***************************************************************************/
-
-#define LOG_SCC (0)
-
-/***************************************************************************
- IMPLEMENTATION
-***************************************************************************/
-
-scc8530_t::scc8530_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
- device_t(mconfig, SCC8530, "Zilog 8530 SCC", tag, owner, clock, "scc8530", __FILE__),
- intrq_cb(*this)
-{
-}
-
-
-/*-------------------------------------------------
- scc_updateirqs
--------------------------------------------------*/
-
-void scc8530_t::updateirqs()
-{
- int irqstat;
-
- irqstat = 0;
- if (MasterIRQEnable)
- {
- if ((channel[0].txIRQEnable) && (channel[0].txIRQPending))
- {
- IRQType = IRQ_B_TX;
- irqstat = 1;
- }
- else if ((channel[1].txIRQEnable) && (channel[1].txIRQPending))
- {
- IRQType = IRQ_A_TX;
- irqstat = 1;
- }
- else if ((channel[0].extIRQEnable) && (channel[0].extIRQPending))
- {
- IRQType = IRQ_B_EXT;
- irqstat = 1;
- }
- else if ((channel[1].extIRQEnable) && (channel[1].extIRQPending))
- {
- IRQType = IRQ_A_EXT;
- irqstat = 1;
- }
- }
- else
- {
- IRQType = IRQ_NONE;
- }
-
-// printf("SCC: irqstat %d, last %d\n", irqstat, lastIRQStat);
-// printf("ch0: en %d pd %d ch1: en %d pd %d\n", channel[0].txIRQEnable, channel[0].txIRQPending, channel[1].txIRQEnable, channel[1].txIRQPending);
-
- // don't spam the driver with unnecessary transitions
- if (irqstat != lastIRQStat)
- {
- lastIRQStat = irqstat;
-
- // tell the driver the new IRQ line status if possible
-#if LOG_SCC
- printf("SCC8530 IRQ status => %d\n", irqstat);
-#endif
- if(!intrq_cb.isnull())
- intrq_cb(irqstat);
- }
-}
-
-/*-------------------------------------------------
- scc_initchannel
--------------------------------------------------*/
-void scc8530_t::initchannel(int ch)
-{
- channel[ch].syncHunt = 1;
-}
-
-/*-------------------------------------------------
- scc_resetchannel
--------------------------------------------------*/
-void scc8530_t::resetchannel(int ch)
-{
- emu_timer *timersave = channel[ch].baudtimer;
-
- memset(&channel[ch], 0, sizeof(Chan));
-
- channel[ch].txUnderrun = 1;
- channel[ch].baudtimer = timersave;
-
- channel[ch].baudtimer->adjust(attotime::never, ch);
-}
-
-/*-------------------------------------------------
- scc8530_baud_expire - baud rate timer expiry
--------------------------------------------------*/
-
-void scc8530_t::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- Chan *pChan = &channel[id];
- int brconst = pChan->reg_val[13]<<8 | pChan->reg_val[14];
- int rate;
-
- if (brconst)
- {
- rate = clock() / brconst;
- }
- else
- {
- rate = 0;
- }
-
- // is baud counter IRQ enabled on this channel?
- // always flag pending in case it's enabled after this
- pChan->baudIRQPending = 1;
- if (pChan->baudIRQEnable)
- {
- if (pChan->extIRQEnable)
- {
- pChan->extIRQPending = 1;
- pChan->baudIRQPending = 0;
- updateirqs();
- }
- }
-
- // reset timer according to current register values
- if (rate)
- {
- timer.adjust(attotime::from_hz(rate), 0, attotime::from_hz(rate));
- }
- else
- {
- timer.adjust(attotime::never, 0, attotime::never);
- }
-}
-
-/*-------------------------------------------------
- device_start - device-specific startup
--------------------------------------------------*/
-
-void scc8530_t::device_start()
-{
- intrq_cb.resolve();
-
- memset(channel, 0, sizeof(channel));
-
- mode = 0;
- reg = 0;
- status = 0;
- IRQV = 0;
- MasterIRQEnable = 0;
- lastIRQStat = 0;
- IRQType = IRQ_NONE;
-
- channel[0].baudtimer = timer_alloc(0);
- channel[1].baudtimer = timer_alloc(1);
-}
-
-
-/*-------------------------------------------------
- device_reset - device-specific reset
--------------------------------------------------*/
-void scc8530_t::device_reset()
-{
- IRQType = IRQ_NONE;
- MasterIRQEnable = 0;
- IRQV = 0;
-
- initchannel(0);
- initchannel(1);
- resetchannel(0);
- resetchannel(1);
-}
-
-/*-------------------------------------------------
- scc_set_status
--------------------------------------------------*/
-
-void scc8530_t::set_status(int _status)
-{
- status = _status;
-}
-
-/*-------------------------------------------------
- scc_acknowledge
--------------------------------------------------*/
-
-void scc8530_t::acknowledge()
-{
- if(!intrq_cb.isnull())
- intrq_cb(0);
-}
-
-/*-------------------------------------------------
- scc_getareg
--------------------------------------------------*/
-
-UINT8 scc8530_t::getareg()
-{
- /* Not yet implemented */
- #if LOG_SCC
- printf("SCC: port A reg %d read 0x%02x\n", reg, channel[0].reg_val[reg]);
- #endif
-
- if (reg == 0)
- {
- UINT8 rv = 0;
-
- Chan *ourCh = &channel[0];
-
- rv |= (ourCh->txUnderrun) ? 0x40 : 0;
- rv |= (ourCh->syncHunt) ? 0x10 : 0;
- rv |= channel[0].reg_val[0] & 0x05; // pick up TXBE and RXBF bits
-
- return rv;
- }
- else if (reg == 10)
- {
- return 0;
- }
- return channel[0].reg_val[reg];
-}
-
-
-
-/*-------------------------------------------------
- scc_getareg
--------------------------------------------------*/
-
-UINT8 scc8530_t::getbreg()
-{
- #if LOG_SCC
- printf("SCC: port B reg %i read 0x%02x\n", reg, channel[1].reg_val[reg]);
- #endif
-
- if (reg == 0)
- {
- UINT8 rv = 0;
-
- Chan *ourCh = &channel[1];
-
- rv |= (ourCh->txUnderrun) ? 0x40 : 0;
- rv |= (ourCh->syncHunt) ? 0x10 : 0;
- rv |= channel[1].reg_val[0] & 0x05; // pick up TXBE and RXBF bits
-
- return rv;
- }
- else if (reg == 2)
- {
- /* HACK! but lets the Mac Plus mouse move again. Needs further investigation. */
- acknowledge();
-
- return status;
- }
- else if (reg == 10)
- {
- return 0;
- }
-
- return channel[1].reg_val[reg];
-}
-
-
-
-/*-------------------------------------------------
- scc_putreg
--------------------------------------------------*/
-
-void scc8530_t::putreg(int ch, UINT8 data)
-{
- Chan *pChan = &channel[ch];
-
- channel[ch].reg_val[reg] = data;
- #if LOG_SCC
- printf("SCC: port %c reg %d write 0x%02x\n", 'A'+ch, reg, data);
- #endif
-
- switch (reg)
- {
- case 0: // command register
- switch ((data >> 3) & 7)
- {
- case 1: // select high registers (handled elsewhere)
- break;
-
- case 2: // reset external and status IRQs
- pChan->syncHunt = 0;
- break;
-
- case 5: // ack Tx IRQ
- pChan->txIRQPending = 0;
- updateirqs();
- break;
-
- case 0: // nothing
- case 3: // send SDLC abort
- case 4: // enable IRQ on next Rx byte
- case 6: // reset errors
- case 7: // reset highest IUS
- // we don't handle these yet
- break;
-
- }
- break;
-
- case 1: // Tx/Rx IRQ and data transfer mode defintion
- pChan->extIRQEnable = (data & 1);
- pChan->txIRQEnable = (data & 2) ? 1 : 0;
- pChan->rxIRQEnable = (data >> 3) & 3;
- updateirqs();
- break;
-
- case 2: // IRQ vector
- IRQV = data;
- break;
-
- case 3: // Rx parameters and controls
- pChan->rxEnable = (data & 1);
- pChan->syncHunt = (data & 0x10) ? 1 : 0;
- break;
-
- case 5: // Tx parameters and controls
-// printf("ch %d TxEnable = %d [%02x]\n", ch, data & 8, data);
- pChan->txEnable = data & 8;
-
- if (pChan->txEnable)
- {
- pChan->reg_val[0] |= 0x04; // Tx empty
- }
- break;
-
- case 4: // Tx/Rx misc parameters and modes
- case 6: // sync chars/SDLC address field
- case 7: // sync char/SDLC flag
- break;
-
- case 9: // master IRQ control
- MasterIRQEnable = (data & 8) ? 1 : 0;
- updateirqs();
-
- // channel reset command
- switch ((data>>6) & 3)
- {
- case 0: // do nothing
- break;
-
- case 1: // reset channel B
- resetchannel(0);
- break;
-
- case 2: // reset channel A
- resetchannel(1);
- break;
-
- case 3: // force h/w reset (entire chip)
- IRQType = IRQ_NONE;
- MasterIRQEnable = 0;
- IRQV = 0;
-
- initchannel(0);
- initchannel(1);
- resetchannel(0);
- resetchannel(1);
-
- // make sure we stop yanking the IRQ line if we were
- updateirqs();
- break;
-
- }
- break;
-
- case 10: // misc transmitter/receiver control bits
- case 11: // clock mode control
- case 12: // lower byte of baud rate gen
- case 13: // upper byte of baud rate gen
- break;
-
- case 14: // misc control bits
- if (data & 0x01) // baud rate generator enable?
- {
- int brconst = pChan->reg_val[13]<<8 | pChan->reg_val[14];
- int rate = clock() / brconst;
-
- pChan->baudtimer->adjust(attotime::from_hz(rate), 0, attotime::from_hz(rate));
- }
- break;
-
- case 15: // external/status interrupt control
- pChan->baudIRQEnable = (data & 2) ? 1 : 0;
- pChan->DCDEnable = (data & 8) ? 1 : 0;
- pChan->CTSEnable = (data & 0x20) ? 1 : 0;
- pChan->txUnderrunEnable = (data & 0x40) ? 1 : 0;
- break;
- }
-}
-
-/*-------------------------------------------------
- scc8530_get_reg_a
--------------------------------------------------*/
-
-UINT8 scc8530_t::get_reg_a(int reg)
-{
- return channel[0].reg_val[reg];
-}
-
-
-
-/*-------------------------------------------------
- scc8530_get_reg_b
--------------------------------------------------*/
-
-UINT8 scc8530_t::get_reg_b(int reg)
-{
- return channel[1].reg_val[reg];
-}
-
-
-
-/*-------------------------------------------------
- scc8530_set_reg_a
--------------------------------------------------*/
-
-void scc8530_t::set_reg_a(int reg, UINT8 data)
-{
- channel[0].reg_val[reg] = data;
-}
-
-
-
-/*-------------------------------------------------
- scc8530_set_reg_a
--------------------------------------------------*/
-
-void scc8530_t::set_reg_b(int reg, UINT8 data)
-{
- channel[1].reg_val[reg] = data;
-}
-
-
-
-/*-------------------------------------------------
- scc8530_r
--------------------------------------------------*/
-
-READ8_MEMBER( scc8530_t::reg_r)
-{
- UINT8 result = 0;
-
- offset %= 4;
-
- switch(offset)
- {
- case 0:
- /* Channel B (Printer Port) Control */
- if (mode == 1)
- mode = 0;
- else
- reg = 0;
-
- result = getbreg();
- break;
-
- case 1:
- /* Channel A (Modem Port) Control */
- if (mode == 1)
- mode = 0;
- else
- reg = 0;
-
- result = getareg();
- break;
-
- case 2:
- /* Channel B (Printer Port) Data */
- result = channel[1].rxData;
- break;
-
- case 3:
- /* Channel A (Modem Port) Data */
- result = channel[0].rxData;
- break;
- }
- return result;
-}
-
-
-
-/*-------------------------------------------------
- scc8530_w
--------------------------------------------------*/
-
-WRITE8_MEMBER( scc8530_t::reg_w )
-{
- Chan *pChan;
-
- offset &= 3;
-
-// printf(" mode %d data %x offset %d \n", mode, data, offset);
-
- switch(offset)
- {
- case 0:
- /* Channel B (Printer Port) Control */
- if (mode == 0)
- {
- if((data & 0xf0) == 0) // not a reset command
- {
- mode = 1;
- reg = data & 0x0f;
-// putbreg(data & 0xf0);
- }
- else if (data == 0x10)
- {
- pChan = &channel[1];
- // clear ext. interrupts
- pChan->extIRQPending = 0;
- pChan->baudIRQPending = 0;
- updateirqs();
- }
- }
- else
- {
- mode = 0;
- putreg(1, data);
- }
- break;
-
- case 1:
- /* Channel A (Modem Port) Control */
- if (mode == 0)
- {
- if((data & 0xf0) == 0) // not a reset command
- {
- mode = 1;
- reg = data & 0x0f;
-// putareg(data & 0xf0);
- }
- else if (data == 0x10)
- {
- pChan = &channel[0];
- // clear ext. interrupts
- pChan->extIRQPending = 0;
- pChan->baudIRQPending = 0;
- updateirqs();
- }
- }
- else
- {
- mode = 0;
- putreg(0, data);
- }
- break;
-
- case 2:
- /* Channel B (Printer Port) Data */
- pChan = &channel[1];
-
- if (pChan->txEnable)
- {
- pChan->txData = data;
- // local loopback?
- if (pChan->reg_val[14] & 0x10)
- {
- pChan->rxData = data;
- pChan->reg_val[0] |= 0x01; // Rx character available
- }
- pChan->reg_val[1] |= 0x01; // All sent
- pChan->reg_val[0] |= 0x04; // Tx empty
- pChan->txUnderrun = 1;
- pChan->txIRQPending = 1;
- updateirqs();
- }
- break;
-
- case 3:
- /* Channel A (Modem Port) Data */
- pChan = &channel[0];
-
- if (pChan->txEnable)
- {
- pChan->txData = data;
- // local loopback?
- if (pChan->reg_val[14] & 0x10)
- {
- pChan->rxData = data;
- pChan->reg_val[0] |= 0x01; // Rx character available
- }
- pChan->reg_val[1] |= 0x01; // All sent
- pChan->reg_val[0] |= 0x04; // Tx empty
- pChan->txUnderrun = 1;
- pChan->txIRQPending = 1;
- updateirqs();
- }
- break;
- }
-}
-
-/*
-
-AppleTalk check:
-
-SCC: port B reg 9 write 0x40 Channel Reset B
-SCC: port B reg 4 write 0x20 SDLC mode
-SCC: port B reg 10 write 0xe0 CRC preset + FM0
-SCC: port B reg 6 write 0x00 SDLC address
-SCC: port B reg 7 write 0x7e SDLC flag
-SCC: port B reg 12 write 0x06 baud rate low
-SCC: port B reg 13 write 0x00 baud rate high
-SCC: port B reg 14 write 0xc0 Set FM mode
-SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable
-SCC: port B reg 2 write 0x00 interrupt vector 0
-SCC: port B reg 15 write 0x08 DCD interrupt enable
-SCC: port B reg 1 write 0x09 Rx IRQ on first char or special, ext int enable
-SCC: port B reg 9 write 0x0a Master IRQ enable, no-vector mode
-SCC: port B reg 11 write 0x70 Rx clock = DPLL output, Tx clock = BR generator
-SCC: port B reg 14 write 0x21 Enter search mode, BR generator enable
-SCC: port B reg 5 write 0x60 Tx 8 bits/char
-SCC: port B reg 6 write 0x2a SDLC address
-SCC: port B reg 0 read 0x00
-SCC: port B reg 15 write 0x88 DCD interrupt enable, break/abort interrupt enable
-
-(repeats)
-SCC: port B reg 1 read 0x09
-SCC: port B reg 3 write 0xd0
-SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable
-SCC: port B reg 15 write 0x08 DCD interrupt enable
-SCC: port B reg 0 read 0x00
-SCC: port B reg 15 write 0x88
-
-System 7:
-
-SCC: port B reg 9 write 0x40 Channel Reset B
-SCC: port B reg 4 write 0x20 SDLC mode
-SCC: port B reg 10 write 0xe0 CRC preset + FM0
-SCC: port B reg 6 write 0x00 SDLC address
-SCC: port B reg 7 write 0x7e SDLC flag
-SCC: port B reg 12 write 0x06 baud rate low
-SCC: port B reg 13 write 0x00 baud rate high
-SCC: port B reg 14 write 0xc0 Set FM mode
-SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable
-SCC: port B reg 2 write 0x00 interrupt vector 0
-SCC: port B reg 15 write 0x08 DCD interrupt enable
-SCC: port B reg 1 write 0x09 Rx IRQ on first char or special, ext int enable
-SCC: port B reg 9 write 0x0a Master IRQ enable, no-vector mode
-SCC: port B reg 11 write 0x70 Rx clock = DPLL output, Tx clock = BR generator
-SCC: port B reg 14 write 0x21 Enter search mode, BR generator enable
-SCC: port B reg 5 write 0x60 Tx 8 bits/char
-SCC: port B reg 6 write 0x01 SDLC address
-SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable
-
-(repeats)
-
-SCC: port B reg 0 read 0x00
-SCC: port B reg 15 write 0x88 DCD interrupt enable, break/abort interrupt enable
-SCC: port B reg 15 write 0x08 DCD interrupt enable
-SCC: port B reg 1 read 0x09 Rx IRQ on first char or special, ext int enable
-SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable
-
-*/
diff --git a/src/mess/machine/8530scc.h b/src/mess/machine/8530scc.h
deleted file mode 100644
index 97db19978d0..00000000000
--- a/src/mess/machine/8530scc.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*********************************************************************
-
- 8530scc.h
-
- Zilog 8530 SCC (Serial Control Chip) code
-
-*********************************************************************/
-
-#ifndef __8530SCC_H__
-#define __8530SCC_H__
-
-#define MCFG_Z8530_INTRQ_CALLBACK(_write) \
- devcb = &scc8530_t::set_intrq_wr_callback(*device, DEVCB2_##_write);
-
-class scc8530_t : public device_t
-{
-public:
- enum IRQType_t {
- IRQ_NONE,
- IRQ_A_RX,
- IRQ_A_RX_SPECIAL,
- IRQ_B_RX,
- IRQ_B_RX_SPECIAL,
- IRQ_A_TX,
- IRQ_B_TX,
- IRQ_A_EXT,
- IRQ_B_EXT,
- };
-
- scc8530_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- template<class _Object> static devcb2_base &set_intrq_wr_callback(device_t &device, _Object object) { return downcast<scc8530_t &>(device).intrq_cb.set_callback(object); }
-
- UINT8 get_reg_a(int reg);
- UINT8 get_reg_b(int reg);
- void set_reg_a(int reg, UINT8 data);
- void set_reg_b(int reg, UINT8 data);
-
- void set_status(int status);
-
- DECLARE_READ8_MEMBER(reg_r);
- DECLARE_WRITE8_MEMBER(reg_w);
-
-protected:
- virtual void device_start();
- virtual void device_reset();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
-
-private:
- struct Chan {
- bool txIRQEnable;
- bool rxIRQEnable;
- bool extIRQEnable;
- bool baudIRQEnable;
- bool txIRQPending;
- bool rxIRQPending;
- bool extIRQPending;
- bool baudIRQPending;
- bool txEnable;
- bool rxEnable;
- bool txUnderrun;
- bool txUnderrunEnable;
- bool syncHunt;
- bool DCDEnable;
- bool CTSEnable;
- UINT8 rxData;
- UINT8 txData;
-
- emu_timer *baudtimer;
-
- UINT8 reg_val[16];
- };
-
- int mode;
- int reg;
- int status;
- int IRQV;
- int MasterIRQEnable;
- int lastIRQStat;
- IRQType_t IRQType;
-
- Chan channel[2];
-
- devcb2_write_line intrq_cb;
-
- void updateirqs();
- void initchannel(int ch);
- void resetchannel(int ch);
- void acknowledge();
- UINT8 getareg();
- UINT8 getbreg();
- void putreg(int ch, UINT8 data);
-};
-
-/***************************************************************************
- MACROS
-***************************************************************************/
-
-extern const device_type SCC8530;
-
-#endif /* __8530SCC_H__ */
diff --git a/src/mess/machine/cs4031.c b/src/mess/machine/cs4031.c
deleted file mode 100644
index ba35f39f55d..00000000000
--- a/src/mess/machine/cs4031.c
+++ /dev/null
@@ -1,993 +0,0 @@
-/***************************************************************************
-
- Chips & Technologies CS4031 chipset
-
- license: MAME, GPL-2.0+
- copyright-holders: Dirk Best
-
- Chipset for 486 based PC/AT compatible systems. Consists of two
- individual chips:
-
- * F84031
- - DRAM controller
- - ISA-bus controller
- - VESA VL-BUS controller
-
- * F84035 (82C206 IPC core)
- - 2x 8257 DMA controller
- - 2x 8259 interrupt controller
- - 8254 timer
- - MC14818 RTC
-
- TODO:
- - No emulation of memory parity checks
- - Move IPC core to its own file so it can be shared with
- other chipsets
-
-***************************************************************************/
-
-#include "emu.h"
-#include "machine/ram.h"
-#include "machine/cs4031.h"
-
-
-//**************************************************************************
-// MACROS/CONSTANTS
-//**************************************************************************
-
-#define LOG_REGISTER 1
-#define LOG_MEMORY 1
-#define LOG_IO 1
-#define LOG_KEYBOARD 0
-
-
-//**************************************************************************
-// DEVICE DEFINITIONS
-//**************************************************************************
-
-const device_type CS4031 = &device_creator<cs4031_device>;
-
-const char* cs4031_device::m_register_names[] =
-{
- /* 00 */ "RESERVED",
- /* 01 */ "DMA WAIT STATE CONTROL",
- /* 02 */ "RESERVED",
- /* 03 */ "RESERVED",
- /* 04 */ "RESERVED",
- /* 05 */ "ISA BUS COMMAND DELAY",
- /* 06 */ "ISA BUS WAIT STATES AND ADDRESS HOLD",
- /* 07 */ "ISA BUS CLOCK SELECTION",
- /* 08 */ "PERFORMANCE CONTROL",
- /* 09 */ "84035 MISC CONTROL",
- /* 0a */ "DMA CLOCK SELECTION",
- /* 0b */ "RESERVED",
- /* 0c */ "RESERVED",
- /* 0d */ "RESERVED",
- /* 0e */ "RESERVED",
- /* 0f */ "RESERVED",
- /* 10 */ "DRAM TIMING",
- /* 11 */ "DRAM SETUP",
- /* 12 */ "DRAM CONFIGURATION 0 AND 1",
- /* 13 */ "DRAM CONFIGURATION 2 AND 3",
- /* 14 */ "DRAM BLOCK 0 STARTING ADDRESS",
- /* 15 */ "DRAM BLOCK 1 STARTING ADDRESS",
- /* 16 */ "DRAM BLOCK 2 STARTING ADDRESS",
- /* 17 */ "DRAM BLOCK 3 STARTING ADDRESS",
- /* 18 */ "VIDEO AREA SHADOW AND LOCAL BUS CONTROL",
- /* 19 */ "DRAM SHADOW READ ENABLE",
- /* 1a */ "DRAM SHADOW WRITE ENABLE",
- /* 1b */ "ROMCS ENABLE",
- /* 1c */ "SOFT RESET AND GATEA20",
- /* 1d */ "RESERVED",
- /* 1e */ "RESERVED",
- /* 1f */ "RESERVED"
-};
-
-const float cs4031_device::m_dma_clock_divider[] =
-{
- 10, 8, 6, 0, 0, 0, 0, 0, 5, 4, 3, 2.5, 2, 1.5, 0, 0
-};
-
-//-------------------------------------------------
-// machine_config_additions - device-specific
-// machine configurations
-//-------------------------------------------------
-
-I8237_INTERFACE( dma1_config )
-{
- DEVCB_DEVICE_LINE_MEMBER("dma2", am9517a_device, dreq0_w),
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_eop_w),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma_read_byte),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma_write_byte),
- {
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_ior0_r),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_ior1_r),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_ior2_r),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_ior3_r)
- },
- {
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_iow0_w),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_iow1_w),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_iow2_w),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_iow3_w)
- },
- {
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_dack0_w),
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_dack1_w),
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_dack2_w),
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma1_dack3_w)
- }
-};
-
-I8237_INTERFACE( dma2_config )
-{
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_hreq_w),
- DEVCB_NULL,
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma_read_word),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma_write_word),
- {
- DEVCB_NULL,
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_ior1_r),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_ior2_r),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_ior3_r)
- },
- {
- DEVCB_NULL,
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_iow1_w),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_iow2_w),
- DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_iow3_w)
- },
- {
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_dack0_w),
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_dack1_w),
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_dack2_w),
- DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, cs4031_device, dma2_dack3_w)
- }
-};
-
-static MACHINE_CONFIG_FRAGMENT( cs4031 )
- MCFG_I8237_ADD("dma1", 0, dma1_config)
- MCFG_I8237_ADD("dma2", 0, dma2_config)
- MCFG_PIC8259_ADD("intc1", WRITELINE(cs4031_device, intc1_int_w), VCC, READ8(cs4031_device, intc1_slave_ack_r))
- MCFG_PIC8259_ADD("intc2", DEVWRITELINE("intc1", pic8259_device, ir2_w), GND, NULL)
-
- MCFG_DEVICE_ADD("ctc", PIT8254, 0)
- MCFG_PIT8253_CLK0(XTAL_14_31818MHz / 12)
- MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("intc1", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(XTAL_14_31818MHz / 12)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(cs4031_device, ctc_out1_w))
- MCFG_PIT8253_CLK2(XTAL_14_31818MHz / 12)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(cs4031_device, ctc_out2_w))
-
- MCFG_DS12885_ADD("rtc")
- MCFG_MC146818_IRQ_HANDLER(WRITELINE(cs4031_device, rtc_irq_w))
- MCFG_MC146818_CENTURY_INDEX(0x32)
-MACHINE_CONFIG_END
-
-machine_config_constructor cs4031_device::device_mconfig_additions() const
-{
- return MACHINE_CONFIG_NAME( cs4031 );
-}
-
-
-//**************************************************************************
-// LIVE DEVICE
-//**************************************************************************
-
-//-------------------------------------------------
-// cs4031_device - constructor
-//-------------------------------------------------
-
-cs4031_device::cs4031_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
- device_t(mconfig, CS4031, "CS4031", tag, owner, clock, "cs4031", __FILE__),
- m_read_ior(*this),
- m_write_iow(*this),
- m_write_tc(*this),
- m_write_hold(*this),
- m_write_nmi(*this),
- m_write_intr(*this),
- m_write_cpureset(*this),
- m_write_a20m(*this),
- m_write_spkr(*this),
- m_dma1(*this, "dma1"),
- m_dma2(*this, "dma2"),
- m_intc1(*this, "intc1"),
- m_intc2(*this, "intc2"),
- m_ctc(*this, "ctc"),
- m_rtc(*this, "rtc"),
- m_dma_eop(0),
- m_dma_high_byte(0xff),
- m_dma_channel(-1),
- m_portb(0x0f),
- m_refresh_toggle(0),
- m_iochck(1),
- m_nmi_mask(1),
- m_cpureset(0),
- m_kbrst(1),
- m_ext_gatea20(0),
- m_fast_gatea20(0),
- m_emu_gatea20(0),
- m_keybc_d1_written(false),
- m_keybc_data_blocked(false),
- m_address(0),
- m_address_valid(false)
-{
-}
-
-void cs4031_device::static_set_cputag(device_t &device, const char *tag)
-{
- cs4031_device &cs4031 = downcast<cs4031_device &>(device);
- cs4031.m_cputag = tag;
-}
-
-void cs4031_device::static_set_isatag(device_t &device, const char *tag)
-{
- cs4031_device &cs4031 = downcast<cs4031_device &>(device);
- cs4031.m_isatag = tag;
-}
-
-void cs4031_device::static_set_biostag(device_t &device, const char *tag)
-{
- cs4031_device &cs4031 = downcast<cs4031_device &>(device);
- cs4031.m_biostag = tag;
-}
-
-void cs4031_device::static_set_keybctag(device_t &device, const char *tag)
-{
- cs4031_device &cs4031 = downcast<cs4031_device &>(device);
- cs4031.m_keybctag = tag;
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void cs4031_device::device_start()
-{
- ram_device *ram_dev = machine().device<ram_device>(RAM_TAG);
-
- // make sure the ram device is already running
- if (!ram_dev->started())
- throw device_missing_dependencies();
-
- // resolve callbacks
- m_read_ior.resolve_safe(0);
- m_write_iow.resolve_safe();
- m_write_tc.resolve_safe();
- m_write_hold.resolve_safe();
- m_write_nmi.resolve_safe();
- m_write_intr.resolve_safe();
- m_write_cpureset.resolve_safe();
- m_write_a20m.resolve_safe();
- m_write_spkr.resolve_safe();
-
- // register for state saving
- save_item(NAME(m_dma_eop));
- save_item(NAME(m_dma_page));
- save_item(NAME(m_dma_high_byte));
- save_item(NAME(m_dma_channel));
- save_item(NAME(m_portb));
- save_item(NAME(m_refresh_toggle));
- save_item(NAME(m_iochck));
- save_item(NAME(m_nmi_mask));
- save_item(NAME(m_cpureset));
- save_item(NAME(m_kbrst));
- save_item(NAME(m_ext_gatea20));
- save_item(NAME(m_fast_gatea20));
- save_item(NAME(m_address));
- save_item(NAME(m_address_valid));
- save_item(NAME(m_registers));
-
- device_t *cpu = machine().device(m_cputag);
- m_space = &cpu->memory().space(AS_PROGRAM);
- m_space_io = &cpu->memory().space(AS_IO);
-
- m_isa = machine().root_device().memregion(m_isatag)->base();
- m_bios = machine().root_device().memregion(m_biostag)->base();
- m_keybc = downcast<at_keyboard_controller_device *>(machine().device(m_keybctag));
-
- m_ram = ram_dev->pointer();
- UINT32 ram_size = ram_dev->size();
-
- // install base memory
- m_space->install_ram(0x000000, 0x09ffff, m_ram);
-
- // install extended memory
- if (ram_size > 0x100000)
- m_space->install_ram(0x100000, ram_size - 1, m_ram + 0x100000);
-
- // install bios rom at cpu inital pc
- m_space->install_rom(0xffff0000, 0xffffffff, m_bios + 0xf0000);
-
- // install i/o accesses
- m_space_io->install_readwrite_handler(0x0000, 0x000f, read8_delegate(FUNC(am9517a_device::read), &(*m_dma1)), write8_delegate(FUNC(am9517a_device::write), &(*m_dma1)), 0xffffffff);
- m_space_io->install_readwrite_handler(0x0020, 0x0023, read8_delegate(FUNC(pic8259_device::read), &(*m_intc1)), write8_delegate(FUNC(pic8259_device::write), &(*m_intc1)), 0x0000ffff);
- m_space_io->install_write_handler(0x0020, 0x0023, write8_delegate(FUNC(cs4031_device::config_address_w), this), 0x00ff0000);
- m_space_io->install_readwrite_handler(0x0020, 0x0023, read8_delegate(FUNC(cs4031_device::config_data_r), this), write8_delegate(FUNC(cs4031_device::config_data_w), this), 0xff000000);
- m_space_io->install_readwrite_handler(0x0040, 0x0043, read8_delegate(FUNC(pit8254_device::read), &(*m_ctc)), write8_delegate(FUNC(pit8254_device::write), &(*m_ctc)), 0xffffffff);
- m_space_io->install_readwrite_handler(0x0060, 0x0063, read8_delegate(FUNC(cs4031_device::keyb_data_r), this), write8_delegate(FUNC(cs4031_device::keyb_data_w), this), 0x000000ff);
- m_space_io->install_readwrite_handler(0x0060, 0x0063, read8_delegate(FUNC(cs4031_device::portb_r), this), write8_delegate(FUNC(cs4031_device::portb_w), this), 0x0000ff00);
- m_space_io->install_readwrite_handler(0x0064, 0x0067, read8_delegate(FUNC(cs4031_device::keyb_status_r), this), write8_delegate(FUNC(cs4031_device::keyb_command_w), this), 0x000000ff);
- m_space_io->install_readwrite_handler(0x0070, 0x0073, read8_delegate(FUNC(mc146818_device::read), &(*m_rtc)), write8_delegate(FUNC(cs4031_device::rtc_w), this), 0x0000ffff);
- m_space_io->install_readwrite_handler(0x0080, 0x008f, read8_delegate(FUNC(cs4031_device::dma_page_r), this), write8_delegate(FUNC(cs4031_device::dma_page_w), this), 0xffffffff);
- m_space_io->install_readwrite_handler(0x0090, 0x0093, read8_delegate(FUNC(cs4031_device::sysctrl_r), this), write8_delegate(FUNC(cs4031_device::sysctrl_w), this), 0x00ff0000);
- m_space_io->install_readwrite_handler(0x00a0, 0x00a3, read8_delegate(FUNC(pic8259_device::read), &(*m_intc2)), write8_delegate(FUNC(pic8259_device::write), &(*m_intc2)), 0x0000ffff);
- m_space_io->install_readwrite_handler(0x00c0, 0x00df, read8_delegate(FUNC(cs4031_device::dma2_r),this), write8_delegate(FUNC(cs4031_device::dma2_w),this), 0xffffffff);
-}
-
-//-------------------------------------------------
-// device_reset - device-specific reset
-//-------------------------------------------------
-
-void cs4031_device::device_reset()
-{
- // setup default values
- memset(&m_registers, 0x00, sizeof(m_registers));
- m_registers[ROMCS] = 0x60;
-
- // update rom/ram regions below 1mb
- update_read_regions();
- update_write_regions();
-
- // initialize dma controller clocks
- update_dma_clock();
-}
-
-//-------------------------------------------------
-// device_reset_after_children
-//-------------------------------------------------
-
-void cs4031_device::device_reset_after_children()
-{
- // timer 2 default state
- m_ctc->write_gate2(1);
-}
-
-
-//**************************************************************************
-// DMA CONTROLLER
-//**************************************************************************
-
-offs_t cs4031_device::page_offset()
-{
- switch (m_dma_channel)
- {
- case 0: return (offs_t) m_dma_page[0x07] << 16;
- case 1: return (offs_t) m_dma_page[0x03] << 16;
- case 2: return (offs_t) m_dma_page[0x01] << 16;
- case 3: return (offs_t) m_dma_page[0x02] << 16;
- case 5: return (offs_t) m_dma_page[0x0b] << 16;
- case 6: return (offs_t) m_dma_page[0x09] << 16;
- case 7: return (offs_t) m_dma_page[0x0a] << 16;
- }
-
- // should never get here
- return 0xff0000;
-}
-
-READ8_MEMBER( cs4031_device::dma_read_byte )
-{
- if (m_dma_channel == -1)
- return 0xff;
-
- return m_space->read_byte(page_offset() + offset);
-}
-
-WRITE8_MEMBER( cs4031_device::dma_write_byte )
-{
- if (m_dma_channel == -1)
- return;
-
- m_space->write_byte(page_offset() + offset, data);
-}
-
-READ8_MEMBER( cs4031_device::dma_read_word )
-{
- if (m_dma_channel == -1)
- return 0xff;
-
- UINT16 result = m_space->read_word(page_offset() + (offset << 1));
- m_dma_high_byte = result >> 8;
-
- return result;
-}
-
-WRITE8_MEMBER( cs4031_device::dma_write_word )
-{
- if (m_dma_channel == -1)
- return;
-
- m_space->write_word(page_offset() + (offset << 1), (m_dma_high_byte << 8) | data);
-}
-
-WRITE_LINE_MEMBER( cs4031_device::dma2_dack0_w )
-{
- m_dma1->hack_w(state ? 0 : 1); // inverted?
-}
-
-WRITE_LINE_MEMBER( cs4031_device::dma1_eop_w )
-{
- m_dma_eop = state;
- if (m_dma_channel != -1)
- m_write_tc(m_dma_channel, state, 0xff);
-}
-
-void cs4031_device::set_dma_channel(int channel, bool state)
-{
- if (!state)
- {
- m_dma_channel = channel;
- if (m_dma_eop)
- m_write_tc(channel, 1, 0xff);
- }
- else
- {
- if (m_dma_channel == channel)
- {
- m_dma_channel = -1;
- if (m_dma_eop)
- m_write_tc(channel, 0, 0xff);
- }
- }
-}
-
-void cs4031_device::update_dma_clock()
-{
- if (m_dma_clock_divider[m_registers[DMA_CLOCK] & 0x0f] != 0)
- {
- UINT32 dma_clock = clock() / m_dma_clock_divider[m_registers[DMA_CLOCK] & 0x0f];
-
- if (!BIT(m_registers[DMA_WAIT_STATE], 0))
- dma_clock /= 2;
-
- logerror("cs4031_device::update_dma_clock: dma clock is now %u\n", dma_clock);
-
- m_dma1->set_unscaled_clock(dma_clock);
- m_dma2->set_unscaled_clock(dma_clock);
- }
-}
-
-
-//**************************************************************************
-// INTERRUPTS
-//**************************************************************************
-
-/*
- Check NMI sources and generate NMI if needed
-
- Not emulated here: Parity check NMI
- */
-void cs4031_device::nmi()
-{
- if (m_nmi_mask & BIT(m_portb, 6))
- {
- m_write_nmi(1);
- m_write_nmi(0);
- }
-}
-
-READ8_MEMBER( cs4031_device::intc1_slave_ack_r )
-{
- if (offset == 2) // IRQ 2
- return m_intc2->inta_r();
-
- return 0x00;
-}
-
-WRITE_LINE_MEMBER( cs4031_device::rtc_irq_w )
-{
- m_intc2->ir0_w(state ? 0 : 1); // inverted?
-}
-
-WRITE_LINE_MEMBER( cs4031_device::iochck_w )
-{
- if (LOG_IO)
- logerror("cs4031_device::iochck_w: %u\n", state);
-
- if (BIT(m_portb, 3) == 0)
- {
- if (m_iochck && state == 0)
- {
- // set channel check latch
- m_portb |= 1 << 6;
- nmi();
- }
-
- m_iochck = state;
- }
-}
-
-
-//**************************************************************************
-// TIMER
-//**************************************************************************
-
-WRITE_LINE_MEMBER( cs4031_device::ctc_out1_w )
-{
- m_refresh_toggle ^= state;
- m_portb = (m_portb & 0xef) | (m_refresh_toggle << 4);
-}
-
-WRITE_LINE_MEMBER( cs4031_device::ctc_out2_w )
-{
- m_write_spkr(!(state & BIT(m_portb, 1)));
- m_portb = (m_portb & 0xdf) | (state << 5);
-}
-
-
-//**************************************************************************
-// CHIPSET CONFIGURATION
-//**************************************************************************
-
-WRITE8_MEMBER( cs4031_device::config_address_w )
-{
- m_address = data;
- m_address_valid = (m_address < 0x20) ? true : false;
-}
-
-READ8_MEMBER( cs4031_device::config_data_r )
-{
- UINT8 result = 0xff;
-
- if (m_address_valid)
- {
- if (LOG_REGISTER)
- logerror("cs4031_device: read %s = %02x\n", m_register_names[m_address], m_registers[m_address]);
-
- result = m_registers[m_address];
- }
-
- // after a read the selected address needs to be reset
- m_address_valid = false;
-
- return result;
-}
-
-WRITE8_MEMBER( cs4031_device::config_data_w )
-{
- if (m_address_valid)
- {
- if (LOG_REGISTER)
- logerror("cs4031_device: write %s = %02x\n", m_register_names[m_address], data);
-
- // update register with new data
- m_registers[m_address] = data;
-
- // execute command
- switch (m_address)
- {
- case DMA_WAIT_STATE:
- update_dma_clock();
- break;
-
- case 0x05: break;
- case 0x06: break;
- case 0x07: break;
- case 0x08: break;
- case 0x09: break;
-
- case DMA_CLOCK:
- update_dma_clock();
- break;
-
- case 0x10: break;
- case 0x11: break;
- case 0x12: break;
- case 0x13: break;
- case 0x14: break;
- case 0x15: break;
- case 0x16: break;
- case 0x17: break;
- case 0x18: break;
-
- case SHADOW_READ:
- update_read_regions();
- break;
-
- case SHADOW_WRITE:
- update_write_regions();
- break;
-
- case ROMCS:
- update_read_regions();
- update_write_regions();
- break;
-
- case SOFT_RESET_AND_GATEA20:
- a20m();
- break;
- }
- }
-
- // after a write the selected address needs to be reset
- m_address_valid = false;
-}
-
-
-//**************************************************************************
-// MEMORY MAPPER
-//**************************************************************************
-
-void cs4031_device::update_read_region(int index, const char *region, offs_t start, offs_t end)
-{
- if (!BIT(m_registers[SHADOW_READ], index) && BIT(m_registers[ROMCS], index))
- {
- if (LOG_MEMORY)
- logerror("ROM read from %x to %x\n", start, end);
-
- m_space->install_read_bank(start, end, region);
- machine().root_device().membank(region)->set_base(m_bios + start);
- }
- else if (!BIT(m_registers[SHADOW_READ], index) && !BIT(m_registers[ROMCS], index))
- {
- if (LOG_MEMORY)
- logerror("ISA read from %x to %x\n", start, end);
-
- m_space->install_read_bank(start, end, region);
- machine().root_device().membank(region)->set_base(m_isa + start - 0xc0000);
- }
- else if (BIT(m_registers[SHADOW_READ], index))
- {
- if (LOG_MEMORY)
- logerror("RAM read from %x to %x\n", start, end);
-
- m_space->install_read_bank(start, end, region);
- machine().root_device().membank(region)->set_base(m_ram + start);
- }
- else
- {
- if (LOG_MEMORY)
- logerror("NOP read from %x to %x\n", start, end);
-
- m_space->nop_read(start, end);
- }
-}
-
-void cs4031_device::update_write_region(int index, const char *region, offs_t start, offs_t end)
-{
- if (!BIT(m_registers[SHADOW_WRITE], index) && BIT(m_registers[ROMCS], index) && BIT(m_registers[ROMCS], 7))
- {
- if (LOG_MEMORY)
- logerror("ROM write from %x to %x\n", start, end);
-
- m_space->install_write_bank(start, end, region);
- machine().root_device().membank(region)->set_base(m_bios + start);
- }
- else if (!BIT(m_registers[SHADOW_WRITE], index) && !BIT(m_registers[ROMCS], index))
- {
- if (LOG_MEMORY)
- logerror("ISA write from %x to %x\n", start, end);
-
- m_space->install_write_bank(start, end, region);
- machine().root_device().membank(region)->set_base(m_isa + start - 0xc0000);
- }
- else if (BIT(m_registers[SHADOW_WRITE], index))
- {
- if (LOG_MEMORY)
- logerror("RAM write from %x to %x\n", start, end);
-
- m_space->install_write_bank(start, end, region);
- machine().root_device().membank(region)->set_base(m_ram + start);
- }
- else
- {
- if (LOG_MEMORY)
- logerror("NOP write from %x to %x\n", start, end);
-
- m_space->nop_write(start, end);
- }
-}
-
-void cs4031_device::update_read_regions()
-{
- update_read_region(0, "read_c0000", 0xc0000, 0xc3fff);
- update_read_region(1, "read_c4000", 0xc4000, 0xc7fff);
- update_read_region(2, "read_c8000", 0xc8000, 0xcbfff);
- update_read_region(3, "read_cc000", 0xcc000, 0xcffff);
- update_read_region(4, "read_d0000", 0xd0000, 0xdffff);
- update_read_region(5, "read_e0000", 0xe0000, 0xeffff);
- update_read_region(6, "read_f0000", 0xf0000, 0xfffff);
-}
-
-void cs4031_device::update_write_regions()
-{
- update_write_region(0, "write_c0000", 0xc0000, 0xc3fff);
- update_write_region(1, "write_c4000", 0xc4000, 0xc7fff);
- update_write_region(2, "write_c8000", 0xc8000, 0xcbfff);
- update_write_region(3, "write_cc000", 0xcc000, 0xcffff);
- update_write_region(4, "write_d0000", 0xd0000, 0xdffff);
- update_write_region(5, "write_e0000", 0xe0000, 0xeffff);
- update_write_region(6, "write_f0000", 0xf0000, 0xfffff);
-}
-
-
-//**************************************************************************
-// KEYBOARD / 8042
-//**************************************************************************
-
-void cs4031_device::a20m()
-{
- // external signal is ignored when emulation is on
- if (BIT(m_registers[SOFT_RESET_AND_GATEA20], 5))
- m_write_a20m(m_fast_gatea20 | m_emu_gatea20);
- else
- m_write_a20m(m_fast_gatea20 | m_ext_gatea20);
-}
-
-void cs4031_device::emulated_kbreset(int state)
-{
- if (BIT(m_registers[SOFT_RESET_AND_GATEA20], 4))
- {
- // kbreset (input) is active low
- // cpureset (output) is active high
- m_write_cpureset(!state);
- }
-}
-
-void cs4031_device::emulated_gatea20(int state)
-{
- if (BIT(m_registers[SOFT_RESET_AND_GATEA20], 5))
- {
- m_emu_gatea20 = state;
- a20m();
- }
-}
-
-void cs4031_device::fast_gatea20(int state)
-{
- m_fast_gatea20 = state;
- a20m();
-}
-
-void cs4031_device::keyboard_gatea20(int state)
-{
- m_ext_gatea20 = state;
- a20m();
-}
-
-READ8_MEMBER( cs4031_device::keyb_status_r )
-{
- if (LOG_KEYBOARD)
- logerror("cs4031_device::keyb_status_r\n");
-
- return m_keybc->status_r(space, 0);
-}
-
-WRITE8_MEMBER( cs4031_device::keyb_command_blocked_w )
-{
- // command is optionally blocked
- if (!BIT(m_registers[SOFT_RESET_AND_GATEA20], 7))
- m_keybc->command_w(space, 0, data);
-}
-
-WRITE8_MEMBER( cs4031_device::keyb_command_w )
-{
- if (LOG_KEYBOARD)
- logerror("cs4031_device::keyb_command_w: %02x\n", data);
-
- m_keybc_d1_written = false;
-
- switch (data)
- {
- // self-test
- case 0xaa:
- emulated_kbreset(1);
- emulated_gatea20(1);
-
- // self-test is never blocked
- m_keybc->command_w(space, 0, data);
- break;
-
- case 0xd1:
- m_keybc_d1_written = true;
- keyb_command_blocked_w(space, 0, data);
- break;
-
- case 0xf0:
- case 0xf1:
- case 0xf2:
- case 0xf4:
- case 0xf5:
- case 0xf6:
- case 0xf8:
- case 0xf9:
- case 0xfa:
- case 0xfc:
- case 0xfd:
- case 0xfe:
- // toggle keyboard reset?
- if (!BIT(data, 0))
- {
- emulated_kbreset(0);
- emulated_kbreset(1);
- }
-
- // toggle gatea20?
- if (!BIT(data, 1))
- {
- emulated_gatea20(0);
- emulated_gatea20(1);
- }
-
- keyb_command_blocked_w(space, 0, data);
-
- break;
-
- case 0xff:
- // last data write was blocked?
- if (m_keybc_data_blocked)
- {
- m_keybc_data_blocked = false;
- keyb_command_blocked_w(space, 0, data);
- }
- else
- m_keybc->command_w(space, 0, data);
-
- break;
-
- // everything else goes directly to the keyboard controller
- default:
- m_keybc->command_w(space, 0, data);
- break;
- }
-}
-
-READ8_MEMBER( cs4031_device::keyb_data_r )
-{
- if (LOG_KEYBOARD)
- logerror("cs4031_device::keyb_data_r\n");
-
- return m_keybc->data_r(space, 0);
-}
-
-WRITE8_MEMBER( cs4031_device::keyb_data_w )
-{
- if (LOG_KEYBOARD)
- logerror("cs4031_device::keyb_data_w: %02x\n", data);
-
- // data is blocked only for d1 command
- if (BIT(m_registers[SOFT_RESET_AND_GATEA20], 7) && m_keybc_d1_written)
- {
- m_keybc_data_blocked = true;
- emulated_kbreset(BIT(data, 0));
- emulated_gatea20(BIT(data, 1));
- }
- else
- {
- m_keybc_data_blocked = false;
- m_keybc->data_w(space, 0, data);
- }
-}
-
-WRITE_LINE_MEMBER( cs4031_device::gatea20_w )
-{
- if (LOG_KEYBOARD)
- logerror("cs4031_device::gatea20_w: %u\n", state);
-
- keyboard_gatea20(state);
-}
-
-WRITE_LINE_MEMBER( cs4031_device::kbrst_w )
-{
- if (LOG_KEYBOARD)
- logerror("cs4031_device::kbrst_w: %u\n", state);
-
- // convert to active low signal (gets inverted in at_keybc.c)
- state = (state == ASSERT_LINE ? 0 : 1);
-
- // external kbreset is ignored when emulation enabled
- if (!BIT(m_registers[SOFT_RESET_AND_GATEA20], 4))
- {
- // detect transition
- if (m_kbrst == 1 && state == 0)
- {
- m_write_cpureset(1);
- m_write_cpureset(0);
- }
- }
-
- m_kbrst = state;
-}
-
-/*
- Fast CPU reset and Gate A20
-
- 0 - Fast CPU reset
- 1 - Fast Gate A20
-
- */
-WRITE8_MEMBER( cs4031_device::sysctrl_w )
-{
- if (LOG_IO)
- logerror("cs4031_device::sysctrl_w: %u\n", data);
-
- fast_gatea20(BIT(data, 1));
-
- if (m_cpureset == 0 && BIT(data, 0))
- {
- // pulse reset line
- m_write_cpureset(1);
- m_write_cpureset(0);
- }
-
- m_cpureset = BIT(data, 0);
-}
-
-READ8_MEMBER( cs4031_device::sysctrl_r )
-{
- UINT8 result = 0; // reserved bits read as 0?
-
- result |= m_cpureset << 0;
- result |= m_fast_gatea20 << 1;
-
- if (LOG_IO)
- logerror("cs4031_device::sysctrl_r: %u\n", result);
-
- return result;
-}
-
-
-//**************************************************************************
-// MISCELLANEOUS
-//**************************************************************************
-
-/*
- "Port B" - AT-compatible port with miscellaneous information
-
- 0 - Timer 2 gate (rw)
- 1 - Speaker data (rw)
- 2 - Enable parity check (rw) [not emulated]
- 3 - Enable IOCHECK (rw)
- 4 - Refresh detect (r)
- 5 - Timer 2 output (r)
- 6 - Channel check latch (r)
- 7 - Parity check latch (r) [not emulated]
-*/
-
-READ8_MEMBER( cs4031_device::portb_r )
-{
- if (0)
- logerror("cs4031_device::portb_r: %02x\n", m_portb);
-
- return m_portb;
-}
-
-WRITE8_MEMBER( cs4031_device::portb_w )
-{
- if (0)
- logerror("cs4031_device::portb_w: %02x\n", data);
-
- m_portb = (m_portb & 0xf0) | (data & 0x0f);
-
- // bit 5 forced to 1 if timer disabled
- if (!BIT(m_portb, 0))
- m_portb |= 1 << 5;
-
- m_ctc->write_gate2(BIT(m_portb, 0));
-
- m_write_spkr(!BIT(m_portb, 1));
-
- // clear channel check latch?
- if (BIT(m_portb, 3))
- m_portb &= 0xbf;
-}
-
-/*
- NMI mask and RTC address
-
- 7 - NMI mask
- 6:0 - RTC address
- */
-WRITE8_MEMBER( cs4031_device::rtc_w )
-{
- if (0)
- logerror("cs4031_device::rtc_w: %02x\n", data);
-
- if (offset == 0)
- {
- m_nmi_mask = !BIT(data, 7);
- data &= 0x7f;
- }
-
- m_rtc->write(space, offset, data);
-}
diff --git a/src/mess/machine/cs4031.h b/src/mess/machine/cs4031.h
deleted file mode 100644
index 9d1a95e6c14..00000000000
--- a/src/mess/machine/cs4031.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/***************************************************************************
-
- Chips & Technologies CS4031 chipset
-
- license: MAME, GPL-2.0+
- copyright-holders: Dirk Best
-
- Chipset for 486 based PC/AT compatible systems. Consists of two
- individual chips:
-
- * F84031
- - DRAM controller
- - ISA-bus controller
- - VESA VL-BUS controller
-
- * F84035 (82C206 IPC core)
- - 2x 8257 DMA controller
- - 2x 8259 interrupt controller
- - 8254 timer
- - MC14818 RTC
-
-***************************************************************************/
-
-#pragma once
-
-#ifndef __CS4031_H__
-#define __CS4031_H__
-
-#include "emu.h"
-#include "machine/am9517a.h"
-#include "machine/pic8259.h"
-#include "machine/pit8253.h"
-#include "machine/ds128x.h"
-#include "machine/at_keybc.h"
-
-
-//**************************************************************************
-// INTERFACE CONFIGURATION MACROS
-//**************************************************************************
-
-#define MCFG_CS4031_ADD(_tag, _clock, _cputag, _isatag, _biostag, _keybctag) \
- MCFG_DEVICE_ADD(_tag, CS4031, _clock) \
- cs4031_device::static_set_cputag(*device, _cputag); \
- cs4031_device::static_set_isatag(*device, _isatag); \
- cs4031_device::static_set_biostag(*device, _biostag); \
- cs4031_device::static_set_keybctag(*device, _keybctag);
-
-#define MCFG_CS4031_IOR(_ior) \
- downcast<cs4031_device *>(device)->set_ior_callback(DEVCB2_##_ior);
-
-#define MCFG_CS4031_IOW(_iow) \
- downcast<cs4031_device *>(device)->set_iow_callback(DEVCB2_##_iow);
-
-#define MCFG_CS4031_TC(_tc) \
- downcast<cs4031_device *>(device)->set_tc_callback(DEVCB2_##_tc);
-
-#define MCFG_CS4031_HOLD(_hold) \
- downcast<cs4031_device *>(device)->set_hold_callback(DEVCB2_##_hold);
-
-#define MCFG_CS4031_NMI(_nmi) \
- downcast<cs4031_device *>(device)->set_nmi_callback(DEVCB2_##_nmi);
-
-#define MCFG_CS4031_INTR(_intr) \
- downcast<cs4031_device *>(device)->set_intr_callback(DEVCB2_##_intr);
-
-#define MCFG_CS4031_CPURESET(_cpureset) \
- downcast<cs4031_device *>(device)->set_cpureset_callback(DEVCB2_##_cpureset);
-
-#define MCFG_CS4031_A20M(_a20m) \
- downcast<cs4031_device *>(device)->set_a20m_callback(DEVCB2_##_a20m);
-
-#define MCFG_CS4031_SPKR(_spkr) \
- downcast<cs4031_device *>(device)->set_spkr_callback(DEVCB2_##_spkr);
-
-
-//**************************************************************************
-// TYPE DEFINITIONS
-//**************************************************************************
-
-// ======================> cs4031_device
-
-class cs4031_device : public device_t
-{
-public:
- // construction/destruction
- cs4031_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- // optional information overrides
- virtual machine_config_constructor device_mconfig_additions() const;
-
- // callbacks
- template<class _ior> void set_ior_callback(_ior ior) { m_read_ior.set_callback(ior); }
- template<class _iow> void set_iow_callback(_iow iow) { m_write_iow.set_callback(iow); }
- template<class _tc> void set_tc_callback(_tc tc) { m_write_tc.set_callback(tc); }
- template<class _hold> void set_hold_callback(_hold hold) { m_write_hold.set_callback(hold); }
- template<class _cpureset> void set_cpureset_callback(_cpureset cpureset) { m_write_cpureset.set_callback(cpureset); }
- template<class _nmi> void set_nmi_callback(_nmi nmi) { m_write_nmi.set_callback(nmi); }
- template<class _intr> void set_intr_callback(_intr intr) { m_write_intr.set_callback(intr); }
- template<class _a20m> void set_a20m_callback(_a20m a20m) { m_write_a20m.set_callback(a20m); }
- template<class _spkr> void set_spkr_callback(_spkr spkr) { m_write_spkr.set_callback(spkr); }
-
- // not really public
- DECLARE_READ8_MEMBER( dma_read_byte );
- DECLARE_WRITE8_MEMBER( dma_write_byte );
- DECLARE_READ8_MEMBER( dma_read_word );
- DECLARE_WRITE8_MEMBER( dma_write_word );
- DECLARE_WRITE_LINE_MEMBER( dma1_eop_w );
- DECLARE_READ8_MEMBER( dma1_ior0_r ) { return m_read_ior(0); }
- DECLARE_READ8_MEMBER( dma1_ior1_r ) { return m_read_ior(1); }
- DECLARE_READ8_MEMBER( dma1_ior2_r ) { return m_read_ior(2); }
- DECLARE_READ8_MEMBER( dma1_ior3_r ) { return m_read_ior(3); }
- DECLARE_READ8_MEMBER( dma2_ior1_r ) { UINT16 result = m_read_ior(5); m_dma_high_byte = result >> 8; return result; }
- DECLARE_READ8_MEMBER( dma2_ior2_r ) { UINT16 result = m_read_ior(6); m_dma_high_byte = result >> 8; return result; }
- DECLARE_READ8_MEMBER( dma2_ior3_r ) { UINT16 result = m_read_ior(7); m_dma_high_byte = result >> 8; return result; }
- DECLARE_WRITE8_MEMBER( dma1_iow0_w ) { m_write_iow(0, data, 0xffff); }
- DECLARE_WRITE8_MEMBER( dma1_iow1_w ) { m_write_iow(1, data, 0xffff); }
- DECLARE_WRITE8_MEMBER( dma1_iow2_w ) { m_write_iow(2, data, 0xffff); }
- DECLARE_WRITE8_MEMBER( dma1_iow3_w ) { m_write_iow(3, data, 0xffff); }
- DECLARE_WRITE8_MEMBER( dma2_iow1_w ) { m_write_iow(5, (m_dma_high_byte << 8) | data, 0xffff); }
- DECLARE_WRITE8_MEMBER( dma2_iow2_w ) { m_write_iow(6, (m_dma_high_byte << 8) | data, 0xffff); }
- DECLARE_WRITE8_MEMBER( dma2_iow3_w ) { m_write_iow(7, (m_dma_high_byte << 8) | data, 0xffff); }
- DECLARE_WRITE_LINE_MEMBER( dma1_dack0_w ) { set_dma_channel(0, state); }
- DECLARE_WRITE_LINE_MEMBER( dma1_dack1_w ) { set_dma_channel(1, state); }
- DECLARE_WRITE_LINE_MEMBER( dma1_dack2_w ) { set_dma_channel(2, state); }
- DECLARE_WRITE_LINE_MEMBER( dma1_dack3_w ) { set_dma_channel(3, state); }
- DECLARE_WRITE_LINE_MEMBER( dma2_dack0_w );
- DECLARE_WRITE_LINE_MEMBER( dma2_dack1_w ) { set_dma_channel(5, state); }
- DECLARE_WRITE_LINE_MEMBER( dma2_dack2_w ) { set_dma_channel(6, state); }
- DECLARE_WRITE_LINE_MEMBER( dma2_dack3_w ) { set_dma_channel(7, state); }
- DECLARE_WRITE_LINE_MEMBER( dma2_hreq_w ) { m_write_hold(state); }
- DECLARE_WRITE_LINE_MEMBER( intc1_int_w ) { m_write_intr(state); }
- DECLARE_READ8_MEMBER( intc1_slave_ack_r );
- DECLARE_WRITE_LINE_MEMBER( ctc_out1_w );
- DECLARE_WRITE_LINE_MEMBER( ctc_out2_w );
- DECLARE_WRITE_LINE_MEMBER( rtc_irq_w );
-
- // internal io
- DECLARE_WRITE8_MEMBER( config_address_w );
- DECLARE_READ8_MEMBER( config_data_r );
- DECLARE_WRITE8_MEMBER( config_data_w );
- DECLARE_READ8_MEMBER( portb_r );
- DECLARE_WRITE8_MEMBER( portb_w );
- DECLARE_WRITE8_MEMBER( rtc_w );
- DECLARE_WRITE8_MEMBER( sysctrl_w );
- DECLARE_READ8_MEMBER( sysctrl_r );
- DECLARE_READ8_MEMBER( dma_page_r ) { return m_dma_page[offset]; }
- DECLARE_WRITE8_MEMBER( dma_page_w ) { m_dma_page[offset] = data; }
- DECLARE_READ8_MEMBER( dma2_r ) { return m_dma2->read(space, offset / 2); }
- DECLARE_WRITE8_MEMBER( dma2_w ) { m_dma2->write(space, offset / 2, data); }
- DECLARE_READ8_MEMBER( keyb_data_r );
- DECLARE_WRITE8_MEMBER( keyb_data_w );
- DECLARE_READ8_MEMBER( keyb_status_r );
- DECLARE_WRITE8_MEMBER( keyb_command_w );
- DECLARE_WRITE8_MEMBER( keyb_command_blocked_w );
-
- // input lines
- DECLARE_WRITE_LINE_MEMBER( irq01_w ) { m_intc1->ir1_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq03_w ) { m_intc1->ir3_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq04_w ) { m_intc1->ir4_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq05_w ) { m_intc1->ir5_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq06_w ) { m_intc1->ir6_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq07_w ) { m_intc1->ir7_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq09_w ) { m_intc2->ir1_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq10_w ) { m_intc2->ir2_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq11_w ) { m_intc2->ir3_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq12_w ) { m_intc2->ir4_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq13_w ) { m_intc2->ir5_w(state); } // also FERR#
- DECLARE_WRITE_LINE_MEMBER( irq14_w ) { m_intc2->ir6_w(state); }
- DECLARE_WRITE_LINE_MEMBER( irq15_w ) { m_intc2->ir7_w(state); }
- DECLARE_WRITE_LINE_MEMBER( dreq0_w ) { m_dma1->dreq0_w(state); }
- DECLARE_WRITE_LINE_MEMBER( dreq1_w ) { m_dma1->dreq1_w(state); }
- DECLARE_WRITE_LINE_MEMBER( dreq2_w ) { m_dma1->dreq2_w(state); }
- DECLARE_WRITE_LINE_MEMBER( dreq3_w ) { m_dma1->dreq3_w(state); }
- DECLARE_WRITE_LINE_MEMBER( dreq5_w ) { m_dma2->dreq1_w(state); }
- DECLARE_WRITE_LINE_MEMBER( dreq6_w ) { m_dma2->dreq2_w(state); }
- DECLARE_WRITE_LINE_MEMBER( dreq7_w ) { m_dma2->dreq3_w(state); }
- DECLARE_WRITE_LINE_MEMBER( hlda_w ) { m_dma2->hack_w(state); }
- DECLARE_WRITE_LINE_MEMBER( iochck_w );
- DECLARE_WRITE_LINE_MEMBER( gatea20_w );
- DECLARE_WRITE_LINE_MEMBER( kbrst_w );
-
- UINT8 int_ack_r() { return m_intc1->inta_r(); }
-
- // inline configuration
- static void static_set_cputag(device_t &device, const char *tag);
- static void static_set_isatag(device_t &device, const char *tag);
- static void static_set_biostag(device_t &device, const char *tag);
- static void static_set_keybctag(device_t &device, const char *tag);
-
-protected:
- // device-level overrides
- virtual void device_start();
- virtual void device_reset();
- virtual void device_reset_after_children();
-
-private:
- devcb2_read16 m_read_ior;
- devcb2_write16 m_write_iow;
- devcb2_write8 m_write_tc;
- devcb2_write_line m_write_hold;
- devcb2_write_line m_write_nmi;
- devcb2_write_line m_write_intr;
- devcb2_write_line m_write_cpureset;
- devcb2_write_line m_write_a20m;
- devcb2_write_line m_write_spkr;
-
- offs_t page_offset();
- void set_dma_channel(int channel, bool state);
- void update_dma_clock();
-
- void nmi();
- void a20m();
-
- void emulated_kbreset(int state);
- void emulated_gatea20(int state);
- void fast_gatea20(int state);
- void keyboard_gatea20(int state);
-
- void update_read_region(int index, const char *region, offs_t start, offs_t end);
- void update_write_region(int index, const char *region, offs_t start, offs_t end);
- void update_read_regions();
- void update_write_regions();
-
- // internal state
- const char *m_cputag;
- const char *m_isatag;
- const char *m_biostag;
- const char *m_keybctag;
-
- address_space *m_space;
- address_space *m_space_io;
- UINT8 *m_isa;
- UINT8 *m_bios;
- UINT8 *m_ram;
-
- // ipc core devices
- required_device<am9517a_device> m_dma1;
- required_device<am9517a_device> m_dma2;
- required_device<pic8259_device> m_intc1;
- required_device<pic8259_device> m_intc2;
- required_device<pit8254_device> m_ctc;
- required_device<ds12885_device> m_rtc;
-
- int m_dma_eop;
- UINT8 m_dma_page[0x10];
- UINT8 m_dma_high_byte;
- int m_dma_channel;
-
- UINT8 m_portb;
- int m_refresh_toggle;
- int m_iochck;
- int m_nmi_mask;
-
- // keyboard
- at_keyboard_controller_device *m_keybc;
- int m_cpureset;
- int m_kbrst;
- int m_ext_gatea20;
- int m_fast_gatea20;
- int m_emu_gatea20;
- bool m_keybc_d1_written;
- bool m_keybc_data_blocked;
-
- // chipset configuration
- static const char* m_register_names[];
- static const float m_dma_clock_divider[];
-
- enum
- {
- DMA_WAIT_STATE = 0x01,
- PERFORMANCE = 0x08,
- F84035_MISC = 0x09,
- DMA_CLOCK = 0x0a,
- SHADOW_READ = 0x19,
- SHADOW_WRITE = 0x1a,
- ROMCS = 0x1b,
- SOFT_RESET_AND_GATEA20 = 0x1c
- };
-
- UINT8 m_address;
- bool m_address_valid;
-
- UINT8 m_registers[0x20];
-};
-
-
-// device type definition
-extern const device_type CS4031;
-
-
-#endif /* __CS4031_H__ */
diff --git a/src/mess/machine/cs8221.c b/src/mess/machine/cs8221.c
deleted file mode 100644
index f62c1280ed3..00000000000
--- a/src/mess/machine/cs8221.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/***************************************************************************
-
- Chips & Technologies CS8221 chipset
-
- a.k.a. NEW ENHANCED AT (NEAT)
-
- Consists of four individual chips:
-
- * 82C211 - CPU/Bus controller
- * 82C212 - Page/Interleave and EMS Memory controller
- * 82C215 - Data/Address buffer
- * 82C206 - Integrated Peripherals Controller(IPC)
-
-***************************************************************************/
-
-#include "emu.h"
-#include "machine/ram.h"
-#include "machine/cs8221.h"
-
-
-//**************************************************************************
-// GLOBAL VARIABLES
-//**************************************************************************
-
-#define LOG_REGISTER 1
-#define LOG_MEMORY 1
-
-const device_type CS8221 = &device_creator<cs8221_device>;
-
-
-static const char *const register_names[] =
-{
- /* 00 */ "PROCCLK",
- /* 01 */ "COMMAND DELAY",
- /* 02 */ "WAIT STATES",
- /* 03 */ "RESERVED",
- /* 04 */ "VERSION",
- /* 05 */ "ROM CONFIGURATION",
- /* 06 */ "MEMORY ENABLE-1",
- /* 07 */ "MEMORY ENABLE-2",
- /* 08 */ "MEMORY ENABLE-3",
- /* 09 */ "MEMORY ENABLE-4",
- /* 0a */ "BANK 0/1 ENABLE",
- /* 0b */ "DRAM CONFIGURATION",
- /* 0c */ "BANK 2/3 ENABLE",
- /* 0d */ "EMS BASE ADDRESS",
- /* 0e */ "EMS ADDRESS EXTENSION",
- /* 0f */ "MISCELLANEOUS"
-};
-
-//**************************************************************************
-// LIVE DEVICE
-//**************************************************************************
-
-//-------------------------------------------------
-// cs8221_device - constructor
-//-------------------------------------------------
-
-cs8221_device::cs8221_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, CS8221, "CS8221", tag, owner, clock, "cs8221", __FILE__),
- m_address(0),
- m_address_valid(false)
-{
-}
-
-void cs8221_device::static_set_cputag(device_t &device, const char *tag)
-{
- cs8221_device &cs8221 = downcast<cs8221_device &>(device);
- cs8221.m_cputag = tag;
-}
-
-void cs8221_device::static_set_isatag(device_t &device, const char *tag)
-{
- cs8221_device &cs8221 = downcast<cs8221_device &>(device);
- cs8221.m_isatag = tag;
-}
-
-void cs8221_device::static_set_biostag(device_t &device, const char *tag)
-{
- cs8221_device &cs8221 = downcast<cs8221_device &>(device);
- cs8221.m_biostag = tag;
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void cs8221_device::device_start()
-{
-}
-
-//-------------------------------------------------
-// device_reset - device-specific reset
-//-------------------------------------------------
-
-void cs8221_device::device_reset()
-{
- // setup default values
- memset(&m_registers, 0x00, sizeof(m_registers));
-}
-
-
-//**************************************************************************
-// READ/WRITE HANDLERS
-//**************************************************************************
-
-WRITE8_MEMBER( cs8221_device::address_w )
-{
- m_address = data;
- m_address_valid = ((m_address & 0x60)== 0x60) ? true : false;
-}
-
-READ8_MEMBER( cs8221_device::data_r )
-{
- UINT8 result = 0xff;
-
- if (m_address_valid)
- {
- if (LOG_REGISTER)
- logerror("cs8221_device: read %s = %02x\n", register_names[m_address & 0x0f], m_registers[m_address & 0x0f]);
-
- result = m_registers[m_address & 0x0f];
- }
-
- // after a read the selected address needs to be reset
- m_address_valid = false;
-
- return result;
-}
-
-WRITE8_MEMBER( cs8221_device::data_w )
-{
- if (m_address_valid)
- {
- if (LOG_REGISTER)
- logerror("cs8221_device: write %s = %02x\n", register_names[m_address & 0x0f], data);
-
- // update register with new data
- m_registers[m_address & 0x0f] = data;
-
- // execute command
- switch (m_address)
- {
- case 0x60: break;
- case 0x61: break;
- case 0x62: break;
- case 0x63: break;
- case 0x64: break;
- case 0x65: break;
- case 0x66: break;
- case 0x67: break;
- case 0x68: break;
- case 0x69: break;
- case 0x6a: break;
- case 0x6b: break;
- case 0x6c: break;
- case 0x6d: break;
- case 0x6e: break;
- case 0x6f: break;
- }
- }
-
- // after a write the selected address needs to be reset
- m_address_valid = false;
-}
diff --git a/src/mess/machine/cs8221.h b/src/mess/machine/cs8221.h
deleted file mode 100644
index 33934b0e3a8..00000000000
--- a/src/mess/machine/cs8221.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/***************************************************************************
-
- Chips & Technologies CS8221 chipset
-
- a.k.a. NEW ENHANCED AT (NEAT)
-
- Consists of four individual chips:
-
- * 82C211 - CPU/Bus controller
- * 82C212 - Page/Interleave and EMS Memory controller
- * 82C215 - Data/Address buffer
- * 82C206 - Integrated Peripherals Controller(IPC)
-
-***************************************************************************/
-
-#pragma once
-
-#ifndef __CS8221_H__
-#define __CS8221_H__
-
-#include "emu.h"
-
-
-//**************************************************************************
-// INTERFACE CONFIGURATION MACROS
-//**************************************************************************
-
-#define MCFG_CS8221_ADD(_tag, _cputag, _isatag, _biostag) \
- MCFG_DEVICE_ADD(_tag, CS8221, 0) \
- cs8221_device::static_set_cputag(*device, _cputag); \
- cs8221_device::static_set_isatag(*device, _isatag); \
- cs8221_device::static_set_biostag(*device, _biostag);
-
-
-//**************************************************************************
-// TYPE DEFINITIONS
-//**************************************************************************
-
-// ======================> cs8221_device
-
-class cs8221_device : public device_t
-{
-public:
- // construction/destruction
- cs8221_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- DECLARE_WRITE8_MEMBER( address_w );
- DECLARE_READ8_MEMBER( data_r );
- DECLARE_WRITE8_MEMBER( data_w );
-
- // inline configuration
- static void static_set_cputag(device_t &device, const char *tag);
- static void static_set_isatag(device_t &device, const char *tag);
- static void static_set_biostag(device_t &device, const char *tag);
-
-protected:
- // device-level overrides
- virtual void device_start();
- virtual void device_reset();
-
-private:
-
- // internal state
- //address_space *m_space;
- //UINT8 *m_isa;
- //UINT8 *m_bios;
- //UINT8 *m_ram;
-
- // address selection
- UINT8 m_address;
- bool m_address_valid;
-
- const char *m_cputag;
- const char *m_isatag;
- const char *m_biostag;
-
-
- UINT8 m_registers[0x10];
-};
-
-
-// device type definition
-extern const device_type CS8221;
-
-
-#endif /* __CS8221_H__ */
diff --git a/src/mess/machine/hd63450.c b/src/mess/machine/hd63450.c
deleted file mode 100644
index c39a39d2919..00000000000
--- a/src/mess/machine/hd63450.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- Hitachi HD63450 DMA Controller
-
- Largely based on documentation of the Sharp X68000
-*/
-
-#include "hd63450.h"
-#include "devlegcy.h"
-
-struct hd63450_regs
-{ // offsets in bytes
- unsigned char csr; // [00] Channel status register (R/W)
- unsigned char cer; // [01] Channel error register (R)
- unsigned char dcr; // [04] Device control register (R/W)
- unsigned char ocr; // [05] Operation control register (R/W)
- unsigned char scr; // [06] Sequence control register (R/W)
- unsigned char ccr; // [07] Channel control register (R/W)
- unsigned short mtc; // [0a,0b] Memory Transfer Counter (R/W)
- unsigned long mar; // [0c-0f] Memory Address Register (R/W)
- unsigned long dar; // [14-17] Device Address Register (R/W)
- unsigned short btc; // [1a,1b] Base Transfer Counter (R/W)
- unsigned long bar; // [1c-1f] Base Address Register (R/W)
- unsigned char niv; // [25] Normal Interrupt Vector (R/W)
- unsigned char eiv; // [27] Error Interrupt Vector (R/W)
- unsigned char mfc; // [29] Memory Function Code (R/W)
- unsigned char cpr; // [2d] Channel Priority Register (R/W)
- unsigned char dfc; // [31] Device Function Code (R/W)
- unsigned char bfc; // [39] Base Function Code (R/W)
- unsigned char gcr; // [3f] General Control Register (R/W)
-};
-
-struct hd63450_t
-{
- hd63450_regs reg[4];
- emu_timer* timer[4]; // for timing data reading/writing each channel
- attotime clock[4];
- attotime burst_clock[4];
- int in_progress[4]; // if a channel is in use
- int transfer_size[4];
- int halted[4]; // non-zero if a channel has been halted, and can be continued later.
- const hd63450_intf* intf;
-};
-
-static TIMER_CALLBACK(dma_transfer_timer);
-static void dma_transfer_abort(device_t* device, int channel);
-static void dma_transfer_halt(device_t* device, int channel);
-static void dma_transfer_continue(device_t* device, int channel);
-static void dma_transfer_start(device_t* device, int channel, int dir);
-
-INLINE hd63450_t *get_safe_token(device_t *device)
-{
- assert(device != NULL);
- assert(device->type() == HD63450);
-
- return (hd63450_t *)downcast<hd63450_device *>(device)->token();
-}
-
-static DEVICE_START(hd63450)
-{
- hd63450_t* dmac = get_safe_token(device);
- int x;
-
- dmac->intf = (const hd63450_intf*)device->static_config();
-
- // Initialise timers and registers
- for(x=0;x<4;x++)
- {
- dmac->timer[x] = device->machine().scheduler().timer_alloc(FUNC(dma_transfer_timer), (void*)device);
- dmac->reg[x].niv = 0x0f; // defaults?
- dmac->reg[x].eiv = 0x0f;
- dmac->clock[x] = dmac->intf->clock[x];
- dmac->burst_clock[x] = dmac->intf->burst_clock[x];
- }
-}
-
-int hd63450_read(device_t* device, int offset, UINT16 mem_mask)
-{
- int channel,reg;
- hd63450_t* dmac = get_safe_token(device);
-
- channel = (offset & 0x60) >> 5;
- reg = offset & 0x1f;
-
- switch(reg)
- {
- case 0x00: // CSR / CER
- return (dmac->reg[channel].csr << 8) | dmac->reg[channel].cer;
- case 0x02: // DCR / OCR
- return (dmac->reg[channel].dcr << 8) | dmac->reg[channel].ocr;
- case 0x03: // SCR / CCR
- return (dmac->reg[channel].scr << 8) | dmac->reg[channel].ccr;
- case 0x05: // MTC
- return dmac->reg[channel].mtc;
- case 0x06: // MAR (high)
- return (dmac->reg[channel].mar & 0xffff0000) >> 16;
- case 0x07: // MAR (low)
- return (dmac->reg[channel].mar & 0x0000ffff);
- case 0x0a: // DAR (high)
- return (dmac->reg[channel].dar & 0xffff0000) >> 16;
- case 0x0b: // DAR (low)
- return (dmac->reg[channel].dar & 0x0000ffff);
- case 0x0d: // BTC
- return dmac->reg[channel].btc;
- case 0x0e: // BAR (high)
- return (dmac->reg[channel].bar & 0xffff0000) >> 16;
- case 0x0f: // BAR (low)
- return (dmac->reg[channel].bar & 0x0000ffff);
- case 0x12: // NIV
- return dmac->reg[channel].niv;
- case 0x13: // EIV
- return dmac->reg[channel].eiv;
- case 0x14: // MFC
- return dmac->reg[channel].mfc;
- case 0x16: // CPR
- return dmac->reg[channel].cpr;
- case 0x18: // DFC
- return dmac->reg[channel].dfc;
- case 0x1c: // BFC
- return dmac->reg[channel].bfc;
- case 0x1f: // GCR
- return dmac->reg[channel].gcr;
- }
- return 0xff;
-}
-
-void hd63450_write(device_t* device, int offset, int data, UINT16 mem_mask)
-{
- int channel,reg;
-
- hd63450_t* dmac = get_safe_token(device);
-
- channel = (offset & 0x60) >> 5;
- reg = offset & 0x1f;
- switch(reg)
- {
- case 0x00: // CSR / CER
- if(ACCESSING_BITS_8_15)
- {
-// dmac->reg[channel].csr = (data & 0xff00) >> 8;
-// logerror("DMA#%i: Channel status write : %02x\n",channel,dmac.reg[channel].csr);
- }
- // CER is read-only, so no action needed there.
- break;
- case 0x02: // DCR / OCR
- if(ACCESSING_BITS_8_15)
- {
- dmac->reg[channel].dcr = (data & 0xff00) >> 8;
- logerror("DMA#%i: Device Control write : %02x\n",channel,dmac->reg[channel].dcr);
- }
- if(ACCESSING_BITS_0_7)
- {
- dmac->reg[channel].ocr = data & 0x00ff;
- logerror("DMA#%i: Operation Control write : %02x\n",channel,dmac->reg[channel].ocr);
- }
- break;
- case 0x03: // SCR / CCR
- if(ACCESSING_BITS_8_15)
- {
- dmac->reg[channel].scr = (data & 0xff00) >> 8;
- logerror("DMA#%i: Sequence Control write : %02x\n",channel,dmac->reg[channel].scr);
- }
- if(ACCESSING_BITS_0_7)
- {
- dmac->reg[channel].ccr = data & 0x00ff;
- if((data & 0x0080))// && !dmac->intf->dma_read[channel] && !dmac->intf->dma_write[channel])
- dma_transfer_start(device, channel,0);
- if(data & 0x0010) // software abort
- dma_transfer_abort(device,channel);
- if(data & 0x0020) // halt operation
- dma_transfer_halt(device,channel);
- if(data & 0x0040) // continure operation
- dma_transfer_continue(device,channel);
- logerror("DMA#%i: Channel Control write : %02x\n",channel,dmac->reg[channel].ccr);
- }
- break;
- case 0x05: // MTC
- dmac->reg[channel].mtc = data;
- logerror("DMA#%i: Memory Transfer Counter write : %04x\n",channel,dmac->reg[channel].mtc);
- break;
- case 0x06: // MAR (high)
- dmac->reg[channel].mar = (dmac->reg[channel].mar & 0x0000ffff) | (data << 16);
- logerror("DMA#%i: Memory Address write : %08lx\n",channel,dmac->reg[channel].mar);
- break;
- case 0x07: // MAR (low)
- dmac->reg[channel].mar = (dmac->reg[channel].mar & 0xffff0000) | (data & 0x0000ffff);
- logerror("DMA#%i: Memory Address write : %08lx\n",channel,dmac->reg[channel].mar);
- break;
- case 0x0a: // DAR (high)
- dmac->reg[channel].dar = (dmac->reg[channel].dar & 0x0000ffff) | (data << 16);
- logerror("DMA#%i: Device Address write : %08lx\n",channel,dmac->reg[channel].dar);
- break;
- case 0x0b: // DAR (low)
- dmac->reg[channel].dar = (dmac->reg[channel].dar & 0xffff0000) | (data & 0x0000ffff);
- logerror("DMA#%i: Device Address write : %08lx\n",channel,dmac->reg[channel].dar);
- break;
- case 0x0d: // BTC
- dmac->reg[channel].btc = data;
- logerror("DMA#%i: Base Transfer Counter write : %04x\n",channel,dmac->reg[channel].btc);
- break;
- case 0x0e: // BAR (high)
- dmac->reg[channel].bar = (dmac->reg[channel].bar & 0x0000ffff) | (data << 16);
- logerror("DMA#%i: Base Address write : %08lx\n",channel,dmac->reg[channel].bar);
- break;
- case 0x0f: // BAR (low)
- dmac->reg[channel].bar = (dmac->reg[channel].bar & 0xffff0000) | (data & 0x0000ffff);
- logerror("DMA#%i: Base Address write : %08lx\n",channel,dmac->reg[channel].bar);
- break;
- case 0x12: // NIV
- dmac->reg[channel].niv = data & 0xff;
- logerror("DMA#%i: Normal IRQ Vector write : %02x\n",channel,dmac->reg[channel].niv);
- break;
- case 0x13: // EIV
- dmac->reg[channel].eiv = data & 0xff;
- logerror("DMA#%i: Error IRQ Vector write : %02x\n",channel,dmac->reg[channel].eiv);
- break;
- case 0x14: // MFC
- dmac->reg[channel].mfc = data & 0xff;
- logerror("DMA#%i: Memory Function Code write : %02x\n",channel,dmac->reg[channel].mfc);
- break;
- case 0x16: // CPR
- dmac->reg[channel].cpr = data & 0xff;
- logerror("DMA#%i: Channel Priority write : %02x\n",channel,dmac->reg[channel].cpr);
- break;
- case 0x18: // DFC
- dmac->reg[channel].dfc = data & 0xff;
- logerror("DMA#%i: Device Function Code write : %02x\n",channel,dmac->reg[channel].dfc);
- break;
- case 0x1c: // BFC
- dmac->reg[channel].bfc = data & 0xff;
- logerror("DMA#%i: Base Function Code write : %02x\n",channel,dmac->reg[channel].bfc);
- break;
- case 0x1f:
- dmac->reg[channel].gcr = data & 0xff;
- logerror("DMA#%i: General Control write : %02x\n",channel,dmac->reg[channel].gcr);
- break;
- }
-}
-
-static void dma_transfer_start(device_t* device, int channel, int dir)
-{
- address_space &space = device->machine().firstcpu->space(AS_PROGRAM);
- hd63450_t* dmac = get_safe_token(device);
- dmac->in_progress[channel] = 1;
- dmac->reg[channel].csr &= ~0xe0;
- dmac->reg[channel].csr |= 0x08; // Channel active
- dmac->reg[channel].csr &= ~0x30; // Reset Error and Normal termination bits
- if((dmac->reg[channel].ocr & 0x0c) != 0x00) // Array chain or Link array chain
- {
- dmac->reg[channel].mar = space.read_word(dmac->reg[channel].bar) << 16;
- dmac->reg[channel].mar |= space.read_word(dmac->reg[channel].bar+2);
- dmac->reg[channel].mtc = space.read_word(dmac->reg[channel].bar+4);
- if(dmac->reg[channel].btc > 0)
- dmac->reg[channel].btc--;
- }
-
- // Burst transfers will halt the CPU until the transfer is complete
- if((dmac->reg[channel].dcr & 0xc0) == 0x00) // Burst transfer
- {
- device_t *cpu = device->machine().device(dmac->intf->cpu_tag);
- cpu->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
- dmac->timer[channel]->adjust(attotime::zero, channel, dmac->burst_clock[channel]);
- }
- else if(!(dmac->reg[channel].ocr & 2))
- dmac->timer[channel]->adjust(attotime::from_usec(500), channel, dmac->clock[channel]);
- else if((dmac->reg[channel].ocr & 3) == 3)
- dmac->timer[channel]->adjust(attotime::from_usec(500), channel, attotime::never);
-
- dmac->transfer_size[channel] = dmac->reg[channel].mtc;
-
- logerror("DMA: Transfer begins: size=0x%08x\n",dmac->transfer_size[channel]);
-}
-
-void hd63450_set_timer(device_t* device, int channel, attotime tm)
-{
- hd63450_t* dmac = get_safe_token(device);
-
- dmac->clock[channel] = tm;
- if(dmac->in_progress[channel] != 0)
- dmac->timer[channel]->adjust(attotime::zero, channel, dmac->clock[channel]);
-}
-
-static TIMER_CALLBACK(dma_transfer_timer)
-{
- hd63450_single_transfer((device_t*)ptr, param);
-}
-
-static void dma_transfer_abort(device_t* device, int channel)
-{
- hd63450_t* dmac = get_safe_token(device);
-
- logerror("DMA#%i: Transfer aborted\n",channel);
- dmac->timer[channel]->adjust(attotime::zero);
- dmac->in_progress[channel] = 0;
- dmac->reg[channel].mtc = dmac->transfer_size[channel];
- dmac->reg[channel].csr |= 0xe0; // channel operation complete, block transfer complete
- dmac->reg[channel].csr &= ~0x08; // channel no longer active
-}
-
-static void dma_transfer_halt(device_t* device, int channel)
-{
- hd63450_t* dmac = get_safe_token(device);
-
- dmac->halted[channel] = 1;
- dmac->timer[channel]->adjust(attotime::zero);
-}
-
-static void dma_transfer_continue(device_t* device, int channel)
-{
- hd63450_t* dmac = get_safe_token(device);
-
- if(dmac->halted[channel] != 0)
- {
- dmac->halted[channel] = 0;
- dmac->timer[channel]->adjust(attotime::zero, channel, dmac->clock[channel]);
- }
-}
-
-void hd63450_single_transfer(device_t* device, int x)
-{
- address_space &space = device->machine().firstcpu->space(AS_PROGRAM);
- int data;
- int datasize = 1;
- hd63450_t* dmac = get_safe_token(device);
-
- if(dmac->in_progress[x] != 0) // DMA in progress in channel x
- {
- if(dmac->reg[x].ocr & 0x80) // direction: 1 = device -> memory
- {
- if(dmac->intf->dma_read[x])
- {
- data = dmac->intf->dma_read[x](device->machine(),dmac->reg[x].mar);
- if(data == -1)
- return; // not ready to receive data
- space.write_byte(dmac->reg[x].mar,data);
- datasize = 1;
- }
- else
- {
- switch(dmac->reg[x].ocr & 0x30) // operation size
- {
- case 0x00: // 8 bit
- data = space.read_byte(dmac->reg[x].dar); // read from device address
- space.write_byte(dmac->reg[x].mar, data); // write to memory address
- datasize = 1;
- break;
- case 0x10: // 16 bit
- data = space.read_word(dmac->reg[x].dar); // read from device address
- space.write_word(dmac->reg[x].mar, data); // write to memory address
- datasize = 2;
- break;
- case 0x20: // 32 bit
- data = space.read_word(dmac->reg[x].dar) << 16; // read from device address
- data |= space.read_word(dmac->reg[x].dar+2);
- space.write_word(dmac->reg[x].mar, (data & 0xffff0000) >> 16); // write to memory address
- space.write_word(dmac->reg[x].mar+2, data & 0x0000ffff);
- datasize = 4;
- break;
- case 0x30: // 8 bit packed (?)
- data = space.read_byte(dmac->reg[x].dar); // read from device address
- space.write_byte(dmac->reg[x].mar, data); // write to memory address
- datasize = 1;
- break;
- }
- }
-// logerror("DMA#%i: byte transfer %08lx -> %08lx (byte = %02x)\n",x,dmac.reg[x].dar,dmac.reg[x].mar,data);
- }
- else // memory -> device
- {
- if(dmac->intf->dma_write[x])
- {
- data = space.read_byte(dmac->reg[x].mar);
- dmac->intf->dma_write[x](device->machine(), dmac->reg[x].mar,data);
- datasize = 1;
- }
- else
- {
- switch(dmac->reg[x].ocr & 0x30) // operation size
- {
- case 0x00: // 8 bit
- data = space.read_byte(dmac->reg[x].mar); // read from memory address
- space.write_byte(dmac->reg[x].dar, data); // write to device address
- datasize = 1;
- break;
- case 0x10: // 16 bit
- data = space.read_word(dmac->reg[x].mar); // read from memory address
- space.write_word(dmac->reg[x].dar, data); // write to device address
- datasize = 2;
- break;
- case 0x20: // 32 bit
- data = space.read_word(dmac->reg[x].mar) << 16; // read from memory address
- data |= space.read_word(dmac->reg[x].mar+2); // read from memory address
- space.write_word(dmac->reg[x].dar, (data & 0xffff0000) >> 16); // write to device address
- space.write_word(dmac->reg[x].dar+2, data & 0x0000ffff); // write to device address
- datasize = 4;
- break;
- case 0x30: // 8 bit packed (?)
- data = space.read_byte(dmac->reg[x].mar); // read from memory address
- space.write_byte(dmac->reg[x].dar, data); // write to device address
- datasize = 1;
- break;
- }
- }
-// logerror("DMA#%i: byte transfer %08lx -> %08lx\n",x,dmac->reg[x].mar,dmac->reg[x].dar);
- }
-
-
- // decrease memory transfer counter
- if(dmac->reg[x].mtc > 0)
- dmac->reg[x].mtc--;
-
- // handle change of memory and device addresses
- if((dmac->reg[x].scr & 0x03) == 0x01)
- dmac->reg[x].dar+=datasize;
- else if((dmac->reg[x].scr & 0x03) == 0x02)
- dmac->reg[x].dar-=datasize;
-
- if((dmac->reg[x].scr & 0x0c) == 0x04)
- dmac->reg[x].mar+=datasize;
- else if((dmac->reg[x].scr & 0x0c) == 0x08)
- dmac->reg[x].mar-=datasize;
-
- if(dmac->reg[x].mtc <= 0)
- {
- // End of transfer
- logerror("DMA#%i: End of transfer\n",x);
- if((dmac->reg[x].ocr & 0x0c) != 0 && dmac->reg[x].btc > 0)
- {
- dmac->reg[x].btc--;
- dmac->reg[x].bar+=6;
- dmac->reg[x].mar = space.read_word(dmac->reg[x].bar) << 16;
- dmac->reg[x].mar |= space.read_word(dmac->reg[x].bar+2);
- dmac->reg[x].mtc = space.read_word(dmac->reg[x].bar+4);
- return;
- }
- dmac->timer[x]->adjust(attotime::zero);
- dmac->in_progress[x] = 0;
- dmac->reg[x].csr |= 0xe0; // channel operation complete, block transfer complete
- dmac->reg[x].csr &= ~0x08; // channel no longer active
-
- // Burst transfer
- if((dmac->reg[x].dcr & 0xc0) == 0x00)
- {
- device_t *cpu = device->machine().device(dmac->intf->cpu_tag);
- cpu->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
- }
-
- if(dmac->intf->dma_end)
- dmac->intf->dma_end(device->machine(),x,dmac->reg[x].ccr & 0x08);
- }
- }
-}
-
-int hd63450_get_vector(device_t* device, int channel)
-{
- hd63450_t* dmac = get_safe_token(device);
- return dmac->reg[channel].niv;
-}
-
-int hd63450_get_error_vector(device_t* device, int channel)
-{
- hd63450_t* dmac = get_safe_token(device);
- return dmac->reg[channel].eiv;
-}
-
-READ16_DEVICE_HANDLER(hd63450_r) { return hd63450_read(device,offset,mem_mask); }
-WRITE16_DEVICE_HANDLER(hd63450_w) { hd63450_write(device,offset,data,mem_mask); }
-
-const device_type HD63450 = &device_creator<hd63450_device>;
-
-hd63450_device::hd63450_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, HD63450, "Hitachi HD63450", tag, owner, clock, "hd63450", __FILE__)
-{
- m_token = global_alloc_clear(hd63450_t);
-}
-
-hd63450_device::~hd63450_device() { global_free(m_token); }
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void hd63450_device::device_config_complete()
-{
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void hd63450_device::device_start()
-{
- DEVICE_START_NAME( hd63450 )(this);
-}
diff --git a/src/mess/machine/hd63450.h b/src/mess/machine/hd63450.h
deleted file mode 100644
index e732608ec9e..00000000000
--- a/src/mess/machine/hd63450.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- Hitachi HD63450 DMA Controller
-*/
-
-#include "emu.h"
-
-struct hd63450_intf
-{
- const char *cpu_tag;
- attotime clock[4];
- attotime burst_clock[4];
- void (*dma_end)(running_machine &machine,int channel,int irq); // called when the DMA transfer ends
- void (*dma_error)(running_machine &machine,int channel, int irq); // called when a DMA transfer error occurs
- int (*dma_read[4])(running_machine &machine,int addr); // special read / write handlers for each channel
- void (*dma_write[4])(running_machine &machine,int addr,int data);
-};
-
-int hd63450_read(device_t* device, int offset, UINT16 mem_mask);
-void hd63450_write(device_t* device,int offset, int data, UINT16 mem_mask);
-void hd63450_single_transfer(device_t* device, int x);
-void hd63450_set_timer(device_t* device, int channel, attotime tm);
-
-int hd63450_get_vector(device_t* device, int channel);
-int hd63450_get_error_vector(device_t* device, int channel);
-
-class hd63450_device : public device_t
-{
-public:
- hd63450_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
- ~hd63450_device();
-
- // access to legacy token
- struct hd63450_t *token() const { assert(m_token != NULL); return m_token; }
-protected:
- // device-level overrides
- virtual void device_config_complete();
- virtual void device_start();
-private:
- // internal state
- struct hd63450_t *m_token;
-};
-
-extern const device_type HD63450;
-
-
-#define MCFG_HD63450_ADD(_tag, _config) \
- MCFG_DEVICE_ADD(_tag, HD63450, 0) \
- MCFG_DEVICE_CONFIG(_config)
-
-DECLARE_READ16_DEVICE_HANDLER( hd63450_r );
-DECLARE_WRITE16_DEVICE_HANDLER( hd63450_w );
diff --git a/src/mess/machine/hd64610.c b/src/mess/machine/hd64610.c
deleted file mode 100644
index c56775e486f..00000000000
--- a/src/mess/machine/hd64610.c
+++ /dev/null
@@ -1,366 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Sandro Ronco
-/**********************************************************************
-
- Hitachi HD64610 Real Time Clock
-
-*********************************************************************/
-
-/*
-
- TODO:
- - leap year
- - test mode
-
-*/
-
-#include "hd64610.h"
-#include "coreutil.h"
-
-
-// device type definition
-const device_type HD64610 = &device_creator<hd64610_device>;
-
-
-//**************************************************************************
-// MACROS / CONSTANTS
-//**************************************************************************
-
-#define LOG 1
-
-// internal registers
-enum
-{
- REG_64HZ = 0,
- REG_SECOND,
- REG_MINUTE,
- REG_HOUR,
- REG_DAY_OF_THE_WEEK,
- REG_DAY,
- REG_MONTH,
- REG_YEAR,
- REG_64HZ_ALARM,
- REG_SECOND_ALARM,
- REG_MINUTE_ALARM,
- REG_HOUR_ALARM,
- REG_DAY_OF_THE_WEEK_ALARM,
- REG_DAY_ALARM,
- REG_CRA,
- REG_CRB,
-};
-
-
-// Control Register A
-#define CRA_CF 0x80
-#define CRA_CIE 0x10
-#define CRA_AIE 0x08
-#define CRA_AF 0x01
-
-// Control Register B
-#define CRB_TEST 0x08
-#define CRB_ADJ 0x04
-#define CRB_RESET 0x02
-#define CRB_S 0x01
-
-// alarm
-#define ALARM_ENB 0x80
-
-// register write mask
-static const int REG_WRITE_MASK[0x10] =
-{
- 0x00, 0x7f, 0x7f, 0x3f, 0x07, 0x3f, 0x1f, 0xff, 0xff, 0xff, 0xff, 0xbf, 0x83, 0xbf, 0x18, 0xff
-};
-
-//**************************************************************************
-// INLINE HELPERS
-//**************************************************************************
-
-//-------------------------------------------------
-// set_irq_line -
-//-------------------------------------------------
-
-inline void hd64610_device::set_irq_line()
-{
- int irq_out = (((m_regs[REG_CRA] & CRA_CF) && (m_regs[REG_CRA] & CRA_CIE)) ||
- ((m_regs[REG_CRA] & CRA_AF) && (m_regs[REG_CRA] & CRA_AIE))) ? 0 : 1;
-
- if (m_irq_out != irq_out)
- {
- if (LOG) logerror("HD64610 '%s' IRQ %u\n", tag(), irq_out);
-
- m_out_irq_cb(irq_out);
- m_irq_out = irq_out;
- }
-}
-
-
-//-------------------------------------------------
-// read_counter -
-//-------------------------------------------------
-
-inline UINT8 hd64610_device::read_counter(int counter)
-{
- return bcd_2_dec(m_regs[counter]);
-}
-
-
-//-------------------------------------------------
-// write_counter -
-//-------------------------------------------------
-
-inline void hd64610_device::write_counter(int counter, UINT8 value)
-{
- m_regs[counter] = dec_2_bcd(value);
-}
-
-
-//-------------------------------------------------
-// check_alarm -
-//-------------------------------------------------
-
-inline void hd64610_device::check_alarm()
-{
- bool alarm_flag = true;
-
- // clear alarm flag
- m_regs[REG_CRA] &= ~CRA_AF;
-
- if (m_regs[REG_64HZ_ALARM] & ALARM_ENB || m_regs[REG_SECOND_ALARM] & ALARM_ENB || m_regs[REG_MINUTE_ALARM] & ALARM_ENB ||
- m_regs[REG_HOUR_ALARM] & ALARM_ENB || m_regs[REG_DAY_OF_THE_WEEK_ALARM] & ALARM_ENB || m_regs[REG_DAY_ALARM] & ALARM_ENB)
- {
- // at least one ENB is active
-
- for (int i = REG_64HZ; i <= REG_DAY; i++)
- {
- if ((m_regs[i] & REG_WRITE_MASK[i]) != (m_regs[i+8] & REG_WRITE_MASK[i]) && m_regs[i+8] & ALARM_ENB)
- alarm_flag = false;
- }
-
- m_regs[REG_CRA] |= (alarm_flag ? CRA_AF : 0);
- }
-}
-
-
-
-//**************************************************************************
-// LIVE DEVICE
-//**************************************************************************
-
-//-------------------------------------------------
-// hd64610_device - constructor
-//-------------------------------------------------
-
-hd64610_device::hd64610_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, HD64610, "HD64610", tag, owner, clock, "hd64610", __FILE__),
- device_rtc_interface(mconfig, *this),
- device_nvram_interface(mconfig, *this),
- m_out_irq_cb(*this),
- m_out_1hz_cb(*this),
- m_hline_state(1),
- m_irq_out(1)
-{
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void hd64610_device::device_start()
-{
- // resolve callbacks
- m_out_irq_cb.resolve_safe();
- m_out_1hz_cb.resolve_safe();
-
- // allocate timers
- m_counter_timer = timer_alloc(TIMER_UPDATE_COUNTER);
- m_counter_timer->adjust(attotime::from_hz(clock() / 256), 0, attotime::from_hz(clock() / 256));
-
- // state saving
- save_item(NAME(m_regs));
- save_item(NAME(m_irq_out));
- save_item(NAME(m_hline_state));
-}
-
-
-//-------------------------------------------------
-// device_start - device-specific reset
-//-------------------------------------------------
-
-void hd64610_device::device_reset()
-{
- set_current_time(machine());
-}
-
-
-//-------------------------------------------------
-// device_timer - handler timer events
-//-------------------------------------------------
-
-void hd64610_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- switch (id)
- {
- case TIMER_UPDATE_COUNTER:
- if(m_hline_state || (m_regs[REG_CRB] & CRB_S))
- {
- m_regs[REG_64HZ]++;
-
- if (m_regs[REG_64HZ] & 0x80)
- {
- // update seconds
- advance_seconds();
-
- // set carry flag
- m_regs[REG_CRA] |= CRA_CF;
-
- m_regs[REG_64HZ] &= 0x7f;
- }
-
- // update 1Hz out
- m_out_1hz_cb(BIT(m_regs[REG_64HZ], 6));
-
- // update IRQ
- check_alarm();
- set_irq_line();
- }
- break;
- }
-}
-
-
-//-------------------------------------------------
-// rtc_clock_updated -
-//-------------------------------------------------
-
-void hd64610_device::rtc_clock_updated(int year, int month, int day, int day_of_week, int hour, int minute, int second)
-{
- write_counter(REG_SECOND, second);
- write_counter(REG_MINUTE, minute);
- write_counter(REG_HOUR, hour);
- write_counter(REG_DAY, day);
- write_counter(REG_MONTH, month);
- write_counter(REG_YEAR, year);
- m_regs[REG_DAY_OF_THE_WEEK] = day_of_week;
-
- check_alarm();
- set_irq_line();
-}
-
-
-//-------------------------------------------------
-// nvram_default - called to initialize NVRAM to
-// its default state
-//-------------------------------------------------
-
-void hd64610_device::nvram_default()
-{
- memset(m_regs, 0, 0x10);
-}
-
-
-//-------------------------------------------------
-// nvram_read - called to read NVRAM from the
-// .nv file
-//-------------------------------------------------
-
-void hd64610_device::nvram_read(emu_file &file)
-{
- file.read(m_regs, 0x10);
-}
-
-
-//-------------------------------------------------
-// nvram_write - called to write NVRAM to the
-// .nv file
-//-------------------------------------------------
-
-void hd64610_device::nvram_write(emu_file &file)
-{
- file.write(m_regs, 0x10);
-}
-
-
-//-------------------------------------------------
-// hardware start/stop
-//-------------------------------------------------
-
-WRITE_LINE_MEMBER( hd64610_device::h_w )
-{
- m_hline_state = state;
-}
-
-
-//-------------------------------------------------
-// read -
-//-------------------------------------------------
-
-READ8_MEMBER( hd64610_device::read )
-{
- UINT8 data = m_regs[offset & 0x0f];
-
- if (LOG) logerror("HD64610 '%s' Register %u Read %02x\n", tag(), offset, data);
-
- return data;
-}
-
-
-//-------------------------------------------------
-// write -
-//-------------------------------------------------
-
-WRITE8_MEMBER( hd64610_device::write )
-{
- switch (offset & 0x0f)
- {
- case REG_64HZ:
- // read only
- logerror("HD64610 '%s' Writing to read-only register 64Hz Counter\n", tag());
- break;
-
- case REG_CRA:
- m_regs[REG_CRA] = data & REG_WRITE_MASK[REG_CRA];
-
- if ((data & CRA_CF) == 0)
- {
- if (LOG) logerror("HD64610 '%s' clear carry flag\n", tag());
- m_regs[REG_CRA] &= 0x7f;
- }
- if ((data & CRA_AF) == 0)
- {
- if (LOG) logerror("HD64610 '%s' clear alarm flag\n", tag());
- m_regs[REG_CRA] &= 0xfe;
- }
-
- if (LOG) logerror("HD64610 '%s' set alarm IRQ %d\n", tag(), BIT(data, 3));
- if (LOG) logerror("HD64610 '%s' set carry IRQ %d\n", tag(), BIT(data, 4));
- break;
-
- case REG_CRB:
- m_regs[REG_CRB] = data & REG_WRITE_MASK[REG_CRB];
-
- if (data & CRB_ADJ)
- {
- if (LOG) logerror("HD64610 '%s' 30-sec adjustament\n", tag());
- adjust_seconds();
- m_regs[REG_64HZ] = 0;
-
- m_regs[REG_CRB] &= ~CRB_ADJ;
- }
-
- if (data & CRB_RESET)
- {
- if (LOG) logerror("HD64610 '%s' CRB reset\n", tag());
- m_regs[REG_64HZ] = 0;
-
- m_regs[REG_CRB] &= ~CRB_RESET;
- }
-
- if (LOG) logerror("HD64610 '%s' set timer %d\n", tag(), BIT(data, 0));
- break;
-
- default:
- m_regs[offset & 0x0f] = data & REG_WRITE_MASK[offset & 0x0f];
- if (LOG) logerror("HD64610 '%s' Register %u Write %02x\n", tag(), offset & 0x0f, data);
- break;
- }
-}
diff --git a/src/mess/machine/hd64610.h b/src/mess/machine/hd64610.h
deleted file mode 100644
index 4d25cef9a7a..00000000000
--- a/src/mess/machine/hd64610.h
+++ /dev/null
@@ -1,105 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Sandro Ronco
-/**********************************************************************
-
- Hitachi HD64610 Real Time Clock
-
-**********************************************************************
- _____ _____
- GND 1 |* \_/ | 24 Vcc
- H-Start/Stop 2 | | 23 OSC2
- _IRQ 3 | | 22 OSC1
- 1Hz 4 | HD64610 | 21 GND
- A3 5 | | 20 _WE
- A2 6 | | 19 _OE
- A1 7 | | 18 _CS
- A0 8 | | 17 I/O8
- I/O1 9 | | 16 I/O7
- I/O2 10 | | 15 I/O6
- I/O3 11 | | 14 I/O5
- GND 12 |_____________| 13 I/O4
-
-**********************************************************************/
-
-#pragma once
-
-#ifndef __HD64610__
-#define __HD64610__
-
-#include "emu.h"
-
-
-
-//**************************************************************************
-// INTERFACE CONFIGURATION MACROS
-//**************************************************************************
-
-#define MCFG_HD64610_OUT_IRQ_CB(_devcb) \
- devcb = &hd64610_device::set_out_irq_callback(*device, DEVCB2_##_devcb);
-
-#define MCFG_HD64610_OUT_1HZ_CB(_devcb) \
- devcb = &hd64610_device::set_out_1hz_callback(*device, DEVCB2_##_devcb);
-
-
-//**************************************************************************
-// TYPE DEFINITIONS
-//**************************************************************************
-
-// ======================> hd64610_device
-
-class hd64610_device : public device_t,
- public device_rtc_interface,
- public device_nvram_interface
-{
-public:
- // construction/destruction
- hd64610_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- template<class _Object> static devcb2_base &set_out_irq_callback(device_t &device, _Object object) { return downcast<hd64610_device &>(device).m_out_irq_cb.set_callback(object); }
- template<class _Object> static devcb2_base &set_out_1hz_callback(device_t &device, _Object object) { return downcast<hd64610_device &>(device).m_out_1hz_cb.set_callback(object); }
-
- DECLARE_READ8_MEMBER( read );
- DECLARE_WRITE8_MEMBER( write );
-
- // hardware start/stop line
- DECLARE_WRITE_LINE_MEMBER( h_w );
-
-protected:
- // device-level overrides
- virtual void device_start();
- virtual void device_reset();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
-
- // device_rtc_interface overrides
- virtual void rtc_clock_updated(int year, int month, int day, int day_of_week, int hour, int minute, int second);
-
- // device_nvram_interface overrides
- virtual void nvram_default();
- virtual void nvram_read(emu_file &file);
- virtual void nvram_write(emu_file &file);
-
-private:
- inline void set_irq_line();
- inline UINT8 read_counter(int counter);
- inline void write_counter(int counter, UINT8 value);
- inline void check_alarm();
-
- static const device_timer_id TIMER_UPDATE_COUNTER = 0;
-
- devcb2_write_line m_out_irq_cb;
- devcb2_write_line m_out_1hz_cb;
-
- UINT8 m_regs[0x10]; // Internal registers
- int m_hline_state; // H-Start/Stop line
- int m_irq_out; // alarm output
-
- // timers
- emu_timer *m_counter_timer;
-};
-
-
-// device type definition
-extern const device_type HD64610;
-
-
-#endif
diff --git a/src/mess/machine/i8271.c b/src/mess/machine/i8271.c
deleted file mode 100644
index e24b2a591a3..00000000000
--- a/src/mess/machine/i8271.c
+++ /dev/null
@@ -1,1543 +0,0 @@
-/* Intel 8271 Floppy Disc Controller */
-/* used in BBC Micro B,Acorn Atom */
-/* Jun 2000. Kev Thacker */
-
-/* TODO:
-
- - Scan commands
- - Check the commands work properly using a BBC disc copier program
- - check if 0 is specified as number of sectors, how many sectors
- is actually transfered
- - deleted data functions (error if data finds deleted data?)
-*/
-
-
-#include "emu.h"
-#include "i8271.h"
-#include "imagedev/flopdrv.h"
-
-/* data request */
-#define I8271_FLAGS_DATA_REQUEST 0x01
-/* data direction. If 0x02, then it is from fdc to cpu, else
-it is from cpu to fdc */
-#define I8271_FLAGS_DATA_DIRECTION 0x02
-
-enum I8271_STATE_t
-{
- I8271_STATE_EXECUTION_READ = 0,
- I8271_STATE_EXECUTION_WRITE
-};
-
-/* commands accepted */
-#define I8271_COMMAND_SPECIFY 0x035
-#define I8271_COMMAND_SEEK 0x029
-#define I8271_COMMAND_READ_DRIVE_STATUS 0x02c
-#define I8271_COMMAND_READ_SPECIAL_REGISTER 0x03d
-#define I8271_COMMAND_WRITE_SPECIAL_REGISTER 0x03a
-#define I8271_COMMAND_FORMAT 0x023
-#define I8271_COMMAND_READ_ID 0x01b
-#define I8271_COMMAND_READ_DATA_SINGLE_RECORD 0x012
-#define I8271_COMMAND_READ_DATA_AND_DELETED_DATA_SINGLE_RECORD 0x016
-#define I8271_COMMAND_WRITE_DATA_SINGLE_RECORD 0x00a
-#define I8271_COMMAND_WRITE_DELETED_DATA_SINGLE_RECORD 0x00e
-#define I8271_COMMAND_VERIFY_DATA_AND_DELETED_DATA_SINGLE_RECORD 0x01e
-#define I8271_COMMAND_READ_DATA_MULTI_RECORD 0x013
-#define I8271_COMMAND_READ_DATA_AND_DELETED_DATA_MULTI_RECORD 0x017
-#define I8271_COMMAND_WRITE_DATA_MULTI_RECORD 0x00b
-#define I8271_COMMAND_WRITE_DELETED_DATA_MULTI_RECORD 0x00f
-#define I8271_COMMAND_VERIFY_DATA_AND_DELETED_DATA_MULTI_RECORD 0x01f
-#define I8271_COMMAND_SCAN_DATA 0x000
-#define I8271_COMMAND_SCAN_DATA_AND_DELETED_DATA 0x004
-
-/*
-#define I8271_COMMAND_READ_OPERATION (1<<4)
-#define I8271_COMMAND_DELETED_DATA (1<<2)
-#define I8271_COMMAND_MULTI_RECORD (1<<0)
-*/
-
-
-
-/* first parameter for specify command */
-#define I8271_SPECIFY_INITIALIZATION 0x0d
-#define I8271_SPECIFY_LOAD_BAD_TRACKS_SURFACE_0 0x010
-#define I8271_SPECIFY_LOAD_BAD_TRACKS_SURFACE_1 0x018
-
-/* first parameter for read/write special register */
-#define I8271_SPECIAL_REGISTER_SCAN_SECTOR_NUMBER 0x06
-#define I8271_SPECIAL_REGISTER_SCAN_MSB_OF_COUNT 0x014
-#define I8271_SPECIAL_REGISTER_SCAN_LSB_OF_COUNT 0x013
-#define I8271_SPECIAL_REGISTER_SURFACE_0_CURRENT_TRACK 0x012
-#define I8271_SPECIAL_REGISTER_SURFACE_1_CURRENT_TRACK 0x01a
-#define I8271_SPECIAL_REGISTER_MODE_REGISTER 0x017
-#define I8271_SPECIAL_REGISTER_DRIVE_CONTROL_OUTPUT_PORT 0x023
-#define I8271_SPECIAL_REGISTER_DRIVE_CONTROL_INPUT_PORT 0x022
-#define I8271_SPECIAL_REGISTER_SURFACE_0_BAD_TRACK_1 0x010
-#define I8271_SPECIAL_REGISTER_SURFACE_0_BAD_TRACK_2 0x011
-#define I8271_SPECIAL_REGISTER_SURFACE_1_BAD_TRACK_1 0x018
-#define I8271_SPECIAL_REGISTER_SURFACE_1_BAD_TRACK_2 0x019
-
-
-/* status register bits */
-#define I8271_STATUS_COMMAND_BUSY 0x080
-#define I8271_STATUS_COMMAND_FULL 0x040
-#define I8271_STATUS_PARAMETER_FULL 0x020
-#define I8271_STATUS_RESULT_FULL 0x010
-#define I8271_STATUS_INT_REQUEST 0x008
-#define I8271_STATUS_NON_DMA_REQUEST 0x004
-
-#define VERBOSE 0
-
-#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#define FDC_LOG(x) do { if (VERBOSE) logerror("I8271: %s\n",x); } while (0)
-#define FDC_LOG_COMMAND(x) do { if (VERBOSE) logerror("I8271: COMMAND %s\n",x); } while (0)
-
-
-/* Device Interface */
-
-const device_type I8271 = &device_creator<i8271_device>;
-
-i8271_device::i8271_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, I8271, "Intel 8271", tag, owner, clock, "i8271", __FILE__),
- m_flags(0),
- m_state(0),
- m_Command(0),
- m_StatusRegister(0),
- m_CommandRegister(0),
- m_ResultRegister(0),
- m_ParameterRegister(0),
- m_ResetRegister(0),
- m_data(0),
- m_ParameterCount(0),
- m_ParameterCountWritten(0),
- m_Mode(0),
- m_drive(0),
- m_side(0),
- m_drive_control_output(0),
- m_drive_control_input(0),
- m_StepRate(0),
- m_HeadSettlingTime(0),
- m_IndexCountBeforeHeadUnload(0),
- m_HeadLoadTime(0),
- //m_ID_C(0),
- //m_ID_H(0),
- m_ID_R(0),
- m_ID_N(0),
- m_data_id(0),
- m_ExecutionPhaseTransferCount(0),
- m_ExecutionPhaseCount(0),
- m_Counter(0)
- //m_data_direction(0)
-{
- for (int i = 0; i < 8; i++ )
- {
- m_CommandParameters[i] = 0;
- }
-
- for (int i = 0; i < 2; i++ )
- {
- m_CurrentTrack[i] = 0;
- }
-
- for (int i = 0; i < 4; i++ )
- {
- m_BadTracks[i] = 0;
- }
-}
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void i8271_device::device_config_complete()
-{
- // inherit a copy of the static data
- const i8271_interface *intf = reinterpret_cast<const i8271_interface *>(static_config());
- if (intf != NULL)
- *static_cast<i8271_interface *>(this) = *intf;
-
- // or initialize to defaults if none provided
- else
- {
- memset(&m_interrupt_cb, 0, sizeof(m_interrupt_cb));
- m_dma_request = NULL;
- m_floppy_drive_tags[0] = "";
- m_floppy_drive_tags[1] = "";
- }
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void i8271_device::device_start()
-{
- m_data_timer = timer_alloc(TIMER_DATA_CALLBACK);
- m_command_complete_timer = timer_alloc(TIMER_TIMED_COMMAND_COMPLETE);
- m_drive = 0;
- m_pExecutionPhaseData = auto_alloc_array(machine(), char, 0x4000);
- m_interrupt_func.resolve(m_interrupt_cb, *this);
-
- // register for state saving
- /*save_item(NAME(m_flags));
- save_item(NAME(m_state));
- save_item(NAME(m_Command));
- save_item(NAME(m_StatusRegister));
- save_item(NAME(m_CommandRegister));
- save_item(NAME(m_ResultRegister));
- save_item(NAME(m_ParameterRegister));
- save_item(NAME(m_ResetRegister));
- save_item(NAME(m_data));
- //save_item(NAME(m_ParameterCount));
- //save_item(NAME(m_ParameterCountWritten));
- save_item(NAME(m_CommandParameters));
- //save_item(NAME(m_CurrentTrack));
- //save_item(NAME(m_BadTracks));
- //save_item(NAME(m_Mode));
- save_item(NAME(m_drive));
- save_item(NAME(m_side));
- save_item(NAME(m_drive_control_output));
- save_item(NAME(m_drive_control_input));
- //save_item(NAME(m_StepRate));
- //save_item(NAME(m_HeadSettlingTime));
- //save_item(NAME(m_IndexCountBeforeHeadUnload));
- //save_item(NAME(m_HeadLoadTime));
- save_item(NAME(m_ID_C));
- save_item(NAME(m_ID_H));
- save_item(NAME(m_ID_R));
- save_item(NAME(m_ID_N));
- save_item(NAME(m_data_id));
- save_item(NAME(m_ExecutionPhaseTransferCount));
- save_item(NAME(m_ExecutionPhaseCount));
- save_item(NAME(m_Counter));
- save_item(NAME(m_data_direction));
- save_pointer(NAME(m_pExecutionPhaseData), 0x4000);*/
-}
-
-//-------------------------------------------------
-// device_reset - device-specific reset
-//-------------------------------------------------
-
-void i8271_device::device_reset()
-{
- m_StatusRegister = 0; //I8271_STATUS_INT_REQUEST | I8271_STATUS_NON_DMA_REQUEST;
- m_Mode = 0x0c0; /* bits 0, 1 are initialized to zero */
- m_ParameterCountWritten = 0;
- m_ParameterCount = 0;
-
- /* if timer is active remove */
- m_command_complete_timer->reset();
- m_data_timer->reset();
-
- /* clear irq */
- set_irq_state(0);
- /* clear dma */
- set_dma_drq();
-}
-
-device_t *i8271_device::current_image()
-{
- if (m_floppy_drive_tags[m_drive]!=NULL) {
- return machine().device(m_floppy_drive_tags[m_drive]);
- } else {
- return NULL;
- }
-}
-
-
-void i8271_device::seek_to_track(int track)
-{
- device_t *img = current_image();
- if (track==0)
- {
- /* seek to track 0 */
- unsigned char StepCount = 0x0ff;
-
- /*logerror("step\n"); */
-
- /* track 0 not set, not seeked more than 255 tracks */
- while (floppy_tk00_r(img) && (StepCount != 0))
- {
-/* logerror("step\n"); */
- StepCount--;
- floppy_drive_seek(img, -1);
- }
-
- m_CurrentTrack[m_drive] = 0;
-
- /* failed to find track 0? */
- if (StepCount==0)
- {
- /* Completion Type: operator intervation probably required for recovery */
- /* Completion code: track 0 not found */
- m_ResultRegister |= (2<<3) | 2<<1;
- }
-
- /* step out - towards track 0 */
- m_drive_control_output &=~(1<<2);
- }
- else
- {
- signed int SignedTracks;
-
- /* calculate number of tracks to seek */
- SignedTracks = track - m_CurrentTrack[m_drive];
-
- /* step towards 0 */
- m_drive_control_output &= ~(1<<2);
-
- if (SignedTracks>0)
- {
- /* step away from 0 */
- m_drive_control_output |= (1<<2);
- }
-
-
- /* seek to track 0 */
- floppy_drive_seek(img, SignedTracks);
-
- m_CurrentTrack[m_drive] = track;
- }
-}
-
-void i8271_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- switch (id)
- {
- case TIMER_DATA_CALLBACK:
- /* ok, trigger data request now */
- data_request();
-
- /* stop it */
- m_data_timer->reset();
- break;
-
- case TIMER_TIMED_COMMAND_COMPLETE:
- command_complete(1,1);
-
- /* stop it, but don't allow it to be free'd */
- m_command_complete_timer->reset();
- break;
-
- default:
- break;
- }
-}
-
-/* setup a timed data request - data request will be triggered in a few usecs time */
-void i8271_device::timed_data_request()
-{
- int usecs;
- /* 64 for single density */
- usecs = 64;
-
- /* set timers */
- m_command_complete_timer->reset();
- m_data_timer->adjust(attotime::from_usec(usecs));
-}
-
-
-/* setup a irq to occur 128us later - in reality this would be much later, because the int would
-come after reading the two CRC bytes at least! This function is used when a irq is required at
-command completion. Required for read data and write data, where last byte could be missed! */
-void i8271_device::timed_command_complete()
-{
- int usecs;
-
- /* 64 for single density - 2 crc bytes later*/
- usecs = 64*2;
-
- /* set timers */
- m_data_timer->reset();
- m_command_complete_timer->adjust(attotime::from_usec(usecs));
-}
-
-void i8271_device::set_irq_state(int state)
-{
- m_StatusRegister &= ~I8271_STATUS_INT_REQUEST;
- if (state)
- {
- m_StatusRegister |= I8271_STATUS_INT_REQUEST;
- }
-
- if (!m_interrupt_func.isnull())
- m_interrupt_func(m_StatusRegister & I8271_STATUS_INT_REQUEST);
-}
-
-void i8271_device::set_dma_drq()
-{
- if (m_dma_request)
- {
- m_dma_request(*this, (m_flags & I8271_FLAGS_DATA_REQUEST), (m_flags & I8271_FLAGS_DATA_DIRECTION));
- }
-}
-
-void i8271_device::load_bad_tracks(int surface)
-{
- m_BadTracks[(surface<<1) + 0] = m_CommandParameters[1];
- m_BadTracks[(surface<<1) + 1] = m_CommandParameters[2];
- m_CurrentTrack[surface] = m_CommandParameters[3];
-}
-
-void i8271_device::write_bad_track(int surface, int track, int data)
-{
- m_BadTracks[(surface<<1) + (track-1)] = data;
-}
-
-void i8271_device::write_current_track(int surface, int track)
-{
- m_CurrentTrack[surface] = track;
-}
-
-int i8271_device::read_current_track(int surface)
-{
- return m_CurrentTrack[surface];
-}
-
-int i8271_device::read_bad_track(int surface, int track)
-{
- return m_BadTracks[(surface<<1) + (track-1)];
-}
-
-void i8271_device::get_drive()
-{
- /* &40 = drive 0 side 0 */
- /* &80 = drive 1 side 0 */
-
-
-
- if (m_CommandRegister & (1<<6))
- {
- m_drive = 0;
- }
-
- if (m_CommandRegister & (1<<7))
- {
- m_drive = 1;
- }
-
-}
-
-void i8271_device::check_all_parameters_written()
-{
- if (m_ParameterCount == m_ParameterCountWritten)
- {
- m_StatusRegister &= ~I8271_STATUS_COMMAND_FULL;
-
- command_execute();
- }
-}
-
-
-void i8271_device::update_state()
-{
- switch (m_state)
- {
- /* fdc reading data and passing it to cpu which must read it */
- case I8271_STATE_EXECUTION_READ:
- {
- // /* if data request has been cleared, i.e. caused by a read of the register */
- // if ((m_flags & I8271_FLAGS_DATA_REQUEST)==0)
- {
- /* setup data with byte */
- m_data = m_pExecutionPhaseData[m_ExecutionPhaseCount];
-
-/* logerror("read data %02x\n", m_data); */
-
- /* update counters */
- m_ExecutionPhaseCount++;
- m_ExecutionPhaseTransferCount--;
-
- // logerror("Count: %04x\n", m_ExecutionPhaseCount);
- // logerror("Remaining: %04x\n", m_ExecutionPhaseTransferCount);
-
- /* completed? */
- if (m_ExecutionPhaseTransferCount==0)
- {
- /* yes */
-
- // logerror("sector read complete!\n");
- /* continue command */
- command_continue();
- }
- else
- {
- /* no */
-
- /* issue data request */
- timed_data_request();
- }
- }
- }
- break;
-
- /* fdc reading data and passing it to cpu which must read it */
- case I8271_STATE_EXECUTION_WRITE:
- {
- /* setup data with byte */
- m_pExecutionPhaseData[m_ExecutionPhaseCount] = m_data;
- /* update counters */
- m_ExecutionPhaseCount++;
- m_ExecutionPhaseTransferCount--;
-
- /* completed? */
- if (m_ExecutionPhaseTransferCount==0)
- {
- /* yes */
-
- /* continue command */
- command_continue();
- }
- else
- {
- /* no */
-
- /* issue data request */
- timed_data_request();
- }
- }
- break;
-
- default:
- break;
- }
-}
-
-void i8271_device::initialise_execution_phase_read(int transfer_size)
-{
- /* read */
- m_flags |= I8271_FLAGS_DATA_DIRECTION;
- m_ExecutionPhaseCount = 0;
- m_ExecutionPhaseTransferCount = transfer_size;
- m_state = I8271_STATE_EXECUTION_READ;
-}
-
-
-void i8271_device::initialise_execution_phase_write(int transfer_size)
-{
- /* write */
- m_flags &= ~I8271_FLAGS_DATA_DIRECTION;
- m_ExecutionPhaseCount = 0;
- m_ExecutionPhaseTransferCount = transfer_size;
- m_state = I8271_STATE_EXECUTION_WRITE;
-}
-
-/* for data transfers */
-void i8271_device::data_request()
-{
- m_flags |= I8271_FLAGS_DATA_REQUEST;
-
- if ((m_Mode & 0x01)!=0)
- {
- /* non-dma */
- m_StatusRegister |= I8271_STATUS_NON_DMA_REQUEST;
- /* set int */
- set_irq_state(1);
- }
- else
- {
- /* dma */
- m_StatusRegister &= ~I8271_STATUS_NON_DMA_REQUEST;
-
- set_dma_drq();
- }
-}
-
-void i8271_device::command_complete(int result, int int_rq)
-{
- /* not busy, and not a execution phase data request in non-dma mode */
- m_StatusRegister &= ~(I8271_STATUS_COMMAND_BUSY | I8271_STATUS_NON_DMA_REQUEST);
-
- if (result)
- {
- m_StatusRegister |= I8271_STATUS_RESULT_FULL;
- }
-
- if (int_rq)
- {
- /* trigger an int */
- set_irq_state(1);
- }
-
- /* correct?? */
- m_drive_control_output &=~1;
-}
-
-
-/* for data transfers */
-void i8271_device::clear_data_request()
-{
- m_flags &= ~I8271_FLAGS_DATA_REQUEST;
-
- if ((m_Mode & 0x01)!=0)
- {
- /* non-dma */
- m_StatusRegister &= ~I8271_STATUS_NON_DMA_REQUEST;
- /* set int */
- set_irq_state(0);
- }
- else
- {
- /* dma */
- set_dma_drq();
- }
-}
-
-
-void i8271_device::command_continue()
-{
- switch (m_Command)
- {
- case I8271_COMMAND_READ_DATA_MULTI_RECORD:
- case I8271_COMMAND_READ_DATA_SINGLE_RECORD:
- {
- /* completed all sectors? */
- m_Counter--;
- /* increment sector id */
- m_ID_R++;
-
- /* end command? */
- if (m_Counter==0)
- {
- timed_command_complete();
- return;
- }
-
- do_read();
- }
- break;
-
- case I8271_COMMAND_WRITE_DATA_MULTI_RECORD:
- case I8271_COMMAND_WRITE_DATA_SINGLE_RECORD:
- {
- /* put the buffer to the sector */
- floppy_drive_write_sector_data(current_image(), m_side, m_data_id, m_pExecutionPhaseData, 1<<(m_ID_N+7),0);
-
- /* completed all sectors? */
- m_Counter--;
- /* increment sector id */
- m_ID_R++;
-
- /* end command? */
- if (m_Counter==0)
- {
- timed_command_complete();
- return;
- }
-
- do_write();
- }
- break;
-
- case I8271_COMMAND_READ_ID:
- {
- m_Counter--;
-
- if (m_Counter==0)
- {
- timed_command_complete();
- return;
- }
-
- do_read_id();
- }
- break;
-
- default:
- break;
- }
-}
-
-void i8271_device::do_read()
-{
- /* find the sector */
- if (find_sector())
- {
- /* get the sector into the buffer */
- floppy_drive_read_sector_data(current_image(), m_side, m_data_id, m_pExecutionPhaseData, 1<<(m_ID_N+7));
-
- /* initialise for reading */
- initialise_execution_phase_read(1<<(m_ID_N+7));
-
- /* update state - gets first byte and triggers a data request */
- timed_data_request();
- return;
- }
- LOG(("error getting sector data\n"));
-
- timed_command_complete();
-}
-
-void i8271_device::do_read_id()
-{
- chrn_id id;
-
- /* get next id from disc */
- floppy_drive_get_next_id(current_image(), m_side,&id);
-
- m_pExecutionPhaseData[0] = id.C;
- m_pExecutionPhaseData[1] = id.H;
- m_pExecutionPhaseData[2] = id.R;
- m_pExecutionPhaseData[3] = id.N;
-
- initialise_execution_phase_read(4);
-}
-
-
-void i8271_device::do_write()
-{
- /* find the sector */
- if (find_sector())
- {
- /* initialise for reading */
- initialise_execution_phase_write(1<<(m_ID_N+7));
-
- /* update state - gets first byte and triggers a data request */
- timed_data_request();
- return;
- }
- LOG(("error getting sector data\n"));
-
- timed_command_complete();
-}
-
-
-
-int i8271_device::find_sector()
-{
- device_t *img = current_image();
-// int track_count_attempt;
-
-// track_count_attempt
- /* find sector within one revolution of the disc - 2 index pulses */
-
- /* number of times we have seen index hole */
- int index_count = 0;
-
- /* get sector id's */
- do
- {
- chrn_id id;
-
- /* get next id from disc */
- if (floppy_drive_get_next_id(img, m_side,&id))
- {
- /* tested on Amstrad CPC - All bytes must match, otherwise
- a NO DATA error is reported */
- if (id.R == m_ID_R)
- {
- /* TODO: Is this correct? What about bad tracks? */
- if (id.C == m_CurrentTrack[m_drive])
- {
- m_data_id = id.data_id;
- return 1;
- }
- else
- {
- /* TODO: if track doesn't match, the real 8271 does a step */
-
-
- return 0;
- }
- }
- }
-
- /* index set? */
- if (floppy_drive_get_flag_state(img, FLOPPY_DRIVE_INDEX))
- {
- index_count++;
- }
-
- }
- while (index_count!=2);
-
- /* completion type: command/drive error */
- /* completion code: sector not found */
- m_ResultRegister |= (3<<3);
-
- return 0;
-}
-
-void i8271_device::command_execute()
-{
- device_t *img = current_image();
-
- /* clear it = good completion status */
- /* this will be changed if anything bad happens! */
- m_ResultRegister = 0;
-
- switch (m_Command)
- {
- case I8271_COMMAND_SPECIFY:
- {
- switch (m_CommandParameters[0])
- {
- case 0x0d:
- {
- LOG(("Initialization\n"));
- m_StepRate = m_CommandParameters[1];
- m_HeadSettlingTime = m_CommandParameters[2];
- m_IndexCountBeforeHeadUnload = (m_CommandParameters[3]>>4) & 0x0f;
- m_HeadLoadTime = (m_CommandParameters[3] & 0x0f);
- }
- break;
-
- case 0x010:
- {
- LOG(("Load bad Tracks Surface 0\n"));
- load_bad_tracks(0);
-
- }
- break;
-
- case 0x018:
- {
- LOG(("Load bad Tracks Surface 1\n"));
- load_bad_tracks(1);
-
- }
- break;
- }
-
- /* no result */
- command_complete(0,0);
- }
- break;
-
- case I8271_COMMAND_READ_SPECIAL_REGISTER:
- {
- /* unknown - what is read when a special register that isn't allowed is specified? */
- int data = 0x0ff;
-
- switch (m_CommandParameters[0])
- {
- case I8271_SPECIAL_REGISTER_MODE_REGISTER:
- {
- data = m_Mode;
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_0_CURRENT_TRACK:
- {
- data = read_current_track(0);
-
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_1_CURRENT_TRACK:
- {
- data = read_current_track(1);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_0_BAD_TRACK_1:
- {
- data = read_bad_track(0,1);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_0_BAD_TRACK_2:
- {
- data = read_bad_track(0,2);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_1_BAD_TRACK_1:
- {
- data = read_bad_track(1,1);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_1_BAD_TRACK_2:
- {
- data = read_bad_track(1,2);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_DRIVE_CONTROL_OUTPUT_PORT:
- {
- FDC_LOG_COMMAND("Read Drive Control Output port\n");
-
- get_drive();
-
- /* assumption: select bits reflect the select bits from the previous
- command. i.e. read drive status */
- data = (m_drive_control_output & ~0x0c0)
- | (m_CommandRegister & 0x0c0);
-
-
- }
- break;
-
- case I8271_SPECIAL_REGISTER_DRIVE_CONTROL_INPUT_PORT:
- {
- /* bit 7: not used */
- /* bit 6: ready 1 */
- /* bit 5: write fault */
- /* bit 4: index */
- /* bit 3: wr prot */
- /* bit 2: rdy 0 */
- /* bit 1: track 0 */
- /* bit 0: cnt/opi */
-
- FDC_LOG_COMMAND("Read Drive Control Input port\n");
-
-
- m_drive_control_input = (1<<6) | (1<<2);
-
- /* bit 3 = 0 if write protected */
- m_drive_control_input |= floppy_wpt_r(img) << 3;
-
- /* bit 1 = 0 if head at track 0 */
- m_drive_control_input |= floppy_tk00_r(img) << 1;
-
- /* need to setup this register based on drive selected */
- data = m_drive_control_input;
- }
- break;
-
- }
-
- m_ResultRegister = data;
-
- command_complete(1,0);
- }
- break;
-
-
- case I8271_COMMAND_WRITE_SPECIAL_REGISTER:
- {
- switch (m_CommandParameters[0])
- {
- case I8271_SPECIAL_REGISTER_MODE_REGISTER:
- {
- /* TODO: Check bits 6-7 and 5-2 are valid */
- m_Mode = m_CommandParameters[1];
-
- if (m_Mode & 0x01)
- {
- LOG(("Mode: Non-DMA\n"));
- }
- else
- {
- LOG(("Mode: DMA\n"));
- }
-
- if (m_Mode & 0x02)
- {
- LOG(("Single actuator\n"));
- }
- else
- {
- LOG(("Double actuator\n"));
- }
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_0_CURRENT_TRACK:
- {
- LOG(("Surface 0 Current Track\n"));
- write_current_track(0, m_CommandParameters[1]);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_1_CURRENT_TRACK:
- {
- LOG(("Surface 1 Current Track\n"));
- write_current_track(1, m_CommandParameters[1]);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_0_BAD_TRACK_1:
- {
- LOG(("Surface 0 Bad Track 1\n"));
- write_bad_track(0, 1, m_CommandParameters[1]);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_0_BAD_TRACK_2:
- {
- LOG(("Surface 0 Bad Track 2\n"));
- write_bad_track(0, 2,m_CommandParameters[1]);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_1_BAD_TRACK_1:
- {
- LOG(("Surface 1 Bad Track 1\n"));
-
-
- write_bad_track(1, 1, m_CommandParameters[1]);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_SURFACE_1_BAD_TRACK_2:
- {
- LOG(("Surface 1 Bad Track 2\n"));
-
- write_bad_track(1, 2, m_CommandParameters[1]);
- }
- break;
-
- case I8271_SPECIAL_REGISTER_DRIVE_CONTROL_OUTPUT_PORT:
- {
-// /* get drive selected */
-// m_drive = (m_CommandParameters[1]>>6) & 0x03;
-
- FDC_LOG_COMMAND("Write Drive Control Output port\n");
-
-
- if (m_CommandParameters[1] & 0x01)
- {
- LOG(("Write Enable\n"));
- }
- if (m_CommandParameters[1] & 0x02)
- {
- LOG(("Seek/Step\n"));
- }
- if (m_CommandParameters[1] & 0x04)
- {
- LOG(("Direction\n"));
- }
- if (m_CommandParameters[1] & 0x08)
- {
- LOG(("Load Head\n"));
- }
- if (m_CommandParameters[1] & 0x010)
- {
- LOG(("Low head current\n"));
- }
- if (m_CommandParameters[1] & 0x020)
- {
- LOG(("Write Fault Reset\n"));
- }
-
- LOG(("Select %02x\n", (m_CommandParameters[1] & 0x0c0)>>6));
-
- /* get drive */
- get_drive();
-
- /* on bbc dfs 09 this is the side select output */
- m_side = (m_CommandParameters[1]>>5) & 0x01;
-
- /* load head - on mini-sized drives this turns on the disc motor,
- on standard-sized drives this loads the head and turns the motor on */
- floppy_mon_w(img, !BIT(m_CommandParameters[1], 3));
- floppy_drive_set_ready_state(img, 1, 1);
-
- /* step pin changed? if so perform a step in the direction indicated */
- if (((m_drive_control_output^m_CommandParameters[1]) & (1<<1))!=0)
- {
- /* step pin changed state? */
-
- if ((m_CommandParameters[1] & (1<<1))!=0)
- {
- signed int signed_tracks;
-
- if ((m_CommandParameters[1] & (1<<2))!=0)
- {
- signed_tracks = 1;
- }
- else
- {
- signed_tracks = -1;
- }
-
- floppy_drive_seek(img, signed_tracks);
- }
- }
-
- m_drive_control_output = m_CommandParameters[1];
-
-
- }
- break;
-
- case I8271_SPECIAL_REGISTER_DRIVE_CONTROL_INPUT_PORT:
- {
- FDC_LOG_COMMAND("Write Drive Control Input port\n");
-
- // m_drive_control_input = m_CommandParameters[1];
- }
- break;
-
- }
-
- /* write doesn't supply a result */
- command_complete(0,0);
- }
- break;
-
- case I8271_COMMAND_READ_DRIVE_STATUS:
- {
- unsigned char status;
-
- get_drive();
-
- /* no write fault */
- status = 0;
-
- status |= (1<<2) | (1<<6);
-
- /* these two do not appear to be set at all! ?? */
-
- if (m_floppy_drive_tags[0]!=NULL) {
- if (floppy_drive_get_flag_state(machine().device(m_floppy_drive_tags[0]), FLOPPY_DRIVE_READY))
- {
- status |= (1<<2);
- }
- }
-
- if (m_floppy_drive_tags[1]!=NULL) {
- if (floppy_drive_get_flag_state(machine().device(m_floppy_drive_tags[1]), FLOPPY_DRIVE_READY))
- {
- status |= (1<<6);
- }
- }
-
- /* bit 3 = 1 if write protected */
- status |= !floppy_wpt_r(img) << 3;
-
- /* bit 1 = 1 if head at track 0 */
- status |= !floppy_tk00_r(img) << 1;
-
- m_ResultRegister = status;
- command_complete(1,0);
-
- }
- break;
-
- case I8271_COMMAND_SEEK:
- {
- get_drive();
-
-
- seek_to_track(m_CommandParameters[0]);
-
- /* check for bad seek */
- timed_command_complete();
-
- }
- break;
-
- case I8271_COMMAND_READ_DATA_MULTI_RECORD:
- {
- /* N value as stored in ID field */
- m_ID_N = (m_CommandParameters[2]>>5) & 0x07;
-
- /* starting sector id */
- m_ID_R = m_CommandParameters[1];
-
- /* number of sectors to transfer */
- m_Counter = m_CommandParameters[2] & 0x01f;
-
-
- FDC_LOG_COMMAND("READ DATA MULTI RECORD");
-
- LOG(("Sector Count: %02x\n", m_Counter));
- LOG(("Track: %02x\n",m_CommandParameters[0]));
- LOG(("Sector: %02x\n", m_CommandParameters[1]));
- LOG(("Sector Length: %02x bytes\n", 1<<(m_ID_N+7)));
-
- get_drive();
-
- if (!floppy_drive_get_flag_state(img, FLOPPY_DRIVE_READY))
- {
- /* Completion type: operation intervention probably required for recovery */
- /* Completion code: Drive not ready */
- m_ResultRegister = (2<<3);
- timed_command_complete();
- }
- else
- {
- seek_to_track(m_CommandParameters[0]);
-
-
- do_read();
- }
-
- }
- break;
-
- case I8271_COMMAND_READ_DATA_SINGLE_RECORD:
- {
- FDC_LOG_COMMAND("READ DATA SINGLE RECORD");
-
- m_ID_N = 0;
- m_Counter = 1;
- m_ID_R = m_CommandParameters[1];
-
- LOG(("Sector Count: %02x\n", m_Counter));
- LOG(("Track: %02x\n",m_CommandParameters[0]));
- LOG(("Sector: %02x\n", m_CommandParameters[1]));
- LOG(("Sector Length: %02x bytes\n", 1<<(m_ID_N+7)));
-
- get_drive();
-
- if (!floppy_drive_get_flag_state(img, FLOPPY_DRIVE_READY))
- {
- /* Completion type: operation intervention probably required for recovery */
- /* Completion code: Drive not ready */
- m_ResultRegister = (2<<3);
- timed_command_complete();
- }
- else
- {
- seek_to_track(m_CommandParameters[0]);
-
- do_read();
- }
-
- }
- break;
-
- case I8271_COMMAND_WRITE_DATA_MULTI_RECORD:
- {
- /* N value as stored in ID field */
- m_ID_N = (m_CommandParameters[2]>>5) & 0x07;
-
- /* starting sector id */
- m_ID_R = m_CommandParameters[1];
-
- /* number of sectors to transfer */
- m_Counter = m_CommandParameters[2] & 0x01f;
-
- FDC_LOG_COMMAND("READ DATA MULTI RECORD");
-
- LOG(("Sector Count: %02x\n", m_Counter));
- LOG(("Track: %02x\n",m_CommandParameters[0]));
- LOG(("Sector: %02x\n", m_CommandParameters[1]));
- LOG(("Sector Length: %02x bytes\n", 1<<(m_ID_N+7)));
-
- get_drive();
-
- m_drive_control_output &=~1;
-
- if (!floppy_drive_get_flag_state(img, FLOPPY_DRIVE_READY))
- {
- /* Completion type: operation intervention probably required for recovery */
- /* Completion code: Drive not ready */
- m_ResultRegister = (2<<3);
- timed_command_complete();
- }
- else
- {
- if (floppy_wpt_r(img) == CLEAR_LINE)
- {
- /* Completion type: operation intervention probably required for recovery */
- /* Completion code: Drive write protected */
- m_ResultRegister = (2<<3) | (1<<1);
- timed_command_complete();
- }
- else
- {
- m_drive_control_output |=1;
-
- seek_to_track(m_CommandParameters[0]);
-
- do_write();
- }
- }
- }
- break;
-
- case I8271_COMMAND_WRITE_DATA_SINGLE_RECORD:
- {
- FDC_LOG_COMMAND("WRITE DATA SINGLE RECORD");
-
- m_ID_N = 0;
- m_Counter = 1;
- m_ID_R = m_CommandParameters[1];
-
-
- LOG(("Sector Count: %02x\n", m_Counter));
- LOG(("Track: %02x\n",m_CommandParameters[0]));
- LOG(("Sector: %02x\n", m_CommandParameters[1]));
- LOG(("Sector Length: %02x bytes\n", 1<<(m_ID_N+7)));
- get_drive();
-
- m_drive_control_output &=~1;
-
- if (!floppy_drive_get_flag_state(img, FLOPPY_DRIVE_READY))
- {
- /* Completion type: operation intervention probably required for recovery */
- /* Completion code: Drive not ready */
- m_ResultRegister = (2<<3);
- timed_command_complete();
- }
- else
- {
- if (floppy_wpt_r(img) == CLEAR_LINE)
- {
- /* Completion type: operation intervention probably required for recovery */
- /* Completion code: Drive write protected */
- m_ResultRegister = (2<<3) | (1<<1);
- timed_command_complete();
- }
- else
- {
- m_drive_control_output |=1;
-
- seek_to_track(m_CommandParameters[0]);
-
- do_write();
- }
- }
-
- }
- break;
-
-
- case I8271_COMMAND_READ_ID:
- {
- FDC_LOG_COMMAND("READ ID");
-
- LOG(("Track: %02x\n",m_CommandParameters[0]));
- LOG(("ID Field Count: %02x\n", m_CommandParameters[2]));
-
- get_drive();
-
- if (!floppy_drive_get_flag_state(img, FLOPPY_DRIVE_READY))
- {
- /* Completion type: operation intervention probably required for recovery */
- /* Completion code: Drive not ready */
- m_ResultRegister = (2<<3);
- timed_command_complete();
- }
- else
- {
- m_Counter = m_CommandParameters[2];
-
- seek_to_track(m_CommandParameters[0]);
-
- do_read_id();
- }
- }
- break;
-
- default:
- LOG(("ERROR Unrecognised Command\n"));
- break;
- }
-}
-
-
-
-WRITE8_MEMBER(i8271_device::write)
-{
- switch (offset & 3)
- {
- case 0:
- {
- LOG(("I8271 W Command Register: %02x\n", data));
-
- m_CommandRegister = data;
- m_Command = m_CommandRegister & 0x03f;
-
- m_StatusRegister |= I8271_STATUS_COMMAND_BUSY | I8271_STATUS_COMMAND_FULL;
- m_StatusRegister &= ~I8271_STATUS_PARAMETER_FULL | I8271_STATUS_RESULT_FULL;
- m_ParameterCountWritten = 0;
-
- switch (m_Command)
- {
- case I8271_COMMAND_SPECIFY:
- {
- FDC_LOG_COMMAND("SPECIFY");
-
- m_ParameterCount = 4;
- }
- break;
-
- case I8271_COMMAND_SEEK:
- {
- FDC_LOG_COMMAND("SEEK");
-
- m_ParameterCount = 1;
- }
- break;
-
- case I8271_COMMAND_READ_DRIVE_STATUS:
- {
- FDC_LOG_COMMAND("READ DRIVE STATUS");
-
- m_ParameterCount = 0;
- }
- break;
-
- case I8271_COMMAND_READ_SPECIAL_REGISTER:
- {
- FDC_LOG_COMMAND("READ SPECIAL REGISTER");
-
- m_ParameterCount = 1;
- }
- break;
-
- case I8271_COMMAND_WRITE_SPECIAL_REGISTER:
- {
- FDC_LOG_COMMAND("WRITE SPECIAL REGISTER");
-
- m_ParameterCount = 2;
- }
- break;
-
- case I8271_COMMAND_FORMAT:
- {
- m_ParameterCount = 5;
- }
- break;
-
- case I8271_COMMAND_READ_ID:
- {
- m_ParameterCount = 3;
-
- }
- break;
-
-
- case I8271_COMMAND_READ_DATA_SINGLE_RECORD:
- case I8271_COMMAND_READ_DATA_AND_DELETED_DATA_SINGLE_RECORD:
- case I8271_COMMAND_WRITE_DATA_SINGLE_RECORD:
- case I8271_COMMAND_WRITE_DELETED_DATA_SINGLE_RECORD:
- case I8271_COMMAND_VERIFY_DATA_AND_DELETED_DATA_SINGLE_RECORD:
- {
- m_ParameterCount = 2;
- }
- break;
-
- case I8271_COMMAND_READ_DATA_MULTI_RECORD:
- case I8271_COMMAND_READ_DATA_AND_DELETED_DATA_MULTI_RECORD:
- case I8271_COMMAND_WRITE_DATA_MULTI_RECORD:
- case I8271_COMMAND_WRITE_DELETED_DATA_MULTI_RECORD:
- case I8271_COMMAND_VERIFY_DATA_AND_DELETED_DATA_MULTI_RECORD:
- {
- m_ParameterCount = 3;
- }
- break;
-
- case I8271_COMMAND_SCAN_DATA:
- case I8271_COMMAND_SCAN_DATA_AND_DELETED_DATA:
- {
- m_ParameterCount = 5;
- }
- break;
-
-
-
-
-
-
- }
-
- check_all_parameters_written();
- }
- break;
-
- case 1:
- {
- LOG(("I8271 W Parameter Register: %02x\n",data));
- m_ParameterRegister = data;
-
- if (m_ParameterCount!=0)
- {
- m_CommandParameters[m_ParameterCountWritten] = data;
- m_ParameterCountWritten++;
- }
-
- check_all_parameters_written();
- }
- break;
-
- case 2:
- {
- LOG(("I8271 W Reset Register: %02x\n", data));
- if (((data ^ m_ResetRegister) & 0x01)!=0)
- {
- if ((data & 0x01)==0)
- {
- reset();
- }
- }
-
- m_ResetRegister = data;
-
-
- }
- break;
-
- default:
- break;
- }
-}
-
-READ8_MEMBER(i8271_device::read)
-{
- switch (offset & 3)
- {
- case 0:
- {
- /* bit 1,0 are zero other bits contain status data */
- m_StatusRegister &= ~0x03;
- LOG(("I8271 R Status Register: %02x\n",m_StatusRegister));
- return m_StatusRegister;
- }
-
- case 1:
- {
- if ((m_StatusRegister & I8271_STATUS_COMMAND_BUSY)==0)
- {
- /* clear IRQ */
- set_irq_state(0);
-
- m_StatusRegister &= ~I8271_STATUS_RESULT_FULL;
- LOG(("I8271 R Result Register %02x\n",m_ResultRegister));
- return m_ResultRegister;
- }
-
- /* not useful information when command busy */
- return 0x0ff;
- }
-
-
- default:
- break;
- }
-
- return 0x0ff;
-}
-
-
-/* to be completed! */
-READ8_MEMBER(i8271_device::dack_r)
-{
- return data_r(space, offset);
-}
-
-/* to be completed! */
-WRITE8_MEMBER(i8271_device::dack_w)
-{
- data_w(space, offset, data);
-}
-
-READ8_MEMBER(i8271_device::data_r)
-{
- clear_data_request();
-
- update_state();
-
- // logerror("I8271 R data: %02x\n",m_data);
-
-
- return m_data;
-}
-
-WRITE8_MEMBER(i8271_device::data_w)
-{
- m_data = data;
-
-// logerror("I8271 W data: %02x\n",m_data);
-
- clear_data_request();
-
- update_state();
-}
diff --git a/src/mess/machine/i8271.h b/src/mess/machine/i8271.h
deleted file mode 100644
index eb561f8b70c..00000000000
--- a/src/mess/machine/i8271.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*****************************************************************************
- *
- * machine/i8271.h
- *
- ****************************************************************************/
-
-#ifndef I8271_H_
-#define I8271_H_
-
-/***************************************************************************
- TYPE DEFINITIONS
-***************************************************************************/
-
-typedef void (*i8271_dma_request)(device_t &device, int state, int read_);
-#define I8271_DMA_REQUEST(name) void name(device_t &device, int state, int read_)
-
-struct i8271_interface
-{
- devcb_write_line m_interrupt_cb;
- i8271_dma_request m_dma_request;
- const char *m_floppy_drive_tags[2];
-};
-
-/***************************************************************************
- MACROS
-***************************************************************************/
-
-class i8271_device : public device_t,
- public i8271_interface
-{
-public:
- i8271_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
- ~i8271_device() {}
-
- DECLARE_READ8_MEMBER(read);
- DECLARE_WRITE8_MEMBER(write);
-
- DECLARE_READ8_MEMBER(dack_r);
- DECLARE_WRITE8_MEMBER(dack_w);
-
- DECLARE_READ8_MEMBER(data_r);
- DECLARE_WRITE8_MEMBER(data_w);
-
-protected:
- // device-level overrides
- virtual void device_config_complete();
- virtual void device_start();
- virtual void device_reset();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
-
-private:
- // internal state
- enum
- {
- TIMER_DATA_CALLBACK,
- TIMER_TIMED_COMMAND_COMPLETE
- };
-
- int m_flags;
- int m_state;
- unsigned char m_Command;
- unsigned char m_StatusRegister;
- unsigned char m_CommandRegister;
- unsigned char m_ResultRegister;
- unsigned char m_ParameterRegister;
- unsigned char m_ResetRegister;
- unsigned char m_data;
-
- /* number of parameters required after command is specified */
- unsigned long m_ParameterCount;
- /* number of parameters written so far */
- unsigned long m_ParameterCountWritten;
-
- unsigned char m_CommandParameters[8];
-
- /* current track for each drive */
- unsigned long m_CurrentTrack[2];
-
- /* 2 bad tracks for drive 0, followed by 2 bad tracks for drive 1 */
- unsigned long m_BadTracks[4];
-
- /* mode special register */
- unsigned long m_Mode;
-
-
- /* drive outputs */
- int m_drive;
- int m_side;
-
- /* drive control output special register */
- int m_drive_control_output;
- /* drive control input special register */
- int m_drive_control_input;
-
- unsigned long m_StepRate;
- unsigned long m_HeadSettlingTime;
- unsigned long m_IndexCountBeforeHeadUnload;
- unsigned long m_HeadLoadTime;
-
- /* id on disc to find */
- //int m_ID_C;
- //int m_ID_H;
- int m_ID_R;
- int m_ID_N;
-
- /* id of data for read/write */
- int m_data_id;
-
- int m_ExecutionPhaseTransferCount;
- char *m_pExecutionPhaseData;
- int m_ExecutionPhaseCount;
-
- /* sector counter and id counter */
- int m_Counter;
-
- /* ==0, to cpu, !=0 =from cpu */
- //int m_data_direction;
-
- emu_timer *m_data_timer;
- emu_timer *m_command_complete_timer;
-
- devcb_resolved_write_line m_interrupt_func;
-
- device_t *current_image();
- void seek_to_track(int track);
- void load_bad_tracks(int surface);
- void write_bad_track(int surface, int track, int data);
- void write_current_track(int surface, int track);
- int read_current_track(int surface);
- int read_bad_track(int surface, int track);
- void get_drive();
- void check_all_parameters_written();
- void update_state();
- void initialise_execution_phase_read(int transfer_size);
- void initialise_execution_phase_write(int transfer_size);
- void command_execute();
- void command_continue();
- void command_complete(int result, int int_rq);
- void timed_command_complete();
- void data_request();
- void clear_data_request();
- void timed_data_request();
- /* locate sector for read/write operation */
- int find_sector();
- /* do a read operation */
- void do_read();
- void do_write();
- void do_read_id();
- void set_irq_state(int);
- void set_dma_drq();
-};
-
-extern const device_type I8271;
-
-
-/***************************************************************************
- DEVICE CONFIGURATION MACROS
-***************************************************************************/
-
-#define MCFG_I8271_ADD(_tag, _intrf) \
- MCFG_DEVICE_ADD(_tag, I8271, 0) \
- MCFG_DEVICE_CONFIG(_intrf)
-
-#endif /* I8271_H_ */
diff --git a/src/mess/machine/kb3600.c b/src/mess/machine/kb3600.c
deleted file mode 100644
index de24bd3f822..00000000000
--- a/src/mess/machine/kb3600.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/**********************************************************************
-
- General Instruments AY-5-3600 Keyboard Encoder emulation
-
- Copyright MESS Team.
- Visit http://mamedev.org for licensing and usage restrictions.
-
-*********************************************************************/
-
-/*
-
- TODO:
-
- - scan timer clock frequency
- - more accurate emulation of real chip
-
-*/
-
-#include "kb3600.h"
-
-
-
-//**************************************************************************
-// MACROS / CONSTANTS
-//**************************************************************************
-
-#define LOG 0
-
-
-
-//**************************************************************************
-// GLOBAL VARIABLES
-//**************************************************************************
-
-// devices
-const device_type AY3600 = &device_creator<ay3600_device>;
-
-//**************************************************************************
-// LIVE DEVICE
-//**************************************************************************
-
-//-------------------------------------------------
-// ay3600_device - constructor
-//-------------------------------------------------
-
-ay3600_device::ay3600_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, AY3600, "AY-5-3600", tag, owner, clock, "ay3600", __FILE__),
- m_read_x0(*this),
- m_read_x1(*this),
- m_read_x2(*this),
- m_read_x3(*this),
- m_read_x4(*this),
- m_read_x5(*this),
- m_read_x6(*this),
- m_read_x7(*this),
- m_read_x8(*this),
- m_read_shift(*this),
- m_read_control(*this),
- m_write_data_ready(*this),
- m_write_ako(*this)
-{
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void ay3600_device::device_start()
-{
- // resolve callbacks
- m_read_x0.resolve_safe(0);
- m_read_x1.resolve_safe(0);
- m_read_x2.resolve_safe(0);
- m_read_x3.resolve_safe(0);
- m_read_x4.resolve_safe(0);
- m_read_x5.resolve_safe(0);
- m_read_x6.resolve_safe(0);
- m_read_x7.resolve_safe(0);
- m_read_x8.resolve_safe(0);
- m_read_shift.resolve_safe(0);
- m_read_control.resolve_safe(0);
- m_write_data_ready.resolve_safe();
- m_write_ako.resolve_safe();
-
- // allocate timers
- m_scan_timer = timer_alloc();
- m_scan_timer->adjust(attotime::from_hz(60), 0, attotime::from_hz(60));
-
- // state saving
- save_item(NAME(m_b));
- save_item(NAME(m_ako));
- save_item(NAME(m_keys_down));
-}
-
-
-//-------------------------------------------------
-// device_start - device-specific reset
-//-------------------------------------------------
-
-void ay3600_device::device_reset()
-{
- m_ako = 0;
- for (int i = 0; i < MAX_KEYS_DOWN; i++)
- {
- m_keys_down[i] = -1;
- }
-}
-
-//-------------------------------------------------
-// device_timer - handler timer events
-//-------------------------------------------------
-
-void ay3600_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- int ako = 0;
-
- for (int x = 0; x < 9; x++)
- {
- UINT16 data = 0;
-
- switch(x)
- {
- case 0: data = m_read_x0(); break;
- case 1: data = m_read_x1(); break;
- case 2: data = m_read_x2(); break;
- case 3: data = m_read_x3(); break;
- case 4: data = m_read_x4(); break;
- case 5: data = m_read_x5(); break;
- case 6: data = m_read_x6(); break;
- case 7: data = m_read_x7(); break;
- case 8: data = m_read_x8(); break;
- }
-
- for (int y = 0; y < 10; y++)
- {
- int b = (x * 10) + y;
-
- if (b > 63)
- {
- b -= 64;
- b = 0x100 | b;
- }
-
- b |= (m_read_shift() << 6);
- b |= (m_read_control() << 7);
-
- if (BIT(data, y))
- {
- bool found = false;
-
- // is this key already down?
- for (int k = 0; k < MAX_KEYS_DOWN; k++)
- {
- if (b == m_keys_down[k])
- {
- found = true;
- break;
- }
- }
-
- if (!found)
- {
- ako = 1;
-
- if (m_b != b)
- {
- m_b = b;
-
- m_write_data_ready(1);
- return;
- }
-
- // add to the keys down list
- for (int k = 0; k < MAX_KEYS_DOWN; k++)
- {
- if (m_keys_down[k] == -1)
- {
- m_keys_down[k] = b;
- break;
- }
- }
- }
- }
- else // key released, unmark it from the keys_down table
- {
- for (int k = 0; k < MAX_KEYS_DOWN; k++)
- {
- if (b == m_keys_down[k])
- {
- m_keys_down[k] = -1;
- }
- }
- }
- }
- }
-
- if (!ako)
- {
- m_b = -1;
- }
-
- if (ako != m_ako)
- {
- m_write_ako(ako);
- m_ako = ako;
- }
-}
-
-
-//-------------------------------------------------
-// b_r -
-//-------------------------------------------------
-
-UINT16 ay3600_device::b_r()
-{
- UINT16 data = m_b;
-
- m_write_data_ready(0);
-
- return data;
-}
diff --git a/src/mess/machine/kb3600.h b/src/mess/machine/kb3600.h
deleted file mode 100644
index 003424ea8bf..00000000000
--- a/src/mess/machine/kb3600.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/**********************************************************************
-
- General Instruments AY-5-3600 Keyboard Encoder emulation
-
- Copyright MESS Team.
- Visit http://mamedev.org for licensing and usage restrictions.
-
-**********************************************************************
- _____ _____
- 1 |* \_/ | 40 X0
- 2 | | 39 X1
- 3 | | 38 X2
- 4 | | 37 X3
- 5 | | 36 X4
- B9 6 | | 35 X5
- B8 7 | | 34 X6
- B7 8 | | 33 X7
- B6 9 | | 32 X8
- B5 10 | AY-5-3600 | 31 DELAY NODE
- B4 11 | | 30 Vcc
- B3 12 | | 29 SHIFT
- B2 13 | | 28 CONTROL
- B1 14 | | 27 Vgg
- Vdd 15 | | 26 Y9
- DATA READY 16 | | 25 Y8
- Y0 17 | | 24 Y7
- Y1 18 | | 23 Y6
- Y2 19 | | 22 Y5
- Y3 20 |_____________| 21 Y4
-
- _____ _____
- Vcc 1 |* \_/ | 40 Vss
- B9 2 | | 39 Vgg
- B8 3 | | 38 _STCL?
- B7 4 | | 37 _MCLR
- TEST 5 | | 36 OSC
- B6 6 | | 35 CLK OUT
- B5 7 | | 34 X7
- B4 8 | | 33 X6
- B3 9 | | 32 X5
- B2 10 | AY-5-3600 | 31 X4
- B1 11 | PRO 002 | 30 X3
- X8 12 | | 29 X2
- AKO 13 | | 28 X1
- CTRL 14 | | 27 X0
- SHIFT 15 | | 26 Y9
- DATA READY 16 | | 25 Y8
- Y0 17 | | 24 Y7
- Y1 18 | | 23 Y6
- Y2 19 | | 22 Y5
- Y3 20 |_____________| 21 Y4
-
-**********************************************************************/
-
-#pragma once
-
-#ifndef __AY3600__
-#define __AY3600__
-
-#include "emu.h"
-
-
-
-//**************************************************************************
-// INTERFACE CONFIGURATION MACROS
-//**************************************************************************
-
-#define MCFG_AY3600_MATRIX_X0(_cb) \
- devcb = &ay3600_device::set_x0_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_MATRIX_X1(_cb) \
- devcb = &ay3600_device::set_x1_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_MATRIX_X2(_cb) \
- devcb = &ay3600_device::set_x2_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_MATRIX_X3(_cb) \
- devcb = &ay3600_device::set_x3_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_MATRIX_X4(_cb) \
- devcb = &ay3600_device::set_x4_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_MATRIX_X5(_cb) \
- devcb = &ay3600_device::set_x5_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_MATRIX_X6(_cb) \
- devcb = &ay3600_device::set_x6_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_MATRIX_X7(_cb) \
- devcb = &ay3600_device::set_x7_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_MATRIX_X8(_cb) \
- devcb = &ay3600_device::set_x8_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_SHIFT_CB(_cb) \
- devcb = &ay3600_device::set_shift_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_CONTROL_CB(_cb) \
- devcb = &ay3600_device::set_control_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_DATA_READY_CB(_cb) \
- devcb = &ay3600_device::set_data_ready_cb(*device, DEVCB2_##_cb);
-#define MCFG_AY3600_AKO_CB(_cb) \
- devcb = &ay3600_device::set_ako_cb(*device, DEVCB2_##_cb);
-
-//**************************************************************************
-// TYPE DEFINITIONS
-//**************************************************************************
-
-// ======================> ay3600_device
-
-class ay3600_device : public device_t
-{
-public:
- // construction/destruction
- ay3600_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- // public interface
- UINT16 b_r();
-
- template<class _Object> static devcb2_base &set_x0_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x0.set_callback(rd); }
- template<class _Object> static devcb2_base &set_x1_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x1.set_callback(rd); }
- template<class _Object> static devcb2_base &set_x2_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x2.set_callback(rd); }
- template<class _Object> static devcb2_base &set_x3_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x3.set_callback(rd); }
- template<class _Object> static devcb2_base &set_x4_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x4.set_callback(rd); }
- template<class _Object> static devcb2_base &set_x5_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x5.set_callback(rd); }
- template<class _Object> static devcb2_base &set_x6_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x6.set_callback(rd); }
- template<class _Object> static devcb2_base &set_x7_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x7.set_callback(rd); }
- template<class _Object> static devcb2_base &set_x8_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_x8.set_callback(rd); }
- template<class _Object> static devcb2_base &set_shift_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_shift.set_callback(rd); }
- template<class _Object> static devcb2_base &set_control_cb(device_t &device, _Object rd) { return downcast<ay3600_device &>(device).m_read_control.set_callback(rd); }
- template<class _Object> static devcb2_base &set_data_ready_cb(device_t &device, _Object wr) { return downcast<ay3600_device &>(device).m_write_data_ready.set_callback(wr); }
- template<class _Object> static devcb2_base &set_ako_cb(device_t &device, _Object wr) { return downcast<ay3600_device &>(device).m_write_ako.set_callback(wr); }
-
- devcb2_read16 m_read_x0, m_read_x1, m_read_x2, m_read_x3, m_read_x4, m_read_x5, m_read_x6, m_read_x7, m_read_x8;
- devcb2_read_line m_read_shift, m_read_control;
- devcb2_write_line m_write_data_ready, m_write_ako;
-
-protected:
- // device-level overrides
- virtual void device_start();
- virtual void device_reset();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
-
-private:
- static const int MAX_KEYS_DOWN = 4;
-
- int m_b; // output buffer
- int m_ako; // any key down
-
- int m_keys_down[MAX_KEYS_DOWN];
-
- // timers
- emu_timer *m_scan_timer; // keyboard scan timer
-};
-
-
-// device type definition
-extern const device_type AY3600;
-
-
-
-#endif
diff --git a/src/mess/machine/kr2376.c b/src/mess/machine/kr2376.c
deleted file mode 100644
index e9db28e7eff..00000000000
--- a/src/mess/machine/kr2376.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/**********************************************************************
-
- SMC KR2376 Keyboard Encoder emulation
-
- Copyright MESS Team.
- Visit http://mamedev.org for licensing and usage restrictions.
-
-**********************************************************************/
-
-#include "emu.h"
-#include "kr2376.h"
-
-static const UINT8 KR2376_KEY_CODES[3][8][11] =
-{
- // normal
- {
- // Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
- // NUL SOH STX ETX EOT ENQ ACK BEL DC1 P O X0
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x11, 0x50, 0x30 }, // X0
- // DLE K L N M NAK SYN ETB CAN EM SUB X1
- { 0x10, 0x4b, 0x4c, 0x4e, 0x4d, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a }, // X1
- // - FS GS RS US < > , SP . _ X2
- { 0x2d, 0x1c, 0x1d, 0x1e, 0x1f, 0x3c, 0x3e, 0x2c, 0x20, 0x2e, 0x5f }, // X2
- // 0 : p _ @ BS [ ] CR LF DEL X3
- { 0x30, 0x3a, 0x70, 0x5f, 0x40, 0x08, 0x5B, 0x5d, 0x0d, 0x0a, 0x7f }, // X3
- { 0x3b, 0x2f, 0x2e, 0x2c, 0x6d, 0x6e, 0x62, 0x76, 0x63, 0x78, 0x7a }, // X4
- { 0x6c, 0x6b, 0x6a, 0x68, 0x67, 0x66, 0x64, 0x73, 0x61, 0x0c, 0x1b }, // X5
- { 0x6f, 0x69, 0x75, 0x79, 0x74, 0x72, 0x65, 0x77, 0x71, 0x09, 0x0b }, // X6
- { 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x5e, 0x5c } // X7
- },
-
- // shift
- {
- // Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
- // NUL SOH STX ETX EOT ENQ ACK BEL DC1 @ _ X0
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x11, 0x40, 0x5f }, // X0
- // DLE [ \ ^ ] NAK SYN ETB CAN EM SUB X1
- { 0x10, 0x5b, 0x5c, 0x5e, 0x5d, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a }, // X1
- // = FS GS RS US < > , SP . _ X2
- { 0x3d, 0x1c, 0x1d, 0x1e, 0x1f, 0x3c, 0x3e, 0x2c, 0x20, 0x2e, 0x5f }, // X2
- // NUL * P DEL ` BS { } CR LF DEL X3
- { 0x00, 0x2a, 0x50, 0x7f, 0x60, 0x08, 0x7b, 0x7d, 0x0d, 0x0a, 0x7f }, // X3
- { 0x2b, 0x3f, 0x3e, 0x3c, 0x4d, 0x4e, 0x42, 0x56, 0x43, 0x58, 0x5a }, // X4
- { 0x4c, 0x4b, 0x4a, 0x48, 0x47, 0x46, 0x44, 0x53, 0x41, 0x0c, 0x1b }, // X5
- { 0x4f, 0x49, 0x55, 0x59, 0x54, 0x52, 0x45, 0x57, 0x51, 0x09, 0x0b }, // X6
- { 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x7e, 0x7c } // X7
- },
-
- // control
- {
- // Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
- // NUL SOH STX ETX EOT ENQ ACK BEL DC1 DLE SI X0
- { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x11, 0x10, 0x0f }, // X0
- // DLE VT FF SO CR NAK SYN ETB CAN EM SUB X1
- { 0x10, 0x0b, 0x0c, 0x0e, 0x0d, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a }, // X1
- // NUL FS GS RS US NUL NUL NUL SP NUL US X2
- { 0x00, 0x1c, 0x1d, 0x1e, 0x1f, 0x00, 0x00, 0x00, 0x20, 0x00, 0x1f }, // X2
- // NUL NUL DLE US NUL BS ESC GS CR LF DEL X3
- { 0x00, 0x00, 0x10, 0x1f, 0x00, 0x08, 0x1B, 0x1d, 0x0d, 0x0a, 0x7f }, // X3
- { 0x00, 0x00, 0x00, 0x00, 0x1d, 0x0e, 0x02, 0x16, 0x03, 0x18, 0x1a }, // X4
- { 0x0c, 0x0b, 0x0a, 0x08, 0x07, 0x06, 0x04, 0x13, 0x01, 0x0c, 0x1b }, // X5
- { 0x1f, 0x09, 0x15, 0x19, 0x14, 0x12, 0x05, 0x17, 0x11, 0x09, 0x0b }, // X6
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x1c } // X7
- }
-};
-
-
-const device_type KR2376 = &device_creator<kr2376_device>;
-
-kr2376_device::kr2376_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, KR2376, "SMC KR2376", tag, owner, clock, "kr2376", __FILE__)
-{
-}
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void kr2376_device::device_config_complete()
-{
- // inherit a copy of the static data
- const kr2376_interface *intf = reinterpret_cast<const kr2376_interface *>(static_config());
- if (intf != NULL)
- *static_cast<kr2376_interface *>(this) = *intf;
-
- // or initialize to defaults if none provided
- else
- {
- m_our_clock = 0;
- memset(&m_on_strobe_changed_cb, 0, sizeof(m_on_strobe_changed_cb));
- }
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void kr2376_device::device_start()
-{
- m_on_strobe_changed.resolve(m_on_strobe_changed_cb, *this);
-
- /* set initial values */
- m_ring11 = 0;
- m_ring8 = 0;
- m_modifiers = 0;
- m_strobe = 0;
- m_strobe_old = 0;
- m_parity = 0;
- m_data = 0;
- change_output_lines();
-
- /* create the timers */
- m_scan_timer = timer_alloc(TIMER_SCAN_TICK);
- m_scan_timer->adjust(attotime::zero, 0, attotime::from_hz(m_our_clock));
-
- /* register for state saving */
- save_item(NAME(m_ring11));
- save_item(NAME(m_ring8));
- save_item(NAME(m_modifiers));
- save_item(NAME(m_strobe));
- save_item(NAME(m_strobe_old));
- save_item(NAME(m_parity));
- save_item(NAME(m_data));
-}
-
-/*-------------------------------------------------
- set_input_pin - set an input pin
--------------------------------------------------*/
-void kr2376_device::set_input_pin( kr2376_input_pin_t pin, int data )
-{
- data = data ? 1 : 0;
- switch ( pin )
- {
- case KR2376_PII:
- case KR2376_DSII:
- m_pins[pin] = data;
- break;
- }
-}
-
-
-/*-------------------------------------------------
- get_output_pin - get the status of an output pin
--------------------------------------------------*/
-int kr2376_device::get_output_pin( kr2376_output_pin_t pin )
-{
- return m_pins[pin];
-}
-
-
-void kr2376_device::change_output_lines()
-{
- if (m_strobe != m_strobe_old)
- {
- m_strobe_old = m_strobe;
-
- if (m_strobe) // strobe 0 --> 1 transition
- {
- /* update parity */
- m_pins[KR2376_PO] = m_parity ^ m_pins[KR2376_PII];
- }
- m_pins[KR2376_SO] = m_strobe ^ m_pins[KR2376_DSII];
- if (!m_on_strobe_changed.isnull())
- m_on_strobe_changed(m_strobe ^ m_pins[KR2376_DSII]);
- }
-}
-
-void kr2376_device::clock_scan_counters()
-{
- /* ring counters inhibited while strobe active */
- if (!m_strobe)
- {
- m_ring11++;
- if (m_ring11 == 11)
- {
- m_ring11 = 0;
- m_ring8++;
- if (m_ring8 == 8)
- m_ring8 = 0;
- }
- }
-}
-
-void kr2376_device::detect_keypress()
-{
- static const char *const keynames[] = { "X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7" };
-
- if (ioport(keynames[m_ring8])->read() == (1 << m_ring11))
- {
- m_modifiers = ioport("MODIFIERS")->read();
-
- m_strobe = 1;
- /* strobe 0->1 transition, encode char and update parity */
- if (!m_strobe_old)
- {
- int i;
- int parbit;
- int shift = BIT(m_modifiers, 0);
- int control = BIT(m_modifiers, 1);
- int alpha = BIT(m_modifiers, 2);
- int table = 0;
-
- if (shift || alpha)
- table = 1;
- else if (control)
- table = 2;
-
- m_data = KR2376_KEY_CODES[table][m_ring8][m_ring11];
-
- /* Compute ODD parity */
- m_parity = m_data;
- parbit = 0;
- for (i=0; i<8; i++)
- parbit ^= (m_parity >> i) & 1;
- m_parity = parbit;
- }
- }
- else
- {
- m_strobe = 0;
- }
-}
-
-void kr2376_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- switch (id)
- {
- case TIMER_SCAN_TICK:
- change_output_lines();
- clock_scan_counters();
- detect_keypress();
- break;
- }
-}
-
-/* Keyboard Data */
-
-READ8_MEMBER( kr2376_device::data_r )
-{
- if (m_pins[KR2376_DSII])
- return m_data ^ 0xff;
- else
- return m_data;
-}
-
-/* Input Ports */
-
-INPUT_PORTS_START( kr2376 )
- PORT_START("X0")
- PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_UNUSED )
-
- PORT_START("X1")
- PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_UNUSED )
-
-
- PORT_START("X2")
- PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
- PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
- PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CHAR('_')
-
- PORT_START("X3")
- PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
- PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(':') PORT_CHAR('*')
- PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
- PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('`') PORT_CHAR('@')
- PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) PORT_NAME("Del")
- PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
- PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}')
- PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13) PORT_NAME("CR")
- PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_HOME) PORT_CHAR(UCHAR_MAMEKEY(HOME)) PORT_CHAR(10) PORT_NAME("LF")
- PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_UNUSED )
-
- PORT_START("X4")
- PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
- PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
- PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
- PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
- PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
- PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
- PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
- PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
- PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
- PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
- PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
-
-
- PORT_START("X5")
- PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
- PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
- PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
- PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
- PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('c') PORT_CHAR('G')
- PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
- PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
- PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
- PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
- PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_UNUSED )
- PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
-
-
- PORT_START("X6")
- PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
- PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
- PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
- PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
- PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
- PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
- PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
- PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
- PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
-
- PORT_START("X7")
- PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
- PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
- PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
- PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
- PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
- PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
- PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
- PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
- PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
- PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('^') PORT_CHAR('~')
- PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|')
-
- PORT_START("MODIFIERS")
- PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
- PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_MAMEKEY(LCONTROL)) PORT_CHAR(UCHAR_MAMEKEY(RCONTROL))
- PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
-INPUT_PORTS_END
-
-//-------------------------------------------------
-// input_ports - device-specific input ports
-//-------------------------------------------------
-
-ioport_constructor kr2376_device::device_input_ports() const
-{
- return INPUT_PORTS_NAME( kr2376 );
-} \ No newline at end of file
diff --git a/src/mess/machine/kr2376.h b/src/mess/machine/kr2376.h
deleted file mode 100644
index ad3bf02b4f7..00000000000
--- a/src/mess/machine/kr2376.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/**********************************************************************
-
- SMC KR2376 Keyboard Encoder emulation
-
- Copyright MESS Team.
- Visit http://mamedev.org for licensing and usage restrictions.
-
-**********************************************************************
- _____ _____
- Vcc 1 |* \_/ | 40 Frequency Control A
- Frequency Control B 2 | | 39 X0
- Frequency Control C 3 | | 38 X1
- Shift Input 4 | | 37 X2
- Control Input 5 | | 36 X3
- Parity Invert Input 6 | | 35 X4
- Parity Output 7 | | 34 X5
- Data Output B8 8 | | 33 X6
- Data Output B7 9 | | 32 X7
- Data Output B6 10 | KR2376 | 31 Y0
- Data Output B5 11 | | 30 Y1
- Data Output B4 12 | | 29 Y2
- Data Output B3 13 | | 28 Y3
- Data Output B2 14 | | 27 Y4
- Data Output B1 15 | | 26 Y5
- Strobe Output 16 | | 25 Y6
- Ground 17 | | 24 Y7
- Vgg 18 | | 23 Y8
- Strobe Control Input 19 | | 22 Y9
- Invert Input 20 |_____________| 21 Y10
-
-**********************************************************************/
-
-#ifndef __KR2376__
-#define __KR2376__
-
-/*
- * Input pins
- */
-enum kr2376_input_pin_t
-{
- KR2376_DSII=20, /* DSII - Pin 20 - Data & Strobe Invert Input */
- KR2376_PII=6 /* PII - Pin 6 - Parity Invert Input */
-};
-
-enum kr2376_output_pin_t
-{
- KR2376_SO=16, /* SO - Pin 16 - Strobe Output */
- KR2376_PO=7 /* PO - Pin 7 - Parity Output */
-};
-
-typedef void (*kr2376_on_strobe_changed_func) (device_t *device, int level);
-#define KR2376_ON_STROBE_CHANGED(name) void name(device_t *device, int level)
-
-/* interface */
-struct kr2376_interface
-{
- /* The clock of the chip (Typical 50 kHz) */
- int m_our_clock;
-
- /* This will be called for every change of the strobe pin (pin 16). Optional */
- devcb_write_line m_on_strobe_changed_cb;
-};
-
-class kr2376_device : public device_t,
- public kr2376_interface
-{
-public:
- kr2376_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
- ~kr2376_device() {}
-
- /* keyboard data */
- DECLARE_READ8_MEMBER( data_r );
-
- /* Set an input pin */
- void set_input_pin( kr2376_input_pin_t pin, int data );
-
- /* Get an output pin */
- int get_output_pin( kr2376_output_pin_t pin );
-
-protected:
- // device-level overrides
- virtual void device_config_complete();
- virtual void device_start();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
- virtual ioport_constructor device_input_ports() const;
-
-private:
- // internal state
- int m_pins[41];
-
- int m_ring11; /* sense input scan counter */
- int m_ring8; /* drive output scan counter */
- int m_modifiers; /* modifier inputs */
-
- int m_strobe; /* strobe output */
- int m_strobe_old;
- int m_parity;
- int m_data;
-
- /* timers */
- emu_timer *m_scan_timer; /* keyboard scan timer */
- devcb_resolved_write_line m_on_strobe_changed;
-
- enum
- {
- TIMER_SCAN_TICK
- };
-
- void change_output_lines();
- void clock_scan_counters();
- void detect_keypress();
-};
-
-extern const device_type KR2376;
-
-
-#define MCFG_KR2376_ADD(_tag, _intrf) \
- MCFG_DEVICE_ADD(_tag, KR2376, 0) \
- MCFG_DEVICE_CONFIG(_intrf)
-
-#define KR2376_INTERFACE(name) const kr2376_interface (name)=
-
-#endif
diff --git a/src/mess/machine/lh5810.c b/src/mess/machine/lh5810.c
deleted file mode 100644
index c64e478b17f..00000000000
--- a/src/mess/machine/lh5810.c
+++ /dev/null
@@ -1,192 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Sandro Ronco
-/**********************************************************************
-
- LH5810/LH5811 Input/Output Port Controller
-
- TODO:
- - serial data transfer
- - data transfer to the cassette tape
-
-**********************************************************************/
-
-#include "emu.h"
-#include "lh5810.h"
-
-//**************************************************************************
-// GLOBAL VARIABLES
-//**************************************************************************
-
-const device_type LH5810 = &device_creator<lh5810_device>;
-
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void lh5810_device::device_config_complete()
-{
- // inherit a copy of the static data
- const lh5810_interface *intf = reinterpret_cast<const lh5810_interface *>(static_config());
- if (intf != NULL)
- *static_cast<lh5810_interface *>(this) = *intf;
-
- // or initialize to defaults if none provided
- else
- {
- memset(&m_porta_r_cb, 0, sizeof(m_porta_r_cb));
- memset(&m_porta_w_cb, 0, sizeof(m_porta_w_cb));
- memset(&m_portb_r_cb, 0, sizeof(m_portb_r_cb));
- memset(&m_portb_w_cb, 0, sizeof(m_portb_w_cb));
- memset(&m_portc_w_cb, 0, sizeof(m_portc_w_cb));
- memset(&m_out_int_cb, 0, sizeof(m_out_int_cb));
- }
-}
-
-
-//**************************************************************************
-// LIVE DEVICE
-//**************************************************************************
-
-//-------------------------------------------------
-// lh5810_device - constructor
-//-------------------------------------------------
-
-lh5810_device::lh5810_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, LH5810, "LH5810", tag, owner, clock, "lh5810", __FILE__)
-{
-}
-
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void lh5810_device::device_start()
-{
- // resolve callbacks
- m_porta_r_func.resolve(m_porta_r_cb, *this);
- m_porta_w_func.resolve(m_porta_w_cb, *this);
- m_portb_r_func.resolve(m_portb_r_cb, *this);
- m_portb_w_func.resolve(m_portb_w_cb, *this);
- m_portc_w_func.resolve(m_portc_w_cb, *this);
- m_out_int_func.resolve(m_out_int_cb, *this);
-
- // register for state saving
- save_item(NAME(m_irq));
- save_item(NAME(m_reg));
-}
-
-
-//-------------------------------------------------
-// device_reset - device-specific reset
-//-------------------------------------------------
-
-void lh5810_device::device_reset()
-{
- memset(m_reg, 0, sizeof(m_reg));
- m_irq = 0;
-}
-
-
-//-------------------------------------------------
-// data_r - data read
-//-------------------------------------------------
-
-READ8_MEMBER( lh5810_device::data_r )
-{
- switch (offset)
- {
- case LH5810_U:
- case LH5810_L:
- case LH5810_G:
- case LH5810_DDA:
- case LH5810_DDB:
- case LH5810_OPC:
- case LH5820_F:
- return m_reg[offset];
-
- case LH5810_IF:
- if (BIT(m_portb_r_func(0) & ~m_reg[LH5810_DDB], 7))
- m_reg[offset] |= 2;
- else
- m_reg[offset] &= 0xfd;
-
- return m_reg[offset];
-
- case LH5810_MSK:
- return (m_reg[offset]&0x0f) | (m_irq<<4) | (BIT(m_reg[LH5810_OPB],7)<<5);
-
- case LH5810_OPA:
- m_reg[offset] = (m_reg[offset] & m_reg[LH5810_DDA]) | (m_porta_r_func(0) & ~m_reg[LH5810_DDA]);
- return m_reg[offset];
-
- case LH5810_OPB:
- m_reg[offset] = (m_reg[offset] & m_reg[LH5810_DDB]) | (m_portb_r_func(0) & ~m_reg[LH5810_DDB]);
- m_out_int_func((m_reg[offset] & 0x80 && m_reg[LH5810_MSK] & 0x02) ? ASSERT_LINE : CLEAR_LINE);
- return m_reg[offset];
-
- default:
- return 0x00;
- }
-}
-
-
-//-------------------------------------------------
-// data_w - data write
-//-------------------------------------------------
-
-WRITE8_MEMBER( lh5810_device::data_w )
-{
- switch (offset)
- {
- case LH5810_RESET:
- break;
-
- case LH5810_G:
- case LH5820_F:
- case LH5810_DDA:
- case LH5810_DDB:
- m_reg[offset] = data;
- break;
-
- case LH5810_U:
- //writing on U register clear the RD flag of IF register
- m_reg[LH5810_IF] &= 0xfb;
- m_reg[offset] = data;
- break;
-
- case LH5810_L:
- //writing on L register clear the TD flag of IF register
- m_reg[LH5810_IF] &= 0xf7;
- m_reg[offset] = data;
- break;
-
- case LH5810_MSK:
- m_reg[offset] = data & 0x0f;
- break;
-
- case LH5810_IF:
- //only bit 0 and 1 are writable
- m_reg[offset] = (m_reg[offset] & 0xfc) | (data & 0x03);
- break;
-
- case LH5810_OPA:
- m_reg[offset] = (data & m_reg[LH5810_DDA]) | (m_reg[offset] & ~m_reg[LH5810_DDA]);
- m_porta_w_func(0, m_reg[offset]);
- break;
-
- case LH5810_OPB:
- m_reg[offset] = (data & m_reg[LH5810_DDB]) | (m_reg[offset] & ~m_reg[LH5810_DDB]);
- m_portb_w_func(0, m_reg[offset]);
- m_out_int_func((m_reg[offset] & 0x80 && m_reg[LH5810_MSK] & 0x02) ? ASSERT_LINE : CLEAR_LINE);
- break;
-
- case LH5810_OPC:
- m_reg[offset] = data;
- m_portc_w_func(0, m_reg[offset]);
- break;
- }
-}
diff --git a/src/mess/machine/lh5810.h b/src/mess/machine/lh5810.h
deleted file mode 100644
index 3a5e9c5eee1..00000000000
--- a/src/mess/machine/lh5810.h
+++ /dev/null
@@ -1,99 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Sandro Ronco
-/**********************************************************************
-
- LH5810/LH5811 Input/Output Port Controller
-
-**********************************************************************/
-
-#pragma once
-
-#ifndef __LH5810__
-#define __LH5810__
-
-#include "emu.h"
-
-//*************************************************************************
-// MACROS / CONSTANTS
-//*************************************************************************
-
-enum
-{
- LH5810_RESET = 4,
- LH5810_U,
- LH5810_L,
- LH5820_F,
- LH5810_OPC,
- LH5810_G,
- LH5810_MSK,
- LH5810_IF,
- LH5810_DDA,
- LH5810_DDB,
- LH5810_OPA,
- LH5810_OPB
-};
-
-
-//*************************************************************************
-// INTERFACE CONFIGURATION MACROS
-//*************************************************************************
-
-#define MCFG_LH5810_ADD(_tag, _config) \
- MCFG_DEVICE_ADD((_tag), LH5810, 0) \
- MCFG_DEVICE_CONFIG(_config)
-
-
-
-//*************************************************************************
-// TYPE DEFINITIONS
-//*************************************************************************
-
-// ======================> lh5810_interface
-
-struct lh5810_interface
-{
- devcb_read8 m_porta_r_cb; //port A read
- devcb_write8 m_porta_w_cb; //port A write
- devcb_read8 m_portb_r_cb; //port B read
- devcb_write8 m_portb_w_cb; //port B write
- devcb_write8 m_portc_w_cb; //port C write
-
- devcb_write_line m_out_int_cb; //IRQ callback
-};
-
-// ======================> lh5810_device
-
-class lh5810_device : public device_t,
- public lh5810_interface
-{
-public:
- // construction/destruction
- lh5810_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- DECLARE_READ8_MEMBER( data_r );
- DECLARE_WRITE8_MEMBER( data_w );
-
-protected:
- // device-level overrides
- virtual void device_start();
- virtual void device_reset();
- virtual void device_config_complete();
-
-private:
-
- devcb_resolved_read8 m_porta_r_func;
- devcb_resolved_write8 m_porta_w_func;
- devcb_resolved_read8 m_portb_r_func;
- devcb_resolved_write8 m_portb_w_func;
- devcb_resolved_write8 m_portc_w_func;
- devcb_resolved_write_line m_out_int_func;
-
- UINT8 m_reg[0x10];
- UINT8 m_irq;
-};
-
-
-// device type definition
-extern const device_type LH5810;
-
-#endif
diff --git a/src/mess/machine/mb8795.c b/src/mess/machine/mb8795.c
deleted file mode 100644
index e56a2b97d51..00000000000
--- a/src/mess/machine/mb8795.c
+++ /dev/null
@@ -1,327 +0,0 @@
-
-#include "emu.h"
-#include "mb8795.h"
-
-const device_type MB8795 = &device_creator<mb8795_device>;
-
-DEVICE_ADDRESS_MAP_START(map, 8, mb8795_device)
- AM_RANGE(0x0, 0x0) AM_READWRITE(txstat_r, txstat_w)
- AM_RANGE(0x1, 0x1) AM_READWRITE(txmask_r, txmask_w)
- AM_RANGE(0x2, 0x2) AM_READWRITE(rxstat_r, rxstat_w)
- AM_RANGE(0x3, 0x3) AM_READWRITE(rxmask_r, rxmask_w)
- AM_RANGE(0x4, 0x4) AM_READWRITE(txmode_r, txmode_w)
- AM_RANGE(0x5, 0x5) AM_READWRITE(rxmode_r, rxmode_w)
- AM_RANGE(0x6, 0x6) AM_WRITE(reset_w)
- AM_RANGE(0x7, 0x7) AM_READ(tdc_lsb_r)
- AM_RANGE(0x8, 0xf) AM_READWRITE(mac_r, mac_w) // Mapping limitation, real is up to 0xd
-ADDRESS_MAP_END
-
-mb8795_device::mb8795_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, MB8795, "Fujitsu MB8795", tag, owner, clock, "mb8795", __FILE__),
- device_network_interface(mconfig, *this, 10)
-{
-}
-
-void mb8795_device::set_irq_cb(line_cb_t tx, line_cb_t rx)
-{
- irq_tx_cb = tx;
- irq_rx_cb = rx;
-}
-
-void mb8795_device::set_drq_cb(line_cb_t tx, line_cb_t rx)
-{
- drq_tx_cb = tx;
- drq_rx_cb = rx;
-}
-
-void mb8795_device::check_irq()
-{
- bool old_irq_tx = irq_tx;
- bool old_irq_rx = irq_rx;
- irq_tx = txstat & txmask;
- irq_rx = rxstat & rxmask;
- if(irq_tx != old_irq_tx && !irq_tx_cb.isnull())
- irq_tx_cb(irq_tx);
- if(irq_rx != old_irq_rx && !irq_rx_cb.isnull())
- irq_rx_cb(irq_rx);
-}
-
-void mb8795_device::device_start()
-{
- memset(mac, 0, 6);
- timer_tx = timer_alloc(TIMER_TX);
- timer_rx = timer_alloc(TIMER_RX);
-}
-
-void mb8795_device::device_reset()
-{
- txstat = EN_TXS_READY;
- txmask = 0x00;
- rxstat = 0x00;
- rxmask = 0x00;
- txmode = 0x00;
- rxmode = 0x00;
-
- drq_tx = drq_rx = false;
- irq_tx = irq_rx = false;
-
- txlen = rxlen = txcount = 0;
-
- set_promisc(true);
-
- start_send();
-}
-
-void mb8795_device::recv_cb(UINT8 *buf, int len)
-{
- memcpy(rxbuf, buf, len);
- rxlen = len;
- receive();
-}
-
-READ8_MEMBER(mb8795_device::txstat_r)
-{
- // logerror("%s: txstat_r %02x (%08x)\n", tag(), txstat, space.device().safe_pc());
- return txstat;
-}
-
-WRITE8_MEMBER(mb8795_device::txstat_w)
-{
- txstat = txstat & (0xf0 | ~data);
- check_irq();
- logerror("%s: txstat_w %02x (%08x)\n", tag(), txstat, space.device().safe_pc());
-}
-
-READ8_MEMBER(mb8795_device::txmask_r)
-{
- logerror("%s: txmask_r %02x (%08x)\n", tag(), txmask, space.device().safe_pc());
- return txmask;
-}
-
-WRITE8_MEMBER(mb8795_device::txmask_w)
-{
- txmask = data & 0xaf;
- check_irq();
- logerror("%s: txmask_w %02x (%08x)\n", tag(), txmask, space.device().safe_pc());
-}
-
-READ8_MEMBER(mb8795_device::rxstat_r)
-{
- logerror("%s: rxstat_r %02x (%08x)\n", tag(), rxstat, space.device().safe_pc());
- return rxstat;
-}
-
-WRITE8_MEMBER(mb8795_device::rxstat_w)
-{
- rxstat = rxstat & (0x70 | ~data);
- check_irq();
- logerror("%s: rxstat_w %02x (%08x)\n", tag(), rxstat, space.device().safe_pc());
-}
-
-READ8_MEMBER(mb8795_device::rxmask_r)
-{
- logerror("%s: rxmask_r %02x (%08x)\n", tag(), rxmask, space.device().safe_pc());
- return rxmask;
-}
-
-WRITE8_MEMBER(mb8795_device::rxmask_w)
-{
- rxmask = data & 0x9f;
- check_irq();
- logerror("%s: rxmask_w %02x (%08x)\n", tag(), rxmask, space.device().safe_pc());
-}
-
-READ8_MEMBER(mb8795_device::txmode_r)
-{
- logerror("%s: txmode_r %02x (%08x)\n", tag(), txmode, space.device().safe_pc());
- return txmode;
-}
-
-WRITE8_MEMBER(mb8795_device::txmode_w)
-{
- txmode = data;
- logerror("%s: txmode_w %02x (%08x)\n", tag(), txmode, space.device().safe_pc());
-}
-
-READ8_MEMBER(mb8795_device::rxmode_r)
-{
- logerror("%s: rxmode_r %02x (%08x)\n", tag(), rxmode, space.device().safe_pc());
- return rxmode;
-}
-
-WRITE8_MEMBER(mb8795_device::rxmode_w)
-{
- rxmode = data;
- logerror("%s: rxmode_w %02x (%08x)\n", tag(), rxmode, space.device().safe_pc());
-}
-
-WRITE8_MEMBER(mb8795_device::reset_w)
-{
- if(data & EN_RST_RESET)
- device_reset();
-}
-
-READ8_MEMBER(mb8795_device::tdc_lsb_r)
-{
- logerror("%s: tdc_lsb_r %02x (%08x)\n", tag(), txcount & 0xff, space.device().safe_pc());
- return txcount;
-}
-
-READ8_MEMBER(mb8795_device::mac_r)
-{
- if(offset < 6)
- return mac[offset];
- if(offset == 7) {
- logerror("%s: tdc_msb_r %02x (%08x)\n", tag(), txcount >> 8, space.device().safe_pc());
- return (txcount >> 8) & 0x3f;
- }
- return 0;
-}
-
-WRITE8_MEMBER(mb8795_device::mac_w)
-{
- if(offset < 6) {
- mac[offset] = data;
- set_mac((const char *)mac);
- }
-}
-
-void mb8795_device::start_send()
-{
- timer_tx->adjust(attotime::zero);
-}
-
-void mb8795_device::tx_dma_w(UINT8 data, bool eof)
-{
- txbuf[txlen++] = data;
- if(txstat & EN_TXS_READY) {
- txstat &= ~EN_TXS_READY;
- check_irq();
- }
-
- drq_tx = false;
- if(!drq_tx_cb.isnull())
- drq_tx_cb(drq_tx);
-
- if(eof) {
- logerror("%s: send packet, dest=%02x.%02x.%02x.%02x.%02x.%02x len=%04x loopback=%s\n", tag(),
- txbuf[0], txbuf[1], txbuf[2], txbuf[3], txbuf[4], txbuf[5],
- txlen,
- txmode & EN_TMD_LB_DISABLE ? "off" : "on");
-
- if(txlen > 1500)
- txlen = 1500; // Weird packet send on loopback test in the next
-
- if(!(txmode & EN_TMD_LB_DISABLE)) {
- memcpy(rxbuf, txbuf, txlen);
- rxlen = txlen;
- receive();
- }
- send(txbuf, txlen);
- txlen = 0;
- txstat |= EN_TXS_READY;
- txcount++;
- start_send();
- } else
- timer_tx->adjust(attotime::from_nsec(800));
-}
-
-void mb8795_device::rx_dma_r(UINT8 &data, bool &eof)
-{
- drq_rx = false;
- if(!drq_rx_cb.isnull())
- drq_rx_cb(drq_rx);
-
- if(rxlen) {
- data = rxbuf[0];
- rxlen--;
- memmove(rxbuf, rxbuf+1, rxlen);
- } else
- data = 0;
-
- if(rxlen) {
- timer_rx->adjust(attotime::from_nsec(800));
- eof = false;
- } else
- eof = true;
-}
-
-void mb8795_device::receive()
-{
- bool keep = false;
- switch(rxmode & EN_RMD_WHATRECV) {
- case EN_RMD_RECV_NONE:
- keep = false;
- break;
- case EN_RMD_RECV_NORMAL:
- keep = recv_is_broadcast() || recv_is_me() || recv_is_local_multicast();
- break;
- case EN_RMD_RECV_MULTI:
- keep = recv_is_broadcast() || recv_is_me() || recv_is_multicast();
- break;
- case EN_RMD_RECV_PROMISC:
- keep = true;
- break;
- }
- logerror("%s: received packet for %02x.%02x.%02x.%02x.%02x.%02x len=%04x, mode=%d -> %s\n", tag(),
- rxbuf[0], rxbuf[1], rxbuf[2], rxbuf[3], rxbuf[4], rxbuf[5],
- rxlen, rxmode & 3, keep ? "kept" : "dropped");
- if(!keep)
- rxlen = false;
- else {
- rxstat |= EN_RXS_OK;
- check_irq();
- timer_rx->adjust(attotime::zero);
- }
-}
-
-bool mb8795_device::recv_is_broadcast()
-{
- return
- rxbuf[0] == 0xff &&
- rxbuf[1] == 0xff &&
- rxbuf[2] == 0xff &&
- rxbuf[3] == 0xff &&
- rxbuf[4] == 0xff &&
- rxbuf[5] == 0xff;
-}
-
-bool mb8795_device::recv_is_me()
-{
- return
- rxbuf[0] == mac[0] &&
- rxbuf[1] == mac[1] &&
- rxbuf[2] == mac[2] &&
- rxbuf[3] == mac[3] &&
- rxbuf[4] == mac[4] &&
- ((rxmode & EN_RMD_ADDRSIZE) || rxbuf[5] == mac[5]);
-}
-
-bool mb8795_device::recv_is_local_multicast()
-{
- return
- (rxbuf[0] & 0x01) &&
- (rxbuf[0] & 0xfe) == mac[0] &&
- rxbuf[1] == mac[1] &&
- rxbuf[2] == mac[2];
-}
-
-bool mb8795_device::recv_is_multicast()
-{
- return rxbuf[0] & 0x01;
-}
-
-void mb8795_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- if(id == TIMER_TX) {
- drq_tx = true;
- if(!drq_tx_cb.isnull())
- drq_tx_cb(drq_tx);
- }
-
- if(id == TIMER_RX && rxlen) {
- drq_rx = true;
- if(!drq_rx_cb.isnull())
- drq_rx_cb(drq_rx);
- }
-}
diff --git a/src/mess/machine/mb8795.h b/src/mess/machine/mb8795.h
deleted file mode 100644
index 40cd1d6b156..00000000000
--- a/src/mess/machine/mb8795.h
+++ /dev/null
@@ -1,108 +0,0 @@
-#ifndef MB8795_H
-#define MB8795_H
-
-#define MCFG_MB8795_ADD(_tag, _tx_irq, _rx_irq, _tx_drq, _rx_drq) \
- MCFG_DEVICE_ADD(_tag, MB8795, 0) \
- downcast<mb8795_device *>(device)->set_irq_cb(_tx_irq, _rx_irq); \
- downcast<mb8795_device *>(device)->set_drq_cb(_tx_drq, _rx_drq);
-
-class mb8795_device : public device_t,
- public device_network_interface
-{
-public:
- mb8795_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- void set_irq_cb(line_cb_t tx, line_cb_t rx);
- void set_drq_cb(line_cb_t tx, line_cb_t rx);
-
- DECLARE_ADDRESS_MAP(map, 8);
-
- DECLARE_READ8_MEMBER(txstat_r);
- DECLARE_WRITE8_MEMBER(txstat_w);
- DECLARE_READ8_MEMBER(txmask_r);
- DECLARE_WRITE8_MEMBER(txmask_w);
- DECLARE_READ8_MEMBER(rxstat_r);
- DECLARE_WRITE8_MEMBER(rxstat_w);
- DECLARE_READ8_MEMBER(rxmask_r);
- DECLARE_WRITE8_MEMBER(rxmask_w);
- DECLARE_READ8_MEMBER(txmode_r);
- DECLARE_WRITE8_MEMBER(txmode_w);
- DECLARE_READ8_MEMBER(rxmode_r);
- DECLARE_WRITE8_MEMBER(rxmode_w);
- DECLARE_WRITE8_MEMBER(reset_w);
- DECLARE_READ8_MEMBER(tdc_lsb_r);
- DECLARE_READ8_MEMBER(mac_r);
- DECLARE_WRITE8_MEMBER(mac_w);
-
- void tx_dma_w(UINT8 data, bool eof);
- void rx_dma_r(UINT8 &data, bool &eof);
-
-protected:
- virtual void device_start();
- virtual void device_reset();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
-
- virtual void recv_cb(UINT8 *buf, int len);
-
-private:
- enum { TIMER_TX, TIMER_RX };
-
- // Lifted from netbsd
- enum {
- EN_TXS_READY = 0x80, /* ready for packet */
- EN_TXS_BUSY = 0x40, /* receive carrier detect */
- EN_TXS_TXRECV = 0x20, /* transmission received */
- EN_TXS_SHORTED = 0x10, /* possible coax short */
- EN_TXS_UNDERFLOW = 0x08, /* underflow on xmit */
- EN_TXS_COLLERR = 0x04, /* collision detected */
- EN_TXS_COLLERR16 = 0x02, /* 16th collision error */
- EN_TXS_PARERR = 0x01, /* parity error in tx data */
-
- EN_RXS_OK = 0x80, /* packet received ok */
- EN_RXS_RESET = 0x10, /* reset packet received */
- EN_RXS_SHORT = 0x08, /* < minimum length */
- EN_RXS_ALIGNERR = 0x04, /* alignment error */
- EN_RXS_CRCERR = 0x02, /* CRC error */
- EN_RXS_OVERFLOW = 0x01, /* receiver FIFO overflow */
-
- EN_TMD_COLLMASK = 0xf0, /* collision count */
- EN_TMD_COLLSHIFT = 4,
- EN_TMD_PARIGNORE = 0x08, /* ignore parity */
- EN_TMD_TURBO1 = 0x04,
- EN_TMD_LB_DISABLE = 0x02, /* loop back disabled */
- EN_TMD_DISCONTENT = 0x01, /* disable contention (rx carrier) */
-
- EN_RMD_TEST = 0x80, /* must be zero */
- EN_RMD_ADDRSIZE = 0x10, /* reduces NODE match to 5 chars */
- EN_RMD_SHORTENABLE = 0x08, /* "rx packets >= 10 bytes" - <? */
- EN_RMD_RESETENABLE = 0x04, /* detect "reset" ethernet frames */
- EN_RMD_WHATRECV = 0x03, /* controls what packets are received */
- EN_RMD_RECV_PROMISC = 0x03, /* all packets */
- EN_RMD_RECV_MULTI = 0x02, /* accept broad/multicasts */
- EN_RMD_RECV_NORMAL = 0x01, /* accept broad/limited multicasts */
- EN_RMD_RECV_NONE = 0x00, /* accept no packets */
-
- EN_RST_RESET = 0x80 /* reset interface */
- };
-
- UINT8 mac[6];
- UINT8 txbuf[2000], rxbuf[2000];
- UINT8 txstat, txmask, rxstat, rxmask, txmode, rxmode;
- UINT16 txlen, rxlen, txcount;
- bool drq_tx, drq_rx, irq_tx, irq_rx;
- emu_timer *timer_tx, *timer_rx;
-
- line_cb_t irq_tx_cb, irq_rx_cb, drq_tx_cb, drq_rx_cb;
-
- void check_irq();
- void start_send();
- void receive();
- bool recv_is_broadcast();
- bool recv_is_me();
- bool recv_is_multicast();
- bool recv_is_local_multicast();
-};
-
-extern const device_type MB8795;
-
-#endif
diff --git a/src/mess/machine/mb89352.c b/src/mess/machine/mb89352.c
deleted file mode 100644
index 43ab2365122..00000000000
--- a/src/mess/machine/mb89352.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/*
- * Fujitsu MB89352A SCSI Protocol Controller
- *
- * Should be compatible with the MB87030/31, and MB89351
- *
- * Used on the Sharp X68000 Super, X68000 XVI and X68030 (internal), and on SCSI expansion cards for any X680x0 (external)
- *
- * Registers (based on datasheet):
- *
- * 0: BDID (Bus Device ID)
- * bit = device ID (ie: bit 2 = device 2) (read)
- * bit 0 = ID1, bit 1 = ID2, bit 2 = ID4 (write)
- *
- * 1: SCTL (SPC Control)
- * (all read/write)
- * bit 0 = INT Enable
- * bit 1 = Reselect Enable
- * bit 2 = Select Enable
- * bit 3 = Parity Enable
- * bit 4 = Arbitration Phase Enable
- * bit 5 = Diag Mode
- * bit 6 = Control Reset
- * bit 7 = Reset and Disable
- *
- * 2: SCMD (Command)
- * bits 0-2 = Transfer Modifier (read)
- * bit 0 = Term Mode (write)
- * bit 2 = PRG Xfer (write)
- * bit 3 = Intercept Xfer (read/write)
- * bit 4 = RST Out (read/write)
- * bits 5-7 = Command code (read/write) (would have been nice if these codes were mentioned in the datasheet...)
- * 000 = Bus release
- * 001 = Selection
- * 010 = Reset ATN
- * 011 = Set ATN
- * 100 = Transfer
- * 101 = Transfer Pause
- * 110 = Reset ACK/REQ
- * 111 = Set ACK/REQ
- *
- * 3: Unused
- *
- * 4: INTS (Interrupt Sense)
- * on write, clear interrupt
- * on read:
- * bit 0 = Reset Condition
- * bit 1 = SPC Hard Error
- * bit 2 = Timeout
- * bit 3 = Service Required
- * bit 4 = Command Complete
- * bit 5 = Disconnect
- * bit 6 = Reselected
- * bit 7 = Selected
- *
- * 5: PSNS (Phase Sense) (read-only)
- * b7 b0
- * | REQ | ACK | ATN | SEL | BSY | MSG | C/D | I/O |
- * SDGC (SPC Diag. Control) (write-only)
- * bit 5 = Xfer Enable
- * bit 4 = Unused
- * all other bits are Diag. of the matching inputs above.
- *
- * 6: SSTS (SPC Status) (read-only)
- * bit 0 = DREG Empty
- * bit 1 = DREG Full
- * bit 2 = TC=0
- * bit 3 = SCSI RST
- * bit 4 = Xfer in progress
- * bit 5 = SPC BSY
- * bit 6 = Connected to Target
- * bit 7 = Connected to Initiator
- *
- * 7: SERR (SCSI Error Status) (read-only)
- * bit 1 = Short Transfer Period
- * bit 3 = TC Parity Error
- * bit 5 = Xfer Out (related to SDGC bit 5)
- * bits 6,7 = Data error (10 = undefined, 00 = no error, 01 and 11 = parity error)
- *
- * 8: PCTL (Phase Control)
- * (read/write)
- * bits 0-2 = transfer phase ( | MSG | C/D | I/O | )
- * bits 7 = Bus Free interrupt enable
- * other bits read 0
- *
- * 9: MBC (Modified Byte Counter)
- * (read-only)
- * bits 0-3 = MBC bits 0-3
- * other bits read 0
- *
- * A: DREG (Data Register)
- * 8-bit FIFO
- *
- * B: TEMP (Temporary Register)
- * on read, from SCSI
- * on write, to SCSI
- *
- * C, D, E: TCH, TCM, TCL (Transfer Counter High, Mid, Low)
- * 24-bit transfer counter
- *
- */
-
-#include "emu.h"
-#include "mb89352.h"
-
-/*
- * Device config
- */
-
-const device_type MB89352A = &device_creator<mb89352_device>;
-
-
-void mb89352_device::device_config_complete()
-{
- // copy static configuration if present
- const mb89352_interface *intf = reinterpret_cast<const mb89352_interface *>(static_config());
- if (intf != NULL)
- *static_cast<mb89352_interface *>(this) = *intf;
-
- // otherwise, initialize it to defaults
- else
- {
- memset(&irq_callback,0,sizeof(irq_callback));
- memset(&drq_callback,0,sizeof(drq_callback));
- }
-}
-
-/*
- * Device
- */
-
-mb89352_device::mb89352_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, MB89352A, "MB89352A", tag, owner, clock, "mb89352", __FILE__)
-{
-}
-
-void mb89352_device::device_start()
-{
- m_phase = SCSI_PHASE_BUS_FREE;
- m_target = 0;
- m_command_index = 0;
- m_line_status = 0x00;
- m_spc_status = 0x01; // presumably the data reg is empty to start with
- m_error_status = 0x00;
- m_transfer_count = 0;
- if(m_transfer_count == 0)
- m_spc_status |= SSTS_TC_ZERO;
- m_ints = 0x00;
-
- m_irq_func.resolve(irq_callback,*this);
- m_drq_func.resolve(drq_callback,*this);
-
- memset(m_SCSIdevices,0,sizeof(m_SCSIdevices));
-
- // allocate read timer
- m_transfer_timer = timer_alloc(TIMER_TRANSFER);
-
- // try to open the devices
- for( device_t *device = owner()->first_subdevice(); device != NULL; device = device->next() )
- {
- scsihle_device *scsidev = dynamic_cast<scsihle_device *>(device);
- if( scsidev != NULL )
- {
- m_SCSIdevices[scsidev->GetDeviceID()] = scsidev;
- }
- }
-}
-
-void mb89352_device::device_reset()
-{
- m_phase = SCSI_PHASE_BUS_FREE;
- m_target = 0;
- m_command_index = 0;
- m_line_status = 0x00;
- m_error_status = 0x00;
- m_transfer_count = 0;
- m_spc_status = 0x05; // presumably the data reg is empty to start with
- m_busfree_int_enable = 0;
-}
-
-void mb89352_device::device_stop()
-{
-}
-
-// get the length of a SCSI command based on it's command byte type
-int mb89352_device::get_scsi_cmd_len(UINT8 cbyte)
-{
- int group;
-
- group = (cbyte>>5) & 7;
-
- if (group == 0) return 6;
- if (group == 1 || group == 2) return 10;
- if (group == 5) return 12;
-
- fatalerror("MB89352: Unknown SCSI command group %d\n", group);
-
- return 6;
-}
-
-void mb89352_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- switch(id)
- {
- case TIMER_TRANSFER:
- // TODO: check interrupts are actually enabled
- {
- m_drq_func(1);
- }
- break;
- }
-}
-
-void mb89352_device::set_phase(int phase)
-{
- m_phase = phase;
- switch(phase)
- {
- case SCSI_PHASE_BUS_FREE:
- m_line_status = 0;
- m_spc_status &= ~SSTS_XFER_IN_PROGRESS;
- break;
- case SCSI_PHASE_COMMAND:
- m_line_status |= MB89352_LINE_REQ;
- m_line_status &= ~MB89352_LINE_ACK;
- m_line_status &= ~MB89352_LINE_MSG;
- m_line_status |= MB89352_LINE_CD;
- m_line_status &= ~MB89352_LINE_IO;
- break;
- case SCSI_PHASE_STATUS:
-// m_line_status |= MB89352_LINE_REQ;
-// m_line_status &= ~MB89352_LINE_ACK;
- m_line_status &= ~MB89352_LINE_MSG;
- m_line_status |= MB89352_LINE_CD;
- m_line_status |= MB89352_LINE_IO;
- break;
- case SCSI_PHASE_DATAIN:
-// m_line_status |= MB89352_LINE_REQ;
-// m_line_status &= ~MB89352_LINE_ACK;
- m_line_status &= ~MB89352_LINE_MSG;
- m_line_status &= ~MB89352_LINE_CD;
- m_line_status |= MB89352_LINE_IO;
- break;
- case SCSI_PHASE_DATAOUT:
-// m_line_status |= MB89352_LINE_REQ;
-// m_line_status &= ~MB89352_LINE_ACK;
- m_line_status &= ~MB89352_LINE_MSG;
- m_line_status &= ~MB89352_LINE_CD;
- m_line_status &= ~MB89352_LINE_IO;
- break;
- case SCSI_PHASE_MESSAGE_IN:
-// m_line_status |= MB89352_LINE_REQ;
-// m_line_status &= ~MB89352_LINE_ACK;
- m_line_status |= MB89352_LINE_MSG;
- m_line_status |= MB89352_LINE_CD;
- m_line_status |= MB89352_LINE_IO;
- break;
- case SCSI_PHASE_MESSAGE_OUT:
-// m_line_status |= MB89352_LINE_REQ;
-// m_line_status &= ~MB89352_LINE_ACK;
- m_line_status |= MB89352_LINE_MSG;
- m_line_status |= MB89352_LINE_CD;
- m_line_status &= ~MB89352_LINE_IO;
- break;
- }
- logerror("MB89352: phase set to %i\n",m_phase);
-}
-
-int mb89352_device::get_phase(void)
-{
- return m_phase;
-}
-
-READ8_MEMBER( mb89352_device::mb89352_r )
-{
- UINT8 ret;
- switch(offset & 0x0f)
- {
- case 0x00: // BDID - Bus Device ID
- return (1 << m_bdid);
- case 0x01: // SCTL - SPC Control
- ret = 0x00;
- if(m_arbit_enable)
- ret |= 0x10;
- if(m_parity_enable)
- ret |= 0x08;
- if(m_sel_enable)
- ret |= 0x04;
- if(m_resel_enable)
- ret |= 0x02;
- if(m_int_enable)
- ret |= 0x01;
- return ret;
- case 0x02: // SCMD - Command
- return m_scmd;
- case 0x03: // Unused
- return 0xff;
- case 0x04: // INTS - Interrupt Sense
- return m_ints;
- case 0x05: // PSNS - Phase Sense
- return m_line_status; // active low -- but Human68k expects it to be zero?
- case 0x06: // SSTS - SPC Status
- return m_spc_status;
- case 0x07: // SERR - SPC Error Status
- /* #define SERR_SCSI_PAR 0x80
- #define SERR_SPC_PAR 0x40
- #define SERR_TC_PAR 0x08
- #define SERR_PHASE_ERR 0x04
- #define SERR_SHORT_XFR 0x02
- #define SERR_OFFSET 0x01*/
- return 0;
- case 0x08: // PCTL - Phase Control
- return ((m_busfree_int_enable) ? (m_line_status & 0x07) | 0x80 : (m_line_status & 0x07));
- case 0x0a: // DREG - Data register (for data transfers)
- if(m_spc_status & SSTS_XFER_IN_PROGRESS)
- {
- m_data = m_buffer[m_transfer_index % 512];
- m_transfer_index++;
- m_transfer_count--;
- if(m_transfer_index % 512 == 0)
- m_SCSIdevices[m_target]->ReadData(m_buffer,512);
- if(m_transfer_count == 0)
- {
- // End of transfer
- m_spc_status &= ~SSTS_XFER_IN_PROGRESS;
- m_spc_status |= SSTS_DREG_EMPTY;
- m_ints |= INTS_COMMAND_COMPLETE;
- if(m_int_enable != 0)
- m_irq_func(1);
- if(m_phase == SCSI_PHASE_MESSAGE_IN)
- set_phase(SCSI_PHASE_BUS_FREE);
- else if(m_phase == SCSI_PHASE_DATAIN)
- set_phase(SCSI_PHASE_STATUS);
- }
- }
- return m_data;
- case 0x0b: // TEMP - Temporary
- logerror("mb89352: read temporary register.\n");
- return m_temp;
- case 0x0c: // TCH - Transfer Counter High
- return (m_transfer_count & 0x00ff0000) >> 16;
- case 0x0d: // TCM - Transfer Counter Mid
- return (m_transfer_count & 0x0000ff00) >> 8;
- case 0x0e: // TCL - Transfer Counter Low
- return (m_transfer_count & 0x000000ff);
- default:
- logerror("mb89352: read from register %02x\n",offset & 0x0f);
- }
- return 0xff;
-}
-
-WRITE8_MEMBER( mb89352_device::mb89352_w )
-{
- switch(offset & 0x0f)
- {
- case 0x00: // BDID - Bus Device ID
- m_bdid = data;
- m_spc_status &= ~SSTS_TARG_CONNECTED;
- m_spc_status |= SSTS_INIT_CONNECTED;
- logerror("mb89352: BDID set to %i\n",data);
- break;
- case 0x01: // SCTL - SPC Control
- if(data & 0x80) // reset and disable
- {
- device_reset();
- logerror("mb89352: SCTL: Reset and disable.\n");
- }
- if(data & 0x10)
- {
- m_arbit_enable = 1;
- logerror("mb89352: SCTL: Arbitration enabled.\n");
- }
- else
- m_arbit_enable = 0;
- if(data & 0x08)
- {
- m_parity_enable = 1;
- logerror("mb89352: SCTL: Parity enabled.\n");
- }
- else
- m_parity_enable = 0;
- if(data & 0x04)
- {
- m_sel_enable = 1;
- logerror("mb89352: SCTL: Selection enabled.\n");
- }
- else
- m_sel_enable = 0;
- if(data & 0x02)
- {
- m_resel_enable = 1;
- logerror("mb89352: SCTL: Reselection enabled.\n");
- }
- else
- m_resel_enable = 0;
- if(data & 0x01)
- {
- m_int_enable = 1;
- logerror("mb89352: SCTL: Interrupts enabled.\n");
- }
- else
- {
- m_int_enable = 0;
- logerror("mb89352: SCTL: Interrupts disabled.\n");
- }
- break;
- case 0x02: // SCMD - Command
- /* From NetBSD/x68k source
- #define SCMD_BUS_REL 0x00
- #define SCMD_SELECT 0x20
- #define SCMD_RST_ATN 0x40
- #define SCMD_SET_ATN 0x60
- #define SCMD_XFR 0x80
- #define SCMD_XFR_PAUSE 0xa0
- #define SCMD_RST_ACK 0xc0
- #define SCMD_SET_ACK 0xe0
- */
- m_scmd = data;
- switch((data & 0xe0) >> 5)
- {
- case 0x00:
- // Bus Free
- m_line_status = 0;
- m_spc_status &= ~SSTS_TARG_CONNECTED;
- m_spc_status &= ~SSTS_INIT_CONNECTED;
- m_spc_status &= ~SSTS_XFER_IN_PROGRESS;
- set_phase(SCSI_PHASE_BUS_FREE);
- if(m_busfree_int_enable)
- {
- if(m_int_enable != 0)
- m_irq_func(1);
- }
- logerror("mb89352: SCMD: Bus free\n");
- break;
- case 0x01:
- // Selection
- m_target = m_temp;
- m_target &= ~(1 << m_bdid); // mask off the bit relating to initiator
- switch(m_target)
- {
- case 0x01: m_target = 0; break;
- case 0x02: m_target = 1; break;
- case 0x04: m_target = 2; break;
- case 0x08: m_target = 3; break;
- case 0x10: m_target = 4; break;
- case 0x20: m_target = 5; break;
- case 0x40: m_target = 6; break;
- case 0x80: m_target = 7; break;
- }
- if(m_sel_enable != 0)
- {
- //m_ints |= INTS_SELECTION;
- }
- set_phase(SCSI_PHASE_COMMAND); // straight to command phase, may need a delay between selection and command phases
- m_line_status |= MB89352_LINE_SEL;
- m_line_status |= MB89352_LINE_BSY;
- m_spc_status &= ~SSTS_TARG_CONNECTED;
- m_spc_status |= SSTS_INIT_CONNECTED;
- m_spc_status |= SSTS_SPC_BSY;
- m_ints |= INTS_COMMAND_COMPLETE;
- if(m_int_enable != 0)
- m_irq_func(1);
- logerror("mb89352: SCMD: Selection (SCSI ID%i)\n",m_target);
- break;
- case 0x02: // Reset ATN
- m_line_status &= ~MB89352_LINE_ATN;
- logerror("mb89352: SCMD: Reset ATN\n");
- break;
- case 0x03: // Set ATN
- m_line_status |= MB89352_LINE_ATN;
- logerror("mb89352: SCMD: Set ATN\n");
- break;
- case 0x04: // Transfer
- m_transfer_index = 0;
- m_spc_status |= SSTS_XFER_IN_PROGRESS;
- if(m_phase == SCSI_PHASE_DATAIN) // if we are reading data...
- {
- m_spc_status &= ~SSTS_DREG_EMPTY; // DREG is no longer empty
- m_SCSIdevices[m_target]->ReadData(m_buffer,512);
- }
- if(m_phase == SCSI_PHASE_MESSAGE_IN)
- {
- m_spc_status &= ~SSTS_DREG_EMPTY; // DREG is no longer empty
- m_data = 0;
- m_temp = 0x00;
- set_phase(SCSI_PHASE_BUS_FREE);
- m_spc_status &= ~SSTS_XFER_IN_PROGRESS;
- m_command_index = 0;
- }
- logerror("mb89352: SCMD: Start Transfer\n");
- break;
- case 0x05: // Transfer pause
- logerror("mb89352: SCMD: Pause Transfer\n");
- break;
- case 0x06: // reset REQ/ACK
- m_line_status &= ~MB89352_LINE_ACK;
- if(m_phase != SCSI_PHASE_BUS_FREE)
- {
- m_line_status |= MB89352_LINE_REQ;
- }
- else
- {
- m_spc_status &= ~SSTS_INIT_CONNECTED;
- m_spc_status &= ~SSTS_TARG_CONNECTED;
- m_spc_status &= ~SSTS_SPC_BSY;
- }
- logerror("mb89352: SCMD: Reset REQ/ACK\n");
- break;
- case 0x07: // set REQ/ACK
- m_line_status &= ~MB89352_LINE_REQ;
- m_line_status |= MB89352_LINE_ACK;
- logerror("mb89352: SCMD: Set REQ/ACK\n");
- if(m_phase == SCSI_PHASE_COMMAND)
- {
- m_command[m_command_index++] = m_temp; // temp register puts data onto the SCSI bus
- if(m_command_index >= get_scsi_cmd_len(m_command[0]))
- {
- int x;
- int phase;
- // execute SCSI command
- m_SCSIdevices[m_target]->SetCommand(m_command,m_command_index);
- m_SCSIdevices[m_target]->ExecCommand();
- m_SCSIdevices[m_target]->GetLength(&m_result_length);
- m_SCSIdevices[m_target]->GetPhase(&phase);
- if(m_command[0] == 1) // Rezero Unit - not implemented in SCSI code
- set_phase(SCSI_PHASE_STATUS);
- else
- set_phase(phase);
- logerror("Command executed: ");
- for(x=0;x<m_command_index;x++)
- logerror(" %02x",m_command[x]);
- logerror("\n");
- }
- return;
- }
- if(m_phase == SCSI_PHASE_STATUS)
- {
- void *image;
- m_SCSIdevices[m_target]->GetDevice(&image);
- if (image != NULL)
- m_temp = 0x00;
- else
- m_temp = 0x02;
- set_phase(SCSI_PHASE_MESSAGE_IN);
- return;
- }
- if(m_phase == SCSI_PHASE_MESSAGE_IN)
- {
- m_temp = 0x00;
- set_phase(SCSI_PHASE_BUS_FREE);
- m_command_index = 0;
- return;
- }
- break;
- default:
- logerror("mb89352: SCMD: Unimplemented command %02x\n",(data & 0xe0) >> 5);
- break;
- }
- break;
- case 0x04: // INTS - Interrupt Sense
- m_ints &= ~data; // resets relevant status bits to zero
- m_irq_func(0); // clear IRQ
- logerror("mb89352: Reset INTS status bits %02x\n",data);
- break;
- case 0x08: // PCTL - Phase control
- if((data & 0x80) == 0 && (m_phase == SCSI_PHASE_SELECT)) // if writing 0 to bit 7, selection phase is reset
- {
- m_ints &= ~INTS_SELECTION;
- m_target = 0;
- logerror("mb89352: PCTL selection cancelled\n");
- }
- // writing to the low 3 bits sets the phase
- if((m_phase & 0x07) != (data & 0x07))
- set_phase(data & 0x07);
- m_busfree_int_enable = data & 0x80;
- logerror("mb89352: PCTL write %02x\n",data);
- break;
- case 0x0a: // DREG - Data register
- if(m_phase == SCSI_PHASE_COMMAND)
- {
- m_command[m_command_index++] = data;
- if(m_command_index >= get_scsi_cmd_len(m_command[0]))
- {
- int x;
- int phase;
- // execute SCSI command
- m_SCSIdevices[m_target]->SetCommand(m_command,m_command_index);
- m_SCSIdevices[m_target]->ExecCommand();
- m_SCSIdevices[m_target]->GetLength(&m_result_length);
- m_SCSIdevices[m_target]->GetPhase(&phase);
- if(m_command[0] == 1) // Rezero Unit - not implemented in SCSI code
- set_phase(SCSI_PHASE_STATUS);
- else
- set_phase(phase);
- logerror("Command executed: ");
- for(x=0;x<m_command_index;x++)
- logerror(" %02x",m_command[x]);
- logerror("\n");
- }
- return;
- }
- if(m_spc_status & SSTS_XFER_IN_PROGRESS)
- {
- m_buffer[m_transfer_index % 512] = data;
- m_spc_status |= SSTS_DREG_EMPTY; // DREG is empty once sent
- m_transfer_index++;
- m_transfer_count--;
- if(m_transfer_index % 512 == 0)
- m_SCSIdevices[m_target]->WriteData(m_buffer,512);
- if(m_transfer_count == 0)
- {
- // End of transfer
- m_spc_status &= ~SSTS_XFER_IN_PROGRESS;
- m_spc_status |= SSTS_DREG_EMPTY;
- m_ints |= INTS_COMMAND_COMPLETE;
- if(m_int_enable != 0)
- m_irq_func(1);
- set_phase(SCSI_PHASE_STATUS);
- }
- }
- break;
- case 0x0b: // TEMP - Temporary
- m_temp = data;
- logerror("mb89352: Write %02x to temporary register\n",data);
- break;
- case 0x0c: // TCH - Transfer Counter High
- m_transfer_count = (m_transfer_count & 0x0000ffff) | (data << 16);
- if(m_transfer_count == 0)
- m_spc_status |= SSTS_TC_ZERO;
- else
- m_spc_status &= ~SSTS_TC_ZERO;
- logerror("mb89352: TCH: Write %02x [%06x]\n",data,m_transfer_count);
- break;
- case 0x0d: // TCM - Transfer Counter Mid
- m_transfer_count = (m_transfer_count & 0x00ff00ff) | (data << 8);
- if(m_transfer_count == 0)
- m_spc_status |= SSTS_TC_ZERO;
- else
- m_spc_status &= ~SSTS_TC_ZERO;
- logerror("mb89352: TCM: Write %02x [%06x]\n",data,m_transfer_count);
- break;
- case 0x0e: // TCL - Transfer Counter Low
- m_transfer_count = (m_transfer_count & 0x00ffff00) | data;
- if(m_transfer_count == 0)
- m_spc_status |= SSTS_TC_ZERO;
- else
- m_spc_status &= ~SSTS_TC_ZERO;
- logerror("mb89352: TCL: Write %02x [%06x]\n",data,m_transfer_count);
- break;
- default:
- logerror("mb89352: write %02x to register %02x\n",data,offset & 0x0f);
- }
-}
diff --git a/src/mess/machine/mb89352.h b/src/mess/machine/mb89352.h
deleted file mode 100644
index 91618e083c6..00000000000
--- a/src/mess/machine/mb89352.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * mb89352.h
- *
- * Created on: 16/01/2011
- */
-
-#ifndef MB89352_H_
-#define MB89352_H_
-
-#include "machine/scsihle.h"
-
-// SCSI lines readable via PSNS register (reg 5)
-#define MB89352_LINE_REQ 0x80
-#define MB89352_LINE_ACK 0x40
-#define MB89352_LINE_ATN 0x20
-#define MB89352_LINE_SEL 0x10
-#define MB89352_LINE_BSY 0x08
-#define MB89352_LINE_MSG 0x04
-#define MB89352_LINE_CD 0x02
-#define MB89352_LINE_IO 0x01
-
-// INTS bits
-#define INTS_RESET 0x01
-#define INTS_HARD_ERROR 0x02
-#define INTS_TIMEOUT 0x04
-#define INTS_SERVICE_REQUIRED 0x08
-#define INTS_COMMAND_COMPLETE 0x10
-#define INTS_DISCONNECTED 0x20
-#define INTS_RESELECTION 0x40
-#define INTS_SELECTION 0x80
-
-// SSTS status bits
-#define SSTS_DREG_EMPTY 0x01
-#define SSTS_DREG_FULL 0x02
-#define SSTS_TC_ZERO 0x04
-#define SSTS_SCSI_RST 0x08
-#define SSTS_XFER_IN_PROGRESS 0x10
-#define SSTS_SPC_BSY 0x20
-#define SSTS_TARG_CONNECTED 0x40
-#define SSTS_INIT_CONNECTED 0x80
-
-// SERR error status bits
-#define SERR_OFFSET 0x01
-#define SERR_SHORT_XFR 0x02
-#define SERR_PHASE_ERR 0x04
-#define SERR_TC_PAR 0x08
-#define SERR_SPC_PAR 0x40
-#define SERR_SCSI_PAR 0x80
-
-
-struct mb89352_interface
-{
- devcb_write_line irq_callback; /* irq callback */
- devcb_write_line drq_callback; /* drq callback */
-};
-
-#define MCFG_MB89352A_ADD(_tag, _intrf) \
- MCFG_DEVICE_ADD(_tag, MB89352A, 0) \
- MCFG_DEVICE_CONFIG(_intrf)
-
-class mb89352_device : public device_t,
- public mb89352_interface
-{
-public:
- // construction/destruction
- mb89352_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- // any publically accessible interfaces needed for runtime
- DECLARE_READ8_MEMBER( mb89352_r );
- DECLARE_WRITE8_MEMBER( mb89352_w );
-
- void set_phase(int phase);
- int get_phase(void);
-
-protected:
- // device-level overrides (none are required, but these are common)
- virtual void device_start();
- virtual void device_reset();
- virtual void device_stop();
- virtual void device_config_complete();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
-
-private:
- // internal device state goes here
- static const device_timer_id TIMER_TRANSFER = 0;
-
- int get_scsi_cmd_len(UINT8 cbyte);
- //void set_ints(UINT8 flag);
-
- devcb_resolved_write_line m_irq_func;
- devcb_resolved_write_line m_drq_func;
-
- scsihle_device* m_SCSIdevices[8];
-
- UINT8 m_phase; // current SCSI phase
- UINT8 m_target; // current SCSI target
- UINT8 m_bdid; // Bus device ID (SCSI ID of the bus?)
- UINT8 m_ints; // Interrupt Sense
- UINT8 m_temp; // Temporary register (To/From SCSI bus)
- UINT8 m_data; // Data register
- UINT8 m_scmd; // SPC Command register
- UINT32 m_transfer_count; // byte transfer counter, also used as a timeout counter for selection.
- UINT8 m_int_enable;
- UINT8 m_sel_enable;
- UINT8 m_resel_enable;
- UINT8 m_parity_enable;
- UINT8 m_arbit_enable;
- UINT8 m_busfree_int_enable;
- UINT8 m_line_status;
- UINT8 m_spc_status;
- UINT8 m_error_status;
- UINT8 m_command_index;
- UINT8 m_command[16];
- UINT32 m_transfer_index;
- int m_result_length;
- UINT8 m_buffer[512];
-
- emu_timer* m_transfer_timer;
-};
-
-extern const device_type MB89352A;
-
-#endif /* MB89352_H_ */
diff --git a/src/mess/machine/mc68328.c b/src/mess/machine/mc68328.c
deleted file mode 100644
index 66ed87d71c0..00000000000
--- a/src/mess/machine/mc68328.c
+++ /dev/null
@@ -1,2907 +0,0 @@
-/**********************************************************************
-
- Motorola 68328 ("DragonBall") System-on-a-Chip implementation
-
- By MooglyGuy
- contact mooglyguy@gmail.com with licensing and usage questions.
-
-**********************************************************************/
-
-#include "emu.h"
-#include "cpu/m68000/m68000.h"
-#include "machine/mc68328.h"
-#include "machine/ram.h"
-
-#define VERBOSE_LEVEL (0)
-
-INLINE void ATTR_PRINTF(3,4) verboselog(running_machine &machine, int n_level, const char *s_fmt, ...)
-{
- if (VERBOSE_LEVEL >= n_level)
- {
- va_list v;
- char buf[32768];
- va_start(v, s_fmt);
- vsprintf(buf, s_fmt, v);
- va_end(v);
- logerror("%s: %s", machine.describe_context(), buf);
- }
-}
-
-const device_type MC68328 = &device_creator<mc68328_device>;
-
-
-mc68328_device::mc68328_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, MC68328, "Motorola MC68328 (DragonBall) Integrated Processor", tag, owner, clock, "mc68328", __FILE__)
-{
-}
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void mc68328_device::device_config_complete()
-{
- // inherit a copy of the static data
- const mc68328_interface *intf = reinterpret_cast<const mc68328_interface *>(static_config());
- if (intf != NULL)
- *static_cast<mc68328_interface *>(this) = *intf;
-
- // or initialize to defaults if none provided
- else
- {
- memset(&m_out_port_a_func, 0, sizeof(m_out_port_a_func));
- memset(&m_out_port_b_func, 0, sizeof(m_out_port_b_func));
- memset(&m_out_port_c_func, 0, sizeof(m_out_port_c_func));
- memset(&m_out_port_d_func, 0, sizeof(m_out_port_d_func));
- memset(&m_out_port_e_func, 0, sizeof(m_out_port_e_func));
- memset(&m_out_port_f_func, 0, sizeof(m_out_port_f_func));
- memset(&m_out_port_g_func, 0, sizeof(m_out_port_g_func));
- memset(&m_out_port_j_func, 0, sizeof(m_out_port_j_func));
- memset(&m_out_port_k_func, 0, sizeof(m_out_port_k_func));
- memset(&m_out_port_m_func, 0, sizeof(m_out_port_m_func));
- memset(&m_in_port_a_func, 0, sizeof(m_in_port_a_func));
- memset(&m_in_port_b_func, 0, sizeof(m_in_port_b_func));
- memset(&m_in_port_c_func, 0, sizeof(m_in_port_c_func));
- memset(&m_in_port_d_func, 0, sizeof(m_in_port_d_func));
- memset(&m_in_port_e_func, 0, sizeof(m_in_port_e_func));
- memset(&m_in_port_f_func, 0, sizeof(m_in_port_f_func));
- memset(&m_in_port_g_func, 0, sizeof(m_in_port_g_func));
- memset(&m_in_port_j_func, 0, sizeof(m_in_port_j_func));
- memset(&m_in_port_k_func, 0, sizeof(m_in_port_k_func));
- memset(&m_in_port_m_func, 0, sizeof(m_in_port_m_func));
- memset(&m_out_pwm_func, 0, sizeof(m_out_pwm_func));
- memset(&m_out_spim_func, 0, sizeof(m_out_spim_func));
- memset(&m_in_spim_func, 0, sizeof(m_in_spim_func));
- memset(&m_spim_xch_trigger_func, 0, sizeof(m_spim_xch_trigger_func));
- m68k_cpu_tag = "";
- }
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void mc68328_device::device_start()
-{
- m_out_port_a.resolve(m_out_port_a_func, *this);
- m_out_port_b.resolve(m_out_port_b_func, *this);
- m_out_port_c.resolve(m_out_port_c_func, *this);
- m_out_port_d.resolve(m_out_port_d_func, *this);
- m_out_port_e.resolve(m_out_port_e_func, *this);
- m_out_port_f.resolve(m_out_port_f_func, *this);
- m_out_port_g.resolve(m_out_port_g_func, *this);
- m_out_port_j.resolve(m_out_port_j_func, *this);
- m_out_port_k.resolve(m_out_port_k_func, *this);
- m_out_port_m.resolve(m_out_port_m_func, *this);
-
- m_in_port_a.resolve(m_in_port_a_func, *this);
- m_in_port_b.resolve(m_in_port_b_func, *this);
- m_in_port_c.resolve(m_in_port_c_func, *this);
- m_in_port_d.resolve(m_in_port_d_func, *this);
- m_in_port_e.resolve(m_in_port_e_func, *this);
- m_in_port_f.resolve(m_in_port_f_func, *this);
- m_in_port_g.resolve(m_in_port_g_func, *this);
- m_in_port_j.resolve(m_in_port_j_func, *this);
- m_in_port_k.resolve(m_in_port_k_func, *this);
- m_in_port_m.resolve(m_in_port_m_func, *this);
-
- m_out_pwm.resolve(m_out_pwm_func, *this);
-
- m_out_spim.resolve(m_out_spim_func, *this);
- m_in_spim.resolve(m_in_spim_func, *this);
-
- m_spim_xch_trigger.resolve(m_spim_xch_trigger_func, *this);
-
- m_cpu = machine().device<cpu_device>(m68k_cpu_tag);
-
- m_gptimer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::timer1_hit),this));
- m_gptimer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::timer2_hit),this));
- m_rtc = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::rtc_tick),this));
- m_pwm = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::pwm_transition),this));
-
- register_state_save();
-}
-
-//-------------------------------------------------
-// device_reset - device-specific reset
-//-------------------------------------------------
-
-void mc68328_device::device_reset()
-{
- m_regs.scr = 0x0c;
- m_regs.grpbasea = 0x0000;
- m_regs.grpbaseb = 0x0000;
- m_regs.grpbasec = 0x0000;
- m_regs.grpbased = 0x0000;
- m_regs.grpmaska = 0x0000;
- m_regs.grpmaskb = 0x0000;
- m_regs.grpmaskc = 0x0000;
- m_regs.grpmaskd = 0x0000;
- m_regs.csa0 = 0x00010006;
- m_regs.csa1 = 0x00010006;
- m_regs.csa2 = 0x00010006;
- m_regs.csa3 = 0x00010006;
- m_regs.csb0 = 0x00010006;
- m_regs.csb1 = 0x00010006;
- m_regs.csb2 = 0x00010006;
- m_regs.csb3 = 0x00010006;
- m_regs.csc0 = 0x00010006;
- m_regs.csc1 = 0x00010006;
- m_regs.csc2 = 0x00010006;
- m_regs.csc3 = 0x00010006;
- m_regs.csd0 = 0x00010006;
- m_regs.csd1 = 0x00010006;
- m_regs.csd2 = 0x00010006;
- m_regs.csd3 = 0x00010006;
-
- m_regs.pllcr = 0x2400;
- m_regs.pllfsr = 0x0123;
- m_regs.pctlr = 0x1f;
-
- m_regs.ivr = 0x00;
- m_regs.icr = 0x0000;
- m_regs.imr = 0x00ffffff;
- m_regs.iwr = 0x00ffffff;
- m_regs.isr = 0x00000000;
- m_regs.ipr = 0x00000000;
-
- m_regs.padir = 0x00;
- m_regs.padata = 0x00;
- m_regs.pasel = 0x00;
- m_regs.pbdir = 0x00;
- m_regs.pbdata = 0x00;
- m_regs.pbsel = 0x00;
- m_regs.pcdir = 0x00;
- m_regs.pcdata = 0x00;
- m_regs.pcsel = 0x00;
- m_regs.pddir = 0x00;
- m_regs.pddata = 0x00;
- m_regs.pdpuen = 0xff;
- m_regs.pdpol = 0x00;
- m_regs.pdirqen = 0x00;
- m_regs.pddataedge = 0x00;
- m_regs.pdirqedge = 0x00;
- m_regs.pedir = 0x00;
- m_regs.pedata = 0x00;
- m_regs.pepuen = 0x80;
- m_regs.pesel = 0x80;
- m_regs.pfdir = 0x00;
- m_regs.pfdata = 0x00;
- m_regs.pfpuen = 0xff;
- m_regs.pfsel = 0xff;
- m_regs.pgdir = 0x00;
- m_regs.pgdata = 0x00;
- m_regs.pgpuen = 0xff;
- m_regs.pgsel = 0xff;
- m_regs.pjdir = 0x00;
- m_regs.pjdata = 0x00;
- m_regs.pjsel = 0x00;
- m_regs.pkdir = 0x00;
- m_regs.pkdata = 0x00;
- m_regs.pkpuen = 0xff;
- m_regs.pksel = 0xff;
- m_regs.pmdir = 0x00;
- m_regs.pmdata = 0x00;
- m_regs.pmpuen = 0xff;
- m_regs.pmsel = 0xff;
-
- m_regs.pwmc = 0x0000;
- m_regs.pwmp = 0x0000;
- m_regs.pwmw = 0x0000;
- m_regs.pwmcnt = 0x0000;
-
- m_regs.tctl[0] = m_regs.tctl[1] = 0x0000;
- m_regs.tprer[0] = m_regs.tprer[1] = 0x0000;
- m_regs.tcmp[0] = m_regs.tcmp[1] = 0xffff;
- m_regs.tcr[0] = m_regs.tcr[1] = 0x0000;
- m_regs.tcn[0] = m_regs.tcn[1] = 0x0000;
- m_regs.tstat[0] = m_regs.tstat[1] = 0x0000;
- m_regs.wctlr = 0x0000;
- m_regs.wcmpr = 0xffff;
- m_regs.wcn = 0x0000;
-
- m_regs.spisr = 0x0000;
-
- m_regs.spimdata = 0x0000;
- m_regs.spimcont = 0x0000;
-
- m_regs.ustcnt = 0x0000;
- m_regs.ubaud = 0x003f;
- m_regs.urx = 0x0000;
- m_regs.utx = 0x0000;
- m_regs.umisc = 0x0000;
-
- m_regs.lssa = 0x00000000;
- m_regs.lvpw = 0xff;
- m_regs.lxmax = 0x03ff;
- m_regs.lymax = 0x01ff;
- m_regs.lcxp = 0x0000;
- m_regs.lcyp = 0x0000;
- m_regs.lcwch = 0x0101;
- m_regs.lblkc = 0x7f;
- m_regs.lpicf = 0x00;
- m_regs.lpolcf = 0x00;
- m_regs.lacdrc = 0x00;
- m_regs.lpxcd = 0x00;
- m_regs.lckcon = 0x40;
- m_regs.llbar = 0x3e;
- m_regs.lotcr = 0x3f;
- m_regs.lposr = 0x00;
- m_regs.lfrcm = 0xb9;
- m_regs.lgpmr = 0x1073;
-
- m_regs.hmsr = 0x00000000;
- m_regs.alarm = 0x00000000;
- m_regs.rtcctl = 0x00;
- m_regs.rtcisr = 0x00;
- m_regs.rtcienr = 0x00;
- m_regs.stpwtch = 0x00;
-
- m_rtc->adjust(attotime::from_hz(1), 0, attotime::from_hz(1));
-}
-
-
-void mc68328_device::set_interrupt_line(UINT32 line, UINT32 active)
-{
- if (active)
- {
- m_regs.ipr |= line;
-
- if (!(m_regs.imr & line) && !(m_regs.isr & line))
- {
- m_regs.isr |= line;
-
- if (m_regs.isr & INT_M68K_LINE7)
- {
- m_cpu->set_input_line_and_vector(M68K_IRQ_7, ASSERT_LINE, m_regs.ivr | 0x07);
- }
- else if (m_regs.isr & INT_M68K_LINE6)
- {
- m_cpu->set_input_line_and_vector(M68K_IRQ_6, ASSERT_LINE, m_regs.ivr | 0x06);
- }
- else if (m_regs.isr & INT_M68K_LINE5)
- {
- m_cpu->set_input_line_and_vector(M68K_IRQ_5, ASSERT_LINE, m_regs.ivr | 0x05);
- }
- else if (m_regs.isr & INT_M68K_LINE4)
- {
- m_cpu->set_input_line_and_vector(M68K_IRQ_4, ASSERT_LINE, m_regs.ivr | 0x04);
- }
- else if (m_regs.isr & INT_M68K_LINE3)
- {
- m_cpu->set_input_line_and_vector(M68K_IRQ_3, ASSERT_LINE, m_regs.ivr | 0x03);
- }
- else if (m_regs.isr & INT_M68K_LINE2)
- {
- m_cpu->set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, m_regs.ivr | 0x02);
- }
- else if (m_regs.isr & INT_M68K_LINE1)
- {
- m_cpu->set_input_line_and_vector(M68K_IRQ_1, ASSERT_LINE, m_regs.ivr | 0x01);
- }
- }
- }
- else
- {
- m_regs.isr &= ~line;
-
- if ((line & INT_M68K_LINE7) && !(m_regs.isr & INT_M68K_LINE7))
- {
- m_cpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
- }
- if ((line & INT_M68K_LINE6) && !(m_regs.isr & INT_M68K_LINE6))
- {
- m_cpu->set_input_line(M68K_IRQ_6, CLEAR_LINE);
- }
- if ((line & INT_M68K_LINE5) && !(m_regs.isr & INT_M68K_LINE5))
- {
- m_cpu->set_input_line(M68K_IRQ_5, CLEAR_LINE);
- }
- if ((line & INT_M68K_LINE4) && !(m_regs.isr & INT_M68K_LINE4))
- {
- m_cpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
- }
- if ((line & INT_M68K_LINE3) && !(m_regs.isr & INT_M68K_LINE3))
- {
- m_cpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
- }
- if ((line & INT_M68K_LINE2) && !(m_regs.isr & INT_M68K_LINE2))
- {
- m_cpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
- }
- if ((line & INT_M68K_LINE1) && !(m_regs.isr & INT_M68K_LINE1))
- {
- m_cpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
- }
- }
-}
-
-void mc68328_device::poll_port_d_interrupts()
-{
- UINT8 line_transitions = m_regs.pddataedge & m_regs.pdirqedge;
- UINT8 line_holds = m_regs.pddata &~ m_regs.pdirqedge;
- UINT8 line_interrupts = (line_transitions | line_holds) & m_regs.pdirqen;
-
- if (line_interrupts)
- {
- set_interrupt_line(line_interrupts << 8, 1);
- }
- else
- {
- set_interrupt_line(INT_KBDINTS, 0);
- }
-}
-
-WRITE_LINE_MEMBER( mc68328_device::set_penirq_line )
-{
- if (state)
- {
- set_interrupt_line(INT_PEN, 1);
- }
- else
- {
- m_regs.ipr &= ~INT_PEN;
- set_interrupt_line(INT_PEN, 0);
- }
-}
-
-void mc68328_device::set_port_d_lines(UINT8 state, int bit)
-{
- UINT8 old_button_state = m_regs.pddata;
-
- if (state & (1 << bit))
- {
- m_regs.pddata |= (1 << bit);
- }
- else
- {
- m_regs.pddata &= ~(1 << bit);
- }
-
- m_regs.pddataedge |= ~old_button_state & m_regs.pddata;
-
- poll_port_d_interrupts();
-}
-
-UINT32 mc68328_device::get_timer_frequency(UINT32 index)
-{
- UINT32 frequency = 0;
-
- switch (m_regs.tctl[index] & TCTL_CLKSOURCE)
- {
- case TCTL_CLKSOURCE_SYSCLK:
- frequency = 32768 * 506;
- break;
-
- case TCTL_CLKSOURCE_SYSCLK16:
- frequency = (32768 * 506) / 16;
- break;
-
- case TCTL_CLKSOURCE_32KHZ4:
- case TCTL_CLKSOURCE_32KHZ5:
- case TCTL_CLKSOURCE_32KHZ6:
- case TCTL_CLKSOURCE_32KHZ7:
- frequency = 32768;
- break;
- }
- frequency /= (m_regs.tprer[index] + 1);
-
- return frequency;
-}
-
-void mc68328_device::maybe_start_timer(UINT32 index, UINT32 new_enable)
-{
- if ((m_regs.tctl[index] & TCTL_TEN) == TCTL_TEN_ENABLE && (m_regs.tctl[index] & TCTL_CLKSOURCE) > TCTL_CLKSOURCE_STOP)
- {
- if ((m_regs.tctl[index] & TCTL_CLKSOURCE) == TCTL_CLKSOURCE_TIN)
- {
- m_gptimer[index]->adjust(attotime::never);
- }
- else if (m_regs.tcmp[index] == 0)
- {
- m_gptimer[index]->adjust(attotime::never);
- }
- else
- {
- UINT32 frequency = get_timer_frequency(index);
- attotime period = (attotime::from_hz(frequency) * m_regs.tcmp[index]);
-
- if (new_enable)
- {
- m_regs.tcn[index] = 0x0000;
- }
-
- m_gptimer[index]->adjust(period);
- }
- }
- else
- {
- m_gptimer[index]->adjust(attotime::never);
- }
-}
-
-void mc68328_device::timer_compare_event(UINT32 index)
-{
- m_regs.tcn[index] = m_regs.tcmp[index];
- m_regs.tstat[index] |= TSTAT_COMP;
-
- if ((m_regs.tctl[index] & TCTL_FRR) == TCTL_FRR_RESTART)
- {
- UINT32 frequency = get_timer_frequency(index);
-
- if (frequency > 0)
- {
- attotime period = attotime::from_hz(frequency) * m_regs.tcmp[index];
-
- m_regs.tcn[index] = 0x0000;
-
- m_gptimer[index]->adjust(period);
- }
- else
- {
- m_gptimer[index]->adjust(attotime::never);
- }
- }
- else
- {
- UINT32 frequency = get_timer_frequency(index);
-
- if (frequency > 0)
- {
- attotime period = attotime::from_hz(frequency) * 0x10000;
-
- m_gptimer[index]->adjust(period);
- }
- else
- {
- m_gptimer[index]->adjust(attotime::never);
- }
- }
- if ((m_regs.tctl[index] & TCTL_IRQEN) == TCTL_IRQEN_ENABLE)
- {
- set_interrupt_line((index == 0) ? INT_TIMER1 : INT_TIMER2, 1);
- }
-}
-
-TIMER_CALLBACK_MEMBER( mc68328_device::timer1_hit )
-{
- timer_compare_event(0);
-}
-
-TIMER_CALLBACK_MEMBER( mc68328_device::timer2_hit )
-{
- timer_compare_event(1);
-}
-
-TIMER_CALLBACK_MEMBER( mc68328_device::pwm_transition )
-{
- if (m_regs.pwmw >= m_regs.pwmp || m_regs.pwmw == 0 || m_regs.pwmp == 0)
- {
- m_pwm->adjust(attotime::never);
- return;
- }
-
- if (((m_regs.pwmc & PWMC_POL) == 0 && (m_regs.pwmc & PWMC_PIN) != 0) ||
- ((m_regs.pwmc & PWMC_POL) != 0 && (m_regs.pwmc & PWMC_PIN) == 0))
- {
- UINT32 frequency = 32768 * 506;
- UINT32 divisor = 4 << (m_regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
- attotime period;
-
- frequency /= divisor;
- period = attotime::from_hz(frequency) * (m_regs.pwmp - m_regs.pwmw);
-
- m_pwm->adjust(period);
-
- if (m_regs.pwmc & PWMC_IRQEN)
- {
- set_interrupt_line(INT_PWM, 1);
- }
- }
- else
- {
- UINT32 frequency = 32768 * 506;
- UINT32 divisor = 4 << (m_regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
- attotime period;
-
- frequency /= divisor;
- period = attotime::from_hz(frequency) * m_regs.pwmw;
-
- m_pwm->adjust(period);
- }
-
- m_regs.pwmc ^= PWMC_PIN;
-
- if (!m_out_pwm.isnull())
- {
- m_out_pwm(0, (m_regs.pwmc & PWMC_PIN) ? 1 : 0);
- }
-}
-
-TIMER_CALLBACK_MEMBER( mc68328_device::rtc_tick )
-{
- if (m_regs.rtcctl & RTCCTL_ENABLE)
- {
- UINT32 set_int = 0;
-
- m_regs.hmsr++;
-
- if (m_regs.rtcienr & RTCINT_SECOND)
- {
- set_int = 1;
- m_regs.rtcisr |= RTCINT_SECOND;
- }
-
- if ((m_regs.hmsr & 0x0000003f) == 0x0000003c)
- {
- m_regs.hmsr &= 0xffffffc0;
- m_regs.hmsr += 0x00010000;
-
- if (m_regs.rtcienr & RTCINT_MINUTE)
- {
- set_int = 1;
- m_regs.rtcisr |= RTCINT_MINUTE;
- }
-
- if ((m_regs.hmsr & 0x003f0000) == 0x003c0000)
- {
- m_regs.hmsr &= 0xffc0ffff;
- m_regs.hmsr += 0x0100000;
-
- if ((m_regs.hmsr & 0x1f000000) == 0x18000000)
- {
- m_regs.hmsr &= 0xe0ffffff;
-
- if (m_regs.rtcienr & RTCINT_DAY)
- {
- set_int = 1;
- m_regs.rtcisr |= RTCINT_DAY;
- }
- }
- }
-
- if (m_regs.stpwtch != 0x003f)
- {
- m_regs.stpwtch--;
- m_regs.stpwtch &= 0x003f;
-
- if (m_regs.stpwtch == 0x003f)
- {
- if (m_regs.rtcienr & RTCINT_STOPWATCH)
- {
- set_int = 1;
- m_regs.rtcisr |= RTCINT_STOPWATCH;
- }
- }
- }
- }
-
- if (m_regs.hmsr == m_regs.alarm)
- {
- if (m_regs.rtcienr & RTCINT_ALARM)
- {
- set_int = 1;
- m_regs.rtcisr |= RTCINT_STOPWATCH;
- }
- }
-
- if (set_int)
- {
- set_interrupt_line(INT_RTC, 1);
- }
- else
- {
- set_interrupt_line(INT_RTC, 0);
- }
- }
-}
-
-WRITE16_MEMBER( mc68328_device::write )
-{
- UINT32 address = offset << 1;
- UINT16 temp16[4] = { 0 };
- UINT32 imr_old = m_regs.imr, imr_diff;
-
- switch (address)
- {
- case 0x000:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff001) = %02x\n", data & 0x00ff);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: SCR = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0x100:
- verboselog(machine(), 2, "mc68328_w: GRPBASEA = %04x\n", data);
- m_regs.grpbasea = data;
- break;
-
- case 0x102:
- verboselog(machine(), 2, "mc68328_w: GRPBASEB = %04x\n", data);
- m_regs.grpbaseb = data;
- break;
-
- case 0x104:
- verboselog(machine(), 2, "mc68328_w: GRPBASEC = %04x\n", data);
- m_regs.grpbasec = data;
- break;
-
- case 0x106:
- verboselog(machine(), 2, "mc68328_w: GRPBASED = %04x\n", data);
- m_regs.grpbased = data;
- break;
-
- case 0x108:
- verboselog(machine(), 2, "mc68328_w: GRPMASKA = %04x\n", data);
- m_regs.grpmaska = data;
- break;
-
- case 0x10a:
- verboselog(machine(), 2, "mc68328_w: GRPMASKB = %04x\n", data);
- m_regs.grpmaskb = data;
- break;
-
- case 0x10c:
- verboselog(machine(), 2, "mc68328_w: GRPMASKC = %04x\n", data);
- m_regs.grpmaskc = data;
- break;
-
- case 0x10e:
- verboselog(machine(), 2, "mc68328_w: GRPMASKD = %04x\n", data);
- m_regs.grpmaskd = data;
- break;
-
- case 0x110:
- verboselog(machine(), 5, "mc68328_w: CSA0(0) = %04x\n", data);
- m_regs.csa0 &= 0xffff0000 | (~mem_mask);
- m_regs.csa0 |= data & mem_mask;
- break;
-
- case 0x112:
- verboselog(machine(), 5, "mc68328_w: CSA0(16) = %04x\n", data);
- m_regs.csa0 &= ~(mem_mask << 16);
- m_regs.csa0 |= (data & mem_mask) << 16;
- break;
-
- case 0x114:
- verboselog(machine(), 5, "mc68328_w: CSA1(0) = %04x\n", data);
- m_regs.csa1 &= 0xffff0000 | (~mem_mask);
- m_regs.csa1 |= data & mem_mask;
- break;
-
- case 0x116:
- verboselog(machine(), 5, "mc68328_w: CSA1(16) = %04x\n", data);
- m_regs.csa1 &= ~(mem_mask << 16);
- m_regs.csa1 |= (data & mem_mask) << 16;
- break;
-
- case 0x118:
- verboselog(machine(), 5, "mc68328_w: CSA2(0) = %04x\n", data);
- m_regs.csa2 &= 0xffff0000 | (~mem_mask);
- m_regs.csa2 |= data & mem_mask;
- break;
-
- case 0x11a:
- verboselog(machine(), 5, "mc68328_w: CSA2(16) = %04x\n", data);
- m_regs.csa2 &= ~(mem_mask << 16);
- m_regs.csa2 |= (data & mem_mask) << 16;
- break;
-
- case 0x11c:
- verboselog(machine(), 5, "mc68328_w: CSA3(0) = %04x\n", data);
- m_regs.csa3 &= 0xffff0000 | (~mem_mask);
- m_regs.csa3 |= data & mem_mask;
- break;
-
- case 0x11e:
- verboselog(machine(), 5, "mc68328_w: CSA3(16) = %04x\n", data);
- m_regs.csa3 &= ~(mem_mask << 16);
- m_regs.csa3 |= (data & mem_mask) << 16;
- break;
-
- case 0x120:
- verboselog(machine(), 5, "mc68328_w: CSB0(0) = %04x\n", data);
- m_regs.csb0 &= 0xffff0000 | (~mem_mask);
- m_regs.csb0 |= data & mem_mask;
- break;
-
- case 0x122:
- verboselog(machine(), 5, "mc68328_w: CSB0(16) = %04x\n", data);
- m_regs.csb0 &= ~(mem_mask << 16);
- m_regs.csb0 |= (data & mem_mask) << 16;
- break;
-
- case 0x124:
- verboselog(machine(), 5, "mc68328_w: CSB1(0) = %04x\n", data);
- m_regs.csb1 &= 0xffff0000 | (~mem_mask);
- m_regs.csb1 |= data & mem_mask;
- break;
-
- case 0x126:
- verboselog(machine(), 5, "mc68328_w: CSB1(16) = %04x\n", data);
- m_regs.csb1 &= ~(mem_mask << 16);
- m_regs.csb1 |= (data & mem_mask) << 16;
- break;
-
- case 0x128:
- verboselog(machine(), 5, "mc68328_w: CSB2(0) = %04x\n", data);
- m_regs.csb2 &= 0xffff0000 | (~mem_mask);
- m_regs.csb2 |= data & mem_mask;
- break;
-
- case 0x12a:
- verboselog(machine(), 5, "mc68328_w: CSB2(16) = %04x\n", data);
- m_regs.csb2 &= ~(mem_mask << 16);
- m_regs.csb2 |= (data & mem_mask) << 16;
- break;
-
- case 0x12c:
- verboselog(machine(), 5, "mc68328_w: CSB3(0) = %04x\n", data);
- m_regs.csb3 &= 0xffff0000 | (~mem_mask);
- m_regs.csb3 |= data & mem_mask;
- break;
-
- case 0x12e:
- verboselog(machine(), 5, "mc68328_w: CSB3(16) = %04x\n", data);
- m_regs.csb3 &= ~(mem_mask << 16);
- m_regs.csb3 |= (data & mem_mask) << 16;
- break;
-
- case 0x130:
- verboselog(machine(), 5, "mc68328_w: CSC0(0) = %04x\n", data);
- m_regs.csc0 &= 0xffff0000 | (~mem_mask);
- m_regs.csc0 |= data & mem_mask;
- break;
-
- case 0x132:
- verboselog(machine(), 5, "mc68328_w: CSC0(16) = %04x\n", data);
- m_regs.csc0 &= ~(mem_mask << 16);
- m_regs.csc0 |= (data & mem_mask) << 16;
- break;
-
- case 0x134:
- verboselog(machine(), 5, "mc68328_w: CSC1(0) = %04x\n", data);
- m_regs.csc1 &= 0xffff0000 | (~mem_mask);
- m_regs.csc1 |= data & mem_mask;
- break;
-
- case 0x136:
- verboselog(machine(), 5, "mc68328_w: CSC1(16) = %04x\n", data);
- m_regs.csc1 &= ~(mem_mask << 16);
- m_regs.csc1 |= (data & mem_mask) << 16;
- break;
-
- case 0x138:
- verboselog(machine(), 5, "mc68328_w: CSC2(0) = %04x\n", data);
- m_regs.csc2 &= 0xffff0000 | (~mem_mask);
- m_regs.csc2 |= data & mem_mask;
- break;
-
- case 0x13a:
- verboselog(machine(), 5, "mc68328_w: CSC2(16) = %04x\n", data);
- m_regs.csc2 &= ~(mem_mask << 16);
- m_regs.csc2 |= (data & mem_mask) << 16;
- break;
-
- case 0x13c:
- verboselog(machine(), 5, "mc68328_w: CSC3(0) = %04x\n", data);
- m_regs.csc3 &= 0xffff0000 | (~mem_mask);
- m_regs.csc3 |= data & mem_mask;
- break;
-
- case 0x13e:
- verboselog(machine(), 5, "mc68328_w: CSC3(16) = %04x\n", data);
- m_regs.csc3 &= ~(mem_mask << 16);
- m_regs.csc3 |= (data & mem_mask) << 16;
- break;
-
- case 0x140:
- verboselog(machine(), 5, "mc68328_w: CSD0(0) = %04x\n", data);
- m_regs.csd0 &= 0xffff0000 | (~mem_mask);
- m_regs.csd0 |= data & mem_mask;
- break;
-
- case 0x142:
- verboselog(machine(), 5, "mc68328_w: CSD0(16) = %04x\n", data);
- m_regs.csd0 &= ~(mem_mask << 16);
- m_regs.csd0 |= (data & mem_mask) << 16;
- break;
-
- case 0x144:
- verboselog(machine(), 5, "mc68328_w: CSD1(0) = %04x\n", data);
- m_regs.csd1 &= 0xffff0000 | (~mem_mask);
- m_regs.csd1 |= data & mem_mask;
- break;
-
- case 0x146:
- verboselog(machine(), 5, "mc68328_w: CSD1(16) = %04x\n", data);
- m_regs.csd1 &= ~(mem_mask << 16);
- m_regs.csd1 |= (data & mem_mask) << 16;
- break;
-
- case 0x148:
- verboselog(machine(), 5, "mc68328_w: CSD2(0) = %04x\n", data);
- m_regs.csd2 &= 0xffff0000 | (~mem_mask);
- m_regs.csd2 |= data & mem_mask;
- break;
-
- case 0x14a:
- verboselog(machine(), 5, "mc68328_w: CSD2(16) = %04x\n", data);
- m_regs.csd2 &= ~(mem_mask << 16);
- m_regs.csd2 |= (data & mem_mask) << 16;
- break;
-
- case 0x14c:
- verboselog(machine(), 5, "mc68328_w: CSD3(0) = %04x\n", data);
- m_regs.csd3 &= 0xffff0000 | (~mem_mask);
- m_regs.csd3 |= data & mem_mask;
- break;
-
- case 0x14e:
- verboselog(machine(), 5, "mc68328_w: CSD3(16) = %04x\n", data);
- m_regs.csd3 &= ~(mem_mask << 16);
- m_regs.csd3 |= (data & mem_mask) << 16;
- break;
-
- case 0x200:
- verboselog(machine(), 2, "mc68328_w: PLLCR = %04x\n", data);
- m_regs.pllcr = data;
- break;
-
- case 0x202:
- verboselog(machine(), 2, "mc68328_w: PLLFSR = %04x\n", data);
- m_regs.pllfsr = data;
- break;
-
- case 0x206:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PCTLR = %02x\n", data & 0x00ff);
- m_regs.pctlr = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff206) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0x300:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff301) = %02x\n", data & 0x00ff);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: IVR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.ivr = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x302:
- verboselog(machine(), 2, "mc68328_w: ICR = %04x\n", data);
- m_regs.icr = data;
- break;
-
- case 0x304:
- verboselog(machine(), 2, "mc68328_w: IMR(16) = %04x\n", data);
- m_regs.imr &= ~(mem_mask << 16);
- m_regs.imr |= (data & mem_mask) << 16;
- m_regs.isr &= ~((data & mem_mask) << 16);
-
- imr_diff = imr_old ^ m_regs.imr;
- set_interrupt_line(imr_diff, 0);
- break;
-
- case 0x306:
- verboselog(machine(), 2, "mc68328_w: IMR(0) = %04x\n", data);
- m_regs.imr &= 0xffff0000 | (~mem_mask);
- m_regs.imr |= data & mem_mask;
- m_regs.isr &= ~(data & mem_mask);
-
- imr_diff = imr_old ^ m_regs.imr;
- set_interrupt_line(imr_diff, 0);
- break;
-
- case 0x308:
- verboselog(machine(), 2, "mc68328_w: IWR(16) = %04x\n", data);
- m_regs.iwr &= ~(mem_mask << 16);
- m_regs.iwr |= (data & mem_mask) << 16;
- break;
-
- case 0x30a:
- verboselog(machine(), 2, "mc68328_w: IWR(0) = %04x\n", data);
- m_regs.iwr &= 0xffff0000 | (~mem_mask);
- m_regs.iwr |= data & mem_mask;
- break;
-
- case 0x30c:
- verboselog(machine(), 2, "mc68328_w: ISR(16) = %04x\n", data);
- // Clear edge-triggered IRQ1
- if ((m_regs.icr & ICR_ET1) == ICR_ET1 && (data & INT_IRQ1_SHIFT) == INT_IRQ1_SHIFT)
- {
- m_regs.isr &= ~INT_IRQ1;
- }
-
- // Clear edge-triggered IRQ2
- if ((m_regs.icr & ICR_ET2) == ICR_ET2 && (data & INT_IRQ2_SHIFT) == INT_IRQ2_SHIFT)
- {
- m_regs.isr &= ~INT_IRQ2;
- }
-
- // Clear edge-triggered IRQ3
- if ((m_regs.icr & ICR_ET3) == ICR_ET3 && (data & INT_IRQ3_SHIFT) == INT_IRQ3_SHIFT)
- {
- m_regs.isr &= ~INT_IRQ3;
- }
-
- // Clear edge-triggered IRQ6
- if ((m_regs.icr & ICR_ET6) == ICR_ET6 && (data & INT_IRQ6_SHIFT) == INT_IRQ6_SHIFT)
- {
- m_regs.isr &= ~INT_IRQ6;
- }
-
- // Clear edge-triggered IRQ7
- if ((data & INT_IRQ7_SHIFT) == INT_IRQ7_SHIFT)
- {
- m_regs.isr &= ~INT_IRQ7;
- }
- break;
-
- case 0x30e:
- verboselog(machine(), 2, "mc68328_w: ISR(0) = %04x (Ignored)\n", data);
- break;
-
- case 0x310:
- verboselog(machine(), 2, "mc68328_w: IPR(16) = %04x (Ignored)\n", data);
- break;
-
- case 0x312:
- verboselog(machine(), 2, "mc68328_w: IPR(0) = %04x (Ignored)\n", data);
- break;
-
- case 0x400:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PADATA = %02x\n", data & 0x00ff);
- m_regs.padata = data & 0x00ff;
- if (!m_out_port_a.isnull())
- {
- m_out_port_a(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PADIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.padir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x402:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PASEL = %02x\n", data & 0x00ff);
- m_regs.pasel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff402) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0x408:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PBDATA = %02x\n", data & 0x00ff);
- m_regs.pbdata = data & 0x00ff;
- if (!m_out_port_b.isnull())
- {
- m_out_port_b(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PBDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pbdir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x40a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PBSEL = %02x\n", data & 0x00ff);
- m_regs.pbsel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff40a) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0x410:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PCDATA = %02x\n", data & 0x00ff);
- m_regs.pcdata = data & 0x00ff;
- if (!m_out_port_c.isnull())
- {
- m_out_port_c(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PCDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pcdir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x412:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PCSEL = %02x\n", data & 0x00ff);
- m_regs.pcsel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff412) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0x418:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PDDATA = %02x\n", data & 0x00ff);
-
- m_regs.pddataedge &= ~(data & 0x00ff);
- poll_port_d_interrupts();
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PDDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pddir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x41a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff41b) = %02x\n", data & 0x00ff);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PDPUEN = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pdpuen = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x41c:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PDIRQEN = %02x\n", data & 0x00ff);
- m_regs.pdirqen = data & 0x00ff;
-
- poll_port_d_interrupts();
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PDPOL = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pdpol = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x41e:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PDIRQEDGE = %02x\n", data & 0x00ff);
- m_regs.pdirqedge = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff41e) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0x420:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PEDATA = %02x\n", data & 0x00ff);
- m_regs.pedata = data & 0x00ff;
- if (!m_out_port_e.isnull())
- {
- m_out_port_e(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PEDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pedir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x422:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PESEL = %02x\n", data & 0x00ff);
- m_regs.pesel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PEPUEN = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pepuen = (data >> 8) & 0x00ff;
- m_regs.pedata |= m_regs.pepuen;
- }
- break;
-
- case 0x428:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PFDATA = %02x\n", data & 0x00ff);
- m_regs.pfdata = data & 0x00ff;
- if (!m_out_port_f.isnull())
- {
- m_out_port_f(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PFDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pfdir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x42a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PFSEL = %02x\n", data & 0x00ff);
- m_regs.pfsel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PFPUEN = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pfpuen = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x430:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PGDATA = %02x\n", data & 0x00ff);
- m_regs.pgdata = data & 0x00ff;
- if (!m_out_port_g.isnull())
- {
- m_out_port_g(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PGDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pgdir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x432:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PGSEL = %02x\n", data & 0x00ff);
- m_regs.pgsel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PGPUEN = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pgpuen = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x438:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PJDATA = %02x\n", data & 0x00ff);
- m_regs.pjdata = data & 0x00ff;
- if (!m_out_port_j.isnull())
- {
- m_out_port_j(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PJDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pjdir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x43a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PJSEL = %02x\n", data & 0x00ff);
- m_regs.pjsel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfff43a) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0x440:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PKDATA = %02x\n", data & 0x00ff);
- m_regs.pkdata = data & 0x00ff;
- if (!m_out_port_k.isnull())
- {
- m_out_port_k(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PKDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pkdir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x442:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PKSEL = %02x\n", data & 0x00ff);
- m_regs.pksel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PKPUEN = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pgpuen = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x448:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PMDATA = %02x\n", data & 0x00ff);
- m_regs.pmdata = data & 0x00ff;
- if (!m_out_port_m.isnull())
- {
- m_out_port_m(0, data & 0x00ff);
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PMDIR = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pmdir = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x44a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: PMSEL = %02x\n", data & 0x00ff);
- m_regs.pmsel = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: PMPUEN = %02x\n", (data >> 8) & 0x00ff);
- m_regs.pmpuen = (data >> 8) & 0x00ff;
- }
- break;
-
- case 0x500:
- verboselog(machine(), 2, "mc68328_w: PWMC = %04x\n", data);
-
- m_regs.pwmc = data;
-
- if (m_regs.pwmc & PWMC_PWMIRQ)
- {
- set_interrupt_line(INT_PWM, 1);
- }
-
- m_regs.pwmc &= ~PWMC_LOAD;
-
- if ((m_regs.pwmc & PWMC_PWMEN) != 0 && m_regs.pwmw != 0 && m_regs.pwmp != 0)
- {
- UINT32 frequency = 32768 * 506;
- UINT32 divisor = 4 << (m_regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
- attotime period;
- frequency /= divisor;
- period = attotime::from_hz(frequency) * m_regs.pwmw;
- m_pwm->adjust(period);
- if (m_regs.pwmc & PWMC_IRQEN)
- {
- set_interrupt_line(INT_PWM, 1);
- }
- m_regs.pwmc ^= PWMC_PIN;
- }
- else
- {
- m_pwm->adjust(attotime::never);
- }
- break;
-
- case 0x502:
- verboselog(machine(), 2, "mc68328_w: PWMP = %04x\n", data);
- m_regs.pwmp = data;
- break;
-
- case 0x504:
- verboselog(machine(), 2, "mc68328_w: PWMW = %04x\n", data);
- m_regs.pwmw = data;
- break;
-
- case 0x506:
- verboselog(machine(), 2, "mc68328_w: PWMCNT = %04x\n", data);
- m_regs.pwmcnt = 0;
- break;
-
- case 0x600:
- verboselog(machine(), 2, "mc68328_w: TCTL1 = %04x\n", data);
- temp16[0] = m_regs.tctl[0];
- m_regs.tctl[0] = data;
- if ((temp16[0] & TCTL_TEN) == (m_regs.tctl[0] & TCTL_TEN))
- {
- maybe_start_timer(0, 0);
- }
- else if ((temp16[0] & TCTL_TEN) != TCTL_TEN_ENABLE && (m_regs.tctl[0] & TCTL_TEN) == TCTL_TEN_ENABLE)
- {
- maybe_start_timer(0, 1);
- }
- break;
-
- case 0x602:
- verboselog(machine(), 2, "mc68328_w: TPRER1 = %04x\n", data);
- m_regs.tprer[0] = data;
- maybe_start_timer(0, 0);
- break;
-
- case 0x604:
- verboselog(machine(), 2, "mc68328_w: TCMP1 = %04x\n", data);
- m_regs.tcmp[0] = data;
- maybe_start_timer(0, 0);
- break;
-
- case 0x606:
- verboselog(machine(), 2, "mc68328_w: TCR1 = %04x (Ignored)\n", data);
- break;
-
- case 0x608:
- verboselog(machine(), 2, "mc68328_w: TCN1 = %04x (Ignored)\n", data);
- break;
-
- case 0x60a:
- verboselog(machine(), 5, "mc68328_w: TSTAT1 = %04x\n", data);
- m_regs.tstat[0] &= ~m_regs.tclear[0];
- if (!(m_regs.tstat[0] & TSTAT_COMP))
- {
- set_interrupt_line(INT_TIMER1, 0);
- }
- break;
-
- case 0x60c:
- verboselog(machine(), 2, "mc68328_w: TCTL2 = %04x\n", data);
- temp16[0] = m_regs.tctl[1];
- m_regs.tctl[1] = data;
- if ((temp16[0] & TCTL_TEN) == (m_regs.tctl[1] & TCTL_TEN))
- {
- maybe_start_timer(1, 0);
- }
- else if ((temp16[0] & TCTL_TEN) != TCTL_TEN_ENABLE && (m_regs.tctl[1] & TCTL_TEN) == TCTL_TEN_ENABLE)
- {
- maybe_start_timer(1, 1);
- }
- break;
-
- case 0x60e:
- verboselog(machine(), 2, "mc68328_w: TPRER2 = %04x\n", data);
- m_regs.tprer[1] = data;
- maybe_start_timer(1, 0);
- break;
-
- case 0x610:
- verboselog(machine(), 2, "mc68328_w: TCMP2 = %04x\n", data);
- m_regs.tcmp[1] = data;
- maybe_start_timer(1, 0);
- break;
-
- case 0x612:
- verboselog(machine(), 2, "mc68328_w: TCR2 = %04x (Ignored)\n", data);
- break;
-
- case 0x614:
- verboselog(machine(), 2, "mc68328_w: TCN2 = %04x (Ignored)\n", data);
- break;
-
- case 0x616:
- verboselog(machine(), 2, "mc68328_w: TSTAT2 = %04x\n", data);
- m_regs.tstat[1] &= ~m_regs.tclear[1];
- if (!(m_regs.tstat[1] & TSTAT_COMP))
- {
- set_interrupt_line(INT_TIMER2, 0);
- }
- break;
-
- case 0x618:
- verboselog(machine(), 2, "mc68328_w: WCTLR = %04x\n", data);
- m_regs.wctlr = data;
- break;
-
- case 0x61a:
- verboselog(machine(), 2, "mc68328_w: WCMPR = %04x\n", data);
- m_regs.wcmpr = data;
- break;
-
- case 0x61c:
- verboselog(machine(), 2, "mc68328_w: WCN = %04x (Ignored)\n", data);
- break;
-
- case 0x700:
- verboselog(machine(), 2, "mc68328_w: SPISR = %04x\n", data);
- m_regs.spisr = data;
- break;
-
- case 0x800:
- verboselog(machine(), 2, "mc68328_w: SPIMDATA = %04x\n", data);
- if (!m_out_spim.isnull())
- {
- m_out_spim(0, data, 0xffff);
- }
- else
- {
- m_regs.spimdata = data;
- }
- break;
-
- case 0x802:
- verboselog(machine(), 2, "mc68328_w: SPIMCONT = %04x\n", data);
- verboselog(machine(), 3, " Count = %d\n", data & SPIM_CLOCK_COUNT);
- verboselog(machine(), 3, " Polarity = %s\n", (data & SPIM_POL) ? "Inverted" : "Active-high");
- verboselog(machine(), 3, " Phase = %s\n", (data & SPIM_PHA) ? "Opposite" : "Normal");
- verboselog(machine(), 3, " IRQ Enable = %s\n", (data & SPIM_IRQEN) ? "Enable" : "Disable");
- verboselog(machine(), 3, " IRQ Pending = %s\n", (data & SPIM_SPIMIRQ) ? "Yes" : "No");
- verboselog(machine(), 3, " Exchange = %s\n", (data & SPIM_XCH) ? "Initiate" : "Idle");
- verboselog(machine(), 3, " SPIM Enable = %s\n", (data & SPIM_SPMEN) ? "Enable" : "Disable");
- verboselog(machine(), 3, " Data Rate = Divide By %d\n", 1 << ((((data & SPIM_RATE) >> 13) & 0x0007) + 2) );
- m_regs.spimcont = data;
- // $$HACK$$ We should probably emulate the ADS7843 A/D device properly.
- if (data & SPIM_XCH)
- {
- m_regs.spimcont &= ~SPIM_XCH;
- if (!m_spim_xch_trigger.isnull())
- {
- m_spim_xch_trigger(0);
- }
- if (data & SPIM_IRQEN)
- {
- m_regs.spimcont |= SPIM_SPIMIRQ;
- verboselog(machine(), 3, "Triggering SPIM Interrupt\n" );
- set_interrupt_line(INT_SPIM, 1);
- }
- }
- if (!(data & SPIM_IRQEN))
- {
- set_interrupt_line(INT_SPIM, 0);
- }
- break;
-
- case 0x900:
- verboselog(machine(), 2, "mc68328_w: USTCNT = %04x\n", data);
- m_regs.ustcnt = data;
- break;
-
- case 0x902:
- verboselog(machine(), 2, "mc68328_w: UBAUD = %04x\n", data);
- m_regs.ubaud = data;
- break;
-
- case 0x904:
- verboselog(machine(), 2, "mc68328_w: URX = %04x\n", data);
- break;
-
- case 0x906:
- verboselog(machine(), 2, "mc68328_w: UTX = %04x\n", data);
- break;
-
- case 0x908:
- verboselog(machine(), 2, "mc68328_w: UMISC = %04x\n", data);
- m_regs.umisc = data;
- break;
-
- case 0xa00:
- verboselog(machine(), 2, "mc68328_w: LSSA(16) = %04x\n", data);
- m_regs.lssa &= ~(mem_mask << 16);
- m_regs.lssa |= (data & mem_mask) << 16;
- verboselog(machine(), 3, " Address: %08x\n", m_regs.lssa);
- break;
-
- case 0xa02:
- verboselog(machine(), 2, "mc68328_w: LSSA(0) = %04x\n", data);
- m_regs.lssa &= 0xffff0000 | (~mem_mask);
- m_regs.lssa |= data & mem_mask;
- verboselog(machine(), 3, " Address: %08x\n", m_regs.lssa);
- break;
-
- case 0xa04:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LVPW = %02x\n", data & 0x00ff);
- m_regs.lvpw = data & 0x00ff;
- verboselog(machine(), 3, " Page Width: %d\n", (m_regs.lvpw + 1) * ((m_regs.lpicf & 0x01) ? 8 : 16));
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa04) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa08:
- verboselog(machine(), 2, "mc68328_w: LXMAX = %04x\n", data);
- m_regs.lxmax = data;
- verboselog(machine(), 3, " Width: %d\n", (data & 0x03ff) + 1);
- break;
-
- case 0xa0a:
- verboselog(machine(), 2, "mc68328_w: LYMAX = %04x\n", data);
- m_regs.lymax = data;
- verboselog(machine(), 3, " Height: %d\n", (data & 0x03ff) + 1);
- break;
-
- case 0xa18:
- verboselog(machine(), 2, "mc68328_w: LCXP = %04x\n", data);
- m_regs.lcxp = data;
- verboselog(machine(), 3, " X Position: %d\n", data & 0x03ff);
- switch (m_regs.lcxp >> 14)
- {
- case 0:
- verboselog(machine(), 3, " Cursor Control: Transparent\n");
- break;
-
- case 1:
- verboselog(machine(), 3, " Cursor Control: Black\n");
- break;
-
- case 2:
- verboselog(machine(), 3, " Cursor Control: Reverse\n");
- break;
-
- case 3:
- verboselog(machine(), 3, " Cursor Control: Invalid\n");
- break;
- }
- break;
-
- case 0xa1a:
- verboselog(machine(), 2, "mc68328_w: LCYP = %04x\n", data);
- m_regs.lcyp = data;
- verboselog(machine(), 3, " Y Position: %d\n", data & 0x01ff);
- break;
-
- case 0xa1c:
- verboselog(machine(), 2, "mc68328_w: LCWCH = %04x\n", data);
- m_regs.lcwch = data;
- verboselog(machine(), 3, " Width: %d\n", (data >> 8) & 0x1f);
- verboselog(machine(), 3, " Height: %d\n", data & 0x1f);
- break;
-
- case 0xa1e:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LBLKC = %02x\n", data & 0x00ff);
- m_regs.lblkc = data & 0x00ff;
- verboselog(machine(), 3, " Blink Enable: %d\n", m_regs.lblkc >> 7);
- verboselog(machine(), 3, " Blink Divisor: %d\n", m_regs.lblkc & 0x7f);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa1e) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa20:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LPOLCF = %02x\n", data & 0x00ff);
- m_regs.lpolcf = data & 0x00ff;
- verboselog(machine(), 3, " LCD Shift Clock Polarity: %s\n", (m_regs.lpicf & 0x08) ? "Active positive edge of LCLK" : "Active negative edge of LCLK");
- verboselog(machine(), 3, " First-line marker polarity: %s\n", (m_regs.lpicf & 0x04) ? "Active Low" : "Active High");
- verboselog(machine(), 3, " Line-pulse polarity: %s\n", (m_regs.lpicf & 0x02) ? "Active Low" : "Active High");
- verboselog(machine(), 3, " Pixel polarity: %s\n", (m_regs.lpicf & 0x01) ? "Active Low" : "Active High");
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: LPICF = %02x\n", (data >> 8) & 0x00ff);
- m_regs.lpicf = (data >> 8) & 0x00ff;
- switch((m_regs.lpicf >> 1) & 0x03)
- {
- case 0:
- verboselog(machine(), 3, " Bus Size: 1-bit\n");
- break;
-
- case 1:
- verboselog(machine(), 3, " Bus Size: 2-bit\n");
- break;
-
- case 2:
- verboselog(machine(), 3, " Bus Size: 4-bit\n");
- break;
-
- case 3:
- verboselog(machine(), 3, " Bus Size: unused\n");
- break;
- }
- verboselog(machine(), 3, " Gray scale enable: %d\n", m_regs.lpicf & 0x01);
- }
- break;
-
- case 0xa22:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LACDRC = %02x\n", data & 0x00ff);
- m_regs.lacdrc = data & 0x00ff;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa22) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa24:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LPXCD = %02x\n", data & 0x00ff);
- m_regs.lpxcd = data & 0x00ff;
- verboselog(machine(), 3, " Clock Divisor: %d\n", m_regs.lpxcd + 1);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa24) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa26:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LCKCON = %02x\n", data & 0x00ff);
- m_regs.lckcon = data & 0x00ff;
- verboselog(machine(), 3, " LCDC Enable: %d\n", (m_regs.lckcon >> 7) & 0x01);
- verboselog(machine(), 3, " DMA Burst Length: %d\n", ((m_regs.lckcon >> 6) & 0x01) ? 16 : 8);
- verboselog(machine(), 3, " DMA Bursting Clock Control: %d\n", ((m_regs.lckcon >> 4) & 0x03) + 1);
- verboselog(machine(), 3, " Bus Width: %d\n", ((m_regs.lckcon >> 1) & 0x01) ? 8 : 16);
- verboselog(machine(), 3, " Pixel Clock Divider Source: %s\n", (m_regs.lckcon & 0x01) ? "PIX" : "SYS");
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa26) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa28:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LLBAR = %02x\n", data & 0x00ff);
- m_regs.llbar = data & 0x00ff;
- verboselog(machine(), 3, " Address: %d\n", (m_regs.llbar & 0x7f) * ((m_regs.lpicf & 0x01) ? 8 : 16));
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa28) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa2a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LOTCR = %02x\n", data & 0x00ff);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa2a) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa2c:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LPOSR = %02x\n", data & 0x00ff);
- m_regs.lposr = data & 0x00ff;
- verboselog(machine(), 3, " Byte Offset: %d\n", (m_regs.lposr >> 3) & 0x01);
- verboselog(machine(), 3, " Pixel Offset: %d\n", m_regs.lposr & 0x07);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa2c) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa30:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_w: LFRCM = %02x\n", data & 0x00ff);
- m_regs.lfrcm = data & 0x00ff;
- verboselog(machine(), 3, " X Modulation: %d\n", (m_regs.lfrcm >> 4) & 0x0f);
- verboselog(machine(), 3, " Y Modulation: %d\n", m_regs.lfrcm & 0x0f);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_w: Unknown address (0xfffa30) = %02x\n", (data >> 8) & 0x00ff);
- }
- break;
-
- case 0xa32:
- verboselog(machine(), 2, "mc68328_w: LGPMR = %04x\n", data);
- m_regs.lgpmr = data;
- verboselog(machine(), 3, " Palette 0: %d\n", (m_regs.lgpmr >> 8) & 0x07);
- verboselog(machine(), 3, " Palette 1: %d\n", (m_regs.lgpmr >> 12) & 0x07);
- verboselog(machine(), 3, " Palette 2: %d\n", (m_regs.lgpmr >> 0) & 0x07);
- verboselog(machine(), 3, " Palette 3: %d\n", (m_regs.lgpmr >> 4) & 0x07);
- break;
-
- case 0xb00:
- verboselog(machine(), 2, "mc68328_w: HMSR(0) = %04x\n", data);
- m_regs.hmsr &= ~(mem_mask << 16);
- m_regs.hmsr |= (data & mem_mask) << 16;
- m_regs.hmsr &= 0x1f3f003f;
- break;
-
- case 0xb02:
- verboselog(machine(), 2, "mc68328_w: HMSR(16) = %04x\n", data);
- m_regs.hmsr &= 0xffff0000 | (~mem_mask);
- m_regs.hmsr |= data & mem_mask;
- m_regs.hmsr &= 0x1f3f003f;
- break;
-
- case 0xb04:
- verboselog(machine(), 2, "mc68328_w: ALARM(0) = %04x\n", data);
- m_regs.alarm &= ~(mem_mask << 16);
- m_regs.alarm |= (data & mem_mask) << 16;
- m_regs.alarm &= 0x1f3f003f;
- break;
-
- case 0xb06:
- verboselog(machine(), 2, "mc68328_w: ALARM(16) = %04x\n", data);
- m_regs.alarm &= 0xffff0000 | (~mem_mask);
- m_regs.alarm |= data & mem_mask;
- m_regs.alarm &= 0x1f3f003f;
- break;
-
- case 0xb0c:
- verboselog(machine(), 2, "mc68328_w: RTCCTL = %04x\n", data);
- m_regs.rtcctl = data & 0x00a0;
- break;
-
- case 0xb0e:
- verboselog(machine(), 2, "mc68328_w: RTCISR = %04x\n", data);
- m_regs.rtcisr &= ~data;
- if (m_regs.rtcisr == 0)
- {
- set_interrupt_line(INT_RTC, 0);
- }
- break;
-
- case 0xb10:
- verboselog(machine(), 2, "mc68328_w: RTCIENR = %04x\n", data);
- m_regs.rtcienr = data & 0x001f;
- break;
-
- case 0xb12:
- verboselog(machine(), 2, "mc68328_w: STPWTCH = %04x\n", data);
- m_regs.stpwtch = data & 0x003f;
- break;
-
- default:
- verboselog(machine(), 0, "mc68328_w: Unknown address (0x%06x) = %04x (%04x)\n", 0xfff000 + address, data, mem_mask);
- break;
- }
-}
-
-READ16_MEMBER( mc68328_device::read )
-{
- UINT16 temp16 = 0;
- UINT32 address = offset << 1;
-
- switch (address)
- {
- case 0x000:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff001)\n", mem_mask);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): SCR = %02x\n", mem_mask, m_regs.scr);
- return m_regs.scr << 8;
- }
- break;
-
- case 0x100:
- verboselog(machine(), 2, "mc68328_r (%04x): GRPBASEA = %04x\n", mem_mask, m_regs.grpbasea);
- return m_regs.grpbasea;
-
- case 0x102:
- verboselog(machine(), 2, "mc68328_r (%04x): GRPBASEB = %04x\n", mem_mask, m_regs.grpbaseb);
- return m_regs.grpbaseb;
-
- case 0x104:
- verboselog(machine(), 2, "mc68328_r (%04x): GRPBASEC = %04x\n", mem_mask, m_regs.grpbasec);
- return m_regs.grpbasec;
-
- case 0x106:
- verboselog(machine(), 2, "mc68328_r (%04x): GRPBASED = %04x\n", mem_mask, m_regs.grpbased);
- return m_regs.grpbased;
-
- case 0x108:
- verboselog(machine(), 2, "mc68328_r (%04x): GRPMASKA = %04x\n", mem_mask, m_regs.grpmaska);
- return m_regs.grpmaska;
-
- case 0x10a:
- verboselog(machine(), 2, "mc68328_r (%04x): GRPMASKB = %04x\n", mem_mask, m_regs.grpmaskb);
- return m_regs.grpmaskb;
-
- case 0x10c:
- verboselog(machine(), 2, "mc68328_r (%04x): GRPMASKC = %04x\n", mem_mask, m_regs.grpmaskc);
- return m_regs.grpmaskc;
-
- case 0x10e:
- verboselog(machine(), 2, "mc68328_r (%04x): GRPMASKD = %04x\n", mem_mask, m_regs.grpmaskd);
- return m_regs.grpmaskd;
-
- case 0x110:
- verboselog(machine(), 5, "mc68328_r (%04x): CSA0(0) = %04x\n", mem_mask, m_regs.csa0 & 0x0000ffff);
- return m_regs.csa0 & 0x0000ffff;
-
- case 0x112:
- verboselog(machine(), 5, "mc68328_r (%04x): CSA0(16) = %04x\n", mem_mask, m_regs.csa0 >> 16);
- return m_regs.csa0 >> 16;
-
- case 0x114:
- verboselog(machine(), 5, "mc68328_r (%04x): CSA1(0) = %04x\n", mem_mask, m_regs.csa1 & 0x0000ffff);
- return m_regs.csa1 & 0x0000ffff;
-
- case 0x116:
- verboselog(machine(), 5, "mc68328_r (%04x): CSA1(16) = %04x\n", mem_mask, m_regs.csa1 >> 16);
- return m_regs.csa1 >> 16;
-
- case 0x118:
- verboselog(machine(), 5, "mc68328_r (%04x): CSA2(0) = %04x\n", mem_mask, m_regs.csa2 & 0x0000ffff);
- return m_regs.csa2 & 0x0000ffff;
-
- case 0x11a:
- verboselog(machine(), 5, "mc68328_r (%04x): CSA2(16) = %04x\n", mem_mask, m_regs.csa2 >> 16);
- return m_regs.csa2 >> 16;
-
- case 0x11c:
- verboselog(machine(), 5, "mc68328_r (%04x): CSA3(0) = %04x\n", mem_mask, m_regs.csa3 & 0x0000ffff);
- return m_regs.csa3 & 0x0000ffff;
-
- case 0x11e:
- verboselog(machine(), 5, "mc68328_r (%04x): CSA3(16) = %04x\n", mem_mask, m_regs.csa3 >> 16);
- return m_regs.csa3 >> 16;
-
- case 0x120:
- verboselog(machine(), 5, "mc68328_r (%04x): CSB0(0) = %04x\n", mem_mask, m_regs.csb0 & 0x0000ffff);
- return m_regs.csb0 & 0x0000ffff;
-
- case 0x122:
- verboselog(machine(), 5, "mc68328_r (%04x): CSB0(16) = %04x\n", mem_mask, m_regs.csb0 >> 16);
- return m_regs.csb0 >> 16;
-
- case 0x124:
- verboselog(machine(), 5, "mc68328_r (%04x): CSB1(0) = %04x\n", mem_mask, m_regs.csb1 & 0x0000ffff);
- return m_regs.csb1 & 0x0000ffff;
-
- case 0x126:
- verboselog(machine(), 5, "mc68328_r (%04x): CSB1(16) = %04x\n", mem_mask, m_regs.csb1 >> 16);
- return m_regs.csb1 >> 16;
-
- case 0x128:
- verboselog(machine(), 5, "mc68328_r (%04x): CSB2(0) = %04x\n", mem_mask, m_regs.csb2 & 0x0000ffff);
- return m_regs.csb2 & 0x0000ffff;
-
- case 0x12a:
- verboselog(machine(), 5, "mc68328_r (%04x): CSB2(16) = %04x\n", mem_mask, m_regs.csb2 >> 16);
- return m_regs.csb2 >> 16;
-
- case 0x12c:
- verboselog(machine(), 5, "mc68328_r (%04x): CSB3(0) = %04x\n", mem_mask, m_regs.csb3 & 0x0000ffff);
- return m_regs.csb3 & 0x0000ffff;
-
- case 0x12e:
- verboselog(machine(), 5, "mc68328_r (%04x): CSB3(16) = %04x\n", mem_mask, m_regs.csb3 >> 16);
- return m_regs.csb3 >> 16;
-
- case 0x130:
- verboselog(machine(), 5, "mc68328_r (%04x): CSC0(0) = %04x\n", mem_mask, m_regs.csc0 & 0x0000ffff);
- return m_regs.csc0 & 0x0000ffff;
-
- case 0x132:
- verboselog(machine(), 5, "mc68328_r (%04x): CSC0(16) = %04x\n", mem_mask, m_regs.csc0 >> 16);
- return m_regs.csc0 >> 16;
-
- case 0x134:
- verboselog(machine(), 5, "mc68328_r (%04x): CSC1(0) = %04x\n", mem_mask, m_regs.csc1 & 0x0000ffff);
- return m_regs.csc1 & 0x0000ffff;
-
- case 0x136:
- verboselog(machine(), 5, "mc68328_r (%04x): CSC1(16) = %04x\n", mem_mask, m_regs.csc1 >> 16);
- return m_regs.csc1 >> 16;
-
- case 0x138:
- verboselog(machine(), 5, "mc68328_r (%04x): CSC2(0) = %04x\n", mem_mask, m_regs.csc2 & 0x0000ffff);
- return m_regs.csc2 & 0x0000ffff;
-
- case 0x13a:
- verboselog(machine(), 5, "mc68328_r (%04x): CSC2(16) = %04x\n", mem_mask, m_regs.csc2 >> 16);
- return m_regs.csc2 >> 16;
-
- case 0x13c:
- verboselog(machine(), 5, "mc68328_r (%04x): CSC3(0) = %04x\n", mem_mask, m_regs.csc3 & 0x0000ffff);
- return m_regs.csc3 & 0x0000ffff;
-
- case 0x13e:
- verboselog(machine(), 5, "mc68328_r (%04x): CSC3(16) = %04x\n", mem_mask, m_regs.csc3 >> 16);
- return m_regs.csc3 >> 16;
-
- case 0x140:
- verboselog(machine(), 5, "mc68328_r (%04x): CSD0(0) = %04x\n", mem_mask, m_regs.csd0 & 0x0000ffff);
- return m_regs.csd0 & 0x0000ffff;
-
- case 0x142:
- verboselog(machine(), 5, "mc68328_r (%04x): CSD0(16) = %04x\n", mem_mask, m_regs.csd0 >> 16);
- return m_regs.csd0 >> 16;
-
- case 0x144:
- verboselog(machine(), 5, "mc68328_r (%04x): CSD1(0) = %04x\n", mem_mask, m_regs.csd1 & 0x0000ffff);
- return m_regs.csd1 & 0x0000ffff;
-
- case 0x146:
- verboselog(machine(), 5, "mc68328_r (%04x): CSD1(16) = %04x\n", mem_mask, m_regs.csd1 >> 16);
- return m_regs.csd1 >> 16;
-
- case 0x148:
- verboselog(machine(), 5, "mc68328_r (%04x): CSD2(0) = %04x\n", mem_mask, m_regs.csd2 & 0x0000ffff);
- return m_regs.csd2 & 0x0000ffff;
-
- case 0x14a:
- verboselog(machine(), 5, "mc68328_r (%04x): CSD2(16) = %04x\n", mem_mask, m_regs.csd2 >> 16);
- return m_regs.csd2 >> 16;
-
- case 0x14c:
- verboselog(machine(), 5, "mc68328_r (%04x): CSD3(0) = %04x\n", mem_mask, m_regs.csd3 & 0x0000ffff);
- return m_regs.csd3 & 0x0000ffff;
-
- case 0x14e:
- verboselog(machine(), 5, "mc68328_r (%04x): CSD3(16) = %04x\n", mem_mask, m_regs.csd3 >> 16);
- return m_regs.csd3 >> 16;
-
- case 0x200:
- verboselog(machine(), 2, "mc68328_r (%04x): PLLCR = %04x\n", mem_mask, m_regs.pllcr);
- return m_regs.pllcr;
-
- case 0x202:
- verboselog(machine(), 2, "mc68328_r (%04x): PLLFSR = %04x\n", mem_mask, m_regs.pllfsr);
- m_regs.pllfsr ^= 0x8000;
- return m_regs.pllfsr;
-
- case 0x206:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff206)\n", mem_mask);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PCTLR = %02x\n", mem_mask, m_regs.pctlr);
- return m_regs.pctlr << 8;
- }
- break;
-
- case 0x300:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff301)\n", mem_mask);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): IVR = %02x\n", mem_mask, m_regs.ivr);
- return m_regs.ivr << 8;
- }
- break;
-
- case 0x302:
- verboselog(machine(), 2, "mc68328_r (%04x): ICR = %04x\n", mem_mask, m_regs.icr);
- return m_regs.icr;
-
- case 0x304:
- verboselog(machine(), 2, "mc68328_r (%04x): IMR(16) = %04x\n", mem_mask, m_regs.imr >> 16);
- return m_regs.imr >> 16;
-
- case 0x306:
- verboselog(machine(), 2, "mc68328_r (%04x): IMR(0) = %04x\n", mem_mask, m_regs.imr & 0x0000ffff);
- return m_regs.imr & 0x0000ffff;
-
- case 0x308:
- verboselog(machine(), 2, "mc68328_r (%04x): IWR(16) = %04x\n", mem_mask, m_regs.iwr >> 16);
- return m_regs.iwr >> 16;
-
- case 0x30a:
- verboselog(machine(), 2, "mc68328_r (%04x): IWR(0) = %04x\n", mem_mask, m_regs.iwr & 0x0000ffff);
- return m_regs.iwr & 0x0000ffff;
-
- case 0x30c:
- verboselog(machine(), 2, "mc68328_r (%04x): ISR(16) = %04x\n", mem_mask, m_regs.isr >> 16);
- return m_regs.isr >> 16;
-
- case 0x30e:
- verboselog(machine(), 2, "mc68328_r (%04x): ISR(0) = %04x\n", mem_mask, m_regs.isr & 0x0000ffff);
- return m_regs.isr & 0x0000ffff;
-
- case 0x310:
- verboselog(machine(), 2, "mc68328_r (%04x): IPR(16) = %04x\n", mem_mask, m_regs.ipr >> 16);
- return m_regs.ipr >> 16;
-
- case 0x312:
- verboselog(machine(), 2, "mc68328_r (%04x): IPR(0) = %04x\n", mem_mask, m_regs.ipr & 0x0000ffff);
- return m_regs.ipr & 0x0000ffff;
-
- case 0x400:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PADATA = %02x\n", mem_mask, m_regs.padata);
- if (!m_in_port_a.isnull())
- {
- return m_in_port_a(0);
- }
- else
- {
- return m_regs.padata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PADIR = %02x\n", mem_mask, m_regs.padir);
- return m_regs.padir << 8;
- }
- break;
-
- case 0x402:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PASEL = %02x\n", mem_mask, m_regs.pasel);
- return m_regs.pasel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff402)\n", mem_mask);
- }
- break;
-
- case 0x408:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PBDATA = %02x\n", mem_mask, m_regs.pbdata);
- if (!m_in_port_b.isnull())
- {
- return m_in_port_b(0);
- }
- else
- {
- return m_regs.pbdata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PBDIR = %02x\n", mem_mask, m_regs.pbdir);
- return m_regs.pbdir << 8;
- }
- break;
-
- case 0x40a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PBSEL = %02x\n", mem_mask, m_regs.pbsel);
- return m_regs.pbsel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff40a)\n", mem_mask);
- }
- break;
-
- case 0x410:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PCDATA = %02x\n", mem_mask, m_regs.pcdata);
- if (!m_in_port_c.isnull())
- {
- return m_in_port_c(0);
- }
- else
- {
- return m_regs.pcdata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PCDIR = %02x\n", mem_mask, m_regs.pcdir);
- return m_regs.pcdir << 8;
- }
- break;
-
- case 0x412:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PCSEL = %02x\n", mem_mask, m_regs.pcsel);
- return m_regs.pcsel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff412)\n", mem_mask);
- }
- break;
-
- case 0x418:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PDDATA = %02x\n", mem_mask, m_regs.pddata);
- if (!m_in_port_d.isnull())
- {
- return m_in_port_d(0);
- }
- else
- {
- return m_regs.pddata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PDDIR = %02x\n", mem_mask, m_regs.pddir);
- return m_regs.pddir << 8;
- }
- break;
-
- case 0x41a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff41b)\n", mem_mask);
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PDPUEN = %02x\n", mem_mask, m_regs.pdpuen);
- return m_regs.pdpuen << 8;
- }
- break;
-
- case 0x41c:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PDIRQEN = %02x\n", mem_mask, m_regs.pdirqen);
- return m_regs.pdirqen;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PDPOL = %02x\n", mem_mask, m_regs.pdpol);
- return m_regs.pdpol << 8;
- }
- break;
-
- case 0x41e:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PDIRQEDGE = %02x\n", mem_mask, m_regs.pdirqedge);
- return m_regs.pdirqedge;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff41e)\n", mem_mask);
- }
- break;
-
- case 0x420:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PEDATA = %02x\n", mem_mask, m_regs.pedata);
- if (!m_in_port_e.isnull())
- {
- return m_in_port_e(0);
- }
- else
- {
- return m_regs.pedata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PEDIR = %02x\n", mem_mask, m_regs.pedir);
- return m_regs.pedir << 8;
- }
- break;
-
- case 0x422:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PESEL = %02x\n", mem_mask, m_regs.pesel);
- return m_regs.pesel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PEPUEN = %02x\n", mem_mask, m_regs.pepuen);
- return m_regs.pepuen << 8;
- }
- break;
-
- case 0x428:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PFDATA = %02x\n", mem_mask, m_regs.pfdata);
- if (!m_in_port_f.isnull())
- {
- return m_in_port_f(0);
- }
- else
- {
- return m_regs.pfdata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PFDIR = %02x\n", mem_mask, m_regs.pfdir);
- return m_regs.pfdir << 8;
- }
- break;
-
- case 0x42a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PFSEL = %02x\n", mem_mask, m_regs.pfsel);
- return m_regs.pfsel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PFPUEN = %02x\n", mem_mask, m_regs.pfpuen);
- return m_regs.pfpuen << 8;
- }
- break;
-
- case 0x430:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PGDATA = %02x\n", mem_mask, m_regs.pgdata);
- if (!m_in_port_g.isnull())
- {
- return m_in_port_g(0);
- }
- else
- {
- return m_regs.pgdata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PGDIR = %02x\n", mem_mask, m_regs.pgdir);
- return m_regs.pgdir << 8;
- }
- break;
-
- case 0x432:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PGSEL = %02x\n", mem_mask, m_regs.pgsel);
- return m_regs.pgsel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PGPUEN = %02x\n", mem_mask, m_regs.pgpuen);
- return m_regs.pgpuen << 8;
- }
- break;
-
- case 0x438:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PJDATA = %02x\n", mem_mask, m_regs.pjdata);
- if (!m_in_port_j.isnull())
- {
- return m_in_port_j(0);
- }
- else
- {
- return m_regs.pjdata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PJDIR = %02x\n", mem_mask, m_regs.pjdir);
- return m_regs.pjdir << 8;
- }
- break;
-
- case 0x43a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PJSEL = %02x\n", mem_mask, m_regs.pjsel);
- return m_regs.pjsel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfff43a)\n", mem_mask);
- }
- break;
-
- case 0x440:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PKDATA = %02x\n", mem_mask, m_regs.pkdata);
- if (!m_in_port_k.isnull())
- {
- return m_in_port_k(0);
- }
- else
- {
- return m_regs.pkdata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PKDIR = %02x\n", mem_mask, m_regs.pkdir);
- return m_regs.pkdir << 8;
- }
- break;
-
- case 0x442:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PKSEL = %02x\n", mem_mask, m_regs.pksel);
- return m_regs.pksel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PKPUEN = %02x\n", mem_mask, m_regs.pkpuen);
- return m_regs.pkpuen << 8;
- }
- break;
-
- case 0x448:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PMDATA = %02x\n", mem_mask, m_regs.pmdata);
- if (!m_in_port_m.isnull())
- {
- return m_in_port_m(0);
- }
- else
- {
- return m_regs.pmdata;
- }
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PMDIR = %02x\n", mem_mask, m_regs.pmdir);
- return m_regs.pmdir << 8;
- }
- break;
-
- case 0x44a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PMSEL = %02x\n", mem_mask, m_regs.pmsel);
- return m_regs.pmsel;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): PMPUEN = %02x\n", mem_mask, m_regs.pmpuen);
- return m_regs.pmpuen << 8;
- }
- break;
-
- case 0x500:
- verboselog(machine(), 2, "mc68328_r (%04x): PWMC = %04x\n", mem_mask, m_regs.pwmc);
- temp16 = m_regs.pwmc;
- if (m_regs.pwmc & PWMC_PWMIRQ)
- {
- m_regs.pwmc &= ~PWMC_PWMIRQ;
- set_interrupt_line(INT_PWM, 0);
- }
- return temp16;
-
- case 0x502:
- verboselog(machine(), 2, "mc68328_r (%04x): PWMP = %04x\n", mem_mask, m_regs.pwmp);
- return m_regs.pwmp;
-
- case 0x504:
- verboselog(machine(), 2, "mc68328_r (%04x): PWMW = %04x\n", mem_mask, m_regs.pwmw);
- return m_regs.pwmw;
-
- case 0x506:
- verboselog(machine(), 2, "mc68328_r (%04x): PWMCNT = %04x\n", mem_mask, m_regs.pwmcnt);
- return m_regs.pwmcnt;
-
- case 0x600:
- verboselog(machine(), 2, "mc68328_r (%04x): TCTL1 = %04x\n", mem_mask, m_regs.tctl[0]);
- return m_regs.tctl[0];
-
- case 0x602:
- verboselog(machine(), 2, "mc68328_r (%04x): TPRER1 = %04x\n", mem_mask, m_regs.tprer[0]);
- return m_regs.tprer[0];
-
- case 0x604:
- verboselog(machine(), 2, "mc68328_r (%04x): TCMP1 = %04x\n", mem_mask, m_regs.tcmp[0]);
- return m_regs.tcmp[0];
-
- case 0x606:
- verboselog(machine(), 2, "mc68328_r (%04x): TCR1 = %04x\n", mem_mask, m_regs.tcr[0]);
- return m_regs.tcr[0];
-
- case 0x608:
- verboselog(machine(), 2, "mc68328_r (%04x): TCN1 = %04x\n", mem_mask, m_regs.tcn[0]);
- return m_regs.tcn[0];
-
- case 0x60a:
- verboselog(machine(), 5, "mc68328_r (%04x): TSTAT1 = %04x\n", mem_mask, m_regs.tstat[0]);
- m_regs.tclear[0] |= m_regs.tstat[0];
- return m_regs.tstat[0];
-
- case 0x60c:
- verboselog(machine(), 2, "mc68328_r (%04x): TCTL2 = %04x\n", mem_mask, m_regs.tctl[1]);
- return m_regs.tctl[1];
-
- case 0x60e:
- verboselog(machine(), 2, "mc68328_r (%04x): TPREP2 = %04x\n", mem_mask, m_regs.tprer[1]);
- return m_regs.tprer[1];
-
- case 0x610:
- verboselog(machine(), 2, "mc68328_r (%04x): TCMP2 = %04x\n", mem_mask, m_regs.tcmp[1]);
- return m_regs.tcmp[1];
-
- case 0x612:
- verboselog(machine(), 2, "mc68328_r (%04x): TCR2 = %04x\n", mem_mask, m_regs.tcr[1]);
- return m_regs.tcr[1];
-
- case 0x614:
- verboselog(machine(), 2, "mc68328_r (%04x): TCN2 = %04x\n", mem_mask, m_regs.tcn[1]);
- return m_regs.tcn[1];
-
- case 0x616:
- verboselog(machine(), 2, "mc68328_r (%04x): TSTAT2 = %04x\n", mem_mask, m_regs.tstat[1]);
- m_regs.tclear[1] |= m_regs.tstat[1];
- return m_regs.tstat[1];
-
- case 0x618:
- verboselog(machine(), 2, "mc68328_r (%04x): WCTLR = %04x\n", mem_mask, m_regs.wctlr);
- return m_regs.wctlr;
-
- case 0x61a:
- verboselog(machine(), 2, "mc68328_r (%04x): WCMPR = %04x\n", mem_mask, m_regs.wcmpr);
- return m_regs.wcmpr;
-
- case 0x61c:
- verboselog(machine(), 2, "mc68328_r (%04x): WCN = %04x\n", mem_mask, m_regs.wcn);
- return m_regs.wcn;
-
- case 0x700:
- verboselog(machine(), 2, "mc68328_r (%04x): SPISR = %04x\n", mem_mask, m_regs.spisr);
- return m_regs.spisr;
-
- case 0x800:
- verboselog(machine(), 2, "mc68328_r (%04x): SPIMDATA = %04x\n", mem_mask, m_regs.spimdata);
- if (!m_in_spim.isnull())
- {
- return m_in_spim(0, 0xffff);
- }
- return m_regs.spimdata;
-
- case 0x802:
- verboselog(machine(), 2, "mc68328_r (%04x): SPIMCONT = %04x\n", mem_mask, m_regs.spimcont);
- if (m_regs.spimcont & SPIM_XCH)
- {
- m_regs.spimcont &= ~SPIM_XCH;
- m_regs.spimcont |= SPIM_SPIMIRQ;
- return ((m_regs.spimcont | SPIM_XCH) &~ SPIM_SPIMIRQ);
- }
- return m_regs.spimcont;
-
- case 0x900:
- verboselog(machine(), 2, "mc68328_r (%04x): USTCNT = %04x\n", mem_mask, m_regs.ustcnt);
- return m_regs.ustcnt;
-
- case 0x902:
- verboselog(machine(), 2, "mc68328_r (%04x): UBAUD = %04x\n", mem_mask, m_regs.ubaud);
- return m_regs.ubaud;
-
- case 0x904:
- verboselog(machine(), 5, "mc68328_r (%04x): URX = %04x\n", mem_mask, m_regs.urx);
- return m_regs.urx;
-
- case 0x906:
- verboselog(machine(), 5, "mc68328_r (%04x): UTX = %04x\n", mem_mask, m_regs.utx);
- return m_regs.utx | UTX_FIFO_EMPTY | UTX_FIFO_HALF | UTX_TX_AVAIL;
-
- case 0x908:
- verboselog(machine(), 2, "mc68328_r (%04x): UMISC = %04x\n", mem_mask, m_regs.umisc);
- return m_regs.umisc;
-
- case 0xa00:
- verboselog(machine(), 2, "mc68328_r (%04x): LSSA(16) = %04x\n", mem_mask, m_regs.lssa >> 16);
- return m_regs.lssa >> 16;
-
- case 0xa02:
- verboselog(machine(), 2, "mc68328_r (%04x): LSSA(0) = %04x\n", mem_mask, m_regs.lssa & 0x0000ffff);
- return m_regs.lssa & 0x0000ffff;
-
- case 0xa04:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LVPW = %02x\n", mem_mask, m_regs.lvpw);
- return m_regs.lvpw;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa04)\n", mem_mask);
- }
- break;
-
- case 0xa08:
- verboselog(machine(), 2, "mc68328_r (%04x): LXMAX = %04x\n", mem_mask, m_regs.lxmax);
- return m_regs.lxmax;
-
- case 0xa0a:
- verboselog(machine(), 2, "mc68328_r (%04x): LYMAX = %04x\n", mem_mask, m_regs.lymax);
- return m_regs.lymax;
-
- case 0xa18:
- verboselog(machine(), 2, "mc68328_r (%04x): LCXP = %04x\n", mem_mask, m_regs.lcxp);
- return m_regs.lcxp;
-
- case 0xa1a:
- verboselog(machine(), 2, "mc68328_r (%04x): LCYP = %04x\n", mem_mask, m_regs.lcyp);
- return m_regs.lcyp;
-
- case 0xa1c:
- verboselog(machine(), 2, "mc68328_r (%04x): LCWCH = %04x\n", mem_mask, m_regs.lcwch);
- return m_regs.lcwch;
-
- case 0xa1e:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LBLKC = %02x\n", mem_mask, m_regs.lblkc);
- return m_regs.lblkc;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa1e)\n", mem_mask);
- }
- break;
-
- case 0xa20:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LPOLCF = %02x\n", mem_mask, m_regs.lpolcf);
- return m_regs.lpolcf;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LPICF = %02x\n", mem_mask, m_regs.lpicf);
- return m_regs.lpicf << 8;
- }
- break;
-
- case 0xa22:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LACDRC = %02x\n", mem_mask, m_regs.lacdrc);
- return m_regs.lacdrc;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa22)\n", mem_mask);
- }
- break;
-
- case 0xa24:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LPXCD = %02x\n", mem_mask, m_regs.lpxcd);
- return m_regs.lpxcd;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa24)\n", mem_mask);
- }
- break;
-
- case 0xa26:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LCKCON = %02x\n", mem_mask, m_regs.lckcon);
- return m_regs.lckcon;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa26)\n", mem_mask);
- }
- break;
-
- case 0xa28:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LLBAR = %02x\n", mem_mask, m_regs.llbar);
- return m_regs.llbar;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa28)\n", mem_mask);
- }
- break;
-
- case 0xa2a:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LOTCR = %02x\n", mem_mask, m_regs.lotcr);
- return m_regs.lotcr;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa2a)\n", mem_mask);
- }
- break;
-
- case 0xa2c:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LPOSR = %02x\n", mem_mask, m_regs.lposr);
- return m_regs.lposr;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa2c)\n", mem_mask);
- }
- break;
-
- case 0xa30:
- if (mem_mask & 0x00ff)
- {
- verboselog(machine(), 2, "mc68328_r (%04x): LFRCM = %02x\n", mem_mask, m_regs.lfrcm);
- return m_regs.lfrcm;
- }
- else
- {
- verboselog(machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa30)\n", mem_mask);
- }
- break;
-
- case 0xa32:
- verboselog(machine(), 2, "mc68328_r (%04x): LGPMR = %04x\n", mem_mask, m_regs.lgpmr);
- return m_regs.lgpmr;
-
- case 0xb00:
- verboselog(machine(), 2, "mc68328_r (%04x): HMSR(0) = %04x\n", mem_mask, m_regs.hmsr & 0x0000ffff);
- return m_regs.hmsr & 0x0000ffff;
-
- case 0xb02:
- verboselog(machine(), 2, "mc68328_r (%04x): HMSR(16) = %04x\n", mem_mask, m_regs.hmsr >> 16);
- return m_regs.hmsr >> 16;
-
- case 0xb04:
- verboselog(machine(), 2, "mc68328_r (%04x): ALARM(0) = %04x\n", mem_mask, m_regs.alarm & 0x0000ffff);
- return m_regs.alarm & 0x0000ffff;
-
- case 0xb06:
- verboselog(machine(), 2, "mc68328_r (%04x): ALARM(16) = %04x\n", mem_mask, m_regs.alarm >> 16);
- return m_regs.alarm >> 16;
-
- case 0xb0c:
- verboselog(machine(), 2, "mc68328_r (%04x): RTCCTL = %04x\n", mem_mask, m_regs.rtcctl);
- return m_regs.rtcctl;
-
- case 0xb0e:
- verboselog(machine(), 2, "mc68328_r (%04x): RTCISR = %04x\n", mem_mask, m_regs.rtcisr);
- return m_regs.rtcisr;
-
- case 0xb10:
- verboselog(machine(), 2, "mc68328_r (%04x): RTCIENR = %04x\n", mem_mask, m_regs.rtcienr);
- return m_regs.rtcienr;
-
- case 0xb12:
- verboselog(machine(), 2, "mc68328_r (%04x): STPWTCH = %04x\n", mem_mask, m_regs.stpwtch);
- return m_regs.stpwtch;
-
- default:
- verboselog(machine(), 0, "mc68328_r (%04x): Unknown address (0x%06x)\n", mem_mask, 0xfff000 + address);
- break;
- }
- return 0;
-}
-
-/* THIS IS PRETTY MUCH TOTALLY WRONG AND DOESN'T REFLECT THE MC68328'S INTERNAL FUNCTIONALITY AT ALL! */
-UINT32 mc68328_device::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
-{
- UINT16 *video_ram = (UINT16 *)(machine().device<ram_device>(RAM_TAG)->pointer() + (m_regs.lssa & 0x00ffffff));
- UINT16 word;
- UINT16 *line;
- int y, x, b;
-
- if (m_regs.lckcon & LCKCON_LCDC_EN)
- {
- for (y = 0; y < 160; y++)
- {
- line = &bitmap.pix16(y);
-
- for (x = 0; x < 160; x += 16)
- {
- word = *(video_ram++);
- for (b = 0; b < 16; b++)
- {
- line[x + b] = (word >> (15 - b)) & 0x0001;
- }
- }
- }
- }
- else
- {
- for (y = 0; y < 160; y++)
- {
- line = &bitmap.pix16(y);
-
- for (x = 0; x < 160; x++)
- {
- line[x] = 0;
- }
- }
- }
- return 0;
-}
-
-
-void mc68328_device::register_state_save()
-{
- save_item(NAME(m_regs.scr));
- save_item(NAME(m_regs.grpbasea));
- save_item(NAME(m_regs.grpbaseb));
- save_item(NAME(m_regs.grpbasec));
- save_item(NAME(m_regs.grpbased));
- save_item(NAME(m_regs.grpmaska));
- save_item(NAME(m_regs.grpmaskb));
- save_item(NAME(m_regs.grpmaskc));
- save_item(NAME(m_regs.grpmaskd));
- save_item(NAME(m_regs.csa0));
- save_item(NAME(m_regs.csa1));
- save_item(NAME(m_regs.csa2));
- save_item(NAME(m_regs.csa3));
- save_item(NAME(m_regs.csb0));
- save_item(NAME(m_regs.csb1));
- save_item(NAME(m_regs.csb2));
- save_item(NAME(m_regs.csb3));
- save_item(NAME(m_regs.csc0));
- save_item(NAME(m_regs.csc1));
- save_item(NAME(m_regs.csc2));
- save_item(NAME(m_regs.csc3));
- save_item(NAME(m_regs.csd0));
- save_item(NAME(m_regs.csd1));
- save_item(NAME(m_regs.csd2));
- save_item(NAME(m_regs.csd3));
-
- save_item(NAME(m_regs.pllcr));
- save_item(NAME(m_regs.pllfsr));
- save_item(NAME(m_regs.pctlr));
-
- save_item(NAME(m_regs.ivr));
- save_item(NAME(m_regs.icr));
- save_item(NAME(m_regs.imr));
- save_item(NAME(m_regs.iwr));
- save_item(NAME(m_regs.isr));
- save_item(NAME(m_regs.ipr));
-
- save_item(NAME(m_regs.padir));
- save_item(NAME(m_regs.padata));
- save_item(NAME(m_regs.pasel));
- save_item(NAME(m_regs.pbdir));
- save_item(NAME(m_regs.pbdata));
- save_item(NAME(m_regs.pbsel));
- save_item(NAME(m_regs.pcdir));
- save_item(NAME(m_regs.pcdata));
- save_item(NAME(m_regs.pcsel));
- save_item(NAME(m_regs.pddir));
- save_item(NAME(m_regs.pddata));
- save_item(NAME(m_regs.pdpuen));
- save_item(NAME(m_regs.pdpol));
- save_item(NAME(m_regs.pdirqen));
- save_item(NAME(m_regs.pddataedge));
- save_item(NAME(m_regs.pdirqedge));
- save_item(NAME(m_regs.pedir));
- save_item(NAME(m_regs.pedata));
- save_item(NAME(m_regs.pepuen));
- save_item(NAME(m_regs.pesel));
- save_item(NAME(m_regs.pfdir));
- save_item(NAME(m_regs.pfdata));
- save_item(NAME(m_regs.pfpuen));
- save_item(NAME(m_regs.pfsel));
- save_item(NAME(m_regs.pgdir));
- save_item(NAME(m_regs.pgdata));
- save_item(NAME(m_regs.pgpuen));
- save_item(NAME(m_regs.pgsel));
- save_item(NAME(m_regs.pjdir));
- save_item(NAME(m_regs.pjdata));
- save_item(NAME(m_regs.pjsel));
- save_item(NAME(m_regs.pkdir));
- save_item(NAME(m_regs.pkdata));
- save_item(NAME(m_regs.pkpuen));
- save_item(NAME(m_regs.pksel));
- save_item(NAME(m_regs.pmdir));
- save_item(NAME(m_regs.pmdata));
- save_item(NAME(m_regs.pmpuen));
- save_item(NAME(m_regs.pmsel));
-
- save_item(NAME(m_regs.pwmc));
- save_item(NAME(m_regs.pwmp));
- save_item(NAME(m_regs.pwmw));
- save_item(NAME(m_regs.pwmcnt));
-
- save_item(NAME(m_regs.tctl[0]));
- save_item(NAME(m_regs.tctl[1]));
- save_item(NAME(m_regs.tprer[0]));
- save_item(NAME(m_regs.tprer[1]));
- save_item(NAME(m_regs.tcmp[0]));
- save_item(NAME(m_regs.tcmp[1]));
- save_item(NAME(m_regs.tcr[0]));
- save_item(NAME(m_regs.tcr[1]));
- save_item(NAME(m_regs.tcn[0]));
- save_item(NAME(m_regs.tcn[1]));
- save_item(NAME(m_regs.tstat[0]));
- save_item(NAME(m_regs.tstat[1]));
- save_item(NAME(m_regs.wctlr));
- save_item(NAME(m_regs.wcmpr));
- save_item(NAME(m_regs.wcn));
-
- save_item(NAME(m_regs.spisr));
-
- save_item(NAME(m_regs.spimdata));
- save_item(NAME(m_regs.spimcont));
-
- save_item(NAME(m_regs.ustcnt));
- save_item(NAME(m_regs.ubaud));
- save_item(NAME(m_regs.urx));
- save_item(NAME(m_regs.utx));
- save_item(NAME(m_regs.umisc));
-
- save_item(NAME(m_regs.lssa));
- save_item(NAME(m_regs.lvpw));
- save_item(NAME(m_regs.lxmax));
- save_item(NAME(m_regs.lymax));
- save_item(NAME(m_regs.lcxp));
- save_item(NAME(m_regs.lcyp));
- save_item(NAME(m_regs.lcwch));
- save_item(NAME(m_regs.lblkc));
- save_item(NAME(m_regs.lpicf));
- save_item(NAME(m_regs.lpolcf));
- save_item(NAME(m_regs.lacdrc));
- save_item(NAME(m_regs.lpxcd));
- save_item(NAME(m_regs.lckcon));
- save_item(NAME(m_regs.llbar));
- save_item(NAME(m_regs.lotcr));
- save_item(NAME(m_regs.lposr));
- save_item(NAME(m_regs.lfrcm));
- save_item(NAME(m_regs.lgpmr));
-
- save_item(NAME(m_regs.hmsr));
- save_item(NAME(m_regs.alarm));
- save_item(NAME(m_regs.rtcctl));
- save_item(NAME(m_regs.rtcisr));
- save_item(NAME(m_regs.rtcienr));
- save_item(NAME(m_regs.stpwtch));
-}
diff --git a/src/mess/machine/mc68328.h b/src/mess/machine/mc68328.h
deleted file mode 100644
index 78ed79fa43b..00000000000
--- a/src/mess/machine/mc68328.h
+++ /dev/null
@@ -1,725 +0,0 @@
-/**********************************************************************
-
- Motorola 68328 ("DragonBall") System-on-a-Chip implementation
-
- By MooglyGuy
- contact mooglyguy@gmail.com with licensing and usage questions.
-
- **********************************************************************/
-
-/*****************************************************************************************************************
-
- P P P P P P P P P P P P P P
- E E E E E E E J J J J J J J
- 1 2 3 4 5 6 7 0 1 2 3 4 5 6
- D D D D D / / / / / / / / / / / / / /
- 3 4 5 6 7 ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
- / / / / / ! ! C C C C C C C C C C C C C C C
- P V P P P P D D G D D D D T T L U V S S S S S S S S G S S S S S S S
- B C B B B B D D 1 1 N 1 1 1 1 M C W W C A A A A B B B B N C C C C D D D
- 3 C 4 5 6 7 8 9 0 1 D 2 3 4 5 S K E E C 0 1 2 3 0 1 2 3 D 0 1 2 3 0 1 2
- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
- +-------------------------------------------------------------------------------+
- | |
- | |
- | |
- | |
- | |
- D2/PB2--| |--PJ7/!CSD3
- D1/PB1--| |--VCC
- D0/PB0--| |--PD0/!KBD0/!INT0
- TDO--| |--PD1/!KBD1/!INT1
- TDI--| |--PD2/!KBD2/!INT2
- GND--| |--PD3/!KBD3/!INT3
- !OE--| |--PD4/!KBD4/!INT4
- !UDS/PC1--| |--PD5/!KBD5/!INT5
- !AS--| |--PD6/!KBD6/!INT6
- A0--| |--PD7/!KBD7/!INT7
- !LDS--| |--GND
- R/!W--| |--LD0
- !DTACK/PC5--| |--LD1
- !RESET--| |--LD2
- VCC--| |--LD3
- !WE/PC6--| |--LFRM
- !JTAGRST--| |--LLP
- BBUSW--| MC68328PV |--LCLK
- A1--| TOP VIEW |--LACD
- A2--| |--VCC
- A3--| |--PK0/SPMTXD0
- A4--| |--PK1/SPMRXD0
- A5--| |--PK2/SPMCLK0
- A6--| |--PK3/SPSEN
- GND--| |--PK4/SPSRXD1
- A7--| |--PK5/SPSCLK1
- A8--| |--PK6/!CE2
- A9--| |--PK7/!CE1
- A10--| |--GND
- A11--| |--PM0/!CTS
- A12--| |--PM1/!RTS
- A13--| |--PM2/!IRQ6
- A14--| |--PM3/!IRQ3
- VCC--| |--PM4/!IRQ2
- A15--| |--PM5/!IRQ1
- A16/PA0--| |--PM6/!PENIRQ
- | |
- | _ |
- | (_) |
- |\ |
- | \ |
- +-------------------------------------------------------------------------------+
- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
- P P P P P G P P P P P P P P V P P P P P P P P G P P P V C G P P P E X P
- A A A A A N A A F F F F F F C F F G G G G G G N G G C C L N C M L X T L
- 1 2 3 4 5 D 6 7 0 1 2 3 4 5 C 6 7 7 6 5 4 3 2 D 1 0 0 C K D 4 7 L T A L
- / / / / / / / / / / / / / / / / / / / / / / / / O / / G A L V
- A A A A A A A A A A A A A A A R T ! T ! P R T M ! U N L C
- 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 T I T I T W X X O I A D C
- 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 C N O N O M D D C R R
- O 1 U 2 U O L Q T
- T T K 7 G
- 1 2 P
- I
- O
-
- Figure 12-1. MC68328 144-Lead Plastic Thin-Quad Flat Pack Pin Assignment
-
- Source: MC68328 (DragonBall)(tm) Integrated Processor User's Manual
-
- *****************************************************************************************************************/
-
-#ifndef __MC68328_H__
-#define __MC68328_H__
-
-
-#define SCR_BETO 0x80
-#define SCR_WPV 0x40
-#define SCR_PRV 0x20
-#define SCR_BETEN 0x10
-#define SCR_SO 0x08
-#define SCR_DMAP 0x04
-#define SCR_WDTH8 0x01
-
-#define ICR_POL6 0x0100
-#define ICR_POL3 0x0200
-#define ICR_POL2 0x0400
-#define ICR_POL1 0x0800
-#define ICR_ET6 0x1000
-#define ICR_ET3 0x2000
-#define ICR_ET2 0x4000
-#define ICR_ET1 0x8000
-
-#define INT_SPIM 0x000001
-#define INT_TIMER2 0x000002
-#define INT_UART 0x000004
-#define INT_WDT 0x000008
-#define INT_RTC 0x000010
-#define INT_RESERVED 0x000020
-#define INT_KB 0x000040
-#define INT_PWM 0x000080
-#define INT_INT0 0x000100
-#define INT_INT1 0x000200
-#define INT_INT2 0x000400
-#define INT_INT3 0x000800
-#define INT_INT4 0x001000
-#define INT_INT5 0x002000
-#define INT_INT6 0x004000
-#define INT_INT7 0x008000
-#define INT_KBDINTS 0x00ff00
-#define INT_IRQ1 0x010000
-#define INT_IRQ2 0x020000
-#define INT_IRQ3 0x040000
-#define INT_IRQ6 0x080000
-#define INT_PEN 0x100000
-#define INT_SPIS 0x200000
-#define INT_TIMER1 0x400000
-#define INT_IRQ7 0x800000
-
-#define INT_M68K_LINE1 (INT_IRQ1)
-#define INT_M68K_LINE2 (INT_IRQ2)
-#define INT_M68K_LINE3 (INT_IRQ3)
-#define INT_M68K_LINE4 (INT_INT0 | INT_INT1 | INT_INT2 | INT_INT3 | INT_INT4 | INT_INT5 | INT_INT6 | INT_INT7 | \
- INT_PWM | INT_KB | INT_RTC | INT_WDT | INT_UART | INT_TIMER2 | INT_SPIM)
-#define INT_M68K_LINE5 (INT_PEN)
-#define INT_M68K_LINE6 (INT_IRQ6 | INT_TIMER1 | INT_SPIS)
-#define INT_M68K_LINE7 (INT_IRQ7)
-#define INT_M68K_LINE67 (INT_M68K_LINE6 | INT_M68K_LINE7)
-#define INT_M68K_LINE567 (INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7)
-#define INT_M68K_LINE4567 (INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7)
-#define INT_M68K_LINE34567 (INT_M68K_LINE3 | INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7)
-#define INT_M68K_LINE234567 (INT_M68K_LINE2 | INT_M68K_LINE3 | INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7)
-
-#define INT_IRQ1_SHIFT 0x000001
-#define INT_IRQ2_SHIFT 0x000002
-#define INT_IRQ3_SHIFT 0x000004
-#define INT_IRQ6_SHIFT 0x000008
-#define INT_PEN_SHIFT 0x000010
-#define INT_SPIS_SHIFT 0x000020
-#define INT_TIMER1_SHIFT 0x000040
-#define INT_IRQ7_SHIFT 0x000080
-
-#define INT_ACTIVE 1
-#define INT_INACTIVE 0
-
-#define GRPBASE_BASE_ADDR 0xfff0
-#define GRPBASE_VALID 0x0001
-
-#define GRPMASK_BASE_MASK 0xfff0
-
-#define CSAB_COMPARE 0xff000000
-#define CSAB_BSW 0x00010000
-#define CSAB_MASK 0x0000ff00
-#define CSAB_RO 0x00000008
-#define CSAB_WAIT 0x00000007
-
-#define CSCD_COMPARE 0xfff00000
-#define CSCD_BSW 0x00010000
-#define CSCD_MASK 0x0000fff0
-#define CSCD_RO 0x00000008
-#define CSCD_WAIT 0x00000007
-
-#define PLLCR_PIXCLK_SEL 0x3800
-#define PLLCR_PIXCLK_SEL_DIV2 0x0000
-#define PLLCR_PIXCLK_SEL_DIV4 0x0800
-#define PLLCR_PIXCLK_SEL_DIV8 0x1000
-#define PLLCR_PIXCLK_SEL_DIV16 0x1800
-#define PLLCR_PIXCLK_SEL_DIV1_0 0x2000
-#define PLLCR_PIXCLK_SEL_DIV1_1 0x2800
-#define PLLCR_PIXCLK_SEL_DIV1_2 0x3000
-#define PLLCR_PIXCLK_SEL_DIV1_3 0x3800
-#define PLLCR_SYSCLK_SEL 0x0700
-#define PLLCR_SYSCLK_SEL_DIV2 0x0000
-#define PLLCR_SYSCLK_SEL_DIV4 0x0100
-#define PLLCR_SYSCLK_SEL_DIV8 0x0200
-#define PLLCR_SYSCLK_SEL_DIV16 0x0300
-#define PLLCR_SYSCLK_SEL_DIV1_0 0x0400
-#define PLLCR_SYSCLK_SEL_DIV1_1 0x0500
-#define PLLCR_SYSCLK_SEL_DIV1_2 0x0600
-#define PLLCR_SYSCLK_SEL_DIV1_3 0x0700
-#define PLLCR_CLKEN 0x0010
-#define PLLCR_DISPLL 0x0008
-
-#define PLLFSR_CLK32 0x8000
-#define PLLFSR_PROT 0x4000
-#define PLLFSR_QCNT 0x0f00
-#define PLLFSR_PCNT 0x00ff
-
-#define PCTLR_PC_EN 0x80
-#define PCTLR_STOP 0x40
-#define PCTLR_WIDTH 0x1f
-
-#define CXP_CC 0xc000
-#define CXP_CC_XLU 0x0000
-#define CXP_CC_BLACK 0x4000
-#define CXP_CC_INVERSE 0x8000
-#define CXP_CC_INVALID 0xc000
-#define CXP_MASK 0x03ff
-
-#define CYP_MASK 0x01ff
-
-#define CWCH_CW 0x1f00
-#define CWCH_CH 0x001f
-
-#define BLKC_BKEN 0x80
-#define BLKC_BD 0x7f
-
-#define LPICF_PBSIZ 0x06
-#define LPICF_PBSIZ_1 0x00
-#define LPICF_PBSIZ_2 0x02
-#define LPICF_PBSIZ_4 0x04
-#define LPICF_PBSIZ_INVALID 0x06
-
-#define LPOLCF_LCKPOL 0x08
-#define LPOLCF_FLMPOL 0x04
-#define LPOLCF_LPPOL 0x02
-#define LPOLCF_PIXPOL 0x01
-
-#define LACDRC_MASK 0x0f
-
-#define LPXCD_MASK 0x3f
-
-#define LCKCON_LCDC_EN 0x80
-#define LCKCON_LCDON 0x80
-#define LCKCON_DMA16 0x40
-#define LCKCON_WS 0x30
-#define LCKCON_WS_1 0x00
-#define LCKCON_WS_2 0x10
-#define LCKCON_WS_3 0x20
-#define LCKCON_WS_4 0x30
-#define LCKCON_DWIDTH 0x02
-#define LCKCON_PCDS 0x01
-
-#define LBAR_MASK 0x7f
-
-#define LPOSR_BOS 0x08
-#define LPOSR_POS 0x07
-
-#define LFRCM_XMOD 0xf0
-#define LFRCM_YMOD 0x0f
-
-#define LGPMR_PAL1 0x7000
-#define LGPMR_PAL0 0x0700
-#define LGPMR_PAL3 0x0070
-#define LGPMR_PAL2 0x0007
-
-#define RTCHMSR_HOURS 0x1f000000
-#define RTCHMSR_MINUTES 0x003f0000
-#define RTCHMSR_SECONDS 0x0000003f
-
-#define RTCCTL_38_4 0x0020
-#define RTCCTL_ENABLE 0x0080
-
-#define RTCINT_STOPWATCH 0x0001
-#define RTCINT_MINUTE 0x0002
-#define RTCINT_ALARM 0x0004
-#define RTCINT_DAY 0x0008
-#define RTCINT_SECOND 0x0010
-
-#define RTCSTPWTCH_MASK 0x003f
-
-#define TCTL_TEN 0x0001
-#define TCTL_TEN_ENABLE 0x0001
-#define TCTL_CLKSOURCE 0x000e
-#define TCTL_CLKSOURCE_STOP 0x0000
-#define TCTL_CLKSOURCE_SYSCLK 0x0002
-#define TCTL_CLKSOURCE_SYSCLK16 0x0004
-#define TCTL_CLKSOURCE_TIN 0x0006
-#define TCTL_CLKSOURCE_32KHZ4 0x0008
-#define TCTL_CLKSOURCE_32KHZ5 0x000a
-#define TCTL_CLKSOURCE_32KHZ6 0x000c
-#define TCTL_CLKSOURCE_32KHZ7 0x000e
-#define TCTL_IRQEN 0x0010
-#define TCTL_IRQEN_ENABLE 0x0010
-#define TCTL_OM 0x0020
-#define TCTL_OM_ACTIVELOW 0x0000
-#define TCTL_OM_TOGGLE 0x0020
-#define TCTL_CAPTURE 0x00c0
-#define TCTL_CAPTURE_NOINT 0x0000
-#define TCTL_CAPTURE_RISING 0x0040
-#define TCTL_CAPTURE_FALLING 0x0080
-#define TCTL_CAPTURE_BOTH 0x00c0
-#define TCTL_FRR 0x0100
-#define TCTL_FRR_RESTART 0x0000
-#define TCTL_FRR_FREERUN 0x0100
-
-#define TSTAT_COMP 0x0001
-#define TSTAT_CAPT 0x0002
-
-#define WCTLR_WDRST 0x0008
-#define WCTLR_LOCK 0x0004
-#define WCTLR_FI 0x0002
-#define WCTLR_WDEN 0x0001
-
-#define USTCNT_UART_EN 0x8000
-#define USTCNT_RX_EN 0x4000
-#define USTCNT_TX_EN 0x2000
-#define USTCNT_RX_CLK_CONT 0x1000
-#define USTCNT_PARITY_EN 0x0800
-#define USTCNT_ODD_EVEN 0x0400
-#define USTCNT_STOP_BITS 0x0200
-#define USTCNT_8_7 0x0100
-#define USTCNT_GPIO_DELTA_EN 0x0080
-#define USTCNT_CTS_DELTA_EN 0x0040
-#define USTCNT_RX_FULL_EN 0x0020
-#define USTCNT_RX_HALF_EN 0x0010
-#define USTCNT_RX_RDY_EN 0x0008
-#define USTCNT_TX_EMPTY_EN 0x0004
-#define USTCNT_TX_HALF_EN 0x0002
-#define USTCNT_TX_AVAIL_EN 0x0001
-
-#define UBAUD_GPIO_DELTA 0x8000
-#define UBAUD_GPIO 0x4000
-#define UBAUD_GPIO_DIR 0x2000
-#define UBAUD_GPIO_SRC 0x1000
-#define UBAUD_BAUD_SRC 0x0800
-#define UBAUD_DIVIDE 0x0700
-#define UBAUD_DIVIDE_1 0x0000
-#define UBAUD_DIVIDE_2 0x0100
-#define UBAUD_DIVIDE_4 0x0200
-#define UBAUD_DIVIDE_8 0x0300
-#define UBAUD_DIVIDE_16 0x0400
-#define UBAUD_DIVIDE_32 0x0500
-#define UBAUD_DIVIDE_64 0x0600
-#define UBAUD_DIVIDE_128 0x0700
-#define UBAUD_PRESCALER 0x00ff
-
-#define URX_FIFO_FULL 0x8000
-#define URX_FIFO_HALF 0x4000
-#define URX_DATA_READY 0x2000
-#define URX_OVRUN 0x0800
-#define URX_FRAME_ERROR 0x0400
-#define URX_BREAK 0x0200
-#define URX_PARITY_ERROR 0x0100
-
-#define UTX_FIFO_EMPTY 0x8000
-#define UTX_FIFO_HALF 0x4000
-#define UTX_TX_AVAIL 0x2000
-#define UTX_SEND_BREAK 0x1000
-#define UTX_IGNORE_CTS 0x0800
-#define UTX_CTS_STATUS 0x0200
-#define UTX_CTS_DELTA 0x0100
-
-#define UMISC_CLK_SRC 0x4000
-#define UMISC_FORCE_PERR 0x2000
-#define UMISC_LOOP 0x1000
-#define UMISC_RTS_CONT 0x0080
-#define UMISC_RTS 0x0040
-#define UMISC_IRDA_ENABLE 0x0020
-#define UMISC_IRDA_LOOP 0x0010
-
-#define SPIS_SPIS_IRQ 0x8000
-#define SPIS_IRQEN 0x4000
-#define SPIS_ENPOL 0x2000
-#define SPIS_DATA_RDY 0x1000
-#define SPIS_OVRWR 0x0800
-#define SPIS_PHA 0x0400
-#define SPIS_POL 0x0200
-#define SPIS_SPISEN 0x0100
-
-#define SPIM_CLOCK_COUNT 0x000f
-#define SPIM_POL 0x0010
-#define SPIM_POL_HIGH 0x0000
-#define SPIM_POL_LOW 0x0010
-#define SPIM_PHA 0x0020
-#define SPIM_PHA_NORMAL 0x0000
-#define SPIM_PHA_OPPOSITE 0x0020
-#define SPIM_IRQEN 0x0040
-#define SPIM_SPIMIRQ 0x0080
-#define SPIM_XCH 0x0100
-#define SPIM_XCH_IDLE 0x0000
-#define SPIM_XCH_INIT 0x0100
-#define SPIM_SPMEN 0x0200
-#define SPIM_SPMEN_DISABLE 0x0000
-#define SPIM_SPMEN_ENABLE 0x0200
-#define SPIM_RATE 0xe000
-#define SPIM_RATE_4 0x0000
-#define SPIM_RATE_8 0x2000
-#define SPIM_RATE_16 0x4000
-#define SPIM_RATE_32 0x6000
-#define SPIM_RATE_64 0x8000
-#define SPIM_RATE_128 0xa000
-#define SPIM_RATE_256 0xc000
-#define SPIM_RATE_512 0xe000
-
-#define PWMC_PWMIRQ 0x8000
-#define PWMC_IRQEN 0x4000
-#define PWMC_LOAD 0x0100
-#define PWMC_PIN 0x0080
-#define PWMC_POL 0x0040
-#define PWMC_PWMEN 0x0010
-#define PWMC_CLKSEL 0x0007
-
-
-struct mc68328_interface
-{
- const char *m68k_cpu_tag;
-
- devcb_write8 m_out_port_a_func; /* 8-bit output */
- devcb_write8 m_out_port_b_func; /* 8-bit output */
- devcb_write8 m_out_port_c_func; /* 8-bit output */
- devcb_write8 m_out_port_d_func; /* 8-bit output */
- devcb_write8 m_out_port_e_func; /* 8-bit output */
- devcb_write8 m_out_port_f_func; /* 8-bit output */
- devcb_write8 m_out_port_g_func; /* 8-bit output */
- devcb_write8 m_out_port_j_func; /* 8-bit output */
- devcb_write8 m_out_port_k_func; /* 8-bit output */
- devcb_write8 m_out_port_m_func; /* 8-bit output */
-
- devcb_read8 m_in_port_a_func; /* 8-bit input */
- devcb_read8 m_in_port_b_func; /* 8-bit input */
- devcb_read8 m_in_port_c_func; /* 8-bit input */
- devcb_read8 m_in_port_d_func; /* 8-bit input */
- devcb_read8 m_in_port_e_func; /* 8-bit input */
- devcb_read8 m_in_port_f_func; /* 8-bit input */
- devcb_read8 m_in_port_g_func; /* 8-bit input */
- devcb_read8 m_in_port_j_func; /* 8-bit input */
- devcb_read8 m_in_port_k_func; /* 8-bit input */
- devcb_read8 m_in_port_m_func; /* 8-bit input */
-
- devcb_write8 m_out_pwm_func; /* 1-bit output */
-
- devcb_write16 m_out_spim_func; /* 16-bit output */
- devcb_read16 m_in_spim_func; /* 16-bit input */
-
- devcb_write_line m_spim_xch_trigger_func; /* SPIM exchange trigger */
-};
-
-
-struct mc68328_regs_t
-{
- // $(FF)FFF000
- UINT8 scr; // System Control Register
- UINT8 unused0[255];
-
- // $(FF)FFF100
- UINT16 grpbasea; // Chip Select Group A Base Register
- UINT16 grpbaseb; // Chip Select Group B Base Register
- UINT16 grpbasec; // Chip Select Group C Base Register
- UINT16 grpbased; // Chip Select Group D Base Register
- UINT16 grpmaska; // Chip Select Group A Mask Register
- UINT16 grpmaskb; // Chip Select Group B Mask Register
- UINT16 grpmaskc; // Chip Select Group C Mask Register
- UINT16 grpmaskd; // Chip Select Group D Mask Register
- UINT32 csa0; // Group A Chip Select 0 Register
- UINT32 csa1; // Group A Chip Select 1 Register
- UINT32 csa2; // Group A Chip Select 2 Register
- UINT32 csa3; // Group A Chip Select 3 Register
- UINT32 csb0; // Group B Chip Select 0 Register
- UINT32 csb1; // Group B Chip Select 1 Register
- UINT32 csb2; // Group B Chip Select 2 Register
- UINT32 csb3; // Group B Chip Select 3 Register
- UINT32 csc0; // Group C Chip Select 0 Register
- UINT32 csc1; // Group C Chip Select 1 Register
- UINT32 csc2; // Group C Chip Select 2 Register
- UINT32 csc3; // Group C Chip Select 3 Register
- UINT32 csd0; // Group D Chip Select 0 Register
- UINT32 csd1; // Group D Chip Select 1 Register
- UINT32 csd2; // Group D Chip Select 2 Register
- UINT32 csd3; // Group D Chip Select 3 Register
- UINT8 unused1[176];
-
- // $(FF)FFF200
- UINT16 pllcr; // PLL Control Register
- UINT16 pllfsr; // PLL Frequency Select Register
- UINT8 pad2[3];
- UINT8 pctlr; // Power Control Register
- UINT8 unused3[248];
-
- // $(FF)FFF300
- UINT8 ivr; // Interrupt Vector Register
- UINT8 unused4[1];
- UINT16 icr; // Interrupt Control Register
- UINT32 imr; // Interrupt Mask Register
- UINT32 iwr; // Interrupt Wakeup Enable Register
- UINT32 isr; // Interrupt Status Register
- UINT32 ipr; // Interrupt Pending Register
- UINT8 unused5[236];
-
- // $(FF)FFF400
- UINT8 padir; // Port A Direction Register
- UINT8 padata; // Port A Data Register
- UINT8 unused6[1];
- UINT8 pasel; // Port A Select Register
- UINT8 unused7[4];
-
- UINT8 pbdir; // Port B Direction Register
- UINT8 pbdata; // Port B Data Register
- UINT8 unused8[1];
- UINT8 pbsel; // Port B Select Register
- UINT8 unused9[4];
-
- UINT8 pcdir; // Port C Direction Register
- UINT8 pcdata; // Port C Data Register
- UINT8 unused10[1];
- UINT8 pcsel; // Port C Select Register
- UINT8 unused11[4];
-
- UINT8 pddir; // Port D Direction Register
- UINT8 pddata; // Port D Data Register
- UINT8 pdpuen; // Port D Pullup Enable Register
- UINT8 unused12[1];
- UINT8 pdpol; // Port D Polarity Register
- UINT8 pdirqen; // Port D IRQ Enable Register
- UINT8 pddataedge; // Port D Data Edge Level
- UINT8 pdirqedge; // Port D IRQ Edge Register
-
- UINT8 pedir; // Port E Direction Register
- UINT8 pedata; // Port E Data Register
- UINT8 pepuen; // Port E Pullup Enable Register
- UINT8 pesel; // Port E Select Register
- UINT8 unused14[4];
-
- UINT8 pfdir; // Port F Direction Register
- UINT8 pfdata; // Port F Data Register
- UINT8 pfpuen; // Port F Pullup Enable Register
- UINT8 pfsel; // Port F Select Register
- UINT8 unused15[4];
-
- UINT8 pgdir; // Port G Direction Register
- UINT8 pgdata; // Port G Data Register
- UINT8 pgpuen; // Port G Pullup Enable Register
- UINT8 pgsel; // Port G Select Register
- UINT8 unused16[4];
-
- UINT8 pjdir; // Port J Direction Register
- UINT8 pjdata; // Port J Data Register
- UINT8 unused17[1];
- UINT8 pjsel; // Port J Select Register
- UINT8 unused18[4];
- UINT8 pkdir; // Port K Direction Register
- UINT8 pkdata; // Port K Data Register
- UINT8 pkpuen; // Port K Pullup Enable Register
- UINT8 pksel; // Port K Select Register
- UINT8 unused19[4];
-
- UINT8 pmdir; // Port M Direction Register
- UINT8 pmdata; // Port M Data Register
- UINT8 pmpuen; // Port M Pullup Enable Register
- UINT8 pmsel; // Port M Select Register
- UINT8 unused20[180];
-
- // $(FF)FFF500
- UINT16 pwmc; // PWM Control Register
- UINT16 pwmp; // PWM Period Register
- UINT16 pwmw; // PWM Width Register
- UINT16 pwmcnt; // PWN Counter
- UINT8 unused21[248];
-
- // $(FF)FFF600
- UINT16 tctl[2]; // Timer Control Register
- UINT16 tprer[2]; // Timer Prescaler Register
- UINT16 tcmp[2]; // Timer Compare Register
- UINT16 tcr[2]; // Timer Capture Register
- UINT16 tcn[2]; // Timer Counter
- UINT16 tstat[2]; // Timer Status
- UINT16 wctlr; // Watchdog Control Register
- UINT16 wcmpr; // Watchdog Compare Register
- UINT16 wcn; // Watchdog Counter
- UINT8 tclear[2]; // Timer Clearable Status
- UINT8 unused22[224];
-
- // $(FF)FFF700
- UINT16 spisr; // SPIS Register
- UINT8 unused23[254];
-
- // $(FF)FFF800
- UINT16 spimdata; // SPIM Data Register
- UINT16 spimcont; // SPIM Control/Status Register
- UINT8 unused24[252];
-
- // $(FF)FFF900
- UINT16 ustcnt; // UART Status/Control Register
- UINT16 ubaud; // UART Baud Control Register
- UINT16 urx; // UART RX Register
- UINT16 utx; // UART TX Register
- UINT16 umisc; // UART Misc Register
- UINT8 unused25[246];
-
- // $(FF)FFFA00
- UINT32 lssa; // Screen Starting Address Register
- UINT8 unused26[1];
- UINT8 lvpw; // Virtual Page Width Register
- UINT8 unused27[2];
- UINT16 lxmax; // Screen Width Register
- UINT16 lymax; // Screen Height Register
- UINT8 unused28[12];
- UINT16 lcxp; // Cursor X Position
- UINT16 lcyp; // Cursor Y Position
- UINT16 lcwch; // Cursor Width & Height Register
- UINT8 unused29[1];
- UINT8 lblkc; // Blink Control Register
- UINT8 lpicf; // Panel Interface Config Register
- UINT8 lpolcf; // Polarity Config Register
- UINT8 unused30[1];
- UINT8 lacdrc; // ACD (M) Rate Control Register
- UINT8 unused31[1];
- UINT8 lpxcd; // Pixel Clock Divider Register
- UINT8 unused32[1];
- UINT8 lckcon; // Clocking Control Register
- UINT8 unused33[1];
- UINT8 llbar; // Last Buffer Address Register
- UINT8 unused34[1];
- UINT8 lotcr; // Octet Terminal Count Register
- UINT8 unused35[1];
- UINT8 lposr; // Panning Offset Register
- UINT8 unused36[3];
- UINT8 lfrcm; // Frame Rate Control Modulation Register
- UINT16 lgpmr; // Gray Palette Mapping Register
- UINT8 unused37[204];
-
- // $(FF)FFFB00
- UINT32 hmsr; // RTC Hours Minutes Seconds Register
- UINT32 alarm; // RTC Alarm Register
- UINT8 unused38[4];
- UINT16 rtcctl; // RTC Control Register
- UINT16 rtcisr; // RTC Interrupt Status Register
- UINT16 rtcienr; // RTC Interrupt Enable Register
- UINT16 stpwtch; // Stopwatch Minutes
- UINT8 unused42[1260];
-};
-
-
-class mc68328_device : public device_t,
- public mc68328_interface
-{
-public:
- mc68328_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
- ~mc68328_device() {}
-
- DECLARE_WRITE16_MEMBER(write);
- DECLARE_READ16_MEMBER(read);
- DECLARE_WRITE_LINE_MEMBER(set_penirq_line);
- void set_port_d_lines(UINT8 state, int bit);
-
- UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
-
-protected:
- // device-level overrides
- virtual void device_config_complete();
- virtual void device_start();
- virtual void device_reset();
-
-private:
- // internal state
- void set_interrupt_line(UINT32 line, UINT32 active);
- void poll_port_d_interrupts();
- UINT32 get_timer_frequency(UINT32 index);
- void maybe_start_timer(UINT32 index, UINT32 new_enable);
- void timer_compare_event(UINT32 index);
-
- void register_state_save();
-
- TIMER_CALLBACK_MEMBER(timer1_hit);
- TIMER_CALLBACK_MEMBER(timer2_hit);
- TIMER_CALLBACK_MEMBER(pwm_transition);
- TIMER_CALLBACK_MEMBER(rtc_tick);
-
- mc68328_regs_t m_regs;
-
- emu_timer *m_gptimer[2];
- emu_timer *m_rtc;
- emu_timer *m_pwm;
-
- devcb_resolved_write8 m_out_port_a; /* 8-bit output */
- devcb_resolved_write8 m_out_port_b; /* 8-bit output */
- devcb_resolved_write8 m_out_port_c; /* 8-bit output */
- devcb_resolved_write8 m_out_port_d; /* 8-bit output */
- devcb_resolved_write8 m_out_port_e; /* 8-bit output */
- devcb_resolved_write8 m_out_port_f; /* 8-bit output */
- devcb_resolved_write8 m_out_port_g; /* 8-bit output */
- devcb_resolved_write8 m_out_port_j; /* 8-bit output */
- devcb_resolved_write8 m_out_port_k; /* 8-bit output */
- devcb_resolved_write8 m_out_port_m; /* 8-bit output */
-
- devcb_resolved_read8 m_in_port_a; /* 8-bit input */
- devcb_resolved_read8 m_in_port_b; /* 8-bit input */
- devcb_resolved_read8 m_in_port_c; /* 8-bit input */
- devcb_resolved_read8 m_in_port_d; /* 8-bit input */
- devcb_resolved_read8 m_in_port_e; /* 8-bit input */
- devcb_resolved_read8 m_in_port_f; /* 8-bit input */
- devcb_resolved_read8 m_in_port_g; /* 8-bit input */
- devcb_resolved_read8 m_in_port_j; /* 8-bit input */
- devcb_resolved_read8 m_in_port_k; /* 8-bit input */
- devcb_resolved_read8 m_in_port_m; /* 8-bit input */
-
- devcb_resolved_write8 m_out_pwm; /* 1-bit output */
-
- devcb_resolved_write16 m_out_spim; /* 16-bit output */
- devcb_resolved_read16 m_in_spim; /* 16-bit input */
-
- devcb_resolved_write_line m_spim_xch_trigger; // not really a write_line, fix when converting to devcb2!
-
- cpu_device *m_cpu;
-};
-
-
-#define MC68328_INTERFACE(name) const mc68328_interface (name)=
-
-
-#define MCFG_MC68328_ADD(_tag, _intrf) \
- MCFG_DEVICE_ADD(_tag, MC68328, 0) \
- MCFG_DEVICE_CONFIG(_intrf)
-
-extern const device_type MC68328;
-
-
-#endif
diff --git a/src/mess/machine/ncr5380.c b/src/mess/machine/ncr5380.c
deleted file mode 100644
index 7bdb27d414a..00000000000
--- a/src/mess/machine/ncr5380.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * ncr5380.c
- *
- * NCR 5380 SCSI controller, as seen in many 680x0 Macs,
- * official Apple add-on cards for the Apple II series,
- * and probably some PC and Amiga cards as well.
- *
- * Emulation by R. Belmont.
- *
- * References:
- * Zilog 5380 manual
- * "Inside Macintosh: Devices" (formerly online at http://www.manolium.org/dev/techsupport/insidemac/Devices/Devices-2.html )
- *
- * NOTES:
- * This implementation is tied closely to the drivers found in the Mac Plus ROM and the routines in Mac
- * System 6 and 7 that it patches out the ROM traps with. While attempts have been made to
- * have the behavior work according to the manual and not the specific Apple driver code,
- * there are almost certainly areas where that is true.
- *
- */
-
-#include "emu.h"
-#include "ncr5380.h"
-
-#define VERBOSE (0)
-
-static const char *const rnames[] =
-{
- "Current data",
- "Initiator cmd",
- "Mode",
- "Target cmd",
- "Bus status",
- "Bus and status",
- "Input data",
- "Reset parity"
-};
-
-static const char *const wnames[] =
-{
- "Output data",
- "Initiator cmd",
- "Mode",
- "Target cmd",
- "Select enable",
- "Start DMA",
- "DMA target",
- "DMA initiator rec"
-};
-
-// get the length of a SCSI command based on it's command byte type
-static int get_cmd_len(int cbyte)
-{
- int group;
-
- group = (cbyte>>5) & 7;
-
- if (group == 0) return 6;
- if (group == 1 || group == 2) return 10;
- if (group == 5) return 12;
-
- fatalerror("NCR5380: Unknown SCSI command group %d\n", group);
-
- return 6;
-}
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void ncr5380_device::device_config_complete()
-{
- // inherit a copy of the static data
- const NCR5380interface *intf = reinterpret_cast<const NCR5380interface *>(static_config());
- if (intf != NULL)
- *static_cast<NCR5380interface *>(this) = *intf;
-
- // or initialize to defaults if none provided
- else
- {
- memset(&m_irq_cb, 0, sizeof(m_irq_cb));
- }
-}
-
-//**************************************************************************
-// LIVE DEVICE
-//**************************************************************************
-
-const device_type NCR5380 = &device_creator<ncr5380_device>;
-
-//-------------------------------------------------
-// ncr5380_device - constructor/destructor
-//-------------------------------------------------
-
-ncr5380_device::ncr5380_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, NCR5380, "5380 SCSI", tag, owner, clock, "ncr5380", __FILE__)
-{
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void ncr5380_device::device_start()
-{
- memset(m_5380_Registers, 0, sizeof(m_5380_Registers));
- memset(m_5380_Data, 0, sizeof(m_5380_Data));
- memset(m_scsi_devices, 0, sizeof(m_scsi_devices));
-
- m_next_req_flag = 0;
- m_irq_func.resolve(m_irq_cb, *this);
-
- save_item(NAME(m_5380_Registers));
- save_item(NAME(m_5380_Command));
- save_item(NAME(m_5380_Data));
- save_item(NAME(m_last_id));
- save_item(NAME(m_cmd_ptr));
- save_item(NAME(m_d_ptr));
- save_item(NAME(m_d_limit));
- save_item(NAME(m_next_req_flag));
-
- // try to open the devices
- for( device_t *device = owner()->first_subdevice(); device != NULL; device = device->next() )
- {
- scsihle_device *scsidev = dynamic_cast<scsihle_device *>(device);
- if( scsidev != NULL )
- {
- m_scsi_devices[scsidev->GetDeviceID()] = scsidev;
- }
- }
-}
-
-//-------------------------------------------------
-// device_reset - device-specific reset
-//-------------------------------------------------
-
-void ncr5380_device::device_reset()
-{
- memset(m_5380_Registers, 0, sizeof(m_5380_Registers));
- memset(m_5380_Data, 0, sizeof(m_5380_Data));
-
- m_next_req_flag = 0;
- m_cmd_ptr = 0;
- m_d_ptr = 0;
- m_d_limit = 0;
- m_last_id = 0;
-}
-
-//-------------------------------------------------
-// device_stop - device-specific stop/shutdown
-//-------------------------------------------------
-void ncr5380_device::device_stop()
-{
-}
-
-//-------------------------------------------------
-// Public API
-//-------------------------------------------------
-UINT8 ncr5380_device::ncr5380_read_reg(UINT32 offset)
-{
- int reg = offset & 7;
- UINT8 rv = 0;
-
- switch( reg )
- {
- case R5380_CURDATA:
- case R5380_INPUTDATA:
- rv = m_5380_Registers[reg];
-
- // if we're in the data transfer phase or DMA, readback device data instead
- if (((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x04) || (m_5380_Registers[R5380_BUSSTATUS] & 0x40))
- {
- rv = m_5380_Data[m_d_ptr];
-
- // if the limit's less than 512, only read "limit" bytes
- if (m_d_limit < 512)
- {
- if (m_d_ptr < (m_d_limit-1))
- {
- m_d_ptr++;
- }
- else
- {
- m_next_req_flag = 1;
- }
- }
- else
- {
- if (m_d_ptr < 511)
- {
- m_d_ptr++;
- }
- else
- {
- m_d_limit -= 512;
- m_d_ptr = 0;
-
- m_next_req_flag = 1;
-
- // don't issue a "false" read
- if (m_d_limit > 0)
- {
- ncr5380_read_data((m_d_limit < 512) ? m_d_limit : 512, m_5380_Data);
- }
- else
- {
- // if this is DMA, signal DMA end
- if (m_5380_Registers[R5380_BUSSTATUS] & 0x40)
- {
- m_5380_Registers[R5380_BUSSTATUS] |= 0x80;
- }
-
- // drop /REQ
- m_5380_Registers[R5380_BUSSTATUS] &= ~0x20;
-
- // clear phase match
- m_5380_Registers[R5380_BUSANDSTAT] &= ~0x08;
- }
- }
- }
-
- }
- break;
-
- default:
- rv = m_5380_Registers[reg];
-
- // temporarily drop /REQ
- if ((reg == R5380_BUSSTATUS) && (m_next_req_flag))
- {
- rv &= ~0x20;
- m_next_req_flag = 0;
- }
- break;
- }
-
- if (VERBOSE)
- logerror("%s NCR5380: read %s (reg %d) = %02x\n", machine().describe_context(), rnames[reg], reg, rv);
-
- return rv;
-}
-
-void ncr5380_device::ncr5380_write_reg(UINT32 offset, UINT8 data)
-{
- int reg = offset & 7;
-
- if (VERBOSE)
- logerror("%s NCR5380: %02x to %s (reg %d)\n", machine().describe_context(), data, wnames[reg], reg);
-
- switch( reg )
- {
- case R5380_OUTDATA:
- // if we're in the command phase, collect the command bytes
- if ((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x08)
- {
- m_5380_Command[m_cmd_ptr++] = data;
- }
-
- // if we're in the select phase, this is the target id
- if (m_5380_Registers[R5380_INICOMMAND] == 0x04)
- {
- data &= 0x7f; // clear the high bit
- if (data == 0x40)
- {
- m_last_id = 6;
- }
- else if (data == 0x20)
- {
- m_last_id = 5;
- }
- else if (data == 0x10)
- {
- m_last_id = 4;
- }
- else if (data == 0x08)
- {
- m_last_id = 3;
- }
- else if (data == 0x04)
- {
- m_last_id = 2;
- }
- else if (data == 0x02)
- {
- m_last_id = 1;
- }
- else if (data == 0x01)
- {
- m_last_id = 0;
- }
- }
-
- // if this is a write, accumulate accordingly
- if (((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x00) && (m_5380_Registers[R5380_INICOMMAND] == 1))
- {
- m_5380_Data[m_d_ptr] = data;
-
- // if we've hit a sector, flush
- if (m_d_ptr == 511)
- {
- ncr5380_write_data(512, &m_5380_Data[0]);
-
- m_d_limit -= 512;
- m_d_ptr = 0;
-
- // no more data? set DMA END flag
- if (m_d_limit <= 0)
- {
- m_5380_Registers[R5380_BUSANDSTAT] = 0xc8;
- }
- }
- else
- {
- m_d_ptr++;
- }
-
- // make sure we don't upset the status readback
- data = 0;
- }
- break;
-
- case R5380_INICOMMAND:
- if (data == 0) // dropping the bus
- {
- // make sure it's not busy
- m_5380_Registers[R5380_BUSSTATUS] &= ~0x40;
-
- // are we in the command phase?
- if ((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x08)
- {
- // is the current command complete?
- if (get_cmd_len(m_5380_Command[0]) == m_cmd_ptr)
- {
- if (VERBOSE)
- logerror("%s NCR5380: Command (to ID %d): %x %x %x %x %x %x %x %x %x %x\n", machine().describe_context(), m_last_id, m_5380_Command[0], m_5380_Command[1], m_5380_Command[2], m_5380_Command[3], m_5380_Command[4], m_5380_Command[5], m_5380_Command[6], m_5380_Command[7], m_5380_Command[8], m_5380_Command[9]);
-
- m_scsi_devices[m_last_id]->SetCommand(&m_5380_Command[0], 16);
- m_scsi_devices[m_last_id]->ExecCommand();
- m_scsi_devices[m_last_id]->GetLength(&m_d_limit);
-
- if (VERBOSE)
- logerror("NCR5380: Command returned %d bytes\n", m_d_limit);
-
- m_d_ptr = 0;
-
- // is data available?
- if (m_d_limit > 0)
- {
- // make sure for transfers under 512 bytes that we always pad with a zero
- if (m_d_limit < 512)
- {
- m_5380_Data[m_d_limit] = 0;
- }
-
- // read back the amount available, or 512 bytes, whichever is smaller
- ncr5380_read_data((m_d_limit < 512) ? m_d_limit : 512, m_5380_Data);
-
- // raise REQ to indicate data is available
- m_5380_Registers[R5380_BUSSTATUS] |= 0x20;
- }
- }
- }
-
- }
-
- if (data == 5) // want the bus?
- {
- // if the device exists, make the bus busy.
- // otherwise don't.
-
- if (m_scsi_devices[m_last_id])
- {
- if (VERBOSE)
- logerror("NCR5380: Giving the bus for ID %d\n", m_last_id);
- m_5380_Registers[R5380_BUSSTATUS] |= 0x40;
- }
- else
- {
- if (VERBOSE)
- logerror("NCR5380: Rejecting the bus for ID %d\n", m_last_id);
- m_5380_Registers[R5380_BUSSTATUS] &= ~0x40;
- }
- }
-
- if (data == 1) // data bus (prelude to command?)
- {
- // raise REQ
- m_5380_Registers[R5380_BUSSTATUS] |= 0x20;
- }
-
- if (data & 0x10) // ACK drops REQ
- {
- // drop REQ
- m_5380_Registers[R5380_BUSSTATUS] &= ~0x20;
- }
- break;
-
- case R5380_MODE:
- if (data == 2) // DMA
- {
- // put us in DMA mode
- m_5380_Registers[R5380_BUSANDSTAT] |= 0x40;
- }
-
- if (data == 1) // arbitrate?
- {
- m_5380_Registers[R5380_INICOMMAND] |= 0x40; // set arbitration in progress
- m_5380_Registers[R5380_INICOMMAND] &= ~0x20; // clear "lost arbitration"
- }
-
- if (data == 0)
- {
- // drop DMA mode
- m_5380_Registers[R5380_BUSANDSTAT] &= ~0x40;
- }
- break;
-
- case R5380_TARGETCMD:
- // sync the bus phase with what was just written
- m_5380_Registers[R5380_BUSSTATUS] &= ~0x1c;
- m_5380_Registers[R5380_BUSSTATUS] |= (data & 7)<<2;
-
- // and set the "phase match" flag
- m_5380_Registers[R5380_BUSANDSTAT] |= 0x08;
-
- // and set /REQ
- m_5380_Registers[R5380_BUSSTATUS] |= 0x20;
-
- // if we're entering the command phase, start accumulating the data
- if ((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x08)
- {
- m_cmd_ptr = 0;
- }
- break;
-
- default:
- break;
- }
-
- m_5380_Registers[reg] = data;
-
- // note: busandstat overlaps startdma, so we need to do this here!
- if (reg == R5380_STARTDMA)
- {
- m_5380_Registers[R5380_BUSANDSTAT] = 0x48;
- }
-}
-
-
-void ncr5380_device::ncr5380_read_data(int bytes, UINT8 *pData)
-{
- if (m_scsi_devices[m_last_id])
- {
- if (VERBOSE)
- logerror("NCR5380: issuing read for %d bytes\n", bytes);
- m_scsi_devices[m_last_id]->ReadData(pData, bytes);
- }
- else
- {
- logerror("ncr5380: read unknown device SCSI ID %d\n", m_last_id);
- }
-}
-
-
-void ncr5380_device::ncr5380_write_data(int bytes, UINT8 *pData)
-{
- if (m_scsi_devices[m_last_id])
- {
- m_scsi_devices[m_last_id]->WriteData(pData, bytes);
- }
- else
- {
- logerror("ncr5380: write to unknown device SCSI ID %d\n", m_last_id);
- }
-}
diff --git a/src/mess/machine/ncr5380.h b/src/mess/machine/ncr5380.h
deleted file mode 100644
index 24f33f9334f..00000000000
--- a/src/mess/machine/ncr5380.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * ncr5380.h SCSI controller
- *
- */
-
-#ifndef _NCR5380_H_
-#define _NCR5380_H_
-
-#include "machine/scsihle.h"
-
-struct NCR5380interface
-{
- devcb_write_line m_irq_cb; /* irq callback */
-};
-
-// 5380 registers
-enum
-{
- R5380_CURDATA = 0, // current SCSI data (read only)
- R5380_OUTDATA = 0, // output data (write only)
- R5380_INICOMMAND, // initiator command
- R5380_MODE, // mode
- R5380_TARGETCMD, // target command
- R5380_SELENABLE, // select enable (write only)
- R5380_BUSSTATUS = R5380_SELENABLE, // bus status (read only)
- R5380_STARTDMA, // start DMA send (write only)
- R5380_BUSANDSTAT = R5380_STARTDMA, // bus and status (read only)
- R5380_DMATARGET, // DMA target (write only)
- R5380_INPUTDATA = R5380_DMATARGET, // input data (read only)
- R5380_DMAINIRECV, // DMA initiator receive (write only)
- R5380_RESETPARITY = R5380_DMAINIRECV // reset parity/interrupt (read only)
-};
-
-// special Mac Plus registers - they implemented it weird
-#define R5380_OUTDATA_DTACK (R5380_OUTDATA | 0x10)
-#define R5380_CURDATA_DTACK (R5380_CURDATA | 0x10)
-
-// device stuff
-#define MCFG_NCR5380_ADD(_tag, _clock, _intrf) \
- MCFG_DEVICE_ADD(_tag, NCR5380, _clock) \
- MCFG_DEVICE_CONFIG(_intrf)
-
-class ncr5380_device : public device_t,
- public NCR5380interface
-{
-public:
- // construction/destruction
- ncr5380_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- // our API
- UINT8 ncr5380_read_reg(UINT32 offset);
- void ncr5380_write_reg(UINT32 offset, UINT8 data);
-
- void ncr5380_read_data(int bytes, UINT8 *pData);
- void ncr5380_write_data(int bytes, UINT8 *pData);
-
-protected:
- // device-level overrides
- virtual void device_start();
- virtual void device_reset();
- virtual void device_stop();
- virtual void device_config_complete();
-
-private:
- scsihle_device *m_scsi_devices[8];
-
- UINT8 m_5380_Registers[8];
- UINT8 m_last_id;
- UINT8 m_5380_Command[32];
- INT32 m_cmd_ptr, m_d_ptr, m_d_limit, m_next_req_flag;
- UINT8 m_5380_Data[512];
- devcb_resolved_write_line m_irq_func;
-};
-
-// device type definition
-extern const device_type NCR5380;
-
-#endif
diff --git a/src/mess/machine/ncr5390.c b/src/mess/machine/ncr5390.c
deleted file mode 100644
index e0e611b9435..00000000000
--- a/src/mess/machine/ncr5390.c
+++ /dev/null
@@ -1,850 +0,0 @@
-
-#include "emu.h"
-#include "ncr5390.h"
-
-#define DELAY_HACK
-
-const device_type NCR5390 = &device_creator<ncr5390_device>;
-
-DEVICE_ADDRESS_MAP_START(map, 8, ncr5390_device)
- AM_RANGE(0x0, 0x0) AM_READWRITE(tcount_lo_r, tcount_lo_w)
- AM_RANGE(0x1, 0x1) AM_READWRITE(tcount_hi_r, tcount_hi_w)
- AM_RANGE(0x2, 0x2) AM_READWRITE(fifo_r, fifo_w)
- AM_RANGE(0x3, 0x3) AM_READWRITE(command_r, command_w)
- AM_RANGE(0x4, 0x4) AM_READWRITE(status_r, bus_id_w)
- AM_RANGE(0x5, 0x5) AM_READWRITE(istatus_r, timeout_w)
- AM_RANGE(0x6, 0x6) AM_READWRITE(seq_step_r, sync_period_w)
- AM_RANGE(0x7, 0x7) AM_READWRITE(fifo_flags_r, sync_offset_w)
- AM_RANGE(0x8, 0x8) AM_READWRITE(conf_r, conf_w)
- AM_RANGE(0x9, 0x9) AM_WRITE(clock_w)
-ADDRESS_MAP_END
-
-ncr5390_device::ncr5390_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : nscsi_device(mconfig, NCR5390, "5390 SCSI", tag, owner, clock, "ncr5390", __FILE__),
- m_irq_handler(*this),
- m_drq_handler(*this)
-{
-}
-
-void ncr5390_device::device_start()
-{
- save_item(NAME(command));
- save_item(NAME(config));
- save_item(NAME(status));
- save_item(NAME(istatus));
- save_item(NAME(fifo_pos));
- save_item(NAME(fifo));
- save_item(NAME(tcount));
- save_item(NAME(mode));
- save_item(NAME(command_pos));
- save_item(NAME(irq));
- save_item(NAME(drq));
- save_item(NAME(clock_conv));
-
- m_irq_handler.resolve_safe();
- m_drq_handler.resolve_safe();
-
- tcount = 0;
- config = 0;
- status = 0;
- bus_id = 0;
- select_timeout = 0;
- tm = timer_alloc(0);
-}
-
-void ncr5390_device::device_reset()
-{
- fifo_pos = 0;
- memset(fifo, 0, sizeof(fifo));
-
- clock_conv = 2;
- sync_period = 5;
- sync_offset = 0;
- seq = 0;
- config &= 7;
- status &= 0x90;
- istatus = 0;
- irq = false;
- m_irq_handler(irq);
- reset_soft();
-}
-
-void ncr5390_device::reset_soft()
-{
- state = IDLE;
- scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL);
- status &= 0xef;
- drq = false;
- m_drq_handler(drq);
- reset_disconnect();
-}
-
-void ncr5390_device::reset_disconnect()
-{
- command_pos = 0;
- command_length = 0;
- memset(command, 0, sizeof(command));
- mode = MODE_D;
-}
-
-void ncr5390_device::scsi_ctrl_changed()
-{
- UINT32 ctrl = scsi_bus->ctrl_r();
- if(ctrl & S_RST) {
- logerror("%s: scsi bus reset\n", tag());
- return;
- }
-
- step(false);
-}
-
-void ncr5390_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
-{
- step(true);
-}
-
-void ncr5390_device::step(bool timeout)
-{
- UINT32 ctrl = scsi_bus->ctrl_r();
- UINT32 data = scsi_bus->data_r();
- UINT8 c = command[0] & 0x7f;
-
- if(0)
- logerror("%s: state=%d.%d %s\n",
- tag(), state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT,
- timeout ? "timeout" : "change");
-
- if(mode == MODE_I && !(ctrl & S_BSY)) {
- state = IDLE;
- istatus |= I_DISCONNECT;
- reset_disconnect();
- check_irq();
- }
- switch(state & SUB_MASK ? state & SUB_MASK : state & STATE_MASK) {
- case IDLE:
- break;
-
- case ARB_COMPLETE << SUB_SHIFT: {
- if(!timeout)
- break;
-
- int win;
- for(win=7; win>=0 && !(data & (1<<win)); win--);
- if(win != scsi_id) {
- scsi_bus->data_w(scsi_refid, 0);
- scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
- fatalerror("need to wait for bus free\n");
- break;
- }
- state = (state & STATE_MASK) | (ARB_ASSERT_SEL << SUB_SHIFT);
- scsi_bus->ctrl_w(scsi_refid, S_SEL, S_SEL);
- delay(6);
- break;
- }
-
- case ARB_ASSERT_SEL << SUB_SHIFT:
- if(!timeout)
- break;
-
- scsi_bus->data_w(scsi_refid, (1<<scsi_id) | (1<<bus_id));
- state = (state & STATE_MASK) | (ARB_SET_DEST << SUB_SHIFT);
- delay_cycles(4);
- break;
-
- case ARB_SET_DEST << SUB_SHIFT:
- if(!timeout)
- break;
-
- state = (state & STATE_MASK) | (ARB_RELEASE_BUSY << SUB_SHIFT);
- scsi_bus->ctrl_w(scsi_refid, c == CD_SELECT_ATN || c == CD_SELECT_ATN_STOP ? S_ATN : 0, S_ATN|S_BSY);
- delay(2);
- break;
-
- case ARB_RELEASE_BUSY << SUB_SHIFT:
- if(!timeout)
- break;
-
- if(ctrl & S_BSY) {
- state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
- if(c == CD_RESELECT)
- scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
- delay_cycles(2);
- } else {
- state = (state & STATE_MASK) | (ARB_TIMEOUT_BUSY << SUB_SHIFT);
-#ifdef DELAY_HACK
- delay(1);
-#else
- delay(8192*select_timeout);
-#endif
- }
- break;
-
- case ARB_DESKEW_WAIT << SUB_SHIFT:
- if(!timeout)
- break;
-
- scsi_bus->data_w(scsi_refid, 0);
- scsi_bus->ctrl_w(scsi_refid, 0, S_SEL);
-
- if(c == CD_RESELECT) {
- logerror("%s: mode switch to Target\n", tag());
- mode = MODE_T;
- } else {
- logerror("%s: mode switch to Initiator\n", tag());
- mode = MODE_I;
- }
- state &= STATE_MASK;
- step(true);
- break;
-
- case ARB_TIMEOUT_BUSY << SUB_SHIFT:
- if(timeout) {
- scsi_bus->data_w(scsi_refid, 0);
- logerror("%s: select timeout\n", tag());
- state = (state & STATE_MASK) | (ARB_TIMEOUT_ABORT << SUB_SHIFT);
- delay(1000);
- } else if(ctrl & S_BSY) {
- state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
- if(c == CD_RESELECT)
- scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
- delay_cycles(2);
- }
- break;
-
- case ARB_TIMEOUT_ABORT << SUB_SHIFT:
- if(!timeout)
- break;
-
- if(ctrl & S_BSY) {
- state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
- if(c == CD_RESELECT)
- scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
- delay_cycles(2);
- } else {
- scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
- state = IDLE;
- istatus |= I_DISCONNECT;
- reset_disconnect();
- check_irq();
- }
- break;
-
- case SEND_WAIT_SETTLE << SUB_SHIFT:
- if(!timeout)
- break;
-
- state = (state & STATE_MASK) | (SEND_WAIT_REQ_0 << SUB_SHIFT);
- step(false);
- break;
-
- case SEND_WAIT_REQ_0 << SUB_SHIFT:
- if(ctrl & S_REQ)
- break;
- state = state & STATE_MASK;
- scsi_bus->data_w(scsi_refid, 0);
- scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
- step(false);
- break;
-
- case RECV_WAIT_REQ_1 << SUB_SHIFT:
- if(!(ctrl & S_REQ))
- break;
-
- state = (state & STATE_MASK) | (RECV_WAIT_SETTLE << SUB_SHIFT);
- delay_cycles(sync_period);
- break;
-
- case RECV_WAIT_SETTLE << SUB_SHIFT:
- if(!timeout)
- break;
-
- if((state & STATE_MASK) != INIT_XFR_RECV_PAD)
- fifo_push(scsi_bus->data_r());
- scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
- state = (state & STATE_MASK) | (RECV_WAIT_REQ_0 << SUB_SHIFT);
- step(false);
- break;
-
- case RECV_WAIT_REQ_0 << SUB_SHIFT:
- if(ctrl & S_REQ)
- break;
- state = state & STATE_MASK;
- step(false);
- break;
-
- case DISC_SEL_ARBITRATION:
- if(c == CD_SELECT) {
- state = DISC_SEL_WAIT_REQ;
- command_length = derive_msg_size(fifo[0]);
- } else
- state = DISC_SEL_ATN_WAIT_REQ;
-
- scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
- if(ctrl & S_REQ)
- step(false);
- break;
-
- case DISC_SEL_ATN_WAIT_REQ:
- if(!(ctrl & S_REQ))
- break;
- if((ctrl & S_PHASE_MASK) != S_PHASE_MSG_OUT) {
- function_complete();
- break;
- }
- if(c == CD_SELECT_ATN)
- scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
- state = DISC_SEL_ATN_SEND_BYTE;
- send_byte();
- break;
-
- case DISC_SEL_ATN_SEND_BYTE:
- if(c == CD_SELECT_ATN_STOP) {
- seq = 1;
- function_complete();
- } else {
- command_length = derive_msg_size(fifo[0]);
- state = DISC_SEL_WAIT_REQ;
- }
- break;
-
- case DISC_SEL_WAIT_REQ:
- if(!(ctrl & S_REQ))
- break;
- if((ctrl & S_PHASE_MASK) != S_PHASE_COMMAND) {
- if(!command_length)
- seq = 4;
- scsi_bus->ctrl_wait(scsi_refid, 0, S_REQ);
- function_bus_complete();
- break;
- }
- if(seq < 3)
- seq = 3;
- state = DISC_SEL_SEND_BYTE;
- send_byte();
- break;
-
- case DISC_SEL_SEND_BYTE:
- if(command_length) {
- command_length--;
- if(!command_length)
- seq = 4;
- }
-
- state = DISC_SEL_WAIT_REQ;
- break;
-
- case INIT_CPT_RECV_BYTE_ACK:
- state = INIT_CPT_RECV_WAIT_REQ;
- scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
- break;
-
- case INIT_CPT_RECV_WAIT_REQ:
- if(!(ctrl & S_REQ))
- break;
-
- if((ctrl & S_PHASE_MASK) != S_PHASE_MSG_IN) {
- command_pos = 0;
- bus_complete();
- } else {
- state = INIT_CPT_RECV_BYTE_NACK;
- recv_byte();
- }
- break;
-
- case INIT_CPT_RECV_BYTE_NACK:
- scsi_bus->ctrl_wait(scsi_refid, 0, S_REQ);
- function_complete();
- break;
-
- case INIT_MSG_WAIT_REQ:
- if((ctrl & (S_REQ|S_BSY)) == S_BSY)
- break;
- bus_complete();
- break;
-
- case INIT_XFR:
- switch(xfr_phase) {
- case S_PHASE_DATA_OUT:
- dma_set(DMA_OUT);
- if(tcount == 0 && fifo_pos == 1)
- scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
- state = INIT_XFR_SEND_BYTE;
- send_byte();
- break;
-
- case S_PHASE_DATA_IN:
- dma_set(DMA_IN);
- state = tcount == fifo_pos+1 ?
- INIT_XFR_RECV_BYTE_NACK : INIT_XFR_RECV_BYTE_ACK;
- recv_byte();
- break;
-
- default:
- logerror("%s: xfer on phase %d\n", tag(), scsi_bus->ctrl_r() & S_PHASE_MASK);
- function_complete();
- break;
- }
- break;
-
- case INIT_XFR_WAIT_REQ:
- if(!(ctrl & S_REQ))
- break;
-
- if((ctrl & S_PHASE_MASK) != xfr_phase) {
- command_pos = 0;
- bus_complete();
- } else {
- state = INIT_XFR;
- step(false);
- }
- break;
-
- case INIT_XFR_SEND_BYTE:
- if(tcount == 0 && fifo_pos == 0)
- bus_complete();
- else
- state = INIT_XFR_WAIT_REQ;
- break;
-
- case INIT_XFR_RECV_BYTE_ACK:
- state = INIT_XFR_WAIT_REQ;
- scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
- break;
-
- case INIT_XFR_RECV_BYTE_NACK:
- function_complete();
- break;
-
- case INIT_XFR_SEND_PAD_WAIT_REQ:
- if(!(ctrl & S_REQ))
- break;
-
- if((ctrl & S_PHASE_MASK) != xfr_phase) {
- command_pos = 0;
- bus_complete();
- } else {
- state = INIT_XFR_SEND_PAD;
- send_byte();
- }
- break;
-
- case INIT_XFR_SEND_PAD:
- tcount--;
- if(tcount) {
- state = INIT_XFR_SEND_PAD_WAIT_REQ;
- step(false);
- } else
- function_complete();
- break;
-
- case INIT_XFR_RECV_PAD_WAIT_REQ:
- if(!(ctrl & S_REQ))
- break;
-
- if((ctrl & S_PHASE_MASK) != xfr_phase) {
- command_pos = 0;
- bus_complete();
- } else {
- state = INIT_XFR_RECV_PAD;
- recv_byte();
- }
- break;
-
- case INIT_XFR_RECV_PAD:
- tcount--;
- if(tcount) {
- state = INIT_XFR_RECV_PAD_WAIT_REQ;
- scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
- step(false);
- } else
- function_complete();
- break;
-
- default:
- logerror("%s: step() unexpected state %d.%d\n",
- tag(),
- state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT);
- exit(0);
- }
-}
-
-void ncr5390_device::send_byte()
-{
- if(!fifo_pos)
- fatalerror("ncr5390_device::send_byte - !fifo_pos\n");
-
- state = (state & STATE_MASK) | (SEND_WAIT_SETTLE << SUB_SHIFT);
- if((state & STATE_MASK) != INIT_XFR_SEND_PAD &&
- ((state & STATE_MASK) != DISC_SEL_SEND_BYTE ||
- command_length))
- scsi_bus->data_w(scsi_refid, fifo_pop());
- else
- scsi_bus->data_w(scsi_refid, 0);
-
- scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
- scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
- delay_cycles(sync_period);
-}
-
-void ncr5390_device::recv_byte()
-{
- scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
- state = (state & STATE_MASK) | (RECV_WAIT_REQ_1 << SUB_SHIFT);
- step(false);
-}
-
-void ncr5390_device::function_bus_complete()
-{
- state = IDLE;
- istatus |= I_FUNCTION|I_BUS;
- dma_set(DMA_NONE);
- check_irq();
-}
-
-void ncr5390_device::function_complete()
-{
- state = IDLE;
- istatus |= I_FUNCTION;
- dma_set(DMA_NONE);
- check_irq();
-}
-
-void ncr5390_device::bus_complete()
-{
- state = IDLE;
- istatus |= I_BUS;
- dma_set(DMA_NONE);
- check_irq();
-}
-
-void ncr5390_device::delay(int cycles)
-{
- if(!clock_conv)
- return;
- cycles *= clock_conv;
- tm->adjust(clocks_to_attotime(cycles));
-}
-
-void ncr5390_device::delay_cycles(int cycles)
-{
- tm->adjust(clocks_to_attotime(cycles));
-}
-
-READ8_MEMBER(ncr5390_device::tcount_lo_r)
-{
- logerror("%s: tcount_lo_r %02x (%08x)\n", tag(), tcount & 0xff, space.device().safe_pc());
- return tcount;
-}
-
-WRITE8_MEMBER(ncr5390_device::tcount_lo_w)
-{
- tcount = (tcount & 0xff00) | data;
- status &= ~S_TC0;
- logerror("%s: tcount_lo_w %02x (%08x)\n", tag(), data, space.device().safe_pc());
-}
-
-READ8_MEMBER(ncr5390_device::tcount_hi_r)
-{
- logerror("%s: tcount_hi_r %02x (%08x)\n", tag(), tcount >> 8, space.device().safe_pc());
- return tcount >> 8;
-}
-
-WRITE8_MEMBER(ncr5390_device::tcount_hi_w)
-{
- tcount = (tcount & 0x00ff) | (data << 8);
- status &= ~S_TC0;
- logerror("%s: tcount_hi_w %02x (%08x)\n", tag(), data, space.device().safe_pc());
-}
-
-UINT8 ncr5390_device::fifo_pop()
-{
- UINT8 r = fifo[0];
- fifo_pos--;
- memmove(fifo, fifo+1, fifo_pos);
- if((!fifo_pos) && tcount && dma_dir == DMA_OUT)
- drq_set();
- return r;
-}
-
-void ncr5390_device::fifo_push(UINT8 val)
-{
- fifo[fifo_pos++] = val;
- if(!drq && dma_dir == DMA_IN)
- drq_set();
-}
-
-READ8_MEMBER(ncr5390_device::fifo_r)
-{
- UINT8 r;
- if(fifo_pos) {
- r = fifo[0];
- fifo_pos--;
- memmove(fifo, fifo+1, fifo_pos);
- } else
- r = 0;
- return r;
-}
-
-WRITE8_MEMBER(ncr5390_device::fifo_w)
-{
- if(fifo_pos != 16)
- fifo[fifo_pos++] = data;
-}
-
-READ8_MEMBER(ncr5390_device::command_r)
-{
- logerror("%s: command_r (%08x)\n", tag(), space.device().safe_pc());
- return command[0];
-}
-
-WRITE8_MEMBER(ncr5390_device::command_w)
-{
- // logerror("%s: command_w %02x (%08x)\n", tag(), data, space.device().safe_pc());
- if(command_pos == 2) {
- status |= S_GROSS_ERROR;
- check_irq();
- return;
- }
- command[command_pos++] = data;
- if(command_pos == 1)
- start_command();
-}
-
-void ncr5390_device::command_pop_and_chain()
-{
- if(command_pos) {
- command_pos--;
- if(command_pos) {
- command[0] = command[1];
- start_command();
- }
- }
-}
-
-void ncr5390_device::start_command()
-{
- UINT8 c = command[0] & 0x7f;
- if(!check_valid_command(c)) {
- logerror("%s: invalid command %02x\n", tag(), command[0]);
- istatus |= I_ILLEGAL;
- check_irq();
- return;
- }
-
- switch(c) {
- case CM_NOP:
- command_pop_and_chain();
- break;
-
- case CM_FLUSH_FIFO:
- fifo_pos = 0;
- command_pop_and_chain();
- break;
-
- case CM_RESET:
- device_reset();
- break;
-
- case CM_RESET_BUS:
- reset_soft();
- break;
-
- case CD_RESELECT:
- state = DISC_REC_ARBITRATION;
- arbitrate();
- break;
-
- case CD_SELECT:
- case CD_SELECT_ATN:
- case CD_SELECT_ATN_STOP:
- seq = 0;
- state = DISC_SEL_ARBITRATION;
- arbitrate();
- break;
-
- case CD_ENABLE_SEL:
- command_pop_and_chain();
- break;
-
- case CI_XFER:
- state = INIT_XFR;
- xfr_phase = scsi_bus->ctrl_r() & S_PHASE_MASK;
- step(false);
- break;
-
- case CI_COMPLETE:
- state = INIT_CPT_RECV_BYTE_ACK;
- recv_byte();
- break;
-
- case CI_MSG_ACCEPT:
- state = INIT_MSG_WAIT_REQ;
- scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
- step(false);
- break;
-
- case CI_PAD:
- xfr_phase = scsi_bus->ctrl_r() & S_PHASE_MASK;
- if(xfr_phase & S_INP)
- state = INIT_XFR_RECV_PAD_WAIT_REQ;
- else
- state = INIT_XFR_SEND_PAD_WAIT_REQ;
- scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
- step(false);
- break;
-
- default:
- logerror("%s: start unimplemented command %02x\n", tag(), c);
- exit(0);
- }
-}
-
-bool ncr5390_device::check_valid_command(UINT8 cmd)
-{
- int subcmd = cmd & 15;
- switch((cmd >> 4) & 7) {
- case 0: return subcmd <= 3;
- case 4: return mode == MODE_D && subcmd <= 5;
- case 2: return mode == MODE_T && subcmd <= 13 && subcmd != 6;
- case 1: return mode == MODE_I && (subcmd <= 2 || subcmd == 8 || subcmd == 10);
- }
- return false;
-}
-
-int ncr5390_device::derive_msg_size(UINT8 msg_id)
-{
- const static int sizes[8] = { 6, 10, 6, 6, 6, 12, 6, 10 };
- return sizes[msg_id >> 5];
-}
-
-void ncr5390_device::arbitrate()
-{
- state = (state & STATE_MASK) | (ARB_COMPLETE << SUB_SHIFT);
- scsi_bus->data_w(scsi_refid, 1 << scsi_id);
- scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
- delay(11);
-}
-
-void ncr5390_device::check_irq()
-{
- bool oldirq = irq;
- irq = istatus != 0;
- if(irq != oldirq)
- m_irq_handler(irq);
-
-}
-
-READ8_MEMBER(ncr5390_device::status_r)
-{
- UINT32 ctrl = scsi_bus->ctrl_r();
- UINT8 res = status | (ctrl & S_MSG ? 4 : 0) | (ctrl & S_CTL ? 2 : 0) | (ctrl & S_INP ? 1 : 0);
- logerror("%s: status_r %02x (%08x)\n", tag(), res, space.device().safe_pc());
- if(irq)
- status &= ~(S_GROSS_ERROR|S_PARITY|S_TCC);
- return res;
-}
-
-WRITE8_MEMBER(ncr5390_device::bus_id_w)
-{
- bus_id = data & 7;
- logerror("%s: bus_id=%d\n", tag(), bus_id);
-}
-
-READ8_MEMBER(ncr5390_device::istatus_r)
-{
- UINT8 res = istatus;
- istatus = 0;
- seq = 0;
- check_irq();
- if(res)
- command_pop_and_chain();
-
- logerror("%s: istatus_r %02x (%08x)\n", tag(), res, space.device().safe_pc());
- return res;
-}
-
-WRITE8_MEMBER(ncr5390_device::timeout_w)
-{
- select_timeout = data;
-}
-
-READ8_MEMBER(ncr5390_device::seq_step_r)
-{
- logerror("%s: seq_step_r %d (%08x)\n", tag(), seq, space.device().safe_pc());
- return seq;
-}
-
-WRITE8_MEMBER(ncr5390_device::sync_period_w)
-{
- sync_period = data & 0x1f;
-}
-
-READ8_MEMBER(ncr5390_device::fifo_flags_r)
-{
- return fifo_pos;
-}
-
-WRITE8_MEMBER(ncr5390_device::sync_offset_w)
-{
- sync_offset = data & 0x0f;
-}
-
-READ8_MEMBER(ncr5390_device::conf_r)
-{
- return config;
-}
-
-WRITE8_MEMBER(ncr5390_device::conf_w)
-{
- config = data;
- scsi_id = data & 7;
-}
-
-WRITE8_MEMBER(ncr5390_device::clock_w)
-{
- clock_conv = data & 0x07;
-}
-
-void ncr5390_device::dma_set(int dir)
-{
- dma_dir = dir;
- if(dma_dir == DMA_OUT && fifo_pos != 16 && tcount != 0)
- drq_set();
-}
-
-void ncr5390_device::dma_w(UINT8 val)
-{
- fifo_push(val);
- tcount--;
- if(fifo_pos == 16 || tcount == 0)
- drq_clear();
-}
-
-UINT8 ncr5390_device::dma_r()
-{
- UINT8 r = fifo_pop();
- if(!fifo_pos)
- drq_clear();
- tcount--;
- if(tcount == 0) {
- status |= S_TC0;
- step(false);
- }
- return r;
-}
-
-void ncr5390_device::drq_set()
-{
- if(!drq) {
- drq = true;
- m_drq_handler(drq);
- }
-}
-
-void ncr5390_device::drq_clear()
-{
- if(drq) {
- drq = false;
- m_drq_handler(drq);
- }
-}
diff --git a/src/mess/machine/ncr5390.h b/src/mess/machine/ncr5390.h
deleted file mode 100644
index 38b9283ccc7..00000000000
--- a/src/mess/machine/ncr5390.h
+++ /dev/null
@@ -1,230 +0,0 @@
-#ifndef NCR5390_H
-#define NCR5390_H
-
-#include "machine/nscsi_bus.h"
-
-#define MCFG_NCR5390_IRQ_HANDLER(_devcb) \
- devcb = &ncr5390_device::set_irq_handler(*device, DEVCB2_##_devcb);
-
-#define MCFG_NCR5390_DRQ_HANDLER(_devcb) \
- devcb = &ncr5390_device::set_drq_handler(*device, DEVCB2_##_devcb);
-
-class ncr5390_device : public nscsi_device
-{
-public:
- ncr5390_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- // static configuration helpers
- template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ncr5390_device &>(device).m_irq_handler.set_callback(object); }
- template<class _Object> static devcb2_base &set_drq_handler(device_t &device, _Object object) { return downcast<ncr5390_device &>(device).m_drq_handler.set_callback(object); }
-
- DECLARE_ADDRESS_MAP(map, 8);
-
- DECLARE_READ8_MEMBER(tcount_lo_r);
- DECLARE_WRITE8_MEMBER(tcount_lo_w);
- DECLARE_READ8_MEMBER(tcount_hi_r);
- DECLARE_WRITE8_MEMBER(tcount_hi_w);
- DECLARE_READ8_MEMBER(fifo_r);
- DECLARE_WRITE8_MEMBER(fifo_w);
- DECLARE_READ8_MEMBER(command_r);
- DECLARE_WRITE8_MEMBER(command_w);
- DECLARE_READ8_MEMBER(status_r);
- DECLARE_WRITE8_MEMBER(bus_id_w);
- DECLARE_READ8_MEMBER(istatus_r);
- DECLARE_WRITE8_MEMBER(timeout_w);
- DECLARE_READ8_MEMBER(seq_step_r);
- DECLARE_WRITE8_MEMBER(sync_period_w);
- DECLARE_READ8_MEMBER(fifo_flags_r);
- DECLARE_WRITE8_MEMBER(sync_offset_w);
- DECLARE_READ8_MEMBER(conf_r);
- DECLARE_WRITE8_MEMBER(conf_w);
- DECLARE_WRITE8_MEMBER(clock_w);
-
- virtual void scsi_ctrl_changed();
-
- UINT8 dma_r();
- void dma_w(UINT8 val);
-
-protected:
- virtual void device_start();
- virtual void device_reset();
- virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
-
-private:
- enum { MODE_D, MODE_T, MODE_I };
- enum { IDLE };
-
- enum {
- // Bus initiated sequences
- BUSINIT_SETTLE_DELAY = 1,
- BUSINIT_ASSERT_BUS_SEL,
- BUSINIT_MSG_OUT,
- BUSINIT_RECV_BYTE,
- BUSINIT_ASSERT_BUS_RESEL,
- BUSINIT_WAIT_REQ,
- BUSINIT_RECV_BYTE_NACK,
-
- // Bus SCSI Reset
- BUSRESET_WAIT_INT,
- BUSRESET_RESET_BOARD,
-
- // Disconnected state commands
- DISC_SEL_ARBITRATION,
- DISC_SEL_ATN_WAIT_REQ,
- DISC_SEL_ATN_SEND_BYTE,
- DISC_SEL_WAIT_REQ,
- DISC_SEL_SEND_BYTE,
- DISC_REC_ARBITRATION,
- DISC_REC_MSG_IN,
- DISC_REC_SEND_BYTE,
- DISC_RESET,
-
- // Command sequence
- CMDSEQ_CMD_PHASE,
- CMDSEQ_RECV_BYTE,
-
- // Target commands
- TARGET_SEND_BYTE,
- TARGET_CMD_RECV_BYTE,
- TARGET_MSG_RECV_BYTE,
- TARGET_MSG_RECV_PAD,
- TARGET_DISC_SEND_BYTE,
- TARGET_DISC_MSG_IN,
- TARGET_DISC_SEND_BYTE_2,
-
- // Initiator commands
- INIT_MSG_WAIT_REQ,
- INIT_XFR,
- INIT_XFR_SEND_BYTE,
- INIT_XFR_SEND_PAD_WAIT_REQ,
- INIT_XFR_SEND_PAD,
- INIT_XFR_RECV_PAD_WAIT_REQ,
- INIT_XFR_RECV_PAD,
- INIT_XFR_RECV_BYTE_ACK,
- INIT_XFR_RECV_BYTE_NACK,
- INIT_XFR_WAIT_REQ,
- INIT_CPT_RECV_BYTE_ACK,
- INIT_CPT_RECV_WAIT_REQ,
- INIT_CPT_RECV_BYTE_NACK,
- };
-
- enum {
- // Arbitration
- ARB_WAIT_BUS_FREE = 1,
- ARB_COMPLETE,
- ARB_ASSERT_SEL,
- ARB_SET_DEST,
- ARB_RELEASE_BUSY,
- ARB_TIMEOUT_BUSY,
- ARB_TIMEOUT_ABORT,
- ARB_DESKEW_WAIT,
-
- // Send/recieve byte
- SEND_WAIT_SETTLE,
- SEND_WAIT_REQ_0,
- RECV_WAIT_REQ_1,
- RECV_WAIT_SETTLE,
- RECV_WAIT_REQ_0,
- };
-
- enum {
- STATE_MASK = 0x00ff,
- SUB_SHIFT = 8,
- SUB_MASK = 0xff00,
- };
-
- enum { BUS_BUSY, BUS_FREE_WAIT, BUS_FREE };
-
- enum {
- S_GROSS_ERROR = 0x40,
- S_PARITY = 0x20,
- S_TC0 = 0x10,
- S_TCC = 0x08,
-
- I_SCSI_RESET = 0x80,
- I_ILLEGAL = 0x40,
- I_DISCONNECT = 0x20,
- I_BUS = 0x10,
- I_FUNCTION = 0x08,
- I_RESELECTED = 0x04,
- I_SELECT_ATN = 0x02,
- I_SELECTED = 0x01,
-
- CM_NOP = 0x00,
- CM_FLUSH_FIFO = 0x01,
- CM_RESET = 0x02,
- CM_RESET_BUS = 0x03,
- CD_RESELECT = 0x40,
- CD_SELECT = 0x41,
- CD_SELECT_ATN = 0x42,
- CD_SELECT_ATN_STOP = 0x43,
- CD_ENABLE_SEL = 0x44,
- CD_DISABLE_SEL = 0x45,
- CT_SEND_MSG = 0x20,
- CT_SEND_STATUS = 0x21,
- CT_SEND_DATA = 0x22,
- CT_DISCONNECT_SEQ = 0x23,
- CT_TERMINATE = 0x24,
- CT_COMPLETE = 0x25,
- CT_DISCONNECT = 0x27,
- CT_RECV_MSG = 0x28,
- CT_RECV_CMD = 0x29,
- CT_RECV_DATA = 0x2a,
- CT_RECV_CMD_SEQ = 0x2b,
- CI_XFER = 0x10,
- CI_COMPLETE = 0x11,
- CI_MSG_ACCEPT = 0x12,
- CI_PAD = 0x18,
- CI_SET_ATN = 0x1a,
- };
-
- enum { DMA_NONE, DMA_IN, DMA_OUT };
-
- emu_timer *tm;
-
- UINT8 command[2], config, status, istatus;
- UINT8 clock_conv, sync_offset, sync_period, bus_id, select_timeout, seq;
- UINT8 fifo[16];
- UINT16 tcount;
- int mode, fifo_pos, command_pos;
- int state, xfr_phase;
- int command_length;
-
- int dma_dir;
-
- bool irq, drq;
-
- void dma_set(int dir);
- void drq_set();
- void drq_clear();
-
- void start_command();
- void step(bool timeout);
- bool check_valid_command(UINT8 cmd);
- int derive_msg_size(UINT8 msg_id);
- void function_complete();
- void function_bus_complete();
- void bus_complete();
-
- void arbitrate();
- void command_pop_and_chain();
- void check_irq();
-
- void reset_soft();
- void reset_disconnect();
-
- UINT8 fifo_pop();
- void fifo_push(UINT8 val);
- void send_byte();
- void recv_byte();
-
- void delay(int cycles);
- void delay_cycles(int cycles);
-
- devcb2_write_line m_irq_handler;
- devcb2_write_line m_drq_handler;
-};
-
-extern const device_type NCR5390;
-
-#endif
diff --git a/src/mess/machine/s3c44b0.c b/src/mess/machine/s3c44b0.c
deleted file mode 100644
index 73744094c4d..00000000000
--- a/src/mess/machine/s3c44b0.c
+++ /dev/null
@@ -1,2065 +0,0 @@
-/*******************************************************************************
-
- Samsung S3C44B0
-
- (c) 2011 Tim Schuerewegen
-
-*******************************************************************************/
-
-#include "emu.h"
-#include "cpu/arm7/arm7.h"
-#include "cpu/arm7/arm7core.h"
-#include "machine/s3c44b0.h"
-#include "sound/dac.h"
-#include "coreutil.h"
-
-#define VERBOSE_LEVEL ( 0 )
-
-INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ...)
-{
- if (VERBOSE_LEVEL >= n_level)
- {
- va_list v;
- char buf[32768];
- va_start(v, s_fmt);
- vsprintf(buf, s_fmt, v);
- va_end(v);
- logerror("%s: %s", machine.describe_context(), buf);
- }
-}
-
-const device_type S3C44B0 = &device_creator<s3c44b0_device>;
-
-s3c44b0_device::s3c44b0_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, S3C44B0, "Samsung S3C44B0", tag, owner, clock, "s3c44b0", __FILE__)
-{
- memset(&m_irq, 0, sizeof(s3c44b0_irq_t));
- memset(m_zdma, 0, sizeof(s3c44b0_dma_t)*2);
- memset(m_bdma, 0, sizeof(s3c44b0_dma_t)*2);
- memset(&m_clkpow, 0, sizeof(s3c44b0_clkpow_t));
- memset(&m_lcd, 0, sizeof(s3c44b0_lcd_t));
- memset(m_uart, 0, sizeof(s3c44b0_uart_t)*2);
- memset(&m_sio, 0, sizeof(s3c44b0_sio_t));
- memset(&m_pwm, 0, sizeof(s3c44b0_pwm_t));
- memset(&m_wdt, 0, sizeof(s3c44b0_wdt_t));
- memset(&m_iic, 0, sizeof(s3c44b0_iic_t));
- memset(&m_iis, 0, sizeof(s3c44b0_iis_t));
- memset(&m_gpio, 0, sizeof(s3c44b0_gpio_t));
- memset(&m_adc, 0, sizeof(s3c44b0_adc_t));
- memset(&m_cpuwrap, 0, sizeof(s3c44b0_cpuwrap_t));
-}
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void s3c44b0_device::device_config_complete()
-{
- // inherit a copy of the static data
- const s3c44b0_interface *intf = reinterpret_cast<const s3c44b0_interface *>(static_config());
- if (intf != NULL)
- *static_cast<s3c44b0_interface *>(this) = *intf;
-
- // or initialize to defaults if none provided
- else
- {
- }
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void s3c44b0_device::device_start()
-{
- m_cpu = machine().device<cpu_device>("maincpu");
-
- m_port_r.resolve(gpio_itf.port_r, *this);
- m_port_w.resolve(gpio_itf.port_w, *this);
- m_scl_w.resolve(i2c_itf.scl_w, *this);
- m_sda_r.resolve(i2c_itf.sda_r, *this);
- m_sda_w.resolve(i2c_itf.sda_w, *this);
- m_adc_data_r.resolve(adc_itf.data_r, *this);
- m_i2s_data_w.resolve(i2s_itf.data_w, *this);
-
-
- for (int i = 0; i < 6; i++) m_pwm.timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::pwm_timer_exp),this));
- for (int i = 0; i < 2; i++) m_uart[i].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::uart_timer_exp),this));
- for (int i = 0; i < 2; i++) m_zdma[i].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::zdma_timer_exp),this));
- for (int i = 0; i < 2; i++) m_bdma[i].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::bdma_timer_exp),this));
-
- m_lcd.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::lcd_timer_exp),this));
- m_wdt.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::wdt_timer_exp),this));
- m_sio.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::sio_timer_exp),this));
- m_adc.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::adc_timer_exp),this));
- m_iic.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::iic_timer_exp),this));
- m_iis.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(s3c44b0_device::iis_timer_exp),this));
-
- video_start();
-
- save_item(NAME(m_irq.regs.intcon));
- save_item(NAME(m_irq.regs.intpnd));
- save_item(NAME(m_irq.regs.intmod));
- save_item(NAME(m_irq.regs.intmsk));
- save_item(NAME(m_irq.regs.i_pslv));
- save_item(NAME(m_irq.regs.i_pmst));
- save_item(NAME(m_irq.regs.i_cslv));
- save_item(NAME(m_irq.regs.i_cmst));
- save_item(NAME(m_irq.regs.i_ispr));
- save_item(NAME(m_irq.regs.i_ispc));
- save_item(NAME(m_irq.regs.reserved));
- save_item(NAME(m_irq.regs.f_ispr));
- save_item(NAME(m_irq.regs.f_ispc));
- save_item(NAME(m_irq.line_irq));
- save_item(NAME(m_irq.line_fiq));
-
- save_item(NAME(m_clkpow.regs.pllcon));
- save_item(NAME(m_clkpow.regs.clkcon));
- save_item(NAME(m_clkpow.regs.clkslow));
- save_item(NAME(m_clkpow.regs.locktime));
-
- // FIXME: how to save m_lcd.bitmap which gets allocated/freed during emulation?
- save_item(NAME(m_lcd.regs.lcdcon1));
- save_item(NAME(m_lcd.regs.lcdcon2));
- save_item(NAME(m_lcd.regs.lcdsaddr1));
- save_item(NAME(m_lcd.regs.lcdsaddr2));
- save_item(NAME(m_lcd.regs.lcdsaddr3));
- save_item(NAME(m_lcd.regs.redlut));
- save_item(NAME(m_lcd.regs.greenlut));
- save_item(NAME(m_lcd.regs.bluelut));
- save_item(NAME(m_lcd.regs.reserved));
- save_item(NAME(m_lcd.regs.lcdcon3));
- save_item(NAME(m_lcd.regs.dithmode));
- save_item(NAME(m_lcd.vramaddr_cur));
- save_item(NAME(m_lcd.vramaddr_max));
- save_item(NAME(m_lcd.offsize));
- save_item(NAME(m_lcd.pagewidth_cur));
- save_item(NAME(m_lcd.pagewidth_max));
- save_item(NAME(m_lcd.modesel));
- save_item(NAME(m_lcd.bswp));
- save_item(NAME(m_lcd.vpos));
- save_item(NAME(m_lcd.hpos));
- save_item(NAME(m_lcd.framerate));
- save_item(NAME(m_lcd.hpos_min));
- save_item(NAME(m_lcd.hpos_max));
- save_item(NAME(m_lcd.hpos_end));
- save_item(NAME(m_lcd.vpos_min));
- save_item(NAME(m_lcd.vpos_max));
- save_item(NAME(m_lcd.vpos_end));
- save_item(NAME(m_lcd.frame_time));
-
- machine().save().register_postload(save_prepost_delegate(FUNC(s3c44b0_device::s3c44b0_postload), this));
-
- for (int i = 0; i < 2; i++)
- {
- save_item(NAME(m_zdma[i].regs.dcon), i);
- save_item(NAME(m_zdma[i].regs.disrc), i);
- save_item(NAME(m_zdma[i].regs.didst), i);
- save_item(NAME(m_zdma[i].regs.dicnt), i);
- save_item(NAME(m_zdma[i].regs.dcsrc), i);
- save_item(NAME(m_zdma[i].regs.dcdst), i);
- save_item(NAME(m_zdma[i].regs.dccnt), i);
-
- save_item(NAME(m_bdma[i].regs.dcon), i);
- save_item(NAME(m_bdma[i].regs.disrc), i);
- save_item(NAME(m_bdma[i].regs.didst), i);
- save_item(NAME(m_bdma[i].regs.dicnt), i);
- save_item(NAME(m_bdma[i].regs.dcsrc), i);
- save_item(NAME(m_bdma[i].regs.dcdst), i);
- save_item(NAME(m_bdma[i].regs.dccnt), i);
-
- save_item(NAME(m_uart[i].regs.ulcon), i);
- save_item(NAME(m_uart[i].regs.ucon), i);
- save_item(NAME(m_uart[i].regs.ufcon), i);
- save_item(NAME(m_uart[i].regs.umcon), i);
- save_item(NAME(m_uart[i].regs.utrstat), i);
- save_item(NAME(m_uart[i].regs.uerstat), i);
- save_item(NAME(m_uart[i].regs.ufstat), i);
- save_item(NAME(m_uart[i].regs.umstat), i);
- save_item(NAME(m_uart[i].regs.utxh), i);
- save_item(NAME(m_uart[i].regs.urxh), i);
- save_item(NAME(m_uart[i].regs.ubrdiv), i);
- }
-
- save_item(NAME(m_sio.regs.siocon));
- save_item(NAME(m_sio.regs.siodat));
- save_item(NAME(m_sio.regs.sbrdr));
- save_item(NAME(m_sio.regs.itvcnt));
- save_item(NAME(m_sio.regs.dcntz));
-
- save_item(NAME(m_pwm.regs.tcfg0));
- save_item(NAME(m_pwm.regs.tcfg1));
- save_item(NAME(m_pwm.regs.tcon));
- save_item(NAME(m_pwm.regs.tcntb0));
- save_item(NAME(m_pwm.regs.tcmpb0));
- save_item(NAME(m_pwm.regs.tcnto0));
- save_item(NAME(m_pwm.regs.tcntb1));
- save_item(NAME(m_pwm.regs.tcmpb1));
- save_item(NAME(m_pwm.regs.tcnto1));
- save_item(NAME(m_pwm.regs.tcntb2));
- save_item(NAME(m_pwm.regs.tcmpb2));
- save_item(NAME(m_pwm.regs.tcnto2));
- save_item(NAME(m_pwm.regs.tcntb3));
- save_item(NAME(m_pwm.regs.tcmpb3));
- save_item(NAME(m_pwm.regs.tcnto3));
- save_item(NAME(m_pwm.regs.tcntb4));
- save_item(NAME(m_pwm.regs.tcmpb4));
- save_item(NAME(m_pwm.regs.tcnto4));
- save_item(NAME(m_pwm.regs.tcntb5));
- save_item(NAME(m_pwm.regs.tcnto5));
- save_item(NAME(m_pwm.cnt));
- save_item(NAME(m_pwm.cmp));
- save_item(NAME(m_pwm.freq));
-
- save_item(NAME(m_wdt.regs.wtcon));
- save_item(NAME(m_wdt.regs.wtdat));
- save_item(NAME(m_wdt.regs.wtcnt));
-
- save_item(NAME(m_iic.regs.iiccon));
- save_item(NAME(m_iic.regs.iicstat));
- save_item(NAME(m_iic.regs.iicadd));
- save_item(NAME(m_iic.regs.iicds));
- save_item(NAME(m_iic.count));
-
- save_item(NAME(m_iis.regs.iiscon));
- save_item(NAME(m_iis.regs.iismod));
- save_item(NAME(m_iis.regs.iispsr));
- save_item(NAME(m_iis.regs.iisfcon));
- save_item(NAME(m_iis.regs.iisfifo));
- save_item(NAME(m_iis.fifo));
- save_item(NAME(m_iis.fifo_index));
-
- save_item(NAME(m_gpio.regs.gpacon));
- save_item(NAME(m_gpio.regs.gpadat));
- save_item(NAME(m_gpio.regs.gpbcon));
- save_item(NAME(m_gpio.regs.gpbdat));
- save_item(NAME(m_gpio.regs.gpccon));
- save_item(NAME(m_gpio.regs.gpcdat));
- save_item(NAME(m_gpio.regs.gpcup));
- save_item(NAME(m_gpio.regs.gpdcon));
- save_item(NAME(m_gpio.regs.gpddat));
- save_item(NAME(m_gpio.regs.gpdup));
- save_item(NAME(m_gpio.regs.gpecon));
- save_item(NAME(m_gpio.regs.gpedat));
- save_item(NAME(m_gpio.regs.gpeup));
- save_item(NAME(m_gpio.regs.gpfcon));
- save_item(NAME(m_gpio.regs.gpfdat));
- save_item(NAME(m_gpio.regs.gpfup));
- save_item(NAME(m_gpio.regs.gpgcon));
- save_item(NAME(m_gpio.regs.gpgdat));
- save_item(NAME(m_gpio.regs.gpgup));
- save_item(NAME(m_gpio.regs.spucr));
- save_item(NAME(m_gpio.regs.extint));
- save_item(NAME(m_gpio.regs.extintpnd));
-
- save_item(NAME(m_adc.regs.adccon));
- save_item(NAME(m_adc.regs.adcpsr));
- save_item(NAME(m_adc.regs.adcdat));
-
- save_item(NAME(m_cpuwrap.regs.syscfg));
- save_item(NAME(m_cpuwrap.regs.ncachbe0));
- save_item(NAME(m_cpuwrap.regs.ncachbe1));
-}
-
-
-void s3c44b0_device::s3c44b0_postload()
-{
- m_lcd.frame_period = HZ_TO_ATTOSECONDS(m_lcd.framerate);
- m_lcd.scantime = m_lcd.frame_period / m_lcd.vpos_end;
- m_lcd.pixeltime = m_lcd.frame_period / (m_lcd.vpos_end * m_lcd.hpos_end);
-}
-
-//-------------------------------------------------
-// device_reset - device-specific reset
-//-------------------------------------------------
-
-void s3c44b0_device::device_reset()
-{
- m_iis.fifo_index = 0;
- // m_iic.data_index = 0;
-#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
- m_gpio.regs.gstatus2 = 0x00000001; // Boot is caused by power on reset
-#endif
- m_irq.line_irq = m_irq.line_fiq = CLEAR_LINE;
-}
-
-
-/*******************************************************************************
- MACROS & CONSTANTS
-*******************************************************************************/
-
-#define UART_PRINTF
-
-#define CLOCK_MULTIPLIER 1
-
-#define BIT(x,n) (((x)>>(n))&1)
-#define BITS(x,m,n) (((x)>>(n))&(((UINT32)1<<((m)-(n)+1))-1))
-#define CLR_BITS(x,m,n) ((x) & ~((((UINT32)1 << ((m) - (n) + 1)) - 1) << n))
-
-
-/***************************************************************************
- IMPLEMENTATION
-***************************************************************************/
-
-/* LCD Controller */
-
-rgb_t s3c44b0_device::lcd_get_color_stn_04(UINT8 data)
-{
- UINT8 r, g, b;
- r = g = b = BITS(data, 3, 0) << 4;
- return rgb_t(r, g, b);
-}
-
-UINT8 s3c44b0_device::lcd_get_color_stn_08_r(UINT8 data)
-{
- return ((m_lcd.regs.redlut >> (BITS(data, 7, 5) << 2)) & 0xf) << 4;
-}
-
-UINT8 s3c44b0_device::lcd_get_color_stn_08_g(UINT8 data)
-{
- return ((m_lcd.regs.greenlut >> (BITS(data, 4, 2) << 2)) & 0xf) << 4;
-}
-
-UINT8 s3c44b0_device::lcd_get_color_stn_08_b(UINT8 data)
-{
- return ((m_lcd.regs.bluelut >> (BITS(data, 1, 0) << 2)) & 0xf) << 4;
-}
-
-void s3c44b0_device::lcd_dma_reload()
-{
- int lcdbank, lcdbaseu, lcdbasel;
- lcdbank = BITS(m_lcd.regs.lcdsaddr1, 26, 21);
- lcdbaseu = BITS(m_lcd.regs.lcdsaddr1, 20, 0);
- lcdbasel = BITS(m_lcd.regs.lcdsaddr2, 20, 0);
-
- m_lcd.vramaddr_cur = (lcdbank << 22) | (lcdbaseu << 1);
- m_lcd.vramaddr_max = (lcdbank << 22) | (lcdbasel << 1);
- if (lcdbasel == 0) m_lcd.vramaddr_max += 1 << 22;
- m_lcd.offsize = BITS(m_lcd.regs.lcdsaddr3, 19, 9);
- m_lcd.pagewidth_cur = 0;
- m_lcd.pagewidth_max = BITS(m_lcd.regs.lcdsaddr3, 8, 0);
- m_lcd.bswp = BIT(m_lcd.regs.lcdsaddr2, 29); // note: juicebox changes bswp when video playback starts
-// verboselog(machine(), 3, "LCD - vramaddr %08X %08X offsize %08X pagewidth %08X\n", m_lcd.vramaddr_cur, m_lcd.vramaddr_max, m_lcd.offsize, m_lcd.pagewidth_max);
-}
-
-void s3c44b0_device::lcd_dma_init()
-{
- m_lcd.modesel = BITS(m_lcd.regs.lcdsaddr1, 28, 27);
-// verboselog(machine(), 3, "LCD - modesel %d bswp %d\n", m_lcd.modesel, m_lcd.bswp);
- lcd_dma_reload();
-}
-
-void s3c44b0_device::lcd_dma_read(int count, UINT8 *data)
-{
- address_space &space = m_cpu->space(AS_PROGRAM);
- UINT8 *vram = (UINT8 *)space.get_read_ptr(m_lcd.vramaddr_cur);
- for (int i = 0; i < count / 2; i++)
- {
- if (m_lcd.bswp == 0)
- {
- if ((m_lcd.vramaddr_cur & 2) == 0)
- {
- data[0] = *(vram + 3);
- data[1] = *(vram + 2);
- }
- else
- {
- data[0] = *(vram - 1);
- data[1] = *(vram - 2);
- }
- }
- else
- {
- data[0] = *(vram + 0);
- data[1] = *(vram + 1);
- }
- m_lcd.vramaddr_cur += 2;
- m_lcd.pagewidth_cur++;
- if (m_lcd.pagewidth_cur >= m_lcd.pagewidth_max)
- {
- m_lcd.vramaddr_cur += m_lcd.offsize << 1;
- if (m_lcd.vramaddr_cur >= m_lcd.vramaddr_max)
- {
- lcd_dma_reload();
- }
- m_lcd.pagewidth_cur = 0;
- vram = (UINT8 *)space.get_read_ptr(m_lcd.vramaddr_cur);
- }
- else
- {
- vram += 2;
- }
- data += 2;
- }
-}
-
-void s3c44b0_device::lcd_render_stn_04()
-{
- UINT8 *bitmap = m_lcd.bitmap + ((m_lcd.vpos - m_lcd.vpos_min) * (m_lcd.hpos_max - m_lcd.hpos_min + 1)) + (m_lcd.hpos - m_lcd.hpos_min);
- UINT8 data[16];
- lcd_dma_read(16, data);
- for (int i = 0; i < 16; i++)
- {
- for (int j = 0; j < 2; j++)
- {
- *bitmap++ = lcd_get_color_stn_04((data[i] >> 4) & 0x0F);
- data[i] = data[i] << 4;
- m_lcd.hpos++;
- if (m_lcd.hpos >= m_lcd.hpos_min + (m_lcd.pagewidth_max << 2))
- {
- m_lcd.vpos++;
- if (m_lcd.vpos > m_lcd.vpos_max)
- {
- m_lcd.vpos = m_lcd.vpos_min;
- bitmap = m_lcd.bitmap;
- }
- m_lcd.hpos = m_lcd.hpos_min;
- }
- }
- }
-}
-
-void s3c44b0_device::lcd_render_stn_08()
-{
- UINT8 *bitmap = m_lcd.bitmap + ((m_lcd.vpos - m_lcd.vpos_min) * (m_lcd.hpos_max - m_lcd.hpos_min + 1)) + (m_lcd.hpos - m_lcd.hpos_min);
- UINT8 data[16];
- lcd_dma_read(16, data);
- for (int i = 0; i < 16; i++)
- {
- UINT8 xxx[3];
- xxx[0] = lcd_get_color_stn_08_r(data[i]);
- xxx[1] = lcd_get_color_stn_08_g(data[i]);
- xxx[2] = lcd_get_color_stn_08_b(data[i]);
- for (int j = 0; j < 3; j++)
- {
- *bitmap++ = xxx[j];
- m_lcd.hpos++;
- if (m_lcd.hpos >= m_lcd.hpos_min + (m_lcd.pagewidth_max * 6))
- {
- m_lcd.vpos++;
- if (m_lcd.vpos > m_lcd.vpos_max)
- {
- m_lcd.vpos = m_lcd.vpos_min;
- bitmap = m_lcd.bitmap;
- }
- m_lcd.hpos = m_lcd.hpos_min;
- }
- }
- }
-}
-
-attotime s3c44b0_device::time_until_pos(int vpos, int hpos)
-{
- attoseconds_t time1, time2;
- attotime retval;
- verboselog(machine(), 3, "s3c44b0_time_until_pos - vpos %d hpos %d\n", vpos, hpos);
- time1 = (attoseconds_t)vpos * m_lcd.scantime + (attoseconds_t)hpos * m_lcd.pixeltime;
- time2 = (machine().time() - m_lcd.frame_time).as_attoseconds();
- verboselog(machine(), 3, "machine %f frametime %f time1 %f time2 %f\n", machine().time().as_double(), m_lcd.frame_time.as_double(), attotime(0, time1).as_double(), attotime(0, time2).as_double());
- while (time1 <= time2) time1 += m_lcd.frame_period;
- retval = attotime( 0, time1 - time2);
- verboselog(machine(), 3, "result %f\n", retval.as_double());
- return retval;
-}
-
-int s3c44b0_device::lcd_get_vpos()
-{
- attoseconds_t delta;
- int vpos;
- delta = (machine().time() - m_lcd.frame_time).as_attoseconds();
- delta = delta + (m_lcd.pixeltime / 2);
- vpos = delta / m_lcd.scantime;
- return (m_lcd.vpos_min + vpos) % m_lcd.vpos_end;
-}
-
-int s3c44b0_device::lcd_get_hpos()
-{
- attoseconds_t delta;
- int vpos;
- delta = (machine().time() - m_lcd.frame_time).as_attoseconds();
- delta = delta + (m_lcd.pixeltime / 2);
- vpos = delta / m_lcd.scantime;
- delta = delta - (vpos * m_lcd.scantime);
- return delta / m_lcd.pixeltime;
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::lcd_timer_exp )
-{
- int vpos = m_lcd.vpos;
- verboselog(machine(), 2, "LCD timer callback (%f)\n", machine().time().as_double());
- verboselog(machine(), 3, "LCD - (1) vramaddr %08X vpos %d hpos %d\n", m_lcd.vramaddr_cur, m_lcd.vpos, m_lcd.hpos);
- switch (m_lcd.modesel)
- {
- case S3C44B0_MODESEL_04 : lcd_render_stn_04(); break;
- case S3C44B0_MODESEL_08 : lcd_render_stn_08(); break;
- default : verboselog(machine(), 0, "s3c44b0_lcd_timer_exp: modesel %d not supported\n", m_lcd.modesel); break;
- }
- verboselog(machine(), 3, "LCD - (2) vramaddr %08X vpos %d hpos %d\n", m_lcd.vramaddr_cur, m_lcd.vpos, m_lcd.hpos);
- if (m_lcd.vpos < vpos)
- {
-// verboselog(machine(), 3, "LCD - (1) frame_time %f\n", attotime_to_double(m_lcd.frame_time));
- m_lcd.frame_time = machine().time() + time_until_pos(m_lcd.vpos_min, m_lcd.hpos_min);
-// verboselog(machine(), 3, "LCD - (2) frame_time %f\n", attotime_to_double(m_lcd.frame_time));
- }
- m_lcd.timer->adjust(time_until_pos(m_lcd.vpos, m_lcd.hpos), 0);
-}
-
-void s3c44b0_device::video_start()
-{
- // do nothing
-}
-
-UINT32 s3c44b0_device::video_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
-{
- if (m_lcd.regs.lcdcon1 & (1 << 0))
- {
- if (m_lcd.bitmap)
- {
- for (int y = 0; y < screen.height(); y++)
- {
- UINT32 *scanline = &bitmap.pix32(y);
- UINT8 *vram = m_lcd.bitmap + y * (m_lcd.hpos_max - m_lcd.hpos_min + 1);
- for (int x = 0; x < screen.width(); x++)
- {
- *scanline++ = rgb_t(vram[0], vram[1], vram[2]);
- vram += 3;
- }
- }
- }
- }
- else
- {
- for (int y = 0; y < screen.height(); y++)
- {
- UINT32 *scanline = &bitmap.pix32(y);
- memset(scanline, 0, screen.width() * 4);
- }
- }
- return 0;
-}
-
-READ32_MEMBER( s3c44b0_device::lcd_r )
-{
- UINT32 data = ((UINT32*)&m_lcd.regs)[offset];
- switch (offset)
- {
- case S3C44B0_LCDCON1 :
- {
- int vpos = 0;
- // make sure line counter is going
- if (m_lcd.regs.lcdcon1 & (1 << 0))
- {
- vpos = lcd_get_vpos();
- int hpos = lcd_get_hpos();
- if (hpos < m_lcd.hpos_min) vpos = vpos - 1;
- if ((vpos < m_lcd.vpos_min) || (vpos > m_lcd.vpos_max)) vpos = m_lcd.vpos_max;
- vpos = m_lcd.vpos_max - vpos;
- }
- data = (data & ~0xFFC00000) | (vpos << 22);
- }
- break;
- }
-// verboselog(machine(), 9, "(LCD) %08X -> %08X\n", S3C44B0_BASE_LCD + (offset << 2), data);
- return data;
-}
-
-void s3c44b0_device::lcd_configure()
-{
- screen_device *screen = machine().first_screen();
- int dismode, clkval, lineval, wdly, hozval, lineblank, wlh, mclk;
- double vclk, framerate;
- int width, height;
- verboselog(machine(), 5, "s3c44b0_lcd_configure\n");
- dismode = BITS(m_lcd.regs.lcdcon1, 6, 5);
- clkval = BITS(m_lcd.regs.lcdcon1, 21, 12);
- lineval = BITS(m_lcd.regs.lcdcon2, 9, 0);
- wdly = BITS(m_lcd.regs.lcdcon1, 9, 8);
- hozval = BITS(m_lcd.regs.lcdcon2, 20, 10);
- lineblank = BITS(m_lcd.regs.lcdcon2, 31, 21);
- wlh = BITS(m_lcd.regs.lcdcon1, 11, 10);
- mclk = get_mclk();
- verboselog(machine(), 3, "LCD - dismode %d clkval %d lineval %d wdly %d hozval %d lineblank %d wlh %d mclk %d\n", dismode, clkval, lineval, wdly, hozval, lineblank, wlh, mclk);
- vclk = (double)(mclk / (clkval * 2));
- verboselog(machine(), 3, "LCD - vclk %f\n", vclk);
- framerate = 1 / (((1 / vclk) * (hozval + 1) + (1 / mclk) * (wlh + wdly + lineblank)) * (lineval + 1));
- framerate = framerate / 3; // ???
- verboselog(machine(), 3, "LCD - framerate %f\n", framerate);
- switch (dismode)
- {
- case S3C44B0_PNRMODE_STN_04_SS : width = ((hozval + 1) * 4); break;
- case S3C44B0_PNRMODE_STN_04_DS : width = ((hozval + 1) * 4); break;
- case S3C44B0_PNRMODE_STN_08_SS : width = ((hozval + 1) * 8); break;
- default : fatalerror("invalid display mode (%d)\n", dismode); break;
- }
- height = lineval + 1;
- m_lcd.framerate = framerate;
- verboselog(machine(), 3, "video_screen_configure %d %d %f\n", width, height, m_lcd.framerate);
- screen->configure(screen->width(), screen->height(), screen->visible_area(), HZ_TO_ATTOSECONDS(m_lcd.framerate));
- m_lcd.hpos_min = 25;
- m_lcd.hpos_max = 25 + width - 1;
- m_lcd.hpos_end = 25 + width - 1 + 25;
- m_lcd.vpos_min = 25;
- m_lcd.vpos_max = 25 + height - 1;
- m_lcd.vpos_end = 25 + height - 1 + 25;
- verboselog(machine(), 3, "LCD - min_x %d min_y %d max_x %d max_y %d\n", m_lcd.hpos_min, m_lcd.vpos_min, m_lcd.hpos_max, m_lcd.vpos_max);
- if (m_lcd.bitmap)
- {
- auto_free(machine(), m_lcd.bitmap);
- }
- m_lcd.bitmap = auto_alloc_array(machine(), UINT8, (m_lcd.hpos_max - m_lcd.hpos_min + 1) * (m_lcd.vpos_max - m_lcd.vpos_min + 1) * 3);
- m_lcd.frame_period = HZ_TO_ATTOSECONDS(m_lcd.framerate);
- m_lcd.scantime = m_lcd.frame_period / m_lcd.vpos_end;
- m_lcd.pixeltime = m_lcd.frame_period / (m_lcd.vpos_end * m_lcd.hpos_end);
-// printf("frame_period %f\n", attotime( 0, m_lcd.frame_period).as_double());
-// printf("scantime %f\n", attotime( 0, m_lcd.scantime).as_double());
-// printf("pixeltime %f\n", attotime( 0, m_lcd.pixeltime).as_double());
-}
-
-
-void s3c44b0_device::lcd_start()
-{
- screen_device *screen = machine().first_screen();
- verboselog(machine(), 1, "LCD start\n");
- lcd_configure();
- lcd_dma_init();
- m_lcd.vpos = m_lcd.vpos_min;
- m_lcd.hpos = m_lcd.hpos_min;
- m_lcd.frame_time = screen->time_until_pos( 0, 0);
- m_lcd.timer->adjust(m_lcd.frame_time, 0);
- m_lcd.frame_time = machine().time() + m_lcd.frame_time;
-}
-
-void s3c44b0_device::lcd_stop()
-{
- verboselog(machine(), 1, "LCD stop\n");
- m_lcd.timer->adjust(attotime::never, 0);
-}
-
-void s3c44b0_device::lcd_recalc()
-{
- if (m_lcd.regs.lcdcon1 & (1 << 0))
- lcd_start();
- else
- lcd_stop();
-}
-
-WRITE32_MEMBER( s3c44b0_device::lcd_w )
-{
- UINT32 old_value = ((UINT32*)&m_lcd.regs)[offset];
-// verboselog(machine(), 9, "(LCD) %08X <- %08X\n", S3C44B0_BASE_LCD + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_lcd.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_LCDCON1 :
- {
- if ((old_value & (1 << 0)) != (data & (1 << 0)))
- {
- lcd_recalc();
- }
- }
- break;
- }
-}
-
-
-/* Clock & Power Management */
-
-UINT32 s3c44b0_device::get_mclk()
-{
- UINT32 data, mdiv, pdiv, sdiv;
- data = m_clkpow.regs.pllcon;
- mdiv = BITS(data, 19, 12);
- pdiv = BITS(data, 9, 4);
- sdiv = BITS(data, 1, 0);
- return (UINT32)((double)((mdiv + 8) * clock()) / (double)((pdiv + 2) * (1 << sdiv)));
-}
-
-READ32_MEMBER( s3c44b0_device::clkpow_r )
-{
- UINT32 data = ((UINT32*)&m_clkpow.regs)[offset];
- verboselog(machine(), 9, "(CLKPOW) %08X -> %08X\n", S3C44B0_BASE_CLKPOW + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::clkpow_w )
-{
- verboselog(machine(), 9, "(CLKPOW) %08X <- %08X\n", S3C44B0_BASE_CLKPOW + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_clkpow.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_PLLCON :
- {
- verboselog(machine(), 5, "CLKPOW - mclk %d\n", get_mclk());
- m_cpu->set_unscaled_clock(get_mclk() * CLOCK_MULTIPLIER);
- }
- break;
- case S3C44B0_CLKCON :
- {
- if (data & (1 << 2))
- {
- m_cpu->spin_until_interrupt();
- }
- }
- break;
- }
-}
-
-/* Interrupt Controller */
-
-void s3c44b0_device::check_pending_irq()
-{
- // normal irq
- UINT32 temp = (m_irq.regs.intpnd & ~m_irq.regs.intmsk) & ~m_irq.regs.intmod;
-
- if (temp != 0)
- {
- UINT32 int_type = 0;
- while ((temp & 1) == 0)
- {
- int_type++;
- temp = temp >> 1;
- }
- m_irq.regs.i_ispr |= (1 << int_type);
- if (m_irq.line_irq != ASSERT_LINE)
- {
- m_cpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
- m_irq.line_irq = ASSERT_LINE;
- }
- }
- else
- {
- if (m_irq.line_irq != CLEAR_LINE)
- {
- m_cpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
- m_irq.line_irq = CLEAR_LINE;
- }
- }
- // fast irq
- temp = (m_irq.regs.intpnd & ~m_irq.regs.intmsk) & m_irq.regs.intmod;
- if (temp != 0)
- {
- UINT32 int_type = 0;
- while ((temp & 1) == 0)
- {
- int_type++;
- temp = temp >> 1;
- }
- if (m_irq.line_fiq != ASSERT_LINE)
- {
- m_cpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
- m_irq.line_fiq = ASSERT_LINE;
- }
- }
- else
- {
- if (m_irq.line_fiq != CLEAR_LINE)
- {
- m_cpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
- m_irq.line_fiq = CLEAR_LINE;
- }
- }
-}
-
-void s3c44b0_device::request_irq(UINT32 int_type)
-{
- verboselog(machine(), 5, "request irq %d\n", int_type);
- m_irq.regs.intpnd |= (1 << int_type);
- check_pending_irq();
-}
-
-void s3c44b0_device::check_pending_eint()
-{
- UINT32 temp = m_gpio.regs.extintpnd;
- if (temp != 0)
- {
- UINT32 int_type = 0;
- while ((temp & 1) == 0)
- {
- int_type++;
- temp = temp >> 1;
- }
- request_irq(S3C44B0_INT_EINT4_7);
- }
-}
-
-void s3c44b0_device::request_eint(UINT32 number)
-{
- verboselog(machine(), 5, "request external interrupt %d\n", number);
- if (number < 4)
- {
- request_irq(S3C44B0_INT_EINT0 + number);
- }
- else
- {
- m_gpio.regs.extintpnd |= (1 << (number - 4));
- check_pending_eint();
- }
-}
-
-READ32_MEMBER( s3c44b0_device::irq_r )
-{
- UINT32 data = ((UINT32*)&m_irq.regs)[offset];
- verboselog(machine(), 9, "(IRQ) %08X -> %08X\n", S3C44B0_BASE_INT + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::irq_w )
-{
- verboselog(machine(), 9, "(IRQ) %08X <- %08X\n", S3C44B0_BASE_INT + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_irq.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_INTMSK :
- {
- check_pending_irq();
- }
- break;
- case S3C44B0_I_ISPC :
- {
- m_irq.regs.intpnd = (m_irq.regs.intpnd & ~data); // The bit of INTPND bit is cleared to zero by writing '1' on I_ISPC/F_ISPC
- m_irq.regs.i_ispr = (m_irq.regs.i_ispr & ~data); // The pending bit in I_ISPR register should be cleared by writing I_ISPC register.
- check_pending_irq();
- }
- break;
- case S3C44B0_F_ISPC :
- {
- m_irq.regs.intpnd = (m_irq.regs.intpnd & ~data); // The bit of INTPND bit is cleared to zero by writing '1' on I_ISPC/F_ISPC
- check_pending_irq();
- }
- break;
- }
-}
-
-/* PWM Timer */
-
-UINT16 s3c44b0_device::pwm_calc_observation(int ch)
-{
- double timeleft, x1, x2;
- UINT32 cnto;
- timeleft = (m_pwm.timer[ch]->remaining()).as_double();
-// printf( "timeleft %f freq %d cntb %d cmpb %d\n", timeleft, m_pwm.freq[ch], m_pwm.cnt[ch], m_pwm.cmp[ch]);
- x1 = 1 / ((double)m_pwm.freq[ch] / (m_pwm.cnt[ch]- m_pwm.cmp[ch] + 1));
- x2 = x1 / timeleft;
-// printf( "x1 %f\n", x1);
- cnto = m_pwm.cmp[ch] + ((m_pwm.cnt[ch]- m_pwm.cmp[ch]) / x2);
-// printf( "cnto %d\n", cnto);
- return cnto;
-}
-
-READ32_MEMBER( s3c44b0_device::pwm_r )
-{
- UINT32 data = ((UINT32*)&m_pwm.regs)[offset];
- switch (offset)
- {
- case S3C44B0_TCNTO0 :
- {
- data = (data & ~0x0000FFFF) | pwm_calc_observation(0);
- }
- break;
- case S3C44B0_TCNTO1 :
- {
- data = (data & ~0x0000FFFF) | pwm_calc_observation(1);
- }
- break;
- case S3C44B0_TCNTO2 :
- {
- data = (data & ~0x0000FFFF) | pwm_calc_observation(2);
- }
- break;
- case S3C44B0_TCNTO3 :
- {
- data = (data & ~0x0000FFFF) | pwm_calc_observation(3);
- }
- break;
- case S3C44B0_TCNTO4 :
- {
- data = (data & ~0x0000FFFF) | pwm_calc_observation(4);
- }
- break;
- case S3C44B0_TCNTO5 :
- {
- data = (data & ~0x0000FFFF) | pwm_calc_observation(5);
- }
- break;
- }
- verboselog(machine(), 9, "(PWM) %08X -> %08X\n", S3C44B0_BASE_PWM + (offset << 2), data);
- return data;
-}
-
-void s3c44b0_device::pwm_start(int timer)
-{
- const int mux_table[] = { 2, 4, 8, 16};
- const int prescaler_shift[] = { 0, 0, 8, 8, 16, 16};
- const int mux_shift[] = { 0, 4, 8, 12, 16, 20};
- UINT32 mclk, prescaler, mux, cnt, cmp, auto_reload;
- double freq, hz;
- verboselog(machine(), 1, "PWM %d start\n", timer);
- mclk = get_mclk();
- prescaler = (m_pwm.regs.tcfg0 >> prescaler_shift[timer]) & 0xFF;
- mux = (m_pwm.regs.tcfg1 >> mux_shift[timer]) & 0x0F;
- if (mux < 4)
- {
- freq = (double)mclk / (prescaler + 1) / mux_table[mux];
- }
- else
- {
- // todo
- freq = (double)mclk / (prescaler + 1) / 1;
- }
- switch (timer)
- {
- case 0 :
- {
- cnt = BITS(m_pwm.regs.tcntb0, 15, 0);
- cmp = BITS(m_pwm.regs.tcmpb0, 15, 0);
- auto_reload = BIT(m_pwm.regs.tcon, 3);
- }
- break;
- case 1 :
- {
- cnt = BITS(m_pwm.regs.tcntb1, 15, 0);
- cmp = BITS(m_pwm.regs.tcmpb1, 15, 0);
- auto_reload = BIT(m_pwm.regs.tcon, 11);
- }
- break;
- case 2 :
- {
- cnt = BITS(m_pwm.regs.tcntb2, 15, 0);
- cmp = BITS(m_pwm.regs.tcmpb2, 15, 0);
- auto_reload = BIT(m_pwm.regs.tcon, 15);
- }
- break;
- case 3 :
- {
- cnt = BITS(m_pwm.regs.tcntb3, 15, 0);
- cmp = BITS(m_pwm.regs.tcmpb3, 15, 0);
- auto_reload = BIT(m_pwm.regs.tcon, 19);
- }
- break;
- case 4 :
- {
- cnt = BITS(m_pwm.regs.tcntb4, 15, 0);
- cmp = BITS(m_pwm.regs.tcmpb4, 15, 0);
- auto_reload = BIT(m_pwm.regs.tcon, 23);
- }
- break;
- case 5 :
- {
- cnt = BITS(m_pwm.regs.tcntb5, 15, 0);
- cmp = 0;
- auto_reload = BIT(m_pwm.regs.tcon, 26);
- }
- break;
- default :
- {
- cnt = cmp = auto_reload = 0;
- }
- break;
- }
-// hz = freq / (cnt - cmp + 1);
- if (cnt < 2)
- {
- hz = freq;
- }
- else
- {
- hz = freq / cnt;
- }
- verboselog(machine(), 5, "PWM %d - mclk=%d prescaler=%d div=%d freq=%f cnt=%d cmp=%d auto_reload=%d hz=%f\n", timer, mclk, prescaler, mux_table[mux], freq, cnt, cmp, auto_reload, hz);
- m_pwm.cnt[timer] = cnt;
- m_pwm.cmp[timer] = cmp;
- m_pwm.freq[timer] = freq;
- if (cnt == 0)
- {
- m_pwm.timer[timer]->adjust(attotime::never, 0);
- }
- else
- {
- if (auto_reload)
- {
- m_pwm.timer[timer]->adjust(attotime::from_hz(hz), timer, attotime::from_hz(hz));
- }
- else
- {
- m_pwm.timer[timer]->adjust(attotime::from_hz(hz), timer);
- }
- }
-}
-
-void s3c44b0_device::pwm_stop(int timer)
-{
- verboselog(machine(), 1, "PWM %d stop\n", timer);
- m_pwm.timer[timer]->adjust(attotime::never, 0);
-}
-
-void s3c44b0_device::pwm_recalc(int timer)
-{
- const int tcon_shift[] = { 0, 8, 12, 16, 20, 24};
- if (m_pwm.regs.tcon & (1 << tcon_shift[timer]))
- pwm_start(timer);
- else
- pwm_stop(timer);
-}
-
-WRITE32_MEMBER( s3c44b0_device::pwm_w )
-{
- UINT32 old_value = ((UINT32*)&m_pwm.regs)[offset];
- verboselog(machine(), 9, "(PWM) %08X <- %08X\n", S3C44B0_BASE_PWM + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_pwm.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_TCON :
- {
- if ((data & (1 << 0)) != (old_value & (1 << 0)))
- {
- pwm_recalc(0);
- }
- if ((data & (1 << 8)) != (old_value & (1 << 8)))
- {
- pwm_recalc(1);
- }
- if ((data & (1 << 12)) != (old_value & (1 << 12)))
- {
- pwm_recalc(2);
- }
- if ((data & (1 << 16)) != (old_value & (1 << 16)))
- {
- pwm_recalc(3);
- }
- if ((data & (1 << 20)) != (old_value & (1 << 20)))
- {
- pwm_recalc(4);
- }
- if ((data & (1 << 24)) != (old_value & (1 << 24)))
- {
- pwm_recalc(5);
- }
- }
- break;
- }
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::pwm_timer_exp )
-{
- int ch = param;
- const int ch_int[] = { S3C44B0_INT_TIMER0, S3C44B0_INT_TIMER1, S3C44B0_INT_TIMER2, S3C44B0_INT_TIMER3, S3C44B0_INT_TIMER4, S3C44B0_INT_TIMER5 };
- verboselog(machine(), 2, "PWM %d timer callback\n", ch);
- if (BITS(m_pwm.regs.tcfg1, 27, 24) == (ch + 1))
- {
- fatalerror("s3c44b0_dma_request_pwm( device)\n");
- }
- else
- {
- request_irq(ch_int[ch]);
- }
-}
-
-/* IIC */
-
-inline void s3c44b0_device::iface_i2c_scl_w(int state)
-{
- if (!m_scl_w.isnull())
- (m_scl_w)( state);
-}
-
-inline void s3c44b0_device::iface_i2c_sda_w(int state)
-{
- if (!m_sda_w.isnull())
- (m_sda_w)( state);
-}
-
-inline int s3c44b0_device::iface_i2c_sda_r()
-{
- if (!m_sda_r.isnull())
- return (m_sda_r)();
- else
- return 0;
-}
-
-void s3c44b0_device::i2c_send_start()
-{
- verboselog(machine(), 5, "i2c_send_start\n");
- iface_i2c_sda_w(1);
- iface_i2c_scl_w(1);
- iface_i2c_sda_w(0);
- iface_i2c_scl_w(0);
-}
-
-void s3c44b0_device::i2c_send_stop()
-{
- verboselog(machine(), 5, "i2c_send_stop\n");
- iface_i2c_sda_w(0);
- iface_i2c_scl_w(1);
- iface_i2c_sda_w(1);
- iface_i2c_scl_w(0);
-}
-
-UINT8 s3c44b0_device::i2c_receive_byte(int ack)
-{
- UINT8 data = 0;
- verboselog(machine(), 5, "i2c_receive_byte ...\n");
- iface_i2c_sda_w(1);
- for (int i = 0; i < 8; i++)
- {
- iface_i2c_scl_w(1);
- data = (data << 1) + (iface_i2c_sda_r() ? 1 : 0);
- iface_i2c_scl_w(0);
- }
- verboselog(machine(), 5, "recv data %02X\n", data);
- verboselog(machine(), 5, "send ack %d\n", ack);
- iface_i2c_sda_w(ack ? 0 : 1);
- iface_i2c_scl_w(1);
- iface_i2c_scl_w(0);
- return data;
-}
-
-int s3c44b0_device::i2c_send_byte(UINT8 data)
-{
- int ack;
- verboselog(machine(), 5, "i2c_send_byte ...\n");
- verboselog(machine(), 5, "send data %02X\n", data);
- for (int i = 0; i < 8; i++)
- {
- iface_i2c_sda_w((data & 0x80) ? 1 : 0);
- data = data << 1;
- iface_i2c_scl_w(1);
- iface_i2c_scl_w(0);
- }
- iface_i2c_sda_w(1); // ack bit
- iface_i2c_scl_w(1);
- ack = iface_i2c_sda_r();
- verboselog(machine(), 5, "recv ack %d\n", ack);
- iface_i2c_scl_w(0);
- return ack;
-}
-
-void s3c44b0_device::iic_start()
-{
- int mode_selection;
- verboselog(machine(), 1, "IIC start\n");
- i2c_send_start();
- mode_selection = BITS(m_iic.regs.iicstat, 7, 6);
- switch (mode_selection)
- {
- case 2 : i2c_send_byte(m_iic.regs.iicds | 0x01); break;
- case 3 : i2c_send_byte(m_iic.regs.iicds & 0xFE); break;
- }
- m_iic.timer->adjust(attotime::from_usec( 1), 0);
-}
-
-void s3c44b0_device::iic_stop()
-{
- verboselog(machine(), 1, "IIC stop\n");
- i2c_send_stop();
- m_iic.timer->adjust(attotime::never, 0);
-}
-
-void s3c44b0_device::iic_resume()
-{
- int mode_selection;
- verboselog(machine(), 1, "IIC resume\n");
- mode_selection = BITS(m_iic.regs.iicstat, 7, 6);
- switch (mode_selection)
- {
- case 2 : m_iic.regs.iicds = i2c_receive_byte(BIT(m_iic.regs.iiccon, 7)); break;
- case 3 : i2c_send_byte(m_iic.regs.iicds & 0xFF); break;
- }
- m_iic.timer->adjust(attotime::from_usec( 1), 0);
-}
-
-READ32_MEMBER( s3c44b0_device::iic_r )
-{
- UINT32 data = ((UINT32*)&m_iic.regs)[offset];
- switch (offset)
- {
- case S3C44B0_IICSTAT :
- {
- data = data & ~0x0000000F;
- }
- break;
- }
- verboselog(machine(), 9, "(IIC) %08X -> %08X\n", S3C44B0_BASE_IIC + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::iic_w )
-{
- UINT32 old_value = ((UINT32*)&m_iic.regs)[offset];
- verboselog(machine(), 9, "(IIC) %08X <- %08X\n", S3C44B0_BASE_IIC + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_iic.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_IICCON :
- {
- int interrupt_pending_flag;
-#if 0
- const int div_table[] = { 16, 512};
- int enable_interrupt, transmit_clock_value, tx_clock_source_selection
- double clock;
- transmit_clock_value = (data >> 0) & 0xF;
- tx_clock_source_selection = (data >> 6) & 1;
- enable_interrupt = (data >> 5) & 1;
- clock = (double)get_pclk() / div_table[tx_clock_source_selection] / (transmit_clock_value + 1);
-#endif
- interrupt_pending_flag = BIT(old_value, 4);
- if (interrupt_pending_flag != 0)
- {
- interrupt_pending_flag = BIT(data, 4);
- if (interrupt_pending_flag == 0)
- {
- int start_stop_condition;
- start_stop_condition = BIT(m_iic.regs.iicstat, 5);
- if (start_stop_condition != 0)
- {
- if (m_iic.count == 0)
- {
- iic_start();
-
- }
- else
- {
- iic_resume();
- }
- }
- else
- {
- iic_stop();
- }
- }
- }
- }
- break;
- case S3C44B0_IICSTAT :
- {
- int interrupt_pending_flag;
- m_iic.count = 0;
- interrupt_pending_flag = BIT(m_iic.regs.iiccon, 4);
- if (interrupt_pending_flag == 0)
- {
- int start_stop_condition;
- start_stop_condition = BIT(data, 5);
- if (start_stop_condition != 0)
- {
- if (m_iic.count == 0)
- {
- iic_start();
-
- }
- else
- {
- iic_resume();
- }
- }
- else
- {
- iic_stop();
- }
- }
- }
- break;
- }
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::iic_timer_exp )
-{
- int enable_interrupt;
- verboselog(machine(), 2, "IIC timer callback\n");
- m_iic.count++;
- enable_interrupt = BIT(m_iic.regs.iiccon, 5);
-
- m_iic.regs.iicds = 0xFF; // TEST
-
- if (enable_interrupt)
- {
- m_iic.regs.iiccon |= (1 << 4); // [bit 4] interrupt is pending
- request_irq(S3C44B0_INT_IIC);
- }
-}
-
-/* I/O Port */
-
-inline UINT32 s3c44b0_device::iface_gpio_port_r(int port)
-{
- if (!m_port_r.isnull())
- return (m_port_r)(port);
- else
- return 0;
-}
-
-inline void s3c44b0_device::iface_gpio_port_w(int port, UINT32 data)
-{
- if (!m_port_w.isnull())
- (m_port_w)(port, data);
-}
-
-READ32_MEMBER( s3c44b0_device::gpio_r )
-{
- UINT32 data = ((UINT32*)&m_gpio.regs)[offset];
- switch (offset)
- {
- case S3C44B0_GPADAT :
- {
- data = iface_gpio_port_r(S3C44B0_GPIO_PORT_A) & S3C44B0_GPADAT_MASK;
- }
- break;
- case S3C44B0_GPBDAT :
- {
- data = iface_gpio_port_r(S3C44B0_GPIO_PORT_B) & S3C44B0_GPBDAT_MASK;
- }
- break;
- case S3C44B0_GPCDAT :
- {
- data = iface_gpio_port_r(S3C44B0_GPIO_PORT_C) & S3C44B0_GPCDAT_MASK;
- }
- break;
- case S3C44B0_GPDDAT :
- {
- data = iface_gpio_port_r(S3C44B0_GPIO_PORT_D) & S3C44B0_GPDDAT_MASK;
- }
- break;
- case S3C44B0_GPEDAT :
- {
- data = iface_gpio_port_r(S3C44B0_GPIO_PORT_E) & S3C44B0_GPEDAT_MASK;
- }
- break;
- case S3C44B0_GPFDAT :
- {
- data = iface_gpio_port_r(S3C44B0_GPIO_PORT_F) & S3C44B0_GPFDAT_MASK;
- }
- break;
- case S3C44B0_GPGDAT :
- {
- data = iface_gpio_port_r(S3C44B0_GPIO_PORT_G) & S3C44B0_GPGDAT_MASK;
- }
- break;
- }
- verboselog(machine(), 9, "(GPIO) %08X -> %08X\n", S3C44B0_BASE_GPIO + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::gpio_w )
-{
- UINT32 old_value = ((UINT32*)&m_gpio.regs)[offset];
- verboselog(machine(), 9, "(GPIO) %08X <- %08X\n", S3C44B0_BASE_GPIO + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_gpio.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_GPADAT :
- {
- iface_gpio_port_w(S3C44B0_GPIO_PORT_A, data & S3C44B0_GPADAT_MASK);
- }
- break;
- case S3C44B0_GPBDAT :
- {
- iface_gpio_port_w(S3C44B0_GPIO_PORT_B, data & S3C44B0_GPBDAT_MASK);
- }
- break;
- case S3C44B0_GPCDAT :
- {
- iface_gpio_port_w(S3C44B0_GPIO_PORT_C, data & S3C44B0_GPCDAT_MASK);
- }
- break;
- case S3C44B0_GPDDAT :
- {
- iface_gpio_port_w(S3C44B0_GPIO_PORT_D, data & S3C44B0_GPDDAT_MASK);
- }
- break;
- case S3C44B0_GPEDAT :
- {
- iface_gpio_port_w(S3C44B0_GPIO_PORT_E, data & S3C44B0_GPEDAT_MASK);
- }
- break;
- case S3C44B0_GPFDAT :
- {
- iface_gpio_port_w(S3C44B0_GPIO_PORT_F, data & S3C44B0_GPFDAT_MASK);
- }
- break;
- case S3C44B0_GPGDAT :
- {
- iface_gpio_port_w(S3C44B0_GPIO_PORT_G, data & S3C44B0_GPGDAT_MASK);
- }
- break;
- case S3C44B0_EXTINTPND :
- {
- m_gpio.regs.extintpnd = (old_value & ~data);
- check_pending_eint();
- }
- break;
- }
-}
-
-/* UART */
-
-UINT32 s3c44b0_device::uart_r(int ch, UINT32 offset)
-{
- UINT32 data = ((UINT32*)&m_uart[ch].regs)[offset];
- switch (offset)
- {
- case S3C44B0_UTRSTAT :
- {
- data = (data & ~0x00000006) | 0x00000004 | 0x00000002; // [bit 2] Transmitter empty / [bit 1] Transmit buffer empty
- }
- break;
- case S3C44B0_URXH :
- {
- UINT8 rxdata = data & 0xFF;
- verboselog(machine(), 5, "UART %d read %02X (%c)\n", ch, rxdata, ((rxdata >= 32) && (rxdata < 128)) ? (char)rxdata : '?');
- m_uart[ch].regs.utrstat &= ~1; // [bit 0] Receive buffer data ready
- }
- break;
- }
- return data;
-}
-
-void s3c44b0_device::uart_w(int ch, UINT32 offset, UINT32 data, UINT32 mem_mask)
-{
- COMBINE_DATA(&((UINT32*)&m_uart[ch].regs)[offset]);
- switch (offset)
- {
- case S3C44B0_UTXH :
- {
- UINT8 txdata = data & 0xFF;
- verboselog(machine(), 5, "UART %d write %02X (%c)\n", ch, txdata, ((txdata >= 32) && (txdata < 128)) ? (char)txdata : '?');
-#ifdef UART_PRINTF
- printf( "%c", ((txdata >= 32) && (txdata < 128)) ? (char)txdata : '?');
-#endif
- }
- break;
- case S3C44B0_UBRDIV :
- {
- UINT32 mclk, hz;
- mclk = get_mclk();
- hz = (mclk / (m_uart->regs.ubrdiv + 1)) / 16;
- verboselog(machine(), 5, "UART %d - mclk %08X hz %08X\n", ch, mclk, hz);
- m_uart->timer->adjust(attotime::from_hz(hz), ch, attotime::from_hz(hz));
- }
- break;
- }
-}
-
-READ32_MEMBER( s3c44b0_device::uart_0_r )
-{
- UINT32 data = uart_r(0, offset);
-// verboselog(machine(), 9, "(UART 0) %08X -> %08X\n", S3C44B0_BASE_UART_0 + (offset << 2), data);
- return data;
-}
-
-READ32_MEMBER( s3c44b0_device::uart_1_r )
-{
- UINT32 data = uart_r(1, offset);
-// verboselog(machine(), 9, "(UART 1) %08X -> %08X\n", S3C44B0_BASE_UART_1 + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::uart_0_w )
-{
- verboselog(machine(), 9, "(UART 0) %08X <- %08X (%08X)\n", S3C44B0_BASE_UART_0 + (offset << 2), data, mem_mask);
- uart_w(0, offset, data, mem_mask);
-}
-
-WRITE32_MEMBER( s3c44b0_device::uart_1_w )
-{
- verboselog(machine(), 9, "(UART 1) %08X <- %08X (%08X)\n", S3C44B0_BASE_UART_1 + (offset << 2), data, mem_mask);
- uart_w(1, offset, data, mem_mask);
-}
-
-void s3c44b0_device::uart_fifo_w(int uart, UINT8 data)
-{
-// printf("s3c44b0_uart_fifo_w (%c)\n", data);
- m_uart[uart].regs.urxh = data;
- m_uart[uart].regs.utrstat |= 1; // [bit 0] Receive buffer data ready
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::uart_timer_exp )
-{
- int ch = param;
- verboselog(machine(), 2, "UART %d timer callback\n", ch);
- if ((m_uart->regs.ucon & (1 << 9)) != 0)
- {
- const int ch_int[] = { S3C44B0_INT_UTXD0, S3C44B0_INT_UTXD1 };
- request_irq(ch_int[ch]);
- }
-}
-
-/* Watchdog Timer */
-
-UINT16 s3c44b0_device::wdt_calc_current_count()
-{
- return 0;
-}
-
-READ32_MEMBER( s3c44b0_device::wdt_r )
-{
- UINT32 data = ((UINT32*)&m_wdt.regs)[offset];
- switch (offset)
- {
- case S3C44B0_WTCNT :
- {
- // is wdt active?
- if ((m_wdt.regs.wtcon & (1 << 5)) != 0)
- {
- data = wdt_calc_current_count();
- }
- }
- break;
- }
- verboselog(machine(), 9, "(WDT) %08X -> %08X\n", S3C44B0_BASE_WDT + (offset << 2), data);
- return data;
-}
-
-void s3c44b0_device::wdt_start()
-{
- UINT32 mclk, prescaler, clock;
- double freq, hz;
- verboselog(machine(), 1, "WDT start\n");
- mclk = get_mclk();
- prescaler = BITS(m_wdt.regs.wtcon, 15, 8);
- clock = 16 << BITS(m_wdt.regs.wtcon, 4, 3);
- freq = (double)mclk / (prescaler + 1) / clock;
- hz = freq / m_wdt.regs.wtcnt;
- verboselog(machine(), 5, "WDT mclk %d prescaler %d clock %d freq %f hz %f\n", mclk, prescaler, clock, freq, hz);
- m_wdt.timer->adjust(attotime::from_hz(hz), 0, attotime::from_hz(hz));
-}
-
-void s3c44b0_device::wdt_stop()
-{
- verboselog(machine(), 1, "WDT stop\n");
- m_wdt.regs.wtcnt = wdt_calc_current_count();
- m_wdt.timer->adjust(attotime::never, 0);
-}
-
-void s3c44b0_device::wdt_recalc()
-{
- if ((m_wdt.regs.wtcon & (1 << 5)) != 0)
- wdt_start();
- else
- wdt_stop();
-}
-
-WRITE32_MEMBER( s3c44b0_device::wdt_w )
-{
- UINT32 old_value = ((UINT32*)&m_wdt.regs)[offset];
- verboselog(machine(), 9, "(WDT) %08X <- %08X\n", S3C44B0_BASE_WDT + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_wdt.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_WTCON :
- {
- if ((data & (1 << 5)) != (old_value & (1 << 5)))
- {
- wdt_recalc();
- }
- }
- break;
- }
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::wdt_timer_exp )
-{
- verboselog(machine(), 2, "WDT timer callback\n");
- if ((m_wdt.regs.wtcon & (1 << 2)) != 0)
- {
- request_irq(S3C44B0_INT_WDT);
- }
- if ((m_wdt.regs.wtcon & (1 << 0)) != 0)
- {
- //s3c44b0_reset();
- fatalerror("s3c44b0_reset\n");
- }
-}
-
-/* CPU Wrapper */
-
-READ32_MEMBER( s3c44b0_device::cpuwrap_r )
-{
- UINT32 data = ((UINT32*)&m_cpuwrap.regs)[offset];
- verboselog(machine(), 9, "(CPUWRAP) %08X -> %08X\n", S3C44B0_BASE_CPU_WRAPPER + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::cpuwrap_w )
-{
- verboselog(machine(), 9, "(CPUWRAP) %08X <- %08X\n", S3C44B0_BASE_CPU_WRAPPER + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_cpuwrap.regs)[offset]);
-}
-
-/* A/D Converter */
-
-READ32_MEMBER( s3c44b0_device::adc_r )
-{
- UINT32 data = ((UINT32*)&m_adc.regs)[offset];
- verboselog(machine(), 9, "(ADC) %08X -> %08X\n", S3C44B0_BASE_ADC + (offset << 2), data);
- return data;
-}
-
-void s3c44b0_device::adc_start()
-{
- UINT32 mclk, prescaler;
- double freq, hz;
- verboselog(machine(), 1, "ADC start\n");
- mclk = get_mclk();
- prescaler = BITS(m_adc.regs.adcpsr, 7, 0);
- freq = (double)mclk / (2 * (prescaler + 1)) / 16;
- hz = freq / 1; //m_wdt.regs.wtcnt;
- verboselog(machine(), 5, "ADC mclk %d prescaler %d freq %f hz %f\n", mclk, prescaler, freq, hz);
- m_adc.timer->adjust(attotime::from_hz(hz), 0);
-}
-
-void s3c44b0_device::adc_stop()
-{
- verboselog(machine(), 1, "ADC stop\n");
- m_adc.timer->adjust(attotime::never, 0);
-}
-
-void s3c44b0_device::adc_recalc()
-{
- if ((m_adc.regs.adccon & (1 << 0)) != 0)
- adc_start();
- else
- adc_stop();
-}
-
-WRITE32_MEMBER( s3c44b0_device::adc_w )
-{
- UINT32 old_value = ((UINT32*)&m_wdt.regs)[offset];
- verboselog(machine(), 9, "(ADC) %08X <- %08X\n", S3C44B0_BASE_ADC + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_adc.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_ADCCON :
- {
- if ((data & (1 << 0)) != (old_value & (1 << 0)))
- {
- adc_recalc();
- }
- m_adc.regs.adccon &= ~(1 << 0); // "this bit is cleared after the start-up"
- }
- break;
- }
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::adc_timer_exp )
-{
- verboselog(machine(), 2, "ADC timer callback\n");
- m_adc.regs.adccon |= (1 << 6);
- request_irq(S3C44B0_INT_ADC);
-}
-
-/* SIO */
-
-READ32_MEMBER( s3c44b0_device::sio_r )
-{
- UINT32 data = ((UINT32*)&m_sio.regs)[offset];
- verboselog(machine(), 9, "(SIO) %08X -> %08X\n", S3C44B0_BASE_SIO + (offset << 2), data);
- return data;
-}
-
-void s3c44b0_device::sio_start()
-{
- UINT32 mclk, prescaler;
- double freq, hz;
- verboselog(machine(), 1, "SIO start\n");
- mclk = get_mclk();
- prescaler = BITS(m_sio.regs.sbrdr, 11, 0);
- freq = (double)mclk / 2 / (prescaler + 1);
- hz = freq / 1; //m_wdt.regs.wtcnt;
- verboselog(machine(), 5, "SIO mclk %d prescaler %d freq %f hz %f\n", mclk, prescaler, freq, hz);
- m_sio.timer->adjust(attotime::from_hz(hz), 0);
-// printf("SIO transmit %02X (%c)\n", m_sio.regs.siodat, ((m_sio.regs.siodat >= 32) && (m_sio.regs.siodat < 128)) ? (char)m_sio.regs.siodat : '?');
-}
-
-void s3c44b0_device::sio_stop()
-{
- verboselog(machine(), 1, "SIO stop\n");
-// m_wdt.regs.wtcnt = s3c44b0_wdt_calc_current_count( device);
- m_sio.timer->adjust(attotime::never, 0);
-}
-
-void s3c44b0_device::sio_recalc()
-{
- if ((m_sio.regs.siocon & (1 << 3)) != 0)
- sio_start();
- else
- sio_stop();
-}
-
-WRITE32_MEMBER( s3c44b0_device::sio_w )
-{
- UINT32 old_value = ((UINT32*)&m_sio.regs)[offset];
- verboselog(machine(), 9, "(SIO) %08X <- %08X\n", S3C44B0_BASE_SIO + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_sio.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_SIOCON :
- {
- if ((old_value & (1 << 3)) != (data & (1 << 3)))
- {
- sio_recalc();
- }
- m_sio.regs.siocon &= ~(1 << 3); // "This bit is cleared just after writing this bit as 1."
- }
- break;
- }
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::sio_timer_exp )
-{
- verboselog(machine(), 2, "SIO timer callback\n");
-
- m_sio.regs.siodat = 0x00; // TEST
-
- if ((m_sio.regs.siocon & (1 << 0)) != 0)
- {
- request_irq(S3C44B0_INT_SIO);
- }
-}
-
-/* IIS */
-
-inline void s3c44b0_device::iface_i2s_data_w(address_space &space, int ch, UINT16 data)
-{
- if (!m_i2s_data_w.isnull())
- (m_i2s_data_w)(ch, data, 0);
-}
-
-void s3c44b0_device::iis_start()
-{
- UINT32 mclk;
- int prescaler;
- double freq, hz;
- const int div[] = { 2, 4, 6, 8, 10, 12, 14, 16, 1, 0, 3, 0, 5, 0, 7, 0 };
- verboselog(machine(), 1, "IIS start\n");
- mclk = get_mclk();
- prescaler = BITS(m_iis.regs.iispsr, 3, 0);
- freq = (double)mclk / div[prescaler];
- hz = freq / 256 * 2;
- verboselog(machine(), 5, "IIS mclk %d prescaler %d freq %f hz %f\n", mclk, prescaler, freq, hz);
- m_iis.timer->adjust(attotime::from_hz(hz), 0, attotime::from_hz(hz));
-}
-
-void s3c44b0_device::iis_stop()
-{
- verboselog(machine(), 1, "IIS stop\n");
- m_iis.timer->adjust(attotime::never, 0);
-}
-
-READ32_MEMBER( s3c44b0_device::iis_r )
-{
- UINT32 data = ((UINT32*)&m_iis.regs)[offset];
- verboselog(machine(), 9, "(IIS) %08X -> %08X\n", S3C44B0_BASE_IIS + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::iis_w )
-{
- UINT32 old_value = ((UINT32*)&m_iis.regs)[offset];
- verboselog(machine(), 9, "(IIS) %08X <- %08X\n", S3C44B0_BASE_IIS + (offset << 2), data);
- COMBINE_DATA(&((UINT32*)&m_iis.regs)[offset]);
- switch (offset)
- {
- case S3C44B0_IISCON :
- {
- if ((old_value & (1 << 0)) != (data & (1 << 0)))
- {
- if ((data & (1 << 0)) != 0)
- {
- iis_start();
- }
- else
- {
- iis_stop();
- }
- }
- }
- break;
- case S3C44B0_IISFIFO :
- {
- if (ACCESSING_BITS_16_31)
- {
- m_iis.fifo[m_iis.fifo_index++] = BITS(data, 31, 16);
- }
- if (ACCESSING_BITS_0_15)
- {
- m_iis.fifo[m_iis.fifo_index++] = BITS(data, 15, 0);
- }
- if (m_iis.fifo_index == 2)
- {
- m_iis.fifo_index = 0;
- iface_i2s_data_w(space, 0, m_iis.fifo[0]);
- iface_i2s_data_w(space, 1, m_iis.fifo[1]);
- }
- }
- break;
- }
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::iis_timer_exp )
-{
- verboselog(machine(), 2, "IIS timer callback\n");
- if ((m_iis.regs.iiscon & (1 << 5)) != 0)
- {
- bdma_request_iis();
- }
-}
-
-/* ZDMA */
-
-void s3c44b0_device::zdma_trigger(int ch)
-{
- address_space &space = m_cpu->space(AS_PROGRAM);
- UINT32 saddr, daddr;
- int dal, dst, opt, das, cnt;
- verboselog(machine(), 5, "s3c44b0_zdma_trigger %d\n", ch);
- dst = BITS(m_zdma->regs.dcsrc, 31, 30);
- dal = BITS(m_zdma->regs.dcsrc, 29, 28);
- saddr = BITS(m_zdma->regs.dcsrc, 27, 0);
- verboselog(machine(), 5, "dst %d dal %d saddr %08X\n", dst, dal, saddr);
- opt = BITS(m_zdma->regs.dcdst, 31, 30);
- das = BITS(m_zdma->regs.dcdst, 29, 28);
- daddr = BITS(m_zdma->regs.dcdst, 27, 0);
- verboselog(machine(), 5, "opt %d das %d daddr %08X\n", opt, das, daddr);
- cnt = BITS(m_zdma->regs.dccnt, 19, 0);
- verboselog(machine(), 5, "icnt %08X\n", cnt);
- while (cnt > 0)
- {
- verboselog(machine(), 9, "[%08X] -> [%08X]\n", saddr, daddr);
- switch (dst)
- {
- case 0 : space.write_byte(daddr, space.read_byte(saddr)); break;
- case 1 : space.write_word(daddr, space.read_word(saddr)); break;
- case 2 : space.write_dword(daddr, space.read_dword(saddr)); break;
- }
- switch (dal)
- {
- case 1 : saddr += (1 << dst); break;
- case 2 : saddr -= (1 << dst); break;
- }
- switch (das)
- {
- case 1 : daddr += (1 << dst); break;
- case 2 : daddr -= (1 << dst); break;
- }
- cnt -= (1 << dst);
- }
- m_zdma->regs.dcsrc = CLR_BITS(m_zdma->regs.dcsrc, 27, 0) | saddr;
- m_zdma->regs.dcdst = CLR_BITS(m_zdma->regs.dcdst, 27, 0) | daddr;
- m_zdma->regs.dccnt = CLR_BITS(m_zdma->regs.dcdst, 19, 0) | cnt;
- if (cnt == 0)
- {
- if ((m_zdma->regs.dccnt & (1 << 23)) != 0)
- {
- const int ch_int[] = { S3C44B0_INT_ZDMA0, S3C44B0_INT_ZDMA1 };
- request_irq(ch_int[ch]);
- }
- }
-}
-
-void s3c44b0_device::zdma_start(int ch)
-{
- verboselog(machine(), 5, "ZDMA %d start\n", ch);
- m_zdma->regs.dcsrc = m_zdma->regs.disrc;
- m_zdma->regs.dcdst = m_zdma->regs.didst;
- m_zdma->regs.dccnt = m_zdma->regs.dicnt;
- zdma_trigger(ch);
-}
-
-UINT32 s3c44b0_device::zdma_r(int ch, UINT32 offset)
-{
- UINT32 data = ((UINT32*)&m_zdma[ch].regs)[offset];
- return data;
-}
-
-void s3c44b0_device::zdma_w(int ch, UINT32 offset, UINT32 data, UINT32 mem_mask)
-{
- UINT32 old_value = ((UINT32*)&m_zdma[ch].regs)[offset];
- COMBINE_DATA(&((UINT32*)&m_zdma[ch].regs)[offset]);
- switch (offset)
- {
- case S3C44B0_DCON :
- {
- if ((old_value & 3) != (data & 3))
- {
- switch (data & 3)
- {
- case 1 : zdma_start(ch); break;
- }
- }
- m_zdma[ch].regs.dcon &= ~3; // "After writing 01,10,11, CMD bit is cleared automatically"
- }
- break;
- }
-}
-
-READ32_MEMBER( s3c44b0_device::zdma_0_r )
-{
- UINT32 data = zdma_r(0, offset);
- verboselog(machine(), 9, "(ZDMA 0) %08X -> %08X\n", S3C44B0_BASE_ZDMA_0 + (offset << 2), data);
- return data;
-}
-
-READ32_MEMBER( s3c44b0_device::zdma_1_r )
-{
- UINT32 data = zdma_r(1, offset);
- verboselog(machine(), 9, "(ZDMA 1) %08X -> %08X\n", S3C44B0_BASE_ZDMA_1 + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::zdma_0_w )
-{
- verboselog(machine(), 9, "(ZDMA 0) %08X <- %08X (%08X)\n", S3C44B0_BASE_ZDMA_0 + (offset << 2), data, mem_mask);
- zdma_w(0, offset, data, mem_mask);
-}
-
-WRITE32_MEMBER( s3c44b0_device::zdma_1_w )
-{
- verboselog(machine(), 9, "(ZDMA 1) %08X <- %08X (%08X)\n", S3C44B0_BASE_ZDMA_1 + (offset << 2), data, mem_mask);
- zdma_w(1, offset, data, mem_mask);
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::zdma_timer_exp )
-{
- int ch = param;
- verboselog(machine(), 2, "ZDMA %d timer callback\n", ch);
-}
-
-/* BDMA */
-
-void s3c44b0_device::bdma_trigger(int ch)
-{
- address_space &space = m_cpu->space(AS_PROGRAM);
- UINT32 saddr, daddr;
- int dal, dst, tdm, das, cnt;
- verboselog(machine(), 5, "s3c44b0_bdma_trigger %d\n", ch);
- dst = BITS(m_bdma->regs.dcsrc, 31, 30);
- dal = BITS(m_bdma->regs.dcsrc, 29, 28);
- saddr = BITS(m_bdma->regs.dcsrc, 27, 0);
- verboselog(machine(), 5, "dst %d dal %d saddr %08X\n", dst, dal, saddr);
- tdm = BITS(m_bdma->regs.dcdst, 31, 30);
- das = BITS(m_bdma->regs.dcdst, 29, 28);
- daddr = BITS(m_bdma->regs.dcdst, 27, 0);
- verboselog(machine(), 5, "tdm %d das %d daddr %08X\n", tdm, das, daddr);
- cnt = BITS(m_bdma->regs.dccnt, 19, 0);
- verboselog(machine(), 5, "icnt %08X\n", cnt);
- verboselog(machine(), 9, "[%08X] -> [%08X]\n", saddr, daddr);
- switch (dst)
- {
- case 0 : space.write_byte(daddr, space.read_byte(saddr)); break;
- case 1 : space.write_word(daddr, space.read_word(saddr)); break;
- case 2 : space.write_dword(daddr, space.read_dword(saddr)); break;
- }
- switch (dal)
- {
- case 1 : saddr += (1 << dst); break;
- case 2 : saddr -= (1 << dst); break;
- }
- switch (das)
- {
- case 1 : daddr += (1 << dst); break;
- case 2 : daddr -= (1 << dst); break;
- }
- cnt -= (1 << dst);
- m_bdma->regs.dcsrc = CLR_BITS(m_bdma->regs.dcsrc, 27, 0) | saddr;
- m_bdma->regs.dcdst = CLR_BITS(m_bdma->regs.dcdst, 27, 0) | daddr;
- m_bdma->regs.dccnt = CLR_BITS(m_bdma->regs.dcdst, 19, 0) | cnt;
- if (cnt == 0)
- {
- if ((m_bdma->regs.dccnt & (1 << 23)) != 0)
- {
- const int ch_int[] = { S3C44B0_INT_BDMA0, S3C44B0_INT_BDMA1 };
- request_irq(ch_int[ch]);
- }
- }
-}
-
-void s3c44b0_device::bdma_request_iis()
-{
- verboselog(machine(), 5, "s3c44b0_bdma_request_iis\n");
- bdma_trigger(0);
-}
-
-UINT32 s3c44b0_device::bdma_r(int ch, UINT32 offset)
-{
- UINT32 data = ((UINT32*)&m_bdma[ch].regs)[offset];
- return data;
-}
-
-void s3c44b0_device::bdma_start(int ch)
-{
- verboselog(machine(), 5, "BDMA %d start\n", ch);
- int qsc = BITS(m_bdma->regs.dicnt, 31, 30);
- if ((ch == 0) && (qsc == 1))
- {
- // IIS
- }
- else
- {
- printf( "s3c44b0_bdma_start - todo\n");
- }
- m_bdma->regs.dcsrc = m_bdma->regs.disrc;
- m_bdma->regs.dcdst = m_bdma->regs.didst;
- m_bdma->regs.dccnt = m_bdma->regs.dicnt;
-}
-
-void s3c44b0_device::bdma_stop(int ch)
-{
- verboselog(machine(), 5, "BDMA %d stop\n", ch);
- m_bdma[ch].timer->adjust(attotime::never, ch);
-}
-
-void s3c44b0_device::bdma_w(int ch, UINT32 offset, UINT32 data, UINT32 mem_mask)
-{
- UINT32 old_value = ((UINT32*)&m_bdma[ch].regs)[offset];
- COMBINE_DATA(&((UINT32*)&m_bdma[ch].regs)[offset]);
- switch (offset)
- {
- case S3C44B0_DICNT :
- {
- if ((old_value & (1 << 20)) != (data & (1 << 20)))
- {
- if ((data & (1 << 20)) != 0)
- {
- bdma_start(ch);
- }
- else
- {
- bdma_stop(ch);
- }
- }
- }
- break;
- }
-}
-
-READ32_MEMBER( s3c44b0_device::bdma_0_r )
-{
- UINT32 data = bdma_r(0, offset);
- verboselog(machine(), 9, "(BDMA 0) %08X -> %08X\n", S3C44B0_BASE_BDMA_0 + (offset << 2), data);
- return data;
-}
-
-READ32_MEMBER( s3c44b0_device::bdma_1_r )
-{
- UINT32 data = bdma_r(1, offset);
- verboselog(machine(), 9, "(BDMA 1) %08X -> %08X\n", S3C44B0_BASE_BDMA_1 + (offset << 2), data);
- return data;
-}
-
-WRITE32_MEMBER( s3c44b0_device::bdma_0_w )
-{
- verboselog(machine(), 9, "(BDMA 0) %08X <- %08X (%08X)\n", S3C44B0_BASE_BDMA_0 + (offset << 2), data, mem_mask);
- bdma_w(0, offset, data, mem_mask);
-}
-
-WRITE32_MEMBER( s3c44b0_device::bdma_1_w )
-{
- verboselog(machine(), 9, "(BDMA 1) %08X <- %08X (%08X)\n", S3C44B0_BASE_BDMA_1 + (offset << 2), data, mem_mask);
- bdma_w(1, offset, data, mem_mask);
-}
-
-TIMER_CALLBACK_MEMBER( s3c44b0_device::bdma_timer_exp )
-{
- int ch = param;
- verboselog(machine(), 2, "BDMA %d timer callback\n", ch);
-}
diff --git a/src/mess/machine/s3c44b0.h b/src/mess/machine/s3c44b0.h
deleted file mode 100644
index 0ae1c60699c..00000000000
--- a/src/mess/machine/s3c44b0.h
+++ /dev/null
@@ -1,825 +0,0 @@
-/*******************************************************************************
-
- Samsung S3C44B0
-
- (c) 2011 Tim Schuerewegen
-
-*******************************************************************************/
-
-#ifndef __S3C44B0_H__
-#define __S3C44B0_H__
-
-
-/*******************************************************************************
- MACROS & CONSTANTS
-*******************************************************************************/
-
-/* Memory Controller */
-
-#define S3C44B0_BASE_MEMCON 0x01C80000
-
-/* Interrupt Controller */
-
-#define S3C44B0_BASE_INT 0x01E00000
-
-#define S3C44B0_INTCON (0x00 / 4) // Interrupt Control
-#define S3C44B0_INTPND (0x04 / 4) // Interrupt Request Status
-#define S3C44B0_INTMOD (0x08 / 4) // Interrupt Mode Control
-#define S3C44B0_INTMSK (0x0C / 4) // Interrupt Mask Control
-#define S3C44B0_I_PSLV (0x10 / 4)
-#define S3C44B0_I_PMST (0x14 / 4)
-#define S3C44B0_I_CSLV (0x18 / 4)
-#define S3C44B0_I_CMST (0x1C / 4)
-#define S3C44B0_I_ISPR (0x20 / 4)
-#define S3C44B0_I_ISPC (0x24 / 4)
-#define S3C44B0_F_ISPR (0x38 / 4)
-#define S3C44B0_F_ISPC (0x3C / 4)
-
-/* ZDMA & BDMA */
-
-#define S3C44B0_BASE_ZDMA_0 0x01E80000
-#define S3C44B0_BASE_ZDMA_1 0x01E80020
-#define S3C44B0_BASE_BDMA_0 0x01F80000
-#define S3C44B0_BASE_BDMA_1 0x01F80020
-
-#define S3C44B0_DCON (0x00 / 4) // DMA Control
-#define S3C44B0_DISRC (0x04 / 4) // DMA Initial Source
-#define S3C44B0_DIDST (0x08 / 4) // DMA Initial Destination
-#define S3C44B0_DICNT (0x0C / 4) // DMA Initial Transfer Count
-#define S3C44B0_DCSRC (0x10 / 4) // DMA Current Source Address
-#define S3C44B0_DCDST (0x14 / 4) // DMA Current Destination Address
-#define S3C44B0_DCCNT (0x18 / 4) // DMA Current Transfer Count
-
-/* Clock & Power Management */
-
-#define S3C44B0_BASE_CLKPOW 0x01D80000
-
-#define S3C44B0_PLLCON (0x00 / 4) // PLL Control
-#define S3C44B0_CLKCON (0x04 / 4) // Clock Generator Control
-#define S3C44B0_CLKSLOW (0x08 / 4) // Slow Clock Control
-#define S3C44B0_LOCKTIME (0x0C / 4) // PLL lock time Counter
-
-/* LCD Controller */
-
-#define S3C44B0_BASE_LCD 0x01F00000
-
-#define S3C44B0_LCDCON1 (0x00 / 4) // LCD Control 1
-#define S3C44B0_LCDCON2 (0x04 / 4) // LCD Control 2
-#define S3C44B0_LCDSADDR1 (0x08 / 4) // Frame Buffer Start Address 1
-#define S3C44B0_LCDSADDR2 (0x0C / 4) // Frame Buffer Start Address 2
-#define S3C44B0_LCDSADDR3 (0x10 / 4) // Virtual Screen Address Set
-#define S3C44B0_REDLUT (0x14 / 4) // STN: Red Lookup Table
-#define S3C44B0_GREENLUT (0x18 / 4) // STN: Green Lookup Table
-#define S3C44B0_BLUELUT (0x1C / 4) // STN: Blue Lookup Table
-#define S3C44B0_LCDCON3 (0x40 / 4) // LCD Control 3
-#define S3C44B0_DITHMODE (0x44 / 4) // STN: Dithering Mode
-
-/* UART */
-
-#define S3C44B0_BASE_UART_0 0x01D00000
-#define S3C44B0_BASE_UART_1 0x01D04000
-
-#define S3C44B0_ULCON (0x00 / 4) // UART Line Control
-#define S3C44B0_UCON (0x04 / 4) // UART Control
-#define S3C44B0_UFCON (0x08 / 4) // UART FIFO Control
-#define S3C44B0_UMCON (0x0C / 4) // UART Modem Control
-#define S3C44B0_UTRSTAT (0x10 / 4) // UART Tx/Rx Status
-#define S3C44B0_UERSTAT (0x14 / 4) // UART Rx Error Status
-#define S3C44B0_UFSTAT (0x18 / 4) // UART FIFO Status
-#define S3C44B0_UMSTAT (0x1C / 4) // UART Modem Status
-#define S3C44B0_UTXH (0x20 / 4) // UART Transmission Hold
-#define S3C44B0_URXH (0x24 / 4) // UART Receive Buffer
-#define S3C44B0_UBRDIV (0x28 / 4) // UART Baud Rate Divisor
-
-/* SIO */
-
-#define S3C44B0_BASE_SIO 0x01D14000
-
-#define S3C44B0_SIOCON (0x00 / 4) // SIO Control
-#define S3C44B0_SIODAT (0x04 / 4) // SIO Data
-#define S3C44B0_SBRDR (0x08 / 4) // SIO Baud Rate Prescaler
-#define S3C44B0_ITVCNT (0x0C / 4) // SIO Interval Counter
-#define S3C44B0_DCNTZ (0x10 / 4) // SIO DMA Count Zero
-
-/* PWM Timer */
-
-#define S3C44B0_BASE_PWM 0x01D50000
-
-#define S3C44B0_TCFG0 (0x00 / 4) // Timer Configuration
-#define S3C44B0_TCFG1 (0x04 / 4) // Timer Configuration
-#define S3C44B0_TCON (0x08 / 4) // Timer Control
-#define S3C44B0_TCNTB0 (0x0C / 4) // Timer Count Buffer 0
-#define S3C44B0_TCMPB0 (0x10 / 4) // Timer Compare Buffer 0
-#define S3C44B0_TCNTO0 (0x14 / 4) // Timer Count Observation 0
-#define S3C44B0_TCNTB1 (0x18 / 4) // Timer Count Buffer 1
-#define S3C44B0_TCMPB1 (0x1C / 4) // Timer Compare Buffer 1
-#define S3C44B0_TCNTO1 (0x20 / 4) // Timer Count Observation 1
-#define S3C44B0_TCNTB2 (0x24 / 4) // Timer Count Buffer 2
-#define S3C44B0_TCMPB2 (0x28 / 4) // Timer Compare Buffer 2
-#define S3C44B0_TCNTO2 (0x2C / 4) // Timer Count Observation 2
-#define S3C44B0_TCNTB3 (0x30 / 4) // Timer Count Buffer 3
-#define S3C44B0_TCMPB3 (0x34 / 4) // Timer Compare Buffer 3
-#define S3C44B0_TCNTO3 (0x38 / 4) // Timer Count Observation 3
-#define S3C44B0_TCNTB4 (0x3C / 4) // Timer Count Buffer 4
-#define S3C44B0_TCMPB4 (0x40 / 4) // Timer Compare Buffer 4
-#define S3C44B0_TCNTO4 (0x44 / 4) // Timer Count Observation 4
-#define S3C44B0_TCNTB5 (0x48 / 4) // Timer Count Buffer 5
-#define S3C44B0_TCNTO5 (0x4C / 4) // Timer Count Observation 5
-
-/* USB Device */
-
-#define S3C44B0_BASE_USBDEV 0x15200140
-
-/* Watchdog Timer */
-
-#define S3C44B0_BASE_WDT 0x01D30000
-
-#define S3C44B0_WTCON (0x00 / 4) // Watchdog Timer Mode
-#define S3C44B0_WTDAT (0x04 / 4) // Watchdog Timer Data
-#define S3C44B0_WTCNT (0x08 / 4) // Watchdog Timer Count
-
-/* IIC */
-
-#define S3C44B0_BASE_IIC 0x01D60000
-
-#define S3C44B0_IICCON (0x00 / 4) // IIC Control
-#define S3C44B0_IICSTAT (0x04 / 4) // IIC Status
-#define S3C44B0_IICADD (0x08 / 4) // IIC Address
-#define S3C44B0_IICDS (0x0C / 4) // IIC Data Shift
-
-/* IIS */
-
-#define S3C44B0_BASE_IIS 0x01D18000
-
-#define S3C44B0_IISCON (0x00 / 4) // IIS Control
-#define S3C44B0_IISMOD (0x04 / 4) // IIS Mode
-#define S3C44B0_IISPSR (0x08 / 4) // IIS Prescaler
-#define S3C44B0_IISFCON (0x0C / 4) // IIS FIFO Control
-#define S3C44B0_IISFIFO (0x10 / 4) // IIS FIFO Entry
-
-/* I/O Port */
-
-#define S3C44B0_BASE_GPIO 0x01D20000
-
-#define S3C44B0_GPACON (0x00 / 4) // Port A Control
-#define S3C44B0_GPADAT (0x04 / 4) // Port A Data
-#define S3C44B0_GPBCON (0x08 / 4) // Port B Control
-#define S3C44B0_GPBDAT (0x0C / 4) // Port B Data
-#define S3C44B0_GPCCON (0x10 / 4) // Port C Control
-#define S3C44B0_GPCDAT (0x14 / 4) // Port C Data
-#define S3C44B0_GPCUP (0x18 / 4) // Pull-up Control C
-#define S3C44B0_GPDCON (0x1C / 4) // Port D Control
-#define S3C44B0_GPDDAT (0x20 / 4) // Port D Data
-#define S3C44B0_GPDUP (0x24 / 4) // Pull-up Control D
-#define S3C44B0_GPECON (0x28 / 4) // Port E Control
-#define S3C44B0_GPEDAT (0x2C / 4) // Port E Data
-#define S3C44B0_GPEUP (0x30 / 4) // Pull-up Control E
-#define S3C44B0_GPFCON (0x34 / 4) // Port F Control
-#define S3C44B0_GPFDAT (0x38 / 4) // Port F Data
-#define S3C44B0_GPFUP (0x3C / 4) // Pull-up Control F
-#define S3C44B0_GPGCON (0x40 / 4) // Port G Control
-#define S3C44B0_GPGDAT (0x44 / 4) // Port G Data
-#define S3C44B0_GPGUP (0x48 / 4) // Pull-up Control G
-#define S3C44B0_SPUCR (0x4C / 4) // Special Pull-up
-#define S3C44B0_EXTINT (0x50 / 4) // External Interrupt Control
-#define S3C44B0_EXTINTPND (0x54 / 4) // External Interrupt Pending
-
-#define S3C44B0_GPADAT_MASK 0x000003FF
-#define S3C44B0_GPBDAT_MASK 0x000007FF
-#define S3C44B0_GPCDAT_MASK 0x0000FFFF
-#define S3C44B0_GPDDAT_MASK 0x000000FF
-#define S3C44B0_GPEDAT_MASK 0x000001FF
-#define S3C44B0_GPFDAT_MASK 0x000001FF
-#define S3C44B0_GPGDAT_MASK 0x000000FF
-
-/* RTC */
-
-#define S3C44B0_BASE_RTC 0x01D70040
-
-#define S3C44B0_RTCCON (0x00 / 4) // RTC Control
-#define S3C44B0_RTCALM (0x10 / 4) // RTC Alarm Control
-#define S3C44B0_ALMSEC (0x14 / 4) // Alarm Second
-#define S3C44B0_ALMMIN (0x18 / 4) // Alarm Minute
-#define S3C44B0_ALMHOUR (0x1C / 4) // Alarm Hour
-#define S3C44B0_ALMDAY (0x20 / 4) // Alarm Day
-#define S3C44B0_ALMMON (0x24 / 4) // Alarm Month
-#define S3C44B0_ALMYEAR (0x28 / 4) // Alarm Year
-#define S3C44B0_RTCRST (0x2C / 4) // RTC Round Reset
-#define S3C44B0_BCDSEC (0x30 / 4) // BCD Second
-#define S3C44B0_BCDMIN (0x34 / 4) // BCD Minute
-#define S3C44B0_BCDHOUR (0x38 / 4) // BCD Hour
-#define S3C44B0_BCDDAY (0x3C / 4) // BCD Day
-#define S3C44B0_BCDDOW (0x40 / 4) // BCD Day of Week
-#define S3C44B0_BCDMON (0x44 / 4) // BCD Month
-#define S3C44B0_BCDYEAR (0x48 / 4) // BCD Year
-#define S3C44B0_TICNT (0x4C / 4) // Tick Time count
-
-/* A/D Converter */
-
-#define S3C44B0_BASE_ADC 0x01D40000
-
-#define S3C44B0_ADCCON (0x00 / 4) // ADC Control
-#define S3C44B0_ADCPSR (0x04 / 4) // ADC Prescaler
-#define S3C44B0_ADCDAT (0x08 / 4) // ADC Data
-
-/* CPU Wrapper */
-
-#define S3C44B0_BASE_CPU_WRAPPER 0x01C00000
-
-#define S3C44B0_SYSCFG (0x00 / 4) // System Configuration
-#define S3C44B0_NCACHBE0 (0x04 / 4) // Non Cacheable Area 0
-#define S3C44B0_NCACHBE1 (0x08 / 4) // Non Cacheable Area 1
-
-/* ... */
-
-#define S3C44B0_INT_ADC 0
-#define S3C44B0_INT_RTC 1
-#define S3C44B0_INT_UTXD1 2
-#define S3C44B0_INT_UTXD0 3
-#define S3C44B0_INT_SIO 4
-#define S3C44B0_INT_IIC 5
-#define S3C44B0_INT_URXD1 6
-#define S3C44B0_INT_URXD0 7
-#define S3C44B0_INT_TIMER5 8
-#define S3C44B0_INT_TIMER4 9
-#define S3C44B0_INT_TIMER3 10
-#define S3C44B0_INT_TIMER2 11
-#define S3C44B0_INT_TIMER1 12
-#define S3C44B0_INT_TIMER0 13
-#define S3C44B0_INT_UERR 14
-#define S3C44B0_INT_WDT 15
-#define S3C44B0_INT_BDMA1 16
-#define S3C44B0_INT_BDMA0 17
-#define S3C44B0_INT_ZDMA1 18
-#define S3C44B0_INT_ZDMA0 19
-#define S3C44B0_INT_TICK 20
-#define S3C44B0_INT_EINT4_7 21
-#define S3C44B0_INT_EINT3 22
-#define S3C44B0_INT_EINT2 23
-#define S3C44B0_INT_EINT1 24
-#define S3C44B0_INT_EINT0 25
-
-#define S3C44B0_MODESEL_01 0
-#define S3C44B0_MODESEL_02 1
-#define S3C44B0_MODESEL_04 2
-#define S3C44B0_MODESEL_08 3
-
-#define S3C44B0_PNRMODE_STN_04_DS 0
-#define S3C44B0_PNRMODE_STN_04_SS 1
-#define S3C44B0_PNRMODE_STN_08_SS 2
-
-#define S3C44B0_GPIO_PORT_A S3C44B0_GPIO_PORT_A
-#define S3C44B0_GPIO_PORT_B S3C44B0_GPIO_PORT_B
-#define S3C44B0_GPIO_PORT_C S3C44B0_GPIO_PORT_C
-#define S3C44B0_GPIO_PORT_D S3C44B0_GPIO_PORT_D
-#define S3C44B0_GPIO_PORT_E S3C44B0_GPIO_PORT_E
-#define S3C44B0_GPIO_PORT_F S3C44B0_GPIO_PORT_F
-#define S3C44B0_GPIO_PORT_G S3C44B0_GPIO_PORT_G
-
-/*******************************************************************************
- TYPE DEFINITIONS
- *******************************************************************************/
-
-struct s3c44b0_interface_gpio
-{
- devcb_read32 port_r;
- devcb_write32 port_w;
-};
-
-struct s3c44b0_interface_i2c
-{
- devcb_write_line scl_w;
- devcb_read_line sda_r;
- devcb_write_line sda_w;
-};
-
-struct s3c44b0_interface_adc
-{
- devcb_read32 data_r;
-};
-
-struct s3c44b0_interface_i2s
-{
- devcb_write16 data_w;
-};
-
-struct s3c44b0_interface
-{
- s3c44b0_interface_gpio gpio_itf;
- s3c44b0_interface_i2c i2c_itf;
- s3c44b0_interface_adc adc_itf;
- s3c44b0_interface_i2s i2s_itf;
-};
-
-/*******************************************************************************
- MACROS / CONSTANTS
- *******************************************************************************/
-
-
-struct s3c44b0_memcon_regs_t
-{
- UINT32 data[0x34/4];
-};
-
-struct s3c44b0_irq_regs_t
-{
- UINT32 intcon;
- UINT32 intpnd;
- UINT32 intmod;
- UINT32 intmsk;
- UINT32 i_pslv;
- UINT32 i_pmst;
- UINT32 i_cslv;
- UINT32 i_cmst;
- UINT32 i_ispr;
- UINT32 i_ispc;
- UINT32 reserved[4];
- UINT32 f_ispr;
- UINT32 f_ispc;
-};
-
-struct s3c44b0_dma_regs_t
-{
- UINT32 dcon;
- UINT32 disrc;
- UINT32 didst;
- UINT32 dicnt;
- UINT32 dcsrc;
- UINT32 dcdst;
- UINT32 dccnt;
-};
-
-struct s3c44b0_clkpow_regs_t
-{
- UINT32 pllcon;
- UINT32 clkcon;
- UINT32 clkslow;
- UINT32 locktime;
-};
-
-struct s3c44b0_lcd_regs_t
-{
- UINT32 lcdcon1;
- UINT32 lcdcon2;
- UINT32 lcdsaddr1;
- UINT32 lcdsaddr2;
- UINT32 lcdsaddr3;
- UINT32 redlut;
- UINT32 greenlut;
- UINT32 bluelut;
- UINT32 reserved[8];
- UINT32 lcdcon3;
- UINT32 dithmode;
-};
-
-struct s3c44b0_uart_regs_t
-{
- UINT32 ulcon;
- UINT32 ucon;
- UINT32 ufcon;
- UINT32 umcon;
- UINT32 utrstat;
- UINT32 uerstat;
- UINT32 ufstat;
- UINT32 umstat;
- UINT32 utxh;
- UINT32 urxh;
- UINT32 ubrdiv;
-};
-
-struct s3c44b0_sio_regs_t
-{
- UINT32 siocon;
- UINT32 siodat;
- UINT32 sbrdr;
- UINT32 itvcnt;
- UINT32 dcntz;
-};
-
-struct s3c44b0_pwm_regs_t
-{
- UINT32 tcfg0;
- UINT32 tcfg1;
- UINT32 tcon;
- UINT32 tcntb0;
- UINT32 tcmpb0;
- UINT32 tcnto0;
- UINT32 tcntb1;
- UINT32 tcmpb1;
- UINT32 tcnto1;
- UINT32 tcntb2;
- UINT32 tcmpb2;
- UINT32 tcnto2;
- UINT32 tcntb3;
- UINT32 tcmpb3;
- UINT32 tcnto3;
- UINT32 tcntb4;
- UINT32 tcmpb4;
- UINT32 tcnto4;
- UINT32 tcntb5;
- UINT32 tcnto5;
-};
-
-struct s3c44b0_wdt_regs_t
-{
- UINT32 wtcon;
- UINT32 wtdat;
- UINT32 wtcnt;
-};
-
-struct s3c44b0_iic_regs_t
-{
- UINT32 iiccon;
- UINT32 iicstat;
- UINT32 iicadd;
- UINT32 iicds;
-};
-
-struct s3c44b0_iis_regs_t
-{
- UINT32 iiscon;
- UINT32 iismod;
- UINT32 iispsr;
- UINT32 iisfcon;
- UINT32 iisfifo;
-};
-
-struct s3c44b0_gpio_regs_t
-{
- UINT32 gpacon;
- UINT32 gpadat;
- UINT32 gpbcon;
- UINT32 gpbdat;
- UINT32 gpccon;
- UINT32 gpcdat;
- UINT32 gpcup;
- UINT32 gpdcon;
- UINT32 gpddat;
- UINT32 gpdup;
- UINT32 gpecon;
- UINT32 gpedat;
- UINT32 gpeup;
- UINT32 gpfcon;
- UINT32 gpfdat;
- UINT32 gpfup;
- UINT32 gpgcon;
- UINT32 gpgdat;
- UINT32 gpgup;
- UINT32 spucr;
- UINT32 extint;
- UINT32 extintpnd;
-};
-
-struct s3c44b0_rtc_regs_t
-{
- UINT32 rtccon;
- UINT32 reserved[3];
- UINT32 rtcalm;
- UINT32 almsec;
- UINT32 almmin;
- UINT32 almhour;
- UINT32 almday;
- UINT32 almmon;
- UINT32 almyear;
- UINT32 rtcrst;
- UINT32 bcdsec;
- UINT32 bcdmin;
- UINT32 bcdhour;
- UINT32 bcdday;
- UINT32 bcddow;
- UINT32 bcdmon;
- UINT32 bcdyear;
- UINT32 ticnt;
-};
-
-struct s3c44b0_adc_regs_t
-{
- UINT32 adccon;
- UINT32 adcpsr;
- UINT32 adcdat;
-};
-
-struct s3c44b0_cpuwrap_regs_t
-{
- UINT32 syscfg;
- UINT32 ncachbe0;
- UINT32 ncachbe1;
-};
-
-struct s3c44b0_memcon_t
-{
- s3c44b0_memcon_regs_t regs;
-};
-
-struct s3c44b0_irq_t
-{
- s3c44b0_irq_regs_t regs;
- int line_irq, line_fiq;
-};
-
-struct s3c44b0_dma_t
-{
- s3c44b0_dma_regs_t regs;
- emu_timer *timer;
-};
-
-struct s3c44b0_clkpow_t
-{
- s3c44b0_clkpow_regs_t regs;
-};
-
-struct rectangle_t
-{
- int x1, y1, x2, y2;
-};
-
-struct s3c44b0_lcd_t
-{
- s3c44b0_lcd_regs_t regs;
- emu_timer *timer;
- UINT8 *bitmap;
- UINT32 vramaddr_cur;
- UINT32 vramaddr_max;
- UINT32 offsize;
- UINT32 pagewidth_cur;
- UINT32 pagewidth_max;
- UINT32 modesel;
- UINT32 bswp;
- int vpos, hpos;
- double framerate;
- UINT32 hpos_min, hpos_max, hpos_end, vpos_min, vpos_max, vpos_end;
- attotime frame_time;
- attoseconds_t frame_period, pixeltime, scantime;
-};
-
-struct s3c44b0_uart_t
-{
- s3c44b0_uart_regs_t regs;
- emu_timer *timer;
-};
-
-struct s3c44b0_sio_t
-{
- s3c44b0_sio_regs_t regs;
- emu_timer *timer;
-};
-
-struct s3c44b0_pwm_t
-{
- s3c44b0_pwm_regs_t regs;
- emu_timer *timer[6];
- UINT32 cnt[6];
- UINT32 cmp[6];
- UINT32 freq[6];
-};
-
-struct s3c44b0_wdt_t
-{
- s3c44b0_wdt_regs_t regs;
- emu_timer *timer;
-};
-
-struct s3c44b0_iic_t
-{
- s3c44b0_iic_regs_t regs;
- emu_timer *timer;
- int count;
-};
-
-struct s3c44b0_iis_t
-{
- s3c44b0_iis_regs_t regs;
- emu_timer *timer;
- UINT16 fifo[16/2];
- int fifo_index;
-};
-
-struct s3c44b0_gpio_t
-{
- s3c44b0_gpio_regs_t regs;
-};
-
-struct s3c44b0_rtc_t
-{
- s3c44b0_rtc_regs_t regs;
- emu_timer *timer_tick_count;
- emu_timer *timer_update;
-};
-
-struct s3c44b0_adc_t
-{
- s3c44b0_adc_regs_t regs;
- emu_timer *timer;
-};
-
-struct s3c44b0_cpuwrap_t
-{
- s3c44b0_cpuwrap_regs_t regs;
-};
-
-
-enum
-{
- S3C44B0_GPIO_PORT_A = 0,
- S3C44B0_GPIO_PORT_B,
- S3C44B0_GPIO_PORT_C,
- S3C44B0_GPIO_PORT_D,
- S3C44B0_GPIO_PORT_E,
- S3C44B0_GPIO_PORT_F,
- S3C44B0_GPIO_PORT_G
-};
-
-class s3c44b0_device : public device_t,
- public s3c44b0_interface
-{
-public:
- s3c44b0_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
- ~s3c44b0_device() {}
-
- DECLARE_READ32_MEMBER(lcd_r);
- DECLARE_READ32_MEMBER(clkpow_r);
- DECLARE_READ32_MEMBER(irq_r);
- DECLARE_READ32_MEMBER(pwm_r);
- DECLARE_READ32_MEMBER(iic_r);
- DECLARE_READ32_MEMBER(gpio_r);
- DECLARE_READ32_MEMBER(uart_0_r);
- DECLARE_READ32_MEMBER(uart_1_r);
- DECLARE_READ32_MEMBER(wdt_r);
- DECLARE_READ32_MEMBER(cpuwrap_r);
- DECLARE_READ32_MEMBER(adc_r);
- DECLARE_READ32_MEMBER(sio_r);
- DECLARE_READ32_MEMBER(iis_r);
- DECLARE_READ32_MEMBER(zdma_0_r);
- DECLARE_READ32_MEMBER(zdma_1_r);
- DECLARE_READ32_MEMBER(bdma_0_r);
- DECLARE_READ32_MEMBER(bdma_1_r);
-
- DECLARE_WRITE32_MEMBER(lcd_w);
- DECLARE_WRITE32_MEMBER(clkpow_w);
- DECLARE_WRITE32_MEMBER(irq_w);
- DECLARE_WRITE32_MEMBER(pwm_w);
- DECLARE_WRITE32_MEMBER(iic_w);
- DECLARE_WRITE32_MEMBER(gpio_w);
- DECLARE_WRITE32_MEMBER(uart_0_w);
- DECLARE_WRITE32_MEMBER(uart_1_w);
- DECLARE_WRITE32_MEMBER(wdt_w);
- DECLARE_WRITE32_MEMBER(cpuwrap_w);
- DECLARE_WRITE32_MEMBER(adc_w);
- DECLARE_WRITE32_MEMBER(sio_w);
- DECLARE_WRITE32_MEMBER(iis_w);
- DECLARE_WRITE32_MEMBER(zdma_0_w);
- DECLARE_WRITE32_MEMBER(zdma_1_w);
- DECLARE_WRITE32_MEMBER(bdma_0_w);
- DECLARE_WRITE32_MEMBER(bdma_1_w);
-
- void request_eint(UINT32 number);
- UINT32 video_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
-
-protected:
- // device-level overrides
- virtual void device_config_complete();
- virtual void device_start();
- virtual void device_reset();
-
-private:
- // internal state
- // LCD Controller
- rgb_t lcd_get_color_stn_04(UINT8 data);
- UINT8 lcd_get_color_stn_08_r(UINT8 data);
- UINT8 lcd_get_color_stn_08_g(UINT8 data);
- UINT8 lcd_get_color_stn_08_b(UINT8 data);
- void lcd_dma_reload();
- void lcd_dma_init();
- void lcd_dma_read(int count, UINT8 *data);
- void lcd_render_stn_04();
- void lcd_render_stn_08();
- attotime time_until_pos(int vpos, int hpos);
- int lcd_get_vpos();
- int lcd_get_hpos();
- void video_start();
- void lcd_configure();
- void lcd_start();
- void lcd_stop();
- void lcd_recalc();
- TIMER_CALLBACK_MEMBER(lcd_timer_exp);
-
- // Clock & Power Management
- UINT32 get_mclk();
-
- // Interrupt Controller
- void check_pending_irq();
- void request_irq(UINT32 int_type);
- void check_pending_eint();
-
- // PWM Timer
- UINT16 pwm_calc_observation(int ch);
- void pwm_start(int timer);
- void pwm_stop(int timer);
- void pwm_recalc(int timer);
- TIMER_CALLBACK_MEMBER(pwm_timer_exp);
- //void dma_request_pwm();
-
- // IIC
- inline void iface_i2c_scl_w(int state);
- inline void iface_i2c_sda_w(int state);
- inline int iface_i2c_sda_r();
- void i2c_send_start();
- void i2c_send_stop();
- UINT8 i2c_receive_byte(int ack);
- int i2c_send_byte(UINT8 data);
- void iic_start();
- void iic_stop();
- void iic_resume();
- TIMER_CALLBACK_MEMBER(iic_timer_exp);
-
- // I/O Port
- inline UINT32 iface_gpio_port_r(int port);
- inline void iface_gpio_port_w(int port, UINT32 data);
-
- // UART
- UINT32 uart_r(int ch, UINT32 offset);
- void uart_w(int ch, UINT32 offset, UINT32 data, UINT32 mem_mask);
- void uart_fifo_w(int uart, UINT8 data);
- TIMER_CALLBACK_MEMBER(uart_timer_exp);
-
- // Watchdog Timer
- UINT16 wdt_calc_current_count();
- void wdt_start();
- void wdt_stop();
- void wdt_recalc();
- TIMER_CALLBACK_MEMBER(wdt_timer_exp);
-
- // A/D Converter
- void adc_start();
- void adc_stop();
- void adc_recalc();
- TIMER_CALLBACK_MEMBER(adc_timer_exp);
-
- // SIO
- void sio_start();
- void sio_stop();
- void sio_recalc();
- TIMER_CALLBACK_MEMBER(sio_timer_exp);
-
- // IIS
- inline void iface_i2s_data_w(address_space &space, int ch, UINT16 data);
- void iis_start();
- void iis_stop();
- TIMER_CALLBACK_MEMBER(iis_timer_exp);
-
- // ZDMA
- void zdma_trigger(int ch);
- void zdma_start(int ch);
- UINT32 zdma_r(int ch, UINT32 offset);
- void zdma_w(int ch, UINT32 offset, UINT32 data, UINT32 mem_mask);
- TIMER_CALLBACK_MEMBER(zdma_timer_exp);
-
- // BDMA
- void bdma_trigger(int ch);
- void bdma_request_iis();
- UINT32 bdma_r(int ch, UINT32 offset);
- void bdma_start(int ch);
- void bdma_stop(int ch);
- void bdma_w(int ch, UINT32 offset, UINT32 data, UINT32 mem_mask);
- TIMER_CALLBACK_MEMBER(bdma_timer_exp);
-
- cpu_device *m_cpu;
- //s3c44b0_memcon_t m_memcon;
- s3c44b0_irq_t m_irq;
- s3c44b0_dma_t m_zdma[2];
- s3c44b0_dma_t m_bdma[2];
- s3c44b0_clkpow_t m_clkpow;
- s3c44b0_lcd_t m_lcd;
- s3c44b0_uart_t m_uart[2];
- s3c44b0_sio_t m_sio;
- s3c44b0_pwm_t m_pwm;
- s3c44b0_wdt_t m_wdt;
- s3c44b0_iic_t m_iic;
- s3c44b0_iis_t m_iis;
- s3c44b0_gpio_t m_gpio;
- //s3c44b0_rtc_t m_rtc;
- s3c44b0_adc_t m_adc;
- s3c44b0_cpuwrap_t m_cpuwrap;
- devcb_resolved_read32 m_port_r;
- devcb_resolved_write32 m_port_w;
- devcb_resolved_write_line m_scl_w;
- devcb_resolved_read_line m_sda_r;
- devcb_resolved_write_line m_sda_w;
- devcb_resolved_read32 m_adc_data_r;
- devcb_resolved_write16 m_i2s_data_w;
-
- void s3c44b0_postload();
-};
-
-extern const device_type S3C44B0;
-
-
-#define MCFG_S3C44B0_ADD(_tag, _clock, _config) \
- MCFG_DEVICE_ADD(_tag, S3C44B0, _clock) \
- MCFG_DEVICE_CONFIG(_config)
-
-#define S3C44B0_INTERFACE(name) \
- const s3c44b0_interface(name) =
-
-
-#endif
diff --git a/src/mess/machine/upd71071.c b/src/mess/machine/upd71071.c
deleted file mode 100644
index 573c3f933c4..00000000000
--- a/src/mess/machine/upd71071.c
+++ /dev/null
@@ -1,447 +0,0 @@
-
-/*
-
- NEC uPD71071 DMA Controller
- Used on the Fujitsu FM-Towns
-
- Register description:
-
- 0x00: Initialise (Write-only)
- - bit 0: Reset
- - bit 1: 16-bit data bus
-
- 0x01: Channel Register
- On read:
- - bits 0-3: Selected channel
- - bit 4: Only base registers may be read or written
- On write:
- - bits 0-1: Select channel for programming count, address, and mode registers
- - bit 2: Only base registers can be read or written to
-
- 0x02:
- 0x03: Count Register (16-bit)
- DMA Transfer counter
-
- 0x04:
- 0x05:
- 0x06:
- 0x07: Address Register (32-bit)
- Self-explanatory, I hope. :)
- NOTE: Datasheet clearly shows this as 24-bit, with register 7 unused.
- But the FM-Towns definitely uses reg 7 as bits 24-31.
-
- 0x08:
- 0x09: Device Control register (16-bit)
- bit 0: Enable memory-to-memory (MTM) transfers
- bit 1: Enable fixed address for channel 0 only (MTM only)
- bit 2: Disable DMA operation (stops HLDRQ signal to the CPU)
- bit 3: Use compressed timing
- bit 4: Rotational Priority
- bit 5: Extended Writing
- bit 6: DMARQ active level (1=active low)
- bit 7: DMAAK active level (1=active high)
- bit 8: Bus mode (0=bus release, 1=bus hold)
- bit 9: Wait Enable during Verify
-
- 0x0a: Mode Control register
- bit 0: Transfer size (1=16-bit, 0=8-bit, 16-bit data bus size only)
- bit 2-3: Transfer direction (ignored for MTM transfers)
- 00 = Verify
- 01 = I/O to memory
- 10 = memory to I/O
- 11 = invalid
- bit 4: Enable auto-initialise
- bit 5: Address direction (0=increment, 1=decrement, affects only current Address reg)
- bit 6-7: Transfer mode (ignored for MTM transfers)
- 00 = Demand
- 01 = Single
- 10 = Block
- 11 = Cascade
-
- 0x0b: Status register
- bit 0-3: Terminal count (per channel)
- bit 4-7: DMA request present (external hardware DMA only)
-
- 0x0c:
- 0x0d: Temporary register (16-bit, read-only)
- Stores the last data transferred in an MTM transfer
-
- 0x0e: Request register
- bit 0-3: Software DMA request (1=set)
- bit 0 only in MTM transfers
-
- 0x0f: Mask register
- bit 0-3: DMARQ mask
- bits 1 and 0 only in MTM transfers
-
-
-*/
-
-#include "emu.h"
-#include "machine/upd71071.h"
-
-
-const device_type UPD71071 = &device_creator<upd71071_device>;
-
-upd71071_device::upd71071_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
- : device_t(mconfig, UPD71071, "NEC uPD71071", tag, owner, clock, "upd71071", __FILE__)
-{
-}
-
-//-------------------------------------------------
-// device_config_complete - perform any
-// operations now that the configuration is
-// complete
-//-------------------------------------------------
-
-void upd71071_device::device_config_complete()
-{
- // inherit a copy of the static data
- const upd71071_intf *intf = reinterpret_cast<const upd71071_intf *>(static_config());
- if (intf != NULL)
- *static_cast<upd71071_intf *>(this) = *intf;
-
- // or initialize to defaults if none provided
- else
- {
- }
-}
-
-//-------------------------------------------------
-// device_start - device-specific startup
-//-------------------------------------------------
-
-void upd71071_device::device_start()
-{
- m_cpu = machine().device<cpu_device>(cputag);
-
- m_out_hreq_func.resolve(m_out_hreq_cb, *this);
- m_out_eop_func.resolve(m_out_eop_cb, *this);
- for (int x = 0; x < 4; x++)
- {
- m_timer[x] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(upd71071_device::dma_transfer_timer),this));
- m_dma_read[x].resolve(m_dma_read_cb[x], *this);
- m_dma_write[x].resolve(m_dma_write_cb[x], *this);
- m_out_dack_func[x].resolve(m_out_dack_cb[x], *this);
- }
- m_selected_channel = 0;
-
-
- save_item(NAME(m_reg.initialise));
- save_item(NAME(m_reg.channel));
- save_item(NAME(m_reg.count_current));
- save_item(NAME(m_reg.count_base));
- save_item(NAME(m_reg.address_current));
- save_item(NAME(m_reg.address_base));
- save_item(NAME(m_reg.device_control));
- save_item(NAME(m_reg.mode_control));
- save_item(NAME(m_reg.status));
- save_item(NAME(m_reg.temp_l));
- save_item(NAME(m_reg.temp_h));
- save_item(NAME(m_reg.request));
- save_item(NAME(m_reg.mask));
-
- save_item(NAME(m_selected_channel));
- save_item(NAME(m_buswidth));
- save_item(NAME(m_dmarq));
- save_item(NAME(m_base));
- save_item(NAME(m_hreq));
- save_item(NAME(m_eop));
-}
-
-
-
-TIMER_CALLBACK_MEMBER(upd71071_device::dma_transfer_timer)
-{
- // single byte or word transfer
- address_space& space = m_cpu->space(AS_PROGRAM);
- int channel = param;
- UINT16 data = 0; // data to transfer
-
- switch (m_reg.mode_control[channel] & 0x0c)
- {
- case 0x00: // Verify
- break;
- case 0x04: // I/O -> memory
- if (!m_dma_read[channel].isnull())
- data = m_dma_read[channel](0);
- space.write_byte(m_reg.address_current[channel], data & 0xff);
- if (m_reg.mode_control[channel] & 0x20) // Address direction
- m_reg.address_current[channel]--;
- else
- m_reg.address_current[channel]++;
- m_reg.count_current[channel]--;
- if(m_reg.count_current[channel] == 0xffff)
- {
- if (m_reg.mode_control[channel] & 0x10) // auto-initialise
- {
- m_reg.address_current[channel] = m_reg.address_base[channel];
- m_reg.count_current[channel] = m_reg.count_base[channel];
- }
- // TODO: send terminal count
- set_eop(ASSERT_LINE);
- }
- break;
- case 0x08: // memory -> I/O
- data = space.read_byte(m_reg.address_current[channel]);
- if (!m_dma_write[channel].isnull())
- m_dma_write[channel](0, data);
- if (m_reg.mode_control[channel] & 0x20) // Address direction
- m_reg.address_current[channel]--;
- else
- m_reg.address_current[channel]++;
- m_reg.count_current[channel]--;
- if(m_reg.count_current[channel] == 0xffff)
- {
- if (m_reg.mode_control[channel] & 0x10) // auto-initialise
- {
- m_reg.address_current[channel] = m_reg.address_base[channel];
- m_reg.count_current[channel] = m_reg.count_base[channel];
- }
- // TODO: send terminal count
- set_eop(ASSERT_LINE);
- }
- break;
- case 0x0c: // Invalid
- break;
- }
-}
-
-void upd71071_device::soft_reset()
-{
- // Does not change base/current address, count, or buswidth
- m_selected_channel = 0;
- m_base = 0;
- for (int x = 0; x < 4; x++)
- m_reg.mode_control[x] = 0;
- m_reg.device_control = 0;
- m_reg.temp_h = 0;
- m_reg.temp_l = 0;
- m_reg.mask = 0x0f; // mask all channels
- m_reg.status &= ~0x0f; // clears bits 0-3 only
- m_reg.request = 0;
-}
-
-int upd71071_device::dmarq(int state, int channel)
-{
- if (state != 0)
- {
- if (m_reg.device_control & 0x0004)
- return 2;
-
- if (m_reg.mask & (1 << channel)) // is channel masked?
- return 1;
-
- m_dmarq[channel] = 1; // DMARQ line is set
- m_reg.status |= (0x10 << channel);
-
- // start transfer
- switch (m_reg.mode_control[channel] & 0xc0)
- {
- case 0x00: // Demand
- // TODO
- set_eop(CLEAR_LINE);
- m_timer[channel]->adjust(attotime::from_hz(m_upd_clock), channel);
- break;
- case 0x40: // Single
- m_timer[channel]->adjust(attotime::from_hz(m_upd_clock), channel);
- break;
- case 0x80: // Block
- // TODO
- break;
- case 0xc0: // Cascade
- // TODO
- break;
-
- }
- }
- else
- {
- m_dmarq[channel] = 0; // clear DMARQ line
- m_reg.status &= ~(0x10 << channel);
- m_reg.status |= (0x01 << channel); // END or TC
- }
- return 0;
-}
-
-READ8_MEMBER(upd71071_device::read)
-{
- UINT8 ret = 0;
-
- logerror("DMA: read from register %02x\n",offset);
- switch(offset)
- {
- case 0x01: // Channel
- ret = (1 << m_selected_channel);
- if (m_base != 0)
- ret |= 0x10;
- break;
- case 0x02: // Count (low)
- if (m_base != 0)
- ret = m_reg.count_base[m_selected_channel] & 0xff;
- else
- ret = m_reg.count_current[m_selected_channel] & 0xff;
- break;
- case 0x03: // Count (high)
- if (m_base != 0)
- ret = (m_reg.count_base[m_selected_channel] >> 8) & 0xff;
- else
- ret = (m_reg.count_current[m_selected_channel] >> 8) & 0xff;
- break;
- case 0x04: // Address (low)
- if (m_base != 0)
- ret = m_reg.address_base[m_selected_channel] & 0xff;
- else
- ret = m_reg.address_current[m_selected_channel] & 0xff;
- break;
- case 0x05: // Address (mid)
- if (m_base != 0)
- ret = (m_reg.address_base[m_selected_channel] >> 8) & 0xff;
- else
- ret = (m_reg.address_current[m_selected_channel] >> 8) & 0xff;
- break;
- case 0x06: // Address (high)
- if (m_base != 0)
- ret = (m_reg.address_base[m_selected_channel] >> 16) & 0xff;
- else
- ret = (m_reg.address_current[m_selected_channel] >> 16) & 0xff;
- break;
- case 0x07: // Address (highest)
- if (m_base != 0)
- ret = (m_reg.address_base[m_selected_channel] >> 24) & 0xff;
- else
- ret = (m_reg.address_current[m_selected_channel] >> 24) & 0xff;
- break;
- case 0x08: // Device control (low)
- ret = m_reg.device_control & 0xff;
- break;
- case 0x09: // Device control (high)
- ret = (m_reg.device_control >> 8) & 0xff;
- break;
- case 0x0a: // Mode control
- ret = m_reg.mode_control[m_selected_channel];
- break;
- case 0x0b: // Status
- ret = m_reg.status;
- m_reg.status &= ~0x0f; // resets END/TC?
- break;
- case 0x0c: // Temporary (low)
- ret = m_reg.temp_h;
- break;
- case 0x0d: // Temporary (high)
- ret = m_reg.temp_l;
- break;
- case 0x0e: // Request
- ret = m_reg.request;
- break;
- case 0x0f: // Mask
- ret = m_reg.mask;
- break;
- }
- return ret;
-}
-
-WRITE8_MEMBER(upd71071_device::write)
-{
- switch (offset)
- {
- case 0x00: // Initialise
- // TODO: reset (bit 0)
- m_buswidth = data & 0x02;
- if (data & 0x01)
- soft_reset();
- logerror("DMA: Initialise [%02x]\n",data);
- break;
- case 0x01: // Channel
- m_selected_channel = data & 0x03;
- m_base = data & 0x04;
- logerror("DMA: Channel selected [%02x]\n",data);
- break;
- case 0x02: // Count (low)
- m_reg.count_base[m_selected_channel] =
- (m_reg.count_base[m_selected_channel] & 0xff00) | data;
- if (m_base == 0)
- m_reg.count_current[m_selected_channel] =
- (m_reg.count_current[m_selected_channel] & 0xff00) | data;
- logerror("DMA: Channel %i Counter set [%04x]\n",m_selected_channel,m_reg.count_base[m_selected_channel]);
- break;
- case 0x03: // Count (high)
- m_reg.count_base[m_selected_channel] =
- (m_reg.count_base[m_selected_channel] & 0x00ff) | (data << 8);
- if (m_base == 0)
- m_reg.count_current[m_selected_channel] =
- (m_reg.count_current[m_selected_channel] & 0x00ff) | (data << 8);
- logerror("DMA: Channel %i Counter set [%04x]\n",m_selected_channel,m_reg.count_base[m_selected_channel]);
- break;
- case 0x04: // Address (low)
- m_reg.address_base[m_selected_channel] =
- (m_reg.address_base[m_selected_channel] & 0xffffff00) | data;
- if (m_base == 0)
- m_reg.address_current[m_selected_channel] =
- (m_reg.address_current[m_selected_channel] & 0xffffff00) | data;
- logerror("DMA: Channel %i Address set [%08x]\n",m_selected_channel,m_reg.address_base[m_selected_channel]);
- break;
- case 0x05: // Address (mid)
- m_reg.address_base[m_selected_channel] =
- (m_reg.address_base[m_selected_channel] & 0xffff00ff) | (data << 8);
- if (m_base == 0)
- m_reg.address_current[m_selected_channel] =
- (m_reg.address_current[m_selected_channel] & 0xffff00ff) | (data << 8);
- logerror("DMA: Channel %i Address set [%08x]\n",m_selected_channel,m_reg.address_base[m_selected_channel]);
- break;
- case 0x06: // Address (high)
- m_reg.address_base[m_selected_channel] =
- (m_reg.address_base[m_selected_channel] & 0xff00ffff) | (data << 16);
- if (m_base == 0)
- m_reg.address_current[m_selected_channel] =
- (m_reg.address_current[m_selected_channel] & 0xff00ffff) | (data << 16);
- logerror("DMA: Channel %i Address set [%08x]\n",m_selected_channel,m_reg.address_base[m_selected_channel]);
- break;
- case 0x07: // Address (highest)
- m_reg.address_base[m_selected_channel] =
- (m_reg.address_base[m_selected_channel] & 0x00ffffff) | (data << 24);
- if (m_base == 0)
- m_reg.address_current[m_selected_channel] =
- (m_reg.address_current[m_selected_channel] & 0x00ffffff) | (data << 24);
- logerror("DMA: Channel %i Address set [%08x]\n",m_selected_channel,m_reg.address_base[m_selected_channel]);
- break;
- case 0x08: // Device control (low)
- m_reg.device_control = (m_reg.device_control & 0xff00) | data;
- logerror("DMA: Device control set [%04x]\n",m_reg.device_control);
- break;
- case 0x09: // Device control (high)
- m_reg.device_control = (m_reg.device_control & 0x00ff) | (data << 8);
- logerror("DMA: Device control set [%04x]\n",m_reg.device_control);
- break;
- case 0x0a: // Mode control
- m_reg.mode_control[m_selected_channel] = data;
- logerror("DMA: Channel %i Mode control set [%02x]\n",m_selected_channel,m_reg.mode_control[m_selected_channel]);
- break;
- case 0x0e: // Request
- m_reg.request = data;
- logerror("DMA: Request set [%02x]\n",data);
- break;
- case 0x0f: // Mask
- m_reg.mask = data;
- logerror("DMA: Mask set [%02x]\n",data);
- break;
- }
-}
-
-WRITE_LINE_MEMBER(upd71071_device::set_hreq)
-{
- if (m_hreq != state)
- {
- m_out_hreq_func(state);
- m_hreq = state;
- }
-}
-
-WRITE_LINE_MEMBER(upd71071_device::set_eop)
-{
- if (m_eop != state)
- {
- m_out_eop_func(state);
- m_eop = state;
- }
-}
diff --git a/src/mess/machine/upd71071.h b/src/mess/machine/upd71071.h
deleted file mode 100644
index be65382e772..00000000000
--- a/src/mess/machine/upd71071.h
+++ /dev/null
@@ -1,84 +0,0 @@
-#ifndef __UPD71071_H__
-#define __UPD71071_H__
-
-#include "emu.h"
-
-struct upd71071_intf
-{
- const char* cputag;
- int m_upd_clock;
- devcb_write_line m_out_hreq_cb;
- devcb_write_line m_out_eop_cb;
- devcb_read16 m_dma_read_cb[4];
- devcb_write16 m_dma_write_cb[4];
- devcb_write_line m_out_dack_cb[4];
-};
-
-struct upd71071_reg
-{
- UINT8 initialise;
- UINT8 channel;
- UINT16 count_current[4];
- UINT16 count_base[4];
- UINT32 address_current[4];
- UINT32 address_base[4];
- UINT16 device_control;
- UINT8 mode_control[4];
- UINT8 status;
- UINT8 temp_l;
- UINT8 temp_h;
- UINT8 request;
- UINT8 mask;
-};
-
-class upd71071_device : public device_t,
- public upd71071_intf
-{
-public:
- upd71071_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
- ~upd71071_device() {}
-
- DECLARE_READ8_MEMBER(read);
- DECLARE_WRITE8_MEMBER(write);
- DECLARE_WRITE_LINE_MEMBER(set_hreq);
- DECLARE_WRITE_LINE_MEMBER(set_eop);
-
- int dmarq(int state, int channel);
-
-protected:
- // device-level overrides
- virtual void device_config_complete();
- virtual void device_start();
-
-private:
- // internal state
- void soft_reset();
- TIMER_CALLBACK_MEMBER(dma_transfer_timer);
-
- struct upd71071_reg m_reg;
- int m_selected_channel;
- int m_buswidth;
- int m_dmarq[4];
- emu_timer* m_timer[4];
- //int m_in_progress[4];
- //int m_transfer_size[4];
- int m_base;
- devcb_resolved_write_line m_out_hreq_func;
- devcb_resolved_write_line m_out_eop_func;
- devcb_resolved_read16 m_dma_read[4];
- devcb_resolved_write16 m_dma_write[4];
- devcb_resolved_write_line m_out_dack_func[4];
- int m_hreq;
- int m_eop;
- cpu_device *m_cpu;
-};
-
-extern const device_type UPD71071;
-
-
-#define MCFG_UPD71071_ADD(_tag, _config) \
- MCFG_DEVICE_ADD(_tag, UPD71071, 0) \
- MCFG_DEVICE_CONFIG(_config)
-
-
-#endif /*UPD71071_H_*/