diff options
author | 2013-04-18 11:54:35 +0000 | |
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committer | 2013-04-18 11:54:35 +0000 | |
commit | ef517f4fd3cb7116976b42e45deffeeffc6dfb03 (patch) | |
tree | 3dd946b64e66ae23c242417e742021f2b88aa87c /src/mess/machine/hecdisk2.c | |
parent | c2f8663985cb4bf6f8c229fa69235a41d1beca22 (diff) |
some mostly pc related cleanup (nw)
Diffstat (limited to 'src/mess/machine/hecdisk2.c')
-rw-r--r-- | src/mess/machine/hecdisk2.c | 87 |
1 files changed, 39 insertions, 48 deletions
diff --git a/src/mess/machine/hecdisk2.c b/src/mess/machine/hecdisk2.c index d67d17ce368..631578e8d58 100644 --- a/src/mess/machine/hecdisk2.c +++ b/src/mess/machine/hecdisk2.c @@ -44,12 +44,11 @@ /*****************************************************************************/ /**** Management of the interrupts (NMI and INT)between uPD765 and Z80 ******/ /*****************************************************************************/ -void hector_disc2_init( running_machine &machine) +void hec2hrp_state::hector_disc2_init() { - hec2hrp_state *state = machine.driver_data<hec2hrp_state>(); - upd765a_device *fdc = machine.device<upd765a_device>("upd765"); - fdc->setup_intrq_cb(upd765a_device::line_cb(FUNC(hec2hrp_state::disc2_fdc_interrupt), state)); - fdc->setup_drq_cb(upd765a_device::line_cb(FUNC(hec2hrp_state::disc2_fdc_dma_irq), state)); + upd765a_device *fdc = machine().device<upd765a_device>("upd765"); + fdc->setup_intrq_cb(upd765a_device::line_cb(FUNC(hec2hrp_state::disc2_fdc_interrupt), this)); + fdc->setup_drq_cb(upd765a_device::line_cb(FUNC(hec2hrp_state::disc2_fdc_dma_irq), this)); } /* upd765 INT is connected to interrupt of Z80 within a RNMI hardware authorization */ @@ -67,96 +66,88 @@ void hec2hrp_state::disc2_fdc_dma_irq(bool state) } // RESET the disc2 Unit ! -void hector_disc2_reset(running_machine &machine) +void hec2hrp_state::hector_disc2_reset() { - hec2hrp_state *state = machine.driver_data<hec2hrp_state>(); // Initialization Disc2 unit - state->m_disc2cpu->set_input_line(INPUT_LINE_RESET, PULSE_LINE); - machine.device<upd765a_device>("upd765")->reset(); + m_disc2cpu->set_input_line(INPUT_LINE_RESET, PULSE_LINE); + machine().device<upd765a_device>("upd765")->reset(); // Select ROM memory to cold restart - state->membank("bank3")->set_entry(DISCII_BANK_ROM); + membank("bank3")->set_entry(DISCII_BANK_ROM); // Clear the Hardware's buffers - state->m_hector_disc2_data_r_ready=0x0; /* =ff when PC2 = true and data in read buffer (state->m_hector_disc2_data_read) */ - state->m_hector_disc2_data_w_ready=0x0; /* =ff when Disc 2 Port 40 had send a data in write buffer (state->m_hector_disc2_data_write) */ - state->m_hector_disc2_data_read=0; /* Data send by Hector to Disc 2 when PC2=true */ - state->m_hector_disc2_data_write=0; /* Data send by Disc 2 to Hector when Write Port I/O 40 */ - state->m_hector_disc2_RNMI = 0; /* State of I/O 50 D5 = authorization for INT / NMI */ - state->m_IRQ_current_state=0; /* Clear the IRQ active request */ - state->m_NMI_current_state=0; /* Clear the DMA active request */ + m_hector_disc2_data_r_ready=0x0; /* =ff when PC2 = true and data in read buffer (state->m_hector_disc2_data_read) */ + m_hector_disc2_data_w_ready=0x0; /* =ff when Disc 2 Port 40 had send a data in write buffer (state->m_hector_disc2_data_write) */ + m_hector_disc2_data_read=0; /* Data send by Hector to Disc 2 when PC2=true */ + m_hector_disc2_data_write=0; /* Data send by Disc 2 to Hector when Write Port I/O 40 */ + m_hector_disc2_RNMI = 0; /* State of I/O 50 D5 = authorization for INT / NMI */ + m_IRQ_current_state=0; /* Clear the IRQ active request */ + m_NMI_current_state=0; /* Clear the DMA active request */ } /*****************************************************************************/ /******************** Port handling of the Z80 Disc II unit *****************/ /*****************************************************************************/ -READ8_HANDLER( hector_disc2_io00_port_r) +READ8_MEMBER( hec2hrp_state::hector_disc2_io00_port_r) { - hec2hrp_state *state = space.machine().driver_data<hec2hrp_state>(); /* Switch Disc 2 to RAM to let full RAM acces */ - state->membank("bank3")->set_entry(DISCII_BANK_RAM); + membank("bank3")->set_entry(DISCII_BANK_RAM); return 0; } -WRITE8_HANDLER( hector_disc2_io00_port_w) +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io00_port_w) { - hec2hrp_state *state = space.machine().driver_data<hec2hrp_state>(); /* Switch Disc 2 to RAM to let full RAM acces */ - state->membank("bank3")->set_entry(DISCII_BANK_RAM); + membank("bank3")->set_entry(DISCII_BANK_RAM); } -READ8_HANDLER( hector_disc2_io20_port_r) +READ8_MEMBER( hec2hrp_state::hector_disc2_io20_port_r) { // You can implemente the 8251 chip communication here ! return 0; } -WRITE8_HANDLER( hector_disc2_io20_port_w) +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io20_port_w) { // You can implemente the 8251 chip communication here ! } -READ8_HANDLER( hector_disc2_io30_port_r) +READ8_MEMBER( hec2hrp_state::hector_disc2_io30_port_r) { - hec2hrp_state *state = space.machine().driver_data<hec2hrp_state>(); - return state->m_hector_disc2_data_r_ready; + return m_hector_disc2_data_r_ready; } -WRITE8_HANDLER( hector_disc2_io30_port_w) +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io30_port_w) { // Nothing here ! } -READ8_HANDLER( hector_disc2_io40_port_r) +READ8_MEMBER( hec2hrp_state::hector_disc2_io40_port_r) { - hec2hrp_state *state = space.machine().driver_data<hec2hrp_state>(); /* Read data send by Hector, by Disc2*/ - state->m_hector_disc2_data_r_ready = 0x00; /* Clear memory info read ready*/ - return state->m_hector_disc2_data_read; /* send the data !*/ + m_hector_disc2_data_r_ready = 0x00; /* Clear memory info read ready*/ + return m_hector_disc2_data_read; /* send the data !*/ } -WRITE8_HANDLER( hector_disc2_io40_port_w) /* Write data send by Disc2, to Hector*/ +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io40_port_w) /* Write data send by Disc2, to Hector*/ { - hec2hrp_state *state = space.machine().driver_data<hec2hrp_state>(); - state->m_hector_disc2_data_write = data; /* Memorization data*/ - state->m_hector_disc2_data_w_ready = 0x80; /* Memorization data write ready in D7*/ + m_hector_disc2_data_write = data; /* Memorization data*/ + m_hector_disc2_data_w_ready = 0x80; /* Memorization data write ready in D7*/ } -READ8_HANDLER( hector_disc2_io50_port_r) /*Read memory info write ready*/ +READ8_MEMBER( hec2hrp_state::hector_disc2_io50_port_r) /*Read memory info write ready*/ { - hec2hrp_state *state = space.machine().driver_data<hec2hrp_state>(); - return state->m_hector_disc2_data_w_ready; + return m_hector_disc2_data_w_ready; } -WRITE8_HANDLER( hector_disc2_io50_port_w) /* I/O Port to the stuff of Disc2*/ +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io50_port_w) /* I/O Port to the stuff of Disc2*/ { - hec2hrp_state *state = space.machine().driver_data<hec2hrp_state>(); - upd765a_device *fdc = space.machine().device<upd765a_device>("upd765"); + upd765a_device *fdc = machine().device<upd765a_device>("upd765"); /* FDC Motor Control - Bit 0/1 defines the state of the FDD 0/1 motor */ - space.machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(BIT(data, 0)); // Moteur floppy A: - space.machine().device<floppy_connector>("upd765:1")->get_device()->mon_w(BIT(data, 1)); // Moteur floppy B: + machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(BIT(data, 0)); // Moteur floppy A: + machine().device<floppy_connector>("upd765:1")->get_device()->mon_w(BIT(data, 1)); // Moteur floppy B: /* Write bit TC uPD765 on D4 of port I/O 50 */ fdc->tc_w(BIT(data, 4)); /* Authorization interrupt and NMI with RNMI signal*/ - state->m_hector_disc2_RNMI = BIT(data, 5); - state->m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, state->m_IRQ_current_state && state->m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); - state->m_disc2cpu->set_input_line(INPUT_LINE_NMI, state->m_NMI_current_state && state->m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); + m_hector_disc2_RNMI = BIT(data, 5); + m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, m_IRQ_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); + m_disc2cpu->set_input_line(INPUT_LINE_NMI, m_NMI_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); } |