diff options
author | arbee <rb6502@users.noreply.github.com> | 2016-06-11 21:05:57 -0400 |
---|---|---|
committer | arbee <rb6502@users.noreply.github.com> | 2016-06-11 21:05:57 -0400 |
commit | fa0f49897a539f3140419b42f01a81add06d0b0d (patch) | |
tree | 4e159ea96fb3213ec9b0f28dfb5b7a4c97b46617 /src/mame | |
parent | d586ae8d12f927056064b7f0b92805459bf3d92f (diff) |
sun3: many improvements, all models now POST including 3/2xx [R. Belmont]
Diffstat (limited to 'src/mame')
-rw-r--r-- | src/mame/drivers/sun3.cpp | 395 |
1 files changed, 340 insertions, 55 deletions
diff --git a/src/mame/drivers/sun3.cpp b/src/mame/drivers/sun3.cpp index acd477636fa..4d198c29399 100644 --- a/src/mame/drivers/sun3.cpp +++ b/src/mame/drivers/sun3.cpp @@ -159,7 +159,7 @@ framebuffer, and SCSI/ethernet boards available. -3/60 ROM breakpoints for start-of-tests +3/60 ROM breakpoints of interest fefb104 - bus error test fefb18e - interrupt test fefb1da - clock IRQ test @@ -168,9 +168,14 @@ fefb3c4 - MMU read-only permissions test fefb45e - parity test: no spurious NMI generated from normal parity operation fefb50c - parity test: NMI is generated when we write with inverted parity and enable parity NMIs fefb5c8 - size memory by bus error -fef58c0 - EPROM checksum read? +fef581c - EPROM mapping check +fef02b2 - main screen turn on + +3/260 ROM breakpoints of interest +fefcb34 - bpset to stop before each test +fefc0c2 - start of ECC test +fefc34a - start of mem_size, which queries ECC registers for each memory board -fefcb34 - bpset for each test on 3/260 ROM ****************************************************************************/ #include "emu.h" @@ -179,6 +184,7 @@ fefcb34 - bpset for each test on 3/260 ROM #include "machine/ram.h" #include "machine/z80scc.h" #include "machine/bankdev.h" +#include "machine/nvram.h" #include "bus/rs232/rs232.h" #define TIMEKEEPER_TAG "timekpr" @@ -218,6 +224,7 @@ public: m_type2space(*this, "type2"), m_type3space(*this, "type3"), m_rom(*this, "user1"), + m_idprom(*this, "idprom"), m_ram(*this, RAM_TAG) { } @@ -230,7 +237,7 @@ public: optional_shared_ptr<UINT32> m_p_ram; optional_shared_ptr<UINT32> m_bw2_vram; optional_device<address_map_bank_device> m_type0space, m_type1space, m_type2space, m_type3space; - required_memory_region m_rom; + required_memory_region m_rom, m_idprom; required_device<ram_device> m_ram; DECLARE_READ32_MEMBER( tl_mmu_r ); @@ -239,35 +246,67 @@ public: DECLARE_WRITE32_MEMBER( ram_w ); DECLARE_READ32_MEMBER( parity_r ); DECLARE_WRITE32_MEMBER( parity_w ); + DECLARE_READ32_MEMBER( ecc_r ); + DECLARE_WRITE32_MEMBER( ecc_w ); DECLARE_READ32_MEMBER( irqctrl_r ); DECLARE_WRITE32_MEMBER( irqctrl_w ); + DECLARE_READ8_MEMBER( rtc7170_r ); DECLARE_WRITE8_MEMBER( rtc7170_w ); UINT32 bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + UINT32 bw2_16x11_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + UINT32 bw2_350_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + + TIMER_DEVICE_CALLBACK_MEMBER(sun3_timer); private: UINT32 *m_rom_ptr, *m_ram_ptr; - UINT32 m_enable, m_buserr, m_diag, m_dvma_enable, m_parregs[8], m_irqctrl; + UINT8 *m_idprom_ptr; + UINT32 m_enable, m_diag, m_dvma_enable, m_parregs[8], m_irqctrl, m_ecc[4]; + UINT8 m_buserr; UINT32 m_context; UINT8 m_segmap[8][2048]; UINT32 m_pagemap[4096]; UINT32 m_ram_size, m_ram_size_words; bool m_bInBusErr; + + UINT32 m_cache_tags[0x4000], m_cache_data[0x4000]; }; READ32_MEMBER( sun3_state::ram_r ) { + if (m_ecc[0] == 0x10c00000) + { + //printf("ECC testing, RAM read ofs %x\n", offset); + m_ecc[1] &= 0x00ffffff; + + if (m_ecc[2] == 0x01000000) // single-bit error test + { + m_ecc[1] |= 0x8f000000; // put in the syndrome code the first ECC test wants + + if (offset == 0) + { + return 0x80000000; + } + } + else if (m_ecc[2] == 0x01000200) // double-bit error test + { + m_ecc[1] |= 0xfc000000; + } + } + if (offset < m_ram_size_words) return m_ram_ptr[offset]; if (!m_bInBusErr) { //printf("ram_r: bus error on timeout, access to invalid addr %08x, PC=%x\n", offset<<2, m_maincpu->pc); + //fflush(stdout); m_buserr = BE_TIMEOUT; m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE); } - + return 0xffffffff; } @@ -331,10 +370,11 @@ WRITE32_MEMBER( sun3_state::ram_w ) COMBINE_DATA(&m_ram_ptr[offset]); return; } - + if (!m_bInBusErr) { //printf("ram_w: bus error on timeout, access to invalid addr %08x, PC=%x\n", offset<<2, m_maincpu->pc); + fflush(stdout); m_buserr = BE_TIMEOUT; m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE); @@ -352,19 +392,18 @@ READ32_MEMBER( sun3_state::tl_mmu_r ) switch (offset >> 26) { case 0: // IDPROM - printf("sun3: Read IDPROM at %x\n", offset); - return 0xffffffff; + //printf("sun3: Read IDPROM at %x (mask %08x)\n", offset, mem_mask); + return m_idprom_ptr[(offset*4)] << 24 | m_idprom_ptr[(offset*4)+1]<<16 | m_idprom_ptr[(offset*4)+2]<<8 | m_idprom_ptr[(offset*4)+3]; case 1: // page map page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4; - page += (offset >> 11) & 0xf; - + page += (offset >> 11) & 0xf; //printf("sun3: Read page map at %x (entry %d)\n", offset<<1, page); return m_pagemap[page]; case 2: // segment map //printf("sun3: Read segment map at %x (entry %d, user ctx %d mask %x)\n", offset<<2, (offset & ~0x3c000000) >> 15, m_context & 7, mem_mask); - return m_segmap[m_context & 7][(offset & ~0x3c000000) >> 15]<<24; + return m_segmap[m_context & 7][(offset >> 15) & 0x7ff]<<24; case 3: // context reg //printf("sun3: Read context reg\n"); @@ -378,18 +417,19 @@ READ32_MEMBER( sun3_state::tl_mmu_r ) case 6: // bus error m_bInBusErr = false; + //printf("Reading bus error: %02x\n", m_buserr); return m_buserr<<24; case 7: // diagnostic reg - return m_diag<<24; + return 0; case 8: // cache tags - printf("sun3: read cache tags @ %x, PC = %x\n", offset, m_maincpu->pc); - return 0xffffffff; + //printf("sun3: read cache tags @ %x, PC = %x\n", offset, m_maincpu->pc); + return m_cache_tags[(offset & 0x3fff) >> 2]; case 9: // cache data - printf("sun3: read cache data @ %x, PC = %x\n", offset, m_maincpu->pc); - return 0xffffffff; + //printf("sun3: read cache data @ %x, PC = %x\n", offset, m_maincpu->pc); + return m_cache_data[(offset & 0x3fff)]; case 10: // flush cache return 0xffffffff; @@ -399,7 +439,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r ) return 0xffffffff; case 15: // UART bypass - printf("sun3: read UART bypass @ %x, PC = %x\n", offset, m_maincpu->pc); + //printf("sun3: read UART bypass @ %x, PC = %x, mask = %08x\n", offset, m_maincpu->pc, mem_mask); return 0xffffffff; } } @@ -420,7 +460,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r ) UINT8 pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff]; UINT32 entry = (pmeg << 4) + ((offset >> 11) & 0xf); - // printf("sun3: Context = %d, pmeg = %d, offset >> 14 = %x, entry = %d, page = %d\n", m_context&7, pmeg, offset >> 14, entry, (offset >> 10) & 0xf); + //printf("sun3: Context = %d, pmeg = %d, offset >> 15 = %x, entry = %d, page = %d\n", m_context&7, pmeg, (offset >> 15) & 0x7ff, entry, (offset >> 11) & 0xf); if (m_pagemap[entry] & PM_VALID) { @@ -429,6 +469,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r ) m_buserr = BE_PROTERR; m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE); + m_bInBusErr = true; return 0xffffffff; } @@ -440,7 +481,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r ) //printf("pmeg %d, entry %d = %08x, virt %08x => tmp %08x\n", pmeg, entry, m_pagemap[entry], offset << 2, tmp); // if (!space.debugger_access()) - // printf("sun2: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, entry, m_pagemap[entry], offset<<1, fc); + //printf("sun3: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, entry, m_pagemap[entry], offset<<2, fc); switch ((m_pagemap[entry] >> 26) & 3) { @@ -448,7 +489,11 @@ READ32_MEMBER( sun3_state::tl_mmu_r ) return m_type0space->read32(space, tmp, mem_mask); case 1: // type 1 space - //printf("read device space @ %x\n", tmp<<1); + // magic ROM bypass + if ((tmp >= (0x100000>>2)) && (tmp <= (0x10ffff>>2))) + { + return m_rom_ptr[offset & 0x3fff]; + } return m_type1space->read32(space, tmp, mem_mask); case 2: // type 2 space @@ -460,14 +505,15 @@ READ32_MEMBER( sun3_state::tl_mmu_r ) } else { - // uncomment to see real state of driver -/* if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc); +// if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc); m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); - m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);*/ + m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE); + m_buserr = BE_INVALID; + m_bInBusErr = true; return 0xffffffff; } - if (!space.debugger_access()) printf("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc, offset>>15); + if (!space.debugger_access()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc, offset>>15); return 0xffffffff; } @@ -489,9 +535,8 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w ) case 1: // page map fefaf32 page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4; - //printf("context = %d, segment = %d, PMEG = %d\n", m_context & 7, (offset >> 15) & 0x7ff, page); + //printf("context = %d, segment = %d, PMEG = %d, add = %d\n", m_context & 7, (offset >> 15) & 0x7ff, page, (offset >> 11) & 0xf); page += (offset >> 11) & 0xf; - //printf("add = %d\n", (offset >> 11) & 0xf); //printf("sun3: Write %04x to page map at %x (entry %d), ", data, offset<<2, page); COMBINE_DATA(&m_pagemap[page]); @@ -501,7 +546,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w ) case 2: // segment map //printf("sun3: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x mask %x)\n", (data>>24) & 0xff, offset<<2, (offset & ~0x3c000000)>>15, m_context & 7, m_maincpu->pc, mem_mask); - m_segmap[m_context & 7][(offset & ~0x3c000000) >> 15] = (data>>24) & 0xff; + m_segmap[m_context & 7][(offset >> 15) & 0x7ff] = (data>>24) & 0xff; //printf("segment map[%d][%d] now %x\n", m_context & 7, (offset & ~0x3c000000) >> 15, m_segmap[m_context & 7][(offset & ~0x3c000000) >> 15] = (data>>24) & 0xff); return; @@ -519,12 +564,12 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w ) m_dvma_enable = data>>24; return; - case 6: // bus error - m_buserr = data >> 24; + case 6: // bus error (read-only) return; case 7: // diagnostic reg m_diag = data >> 24; + #if 0 printf("sun3: CPU LEDs to %02x (PC=%x) => ", ((data>>24) & 0xff) ^ 0xff, m_maincpu->pc); for (int i = 0; i < 8; i++) { @@ -538,14 +583,17 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w ) } } printf("\n"); + #endif return; case 8: // cache tags - printf("sun3: %08x to cache tags @ %x, PC = %x\n", data, offset, m_maincpu->pc); + //printf("sun3: %08x to cache tags @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask); + m_cache_tags[(offset & 0x3fff) >> 2] = data; return; case 9: // cache data - printf("sun3: %08x to cache data @ %x, PC = %x\n", data, offset, m_maincpu->pc); + //printf("sun3: %08x to cache data @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask); + m_cache_data[(offset & 0x3fff)] = data; return; case 10: // flush cache @@ -556,7 +604,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w ) return; case 15: // UART bypass - printf("sun3: %08x to UART bypass @ %x, PC = %x\n", data, offset, m_maincpu->pc); + //printf("sun3: %08x to UART bypass @ %x, PC = %x\n", data, offset, m_maincpu->pc); return; } } @@ -570,9 +618,11 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w ) if ((!(m_pagemap[entry] & PM_WRITEMASK)) || ((m_pagemap[entry] & PM_SYSMASK) && (fc < M68K_FC_SUPERVISOR_DATA))) { + //printf("sun3: write protect MMU error (PC=%x)\n", m_maincpu->pc); m_buserr = BE_PROTERR; m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE); + m_bInBusErr = true; return; } @@ -581,12 +631,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w ) UINT32 tmp = (m_pagemap[entry] & 0x7ffff) << 11; tmp |= (offset & 0x7ff); - //if (!space.debugger_access()) printf("sun2: Translated addr: %08x, type %d (page entry %08x, orig virt %08x)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, m_pagemap[entry], offset<<1); - - //if (((m_pagemap[entry] >> 26) & 3) == 1) - { - //printf("pmeg %d, entry %d = %08x, virt %08x => tmp %08x\n", pmeg, entry, m_pagemap[entry], offset << 2, tmp); - } + //if (!space.debugger_access()) printf("sun3: Translated addr: %08x, type %d (page entry %08x, orig virt %08x)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, m_pagemap[entry], offset<<2); switch ((m_pagemap[entry] >> 26) & 3) { @@ -610,13 +655,15 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w ) } else { - if (!space.debugger_access()) printf("sun3: pagemap entry not valid!\n"); + //if (!space.debugger_access()) printf("sun3: pagemap entry not valid!\n"); m_buserr = BE_INVALID; m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE); + m_bInBusErr = true; + return; } - printf("sun3: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<2); + logerror("sun3: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<2); } READ32_MEMBER(sun3_state::parity_r) @@ -659,16 +706,26 @@ ADDRESS_MAP_END // type 0 device space static ADDRESS_MAP_START(vmetype0space_map, AS_PROGRAM, 32, sun3_state) - AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE(ram_r, ram_w) + AM_RANGE(0x00000000, 0x08ffffff) AM_READWRITE(ram_r, ram_w) + AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM // not sure what's going on here (3/110) + AM_RANGE(0xff000000, 0xff03ffff) AM_RAM AM_SHARE("bw2_vram") +ADDRESS_MAP_END + +// type 0 without VRAM (3/50) +static ADDRESS_MAP_START(vmetype0space_novram_map, AS_PROGRAM, 32, sun3_state) + AM_RANGE(0x00000000, 0x08ffffff) AM_READWRITE(ram_r, ram_w) ADDRESS_MAP_END // type 1 device space static ADDRESS_MAP_START(vmetype1space_map, AS_PROGRAM, 32, sun3_state) + AM_RANGE(0x00000000, 0x0000000f) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00) AM_RANGE(0x00020000, 0x0002000f) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00) - AM_RANGE(0x00060000, 0x0006ffff) AM_WRITE8(rtc7170_w, 0xffffffff) + AM_RANGE(0x00040000, 0x000407ff) AM_RAM AM_SHARE("nvram") // type 2816 parallel EEPROM + AM_RANGE(0x00060000, 0x0006ffff) AM_READWRITE8(rtc7170_r, rtc7170_w, 0xffffffff) AM_RANGE(0x00080000, 0x0008000f) AM_READWRITE(parity_r, parity_w) AM_RANGE(0x000a0000, 0x000a0003) AM_READWRITE(irqctrl_r, irqctrl_w) AM_RANGE(0x00100000, 0x0010ffff) AM_ROM AM_REGION("user1", 0) + AM_RANGE(0x001e0000, 0x001e00ff) AM_READWRITE(ecc_r, ecc_w) ADDRESS_MAP_END // type 2 device space @@ -716,6 +773,13 @@ WRITE32_MEMBER(sun3_state::irqctrl_w) } } +READ8_MEMBER(sun3_state::rtc7170_r) +{ + //printf("read 7170 @ %x, PC=%x\n", offset, m_maincpu->pc); + + return 0xff; +} + WRITE8_MEMBER(sun3_state::rtc7170_w) { //printf("%02x to 7170 @ %x\n", data, offset); @@ -729,9 +793,49 @@ WRITE8_MEMBER(sun3_state::rtc7170_w) } } +READ32_MEMBER(sun3_state::ecc_r) +{ + //printf("read ECC @ %x, PC=%x\n", offset, m_maincpu->pc); + // fefc34a + int mbram = (m_ram_size / (1024*1024)); + int beoff = (mbram / 32) * 0x10; + + //printf("offset %x MB %d beoff %x\n", offset, mbram, beoff); + + if (offset >= beoff) + { + m_buserr = BE_TIMEOUT; + m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); + m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE); + } + + UINT32 rv = m_ecc[offset & 0xf]; + + if ((offset & 0xf) == 0) rv |= 0x06000000; // indicate each ECC board is 32MB, for 128MB total + + return rv; +} + +WRITE32_MEMBER(sun3_state::ecc_w) +{ + //printf("%08x to ecc @ %x, mask %08x\n", data, offset, mem_mask); + + offset &= 0xf; + m_ecc[offset] = data; +} + +TIMER_DEVICE_CALLBACK_MEMBER(sun3_state::sun3_timer) +{ + if ((m_irqctrl & 0x81000000) == 0x81000000) + { + //printf("NMI tick\n"); + m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE); + m_maincpu->set_input_line(M68K_IRQ_7, ASSERT_LINE); + } +} + UINT32 sun3_state::bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) { -#if 0 UINT32 *scanline; int x, y; UINT8 pixels; @@ -755,7 +859,62 @@ UINT32 sun3_state::bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const *scanline++ = palette[(pixels&1)]; } } -#endif + return 0; +} + +UINT32 sun3_state::bw2_16x11_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + UINT32 *scanline; + int x, y; + UINT8 pixels; + static const UINT32 palette[2] = { 0, 0xffffff }; + UINT8 *m_vram = (UINT8 *)m_bw2_vram.target(); + + for (y = 0; y < 1100; y++) + { + scanline = &bitmap.pix32(y); + for (x = 0; x < 1600/8; x++) + { + pixels = m_vram[(y * (1600/8)) + (BYTE4_XOR_BE(x))]; + + *scanline++ = palette[(pixels>>7)&1]; + *scanline++ = palette[(pixels>>6)&1]; + *scanline++ = palette[(pixels>>5)&1]; + *scanline++ = palette[(pixels>>4)&1]; + *scanline++ = palette[(pixels>>3)&1]; + *scanline++ = palette[(pixels>>2)&1]; + *scanline++ = palette[(pixels>>1)&1]; + *scanline++ = palette[(pixels&1)]; + } + } + return 0; +} + +UINT32 sun3_state::bw2_350_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + UINT32 *scanline; + int x, y; + UINT8 pixels; + static const UINT32 palette[2] = { 0, 0xffffff }; + UINT8 *m_vram = (UINT8 *)&m_ram_ptr[(0x100000>>2)]; + + for (y = 0; y < 900; y++) + { + scanline = &bitmap.pix32(y); + for (x = 0; x < 1152/8; x++) + { + pixels = m_vram[(y * (1152/8)) + (BYTE4_XOR_BE(x))]; + + *scanline++ = palette[(pixels>>7)&1]; + *scanline++ = palette[(pixels>>6)&1]; + *scanline++ = palette[(pixels>>5)&1]; + *scanline++ = palette[(pixels>>4)&1]; + *scanline++ = palette[(pixels>>3)&1]; + *scanline++ = palette[(pixels>>2)&1]; + *scanline++ = palette[(pixels>>1)&1]; + *scanline++ = palette[(pixels&1)]; + } + } return 0; } @@ -767,6 +926,7 @@ void sun3_state::machine_start() { m_rom_ptr = (UINT32 *)m_rom->base(); m_ram_ptr = (UINT32 *)m_ram->pointer(); + m_idprom_ptr = (UINT8 *)m_idprom->base(); m_ram_size = m_ram->size(); m_ram_size_words = m_ram_size >> 2; } @@ -776,22 +936,31 @@ void sun3_state::machine_reset() m_maincpu->reset(); m_enable = 0; m_buserr = 0; - m_diag = 0; + m_diag = 1; m_dvma_enable = 0; m_irqctrl = 0; m_bInBusErr = false; } +// The base Sun 3004 CPU board static MACHINE_CONFIG_START( sun3, sun3_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", M68020, 16670000) MCFG_CPU_PROGRAM_MAP(sun3_mem) + MCFG_SCREEN_ADD("bwtwo", RASTER) + MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_update) + MCFG_SCREEN_SIZE(1600,1100) + MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1) + MCFG_SCREEN_REFRESH_RATE(72) + MCFG_RAM_ADD(RAM_TAG) - MCFG_RAM_DEFAULT_SIZE("2M") - MCFG_RAM_EXTRA_OPTIONS("4M,6M,8M,12M,16M,20M,24M,28M,32M") + MCFG_RAM_DEFAULT_SIZE("4M") + MCFG_RAM_EXTRA_OPTIONS("6M,8M,12M,16M,20M,24M,28M,32M") MCFG_RAM_DEFAULT_VALUE(0x00) + MCFG_NVRAM_ADD_0FILL("nvram") + // MMU Type 0 device space MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0) MCFG_DEVICE_PROGRAM_MAP(vmetype0space_map) @@ -820,6 +989,105 @@ static MACHINE_CONFIG_START( sun3, sun3_state ) MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32) MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000) + MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100)) + + MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0) + MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0) + MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd)) + MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(RS232B_TAG, rs232_port_device, write_txd)) + + MCFG_RS232_PORT_ADD(RS232A_TAG, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, rxa_w)) + MCFG_RS232_DCD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, dcda_w)) + MCFG_RS232_CTS_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, ctsa_w)) + + MCFG_RS232_PORT_ADD(RS232B_TAG, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, rxb_w)) + MCFG_RS232_DCD_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, dcdb_w)) + MCFG_RS232_CTS_HANDLER(DEVWRITELINE(SCC2_TAG, z80scc_device, ctsb_w)) +MACHINE_CONFIG_END + +// Sun 3/60 +static MACHINE_CONFIG_DERIVED( sun3_60, sun3 ) + MCFG_CPU_REPLACE("maincpu", M68020, 20000000) + MCFG_CPU_PROGRAM_MAP(sun3_mem) + + MCFG_SCREEN_MODIFY("bwtwo") + MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_16x11_update) + MCFG_SCREEN_SIZE(1600,1100) + MCFG_SCREEN_VISIBLE_AREA(0, 1600-1, 0, 1100-1) + MCFG_SCREEN_REFRESH_RATE(72) +MACHINE_CONFIG_END + +// Sun 3/E +static MACHINE_CONFIG_DERIVED( sun3e, sun3 ) + MCFG_CPU_REPLACE("maincpu", M68020, 20000000) + MCFG_CPU_PROGRAM_MAP(sun3_mem) +MACHINE_CONFIG_END + +// 3/260 and 3/280 (the Sun 3200 board) +static MACHINE_CONFIG_DERIVED( sun3200, sun3 ) + MCFG_CPU_REPLACE("maincpu", M68020, 25000000) + MCFG_CPU_PROGRAM_MAP(sun3_mem) + + MCFG_SCREEN_MODIFY("bwtwo") + MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_16x11_update) + MCFG_SCREEN_SIZE(1600,1100) + MCFG_SCREEN_VISIBLE_AREA(0, 1600-1, 0, 1100-1) + MCFG_SCREEN_REFRESH_RATE(72) + + MCFG_RAM_MODIFY(RAM_TAG) + MCFG_RAM_DEFAULT_SIZE("32M") + MCFG_RAM_EXTRA_OPTIONS("64M,96M,128M") +MACHINE_CONFIG_END + +static MACHINE_CONFIG_START( sun3_50, sun3_state ) + /* basic machine hardware */ + MCFG_CPU_ADD("maincpu", M68020, 15700000) + MCFG_CPU_PROGRAM_MAP(sun3_mem) + + MCFG_SCREEN_ADD("bwtwo", RASTER) + MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_350_update) + MCFG_SCREEN_SIZE(1600,1100) + MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1) + MCFG_SCREEN_REFRESH_RATE(72) + + MCFG_NVRAM_ADD_0FILL("nvram") + + MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100)) + + MCFG_RAM_ADD(RAM_TAG) + MCFG_RAM_DEFAULT_SIZE("4M") + MCFG_RAM_DEFAULT_VALUE(0x00) + + // MMU Type 0 device space + MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0) + MCFG_DEVICE_PROGRAM_MAP(vmetype0space_novram_map) + MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG) + MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32) + MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000) + + // MMU Type 1 device space + MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0) + MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map) + MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG) + MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32) + MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000) + + // MMU Type 2 device space + MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0) + MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map) + MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG) + MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32) + MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000) + + // MMU Type 3 device space + MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0) + MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map) + MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG) + MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32) + MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000) + MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0) MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0) MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd)) @@ -863,6 +1131,9 @@ Sun 3/50 V2.8 Bootprom ROMX_LOAD( "sun3_50_v2.3", 0x0000, 0x10000, CRC(163500b3) SHA1(437c8d539e12d442ca6877566dbbe165d577fcab), ROM_BIOS(4)) ROM_SYSTEM_BIOS(4, "rev16", "Rev 1.6") ROMX_LOAD( "sun3_50_v1.6", 0x0000, 0x10000, CRC(8be20826) SHA1(2a4d73fcb7fe0f0c83eb0f4c91d957b7bf88b7ed), ROM_BIOS(5)) + + ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF) + ROM_LOAD( "sun3-50-idprom.bin", 0x000000, 0x000020, CRC(80610dbe) SHA1(0f37e31ed209b8905c5dc7c2663fa01a9b9baaba) ) ROM_END ROM_START( sun3_60 ) @@ -882,6 +1153,9 @@ Sun 3/60 V3.0.1 Bootprom ROMX_LOAD( "sun_3.60v2.8.3", 0x0000, 0x10000, CRC(de4ec54d) SHA1(e621a9c1a2a7df4975b12fa3a0d7f106383736ef), ROM_BIOS(2)) ROM_SYSTEM_BIOS(2, "rev19", "Rev 1.9") ROMX_LOAD( "sun_3.60v1.9", 0x0000, 0x10000, CRC(32b6d3a9) SHA1(307756ba5698611d51059881057f8086956ce895), ROM_BIOS(3)) + + ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF) + ROM_LOAD( "sun3-60-idprom.bin", 0x000000, 0x000020, CRC(117e766a) SHA1(f01547be0156bd4e06bbdee4c342d1b38c7646ae) ) ROM_END ROM_START( sun3_110 ) @@ -897,6 +1171,9 @@ Sun 3/110 V3.0 Bootprom */ ROM_SYSTEM_BIOS(0, "rev30", "Rev 3.0") ROMX_LOAD( "sun3_110_v3.0", 0x0000, 0x10000, CRC(a193b26b) SHA1(0f54212ee3a5709f70e921069cca1ddb8c143b1b), ROM_BIOS(1)) + + ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF) + ROM_LOAD( "sun3-110-idprom.bin", 0x000000, 0x000020, CRC(d6cd934a) SHA1(b0913708fe733250ef5c1289c10146dcef6d1a67) ) ROM_END ROM_START( sun3_150 ) @@ -925,6 +1202,10 @@ Sun 3/1[4,5,6,8]0 V3.0 Bootprom ROMX_LOAD( "sun3_160_v2.1_rf", 0x0000, 0x10000, CRC(5c7e9271) SHA1(5e4dbb50859a21f9e1d3e4a06c42494d13a9a8eb), ROM_BIOS(4)) ROM_SYSTEM_BIOS(4, "rev15", "Rev 1.5") ROMX_LOAD( "sun3_160_v1.5", 0x0000, 0x10000, CRC(06daee37) SHA1(b9873cd48d78ad8e0c85d69966fc20c21cfc99aa), ROM_BIOS(5)) + + + ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF) + ROM_LOAD( "sun3-150-idprom.bin", 0x000000, 0x000020, CRC(58956a93) SHA1(7334936dc945e05d63a94a33340e963a371672c9) ) ROM_END ROM_START( sun3_260 ) @@ -945,20 +1226,24 @@ Sun 3/260/280 V3.0 Bootprom ROMX_LOAD( "sun3_260_v2.7", 0x0000, 0x10000, CRC(099fcaab) SHA1(4a5233c778676f48103bdd8bab03b4264686b4aa), ROM_BIOS(2)) ROM_SYSTEM_BIOS(2, "rev26", "Rev 2.6") ROMX_LOAD( "sun3_260_v2.6", 0x0000, 0x10000, CRC(e8b17951) SHA1(e1fdef42670a349d99b0eca9c50c8566b8bb7c56), ROM_BIOS(3)) + + ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF) + ROM_LOAD( "sun3-260-idprom.bin", 0x000000, 0x000020, CRC(d51794f3) SHA1(17930c773b6fe9a32819094ffaf69e5453d1ea4d) ) ROM_END ROM_START( sun3_e ) ROM_REGION32_BE( 0x10000, "user1", ROMREGION_ERASEFF ) ROM_SYSTEM_BIOS(0, "rev28", "Rev 3.2") ROMX_LOAD( "sun3_e.32", 0x0000, 0x10000, CRC(acedde7e) SHA1(1ab6ec28f4365a613a5e326c34cb37585c3f0ecc), ROM_BIOS(1)) -ROM_END -/* Driver */ + ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF) + ROM_LOAD( "sun3-e-idprom.bin", 0x000000, 0x000020, CRC(d1a92116) SHA1(4836f3188f2c3dd5ba49ab66e0b55caa6b1b1791) ) +ROM_END /* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */ -COMP( 198?, sun3_50, 0, 0, sun3, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/50", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Model 25 -COMP( 198?, sun3_60, 0, 0, sun3, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/60", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Ferrari +COMP( 198?, sun3_50, 0, 0, sun3_50, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/50", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Model 25 +COMP( 1988, sun3_60, 0, 0, sun3_60, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/60", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Ferrari COMP( 198?, sun3_110, 0, 0, sun3, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/110", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Prism -COMP( 198?, sun3_150, 0, 0, sun3, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/75/140/150/160/180", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // AKA Carrera -COMP( 198?, sun3_260, 0, 0, sun3, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/260/280", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Prism -COMP( 198?, sun3_e, 0, 0, sun3, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/E", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Polaris +COMP( 1985, sun3_150, 0, 0, sun3, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/75/140/150/160/180", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // AKA Carrera +COMP( 198?, sun3_260, 0, 0, sun3200, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/260/280", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Prism +COMP( 198?, sun3_e, 0, 0, sun3e, sun3, driver_device, 0, "Sun Microsystems", "Sun 3/E", MACHINE_NOT_WORKING | MACHINE_NO_SOUND) // Polaris |