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author Patrick Mackinlay <pmackinlay@hotmail.com>2020-10-29 17:17:42 +0700
committer Patrick Mackinlay <pmackinlay@hotmail.com>2020-10-29 17:17:42 +0700
commit6778308df65f46f0527a9a442fb3a96c58237658 (patch)
tree437db0c93c472bbfb70134a71078445a9f7011aa /src/mame
parentc44f6a05ce7276c5bc9146e5ede7820e54e33fb6 (diff)
ncr5380: bug fixes
* clear ACK upon exit from DMA mode * assert DRQ at start of DMA initiator send cycle
Diffstat (limited to 'src/mame')
-rw-r--r--src/mame/machine/dmac_0266.cpp13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/mame/machine/dmac_0266.cpp b/src/mame/machine/dmac_0266.cpp
index 0e65a33af87..e3343baa8e0 100644
--- a/src/mame/machine/dmac_0266.cpp
+++ b/src/mame/machine/dmac_0266.cpp
@@ -143,12 +143,15 @@ void dmac_0266_device::dma_check(void *ptr, s32 param)
* adapter waits for more data that the DMAC is not ready to supply.
* It's not clear how the real hardware works - for now this hack
* continues to read and discard data from the device, or write
- * arbitrary zero bytes to it until it deasserts the request line.
+ * arbitrary zero bytes to it until it asserts EOP (driven by IRQ).
*/
- if (m_control & DIRECTION)
- m_dma_r();
- else
- m_dma_w(0);
+ if (!(m_status & INTERRUPT))
+ {
+ if (m_control & DIRECTION)
+ m_dma_r();
+ else
+ m_dma_w(0);
+ }
return;
}