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authorGravatarGravatar Miodrag Milanovic <mmicko@gmail.com>2016-06-29 08:34:30 +0200
committerGravatarGravatar Miodrag Milanovic <mmicko@gmail.com>2016-06-29 08:34:30 +0200
commit63f9a01f8c5d43b9cfe68c2d401a84647d19c10e (patch)
treea1f1874aa84850bddbebd2b0e0bfc3e1c77ce8c4 /src/mame
parent1f6f1bfd6cfb748d9c5e159d6bd014bab8d30944 (diff)
Cleanup and version bumpmame0175
Diffstat (limited to 'src/mame')
-rw-r--r--src/mame/audio/mario.cpp2
-rw-r--r--src/mame/drivers/8080bw.cpp16
-rw-r--r--src/mame/drivers/abc80x.cpp40
-rw-r--r--src/mame/drivers/aerofgt.cpp10
-rw-r--r--src/mame/drivers/alesis_qs.cpp38
-rw-r--r--src/mame/drivers/altair.cpp4
-rw-r--r--src/mame/drivers/aristmk5.cpp3
-rw-r--r--src/mame/drivers/aristmk6.cpp154
-rw-r--r--src/mame/drivers/atarigx2.cpp12
-rw-r--r--src/mame/drivers/atlantis.cpp4
-rw-r--r--src/mame/drivers/bfcobra.cpp2
-rw-r--r--src/mame/drivers/bloodbro.cpp2
-rw-r--r--src/mame/drivers/cclimber.cpp28
-rw-r--r--src/mame/drivers/chihiro.cpp2
-rw-r--r--src/mame/drivers/deco_ld.cpp4
-rwxr-xr-xsrc/mame/drivers/divebomb.cpp222
-rw-r--r--src/mame/drivers/dlair.cpp8
-rw-r--r--src/mame/drivers/esh.cpp31
-rw-r--r--src/mame/drivers/fccpu30.cpp491
-rw-r--r--src/mame/drivers/fidel6502.cpp6
-rw-r--r--src/mame/drivers/funkball.cpp4
-rw-r--r--src/mame/drivers/galaxian.cpp2
-rw-r--r--src/mame/drivers/galivan.cpp10
-rw-r--r--src/mame/drivers/gba.cpp4
-rw-r--r--src/mame/drivers/go2000.cpp2
-rw-r--r--src/mame/drivers/goldnpkr.cpp20
-rw-r--r--src/mame/drivers/goldstar.cpp64
-rw-r--r--src/mame/drivers/halleys.cpp8
-rw-r--r--src/mame/drivers/hh_cop400.cpp2
-rw-r--r--src/mame/drivers/hh_tms1k.cpp10
-rw-r--r--src/mame/drivers/holeland.cpp8
-rw-r--r--src/mame/drivers/homedata.cpp74
-rw-r--r--src/mame/drivers/kickgoal.cpp2
-rw-r--r--src/mame/drivers/leland.cpp1
-rw-r--r--src/mame/drivers/lgp.cpp8
-rw-r--r--src/mame/drivers/m63.cpp2
-rw-r--r--src/mame/drivers/magicfly.cpp4
-rw-r--r--src/mame/drivers/megasys1.cpp136
-rw-r--r--src/mame/drivers/metlfrzr.cpp27
-rw-r--r--src/mame/drivers/mgames.cpp2
-rw-r--r--src/mame/drivers/naomi.cpp4
-rw-r--r--src/mame/drivers/neogeo.cpp4
-rw-r--r--src/mame/drivers/pasopia7.cpp4
-rw-r--r--src/mame/drivers/patinho_feio.cpp32
-rw-r--r--src/mame/drivers/pc9801.cpp2
-rw-r--r--src/mame/drivers/rainbow.cpp2
-rw-r--r--src/mame/drivers/sg1000.cpp4
-rw-r--r--src/mame/drivers/sun2.cpp256
-rw-r--r--src/mame/drivers/sun3.cpp266
-rw-r--r--src/mame/drivers/sun4.cpp164
-rw-r--r--src/mame/drivers/system16.cpp18
-rwxr-xr-xsrc/mame/drivers/tek440x.cpp86
-rw-r--r--src/mame/drivers/toaplan1.cpp2
-rw-r--r--src/mame/drivers/toaplan2.cpp24
-rw-r--r--src/mame/drivers/toratora.cpp24
-rw-r--r--src/mame/drivers/vegas.cpp8
-rw-r--r--src/mame/drivers/vsmilepro.cpp10
-rw-r--r--src/mame/drivers/x1.cpp2
-rw-r--r--src/mame/includes/aerofgt.h2
-rw-r--r--src/mame/includes/atarigx2.h8
-rw-r--r--src/mame/includes/divebomb.h140
-rw-r--r--src/mame/includes/gameplan.h2
-rw-r--r--src/mame/includes/megasys1.h2
-rw-r--r--src/mame/includes/namconb1.h2
-rw-r--r--src/mame/includes/nmk16.h2
-rw-r--r--src/mame/includes/plygonet.h2
-rw-r--r--src/mame/includes/sg1000.h2
-rw-r--r--src/mame/includes/tsamurai.h2
-rw-r--r--src/mame/layout/patinho.lay260
-rw-r--r--src/mame/machine/atarixga.h62
-rw-r--r--src/mame/machine/dccons.cpp12
-rw-r--r--src/mame/machine/dec_lk201.cpp36
-rw-r--r--src/mame/machine/dec_lk201.h8
-rw-r--r--src/mame/machine/fd1094.cpp2
-rw-r--r--src/mame/machine/kaneko_toybox.cpp2
-rw-r--r--src/mame/machine/m2comm.cpp6
-rw-r--r--src/mame/machine/namcoic.cpp4
-rw-r--r--src/mame/machine/pcecommn.h2
-rw-r--r--src/mame/machine/seibucop/seibucop.cpp128
-rw-r--r--src/mame/machine/seibucop/seibucop.h24
-rw-r--r--src/mame/machine/sms.cpp4
-rw-r--r--src/mame/machine/xbox.cpp22
-rw-r--r--src/mame/mame.lst6
-rw-r--r--src/mame/video/chihiro.cpp2
-rw-r--r--src/mame/video/divebomb.cpp172
-rw-r--r--src/mame/video/exerion.cpp4
-rw-r--r--src/mame/video/gotya.cpp6
-rw-r--r--src/mame/video/homedata.cpp10
-rw-r--r--src/mame/video/megasys1.cpp2
-rw-r--r--src/mame/video/model3.cpp82
-rw-r--r--src/mame/video/namconb1.cpp4
-rw-r--r--src/mame/video/namcos2.cpp2
-rw-r--r--src/mame/video/powervr2.cpp2
-rw-r--r--src/mame/video/seibu_crtc.cpp2
-rw-r--r--src/mame/video/vtvideo.cpp6
95 files changed, 1706 insertions, 1711 deletions
diff --git a/src/mame/audio/mario.cpp b/src/mame/audio/mario.cpp
index d30fada6968..6e4d5722ec9 100644
--- a/src/mame/audio/mario.cpp
+++ b/src/mame/audio/mario.cpp
@@ -883,7 +883,7 @@ MACHINE_CONFIG_FRAGMENT( mario_audio )
MCFG_CPU_IO_MAP(mario_sound_io_map)
MCFG_SPEAKER_STANDARD_MONO("mono")
-
+
MCFG_GENERIC_LATCH_8_ADD("soundlatch")
MCFG_GENERIC_LATCH_8_ADD("soundlatch2")
MCFG_GENERIC_LATCH_8_ADD("soundlatch3")
diff --git a/src/mame/drivers/8080bw.cpp b/src/mame/drivers/8080bw.cpp
index 1894ebbac57..641f278df1a 100644
--- a/src/mame/drivers/8080bw.cpp
+++ b/src/mame/drivers/8080bw.cpp
@@ -3552,14 +3552,14 @@ ROM_END
ROM_START( sicv1 ) // Original Taito board AA017742B - data match for sicv, just smaller program roms (2708s vs. 2716s)
ROM_REGION( 0x10000, "maincpu", 0 )
- ROM_LOAD( "cv11.s1", 0x0000, 0x0400, CRC(309d4582) SHA1(e60a1a696111502c115ee00d84cd418c85aba9af) )
- ROM_LOAD( "cv12.r1", 0x0400, 0x0400, CRC(70153e09) SHA1(b75068b7738aa232f75272c539fca04b3d0c2c4a) )
- ROM_LOAD( "cv13.np1", 0x0800, 0x0400, CRC(2ca24fee) SHA1(4b516ebd5a777b001443159233d89fc0a331f756) )
- ROM_FILL( 0x0c00, 0x0400, 0xff ) /* rom socket at M1 is unpopulated */
+ ROM_LOAD( "cv11.s1", 0x0000, 0x0400, CRC(309d4582) SHA1(e60a1a696111502c115ee00d84cd418c85aba9af) )
+ ROM_LOAD( "cv12.r1", 0x0400, 0x0400, CRC(70153e09) SHA1(b75068b7738aa232f75272c539fca04b3d0c2c4a) )
+ ROM_LOAD( "cv13.np1", 0x0800, 0x0400, CRC(2ca24fee) SHA1(4b516ebd5a777b001443159233d89fc0a331f756) )
+ ROM_FILL( 0x0c00, 0x0400, 0xff ) /* rom socket at M1 is unpopulated */
ROM_FILL( 0x1000, 0x0400, 0xff ) /* rom socket at L1 is unpopulated */
- ROM_LOAD( "cv14.jk1", 0x1400, 0x0400, CRC(556d9a97) SHA1(fb792e981658d79d1c801b01f06345c237e9e803) )
- ROM_LOAD( "cv15.i1", 0x1800, 0x0400, CRC(ac520cf5) SHA1(47281256083d64a2754b2045c252e74fe5b71153) )
- ROM_LOAD( "cv16.g1", 0x1c00, 0x0400, CRC(285cfb59) SHA1(53eab8ed07dc9ca107e2e91b4556b9424a073530) )
+ ROM_LOAD( "cv14.jk1", 0x1400, 0x0400, CRC(556d9a97) SHA1(fb792e981658d79d1c801b01f06345c237e9e803) )
+ ROM_LOAD( "cv15.i1", 0x1800, 0x0400, CRC(ac520cf5) SHA1(47281256083d64a2754b2045c252e74fe5b71153) )
+ ROM_LOAD( "cv16.g1", 0x1c00, 0x0400, CRC(285cfb59) SHA1(53eab8ed07dc9ca107e2e91b4556b9424a073530) )
ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */
ROM_LOAD( "cv01.1", 0x0000, 0x0400, CRC(037e16ac) SHA1(d585030aaff428330c91ae94d7cd5c96ebdd67dd) )
@@ -4590,7 +4590,7 @@ ROM_END
/*
------------------------------
-Ozma Wars by SHIN NIHON KIKAKU
+Ozma Wars by SHIN NIHON KIKAKU
------------------------------
Location Type File ID Checksum
diff --git a/src/mame/drivers/abc80x.cpp b/src/mame/drivers/abc80x.cpp
index e02e5fdf0ec..17b09bd9441 100644
--- a/src/mame/drivers/abc80x.cpp
+++ b/src/mame/drivers/abc80x.cpp
@@ -1523,26 +1523,26 @@ ROM_START( abc806 )
ROM_REGION( 0x104, "abc_p3", 0 )
/*
- 1 12MHz
- 2 DOT
- 3 RTF
- 4 GTF
- 5 BTF
- 6 RTB
- 7 GTB
- 8 BTB
- 9 SFG
- 10 GND
- 11 GND
- 12 RFG
- 13 GFG
- 14 >YL
- 15 >BL
- 16 >GL
- 17 >RL
- 18 BFG
- 19 >FGE
- 20 Vcc
+ 1 12MHz
+ 2 DOT
+ 3 RTF
+ 4 GTF
+ 5 BTF
+ 6 RTB
+ 7 GTB
+ 8 BTB
+ 9 SFG
+ 10 GND
+ 11 GND
+ 12 RFG
+ 13 GFG
+ 14 >YL
+ 15 >BL
+ 16 >GL
+ 17 >RL
+ 18 BFG
+ 19 >FGE
+ 20 Vcc
*/
ROM_LOAD( "60 90239-01.1b", 0x000, 0x104, CRC(f3d0ba00) SHA1(bcc0ee26ecac0028aef6bf5cb308133b509bb360) ) // "ABC P3-11" PAL16R4, color encoder
diff --git a/src/mame/drivers/aerofgt.cpp b/src/mame/drivers/aerofgt.cpp
index 6794f8bf8e0..cbd5f8465d0 100644
--- a/src/mame/drivers/aerofgt.cpp
+++ b/src/mame/drivers/aerofgt.cpp
@@ -244,8 +244,8 @@ static ADDRESS_MAP_START( spinlbrk_map, AS_PROGRAM, 16, aerofgt_state )
AM_RANGE(0xfff002, 0xfff003) AM_READ_PORT("IN1") AM_WRITE(aerofgt_bg2scrollx_w)
AM_RANGE(0xfff004, 0xfff005) AM_READ_PORT("DSW")
AM_RANGE(0xfff006, 0xfff007) AM_WRITE(sound_command_w)
-// AM_RANGE(0xfff008, 0xfff009) - read when analog inputs are enabled
-// AM_RANGE(0xfff00a, 0xfff00b) /
+// AM_RANGE(0xfff008, 0xfff009) - read when analog inputs are enabled
+// AM_RANGE(0xfff00a, 0xfff00b) /
ADDRESS_MAP_END
static ADDRESS_MAP_START( turbofrc_map, AS_PROGRAM, 16, aerofgt_state )
@@ -1575,15 +1575,15 @@ static MACHINE_CONFIG_START( karatblzbl, aerofgt_state )
MCFG_VSYSTEM_SPR2_GFXDECODE("gfxdecode")
MCFG_VIDEO_START_OVERRIDE(aerofgt_state,karatblz)
-
+
MCFG_GENERIC_LATCH_8_ADD("soundlatch")
MCFG_GENERIC_LATCH_8_ADD("soundlatch2")
/* sound hardware */
-
+
MCFG_SPEAKER_STANDARD_MONO("mono")
- MCFG_SOUND_ADD("ymsnd", YM3812, XTAL_8MHz/2)
+ MCFG_SOUND_ADD("ymsnd", YM3812, XTAL_8MHz/2)
MCFG_YM3812_IRQ_HANDLER(INPUTLINE("audiocpu", 0))
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
diff --git a/src/mame/drivers/alesis_qs.cpp b/src/mame/drivers/alesis_qs.cpp
index e50e7aa3667..61215c782ad 100644
--- a/src/mame/drivers/alesis_qs.cpp
+++ b/src/mame/drivers/alesis_qs.cpp
@@ -51,41 +51,41 @@ static MACHINE_CONFIG_START( qs7, qs_state )
MCFG_CPU_ADD("maincpu", H83048, XTAL_10MHz) /* FIX-ME! Actual CPU is H8/510 and XTAL value is a guess */
MCFG_CPU_PROGRAM_MAP(qs7_prog_map)
- //MCFG_ALESIS_KEYSCAN_ASIC_ADD("keyscan")
+ //MCFG_ALESIS_KEYSCAN_ASIC_ADD("keyscan")
- /* Alesis Sound Generator ASIC */
- //MCFG_ALESIS_SG_ASIC_ADD("sndgen")
+ /* Alesis Sound Generator ASIC */
+ //MCFG_ALESIS_SG_ASIC_ADD("sndgen")
- /* Alesis Sound Effects Processor ASIC */
- //MCFG_ALESIS_FX_ASIC_ADD("sfx")
+ /* Alesis Sound Effects Processor ASIC */
+ //MCFG_ALESIS_FX_ASIC_ADD("sfx")
/* video hardware */
- //TODO: add LCD display controller here
+ //TODO: add LCD display controller here
/* sound hardware */
//MCFG_SPEAKER_STANDARD_STEREO("stereo")
//MCFG_ALESIS_QS_SERIES_ADD("sound", SND_CLOCK)
//MCFG_SOUND_ROUTE(ALL_OUTPUTS, "stereo", 1.0)
- /* Interfaces */
- //MCFG_PCMCIA_ADD("pcmcia")
- //MIDI
- //RS232
+ /* Interfaces */
+ //MCFG_PCMCIA_ADD("pcmcia")
+ //MIDI
+ //RS232
MACHINE_CONFIG_END
ROM_START( alesqs7 )
ROM_REGION( 0x80000, "maincpu", 0 )
ROM_LOAD( "2-31-0069_q7_v1.02_alesis_sp_09_12_96_cs_dbcc.u18", 0x00000, 0x80000, CRC(6e5404cb) SHA1(f00598b66ab7a83b16105cbb73e09c66ce3493a7) )
-// ROM_REGION( 0x200000, "sound", 0 ) /* Samples ROMs (2Mbyte each) */
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
-// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_REGION( 0x200000, "sound", 0 ) /* Samples ROMs (2Mbyte each) */
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
+// ROM_LOAD( "?.u?", 0x00000, 0x200000, NO_DUMP )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
diff --git a/src/mame/drivers/altair.cpp b/src/mame/drivers/altair.cpp
index b9099974f73..60dc683c006 100644
--- a/src/mame/drivers/altair.cpp
+++ b/src/mame/drivers/altair.cpp
@@ -5,7 +5,7 @@
MITS Altair 8800b Turnkey
04/12/2009 Initial driver by Miodrag Milanovic
-
+
Supposedly introduced October 1977.
Commands:
@@ -17,7 +17,7 @@
D - Memory Dump
J - Jump to address
M - Modify memory
-
+
Reference:
http://www.computercloset.org/MITSAltair8800bt.htm
diff --git a/src/mame/drivers/aristmk5.cpp b/src/mame/drivers/aristmk5.cpp
index afcf9106e49..58d7288de1b 100644
--- a/src/mame/drivers/aristmk5.cpp
+++ b/src/mame/drivers/aristmk5.cpp
@@ -2122,7 +2122,7 @@ ROM_END
ROM_START( topbana )
ARISTOCRAT_MK5_BIOS
ROM_REGION( 0x400000, "game_prg", ROMREGION_ERASEFF )
- ROM_LOAD32_WORD("0100550v.u11", 0x0000002, 0x007fffa, BAD_DUMP CRC(140a73bc) SHA1(3fd88797b6310f5849e901d032fbeb8a2d8604fb) ) // This is a bad .u8 from Indian Dream, not proper Top Banana .u11!!
+ ROM_LOAD32_WORD("0100550v.u11", 0x0000002, 0x007fffa, BAD_DUMP CRC(140a73bc) SHA1(3fd88797b6310f5849e901d032fbeb8a2d8604fb) ) // This is a bad .u8 from Indian Dream, not proper Top Banana .u11!!
ROM_LOAD32_WORD("0100550v.u7", 0x0000000, 0x0080000, CRC(1f60241c) SHA1(3a6207d9c919319fc10b6de63bc030f8d335588e) )
ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASE00 ) /* ARM Code */
@@ -2422,4 +2422,3 @@ GAME( 1996, wcougar, aristmk5, aristmk5_usa, aristmk5, aristmk5_state, aristmk
GAME( 1997, wcougaru, wcougar, aristmk5_usa, aristmk5, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Wild Cougar (NHG0296-04, US)", MACHINE_FLAGS ) // 569/8, D - 19/05/97
GAME( 1999, wthing, aristmk5, aristmk5_usa, aristmk5, aristmk5_state, aristmk5, ROT0, "Aristocrat", "Wild Thing (0101158V, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 608/4, B - 14/12/99
GAME( 1999, wtiger, 0, aristmk5, aristmk5, aristmk5_state, aristmk5, ROT0, "Aristocrat", "White Tiger Classic (0200954V, NSW/ACT)", MACHINE_FLAGS ) // 638/1, B - 08/07/99
-
diff --git a/src/mame/drivers/aristmk6.cpp b/src/mame/drivers/aristmk6.cpp
index 5a192fa1d87..d8094f26c6a 100644
--- a/src/mame/drivers/aristmk6.cpp
+++ b/src/mame/drivers/aristmk6.cpp
@@ -305,7 +305,7 @@ MACHINE_CONFIG_END
ROM_LOAD32_WORD_BIOS( 16,"02061013 System 02 Left", 0x0000002, 0x0100000, CRC(e70a7007) SHA1(0935f924866162d9c0fbdbb99391cbf730a04b76) ) \
ROM_LOAD32_WORD_BIOS( 16,"02061013 System 02 Right", 0x0000000, 0x0100000, CRC(7a8619a5) SHA1(bd03ddb68817c1660b009e102ccf69e5b603b875) ) \
ROM_SYSTEM_BIOS( 17, "bios17", "Aristocrat MK6 Base (03030708)" ) \
- ROM_LOAD32_WORD_BIOS( 17,"03030708 System 03 SA LEFT", 0x0000002, 0x0100000, CRC(4e5ad823) SHA1(77ab1c29c6172cfdcef776222a72b2b44114d4da) ) /* From Scatter Magic II */ \
+ ROM_LOAD32_WORD_BIOS( 17,"03030708 System 03 SA LEFT", 0x0000002, 0x0100000, CRC(4e5ad823) SHA1(77ab1c29c6172cfdcef776222a72b2b44114d4da) ) /* From Scatter Magic II */ \
ROM_LOAD32_WORD_BIOS( 17,"03030708 System 03 SA RIGHT", 0x0000000, 0x0100000, CRC(b4b3c6a5) SHA1(5747f98a6eaa5c24a23d1d76a28b33a3bfbbfd1f) ) \
ROM_SYSTEM_BIOS( 18, "bios18", "Aristocrat MK6 Base (09011001)" ) \
ROM_LOAD32_WORD_BIOS( 18,"09011001_SYSTEM_09_EPROM_NSW_LEFT", 0x0000002, 0x0200000, CRC(229c2e63) SHA1(91fd2b1acb69efe073647e93db9f11042add2feb) ) \
@@ -341,7 +341,7 @@ ROM labels all look basically the same (as with aristmk5.cpp boards)
20151911 NSW
INDIAN DREAMING-LL
742 4MB 6 eproms
- Aristocrat � 2005 P U72
+ Aristocrat 2005 P U72
"ID string" + "Region" + "Game Name" + "Combination No." + "ROM size"
+ "ROM numbers" + "Copyright" + "Location"
@@ -378,12 +378,12 @@ ROM_END
ROM_START( 5dragce )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0152309.u71", 0x1000002, 0x0400000, CRC(a0f5999e) SHA1(0be0d58588adbdbc7b728f164538d03509f13fe5) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u72", 0x0800002, 0x0400000, CRC(e399df66) SHA1(d85a8011ab62b899b18873e4296c12da4291870a) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u73", 0x0000002, 0x0400000, CRC(7298e59b) SHA1(b104aec9be996bacad74120f461ad8cd7ef96e09) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u84", 0x1000000, 0x0400000, CRC(f37a1ce5) SHA1(8684d64b20e1fe853e3b0f1a31796cddeb8b0dee) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u85", 0x0800000, 0x0400000, CRC(4af3cae0) SHA1(79eb28b403aacf3ec7f52a5b3ff9e59ea35933c6) ) /* m27v322 */
- ROM_LOAD32_WORD("0152309.u86", 0x0000000, 0x0400000, CRC(1c3fd707) SHA1(3a9fc3e865c43ae0afa31954b2372487eb729d8a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u71", 0x1000002, 0x0400000, CRC(a0f5999e) SHA1(0be0d58588adbdbc7b728f164538d03509f13fe5) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u72", 0x0800002, 0x0400000, CRC(e399df66) SHA1(d85a8011ab62b899b18873e4296c12da4291870a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u73", 0x0000002, 0x0400000, CRC(7298e59b) SHA1(b104aec9be996bacad74120f461ad8cd7ef96e09) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u84", 0x1000000, 0x0400000, CRC(f37a1ce5) SHA1(8684d64b20e1fe853e3b0f1a31796cddeb8b0dee) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u85", 0x0800000, 0x0400000, CRC(4af3cae0) SHA1(79eb28b403aacf3ec7f52a5b3ff9e59ea35933c6) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152309.u86", 0x0000000, 0x0400000, CRC(1c3fd707) SHA1(3a9fc3e865c43ae0afa31954b2372487eb729d8a) ) /* m27v322 */
ROM_END
@@ -561,10 +561,10 @@ ROM_END
ROM_START( arwincm )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0151065.u72", 0x0800002, 0x0400000, CRC(3a133d96) SHA1(4c7dc422c3e0a81da1f81267d525e3a90a7d79d7) ) /* m27v322 */
- ROM_LOAD32_WORD("0151065.u73", 0x0000002, 0x0400000, CRC(0c3e441c) SHA1(763879bae2b256c2c4edddc99507b3c54cbab976) ) /* m27v322 */
- ROM_LOAD32_WORD("0151065.u85", 0x0800000, 0x0400000, CRC(498b2ab7) SHA1(7f1da5ff34572c1f27f9a0735b8a9571b34ac17e) ) /* m27v322 */
- ROM_LOAD32_WORD("0151065.u86", 0x0000000, 0x0400000, CRC(961cca3d) SHA1(f5bd3fdb8863688a1bf96dcd74a261860a008952) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151065.u72", 0x0800002, 0x0400000, CRC(3a133d96) SHA1(4c7dc422c3e0a81da1f81267d525e3a90a7d79d7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151065.u73", 0x0000002, 0x0400000, CRC(0c3e441c) SHA1(763879bae2b256c2c4edddc99507b3c54cbab976) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151065.u85", 0x0800000, 0x0400000, CRC(498b2ab7) SHA1(7f1da5ff34572c1f27f9a0735b8a9571b34ac17e) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151065.u86", 0x0000000, 0x0400000, CRC(961cca3d) SHA1(f5bd3fdb8863688a1bf96dcd74a261860a008952) ) /* m27v322 */
ROM_END
@@ -667,14 +667,14 @@ ROM_END
ROM_START( bobdolly )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0352298.u21", 0x0000000, 0x0400000, CRC(8e32da10) SHA1(28a49ecc3bab512e5828c96392d6fa4ff9394a0f) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u11", 0x0000002, 0x0400000, CRC(d3657369) SHA1(621fb20238f10e06c486dfbd6460f94047898a42) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u22", 0x0800000, 0x0400000, CRC(4302ae5e) SHA1(fe1d122093ad9234a7a5337b3a4c2de7fe046822) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u12", 0x0800002, 0x0400000, CRC(47429081) SHA1(23d996aa522c2f9beadf1fdb7c0584ca939917da) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u23", 0x1000000, 0x0400000, CRC(a9726ec5) SHA1(cdf78adc3ebcd50e503b2587564493a91b73f578) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u13", 0x1000002, 0x0400000, CRC(e73883db) SHA1(6382386ac6f576c739c959cbf6b6df2605496845) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u24", 0x1800000, 0x0400000, CRC(3646c16d) SHA1(c52fab2e11f39c126bcbbb348750bbf30ff96090) ) /* 27v322 */
- ROM_LOAD32_WORD("0352298.u14", 0x1800002, 0x0400000, CRC(0f1a6b7c) SHA1(17686829a1a64f6d8982e015067f2d08bcb00402) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u21", 0x0000000, 0x0400000, CRC(8e32da10) SHA1(28a49ecc3bab512e5828c96392d6fa4ff9394a0f) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u11", 0x0000002, 0x0400000, CRC(d3657369) SHA1(621fb20238f10e06c486dfbd6460f94047898a42) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u22", 0x0800000, 0x0400000, CRC(4302ae5e) SHA1(fe1d122093ad9234a7a5337b3a4c2de7fe046822) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u12", 0x0800002, 0x0400000, CRC(47429081) SHA1(23d996aa522c2f9beadf1fdb7c0584ca939917da) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u23", 0x1000000, 0x0400000, CRC(a9726ec5) SHA1(cdf78adc3ebcd50e503b2587564493a91b73f578) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u13", 0x1000002, 0x0400000, CRC(e73883db) SHA1(6382386ac6f576c739c959cbf6b6df2605496845) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u24", 0x1800000, 0x0400000, CRC(3646c16d) SHA1(c52fab2e11f39c126bcbbb348750bbf30ff96090) ) /* 27v322 */
+ ROM_LOAD32_WORD("0352298.u14", 0x1800002, 0x0400000, CRC(0f1a6b7c) SHA1(17686829a1a64f6d8982e015067f2d08bcb00402) ) /* 27v322 */
ROM_END
@@ -727,7 +727,7 @@ ROM_END
ROM_START( bmbugs )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0351180.u73", 0x0000002, 0x0400000, CRC(79dd907f) SHA1(06352c55ff36a82f4d0550b1723667f3287c4923) ) /* 27v322 */
+ ROM_LOAD32_WORD("0351180.u73", 0x0000002, 0x0400000, CRC(79dd907f) SHA1(06352c55ff36a82f4d0550b1723667f3287c4923) ) /* 27v322 */
ROM_LOAD32_WORD("0351180.u86", 0x0000000, 0x0400000, CRC(f5c204f9) SHA1(592fac02d26ec5edffce862fcce67869430028dd) )
ROM_END
@@ -959,12 +959,12 @@ ROM_END
ROM_START( dimeyece )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0152039.u71", 0x1000002, 0x0400000, CRC(5706aa40) SHA1(d847bd0a4e210e3f065aa59129ee4654e3087909) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u72", 0x0800002, 0x0400000, CRC(9f6b5923) SHA1(739d3848998ddbfaf577982c12d8edd19c348548) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u73", 0x0000002, 0x0400000, CRC(235ba6ca) SHA1(3534b4f74531a42543383b55a2c57853b1d3f4f1) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u84", 0x1000000, 0x0400000, CRC(6d0dea65) SHA1(ee23c0fe2ecb5adb5e383757ade9be17880e6b45) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u85", 0x0800000, 0x0400000, CRC(f6ef5d9c) SHA1(94505a470ad65e75c6c984ec163ce92c558f491a) ) /* m27v322 */
- ROM_LOAD32_WORD("0152039.u86", 0x0000000, 0x0400000, CRC(926ce073) SHA1(12f0aa1e387f0f87be92afb9a917a30d51a63277) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u71", 0x1000002, 0x0400000, CRC(5706aa40) SHA1(d847bd0a4e210e3f065aa59129ee4654e3087909) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u72", 0x0800002, 0x0400000, CRC(9f6b5923) SHA1(739d3848998ddbfaf577982c12d8edd19c348548) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u73", 0x0000002, 0x0400000, CRC(235ba6ca) SHA1(3534b4f74531a42543383b55a2c57853b1d3f4f1) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u84", 0x1000000, 0x0400000, CRC(6d0dea65) SHA1(ee23c0fe2ecb5adb5e383757ade9be17880e6b45) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u85", 0x0800000, 0x0400000, CRC(f6ef5d9c) SHA1(94505a470ad65e75c6c984ec163ce92c558f491a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0152039.u86", 0x0000000, 0x0400000, CRC(926ce073) SHA1(12f0aa1e387f0f87be92afb9a917a30d51a63277) ) /* m27v322 */
ROM_END
@@ -1145,10 +1145,10 @@ ROM_END
ROM_START( flamoljc )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251048.u72", 0x0800002, 0x0400000, CRC(330c1988) SHA1(0d7dae49495c5b164121cd756d6e22af17a9b41b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251048.u73", 0x0000002, 0x0400000, CRC(c8337682) SHA1(e87c5be62528e2e73659ce73a17d1ea21ed3ccf0) ) /* m27v322 */
- ROM_LOAD32_WORD("0251048.u85", 0x0800000, 0x0400000, CRC(2661893a) SHA1(4a79f0b638f5d4fdfa7dcc7661afe3ae1823e6ce) ) /* m27v322 */
- ROM_LOAD32_WORD("0251048.u86", 0x0000000, 0x0400000, CRC(2ea7c6d9) SHA1(cd887f0689737fd447786b966297ea3994fb8cb7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251048.u72", 0x0800002, 0x0400000, CRC(330c1988) SHA1(0d7dae49495c5b164121cd756d6e22af17a9b41b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251048.u73", 0x0000002, 0x0400000, CRC(c8337682) SHA1(e87c5be62528e2e73659ce73a17d1ea21ed3ccf0) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251048.u85", 0x0800000, 0x0400000, CRC(2661893a) SHA1(4a79f0b638f5d4fdfa7dcc7661afe3ae1823e6ce) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251048.u86", 0x0000000, 0x0400000, CRC(2ea7c6d9) SHA1(cd887f0689737fd447786b966297ea3994fb8cb7) ) /* m27v322 */
ROM_END
@@ -1183,10 +1183,10 @@ ROM_END
ROM_START( frogwld )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251114.u72", 0x0800002, 0x0400000, CRC(36f8066f) SHA1(c8a3dc25488d7d578e05bf247b2d3e0959f5c511) ) /* m27v322 */
- ROM_LOAD32_WORD("0251114.u73", 0x0000002, 0x0400000, CRC(f058f8f3) SHA1(02efb3de7765e917fb6c29cbfdd90845fb3f0a7b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251114.u85", 0x0800000, 0x0400000, CRC(b4165c0f) SHA1(823179a70841f49c8100d8d77620548ceea01550) ) /* m27v322 */
- ROM_LOAD32_WORD("0251114.u86", 0x0000000, 0x0400000, CRC(feb93395) SHA1(56c0f9b0e3616bc57a564220303c13f60fc72df8) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251114.u72", 0x0800002, 0x0400000, CRC(36f8066f) SHA1(c8a3dc25488d7d578e05bf247b2d3e0959f5c511) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251114.u73", 0x0000002, 0x0400000, CRC(f058f8f3) SHA1(02efb3de7765e917fb6c29cbfdd90845fb3f0a7b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251114.u85", 0x0800000, 0x0400000, CRC(b4165c0f) SHA1(823179a70841f49c8100d8d77620548ceea01550) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251114.u86", 0x0000000, 0x0400000, CRC(feb93395) SHA1(56c0f9b0e3616bc57a564220303c13f60fc72df8) ) /* m27v322 */
ROM_END
@@ -1482,10 +1482,10 @@ ROM_END
ROM_START( jefffox )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0351068.u72", 0x0800002, 0x0400000, CRC(ff2ff01d) SHA1(c0d17b3d9907d3876c7a1dbc19b023afcffb2bb1) ) /* m27v322 */
- ROM_LOAD32_WORD("0351068.u73", 0x0000002, 0x0400000, CRC(4b778a84) SHA1(d11b2aefcaa2ac22fea80faab524f82511b6344a) ) /* m27v322 */
- ROM_LOAD32_WORD("0351068.u85", 0x0800000, 0x0400000, CRC(52d5395e) SHA1(57b854e516881bc208b48ed82fdef25059e2efab) ) /* m27v322 */
- ROM_LOAD32_WORD("0351068.u86", 0x0000000, 0x0400000, CRC(6b0a7eb3) SHA1(cd99fed52643afa596bfbf4a18deca42043520ef) ) /* m27v322 */
+ ROM_LOAD32_WORD("0351068.u72", 0x0800002, 0x0400000, CRC(ff2ff01d) SHA1(c0d17b3d9907d3876c7a1dbc19b023afcffb2bb1) ) /* m27v322 */
+ ROM_LOAD32_WORD("0351068.u73", 0x0000002, 0x0400000, CRC(4b778a84) SHA1(d11b2aefcaa2ac22fea80faab524f82511b6344a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0351068.u85", 0x0800000, 0x0400000, CRC(52d5395e) SHA1(57b854e516881bc208b48ed82fdef25059e2efab) ) /* m27v322 */
+ ROM_LOAD32_WORD("0351068.u86", 0x0000000, 0x0400000, CRC(6b0a7eb3) SHA1(cd99fed52643afa596bfbf4a18deca42043520ef) ) /* m27v322 */
ROM_END
@@ -1614,8 +1614,8 @@ ROM_END
ROM_START( lovestrk )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0152583.u73", 0x0000002, 0x0400000, BAD_DUMP CRC(421f717d) SHA1(29eaecef6dd389329a8cfdcfa4bf3f90252eb096) ) /* 27v322 */
- ROM_LOAD32_WORD("0152583.u86", 0x0000000, 0x0400000, CRC(c374ee56) SHA1(18b084c32a4dad6dacd3eeaf6ba430053405dbe8) ) /* 27v322 */
+ ROM_LOAD32_WORD("0152583.u73", 0x0000002, 0x0400000, BAD_DUMP CRC(421f717d) SHA1(29eaecef6dd389329a8cfdcfa4bf3f90252eb096) ) /* 27v322 */
+ ROM_LOAD32_WORD("0152583.u86", 0x0000000, 0x0400000, CRC(c374ee56) SHA1(18b084c32a4dad6dacd3eeaf6ba430053405dbe8) ) /* 27v322 */
ROM_END
@@ -1742,10 +1742,10 @@ ROM_END
ROM_START( mystarr )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0151009.u72", 0x0800002, 0x0400000, CRC(4aa6e68b) SHA1(5f015885c15fd206053d23983a38dd1dbb8f89ce) ) /* m27v322 */
- ROM_LOAD32_WORD("0151009.u73", 0x0000002, 0x0400000, CRC(7b8ed0d9) SHA1(6ea4bddedef955513e841ee14ec5e6ded23c1ea7) ) /* m27v322 */
- ROM_LOAD32_WORD("0151009.u85", 0x0800000, 0x0400000, CRC(ea82c5db) SHA1(01db2730b1eec5c9f5c011525459ec72903761cc) ) /* m27v322 */
- ROM_LOAD32_WORD("0151009.u86", 0x0000000, 0x0400000, CRC(8a1475ac) SHA1(c948f0ca991b64d9a07e42fdb346e6df450718f2) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151009.u72", 0x0800002, 0x0400000, CRC(4aa6e68b) SHA1(5f015885c15fd206053d23983a38dd1dbb8f89ce) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151009.u73", 0x0000002, 0x0400000, CRC(7b8ed0d9) SHA1(6ea4bddedef955513e841ee14ec5e6ded23c1ea7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151009.u85", 0x0800000, 0x0400000, CRC(ea82c5db) SHA1(01db2730b1eec5c9f5c011525459ec72903761cc) ) /* m27v322 */
+ ROM_LOAD32_WORD("0151009.u86", 0x0000000, 0x0400000, CRC(8a1475ac) SHA1(c948f0ca991b64d9a07e42fdb346e6df450718f2) ) /* m27v322 */
ROM_END
@@ -1762,10 +1762,10 @@ ROM_END
ROM_START( mysteycmu )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251024.u72", 0x0800002, 0x0400000, CRC(380a868e) SHA1(a1ac6ec1a760f8bbf68b3b86cf5dd4623dc130c7) ) /* m27v322 */
- ROM_LOAD32_WORD("0251024.u73", 0x0000002, 0x0400000, CRC(85ad1a00) SHA1(d4f1d86647eb7724c94c3cfa89d5545a20323e62) ) /* m27v322 */
- ROM_LOAD32_WORD("0251024.u85", 0x0800000, 0x0400000, CRC(ee781c0f) SHA1(7729a55e1d5ff7b8a373dda8a0798374ff60a89b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251024.u86", 0x0000000, 0x0400000, CRC(a7bdbd03) SHA1(0e763933c082163de85c408be91d216d6545e9d7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251024.u72", 0x0800002, 0x0400000, CRC(380a868e) SHA1(a1ac6ec1a760f8bbf68b3b86cf5dd4623dc130c7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251024.u73", 0x0000002, 0x0400000, CRC(85ad1a00) SHA1(d4f1d86647eb7724c94c3cfa89d5545a20323e62) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251024.u85", 0x0800000, 0x0400000, CRC(ee781c0f) SHA1(7729a55e1d5ff7b8a373dda8a0798374ff60a89b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251024.u86", 0x0000000, 0x0400000, CRC(a7bdbd03) SHA1(0e763933c082163de85c408be91d216d6545e9d7) ) /* m27v322 */
ROM_END
@@ -1852,10 +1852,10 @@ ROM_END
ROM_START( parislgtu )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251031.u72", 0x0800002, 0x0400000, CRC(8dc6a0ec) SHA1(855e8f5c6752bfc4ba25116a20ed82dfb4912c07) ) /* m27v322 */
- ROM_LOAD32_WORD("0251031.u73", 0x0000002, 0x0400000, CRC(d0587548) SHA1(30d0021a78ee79c6f66fb27c8c484427a5a2db1b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251031.u85", 0x0800000, 0x0400000, CRC(e7ed0bf4) SHA1(39cb9744462f10fc791d6c604631c1182da9466b) ) /* m27v322 */
- ROM_LOAD32_WORD("0251031.u86", 0x0000000, 0x0400000, CRC(5224e683) SHA1(8b0dbb2fcea4d1a522160d8a6634687c5bad8acd) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251031.u72", 0x0800002, 0x0400000, CRC(8dc6a0ec) SHA1(855e8f5c6752bfc4ba25116a20ed82dfb4912c07) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251031.u73", 0x0000002, 0x0400000, CRC(d0587548) SHA1(30d0021a78ee79c6f66fb27c8c484427a5a2db1b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251031.u85", 0x0800000, 0x0400000, CRC(e7ed0bf4) SHA1(39cb9744462f10fc791d6c604631c1182da9466b) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251031.u86", 0x0000000, 0x0400000, CRC(5224e683) SHA1(8b0dbb2fcea4d1a522160d8a6634687c5bad8acd) ) /* m27v322 */
ROM_END
@@ -2006,16 +2006,16 @@ ROM_END
ROM_START( pwsuper )
ARISTMK6_BIOS
ROM_REGION( 0x3000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0154019.u21", 0x0000000, 0x0400000, CRC(678b0be2) SHA1(16f5460d67a1e897390e0c03b847511f5c14156a) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u11", 0x0000002, 0x0400000, CRC(48f60a2c) SHA1(0d27d544991b3403672250ff79c5bbbf35cdf175) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u22", 0x0800000, 0x0400000, CRC(9dbdefb7) SHA1(445a24233b435e3812747d8376addf969fea5cd2) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u12", 0x0800002, 0x0400000, CRC(5354cff5) SHA1(bf818e53a432aa8e7a2578dbb367be2c5f51bb16) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u23", 0x1000000, 0x0400000, CRC(ae04211a) SHA1(8db4fc936fa6d0e0a372b81f2e9590047522b843) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u13", 0x1000002, 0x0400000, CRC(43b44f26) SHA1(5410eea0a4911a274a794d6b27e369fb98c6edf7) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u24", 0x1800000, 0x0400000, CRC(dbb073f1) SHA1(e3a7f14cabab613453baffde3b592889d11578e7) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u14", 0x1800002, 0x0400000, CRC(a850af7f) SHA1(8d029de0083aad57ddd8b36153214b40cd388d56) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u25", 0x2000000, 0x0400000, CRC(5f9b8ef7) SHA1(f0c954d1f448f2061dbe284c78eddcfcb5afdc7c) ) /* m27v322 */
- ROM_LOAD32_WORD("0154019.u15", 0x2000002, 0x0400000, CRC(2c7fe966) SHA1(42fc364dded0ce079ce4970b1f951c6a0ebf6c51) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u21", 0x0000000, 0x0400000, CRC(678b0be2) SHA1(16f5460d67a1e897390e0c03b847511f5c14156a) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u11", 0x0000002, 0x0400000, CRC(48f60a2c) SHA1(0d27d544991b3403672250ff79c5bbbf35cdf175) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u22", 0x0800000, 0x0400000, CRC(9dbdefb7) SHA1(445a24233b435e3812747d8376addf969fea5cd2) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u12", 0x0800002, 0x0400000, CRC(5354cff5) SHA1(bf818e53a432aa8e7a2578dbb367be2c5f51bb16) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u23", 0x1000000, 0x0400000, CRC(ae04211a) SHA1(8db4fc936fa6d0e0a372b81f2e9590047522b843) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u13", 0x1000002, 0x0400000, CRC(43b44f26) SHA1(5410eea0a4911a274a794d6b27e369fb98c6edf7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u24", 0x1800000, 0x0400000, CRC(dbb073f1) SHA1(e3a7f14cabab613453baffde3b592889d11578e7) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u14", 0x1800002, 0x0400000, CRC(a850af7f) SHA1(8d029de0083aad57ddd8b36153214b40cd388d56) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u25", 0x2000000, 0x0400000, CRC(5f9b8ef7) SHA1(f0c954d1f448f2061dbe284c78eddcfcb5afdc7c) ) /* m27v322 */
+ ROM_LOAD32_WORD("0154019.u15", 0x2000002, 0x0400000, CRC(2c7fe966) SHA1(42fc364dded0ce079ce4970b1f951c6a0ebf6c51) ) /* m27v322 */
ROM_END
@@ -2196,10 +2196,10 @@ ROM_END
ROM_START( sealdeal )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0251029.u72", 0x0800002, 0x0400000, CRC(43ef1218) SHA1(e1d03cd9845ac81a71b5a0471d146addc2f56e0e) ) /* m27v322 */
- ROM_LOAD32_WORD("0251029.u73", 0x0000002, 0x0400000, CRC(383d55a9) SHA1(81bef0ed325ef7208403afa6d7af458c755a4de3) ) /* m27v322 */
- ROM_LOAD32_WORD("0251029.u85", 0x0800000, 0x0400000, CRC(a6327726) SHA1(2c0f02a8d361bcbfc007b9d75a4b7b685aa2b1ac) ) /* m27v322 */
- ROM_LOAD32_WORD("0251029.u86", 0x0000000, 0x0400000, CRC(ea6b666b) SHA1(ad80042770f8e66e7455010b46d81873689f63db) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251029.u72", 0x0800002, 0x0400000, CRC(43ef1218) SHA1(e1d03cd9845ac81a71b5a0471d146addc2f56e0e) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251029.u73", 0x0000002, 0x0400000, CRC(383d55a9) SHA1(81bef0ed325ef7208403afa6d7af458c755a4de3) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251029.u85", 0x0800000, 0x0400000, CRC(a6327726) SHA1(2c0f02a8d361bcbfc007b9d75a4b7b685aa2b1ac) ) /* m27v322 */
+ ROM_LOAD32_WORD("0251029.u86", 0x0000000, 0x0400000, CRC(ea6b666b) SHA1(ad80042770f8e66e7455010b46d81873689f63db) ) /* m27v322 */
ROM_END
@@ -2292,10 +2292,10 @@ ROM_END
ROM_START( stardrftu )
ARISTMK6_BIOS
ROM_REGION( 0x2000000, "game_rom", ROMREGION_ERASEFF)
- ROM_LOAD32_WORD("0451341.u72", 0x0800002, 0x0400000, CRC(dc7a30c1) SHA1(8f24c18efd6171cda7ca841d3b275937e35e2be8) ) /* m27v322 */
- ROM_LOAD32_WORD("0451341.u73", 0x0000002, 0x0400000, CRC(3e59b84f) SHA1(3148d48df74c35681759a234d7aa746cbb0afb0e) ) /* m27v322 */
- ROM_LOAD32_WORD("0451341.u85", 0x0800000, 0x0400000, CRC(689ded33) SHA1(5d5b744321313c4618ecf319827c778be646245f) ) /* m27v322 */
- ROM_LOAD32_WORD("0451341.u86", 0x0000000, 0x0400000, CRC(73023e64) SHA1(4d2d586a1e91ac5bac379994973dffcf9f3a3293) ) /* m27v322 */
+ ROM_LOAD32_WORD("0451341.u72", 0x0800002, 0x0400000, CRC(dc7a30c1) SHA1(8f24c18efd6171cda7ca841d3b275937e35e2be8) ) /* m27v322 */
+ ROM_LOAD32_WORD("0451341.u73", 0x0000002, 0x0400000, CRC(3e59b84f) SHA1(3148d48df74c35681759a234d7aa746cbb0afb0e) ) /* m27v322 */
+ ROM_LOAD32_WORD("0451341.u85", 0x0800000, 0x0400000, CRC(689ded33) SHA1(5d5b744321313c4618ecf319827c778be646245f) ) /* m27v322 */
+ ROM_LOAD32_WORD("0451341.u86", 0x0000000, 0x0400000, CRC(73023e64) SHA1(4d2d586a1e91ac5bac379994973dffcf9f3a3293) ) /* m27v322 */
ROM_END
@@ -2784,13 +2784,13 @@ ROM_END
GAME( 2000, aristmk6, 0, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Aristocrat MK6 System Software", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_IS_BIOS_ROOT)
// Dates listed below are for the combination (reel layout), not release dates
-GAME( 2004, 5drag, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons (20161011, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744, C - 14/01/04
-GAME( 2004, 5dragsp, 5drag, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons (20161011, NSW/ACT, Show Program)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744, C - 14/01/04
-GAME( 2007, 5dragce, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons - Cash Express (0152309, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // US211, A - 01/09/07
-GAME( 2007, 5koipp, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Koi - Power Pay (10250711, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744/2, C - 25/10/07
+GAME( 2004, 5drag, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons (20161011, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744, C - 14/01/04
+GAME( 2004, 5dragsp, 5drag, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons (20161011, NSW/ACT, Show Program)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744, C - 14/01/04
+GAME( 2007, 5dragce, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Dragons - Cash Express (0152309, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // US211, A - 01/09/07
+GAME( 2007, 5koipp, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "5 Koi - Power Pay (10250711, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 744/2, C - 25/10/07
GAME( 2002, 50lions, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "50 Lions (10120511, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 717, A - 11/10/02
GAME( 2003, 50lionsm, 50lions, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "50 Lions (10156111, Malaysia)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 717, D - 20/10/03
-GAME( 2012, 50lionrr, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "50 Lions - Roaring Riches (20301311, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 1049, B - 20/08/12
+GAME( 2012, 50lionrr, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "50 Lions - Roaring Riches (20301311, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 1049, B - 20/08/12
GAME( 2006, 100lions, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "100 Lions (10219211, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 717/4, B - 13/06/06
GAME( 2005, adonisa6, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Adonis (0151178, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // US168, A - 05/26/05
GAME( 2001, adustcm, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "African Dusk - Mr. Cashman (20006711, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 665/1, B- 13/07/01
@@ -2820,7 +2820,7 @@ GAME( 2005, brazil, aristmk6, aristmk6, aristmk6, driver_device, 0, RO
GAME( 2004, bucaneer, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Buccaneer (10173011, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 765, A - 05/04/04
GAME( 2010, buckstop, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "The Buck Stops Here (10294311, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 897/1, A - 22/07/10
GAME( 2006, buffalo, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Buffalo (10217811, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 806, E - 06/10/06
-GAME( 200?, buffalou, buffalo, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Buffalo (0252636, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // MV4328, (no data)
+GAME( 200?, buffalou, buffalo, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Buffalo (0252636, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // MV4328, (no data)
GAME( 2005, bmbugs, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Bumble Bugs (0351180, US)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // US166, A - 05/13/05
GAME( 2001, bushrngr, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Bushranger (10006111, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 673, A - 18/04/01
GAME( 2007, cactusco, aristmk6, aristmk6, aristmk6, driver_device, 0, ROT0, "Aristocrat", "Cactus Corral (10237711, NSW/ACT)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // 818, D - 24/07/07
diff --git a/src/mame/drivers/atarigx2.cpp b/src/mame/drivers/atarigx2.cpp
index 29ec3b5e588..e35dc22e5cb 100644
--- a/src/mame/drivers/atarigx2.cpp
+++ b/src/mame/drivers/atarigx2.cpp
@@ -5,7 +5,7 @@
Atari GX2 hardware
driver by Aaron Giles
-
+
Moto Frenzy protection reverse engineered by:
Morten Shearman Kirkegaard, Samuel Neves, Peter Wilhelmsen
@@ -1181,7 +1181,7 @@ READ32_MEMBER(atarigx2_state::atarigx2_protection_r)
READ32_MEMBER( atarigx2_state::rrreveng_prot_r )
{
- return 0;
+ return 0;
}
@@ -1468,7 +1468,7 @@ static MACHINE_CONFIG_START( atarigx2, atarigx2_state )
MCFG_MACHINE_RESET_OVERRIDE(atarigx2_state,atarigx2)
- MCFG_DEVICE_ADD("xga", ATARI_XGA, 0);
+ MCFG_DEVICE_ADD("xga", ATARI_XGA, 0);
MCFG_ATARI_EEPROM_2816_ADD("eeprom")
@@ -2220,7 +2220,7 @@ ROM_END
DRIVER_INIT_MEMBER(atarigx2_state,spclords)
{
m_playfield_base = 0x000;
- m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atarigx2_state::atarigx2_protection_r),this), write32_delegate(FUNC(atarigx2_state::atarigx2_protection_w),this));
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atarigx2_state::atarigx2_protection_r),this), write32_delegate(FUNC(atarigx2_state::atarigx2_protection_w),this));
}
@@ -2249,14 +2249,14 @@ XMEM=68.A23*E.A22*!E.A21*68.A20 = 1101 xxxx = d0
+68.A23*E.A22*!E.A21*!68.A20*68.A19 = 1100 1xxx = c80000-cfffff
+!68.A23*!E.A22*!E.A21 = 000x xxxx = 000000-1fffff
*/
- m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atari_xga_device::read),&(*m_xga)), write32_delegate(FUNC(atari_xga_device::write),&(*m_xga)));
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atari_xga_device::read),&(*m_xga)), write32_delegate(FUNC(atari_xga_device::write),&(*m_xga)));
}
DRIVER_INIT_MEMBER(atarigx2_state,rrreveng)
{
m_playfield_base = 0x000;
- m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atarigx2_state::atarigx2_protection_r),this), write32_delegate(FUNC(atarigx2_state::atarigx2_protection_w),this));
+ m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xca0000, 0xca0fff, read32_delegate(FUNC(atarigx2_state::atarigx2_protection_r),this), write32_delegate(FUNC(atarigx2_state::atarigx2_protection_w),this));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xca0fc0, 0xca0fc3, read32_delegate(FUNC(atarigx2_state::rrreveng_prot_r),this));
}
diff --git a/src/mame/drivers/atlantis.cpp b/src/mame/drivers/atlantis.cpp
index e18abf06d1e..60173f3ce22 100644
--- a/src/mame/drivers/atlantis.cpp
+++ b/src/mame/drivers/atlantis.cpp
@@ -76,7 +76,7 @@
#define LOG_RTC (0)
#define LOG_RED (0)
#define LOG_PORT (0)
-#define LOG_IRQ (0)
+#define LOG_IRQ (0)
class atlantis_state : public driver_device
{
@@ -810,7 +810,7 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state )
MCFG_PCI9050_SET_MAP(3, map3)
MCFG_PCI9050_USER_OUTPUT_CALLBACK(DEVWRITE32(":", atlantis_state, user_io_output))
MCFG_PCI9050_USER_INPUT_CALLBACK(DEVREAD32(":", atlantis_state, user_io_input))
-
+
MCFG_NVRAM_ADD_0FILL("rtc")
MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x03, 0x0)
diff --git a/src/mame/drivers/bfcobra.cpp b/src/mame/drivers/bfcobra.cpp
index ae57eaed23e..3523fa6e492 100644
--- a/src/mame/drivers/bfcobra.cpp
+++ b/src/mame/drivers/bfcobra.cpp
@@ -1273,7 +1273,7 @@ ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x53, 0x53) AM_DEVWRITE("ramdac", ramdac_device, index_r_w)
ADDRESS_MAP_END
-
+
static ADDRESS_MAP_START( ramdac_map, AS_0, 8, bfcobra_state )
AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac", ramdac_device, ramdac_pal_r, ramdac_rgb666_w)
ADDRESS_MAP_END
diff --git a/src/mame/drivers/bloodbro.cpp b/src/mame/drivers/bloodbro.cpp
index 90c1650d460..354d9068285 100644
--- a/src/mame/drivers/bloodbro.cpp
+++ b/src/mame/drivers/bloodbro.cpp
@@ -520,7 +520,7 @@ static MACHINE_CONFIG_DERIVED( weststry, bloodbro )
MCFG_PALETTE_ENTRIES(1024)
MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)
- // Bootleg video hardware is non-Seibu
+ // Bootleg video hardware is non-Seibu
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(bloodbro_state, screen_update_weststry)
MCFG_DEVICE_REMOVE("crtc")
diff --git a/src/mame/drivers/cclimber.cpp b/src/mame/drivers/cclimber.cpp
index 9c7e887820c..0bad5858b9d 100644
--- a/src/mame/drivers/cclimber.cpp
+++ b/src/mame/drivers/cclimber.cpp
@@ -1937,23 +1937,23 @@ ROM_END
*/
ROM_START( rpatrol )
- ROM_REGION( 0x6000, "maincpu", 0 ) // encrypted
- ROM_LOAD( "1.1h", 0x000000, 0x001000, CRC(065197f0) SHA1(6e482967949bdb126b7ac484abb84c24f4687a3a) )
- ROM_LOAD( "2.1f", 0x001000, 0x001000, CRC(3614b820) SHA1(01966e6ae2ead93797d402bc8d789458b0bdcd75) )
- ROM_LOAD( "3.1d", 0x002000, 0x001000, CRC(ba428bbf) SHA1(ac4cd6ac0adab79bc2cfec3ec2683291c5f0f376) )
- ROM_LOAD( "4.1c", 0x003000, 0x001000, CRC(41497a94) SHA1(7550e74f93c1fd1d5e7fc70c4a2cd2d1b4c22ce5) )
- ROM_LOAD( "5.1a", 0x004000, 0x001000, CRC(e20ee7e7) SHA1(53f7ec5c6805043d3e8f014ade2480cd6dbd94db) )
-
+ ROM_REGION( 0x6000, "maincpu", 0 ) // encrypted
+ ROM_LOAD( "1.1h", 0x000000, 0x001000, CRC(065197f0) SHA1(6e482967949bdb126b7ac484abb84c24f4687a3a) )
+ ROM_LOAD( "2.1f", 0x001000, 0x001000, CRC(3614b820) SHA1(01966e6ae2ead93797d402bc8d789458b0bdcd75) )
+ ROM_LOAD( "3.1d", 0x002000, 0x001000, CRC(ba428bbf) SHA1(ac4cd6ac0adab79bc2cfec3ec2683291c5f0f376) )
+ ROM_LOAD( "4.1c", 0x003000, 0x001000, CRC(41497a94) SHA1(7550e74f93c1fd1d5e7fc70c4a2cd2d1b4c22ce5) )
+ ROM_LOAD( "5.1a", 0x004000, 0x001000, CRC(e20ee7e7) SHA1(53f7ec5c6805043d3e8f014ade2480cd6dbd94db) )
+
ROM_REGION( 0x4000, "gfx1", 0 )
- ROM_LOAD( "6.6l.2732", 0x000000, 0x000800, CRC(b38d8aca) SHA1(b93aa0010b0c0ab23284188a881d4a9bb0fd4582) )
- ROM_CONTINUE( 0x001000, 0x000800 )
- ROM_LOAD( "7.6p.2732", 0x002000, 0x000800, CRC(bc2bddf9) SHA1(4057fc535b1a2db943f893290afe9bfd865ac84b) )
- ROM_CONTINUE( 0x003000, 0x000800 )
+ ROM_LOAD( "6.6l.2732", 0x000000, 0x000800, CRC(b38d8aca) SHA1(b93aa0010b0c0ab23284188a881d4a9bb0fd4582) )
+ ROM_CONTINUE( 0x001000, 0x000800 )
+ ROM_LOAD( "7.6p.2732", 0x002000, 0x000800, CRC(bc2bddf9) SHA1(4057fc535b1a2db943f893290afe9bfd865ac84b) )
+ ROM_CONTINUE( 0x003000, 0x000800 )
ROM_REGION( 0x1000, "gfx2", 0 )
- ROM_LOAD( "9.2t", 0x000000, 0x000800, CRC(d373fc48) SHA1(f06017190955d7458ac652b37c47cee033bc5498) )
- ROM_LOAD( "8.2s", 0x000800, 0x000800, CRC(59747c31) SHA1(92acf07489f3e17f0c1769a0df15b6ddb117830f) )
-
+ ROM_LOAD( "9.2t", 0x000000, 0x000800, CRC(d373fc48) SHA1(f06017190955d7458ac652b37c47cee033bc5498) )
+ ROM_LOAD( "8.2s", 0x000800, 0x000800, CRC(59747c31) SHA1(92acf07489f3e17f0c1769a0df15b6ddb117830f) )
+
ROM_REGION( 0x0060, "proms", 0 )
// probably matches with existing sets
ROM_LOAD( "bprom1.9n", 0x0000, 0x0020, BAD_DUMP CRC(f9a2383b) SHA1(4d88c177740efdb27708474c9ee0fcdca5a78c36) )
diff --git a/src/mame/drivers/chihiro.cpp b/src/mame/drivers/chihiro.cpp
index 0c108510c56..e57641c9630 100644
--- a/src/mame/drivers/chihiro.cpp
+++ b/src/mame/drivers/chihiro.cpp
@@ -646,7 +646,7 @@ static const struct {
} hacks[3] = { { "chihiro", { { 0x6a79f/*3f79f*/, 0x01 }, { 0x6a7a0/*3f7a0*/, 0x00 }, { 0x6b575/*40575*/, 0x00 }, { 0x6b576/*40576*/, 0x00 }, { 0x6b5af/*405af*/, 0x75 }, { 0x6b78a/*4078a*/, 0x75 }, { 0x6b7ca/*407ca*/, 0x00 }, { 0x6b7b8/*407b8*/, 0x00 }, { 0x8f5b2, 0x75 }, { 0x79a9e/*2ea9e*/, 0x74 }, { 0x79b80/*2eb80*/, 0xeb }, { 0x79b97/*2eb97*/, 0x74 }, { 0, 0 } } },
{ "outr2", { { 0x12e4cf, 0x01 }, { 0x12e4d0, 0x00 }, { 0x4793e, 0x01 }, { 0x4793f, 0x00 }, { 0x47aa3, 0x01 }, { 0x47aa4, 0x00 }, { 0x14f2b6, 0x84 }, { 0x14f2d1, 0x75 }, { 0x8732f, 0x7d }, { 0x87384, 0x7d }, { 0x87388, 0xeb }, { 0, 0 } } },
{ "crtaxihr", { { 0x121dce/*f6dce*/, 0xeb }, { 0x121deb/*f6deb*/, 0xeb }, { 0x121fa0/*f6fa0*/, 0xeb }, { 0x14ada5/*11fda5*/, 0x90 }, { 0x14ada6/*11fda6*/, 0x90 }, /*{ 0x8d0bc 620bc , 0xeb },*/ { 0, 0 } } }
- };
+ };
void chihiro_state::hack_usb()
{
diff --git a/src/mame/drivers/deco_ld.cpp b/src/mame/drivers/deco_ld.cpp
index 7101b91cb3b..4ae33ed2bda 100644
--- a/src/mame/drivers/deco_ld.cpp
+++ b/src/mame/drivers/deco_ld.cpp
@@ -468,7 +468,7 @@ static MACHINE_CONFIG_START( rblaster, deco_ld_state )
// MCFG_QUANTUM_TIME(attotime::from_hz(6000))
- MCFG_LASERDISC_LDP1000_ADD("laserdisc")
+ MCFG_LASERDISC_LDP1000_ADD("laserdisc")
MCFG_LASERDISC_OVERLAY_DRIVER(256, 256, deco_ld_state, screen_update_rblaster)
//MCFG_LASERDISC_OVERLAY_CLIP(0, 256-1, 8, 240-1)
MCFG_LASERDISC_OVERLAY_PALETTE("palette")
@@ -482,7 +482,7 @@ static MACHINE_CONFIG_START( rblaster, deco_ld_state )
//MCFG_DEVICE_ADD("acia", ACIA6850, 0)
//MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("laserdisc", sony_ldp1000_device, write))
//MCFG_ACIA6850_RXD_HANDLER(DEVREADLINE("laserdisc", sony_ldp1000_device, read))
-
+
/* sound hardware */
/* TODO: mixing */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
diff --git a/src/mame/drivers/divebomb.cpp b/src/mame/drivers/divebomb.cpp
index 65249b6e6ba..e87e3c6d08d 100755
--- a/src/mame/drivers/divebomb.cpp
+++ b/src/mame/drivers/divebomb.cpp
@@ -3,14 +3,14 @@
/***************************************************************************
Kyuukoukabakugekitai - Dive Bomber Squad
-
+
(C) Konami 1989
****************************************************************************
-
+
PCB Layout
----------
-
+
GX840 PWB35165
|--------------------------------------------------------------------------|
| |
@@ -40,22 +40,22 @@
| U22 SN76489 VR |
| |
|--------------------------------------------------------------------------|
-
+
Notes:
There are numerous wire modificationss connecting pins of U15-U18 to
various other components on the PCB
-
+
MB81C86 - 64kx4 SRAM
HM6116AP - 2kx8 SRAM
8464A - 8kx8 SRAM
MN53060KGB - Panasonic CMOS gate array (6016 gates)
051316 - Konami PSAC
CN1/CN2 - ROM board connectors
-
-
+
+
ROM Board
---------
-
+
GX840 PWB451716
|--------------------------|
| |
@@ -68,15 +68,15 @@
| U41 U5 U9 |
| |
|--------------------------|
-
+
Notes:
All ROMs are 27512 EPROMs
-
+
To do:
* Verify layer alignment
* Deduce unknown DIP switch settings
-
+
To verify against original HW:
* Game has no sprites when you reach level 4 and becomes unplayable
* Game often hangs (sprites no longer animate, screen scrolls/rotates endlessly) due to a communication breakdown
@@ -132,44 +132,44 @@ ADDRESS_MAP_END
READ8_MEMBER(divebomb_state::fgcpu_spr_comm_r)
{
- has_fromsprite = false;
- update_irqs();
- return from_sprite;
+ has_fromsprite = false;
+ update_irqs();
+ return from_sprite;
}
WRITE8_MEMBER(divebomb_state::fgcpu_spr_comm_w)
{
- m_spritecpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
- to_spritecpu = data;
+ m_spritecpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
+ to_spritecpu = data;
}
READ8_MEMBER(divebomb_state::fgcpu_roz_comm_r)
{
- has_fromroz = false;
- update_irqs();
- return from_roz;
+ has_fromroz = false;
+ update_irqs();
+ return from_roz;
}
WRITE8_MEMBER(divebomb_state::fgcpu_roz_comm_w)
{
- m_rozcpucpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
- to_rozcpu = data;
+ m_rozcpucpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
+ to_rozcpu = data;
}
READ8_MEMBER(divebomb_state::fgcpu_comm_flags_r)
{
- UINT8 result = 0;
-
- if (has_fromroz)
- result |= 1;
- if (has_fromsprite)
- result |= 2;
-
- return result;
+ UINT8 result = 0;
+
+ if (has_fromroz)
+ result |= 1;
+ if (has_fromsprite)
+ result |= 2;
+
+ return result;
}
@@ -183,7 +183,7 @@ READ8_MEMBER(divebomb_state::fgcpu_comm_flags_r)
static ADDRESS_MAP_START( divebomb_spritecpu_map, AS_PROGRAM, 8, divebomb_state )
AM_RANGE(0x0000, 0x7fff) AM_ROM
AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("spriteram")
- AM_RANGE(0xc800, 0xdfff) AM_WRITENOP
+ AM_RANGE(0xc800, 0xdfff) AM_WRITENOP
AM_RANGE(0xe000, 0xffff) AM_RAM
ADDRESS_MAP_END
@@ -197,23 +197,23 @@ ADDRESS_MAP_END
READ8_MEMBER(divebomb_state::spritecpu_comm_r)
{
- m_spritecpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
- return to_spritecpu;
+ m_spritecpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
+ return to_spritecpu;
}
WRITE8_MEMBER(divebomb_state::spritecpu_comm_w)
{
- from_sprite = data;
- has_fromsprite = true;
- update_irqs();
+ from_sprite = data;
+ has_fromsprite = true;
+ update_irqs();
}
WRITE8_MEMBER(divebomb_state::spritecpu_port00_w)
{
- // Written with 0x00 on reset
- // Written with 0x34 7 times in succession on occasion (see PC:0x00E3)
+ // Written with 0x00 on reset
+ // Written with 0x34 7 times in succession on occasion (see PC:0x00E3)
}
@@ -226,7 +226,7 @@ WRITE8_MEMBER(divebomb_state::spritecpu_port00_w)
static ADDRESS_MAP_START( divebomb_rozcpu_map, AS_PROGRAM, 8, divebomb_state )
AM_RANGE(0x0000, 0x7fff) AM_ROM
- AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
+ AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_DEVREADWRITE("k051316_1", k051316_device, read, write)
AM_RANGE(0xd000, 0xd7ff) AM_RAM AM_DEVREADWRITE("k051316_2", k051316_device, read, write)
AM_RANGE(0xe000, 0xffff) AM_RAM
@@ -249,26 +249,26 @@ ADDRESS_MAP_END
WRITE8_MEMBER(divebomb_state::rozcpu_bank_w)
{
- UINT32 bank = BITSWAP8(data, 4, 5, 6, 7, 3, 2, 1, 0) >> 4;
- m_bank1->set_entry(bank);
+ UINT32 bank = BITSWAP8(data, 4, 5, 6, 7, 3, 2, 1, 0) >> 4;
+ m_bank1->set_entry(bank);
- if (data & 0x0f)
- logerror("rozcpu_bank_w %02x\n", data);
+ if (data & 0x0f)
+ logerror("rozcpu_bank_w %02x\n", data);
}
READ8_MEMBER(divebomb_state::rozcpu_comm_r)
{
- m_rozcpucpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
- return to_rozcpu;
+ m_rozcpucpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
+ return to_rozcpu;
}
WRITE8_MEMBER(divebomb_state::rozcpu_comm_w)
{
- from_roz = data;
- has_fromroz = true;
- update_irqs();
+ from_roz = data;
+ has_fromroz = true;
+ update_irqs();
}
@@ -281,10 +281,10 @@ WRITE8_MEMBER(divebomb_state::rozcpu_comm_w)
void divebomb_state::update_irqs()
{
- if (has_fromsprite || has_fromroz)
- m_fgcpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
- else
- m_fgcpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
+ if (has_fromsprite || has_fromroz)
+ m_fgcpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
+ else
+ m_fgcpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
}
@@ -328,9 +328,9 @@ static INPUT_PORTS_START( divebomb )
PORT_DIPSETTING( 0x02, "5" )
PORT_DIPSETTING( 0x01, "7" )
PORT_DIPSETTING( 0x00, "9" )
- PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3")
- PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
- PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
+ PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3")
+ PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
+ PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@@ -348,24 +348,24 @@ static INPUT_PORTS_START( divebomb )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW3")
- PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW3:1" )
- PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW3:2" )
- PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW3:3" )
- PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW3:4" )
- PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW3:5" )
- PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW3:6" )
- PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW3:7" )
- PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW3:8" )
-
- PORT_START("DSW4")
- PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW4:1" )
- PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW4:2" )
- PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW4:3" )
- PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW4:4" )
- PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW4:5" )
- PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW4:6" )
- PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW4:7" )
- PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW4:8" )
+ PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW3:1" )
+ PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW3:2" )
+ PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW3:3" )
+ PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW3:4" )
+ PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW3:5" )
+ PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW3:6" )
+ PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW3:7" )
+ PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW3:8" )
+
+ PORT_START("DSW4")
+ PORT_DIPUNUSED_DIPLOC( 0x01, 0x01, "SW4:1" )
+ PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW4:2" )
+ PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW4:3" )
+ PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW4:4" )
+ PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW4:5" )
+ PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW4:6" )
+ PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW4:7" )
+ PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW4:8" )
PORT_START("IN0")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
@@ -388,14 +388,14 @@ static INPUT_PORTS_START( divebomb )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
PORT_START("SYSTEM")
- PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
- PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
@@ -476,10 +476,10 @@ static MACHINE_CONFIG_START( divebomb, divebomb_state )
MCFG_K051316_OFFSETS(-88, -16)
MCFG_K051316_CB(divebomb_state, zoom_callback_2)
- MCFG_MACHINE_START_OVERRIDE(divebomb_state, divebomb)
- MCFG_MACHINE_RESET_OVERRIDE(divebomb_state, divebomb)
+ MCFG_MACHINE_START_OVERRIDE(divebomb_state, divebomb)
+ MCFG_MACHINE_RESET_OVERRIDE(divebomb_state, divebomb)
- MCFG_VIDEO_START_OVERRIDE(divebomb_state, divebomb)
+ MCFG_VIDEO_START_OVERRIDE(divebomb_state, divebomb)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@@ -498,7 +498,7 @@ static MACHINE_CONFIG_START( divebomb, divebomb_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
- // All frequencies unverified
+ // All frequencies unverified
MCFG_SOUND_ADD("sn0", SN76489, XTAL1/8)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.15)
MCFG_SOUND_ADD("sn1", SN76489, XTAL1/8)
@@ -524,7 +524,7 @@ MACHINE_CONFIG_END
ROM_START( divebomb )
ROM_REGION( 0x08000, "fgcpu", 0 )
ROM_LOAD( "U20.27256", 0x00000, 0x08000, CRC(89a30c82) SHA1(ecb3dcc00192b9646dab55ec6c102ab1d2e403e8) )
-
+
ROM_REGION( 0x08000, "spritecpu", 0 )
ROM_LOAD( "U21.27256", 0x00000, 0x08000, CRC(3896d3f6) SHA1(86d10c907bf00977656d8fa426b2f1ac211acdb3) )
@@ -565,17 +565,17 @@ ROM_START( divebomb )
ROM_LOAD( "u36.MB7122.bin", 0x400, 0x400, CRC(0c1ecdb5) SHA1(4ba9e283c747d6a760fe2e0a8b2bfdfcc55a3969) )
ROM_LOAD( "u37.MB7122.bin", 0x000, 0x400, CRC(55c17465) SHA1(153e99a09604467ddd8c641d60c5f1b8d9a205b4) )
- ROM_REGION( 0xc00, "k051316_1_pr", 0 ) // front roz ( k051316_1 )
- // looks like banks 0,1,2 are valid
- ROM_LOAD( "u29.MB7122.bin", 0x000, 0x400, CRC(8b3d60d2) SHA1(a9ac4d3dd5e72522717dd18c32d3f88b75bb077c) ) // the last 0x100 block is invalid (copy of data in u33)
- ROM_LOAD( "u30.MB7122.bin", 0x400, 0x400, CRC(0aeb1a88) SHA1(7b00e85ced210a5f7dfc100c15baa9e1735c7c80) ) // the last 0x100 block is empty
- ROM_LOAD( "u31.MB7122.bin", 0x800, 0x400, CRC(75cf5f3d) SHA1(ec02b99ab65e561596b773918569b28313f21835) ) // the last 0x100 block is invalid (copy of data in u33)
+ ROM_REGION( 0xc00, "k051316_1_pr", 0 ) // front roz ( k051316_1 )
+ // looks like banks 0,1,2 are valid
+ ROM_LOAD( "u29.MB7122.bin", 0x000, 0x400, CRC(8b3d60d2) SHA1(a9ac4d3dd5e72522717dd18c32d3f88b75bb077c) ) // the last 0x100 block is invalid (copy of data in u33)
+ ROM_LOAD( "u30.MB7122.bin", 0x400, 0x400, CRC(0aeb1a88) SHA1(7b00e85ced210a5f7dfc100c15baa9e1735c7c80) ) // the last 0x100 block is empty
+ ROM_LOAD( "u31.MB7122.bin", 0x800, 0x400, CRC(75cf5f3d) SHA1(ec02b99ab65e561596b773918569b28313f21835) ) // the last 0x100 block is invalid (copy of data in u33)
ROM_REGION( 0xc00, "k051316_2_pr", 0 ) // back roz ( k051316_2 )
// 4 valid palettes but our code is only using 1
- ROM_LOAD( "u34.MB7122.bin", 0x000, 0x400, CRC(e0e2d93b) SHA1(9043929520abde15727e9333c153cf97104c9003) )
- ROM_LOAD( "u33.MB7122.bin", 0x400, 0x400, CRC(4df75f4f) SHA1(0157d6e268cdd797622c712648eb2e88214b12d9) )
- ROM_LOAD( "u32.MB7122.bin", 0x800, 0x400, CRC(e2e4b443) SHA1(e97a4e2988e29f992c5dec6f817a783b14535742) )
+ ROM_LOAD( "u34.MB7122.bin", 0x000, 0x400, CRC(e0e2d93b) SHA1(9043929520abde15727e9333c153cf97104c9003) )
+ ROM_LOAD( "u33.MB7122.bin", 0x400, 0x400, CRC(4df75f4f) SHA1(0157d6e268cdd797622c712648eb2e88214b12d9) )
+ ROM_LOAD( "u32.MB7122.bin", 0x800, 0x400, CRC(e2e4b443) SHA1(e97a4e2988e29f992c5dec6f817a783b14535742) )
ROM_REGION( 0x300, "spr_proms", 0 ) // sprite layer palette
ROM_LOAD( "u83.MB7114.bin", 0x000, 0x100, CRC(d216110d) SHA1(3de935dbf876f82864b8b69049c8681101619411) )
@@ -593,30 +593,30 @@ ROM_END
MACHINE_START_MEMBER(divebomb_state, divebomb)
{
- m_bank1->configure_entries(0, 16, memregion("rozcpudata")->base(), 0x4000);
-
- save_item(NAME(roz1_enable));
- save_item(NAME(roz2_enable));
- save_item(NAME(roz1_wrap));
- save_item(NAME(roz2_wrap));
- save_item(NAME(to_spritecpu));
- save_item(NAME(to_rozcpu));
- save_item(NAME(has_fromsprite));
- save_item(NAME(has_fromroz));
- save_item(NAME(from_sprite));
- save_item(NAME(from_roz));
- save_item(NAME(roz_pal));
+ m_bank1->configure_entries(0, 16, memregion("rozcpudata")->base(), 0x4000);
+
+ save_item(NAME(roz1_enable));
+ save_item(NAME(roz2_enable));
+ save_item(NAME(roz1_wrap));
+ save_item(NAME(roz2_wrap));
+ save_item(NAME(to_spritecpu));
+ save_item(NAME(to_rozcpu));
+ save_item(NAME(has_fromsprite));
+ save_item(NAME(has_fromroz));
+ save_item(NAME(from_sprite));
+ save_item(NAME(from_roz));
+ save_item(NAME(roz_pal));
}
MACHINE_RESET_MEMBER(divebomb_state, divebomb)
{
- roz1_enable = false;
- roz2_enable = false;
- roz1_wrap = false;
- roz2_wrap = false;
- has_fromsprite = false;
- has_fromroz = false;
+ roz1_enable = false;
+ roz2_enable = false;
+ roz1_wrap = false;
+ roz2_wrap = false;
+ has_fromsprite = false;
+ has_fromroz = false;
}
diff --git a/src/mame/drivers/dlair.cpp b/src/mame/drivers/dlair.cpp
index c9932c76271..7b6328cc855 100644
--- a/src/mame/drivers/dlair.cpp
+++ b/src/mame/drivers/dlair.cpp
@@ -473,7 +473,7 @@ Address in ROM:
*
*************************************/
- // TODO: DIPs still needs work
+ // TODO: DIPs still needs work
static INPUT_PORTS_START( dlair )
PORT_START("DSW1")
PORT_DIPNAME( 0x01, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("A:1")
@@ -500,7 +500,7 @@ static INPUT_PORTS_START( dlair )
PORT_START("DSW2")
PORT_DIPNAME( 0x01, 0x01, "Sound every 8 attracts" ) PORT_DIPLOCATION("B:1")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x01, DEF_STR( On ) )
+ PORT_DIPSETTING( 0x01, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("B:2")
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@@ -652,7 +652,7 @@ static INPUT_PORTS_START( spaceace )
PORT_DIPSETTING( 0x20, "1 out of eight times" )
PORT_DIPUNUSED_DIPLOC( 0x40, IP_ACTIVE_HIGH, "A:7")
PORT_DIPUNUSED_DIPLOC( 0x80, IP_ACTIVE_HIGH, "A:8")
-
+
PORT_MODIFY("DSW2")
PORT_DIPNAME( 0x01, 0x01, "LD Player" ) PORT_DIPLOCATION("B:1")
PORT_DIPSETTING( 0x00, "LD-PR7820" )
@@ -663,7 +663,7 @@ static INPUT_PORTS_START( spaceace )
PORT_DIPNAME( 0x10, 0x00, DEF_STR( Free_Play ) ) PORT_DIPLOCATION("B:5")
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
- PORT_DIPNAME( 0x20, 0x00, "Unlimited Lives" ) PORT_DIPLOCATION("B:6")
+ PORT_DIPNAME( 0x20, 0x00, "Unlimited Lives" ) PORT_DIPLOCATION("B:6")
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x20, DEF_STR( Yes ) )
PORT_DIPNAME( 0x40, 0x00, "Enable Frame Display" ) PORT_DIPLOCATION("B:7") // ?
diff --git a/src/mame/drivers/esh.cpp b/src/mame/drivers/esh.cpp
index 65940aae7fa..f31fda60211 100644
--- a/src/mame/drivers/esh.cpp
+++ b/src/mame/drivers/esh.cpp
@@ -15,9 +15,9 @@ Notes:
Todo:
- LD TROUBLE appears at POST. Sync/timing issue?
- - Performance spike after some time of gameplay, CPU comms gets corrupt?
- - How to init NVRAM? Current defaults definitely aren't.
- - Wrong overlay colors;
+ - Performance spike after some time of gameplay, CPU comms gets corrupt?
+ - How to init NVRAM? Current defaults definitely aren't.
+ - Wrong overlay colors;
- Convert to tilemaps (see next ToDo for feasibility).
- Rumor has it there's an analog beep hanging off 0xf5? Implement it and finish off 0xf5 bits.
- NVRAM range 0xe000-0xe800 might be too large. It doesn't seem to write past 0xe600...
@@ -85,7 +85,7 @@ UINT32 esh_state::screen_update_esh(screen_device &screen, bitmap_rgb32 &bitmap,
/* clear */
bitmap.fill(0, cliprect);
-
+
/* Draw tiles */
for (charx = 0; charx < 32; charx++)
{
@@ -98,26 +98,26 @@ UINT32 esh_state::screen_update_esh(screen_device &screen, bitmap_rgb32 &bitmap,
bool blinkLine = bool((m_tile_control_ram[current_screen_character] & 0x40) >> 6);
bool blinkChar = bool((m_tile_control_ram[current_screen_character] & 0x80) >> 7);
-
+
// TODO: blink timing
if(blinkChar == true && m_screen->frame_number() & 8)
{
if(trans_mask == 0)
continue;
-
+
for(int yi=0;yi<8;yi++)
for(int xi=0;xi<8;xi++)
bitmap.pix32(yi+chary*8, xi+charx*8) = m_palette->pen(palIndex * 8 + pal_bank * 0x100);
continue;
}
-
+
if(blinkLine == true && m_screen->frame_number() & 8)
gfx = m_gfxdecode->gfx(1);
else
gfx = m_gfxdecode->gfx(0);
-
-
+
+
gfx->transpen(bitmap,cliprect,
m_tile_ram[current_screen_character] + (0x100 * tileOffs),
palIndex + pal_bank,
@@ -193,9 +193,9 @@ WRITE8_MEMBER(esh_state::nmi_line_w)
// 0 -> 1 transition enables this, else disabled?
m_nmi_enable = (data & 1) == 1;
//if (data == 0x00)
- // m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
+ // m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
//if (data == 0x01)
- // m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
+ // m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
if (data & 0xfe)
logerror("NMI line unknown bit set %02x\n",data);
@@ -305,7 +305,7 @@ PALETTE_INIT_MEMBER(esh_state, esh)
bit2 = (color_prom[i+0x100] >> 6) & 0x01;
b = 0x21 * bit0 + 0x47 * bit1 + 0x97 * bit2;
}
-
+
palette.set_pen_color(i,rgb_t(r,g,b));
}
@@ -333,7 +333,7 @@ INTERRUPT_GEN_MEMBER(esh_state::vblank_callback_esh)
device.execute().set_input_line(0, HOLD_LINE);
}
-// TODO: 0xfe NMI enabled after writing to LD command port, NMI reads LD port.
+// TODO: 0xfe NMI enabled after writing to LD command port, NMI reads LD port.
WRITE_LINE_MEMBER(esh_state::ld_command_strobe_cb)
{
if(m_nmi_enable)
@@ -352,7 +352,7 @@ static MACHINE_CONFIG_START( esh, esh_state )
MCFG_CPU_PROGRAM_MAP(z80_0_mem)
MCFG_CPU_IO_MAP(z80_0_io)
MCFG_CPU_VBLANK_INT_DRIVER("screen", esh_state, vblank_callback_esh)
-
+
MCFG_NVRAM_ADD_0FILL("nvram")
MCFG_LASERDISC_LDV1000_ADD("laserdisc")
@@ -380,8 +380,7 @@ MACHINE_CONFIG_END
#define ROM_INTERLACED_GFX \
ROM_REGION( 0x3000, "gfx2", 0 ) \
ROM_COPY( "gfx1", 0, 0, 0x3000 ) \
- ROMX_FILL( 0, 0x3000, 0x00, ROM_SKIP(1) ) \
-
+ ROMX_FILL( 0, 0x3000, 0x00, ROM_SKIP(1) )
ROM_START( esh )
/* Main program CPU */
ROM_REGION( 0x4000, "maincpu", 0 )
diff --git a/src/mame/drivers/fccpu30.cpp b/src/mame/drivers/fccpu30.cpp
index 2be0284abe7..d20e24390b8 100644
--- a/src/mame/drivers/fccpu30.cpp
+++ b/src/mame/drivers/fccpu30.cpp
@@ -7,10 +7,10 @@
* 21/05/2016
*
* Thanks to Al Kossow his site http://www.bitsavers.org/ I got the information
- * required to start the work with this driver.
+ * required to start the work with this driver.
*
- * The driver is currently starting up and the Boot ROM asks for input do start FGA-002
- * diagnostics and do SRAM setup, which it does. After that it jumps to zeroed memory
+ * The driver is currently starting up and the Boot ROM asks for input do start FGA-002
+ * diagnostics and do SRAM setup, which it does. After that it jumps to zeroed memory
* and crashes so needs some more work to be useful
*
*
@@ -102,7 +102,7 @@
* Range Decscription
* --------------------------------------------------------------------------
* 00000000-0xxFFFFF Shared DRAM D8-D32 xx=0x1F-0x03 for 32Mb-4Mb
- * 0yy00000-FAFFFFFF VME A32 D8-D32 yy=xx+1
+ * 0yy00000-FAFFFFFF VME A32 D8-D32 yy=xx+1
* FB000000-FBFEFFFF VME A24 D8-D32
* FBFF0000-FBFFFFFF VME A16 D8-D32
* FC000000-FCFEFFFF VME A24 D8-D16
@@ -219,11 +219,11 @@ private:
required_device<pit68230_device> m_pit2;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
- UINT32 *m_sysrom;
- UINT32 m_sysram[2];
+ UINT32 *m_sysrom;
+ UINT32 m_sysram[2];
- // FGA-002
- UINT8 m_fga002[0x500];
+ // FGA-002
+ UINT8 m_fga002[0x500];
};
static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state)
@@ -239,8 +239,8 @@ static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state)
AM_RANGE (0xffd00000, 0xffd004ff) AM_READWRITE8(fga8_r, fga8_w, 0xffffffff) /* FGA-002 Force Gate Array */
AM_RANGE (0xffe00000, 0xffefffff) AM_ROM AM_REGION("maincpu", 0xffe00000)
- //AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
- //AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
+ //AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
+ //AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
ADDRESS_MAP_END
/* Input ports */
@@ -362,23 +362,23 @@ void fccpu30_state::machine_reset ()
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
m_sysrom = (UINT32*)(memregion ("maincpu")->base () + 0xffe00000);
- /* Reset values for the FGA-002 */
+ /* Reset values for the FGA-002 */
memset(&m_fga002[0], 0, sizeof(m_fga002));
- m_fga002[FGA_RSVMECALL] = 0x80;
- m_fga002[FGA_RSKEYRES] = 0x80;
- m_fga002[FGA_RSCPUCALL] = 0x80;
- m_fga002[FGA_RSLOCSW] = 0x80;
- m_fga002[FGA_ISTIM0] = 0x80;
- m_fga002[FGA_ISDMANORM] = 0x80;
- m_fga002[FGA_ISDMAERR] = 0x80;
- m_fga002[FGA_ISFMB0REF] = 0x80;
- m_fga002[FGA_ISFMB1REF] = 0x80;
- m_fga002[FGA_ISPARITY] = 0x80;
- m_fga002[FGA_ISABORT] = 0x80;
- m_fga002[FGA_ISACFAIL] = 0x80;
- m_fga002[FGA_ISSYSFAIL] = 0x80;
- m_fga002[FGA_ISFMB0MES] = 0x80;
- m_fga002[FGA_ISFMB1MES] = 0x80;
+ m_fga002[FGA_RSVMECALL] = 0x80;
+ m_fga002[FGA_RSKEYRES] = 0x80;
+ m_fga002[FGA_RSCPUCALL] = 0x80;
+ m_fga002[FGA_RSLOCSW] = 0x80;
+ m_fga002[FGA_ISTIM0] = 0x80;
+ m_fga002[FGA_ISDMANORM] = 0x80;
+ m_fga002[FGA_ISDMAERR] = 0x80;
+ m_fga002[FGA_ISFMB0REF] = 0x80;
+ m_fga002[FGA_ISFMB1REF] = 0x80;
+ m_fga002[FGA_ISPARITY] = 0x80;
+ m_fga002[FGA_ISABORT] = 0x80;
+ m_fga002[FGA_ISACFAIL] = 0x80;
+ m_fga002[FGA_ISSYSFAIL] = 0x80;
+ m_fga002[FGA_ISFMB0MES] = 0x80;
+ m_fga002[FGA_ISFMB1MES] = 0x80;
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
@@ -395,12 +395,12 @@ WRITE32_MEMBER (fccpu30_state::bootvect_w){
/*
* FGA-002 driver, might deserve its own driver but will rest here until another board wants it
*
-The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and
-containing 24,000 gates in a 281 pin PGA package. It provides interfaces to the 68020/30 microprocessor
+The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and
+containing 24,000 gates in a 281 pin PGA package. It provides interfaces to the 68020/30 microprocessor
as well as a VMEbus compatible interface. The auxilary interface of the gate array is a high speed data
-channel used by the internal 32 bit DMA controller. The interface allows data transfer rates of up to
-6 MByte/second. The timing of the local I/O interface is programmable and provides easy interfacing of
-local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly
+channel used by the internal 32 bit DMA controller. The interface allows data transfer rates of up to
+6 MByte/second. The timing of the local I/O interface is programmable and provides easy interfacing of
+local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly
connected or connected via buffers to the gate array allowing easy implementation and usage.
The gate array registers are programmed by the local CPU.
@@ -413,210 +413,209 @@ FEATURES:
- 8 bit TIMER with 16 selectable internal source clocks
*/
WRITE8_MEMBER (fccpu30_state::fga8_w){
- LOG(("%s[%04x] <- %02x - ", FUNCNAME, offset, data));
+ LOG(("%s[%04x] <- %02x - ", FUNCNAME, offset, data));
switch(offset)
{
- case FGA_SPECIALENA : LOG(("FGA_SPECIALENA - not implemented\n")); m_fga002[FGA_SPECIALENA] = data; break;
- case FGA_RSVMECALL : LOG(("FGA_RSVMECALL - not implemented\n")); m_fga002[FGA_RSVMECALL] = data; break;
- case FGA_RSKEYRES : LOG(("FGA_RSKEYRES - not implemented\n")); m_fga002[FGA_RSKEYRES] = data; break;
- case FGA_RSCPUCALL : LOG(("FGA_RSCPUCALL - not implemented\n")); m_fga002[FGA_RSCPUCALL] = data; break;
- case FGA_RSLOCSW : LOG(("FGA_RSLOCSW - not implemented\n")); m_fga002[FGA_RSLOCSW] = data; break;
- case FGA_ICRMBOX0 : LOG(("FGA_ICRMBOX0 - not implemented\n")); m_fga002[FGA_ICRMBOX0] = data; break;
- case FGA_ICRMBOX1 : LOG(("FGA_ICRMBOX1 - not implemented\n")); m_fga002[FGA_ICRMBOX1] = data; break;
- case FGA_ICRMBOX2 : LOG(("FGA_ICRMBOX2 - not implemented\n")); m_fga002[FGA_ICRMBOX2] = data; break;
- case FGA_ICRMBOX3 : LOG(("FGA_ICRMBOX3 - not implemented\n")); m_fga002[FGA_ICRMBOX3] = data; break;
- case FGA_ICRMBOX4 : LOG(("FGA_ICRMBOX4 - not implemented\n")); m_fga002[FGA_ICRMBOX4] = data; break;
- case FGA_ICRMBOX5 : LOG(("FGA_ICRMBOX5 - not implemented\n")); m_fga002[FGA_ICRMBOX5] = data; break;
- case FGA_ICRMBOX6 : LOG(("FGA_ICRMBOX6 - not implemented\n")); m_fga002[FGA_ICRMBOX6] = data; break;
- case FGA_ICRMBOX7 : LOG(("FGA_ICRMBOX7 - not implemented\n")); m_fga002[FGA_ICRMBOX7] = data; break;
- case FGA_VMEPAGE : LOG(("FGA_VMEPAGE - not implemented\n")); m_fga002[FGA_VMEPAGE ] = data; break;
- case FGA_ICRVME1 : LOG(("FGA_ICRVME1 - not implemented\n")); m_fga002[FGA_ICRVME1] = data; break;
- case FGA_ICRVME2 : LOG(("FGA_ICRVME2 - not implemented\n")); m_fga002[FGA_ICRVME2] = data; break;
- case FGA_ICRVME3 : LOG(("FGA_ICRVME3 - not implemented\n")); m_fga002[FGA_ICRVME3] = data; break;
- case FGA_ICRVME4 : LOG(("FGA_ICRVME4 - not implemented\n")); m_fga002[FGA_ICRVME4] = data; break;
- case FGA_ICRVME5 : LOG(("FGA_ICRVME5 - not implemented\n")); m_fga002[FGA_ICRVME5] = data; break;
- case FGA_ICRVME6 : LOG(("FGA_ICRVME6 - not implemented\n")); m_fga002[FGA_ICRVME6] = data; break;
- case FGA_ICRVME7 : LOG(("FGA_ICRVME7 - not implemented\n")); m_fga002[FGA_ICRVME7] = data; break;
- case FGA_ICRTIM0 : LOG(("FGA_ICRTIM0 - not implemented\n")); m_fga002[FGA_ICRTIM0] = data; break;
- case FGA_ICRDMANORM : LOG(("FGA_ICRDMANORM - not implemented\n")); m_fga002[FGA_ICRDMANORM] = data; break;
- case FGA_ICRDMAERR : LOG(("FGA_ICRDMAERR - not implemented\n")); m_fga002[FGA_ICRDMAERR] = data; break;
- case FGA_CTL1 : LOG(("FGA_CTL1 - not implemented\n")); m_fga002[FGA_CTL1] = data; break;
- case FGA_CTL2 : LOG(("FGA_CTL2 - not implemented\n")); m_fga002[FGA_CTL2] = data; break;
- case FGA_ICRFMB0REF : LOG(("FGA_ICRFMB0REF - not implemented\n")); m_fga002[FGA_ICRFMB0REF] = data; break;
- case FGA_ICRFMB1REF : LOG(("FGA_ICRFMB1REF - not implemented\n")); m_fga002[FGA_ICRFMB1REF] = data; break;
- case FGA_ICRFMB0MES : LOG(("FGA_ICRFMB0MES - not implemented\n")); m_fga002[FGA_ICRFMB0MES] = data; break;
- case FGA_ICRFMB1MES : LOG(("FGA_ICRFMB1MES - not implemented\n")); m_fga002[FGA_ICRFMB1MES] = data; break;
- case FGA_CTL3 : LOG(("FGA_CTL3 - not implemented\n")); m_fga002[FGA_CTL3] = data; break;
- case FGA_CTL4 : LOG(("FGA_CTL4 - not implemented\n")); m_fga002[FGA_CTL4] = data; break;
- case FGA_ICRPARITY : LOG(("FGA_ICRPARITY - not implemented\n")); m_fga002[FGA_ICRPARITY] = data; break;
- case FGA_AUXPINCTL : LOG(("FGA_AUXPINCTL - not implemented\n")); m_fga002[FGA_AUXPINCTL] = data; break;
- case FGA_CTL5 : LOG(("FGA_CTL5 - not implemented\n")); m_fga002[FGA_CTL5] = data; break;
- case FGA_AUXFIFWEX : LOG(("FGA_AUXFIFWEX - not implemented\n")); m_fga002[FGA_AUXFIFWEX] = data; break;
- case FGA_AUXFIFREX : LOG(("FGA_AUXFIFREX - not implemented\n")); m_fga002[FGA_AUXFIFREX] = data; break;
- case FGA_CTL6 : LOG(("FGA_CTL6 - not implemented\n")); m_fga002[FGA_CTL6] = data; break;
- case FGA_CTL7 : LOG(("FGA_CTL7 - not implemented\n")); m_fga002[FGA_CTL7] = data; break;
- case FGA_CTL8 : LOG(("FGA_CTL8 - not implemented\n")); m_fga002[FGA_CTL8] = data; break;
- case FGA_CTL9 : LOG(("FGA_CTL9 - not implemented\n")); m_fga002[FGA_CTL9] = data; break;
- case FGA_ICRABORT : LOG(("FGA_ICRABORT - not implemented\n")); m_fga002[FGA_ICRABORT] = data; break;
- case FGA_ICRACFAIL : LOG(("FGA_ICRACFAIL - not implemented\n")); m_fga002[FGA_ICRACFAIL] = data; break;
- case FGA_ICRSYSFAIL : LOG(("FGA_ICRSYSFAIL - not implemented\n")); m_fga002[FGA_ICRSYSFAIL] = data; break;
- case FGA_ICRLOCAL0 : LOG(("FGA_ICRLOCAL0 - not implemented\n")); m_fga002[FGA_ICRLOCAL0] = data; break;
- case FGA_ICRLOCAL1 : LOG(("FGA_ICRLOCAL1 - not implemented\n")); m_fga002[FGA_ICRLOCAL1] = data; break;
- case FGA_ICRLOCAL2 : LOG(("FGA_ICRLOCAL2 - not implemented\n")); m_fga002[FGA_ICRLOCAL2] = data; break;
- case FGA_ICRLOCAL3 : LOG(("FGA_ICRLOCAL3 - not implemented\n")); m_fga002[FGA_ICRLOCAL3] = data; break;
- case FGA_ICRLOCAL4 : LOG(("FGA_ICRLOCAL4 - not implemented\n")); m_fga002[FGA_ICRLOCAL4] = data; break;
- case FGA_ICRLOCAL5 : LOG(("FGA_ICRLOCAL5 - not implemented\n")); m_fga002[FGA_ICRLOCAL5] = data; break;
- case FGA_ICRLOCAL6 : LOG(("FGA_ICRLOCAL6 - not implemented\n")); m_fga002[FGA_ICRLOCAL6] = data; break;
- case FGA_ICRLOCAL7 : LOG(("FGA_ICRLOCAL7 - not implemented\n")); m_fga002[FGA_ICRLOCAL7] = data; break;
- case FGA_ENAMCODE : LOG(("FGA_ENAMCODE - not implemented\n")); m_fga002[FGA_ENAMCODE] = data; break;
- case FGA_CTL10 : LOG(("FGA_CTL10 - not implemented\n")); m_fga002[FGA_CTL10] = data; break;
- case FGA_CTL11 : LOG(("FGA_CTL11 - not implemented\n")); m_fga002[FGA_CTL11] = data; break;
- case FGA_MAINUM : LOG(("FGA_MAINUM - not implemented\n")); m_fga002[FGA_MAINUM] = data; break;
- case FGA_MAINUU : LOG(("FGA_MAINUU - not implemented\n")); m_fga002[FGA_MAINUU] = data; break;
- case FGA_BOTTOMPAGEU : LOG(("FGA_BOTTOMPAGEU - not implemented\n")); m_fga002[FGA_BOTTOMPAGEU] = data; break;
- case FGA_BOTTOMPAGEL : LOG(("FGA_BOTTOMPAGEL - not implemented\n")); m_fga002[FGA_BOTTOMPAGEL] = data; break;
- case FGA_TOPPAGEU : LOG(("FGA_TOPPAGEU - not implemented\n")); m_fga002[FGA_TOPPAGEU] = data; break;
- case FGA_TOPPAGEL : LOG(("FGA_TOPPAGEL - not implemented\n")); m_fga002[FGA_TOPPAGEL] = data; break;
- case FGA_MYVMEPAGE : LOG(("FGA_MYVMEPAGE - not implemented\n")); m_fga002[FGA_MYVMEPAGE] = data; break;
- case FGA_TIM0PRELOAD : LOG(("FGA_TIM0PRELOAD - not implemented\n")); m_fga002[FGA_TIM0PRELOAD] = data; break;
- case FGA_TIM0CTL : LOG(("FGA_TIM0CTL - not implemented\n")); m_fga002[FGA_TIM0CTL] = data; break;
- case FGA_DMASRCATT : LOG(("FGA_DMASRCATT - not implemented\n")); m_fga002[FGA_DMASRCATT] = data; break;
- case FGA_DMADSTATT : LOG(("FGA_DMADSTATT - not implemented\n")); m_fga002[FGA_DMADSTATT] = data; break;
- case FGA_DMA_GENERAL : LOG(("FGA_DMA_GENERAL - not implemented\n")); m_fga002[FGA_DMA_GENERAL] = data; break;
- case FGA_CTL12 : LOG(("FGA_CTL12 - not implemented\n")); m_fga002[FGA_CTL12] = data; break;
- case FGA_LIOTIMING : LOG(("FGA_LIOTIMING - not implemented\n")); m_fga002[FGA_LIOTIMING] = data; break;
- case FGA_LOCALIACK : LOG(("FGA_LOCALIACK - not implemented\n")); m_fga002[FGA_LOCALIACK] = data; break;
- case FGA_FMBCTL : LOG(("FGA_FMBCTL - not implemented\n")); m_fga002[FGA_FMBCTL] = data; break;
- case FGA_FMBAREA : LOG(("FGA_FMBAREA - not implemented\n")); m_fga002[FGA_FMBAREA] = data; break;
- case FGA_AUXSRCSTART : LOG(("FGA_AUXSRCSTART - not implemented\n")); m_fga002[FGA_AUXSRCSTART] = data; break;
- case FGA_AUXDSTSTART : LOG(("FGA_AUXDSTSTART - not implemented\n")); m_fga002[FGA_AUXDSTSTART] = data; break;
- case FGA_AUXSRCTERM : LOG(("FGA_AUXSRCTERM - not implemented\n")); m_fga002[FGA_AUXSRCTERM] = data; break;
- case FGA_AUXDSTTERM : LOG(("FGA_AUXDSTTERM - not implemented\n")); m_fga002[FGA_AUXDSTTERM] = data; break;
- case FGA_CTL13 : LOG(("FGA_CTL13 - not implemented\n")); m_fga002[FGA_CTL13] = data; break;
- case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break;
- case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break;
- case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break;
- case FGA_ISTIM0 : LOG(("FGA_ISTIM0 - not implemented\n")); m_fga002[FGA_ISTIM0] = data; break;
- case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break;
- case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break;
- case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break;
- case FGA_ISFMB1REF : LOG(("FGA_ISFMB1REF - not implemented\n")); m_fga002[FGA_ISFMB1REF] = data; break;
- case FGA_ISPARITY : LOG(("FGA_ISPARITY - not implemented\n")); m_fga002[FGA_ISPARITY] = data; break;
- case FGA_DMARUNCTL : LOG(("FGA_DMARUNCTL - not implemented\n")); m_fga002[FGA_DMARUNCTL] = data; break;
- case FGA_ISABORT : LOG(("FGA_ISABORT - not implemented\n")); m_fga002[FGA_ISABORT] = data; break;
- case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break;
- case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break;
- case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break;
+ case FGA_SPECIALENA : LOG(("FGA_SPECIALENA - not implemented\n")); m_fga002[FGA_SPECIALENA] = data; break;
+ case FGA_RSVMECALL : LOG(("FGA_RSVMECALL - not implemented\n")); m_fga002[FGA_RSVMECALL] = data; break;
+ case FGA_RSKEYRES : LOG(("FGA_RSKEYRES - not implemented\n")); m_fga002[FGA_RSKEYRES] = data; break;
+ case FGA_RSCPUCALL : LOG(("FGA_RSCPUCALL - not implemented\n")); m_fga002[FGA_RSCPUCALL] = data; break;
+ case FGA_RSLOCSW : LOG(("FGA_RSLOCSW - not implemented\n")); m_fga002[FGA_RSLOCSW] = data; break;
+ case FGA_ICRMBOX0 : LOG(("FGA_ICRMBOX0 - not implemented\n")); m_fga002[FGA_ICRMBOX0] = data; break;
+ case FGA_ICRMBOX1 : LOG(("FGA_ICRMBOX1 - not implemented\n")); m_fga002[FGA_ICRMBOX1] = data; break;
+ case FGA_ICRMBOX2 : LOG(("FGA_ICRMBOX2 - not implemented\n")); m_fga002[FGA_ICRMBOX2] = data; break;
+ case FGA_ICRMBOX3 : LOG(("FGA_ICRMBOX3 - not implemented\n")); m_fga002[FGA_ICRMBOX3] = data; break;
+ case FGA_ICRMBOX4 : LOG(("FGA_ICRMBOX4 - not implemented\n")); m_fga002[FGA_ICRMBOX4] = data; break;
+ case FGA_ICRMBOX5 : LOG(("FGA_ICRMBOX5 - not implemented\n")); m_fga002[FGA_ICRMBOX5] = data; break;
+ case FGA_ICRMBOX6 : LOG(("FGA_ICRMBOX6 - not implemented\n")); m_fga002[FGA_ICRMBOX6] = data; break;
+ case FGA_ICRMBOX7 : LOG(("FGA_ICRMBOX7 - not implemented\n")); m_fga002[FGA_ICRMBOX7] = data; break;
+ case FGA_VMEPAGE : LOG(("FGA_VMEPAGE - not implemented\n")); m_fga002[FGA_VMEPAGE ] = data; break;
+ case FGA_ICRVME1 : LOG(("FGA_ICRVME1 - not implemented\n")); m_fga002[FGA_ICRVME1] = data; break;
+ case FGA_ICRVME2 : LOG(("FGA_ICRVME2 - not implemented\n")); m_fga002[FGA_ICRVME2] = data; break;
+ case FGA_ICRVME3 : LOG(("FGA_ICRVME3 - not implemented\n")); m_fga002[FGA_ICRVME3] = data; break;
+ case FGA_ICRVME4 : LOG(("FGA_ICRVME4 - not implemented\n")); m_fga002[FGA_ICRVME4] = data; break;
+ case FGA_ICRVME5 : LOG(("FGA_ICRVME5 - not implemented\n")); m_fga002[FGA_ICRVME5] = data; break;
+ case FGA_ICRVME6 : LOG(("FGA_ICRVME6 - not implemented\n")); m_fga002[FGA_ICRVME6] = data; break;
+ case FGA_ICRVME7 : LOG(("FGA_ICRVME7 - not implemented\n")); m_fga002[FGA_ICRVME7] = data; break;
+ case FGA_ICRTIM0 : LOG(("FGA_ICRTIM0 - not implemented\n")); m_fga002[FGA_ICRTIM0] = data; break;
+ case FGA_ICRDMANORM : LOG(("FGA_ICRDMANORM - not implemented\n")); m_fga002[FGA_ICRDMANORM] = data; break;
+ case FGA_ICRDMAERR : LOG(("FGA_ICRDMAERR - not implemented\n")); m_fga002[FGA_ICRDMAERR] = data; break;
+ case FGA_CTL1 : LOG(("FGA_CTL1 - not implemented\n")); m_fga002[FGA_CTL1] = data; break;
+ case FGA_CTL2 : LOG(("FGA_CTL2 - not implemented\n")); m_fga002[FGA_CTL2] = data; break;
+ case FGA_ICRFMB0REF : LOG(("FGA_ICRFMB0REF - not implemented\n")); m_fga002[FGA_ICRFMB0REF] = data; break;
+ case FGA_ICRFMB1REF : LOG(("FGA_ICRFMB1REF - not implemented\n")); m_fga002[FGA_ICRFMB1REF] = data; break;
+ case FGA_ICRFMB0MES : LOG(("FGA_ICRFMB0MES - not implemented\n")); m_fga002[FGA_ICRFMB0MES] = data; break;
+ case FGA_ICRFMB1MES : LOG(("FGA_ICRFMB1MES - not implemented\n")); m_fga002[FGA_ICRFMB1MES] = data; break;
+ case FGA_CTL3 : LOG(("FGA_CTL3 - not implemented\n")); m_fga002[FGA_CTL3] = data; break;
+ case FGA_CTL4 : LOG(("FGA_CTL4 - not implemented\n")); m_fga002[FGA_CTL4] = data; break;
+ case FGA_ICRPARITY : LOG(("FGA_ICRPARITY - not implemented\n")); m_fga002[FGA_ICRPARITY] = data; break;
+ case FGA_AUXPINCTL : LOG(("FGA_AUXPINCTL - not implemented\n")); m_fga002[FGA_AUXPINCTL] = data; break;
+ case FGA_CTL5 : LOG(("FGA_CTL5 - not implemented\n")); m_fga002[FGA_CTL5] = data; break;
+ case FGA_AUXFIFWEX : LOG(("FGA_AUXFIFWEX - not implemented\n")); m_fga002[FGA_AUXFIFWEX] = data; break;
+ case FGA_AUXFIFREX : LOG(("FGA_AUXFIFREX - not implemented\n")); m_fga002[FGA_AUXFIFREX] = data; break;
+ case FGA_CTL6 : LOG(("FGA_CTL6 - not implemented\n")); m_fga002[FGA_CTL6] = data; break;
+ case FGA_CTL7 : LOG(("FGA_CTL7 - not implemented\n")); m_fga002[FGA_CTL7] = data; break;
+ case FGA_CTL8 : LOG(("FGA_CTL8 - not implemented\n")); m_fga002[FGA_CTL8] = data; break;
+ case FGA_CTL9 : LOG(("FGA_CTL9 - not implemented\n")); m_fga002[FGA_CTL9] = data; break;
+ case FGA_ICRABORT : LOG(("FGA_ICRABORT - not implemented\n")); m_fga002[FGA_ICRABORT] = data; break;
+ case FGA_ICRACFAIL : LOG(("FGA_ICRACFAIL - not implemented\n")); m_fga002[FGA_ICRACFAIL] = data; break;
+ case FGA_ICRSYSFAIL : LOG(("FGA_ICRSYSFAIL - not implemented\n")); m_fga002[FGA_ICRSYSFAIL] = data; break;
+ case FGA_ICRLOCAL0 : LOG(("FGA_ICRLOCAL0 - not implemented\n")); m_fga002[FGA_ICRLOCAL0] = data; break;
+ case FGA_ICRLOCAL1 : LOG(("FGA_ICRLOCAL1 - not implemented\n")); m_fga002[FGA_ICRLOCAL1] = data; break;
+ case FGA_ICRLOCAL2 : LOG(("FGA_ICRLOCAL2 - not implemented\n")); m_fga002[FGA_ICRLOCAL2] = data; break;
+ case FGA_ICRLOCAL3 : LOG(("FGA_ICRLOCAL3 - not implemented\n")); m_fga002[FGA_ICRLOCAL3] = data; break;
+ case FGA_ICRLOCAL4 : LOG(("FGA_ICRLOCAL4 - not implemented\n")); m_fga002[FGA_ICRLOCAL4] = data; break;
+ case FGA_ICRLOCAL5 : LOG(("FGA_ICRLOCAL5 - not implemented\n")); m_fga002[FGA_ICRLOCAL5] = data; break;
+ case FGA_ICRLOCAL6 : LOG(("FGA_ICRLOCAL6 - not implemented\n")); m_fga002[FGA_ICRLOCAL6] = data; break;
+ case FGA_ICRLOCAL7 : LOG(("FGA_ICRLOCAL7 - not implemented\n")); m_fga002[FGA_ICRLOCAL7] = data; break;
+ case FGA_ENAMCODE : LOG(("FGA_ENAMCODE - not implemented\n")); m_fga002[FGA_ENAMCODE] = data; break;
+ case FGA_CTL10 : LOG(("FGA_CTL10 - not implemented\n")); m_fga002[FGA_CTL10] = data; break;
+ case FGA_CTL11 : LOG(("FGA_CTL11 - not implemented\n")); m_fga002[FGA_CTL11] = data; break;
+ case FGA_MAINUM : LOG(("FGA_MAINUM - not implemented\n")); m_fga002[FGA_MAINUM] = data; break;
+ case FGA_MAINUU : LOG(("FGA_MAINUU - not implemented\n")); m_fga002[FGA_MAINUU] = data; break;
+ case FGA_BOTTOMPAGEU : LOG(("FGA_BOTTOMPAGEU - not implemented\n")); m_fga002[FGA_BOTTOMPAGEU] = data; break;
+ case FGA_BOTTOMPAGEL : LOG(("FGA_BOTTOMPAGEL - not implemented\n")); m_fga002[FGA_BOTTOMPAGEL] = data; break;
+ case FGA_TOPPAGEU : LOG(("FGA_TOPPAGEU - not implemented\n")); m_fga002[FGA_TOPPAGEU] = data; break;
+ case FGA_TOPPAGEL : LOG(("FGA_TOPPAGEL - not implemented\n")); m_fga002[FGA_TOPPAGEL] = data; break;
+ case FGA_MYVMEPAGE : LOG(("FGA_MYVMEPAGE - not implemented\n")); m_fga002[FGA_MYVMEPAGE] = data; break;
+ case FGA_TIM0PRELOAD : LOG(("FGA_TIM0PRELOAD - not implemented\n")); m_fga002[FGA_TIM0PRELOAD] = data; break;
+ case FGA_TIM0CTL : LOG(("FGA_TIM0CTL - not implemented\n")); m_fga002[FGA_TIM0CTL] = data; break;
+ case FGA_DMASRCATT : LOG(("FGA_DMASRCATT - not implemented\n")); m_fga002[FGA_DMASRCATT] = data; break;
+ case FGA_DMADSTATT : LOG(("FGA_DMADSTATT - not implemented\n")); m_fga002[FGA_DMADSTATT] = data; break;
+ case FGA_DMA_GENERAL : LOG(("FGA_DMA_GENERAL - not implemented\n")); m_fga002[FGA_DMA_GENERAL] = data; break;
+ case FGA_CTL12 : LOG(("FGA_CTL12 - not implemented\n")); m_fga002[FGA_CTL12] = data; break;
+ case FGA_LIOTIMING : LOG(("FGA_LIOTIMING - not implemented\n")); m_fga002[FGA_LIOTIMING] = data; break;
+ case FGA_LOCALIACK : LOG(("FGA_LOCALIACK - not implemented\n")); m_fga002[FGA_LOCALIACK] = data; break;
+ case FGA_FMBCTL : LOG(("FGA_FMBCTL - not implemented\n")); m_fga002[FGA_FMBCTL] = data; break;
+ case FGA_FMBAREA : LOG(("FGA_FMBAREA - not implemented\n")); m_fga002[FGA_FMBAREA] = data; break;
+ case FGA_AUXSRCSTART : LOG(("FGA_AUXSRCSTART - not implemented\n")); m_fga002[FGA_AUXSRCSTART] = data; break;
+ case FGA_AUXDSTSTART : LOG(("FGA_AUXDSTSTART - not implemented\n")); m_fga002[FGA_AUXDSTSTART] = data; break;
+ case FGA_AUXSRCTERM : LOG(("FGA_AUXSRCTERM - not implemented\n")); m_fga002[FGA_AUXSRCTERM] = data; break;
+ case FGA_AUXDSTTERM : LOG(("FGA_AUXDSTTERM - not implemented\n")); m_fga002[FGA_AUXDSTTERM] = data; break;
+ case FGA_CTL13 : LOG(("FGA_CTL13 - not implemented\n")); m_fga002[FGA_CTL13] = data; break;
+ case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break;
+ case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break;
+ case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break;
+ case FGA_ISTIM0 : LOG(("FGA_ISTIM0 - not implemented\n")); m_fga002[FGA_ISTIM0] = data; break;
+ case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break;
+ case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break;
+ case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break;
+ case FGA_ISFMB1REF : LOG(("FGA_ISFMB1REF - not implemented\n")); m_fga002[FGA_ISFMB1REF] = data; break;
+ case FGA_ISPARITY : LOG(("FGA_ISPARITY - not implemented\n")); m_fga002[FGA_ISPARITY] = data; break;
+ case FGA_DMARUNCTL : LOG(("FGA_DMARUNCTL - not implemented\n")); m_fga002[FGA_DMARUNCTL] = data; break;
+ case FGA_ISABORT : LOG(("FGA_ISABORT - not implemented\n")); m_fga002[FGA_ISABORT] = data; break;
+ case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break;
+ case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break;
+ case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break;
default:
LOG(("Unsupported register %04x\n", offset));
}
}
READ8_MEMBER (fccpu30_state::fga8_r){
-
UINT8 ret = 0;
- LOG(("%s[%04x] ", FUNCNAME, offset));
+ LOG(("%s[%04x] ", FUNCNAME, offset));
switch(offset)
{
- case FGA_SPECIALENA : ret = m_fga002[FGA_SPECIALENA]; LOG(("FGA_SPECIALENA returns %02x - not implemented\n", ret)); break;
- case FGA_RSVMECALL : ret = m_fga002[FGA_RSVMECALL]; LOG(("FGA_RSVMECALL returns %02x - not implemented\n", ret)); break;
- case FGA_RSKEYRES : ret = m_fga002[FGA_RSKEYRES]; LOG(("FGA_RSKEYRES returns %02x - not implemented\n", ret)); break;
- case FGA_RSCPUCALL : ret = m_fga002[FGA_RSCPUCALL]; LOG(("FGA_RSCPUCALL returns %02x - not implemented\n", ret)); break;
- case FGA_RSLOCSW : ret = m_fga002[FGA_RSLOCSW]; LOG(("FGA_RSLOCSW returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX0 : ret = m_fga002[FGA_ICRMBOX0]; LOG(("FGA_ICRMBOX0 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX1 : ret = m_fga002[FGA_ICRMBOX1]; LOG(("FGA_ICRMBOX1 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX2 : ret = m_fga002[FGA_ICRMBOX2]; LOG(("FGA_ICRMBOX2 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX3 : ret = m_fga002[FGA_ICRMBOX3]; LOG(("FGA_ICRMBOX3 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX4 : ret = m_fga002[FGA_ICRMBOX4]; LOG(("FGA_ICRMBOX4 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX5 : ret = m_fga002[FGA_ICRMBOX5]; LOG(("FGA_ICRMBOX5 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX6 : ret = m_fga002[FGA_ICRMBOX6]; LOG(("FGA_ICRMBOX6 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRMBOX7 : ret = m_fga002[FGA_ICRMBOX7]; LOG(("FGA_ICRMBOX7 returns %02x - not implemented\n", ret)); break;
- case FGA_VMEPAGE : ret = m_fga002[FGA_VMEPAGE]; LOG(("FGA_VMEPAGE returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME1 : ret = m_fga002[FGA_ICRVME1]; LOG(("FGA_ICRVME1 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME2 : ret = m_fga002[FGA_ICRVME2]; LOG(("FGA_ICRVME2 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME3 : ret = m_fga002[FGA_ICRVME3]; LOG(("FGA_ICRVME3 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME4 : ret = m_fga002[FGA_ICRVME4]; LOG(("FGA_ICRVME4 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME5 : ret = m_fga002[FGA_ICRVME5]; LOG(("FGA_ICRVME5 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME6 : ret = m_fga002[FGA_ICRVME6]; LOG(("FGA_ICRVME6 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRVME7 : ret = m_fga002[FGA_ICRVME7]; LOG(("FGA_ICRVME7 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRTIM0 : ret = m_fga002[FGA_ICRTIM0]; LOG(("FGA_ICRTIM0 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRDMANORM : ret = m_fga002[FGA_ICRDMANORM]; LOG(("FGA_ICRDMANORM returns %02x - not implemented\n", ret)); break;
- case FGA_ICRDMAERR : ret = m_fga002[FGA_ICRDMAERR]; LOG(("FGA_ICRDMAERR returns %02x - not implemented\n", ret)); break;
- case FGA_CTL1 : ret = m_fga002[FGA_CTL1]; LOG(("FGA_CTL1 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL2 : ret = m_fga002[FGA_CTL2]; LOG(("FGA_CTL2 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRFMB0REF : ret = m_fga002[FGA_ICRFMB0REF]; LOG(("FGA_ICRFMB0REF returns %02x - not implemented\n", ret)); break;
- case FGA_ICRFMB1REF : ret = m_fga002[FGA_ICRFMB1REF]; LOG(("FGA_ICRFMB1REF returns %02x - not implemented\n", ret)); break;
- case FGA_ICRFMB0MES : ret = m_fga002[FGA_ICRFMB0MES]; LOG(("FGA_ICRFMB0MES returns %02x - not implemented\n", ret)); break;
- case FGA_ICRFMB1MES : ret = m_fga002[FGA_ICRFMB1MES]; LOG(("FGA_ICRFMB1MES returns %02x - not implemented\n", ret)); break;
- case FGA_CTL3 : ret = m_fga002[FGA_CTL3]; LOG(("FGA_CTL3 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL4 : ret = m_fga002[FGA_CTL4]; LOG(("FGA_CTL4 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRPARITY : ret = m_fga002[FGA_ICRPARITY]; LOG(("FGA_ICRPARITY returns %02x - not implemented\n", ret)); break;
- case FGA_AUXPINCTL : ret = m_fga002[FGA_AUXPINCTL]; LOG(("FGA_AUXPINCTL returns %02x - not implemented\n", ret)); break;
- case FGA_CTL5 : ret = m_fga002[FGA_CTL5]; LOG(("FGA_CTL5 returns %02x - not implemented\n", ret)); break;
- case FGA_AUXFIFWEX : ret = m_fga002[FGA_AUXFIFWEX]; LOG(("FGA_AUXFIFWEX returns %02x - not implemented\n", ret)); break;
- case FGA_AUXFIFREX : ret = m_fga002[FGA_AUXFIFREX]; LOG(("FGA_AUXFIFREX returns %02x - not implemented\n", ret)); break;
- case FGA_CTL6 : ret = m_fga002[FGA_CTL6]; LOG(("FGA_CTL6 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL7 : ret = m_fga002[FGA_CTL7]; LOG(("FGA_CTL7 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL8 : ret = m_fga002[FGA_CTL8]; LOG(("FGA_CTL8 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL9 : ret = m_fga002[FGA_CTL9]; LOG(("FGA_CTL9 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRABORT : ret = m_fga002[FGA_ICRABORT]; LOG(("FGA_ICRABORT returns %02x - not implemented\n", ret)); break;
- case FGA_ICRACFAIL : ret = m_fga002[FGA_ICRACFAIL]; LOG(("FGA_ICRACFAIL returns %02x - not implemented\n", ret)); break;
- case FGA_ICRSYSFAIL : ret = m_fga002[FGA_ICRSYSFAIL]; LOG(("FGA_ICRSYSFAIL returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL0 : ret = m_fga002[FGA_ICRLOCAL0]; LOG(("FGA_ICRLOCAL0 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL1 : ret = m_fga002[FGA_ICRLOCAL1]; LOG(("FGA_ICRLOCAL1 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL2 : ret = m_fga002[FGA_ICRLOCAL2]; LOG(("FGA_ICRLOCAL2 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL3 : ret = m_fga002[FGA_ICRLOCAL3]; LOG(("FGA_ICRLOCAL3 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL4 : ret = m_fga002[FGA_ICRLOCAL4]; LOG(("FGA_ICRLOCAL4 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL5 : ret = m_fga002[FGA_ICRLOCAL5]; LOG(("FGA_ICRLOCAL5 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL6 : ret = m_fga002[FGA_ICRLOCAL6]; LOG(("FGA_ICRLOCAL6 returns %02x - not implemented\n", ret)); break;
- case FGA_ICRLOCAL7 : ret = m_fga002[FGA_ICRLOCAL7]; LOG(("FGA_ICRLOCAL7 returns %02x - not implemented\n", ret)); break;
- case FGA_ENAMCODE : ret = m_fga002[FGA_ENAMCODE]; LOG(("FGA_ENAMCODE returns %02x - not implemented\n", ret)); break;
- case FGA_CTL10 : ret = m_fga002[FGA_CTL10]; LOG(("FGA_CTL10 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL11 : ret = m_fga002[FGA_CTL11]; LOG(("FGA_CTL11 returns %02x - not implemented\n", ret)); break;
- case FGA_MAINUM : ret = m_fga002[FGA_MAINUM]; LOG(("FGA_MAINUM returns %02x - not implemented\n", ret)); break;
- case FGA_MAINUU : ret = m_fga002[FGA_MAINUU]; LOG(("FGA_MAINUU returns %02x - not implemented\n", ret)); break;
- case FGA_BOTTOMPAGEU : ret = m_fga002[FGA_BOTTOMPAGEU]; LOG(("FGA_BOTTOMPAGEU returns %02x - not implemented\n", ret)); break;
- case FGA_BOTTOMPAGEL : ret = m_fga002[FGA_BOTTOMPAGEL]; LOG(("FGA_BOTTOMPAGEL returns %02x - not implemented\n", ret)); break;
- case FGA_TOPPAGEU : ret = m_fga002[FGA_TOPPAGEU]; LOG(("FGA_TOPPAGEU returns %02x - not implemented\n", ret)); break;
- case FGA_TOPPAGEL : ret = m_fga002[FGA_TOPPAGEL]; LOG(("FGA_TOPPAGEL returns %02x - not implemented\n", ret)); break;
- case FGA_MYVMEPAGE : ret = m_fga002[FGA_MYVMEPAGE]; LOG(("FGA_MYVMEPAGE returns %02x - not implemented\n", ret)); break;
- case FGA_TIM0PRELOAD : ret = m_fga002[FGA_TIM0PRELOAD]; LOG(("FGA_TIM0PRELOAD returns %02x - not implemented\n", ret)); break;
- case FGA_TIM0CTL : ret = m_fga002[FGA_TIM0CTL]; LOG(("FGA_TIM0CTL returns %02x - not implemented\n", ret)); break;
- case FGA_DMASRCATT : ret = m_fga002[FGA_DMASRCATT]; LOG(("FGA_DMASRCATT returns %02x - not implemented\n", ret)); break;
- case FGA_DMADSTATT : ret = m_fga002[FGA_DMADSTATT]; LOG(("FGA_DMADSTATT returns %02x - not implemented\n", ret)); break;
- case FGA_DMA_GENERAL : ret = m_fga002[FGA_DMA_GENERAL]; LOG(("FGA_DMA_GENERAL returns %02x - not implemented\n", ret)); break;
- case FGA_CTL12 : ret = m_fga002[FGA_CTL12]; LOG(("FGA_CTL12 returns %02x - not implemented\n", ret)); break;
- case FGA_LIOTIMING : ret = m_fga002[FGA_LIOTIMING]; LOG(("FGA_LIOTIMING returns %02x - not implemented\n", ret)); break;
- case FGA_LOCALIACK : ret = m_fga002[FGA_LOCALIACK]; LOG(("FGA_LOCALIACK returns %02x - not implemented\n", ret)); break;
- case FGA_FMBCTL : ret = m_fga002[FGA_FMBCTL]; LOG(("FGA_FMBCTL returns %02x - not implemented\n", ret)); break;
- case FGA_FMBAREA : ret = m_fga002[FGA_FMBAREA]; LOG(("FGA_FMBAREA returns %02x - not implemented\n", ret)); break;
- case FGA_AUXSRCSTART : ret = m_fga002[FGA_AUXSRCSTART]; LOG(("FGA_AUXSRCSTART returns %02x - not implemented\n", ret)); break;
- case FGA_AUXDSTSTART : ret = m_fga002[FGA_AUXDSTSTART]; LOG(("FGA_AUXDSTSTART returns %02x - not implemented\n", ret)); break;
- case FGA_AUXSRCTERM : ret = m_fga002[FGA_AUXSRCTERM]; LOG(("FGA_AUXSRCTERM returns %02x - not implemented\n", ret)); break;
- case FGA_AUXDSTTERM : ret = m_fga002[FGA_AUXDSTTERM]; LOG(("FGA_AUXDSTTERM returns %02x - not implemented\n", ret)); break;
- case FGA_CTL13 : ret = m_fga002[FGA_CTL13]; LOG(("FGA_CTL13 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break;
- case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break;
- case FGA_ISTIM0 : ret = m_fga002[FGA_ISTIM0]; LOG(("FGA_ISTIM0 returns %02x - not implemented\n", ret)); break;
- case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break;
- case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break;
- case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break;
- case FGA_ISFMB1REF : ret = m_fga002[FGA_ISFMB1REF]; LOG(("FGA_ISFMB1REF returns %02x - not implemented\n", ret)); break;
- case FGA_ISPARITY : ret = m_fga002[FGA_ISPARITY]; LOG(("FGA_ISPARITY returns %02x - not implemented\n", ret)); break;
- case FGA_DMARUNCTL : ret = m_fga002[FGA_DMARUNCTL]; LOG(("FGA_DMARUNCTL returns %02x - not implemented\n", ret)); break;
- case FGA_ISABORT : ret = m_fga002[FGA_ISABORT]; LOG(("FGA_ISABORT returns %02x - not implemented\n", ret)); break;
- case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break;
- case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break;
- case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break;
+ case FGA_SPECIALENA : ret = m_fga002[FGA_SPECIALENA]; LOG(("FGA_SPECIALENA returns %02x - not implemented\n", ret)); break;
+ case FGA_RSVMECALL : ret = m_fga002[FGA_RSVMECALL]; LOG(("FGA_RSVMECALL returns %02x - not implemented\n", ret)); break;
+ case FGA_RSKEYRES : ret = m_fga002[FGA_RSKEYRES]; LOG(("FGA_RSKEYRES returns %02x - not implemented\n", ret)); break;
+ case FGA_RSCPUCALL : ret = m_fga002[FGA_RSCPUCALL]; LOG(("FGA_RSCPUCALL returns %02x - not implemented\n", ret)); break;
+ case FGA_RSLOCSW : ret = m_fga002[FGA_RSLOCSW]; LOG(("FGA_RSLOCSW returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX0 : ret = m_fga002[FGA_ICRMBOX0]; LOG(("FGA_ICRMBOX0 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX1 : ret = m_fga002[FGA_ICRMBOX1]; LOG(("FGA_ICRMBOX1 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX2 : ret = m_fga002[FGA_ICRMBOX2]; LOG(("FGA_ICRMBOX2 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX3 : ret = m_fga002[FGA_ICRMBOX3]; LOG(("FGA_ICRMBOX3 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX4 : ret = m_fga002[FGA_ICRMBOX4]; LOG(("FGA_ICRMBOX4 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX5 : ret = m_fga002[FGA_ICRMBOX5]; LOG(("FGA_ICRMBOX5 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX6 : ret = m_fga002[FGA_ICRMBOX6]; LOG(("FGA_ICRMBOX6 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRMBOX7 : ret = m_fga002[FGA_ICRMBOX7]; LOG(("FGA_ICRMBOX7 returns %02x - not implemented\n", ret)); break;
+ case FGA_VMEPAGE : ret = m_fga002[FGA_VMEPAGE]; LOG(("FGA_VMEPAGE returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME1 : ret = m_fga002[FGA_ICRVME1]; LOG(("FGA_ICRVME1 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME2 : ret = m_fga002[FGA_ICRVME2]; LOG(("FGA_ICRVME2 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME3 : ret = m_fga002[FGA_ICRVME3]; LOG(("FGA_ICRVME3 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME4 : ret = m_fga002[FGA_ICRVME4]; LOG(("FGA_ICRVME4 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME5 : ret = m_fga002[FGA_ICRVME5]; LOG(("FGA_ICRVME5 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME6 : ret = m_fga002[FGA_ICRVME6]; LOG(("FGA_ICRVME6 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRVME7 : ret = m_fga002[FGA_ICRVME7]; LOG(("FGA_ICRVME7 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRTIM0 : ret = m_fga002[FGA_ICRTIM0]; LOG(("FGA_ICRTIM0 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRDMANORM : ret = m_fga002[FGA_ICRDMANORM]; LOG(("FGA_ICRDMANORM returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRDMAERR : ret = m_fga002[FGA_ICRDMAERR]; LOG(("FGA_ICRDMAERR returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL1 : ret = m_fga002[FGA_CTL1]; LOG(("FGA_CTL1 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL2 : ret = m_fga002[FGA_CTL2]; LOG(("FGA_CTL2 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRFMB0REF : ret = m_fga002[FGA_ICRFMB0REF]; LOG(("FGA_ICRFMB0REF returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRFMB1REF : ret = m_fga002[FGA_ICRFMB1REF]; LOG(("FGA_ICRFMB1REF returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRFMB0MES : ret = m_fga002[FGA_ICRFMB0MES]; LOG(("FGA_ICRFMB0MES returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRFMB1MES : ret = m_fga002[FGA_ICRFMB1MES]; LOG(("FGA_ICRFMB1MES returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL3 : ret = m_fga002[FGA_CTL3]; LOG(("FGA_CTL3 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL4 : ret = m_fga002[FGA_CTL4]; LOG(("FGA_CTL4 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRPARITY : ret = m_fga002[FGA_ICRPARITY]; LOG(("FGA_ICRPARITY returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXPINCTL : ret = m_fga002[FGA_AUXPINCTL]; LOG(("FGA_AUXPINCTL returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL5 : ret = m_fga002[FGA_CTL5]; LOG(("FGA_CTL5 returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXFIFWEX : ret = m_fga002[FGA_AUXFIFWEX]; LOG(("FGA_AUXFIFWEX returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXFIFREX : ret = m_fga002[FGA_AUXFIFREX]; LOG(("FGA_AUXFIFREX returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL6 : ret = m_fga002[FGA_CTL6]; LOG(("FGA_CTL6 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL7 : ret = m_fga002[FGA_CTL7]; LOG(("FGA_CTL7 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL8 : ret = m_fga002[FGA_CTL8]; LOG(("FGA_CTL8 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL9 : ret = m_fga002[FGA_CTL9]; LOG(("FGA_CTL9 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRABORT : ret = m_fga002[FGA_ICRABORT]; LOG(("FGA_ICRABORT returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRACFAIL : ret = m_fga002[FGA_ICRACFAIL]; LOG(("FGA_ICRACFAIL returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRSYSFAIL : ret = m_fga002[FGA_ICRSYSFAIL]; LOG(("FGA_ICRSYSFAIL returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL0 : ret = m_fga002[FGA_ICRLOCAL0]; LOG(("FGA_ICRLOCAL0 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL1 : ret = m_fga002[FGA_ICRLOCAL1]; LOG(("FGA_ICRLOCAL1 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL2 : ret = m_fga002[FGA_ICRLOCAL2]; LOG(("FGA_ICRLOCAL2 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL3 : ret = m_fga002[FGA_ICRLOCAL3]; LOG(("FGA_ICRLOCAL3 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL4 : ret = m_fga002[FGA_ICRLOCAL4]; LOG(("FGA_ICRLOCAL4 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL5 : ret = m_fga002[FGA_ICRLOCAL5]; LOG(("FGA_ICRLOCAL5 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL6 : ret = m_fga002[FGA_ICRLOCAL6]; LOG(("FGA_ICRLOCAL6 returns %02x - not implemented\n", ret)); break;
+ case FGA_ICRLOCAL7 : ret = m_fga002[FGA_ICRLOCAL7]; LOG(("FGA_ICRLOCAL7 returns %02x - not implemented\n", ret)); break;
+ case FGA_ENAMCODE : ret = m_fga002[FGA_ENAMCODE]; LOG(("FGA_ENAMCODE returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL10 : ret = m_fga002[FGA_CTL10]; LOG(("FGA_CTL10 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL11 : ret = m_fga002[FGA_CTL11]; LOG(("FGA_CTL11 returns %02x - not implemented\n", ret)); break;
+ case FGA_MAINUM : ret = m_fga002[FGA_MAINUM]; LOG(("FGA_MAINUM returns %02x - not implemented\n", ret)); break;
+ case FGA_MAINUU : ret = m_fga002[FGA_MAINUU]; LOG(("FGA_MAINUU returns %02x - not implemented\n", ret)); break;
+ case FGA_BOTTOMPAGEU : ret = m_fga002[FGA_BOTTOMPAGEU]; LOG(("FGA_BOTTOMPAGEU returns %02x - not implemented\n", ret)); break;
+ case FGA_BOTTOMPAGEL : ret = m_fga002[FGA_BOTTOMPAGEL]; LOG(("FGA_BOTTOMPAGEL returns %02x - not implemented\n", ret)); break;
+ case FGA_TOPPAGEU : ret = m_fga002[FGA_TOPPAGEU]; LOG(("FGA_TOPPAGEU returns %02x - not implemented\n", ret)); break;
+ case FGA_TOPPAGEL : ret = m_fga002[FGA_TOPPAGEL]; LOG(("FGA_TOPPAGEL returns %02x - not implemented\n", ret)); break;
+ case FGA_MYVMEPAGE : ret = m_fga002[FGA_MYVMEPAGE]; LOG(("FGA_MYVMEPAGE returns %02x - not implemented\n", ret)); break;
+ case FGA_TIM0PRELOAD : ret = m_fga002[FGA_TIM0PRELOAD]; LOG(("FGA_TIM0PRELOAD returns %02x - not implemented\n", ret)); break;
+ case FGA_TIM0CTL : ret = m_fga002[FGA_TIM0CTL]; LOG(("FGA_TIM0CTL returns %02x - not implemented\n", ret)); break;
+ case FGA_DMASRCATT : ret = m_fga002[FGA_DMASRCATT]; LOG(("FGA_DMASRCATT returns %02x - not implemented\n", ret)); break;
+ case FGA_DMADSTATT : ret = m_fga002[FGA_DMADSTATT]; LOG(("FGA_DMADSTATT returns %02x - not implemented\n", ret)); break;
+ case FGA_DMA_GENERAL : ret = m_fga002[FGA_DMA_GENERAL]; LOG(("FGA_DMA_GENERAL returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL12 : ret = m_fga002[FGA_CTL12]; LOG(("FGA_CTL12 returns %02x - not implemented\n", ret)); break;
+ case FGA_LIOTIMING : ret = m_fga002[FGA_LIOTIMING]; LOG(("FGA_LIOTIMING returns %02x - not implemented\n", ret)); break;
+ case FGA_LOCALIACK : ret = m_fga002[FGA_LOCALIACK]; LOG(("FGA_LOCALIACK returns %02x - not implemented\n", ret)); break;
+ case FGA_FMBCTL : ret = m_fga002[FGA_FMBCTL]; LOG(("FGA_FMBCTL returns %02x - not implemented\n", ret)); break;
+ case FGA_FMBAREA : ret = m_fga002[FGA_FMBAREA]; LOG(("FGA_FMBAREA returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXSRCSTART : ret = m_fga002[FGA_AUXSRCSTART]; LOG(("FGA_AUXSRCSTART returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXDSTSTART : ret = m_fga002[FGA_AUXDSTSTART]; LOG(("FGA_AUXDSTSTART returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXSRCTERM : ret = m_fga002[FGA_AUXSRCTERM]; LOG(("FGA_AUXSRCTERM returns %02x - not implemented\n", ret)); break;
+ case FGA_AUXDSTTERM : ret = m_fga002[FGA_AUXDSTTERM]; LOG(("FGA_AUXDSTTERM returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL13 : ret = m_fga002[FGA_CTL13]; LOG(("FGA_CTL13 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break;
+ case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break;
+ case FGA_ISTIM0 : ret = m_fga002[FGA_ISTIM0]; LOG(("FGA_ISTIM0 returns %02x - not implemented\n", ret)); break;
+ case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break;
+ case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break;
+ case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break;
+ case FGA_ISFMB1REF : ret = m_fga002[FGA_ISFMB1REF]; LOG(("FGA_ISFMB1REF returns %02x - not implemented\n", ret)); break;
+ case FGA_ISPARITY : ret = m_fga002[FGA_ISPARITY]; LOG(("FGA_ISPARITY returns %02x - not implemented\n", ret)); break;
+ case FGA_DMARUNCTL : ret = m_fga002[FGA_DMARUNCTL]; LOG(("FGA_DMARUNCTL returns %02x - not implemented\n", ret)); break;
+ case FGA_ISABORT : ret = m_fga002[FGA_ISABORT]; LOG(("FGA_ISABORT returns %02x - not implemented\n", ret)); break;
+ case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break;
+ case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break;
+ case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break;
default:
LOG(("Unsupported register %04x\n", offset));
}
return ret;
}
-/*
+/*
* Rotary Switches - to configure the board
*
* Table 25: PI/T #1 Interface Signals
@@ -625,20 +624,20 @@ READ8_MEMBER (fccpu30_state::fga8_r){
* PA4 PA7 SW2 In
*
* Table 38: Upper Rotary Switch (SW2)
- * Bit 3: This bit indicates whether the RAM disk should be initialized after reset. If this bit is set to "0" (settings 0-7),
- * the RAM disk is initialized as defined by bit 0 and 1. When the disk is initialized, all data on the disk is lost.
- * Bit 2: This bit defines the default data size on the VMEbus. If the bit is set to "0", 16 bits are selected, if it is set
+ * Bit 3: This bit indicates whether the RAM disk should be initialized after reset. If this bit is set to "0" (settings 0-7),
+ * the RAM disk is initialized as defined by bit 0 and 1. When the disk is initialized, all data on the disk is lost.
+ * Bit 2: This bit defines the default data size on the VMEbus. If the bit is set to "0", 16 bits are selected, if it is set
* to "1", 32 bits are selected.
* Bit 1 and Bit 0: These two bits define the default RAM disk. See Table 40, "RAM Disk Usage," a detailed description.
- * If AUTOBOOT is set by bit 2 and 3 of SW1, bit 1 and 0 of SW2 define which operating system will be booted. See Table 42,
+ * If AUTOBOOT is set by bit 2 and 3 of SW1, bit 1 and 0 of SW2 define which operating system will be booted. See Table 42,
* "Boot an Operating System (if AUTOBOOT is selected)," on page 129 for detailed description.
*
* Table 39: Lower Rotary Switch (SW1)
* Bit 3 and Bit 2: These two bits define which program is to be invoked after reset. Please refer
* to Table 41, "Program After Reset," on page 129 for a detailed description.
- * Bit 1: If this switch is "0" (settings 0,1,4,5,8,9,C,D), VMEPROM tries to execute a start-up file after reset. The default
+ * Bit 1: If this switch is "0" (settings 0,1,4,5,8,9,C,D), VMEPROM tries to execute a start-up file after reset. The default
* filename is SY$STRT. If the bit is "1", VMEPROM comes up with the default banner.
- * Bit 0: If this switch is set to "0" (settings 0,2,4,6,8,A,C,E), VMEPROM checks the VMEbus for available hardware after reset.
+ * Bit 0: If this switch is set to "0" (settings 0,2,4,6,8,A,C,E), VMEPROM checks the VMEbus for available hardware after reset.
* In addition VMEPROM waits for SYSFAIL to disappear from the VMEbus. The following hardware can be detected:
* - Contiguous memory
* - ASCU-1/2
@@ -655,20 +654,20 @@ READ8_MEMBER (fccpu30_state::fga8_r){
* 0 0 RAM DISK AT 0x4080 0000 (512 Kbytes) 0,4,8,C
*
* Table 41: Program After Reset
- * Bit 3 Bit 2 Lower Switch (SW 1) selected on
- * 1 1 VMEPROM C,D,E,F
- * 1 0 USER PROGRAM AT 0x4070 0000 8,9,A,B
- * 0 1 AUTOBOOT SYSTEM 4,5,6,7
- * 0 0 USER PROGRAM AT 4080.000016 0,1,2,3
+ * Bit 3 Bit 2 Lower Switch (SW 1) selected on
+ * 1 1 VMEPROM C,D,E,F
+ * 1 0 USER PROGRAM AT 0x4070 0000 8,9,A,B
+ * 0 1 AUTOBOOT SYSTEM 4,5,6,7
+ * 0 0 USER PROGRAM AT 4080.000016 0,1,2,3
*
* Table 42: Boot an Operating System (if AUTOBOOT is selected)
- * Bit 1 Bit 0 Upper Switch (SW 2) selected on
- * 1 1 reserved 3,7,B,F
- * 1 0 Boot UNIX/PDOS 4.x 2,6,A,E
- * 0 1 Boot another operating system 1,5,9,D
- * 0 0 Setup for UNIX mailbox driver 0,4,8,C
+ * Bit 1 Bit 0 Upper Switch (SW 2) selected on
+ * 1 1 reserved 3,7,B,F
+ * 1 0 Boot UNIX/PDOS 4.x 2,6,A,E
+ * 0 1 Boot another operating system 1,5,9,D
+ * 0 0 Setup for UNIX mailbox driver 0,4,8,C
*
- * "To start VMEPROM, the rotary switches must both be set to 'F':" Hmm...
+ * "To start VMEPROM, the rotary switches must both be set to 'F':" Hmm...
*/
READ8_MEMBER (fccpu30_state::rotary_rd){
LOG(("%s\n", FUNCNAME));
@@ -676,18 +675,18 @@ READ8_MEMBER (fccpu30_state::rotary_rd){
}
/*
- * PI/T #2 Factory settings
+ * PI/T #2 Factory settings
* B0-B2 Shared Memory Size - From these lines, the on-board Shared RAM capacity can be read in by software.
* 0 0 0 32 Mb
* 0 0 1 16 Mb
* 0 1 0 8 Mb
* 0 1 1 4 Mb
* 1 x x Reserved
- * B3-B7 Board ID(s) - From these lines, the CPU board identification number can be read in by
- * 0 1 0 1 0 CPU-30 R4 software. Every CPU board has a unique number. Different versions of
- * (fill in more) one CPU board (i.e. different speeds, capacity of memory, or modules)
- * contain the same identification number. In the case of the CPU-30 R4, the
- * number is ten ("10" decimal or 0A16 hexadecimal "01010" binary).
+ * B3-B7 Board ID(s) - From these lines, the CPU board identification number can be read in by
+ * 0 1 0 1 0 CPU-30 R4 software. Every CPU board has a unique number. Different versions of
+ * (fill in more) one CPU board (i.e. different speeds, capacity of memory, or modules)
+ * contain the same identification number. In the case of the CPU-30 R4, the
+ * number is ten ("10" decimal or 0A16 hexadecimal "01010" binary).
*/
READ8_MEMBER (fccpu30_state::board_mem_id_rd){
LOG(("%s\n", FUNCNAME));
@@ -734,7 +733,7 @@ static MACHINE_CONFIG_START (fccpu30, fccpu30_state)
MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, rxa_w))
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, ctsa_w))
-// MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
+// MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
MCFG_DEVICE_ADD ("pit1", PIT68230, XTAL_16MHz / 2)
@@ -747,9 +746,9 @@ MACHINE_CONFIG_END
ROM_START (fccpu30)
ROM_REGION32_BE(0xfff00000, "maincpu", 0)
-ROM_LOAD16_BYTE("CPU30LO.BIN", 0xff000000, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9))
-ROM_LOAD16_BYTE("CPU30UP.BIN", 0xff000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8))
-ROM_LOAD("PGA-002.BIN", 0xffe00000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919))
+ROM_LOAD16_BYTE("CPU30LO.BIN", 0xff000000, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9))
+ROM_LOAD16_BYTE("CPU30UP.BIN", 0xff000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8))
+ROM_LOAD("PGA-002.BIN", 0xffe00000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919))
/*
* System ROM information
@@ -784,8 +783,8 @@ ROM_LOAD("PGA-002.BIN", 0xffe00000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a86
* 05 3d -> REG_TTR - Tx BRG 9600 (assuming a 14.7456 crystal)
* 07 2d -> REG_RTR - Rx BRG 9600 (assuming a 14.7456 crystal)
* 0e 27 -> REG_PCR - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
- * 0b f1 -> REG_OMR - RTS low, OUT1 = OUT2 = high, RxRdy asserted for each character,
- * TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
+ * 0b f1 -> REG_OMR - RTS low, OUT1 = OUT2 = high, RxRdy asserted for each character,
+ * TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
* 0f 00 -> REG_CCR - reset Tx Command
* 0f 40 -> REG_CCR - reset Rx Command
* 0f 02 -> REG_CCR - enable Tx Command
diff --git a/src/mame/drivers/fidel6502.cpp b/src/mame/drivers/fidel6502.cpp
index 0cec6776c1b..fc5ff5bc010 100644
--- a/src/mame/drivers/fidel6502.cpp
+++ b/src/mame/drivers/fidel6502.cpp
@@ -4,7 +4,7 @@
/******************************************************************************
Fidelity Electronics 6502 based board driver
-
+
TODO:
- EAS doesn't work, there's some activity if you boot/reset with 1-key held down
@@ -578,7 +578,7 @@ WRITE8_MEMBER(fidel6502_state::eas_ppi_portc_w)
// d0-d3: input/led mux
m_led_select = data & 0xf;
csc_prepare_display();
-
+
// other: ?
}
@@ -1322,7 +1322,7 @@ static MACHINE_CONFIG_START( eas, fidel6502_state )
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( su9, csc )
-
+
/* basic machine hardware */
MCFG_CPU_REPLACE("maincpu", M6502, 2000000) // same as csc?
MCFG_CPU_PROGRAM_MAP(su9_map)
diff --git a/src/mame/drivers/funkball.cpp b/src/mame/drivers/funkball.cpp
index 44eb87d26ec..601b7e14a5c 100644
--- a/src/mame/drivers/funkball.cpp
+++ b/src/mame/drivers/funkball.cpp
@@ -228,7 +228,7 @@ WRITE8_MEMBER( funkball_state::serial_w )
{
if(offset == 0)
{
- // TODO: hack, main CPU sends a CR only here, actually expecting Windows-style newline.
+ // TODO: hack, main CPU sends a CR only here, actually expecting Windows-style newline.
if(data == 0x0d)
m_terminal->write(space,0,0x0a);
else
@@ -839,7 +839,7 @@ static MACHINE_CONFIG_START( funkball, funkball_state )
MCFG_SCREEN_VISIBLE_AREA(0, 511, 16, 447)
MCFG_DEVICE_ADD("terminal", GENERIC_TERMINAL, 0)
-
+
MCFG_INTEL_28F320J5_ADD("u29")
MCFG_INTEL_28F320J5_ADD("u30")
MCFG_INTEL_28F320J5_ADD("u3")
diff --git a/src/mame/drivers/galaxian.cpp b/src/mame/drivers/galaxian.cpp
index 1d6390e9169..81b4bad535e 100644
--- a/src/mame/drivers/galaxian.cpp
+++ b/src/mame/drivers/galaxian.cpp
@@ -2112,7 +2112,7 @@ static ADDRESS_MAP_START( takeoff_sound_portmap, AS_IO, 8, galaxian_state )
AM_RANGE(0x40, 0x40) AM_DEVWRITE("8912", ay8912_device, address_w)
AM_RANGE(0x80, 0x80) AM_DEVREADWRITE("8912", ay8912_device, data_r, data_w)
ADDRESS_MAP_END
-
+
/* King and Balloon with DAC */
static ADDRESS_MAP_START( kingball_sound_map, AS_PROGRAM, 8, galaxian_state )
ADDRESS_MAP_UNMAP_HIGH
diff --git a/src/mame/drivers/galivan.cpp b/src/mame/drivers/galivan.cpp
index 32edd23bf72..4b5e8b109b3 100644
--- a/src/mame/drivers/galivan.cpp
+++ b/src/mame/drivers/galivan.cpp
@@ -23,14 +23,14 @@ TODO
- bit 3 of ninjemak_gfxbank_w, there currently is a kludge to clear text RAM
but it should really copy stuff from the extra ROM.
- Ninja Emaki has minor protection issues, see NB1414M4 simulation for more info.
-- dangarj has unemulated protection at I/Os 0x80-1 for missing sprites.
+- dangarj has unemulated protection at I/Os 0x80-1 for missing sprites.
[0x80] W is data
[0x81] W --11 xxxx address
[0x80] R result
The protection is used for a code snippet at 0xf9c0, that of course is the
- sprite handling. The code snippet is sum8 with 0x27 at 0x9d74 so no, the
+ sprite handling. The code snippet is sum8 with 0x27 at 0x9d74 so no, the
later dangar US version snippet doesn't work ...
-
+
***************************************************************************/
#include "emu.h"
@@ -721,7 +721,7 @@ ROM_START( dangarb ) /* all rom labels are simply numbers, with the owl logo and
ROM_REGION( 0x10000, "audiocpu", 0 ) /* sound cpu code */
ROM_LOAD( "13.14b", 0x0000, 0x4000, CRC(3e041873) SHA1(8f9e1ec64509c8a7e9e45add9efc95f98f35fcfc) )
ROM_LOAD( "14.15b", 0x4000, 0x8000, CRC(488e3463) SHA1(73ff7ab061be54162f3a548f6bd9ef55b9dec5d9) )
-
+
ROM_REGION( 0x04000, "gfx1", 0 )
ROM_LOAD( "11.13d", 0x00000, 0x4000, CRC(e804ffe1) SHA1(22f16c23b9a82f104dda24bc8fccc08f3f69cf97) ) /* chars */
@@ -758,7 +758,7 @@ ROM_START( dangarj ) /* all rom labels are simply numbers, with the owl logo and
ROM_REGION( 0x10000, "audiocpu", 0 ) /* sound cpu code */
ROM_LOAD( "21.14b", 0x0000, 0x4000, CRC(3e041873) SHA1(8f9e1ec64509c8a7e9e45add9efc95f98f35fcfc) )
ROM_LOAD( "22.15b", 0x4000, 0x4000, CRC(1d484f68) SHA1(7de13d6c6850280fed011c1d1b211cdc5ea9f935) )
-
+
ROM_REGION( 0x04000, "gfx1", 0 )
ROM_LOAD( "11.13d", 0x00000, 0x4000, CRC(e804ffe1) SHA1(22f16c23b9a82f104dda24bc8fccc08f3f69cf97) ) /* chars */
diff --git a/src/mame/drivers/gba.cpp b/src/mame/drivers/gba.cpp
index 54a2ca5527f..b58253c03b2 100644
--- a/src/mame/drivers/gba.cpp
+++ b/src/mame/drivers/gba.cpp
@@ -2258,8 +2258,8 @@ void gba_state::machine_start()
static SLOT_INTERFACE_START(gba_cart)
SLOT_INTERFACE_INTERNAL("gba_rom", GBA_ROM_STD)
SLOT_INTERFACE_INTERNAL("gba_sram", GBA_ROM_SRAM)
- SLOT_INTERFACE_INTERNAL("gba_drilldoz", GBA_ROM_DRILLDOZ) // Rumble output unemulated
- SLOT_INTERFACE_INTERNAL("gba_wariotws", GBA_ROM_WARIOTWS) // Rumble output unemulated
+ SLOT_INTERFACE_INTERNAL("gba_drilldoz", GBA_ROM_DRILLDOZ) // Rumble output unemulated
+ SLOT_INTERFACE_INTERNAL("gba_wariotws", GBA_ROM_WARIOTWS) // Rumble output unemulated
SLOT_INTERFACE_INTERNAL("gba_eeprom", GBA_ROM_EEPROM)
SLOT_INTERFACE_INTERNAL("gba_eeprom_4k", GBA_ROM_EEPROM)
SLOT_INTERFACE_INTERNAL("gba_yoshiug", GBA_ROM_YOSHIUG)
diff --git a/src/mame/drivers/go2000.cpp b/src/mame/drivers/go2000.cpp
index 90391a01e20..a9d5e47d241 100644
--- a/src/mame/drivers/go2000.cpp
+++ b/src/mame/drivers/go2000.cpp
@@ -62,7 +62,7 @@ public:
required_device<screen_device> m_screen;
required_device<palette_device> m_palette;
required_device<generic_latch_8_device> m_soundlatch;
-
+
DECLARE_WRITE16_MEMBER(sound_cmd_w);
DECLARE_WRITE8_MEMBER(go2000_pcm_1_bankswitch_w);
virtual void machine_start() override;
diff --git a/src/mame/drivers/goldnpkr.cpp b/src/mame/drivers/goldnpkr.cpp
index 860b7dd0a55..51391adfe19 100644
--- a/src/mame/drivers/goldnpkr.cpp
+++ b/src/mame/drivers/goldnpkr.cpp
@@ -4969,7 +4969,7 @@ ROM_END
Golden Poker derivative, with blue killer circuitry.
Suitable for "Good Luck" and "Buena Suerte" games.
Addressing, ROM banks, and edge connector close to Magic Fly.
-
+
Discrete sound need to be traced...
30x2-pins Edge connector + 10-pin connector.
@@ -4983,7 +4983,7 @@ ROM_END
+5V. | 01 | +5V.
(GND) Speaker- | 02 | Speaker- (GND)
| 03 | Speaker+
- | 04 |
+ | 04 |
| |
Sync | 05 | Red
Green | 06 | Blue
@@ -5007,8 +5007,8 @@ ROM_END
Common D (4) | 21 | Common B (2)
| |
| 22 | n/c (5)
- | 23 |
- | 24 |
+ | 23 |
+ | 24 |
| |
GND | 25 | GND
+12VAC. | 26 | +12VAC.
@@ -5020,10 +5020,10 @@ ROM_END
(0) 12V. AV *IN*: for lamps, audio, and mech counters.
- (1) =
- (2) =
- (3) =
- (4) =
+ (1) =
+ (2) =
+ (3) =
+ (4) =
Note: Each Common GND (A-B-C-D) are for their respective
Multiplexed groups of inputs, since there are 4 groups
@@ -5038,10 +5038,10 @@ ROM_END
** 10-pin connector **
Only the last 4 have a male connector. The rest are just marked on the PCB.
-
+
0000000000
++++
- ||||
+ ||||
|||'-- Out Mech Counter.
||'--- Out Mech Counter.
|'---- n/c (is routed to a place where another transistor could be mounted).
diff --git a/src/mame/drivers/goldstar.cpp b/src/mame/drivers/goldstar.cpp
index 724d243e33f..50c05729146 100644
--- a/src/mame/drivers/goldstar.cpp
+++ b/src/mame/drivers/goldstar.cpp
@@ -7455,8 +7455,8 @@ static const gfx_layout cb3c_tiles8x32_layout =
{ 0, 1, 2, 3 },
{ 4, 0, 12, 8, 20, 16, 28, 24 },
{ 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32, 8*32, 9*32, 10*32, 11*32, 12*32,
- 13*32, 14*32, 15*32, 16*32, 17*32, 18*32, 19*32, 20*32, 21*32, 22*32, 23*32,
- 24*32, 25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32 },
+ 13*32, 14*32, 15*32, 16*32, 17*32, 18*32, 19*32, 20*32, 21*32, 22*32, 23*32,
+ 24*32, 25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32 },
32*32
};
@@ -7541,9 +7541,9 @@ static const gfx_layout flaming7_tilelayout =
{ 0, 2, 4, 6 },
{ 2*8+0, 2*8+1, 3*8+0, 3*8+1, 0, 1, 1*8+0, 1*8+1 },
{ 0*8, 4*8, 8*8, 12*8, 16*8, 20*8, 24*8, 28*8,
- 32*8, 36*8, 40*8, 44*8, 48*8, 52*8, 56*8, 60*8,
- 64*8, 68*8, 72*8, 76*8, 80*8, 84*8, 88*8, 92*8,
- 96*8, 100*8, 104*8, 108*8, 112*8, 116*8, 120*8, 124*8 },
+ 32*8, 36*8, 40*8, 44*8, 48*8, 52*8, 56*8, 60*8,
+ 64*8, 68*8, 72*8, 76*8, 80*8, 84*8, 88*8, 92*8,
+ 96*8, 100*8, 104*8, 108*8, 112*8, 116*8, 120*8, 124*8 },
128*8 /* every char takes 128 consecutive bytes */
};
@@ -7566,9 +7566,9 @@ static const gfx_layout flam7_tw_tilelayout = // FIXME
{ 0, 2, 4, 6 },
{ 3*8+0, 3*8+1, 2*8+0, 1*8+0, 1*8+1, 2*8+1, 0, 1 },
{ 0*8, 4*8, 8*8, 12*8, 16*8, 20*8, 24*8, 28*8,
- 32*8, 36*8, 40*8, 44*8, 48*8, 52*8, 56*8, 60*8,
- 64*8, 68*8, 72*8, 76*8, 80*8, 84*8, 88*8, 92*8,
- 96*8, 100*8, 104*8, 108*8, 112*8, 116*8, 120*8, 124*8 },
+ 32*8, 36*8, 40*8, 44*8, 48*8, 52*8, 56*8, 60*8,
+ 64*8, 68*8, 72*8, 76*8, 80*8, 84*8, 88*8, 92*8,
+ 96*8, 100*8, 104*8, 108*8, 112*8, 116*8, 120*8, 124*8 },
128*8 /* every char takes 128 consecutive bytes */
};
@@ -7695,8 +7695,8 @@ static const gfx_layout tiles8x32_4bpp_layout =
{ RGN_FRAC(0,4), RGN_FRAC(1,4), RGN_FRAC(2,4), RGN_FRAC(3,4) },
{ 0, 1, 2, 3, 4, 5, 6, 7},
{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8, 9*8, 10*8, 11*8, 12*8,
- 13*8, 14*8, 15*8, 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
- 24*8, 25*8, 26*8, 27*8, 28*8, 29*8, 30*8, 31*8 },
+ 13*8, 14*8, 15*8, 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
+ 24*8, 25*8, 26*8, 27*8, 28*8, 29*8, 30*8, 31*8 },
32*8
};
@@ -7812,8 +7812,8 @@ static const gfx_layout cm97_layout32 =
{ 0,1,2,3 },
{ 8,12,0,4,24,28, 16,20 },
{ 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32, 8*32, 9*32, 10*32, 11*32,
- 12*32, 13*32, 14*32, 15*32, 16*32, 17*32, 18*32, 19*32, 20*32, 21*32,
- 22*32, 23*32, 24*32, 25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32 },
+ 12*32, 13*32, 14*32, 15*32, 16*32, 17*32, 18*32, 19*32, 20*32, 21*32,
+ 22*32, 23*32, 24*32, 25*32, 26*32, 27*32, 28*32, 29*32, 30*32, 31*32 },
32*32
};
@@ -8419,7 +8419,7 @@ static MACHINE_CONFIG_DERIVED( flaming7, lucky8 )
MCFG_GFXDECODE_MODIFY("gfxdecode", flaming7)
- // to do serial protection.
+ // to do serial protection.
MCFG_DEVICE_MODIFY("ppi8255_0")
MCFG_I8255_OUT_PORTC_CB(WRITE8(wingco_state, fl7w4_outc802_w))
@@ -8433,7 +8433,7 @@ static MACHINE_CONFIG_DERIVED( flam7_tw, lucky8 )
MCFG_GFXDECODE_MODIFY("gfxdecode", flam7_tw)
- // to do serial protection.
+ // to do serial protection.
MCFG_DEVICE_MODIFY("ppi8255_0")
MCFG_I8255_OUT_PORTC_CB(WRITE8(wingco_state, fl7w4_outc802_w))
@@ -14308,7 +14308,7 @@ ROM_END
Graphics: 4 different types, selectable through DIP switches.
1) Regular Fruits.
- 2) Numbers. (Custom Option 1 in W-4 HW)
+ 2) Numbers. (Custom Option 1 in W-4 HW)
3) Custom Set 1 (Custom Option 2 in W-4 HW)
4) Custom Set 2 (Custom Option 3 in W-4 HW)
@@ -14455,7 +14455,7 @@ ROM_END
| PAPER LOW SENSOR | OFF | | | | | OFF | OFF | OFF | OFF |
| | ON | | | | | ON | OFF | OFF | OFF |
+------------------+----------------+-----+-----+-----+-----+-----+-----+-----+-----+
-
+
NOTE: Set bill validator DIP switches for 1 pulse per dollar. When you choose the
demonation with the DIP switch on the board, the software will know how many
@@ -14567,15 +14567,15 @@ ROM_END
Button Lock |15|51|
|16|52|
|17|53|
- (DBA) Inuput0 |18|54| Coin Switch “A”
- Coin Switch “B” |19|55|
+ (DBA) Inuput0 |18|54| Coin Switch "A"
+ Coin Switch "B" |19|55|
Book Keeping Switch |20|56| Stats / Setup SW
Collect SW |21|57|
Hopper Full Switch |22|58|
- Counter Out “A” |23|59|
+ Counter Out "A" |23|59|
Bell |24|60| Lockout mars (DBA)
Tower Lamp |25|61|
- Counter Out “D” |26|62|
+ Counter Out "D" |26|62|
Played Meter |27|63| Lack of Hopper Counter
Count down Meter Out |28|64|
Start Lamp |29|65|
@@ -14641,10 +14641,10 @@ ROM_END
2) Pin 39 from solder side (speaker GND) and pin 04 from components side (PPI 8255 pin 11, PC6)
are wired with a DS2401 (sillicon serial number) device, to pins 1 & 2 (GND & DATA).
-
- DS2401 has 64bits of internal data: 8 bits for family type + 48 bits for serial + 8 bits for CRC.
- Maxim/Dallas 1-Wire devices use what is called Dow CRC to check that the data bytes were received correctly.
+ DS2401 has 64bits of internal data: 8 bits for family type + 48 bits for serial + 8 bits for CRC.
+
+ Maxim/Dallas 1-Wire devices use what is called Dow CRC to check that the data bytes were received correctly.
This returns an 8-bit CRC value as the last byte and uses a polynomial of X^8 + X^5 + X^4 + X^0.
3) Z80 /INT line (pin 16) is out of socket and wired to a 74161.
@@ -14658,9 +14658,9 @@ ROM_END
Seems that there is an extra layer for the bonus graphics.
This graphic is taken from Bank 2, and is the "representative"
for the chosen gfx set.
-
+
Code writes the bonus graphics at 9A80-9A89, and the "reel scroll"
- at B0C0-B0FF...
+ at B0C0-B0FF...
Tileset:
Reels GFX 1: 00-00-01-02-03-04-05-06-07-00
@@ -14730,7 +14730,7 @@ ROM_END
Main - 50.
Custom Hardware.
-*/
+*/
ROM_START( fl7_50 ) // Serial 00000069A1C9.
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "50-main.u22", 0x0000, 0x8000, CRC(e097e317) SHA1(a903144cc2290b7e22045490784b592adbf9ba97) )
@@ -14762,7 +14762,7 @@ ROM_END
Main - 500.
Custom Hardware.
-*/
+*/
ROM_START( fl7_500 ) // Serial 000000125873.
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "500-main.u22", 0x0000, 0x8000, CRC(e2c82c67) SHA1(951b0044de9b6104f51aa5a3176d0ea475415f7c) )
@@ -14794,7 +14794,7 @@ ROM_END
Main - 2000.
Custom Hardware.
-*/
+*/
ROM_START( fl7_2000 ) // Serial 00000063A47F.
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "2000_main_27c256.u22", 0x0000, 0x8000, CRC(9659b045) SHA1(801b6733b70b35de65cd8faba6814fa013c05ad0) )
@@ -14826,7 +14826,7 @@ ROM_END
2000 Bonus. Egyptian Gold.
Custom Hardware.
-*/
+*/
ROM_START( fl7_2k16 ) // Serial 000000743111.
ROM_REGION( 0x8000, "maincpu", 0 )
ROM_LOAD( "2000_bonus_27c256.u22", 0x0000, 0x8000, CRC(290c37b0) SHA1(a90093d2139fd5ca261870298c2d84648f14e6bc) )
@@ -14857,7 +14857,7 @@ ROM_END
Needs proper graphics ROM decryption and gfxdecode...
-*/
+*/
ROM_START( fl7_tw ) // Serial 00000050E9B7.
ROM_REGION( 0x10000, "maincpu", 0 )
ROM_LOAD( "27c512_tw.u20", 0x0000, 0x10000, CRC(50927a1b) SHA1(2557069f497b23f13978294f3ac108229d9db544) ) // identical halves.
@@ -15532,7 +15532,7 @@ DRIVER_INIT_MEMBER(goldstar_state, wcherry)
/*
Flaming 7's
Cyberdyne Systems.
-
+
Original custom hardware graphics decryption.
*/
@@ -15557,7 +15557,7 @@ DRIVER_INIT_MEMBER(wingco_state, flaming7)
/*
Flaming 7's
Cyberdyne Systems.
-
+
Taiwanese custom hardware.
*/
diff --git a/src/mame/drivers/halleys.cpp b/src/mame/drivers/halleys.cpp
index b3e99df85f6..77ed4220bc6 100644
--- a/src/mame/drivers/halleys.cpp
+++ b/src/mame/drivers/halleys.cpp
@@ -515,7 +515,7 @@ if (0) {
{
if (!(flags & IGNORE_0)) BLOCK_WIPE_COMMON
- dst_ptr += wclip;
+ dst_ptr += wclip;
ecx = wclip = -wclip;
edx = src_dx;
@@ -539,7 +539,7 @@ if (0) {
while (--hclip);
}
else
- {
+ {
do {
do {
al |= *src1_ptr;
@@ -605,7 +605,7 @@ if (0) {
if ((flags & (RGB_MASK | COLOR_ON)) == RGB_MASK + COLOR_ON)
{
if (!(flags & IGNORE_0)) BLOCK_WIPE_COMMON
- dst_ptr += wclip;
+ dst_ptr += wclip;
ecx = wclip = -wclip;
al = ah = (UINT8)pen0;
ebx = rgbmask[color & PENCOLOR] | 0xffffff00;
@@ -708,7 +708,7 @@ if (0) {
//--------------------------------------------------------------------------
- // End of Standard Mode
+ // End of Standard Mode
return;
//--------------------------------------------------------------------------
diff --git a/src/mame/drivers/hh_cop400.cpp b/src/mame/drivers/hh_cop400.cpp
index 2cfa00446c6..6de25264e24 100644
--- a/src/mame/drivers/hh_cop400.cpp
+++ b/src/mame/drivers/hh_cop400.cpp
@@ -999,7 +999,7 @@ MACHINE_CONFIG_END
Milton Bradley Electronic Battleship (1982 version)
* COP420 MCU label COP420-JWE/N
-
+
see hh_tms1k.cpp bship driver for more information
***************************************************************************/
diff --git a/src/mame/drivers/hh_tms1k.cpp b/src/mame/drivers/hh_tms1k.cpp
index cc0b1d20468..e938077bd29 100644
--- a/src/mame/drivers/hh_tms1k.cpp
+++ b/src/mame/drivers/hh_tms1k.cpp
@@ -3722,7 +3722,7 @@ MACHINE_CONFIG_END
This is a 2-player electronic board game. It still needs game pieces like the
original Battleship board game.
-
+
It went through 3 hardware revisions:
1977: model 4750A or B, see notes above
1979: model 4750C: cost-reduced single chip design, lesser quality game board.
@@ -5759,10 +5759,10 @@ MACHINE_CONFIG_END
U.S. Games Super Sports-4
* TMS1100 MP1219 (no decap)
* 4 7seg LEDs, 49 other LEDs, 1-bit sound
-
+
This handheld includes 4 games: Basketball, Football, Soccer, Hockey.
MAME external artwork is needed for the switchable overlays.
-
+
The later Coleco Total Control 4 is clearly based on this.
***************************************************************************/
@@ -5786,7 +5786,7 @@ void ssports4_state::prepare_display()
{
// R0,R1 and R8,R9 are 7segs
set_display_segmask(0x303, 0x7f);
-
+
// note: R2 is an extra column
display_matrix(9, 10, m_o | (m_r << 6 & 0x100), m_r);
}
@@ -5795,7 +5795,7 @@ WRITE16_MEMBER(ssports4_state::write_r)
{
// R10: speaker out
m_speaker->level_w(data >> 10 & 1);
-
+
// R0-R9: led select/data
m_r = data;
prepare_display();
diff --git a/src/mame/drivers/holeland.cpp b/src/mame/drivers/holeland.cpp
index d6f173e6948..54f19c3f6ed 100644
--- a/src/mame/drivers/holeland.cpp
+++ b/src/mame/drivers/holeland.cpp
@@ -124,12 +124,12 @@ static INPUT_PORTS_START( holeland )
INPUT_PORTS_END
static INPUT_PORTS_START( holeland2 )
- PORT_INCLUDE( holeland )
+ PORT_INCLUDE( holeland )
- PORT_MODIFY("DSW1")
- PORT_DIPNAME( 0x04, 0x04, DEF_STR( Language ) )
+ PORT_MODIFY("DSW1")
+ PORT_DIPNAME( 0x04, 0x04, DEF_STR( Language ) )
PORT_DIPSETTING( 0x00, DEF_STR( English ) )
- PORT_DIPSETTING( 0x04, DEF_STR( Spanish ) )
+ PORT_DIPSETTING( 0x04, DEF_STR( Spanish ) )
INPUT_PORTS_END
static INPUT_PORTS_START( crzrally )
diff --git a/src/mame/drivers/homedata.cpp b/src/mame/drivers/homedata.cpp
index e5153d72ca9..716a5b0f0aa 100644
--- a/src/mame/drivers/homedata.cpp
+++ b/src/mame/drivers/homedata.cpp
@@ -156,7 +156,7 @@ Board: X73-PWB-A(C)
CPU: 6809 uPC324C
Sound: SN76489
OSC: 16.000MHz 9.000MHz
-ROM: 28 pin mask rom devices are 1mbit, 32 pin are 2mbit.
+ROM: 28 pin mask rom devices are 1mbit, 32 pin are 2mbit.
----------------------------------------------------------------------------
Mahjong Vitamin C
@@ -971,33 +971,33 @@ INPUT_PORTS_END
static INPUT_PORTS_START( mjjoship )
PORT_INCLUDE( pteacher )
-
+
PORT_MODIFY("DSW")
// SW1
- PORT_DIPNAME( 0x0001, 0x0000, "Attract Sound" ) PORT_DIPLOCATION("SW1:1")
- PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_DIPNAME( 0x0001, 0x0000, "Attract Sound" ) PORT_DIPLOCATION("SW1:1")
+ PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW1:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW1:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW1:4" )
- PORT_DIPNAME( 0x0010, 0x0010, "Player Start Score" ) PORT_DIPLOCATION("SW1:5")
- PORT_DIPSETTING( 0x0010, "1000" )
- PORT_DIPSETTING( 0x0000, "2000" )
+ PORT_DIPNAME( 0x0010, 0x0010, "Player Start Score" ) PORT_DIPLOCATION("SW1:5")
+ PORT_DIPSETTING( 0x0010, "1000" )
+ PORT_DIPSETTING( 0x0000, "2000" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW1:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW1:7" )
- PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
- PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
-
+ PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
+ PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+
// SW2
- PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW2:1" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW2:2" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW2:1" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW2:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW2:3" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW2:4" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW2:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x1000, 0x1000, "SW2:5" )
- PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW2:6" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW2:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x4000, 0x4000, "SW2:7" )
- PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW2:8" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW2:8" )
INPUT_PORTS_END
@@ -1824,35 +1824,35 @@ ROM_START( mjkojink )
ROM_END
ROM_START( mjjoship )
- ROM_REGION( 0x01c000, "maincpu", 0 ) /* 6809 Code */
- ROM_LOAD( "X73_L01.16E", 0x010000, 0xc000, CRC(df950025) SHA1(3dc22c0a8cf03cff7310fbff36f83804019a5337) )
- ROM_CONTINUE( 0x00c000, 0x4000 )
+ ROM_REGION( 0x01c000, "maincpu", 0 ) /* 6809 Code */
+ ROM_LOAD( "X73_L01.16E", 0x010000, 0xc000, CRC(df950025) SHA1(3dc22c0a8cf03cff7310fbff36f83804019a5337) )
+ ROM_CONTINUE( 0x00c000, 0x4000 )
- ROM_REGION( 0x40000, "audiocpu", 0) /* uPD7807 code */
- ROM_LOAD( "X73_B02.9G", 0x00000, 0x20000, CRC(6b01503b) SHA1(2e1575dac0b9b7c7233a3b8262a99a10e24ec813) )
+ ROM_REGION( 0x40000, "audiocpu", 0) /* uPD7807 code */
+ ROM_LOAD( "X73_B02.9G", 0x00000, 0x20000, CRC(6b01503b) SHA1(2e1575dac0b9b7c7233a3b8262a99a10e24ec813) )
ROM_RELOAD( 0x20000, 0x20000 )
- ROM_REGION( 0x80000, "gfx1", 0 )
- ROM_LOAD32_BYTE( "X73A14.1F", 0, 0x20000, CRC(42f429a5) SHA1(41f64258a65b56f818f8a6ecddab606d0bdc11ab) )
- ROM_LOAD32_BYTE( "X73A15.3F", 1, 0x20000, CRC(2d827236) SHA1(d392dc64f136fd2ef19a2874758ad7804741882a) )
+ ROM_REGION( 0x80000, "gfx1", 0 )
+ ROM_LOAD32_BYTE( "X73A14.1F", 0, 0x20000, CRC(42f429a5) SHA1(41f64258a65b56f818f8a6ecddab606d0bdc11ab) )
+ ROM_LOAD32_BYTE( "X73A15.3F", 1, 0x20000, CRC(2d827236) SHA1(d392dc64f136fd2ef19a2874758ad7804741882a) )
ROM_IGNORE( 0x20000 )
- ROM_LOAD32_BYTE( "X73A16.4F", 2, 0x20000, CRC(c606cd02) SHA1(d316f11ad56359c8ae74858a84b373dd06934888) )
+ ROM_LOAD32_BYTE( "X73A16.4F", 2, 0x20000, CRC(c606cd02) SHA1(d316f11ad56359c8ae74858a84b373dd06934888) )
ROM_IGNORE( 0x20000 )
- ROM_LOAD32_BYTE( "X73A17.6F", 3, 0x20000, CRC(2c0fdbc9) SHA1(3ae5b590db4705deeaeff93680a10ca980e6264f) )
+ ROM_LOAD32_BYTE( "X73A17.6F", 3, 0x20000, CRC(2c0fdbc9) SHA1(3ae5b590db4705deeaeff93680a10ca980e6264f) )
ROM_IGNORE( 0x20000 )
- ROM_REGION( 0x100000, "gfx2", 0 )
- ROM_LOAD32_BYTE( "X73A10.1C", 0, 0x40000, CRC(e6663a99) SHA1(361503c16e32977c8f6b9c5ff981002ac0f97426) )
- ROM_LOAD32_BYTE( "X73A11.3C", 1, 0x40000, CRC(d8a35ebe) SHA1(b6e12db38ddd6dcefa8335b92c0a6e269a6a1e9a) )
- ROM_LOAD32_BYTE( "X73A12.4C", 2, 0x40000, CRC(f3b6ad98) SHA1(d91eeffd18684300809c99fa93d4ac0188530ff7) )
- ROM_LOAD32_BYTE( "X73A13.6C", 3, 0x40000, CRC(30ff8c5f) SHA1(e51d89f6b5db0d8e2c22a046337993f962f6ba8c) )
+ ROM_REGION( 0x100000, "gfx2", 0 )
+ ROM_LOAD32_BYTE( "X73A10.1C", 0, 0x40000, CRC(e6663a99) SHA1(361503c16e32977c8f6b9c5ff981002ac0f97426) )
+ ROM_LOAD32_BYTE( "X73A11.3C", 1, 0x40000, CRC(d8a35ebe) SHA1(b6e12db38ddd6dcefa8335b92c0a6e269a6a1e9a) )
+ ROM_LOAD32_BYTE( "X73A12.4C", 2, 0x40000, CRC(f3b6ad98) SHA1(d91eeffd18684300809c99fa93d4ac0188530ff7) )
+ ROM_LOAD32_BYTE( "X73A13.6C", 3, 0x40000, CRC(30ff8c5f) SHA1(e51d89f6b5db0d8e2c22a046337993f962f6ba8c) )
- ROM_REGION( 0x010000, "proms", 0 ) /* static palette */
- ROM_LOAD16_BYTE( "X73_C19.4K", 0x00000, 0x8000, CRC(f4bdce8a) SHA1(e3168d6aa6f8cd24b497706a117c77353d1c6ef3) )
- ROM_LOAD16_BYTE( "X73_C18.3K", 0x00001, 0x8000, CRC(1ab265cc) SHA1(24dced438a28ea9eb2f06c8859c5c07f4d975bfd) )
+ ROM_REGION( 0x010000, "proms", 0 ) /* static palette */
+ ROM_LOAD16_BYTE( "X73_C19.4K", 0x00000, 0x8000, CRC(f4bdce8a) SHA1(e3168d6aa6f8cd24b497706a117c77353d1c6ef3) )
+ ROM_LOAD16_BYTE( "X73_C18.3K", 0x00001, 0x8000, CRC(1ab265cc) SHA1(24dced438a28ea9eb2f06c8859c5c07f4d975bfd) )
- ROM_REGION( 0x20000, "user1", 0 ) /* blitter data */
- ROM_LOAD( "X73A03.12E", 0x0000, 0x20000, CRC(fd32eb8c) SHA1(584afb1ed2da776a4ff9c0b9eb2906c914b28928) )
+ ROM_REGION( 0x20000, "user1", 0 ) /* blitter data */
+ ROM_LOAD( "X73A03.12E", 0x0000, 0x20000, CRC(fd32eb8c) SHA1(584afb1ed2da776a4ff9c0b9eb2906c914b28928) )
ROM_END
diff --git a/src/mame/drivers/kickgoal.cpp b/src/mame/drivers/kickgoal.cpp
index f1f84912c10..587c2786b73 100644
--- a/src/mame/drivers/kickgoal.cpp
+++ b/src/mame/drivers/kickgoal.cpp
@@ -480,7 +480,7 @@ static ADDRESS_MAP_START( kickgoal_program_map, AS_PROGRAM, 16, kickgoal_state )
/// AM_RANGE(0x30001e, 0x30001f) AM_WRITE(kickgoal_snd_w)
AM_RANGE(0x800000, 0x800001) AM_READ_PORT("P1_P2")
AM_RANGE(0x800002, 0x800003) AM_READ_PORT("SYSTEM")
-/// AM_RANGE(0x800004, 0x800005) AM_DEVWRITE("soundlatch", generic_latch_16_device, write)
+/// AM_RANGE(0x800004, 0x800005) AM_DEVWRITE("soundlatch", generic_latch_16_device, write)
AM_RANGE(0x800004, 0x800005) AM_WRITE(actionhw_snd_w)
AM_RANGE(0x900000, 0x900005) AM_WRITE(kickgoal_eeprom_w)
AM_RANGE(0x900006, 0x900007) AM_READ(kickgoal_eeprom_r)
diff --git a/src/mame/drivers/leland.cpp b/src/mame/drivers/leland.cpp
index a7f2bd3316a..aa59e32d783 100644
--- a/src/mame/drivers/leland.cpp
+++ b/src/mame/drivers/leland.cpp
@@ -3027,4 +3027,3 @@ GAME( 1990, wsf, 0, wsf, wsf, leland_state, wsf, ROT0,
GAME( 1991, indyheat, 0, wsf, indyheat, leland_state, indyheat, ROT0, "Leland Corp.", "Danny Sullivan's Indy Heat", 0 )
GAME( 1991, brutforc, 0, wsf, brutforc, leland_state, brutforc, ROT0, "Leland Corp.", "Brute Force", 0 )
GAME( 1991, asylum, 0, wsf, brutforc, leland_state, asylum, ROT270, "Leland Corp.", "Asylum (prototype)", 0 )
-
diff --git a/src/mame/drivers/lgp.cpp b/src/mame/drivers/lgp.cpp
index 82fa4de476c..85edb077992 100644
--- a/src/mame/drivers/lgp.cpp
+++ b/src/mame/drivers/lgp.cpp
@@ -365,7 +365,7 @@ PALETTE_INIT_MEMBER(lgp_state, lgp)
const UINT8 *color_prom = memregion("proms")->base();
int i;
-// for (i = 0; i < palette.entries(); i++)
+// for (i = 0; i < palette.entries(); i++)
for (i = 0; i < 0x20; i++)
{
int r,g,b;
@@ -388,8 +388,8 @@ PALETTE_INIT_MEMBER(lgp_state, lgp)
bit1 = (color_prom[i] >> 4) & 0x01;
bit2 = (color_prom[i] >> 5) & 0x01;
b = 0x21 * bit0 + 0x47 * bit1 + 0x97 * bit2;
-
-
+
+
palette.set_pen_color(i,rgb_t(r,g,b));
}
@@ -513,7 +513,7 @@ ROM_START( lgp )
ROM_LOAD( "a02_39.109", 0x00300, 0x100, CRC(88363809) SHA1(b22a7bd8ce6b28bf7cfa64c3a08e4cf7f9b4cd20) )
ROM_LOAD( "a02_40.110", 0x00400, 0x100, CRC(fdfc7aac) SHA1(2413f7f9ad11c91d2adc0aab37bf70ff5c68ab6f) )
-
+
DISK_REGION( "laserdisc" )
DISK_IMAGE_READONLY( "lgp", 0, NO_DUMP )
ROM_END
diff --git a/src/mame/drivers/m63.cpp b/src/mame/drivers/m63.cpp
index 2e70f38c2a7..e91548c117e 100644
--- a/src/mame/drivers/m63.cpp
+++ b/src/mame/drivers/m63.cpp
@@ -176,7 +176,7 @@ public:
required_device<cpu_device> m_soundcpu;
optional_device<samples_device> m_samples;
required_device<generic_latch_8_device> m_soundlatch;
-
+
DECLARE_WRITE8_MEMBER(m63_videoram_w);
DECLARE_WRITE8_MEMBER(m63_colorram_w);
DECLARE_WRITE8_MEMBER(m63_videoram2_w);
diff --git a/src/mame/drivers/magicfly.cpp b/src/mame/drivers/magicfly.cpp
index 4dec074f4ed..1e4cc8dfbc7 100644
--- a/src/mame/drivers/magicfly.cpp
+++ b/src/mame/drivers/magicfly.cpp
@@ -163,8 +163,8 @@
(4) = Coin 1, Coin 2, Coupon.
Note: Each Common GND (A-B-C-D) are for their respective
- multiplexed groups of inputs, since there are 4 groups
- with 5 valid inputs each one.
+ multiplexed groups of inputs, since there are 4 groups
+ with 5 valid inputs each one.
**** 10-Pins connector ****
diff --git a/src/mame/drivers/megasys1.cpp b/src/mame/drivers/megasys1.cpp
index b30064e9ca2..9cd36745da0 100644
--- a/src/mame/drivers/megasys1.cpp
+++ b/src/mame/drivers/megasys1.cpp
@@ -925,53 +925,53 @@ INPUT_PORTS_END
static INPUT_PORTS_START( edfp )
PORT_INCLUDE( megasys1_generic )
- PORT_START("DSW")
- PORT_DIPNAME( 0x0007, 0x0007, "DSW bits 2-0" )
- PORT_DIPSETTING( 0x0000, "0" )
- PORT_DIPSETTING( 0x0001, "1" )
- PORT_DIPSETTING( 0x0002, "2" )
- PORT_DIPSETTING( 0x0003, "3" )
- PORT_DIPSETTING( 0x0004, "4" )
- PORT_DIPSETTING( 0x0005, "5" )
- PORT_DIPSETTING( 0x0006, "6" )
- PORT_DIPSETTING( 0x0007, "7" )
- PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Lives ) )
- PORT_DIPSETTING( 0x0008, "3" )
- PORT_DIPSETTING( 0x0000, "4" )
- PORT_DIPNAME( 0x0030, 0x0030, DEF_STR( Difficulty ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( Easy ) )
- PORT_DIPSETTING( 0x0030, DEF_STR( Normal ) )
- PORT_DIPSETTING( 0x0010, DEF_STR( Hard ) )
- PORT_DIPSETTING( 0x0020, DEF_STR( Very_Hard ) )
- PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
- PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
- PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) )
- PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
-
- PORT_DIPNAME( 0x0700, 0x0700, DEF_STR( Coin_A ) )
- PORT_DIPSETTING( 0x0400, DEF_STR( 3C_1C ) )
- PORT_DIPSETTING( 0x0200, DEF_STR( 2C_1C ) )
- PORT_DIPSETTING( 0x0700, DEF_STR( 1C_1C ) )
- PORT_DIPSETTING( 0x0300, DEF_STR( 1C_2C ) )
- PORT_DIPSETTING( 0x0500, DEF_STR( 1C_3C ) )
- PORT_DIPSETTING( 0x0100, DEF_STR( 1C_4C ) )
- PORT_DIPSETTING( 0x0600, DEF_STR( 1C_5C ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) )
- PORT_DIPNAME( 0x3800, 0x3800, DEF_STR( Coin_B ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
- PORT_DIPSETTING( 0x2000, DEF_STR( 3C_1C ) )
- PORT_DIPSETTING( 0x1000, DEF_STR( 2C_1C ) )
- PORT_DIPSETTING( 0x3800, DEF_STR( 1C_1C ) )
- PORT_DIPSETTING( 0x1800, DEF_STR( 1C_2C ) )
- PORT_DIPSETTING( 0x2800, DEF_STR( 1C_3C ) )
- PORT_DIPSETTING( 0x0800, DEF_STR( 1C_4C ) )
- PORT_DIPSETTING( 0x3000, DEF_STR( 1C_5C ) )
- PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Demo_Sounds ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x4000, DEF_STR( On ) )
- PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
+ PORT_START("DSW")
+ PORT_DIPNAME( 0x0007, 0x0007, "DSW bits 2-0" )
+ PORT_DIPSETTING( 0x0000, "0" )
+ PORT_DIPSETTING( 0x0001, "1" )
+ PORT_DIPSETTING( 0x0002, "2" )
+ PORT_DIPSETTING( 0x0003, "3" )
+ PORT_DIPSETTING( 0x0004, "4" )
+ PORT_DIPSETTING( 0x0005, "5" )
+ PORT_DIPSETTING( 0x0006, "6" )
+ PORT_DIPSETTING( 0x0007, "7" )
+ PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Lives ) )
+ PORT_DIPSETTING( 0x0008, "3" )
+ PORT_DIPSETTING( 0x0000, "4" )
+ PORT_DIPNAME( 0x0030, 0x0030, DEF_STR( Difficulty ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( Easy ) )
+ PORT_DIPSETTING( 0x0030, DEF_STR( Normal ) )
+ PORT_DIPSETTING( 0x0010, DEF_STR( Hard ) )
+ PORT_DIPSETTING( 0x0020, DEF_STR( Very_Hard ) )
+ PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
+ PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) )
+ PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+
+ PORT_DIPNAME( 0x0700, 0x0700, DEF_STR( Coin_A ) )
+ PORT_DIPSETTING( 0x0400, DEF_STR( 3C_1C ) )
+ PORT_DIPSETTING( 0x0200, DEF_STR( 2C_1C ) )
+ PORT_DIPSETTING( 0x0700, DEF_STR( 1C_1C ) )
+ PORT_DIPSETTING( 0x0300, DEF_STR( 1C_2C ) )
+ PORT_DIPSETTING( 0x0500, DEF_STR( 1C_3C ) )
+ PORT_DIPSETTING( 0x0100, DEF_STR( 1C_4C ) )
+ PORT_DIPSETTING( 0x0600, DEF_STR( 1C_5C ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) )
+ PORT_DIPNAME( 0x3800, 0x3800, DEF_STR( Coin_B ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
+ PORT_DIPSETTING( 0x2000, DEF_STR( 3C_1C ) )
+ PORT_DIPSETTING( 0x1000, DEF_STR( 2C_1C ) )
+ PORT_DIPSETTING( 0x3800, DEF_STR( 1C_1C ) )
+ PORT_DIPSETTING( 0x1800, DEF_STR( 1C_2C ) )
+ PORT_DIPSETTING( 0x2800, DEF_STR( 1C_3C ) )
+ PORT_DIPSETTING( 0x0800, DEF_STR( 1C_4C ) )
+ PORT_DIPSETTING( 0x3000, DEF_STR( 1C_5C ) )
+ PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Demo_Sounds ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x4000, DEF_STR( On ) )
+ PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
INPUT_PORTS_END
@@ -2570,7 +2570,7 @@ ROM_END
/*
EDF (Prototype)
-
+
Main Board: MB-8842 (System-A)
ROM Board: MB8845 (with D6500SCW-362 custom)
*/
@@ -2578,43 +2578,43 @@ ROM_START( edfp )
ROM_REGION( 0xc0000, "maincpu", 0 ) /* Main CPU Code */
ROM_LOAD16_BYTE( "2.ROM2.27C010", 0x000000, 0x020000, CRC(358a6ac3) SHA1(b7beaadd2e934071e6bc9cafdaa9cc5a1241488a) )
ROM_LOAD16_BYTE( "1.ROM1.27C010", 0x000001, 0x020000, CRC(f30cfb25) SHA1(38020aa62e61f15dbd4267293bd4b8df356ed16e) )
- ROM_LOAD16_BYTE( "4.ROM4.27512", 0x040001, 0x010000, CRC(41e1a014) SHA1(8d40353228114c762fe58c525162f35aa71ef21b) )
- ROM_LOAD16_BYTE( "3.ROM3.27512", 0x040000, 0x010000, CRC(f0357ba2) SHA1(e4ff21d5149ae7d0b259238c18edb193eb94be5e) )
+ ROM_LOAD16_BYTE( "4.ROM4.27512", 0x040001, 0x010000, CRC(41e1a014) SHA1(8d40353228114c762fe58c525162f35aa71ef21b) )
+ ROM_LOAD16_BYTE( "3.ROM3.27512", 0x040000, 0x010000, CRC(f0357ba2) SHA1(e4ff21d5149ae7d0b259238c18edb193eb94be5e) )
ROM_REGION( 0x40000, "audiocpu", 0 ) /* Sound CPU Code */
- ROM_LOAD16_BYTE( "5.ROM5.27512", 0x000000, 0x010000, CRC(505d09ff) SHA1(681579123257548f71ebb9d591c4db81fc52ff85) )
- ROM_LOAD16_BYTE( "6.ROM6.27512", 0x000001, 0x010000, CRC(13c14471) SHA1(9661ff7ca829260d1b247dee8fc5eb22d92cb1fa) )
+ ROM_LOAD16_BYTE( "5.ROM5.27512", 0x000000, 0x010000, CRC(505d09ff) SHA1(681579123257548f71ebb9d591c4db81fc52ff85) )
+ ROM_LOAD16_BYTE( "6.ROM6.27512", 0x000001, 0x010000, CRC(13c14471) SHA1(9661ff7ca829260d1b247dee8fc5eb22d92cb1fa) )
- /* No MCU */
+ /* No MCU */
ROM_REGION( 0x080000, "gfx1", 0 ) /* Scroll 0 */
ROM_LOAD( "11.ROM11.27C010", 0x000000, 0x020000, CRC(cfba8249) SHA1(f5ca1114296c2e268b44923b363add25b60f9e98) )
- ROM_LOAD( "12.ROM12.27C010", 0x020000, 0x020000, CRC(c2027f34) SHA1(c685666ae368259b27f62563131ffa4c5db2f985) )
- ROM_LOAD( "13.ROM13.27C010", 0x040000, 0x020000, CRC(d4b87d60) SHA1(94e85c9392150d3395e400defb96f7cb3fbc639b) )
- ROM_LOAD( "14.ROM14.27C010", 0x060000, 0x020000, CRC(9814fe96) SHA1(c1c53534bc2b0d97dda9f1caa0e4917d497c08ae) )
+ ROM_LOAD( "12.ROM12.27C010", 0x020000, 0x020000, CRC(c2027f34) SHA1(c685666ae368259b27f62563131ffa4c5db2f985) )
+ ROM_LOAD( "13.ROM13.27C010", 0x040000, 0x020000, CRC(d4b87d60) SHA1(94e85c9392150d3395e400defb96f7cb3fbc639b) )
+ ROM_LOAD( "14.ROM14.27C010", 0x060000, 0x020000, CRC(9814fe96) SHA1(c1c53534bc2b0d97dda9f1caa0e4917d497c08ae) )
ROM_REGION( 0x080000, "gfx2", 0 ) /* Scroll 1 */
- ROM_LOAD( "15.ROM15.27C010", 0x000000, 0x020000, CRC(a91c027d) SHA1(39b68e81e07c81ce9961e5d14e9c123c72b31051) )
- ROM_LOAD( "16.ROM16.27C010", 0x020000, 0x020000, CRC(2caecbc7) SHA1(82c2afcc3763d79ebf281fcf93b429ddbc6c44ae) )
- ROM_LOAD( "17.ROM17.27C010", 0x040000, 0x020000, CRC(3947efe8) SHA1(925dce253bf81c7d454872a707593b5085a0f3d0) )
- ROM_LOAD( "18.ROM18.27C010", 0x060000, 0x020000, CRC(2de832cb) SHA1(2b0266223561e649c535041ab8c543e3c64885ad) )
+ ROM_LOAD( "15.ROM15.27C010", 0x000000, 0x020000, CRC(a91c027d) SHA1(39b68e81e07c81ce9961e5d14e9c123c72b31051) )
+ ROM_LOAD( "16.ROM16.27C010", 0x020000, 0x020000, CRC(2caecbc7) SHA1(82c2afcc3763d79ebf281fcf93b429ddbc6c44ae) )
+ ROM_LOAD( "17.ROM17.27C010", 0x040000, 0x020000, CRC(3947efe8) SHA1(925dce253bf81c7d454872a707593b5085a0f3d0) )
+ ROM_LOAD( "18.ROM18.27C010", 0x060000, 0x020000, CRC(2de832cb) SHA1(2b0266223561e649c535041ab8c543e3c64885ad) )
ROM_REGION( 0x020000, "gfx3", 0 ) /* Scroll 2 */
ROM_LOAD( "19.ROM19.27C010", 0x000000, 0x020000, CRC(96e38983) SHA1(a4fb94f15d9a9f7df1645be66fe3e179d0ebf765) )
ROM_REGION( 0x080000, "gfx4", 0 ) /* Sprites */
ROM_LOAD( "20.ROM20.27C010", 0x000000, 0x020000, CRC(e6956a01) SHA1(3ded46d0372b0633383f2a5d7b0f53687091b220) )
- ROM_LOAD( "21.ROM21.27C010", 0x020000, 0x020000, CRC(8e19ae9a) SHA1(b12cdce9d6dae96a1c9d134828cc1cd7f85f3dab) )
- ROM_LOAD( "22.ROM22.27C010", 0x040000, 0x020000, CRC(b5be39f3) SHA1(a330f26d7355ebb4ba5c81189564c39c896e7544) )
- ROM_LOAD( "23.ROM23.27C010", 0x060000, 0x020000, CRC(01304689) SHA1(ef1836cce5b6a55633965b3c94293c6b99c59eb5) )
+ ROM_LOAD( "21.ROM21.27C010", 0x020000, 0x020000, CRC(8e19ae9a) SHA1(b12cdce9d6dae96a1c9d134828cc1cd7f85f3dab) )
+ ROM_LOAD( "22.ROM22.27C010", 0x040000, 0x020000, CRC(b5be39f3) SHA1(a330f26d7355ebb4ba5c81189564c39c896e7544) )
+ ROM_LOAD( "23.ROM23.27C010", 0x060000, 0x020000, CRC(01304689) SHA1(ef1836cce5b6a55633965b3c94293c6b99c59eb5) )
ROM_REGION( 0x040000, "oki1", 0 ) /* Samples */
- ROM_LOAD( "9.ROM9.27C010", 0x000000, 0x020000, CRC(7182f27c) SHA1(dc83f3552f6d01365f9f3af89ba97a9936f7899c) )
- ROM_LOAD( "10.ROM10.27C010", 0x020000, 0x020000, CRC(f780d92f) SHA1(8bee845a0aaa0b5ca5532ea4962adeb40699e3be) )
+ ROM_LOAD( "9.ROM9.27C010", 0x000000, 0x020000, CRC(7182f27c) SHA1(dc83f3552f6d01365f9f3af89ba97a9936f7899c) )
+ ROM_LOAD( "10.ROM10.27C010", 0x020000, 0x020000, CRC(f780d92f) SHA1(8bee845a0aaa0b5ca5532ea4962adeb40699e3be) )
ROM_REGION( 0x040000, "oki2", 0 ) /* Samples */
- ROM_LOAD( "7.ROM7.27C010", 0x000000, 0x020000, CRC(b9d79c1e) SHA1(315dbed9b7cc289b383c95e6c94267682324154c) )
- ROM_LOAD( "8.ROM8.27C010", 0x020000, 0x020000, CRC(fa0d1887) SHA1(d24c17806669f5b12527b36bc9c10fd16222e23c) )
+ ROM_LOAD( "7.ROM7.27C010", 0x000000, 0x020000, CRC(b9d79c1e) SHA1(315dbed9b7cc289b383c95e6c94267682324154c) )
+ ROM_LOAD( "8.ROM8.27C010", 0x020000, 0x020000, CRC(fa0d1887) SHA1(d24c17806669f5b12527b36bc9c10fd16222e23c) )
ROM_REGION( 0x0200, "proms", 0 ) /* Priority PROM (N82S131N compatible type PROM) */
ROM_LOAD( "rd.20n", 0x0000, 0x0200, CRC(1d877538) SHA1(a5be0dc65dcfc36fbba10d1fddbe155e24b6122f) )
@@ -4247,7 +4247,7 @@ DRIVER_INIT_MEMBER(megasys1_state,edf)
DRIVER_INIT_MEMBER(megasys1_state,edfp)
{
- phantasm_rom_decode(machine(), "maincpu");
+ phantasm_rom_decode(machine(), "maincpu");
}
READ16_MEMBER(megasys1_state::edfbl_input_r)
diff --git a/src/mame/drivers/metlfrzr.cpp b/src/mame/drivers/metlfrzr.cpp
index 83c4b40d579..6f91fdc8525 100644
--- a/src/mame/drivers/metlfrzr.cpp
+++ b/src/mame/drivers/metlfrzr.cpp
@@ -6,8 +6,8 @@
Metal Freezer (c) 1989 Seibu
driver by Angelo Salese, based off initial work by David Haywood
- thanks to Peter Wilhelmsen for the decryption
-
+ thanks to Peter Wilhelmsen for the decryption
+
HW seems the natural evolution of Dark Mist type.
TODO:
@@ -131,7 +131,6 @@ void metlfrzr_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &clipr
for(count=0x200-4;count>-1;count-=4)
{
-
gfx_element *cur_gfx = base_spriteram[count+1] & 0x40 ? gfx_3 : gfx_2;
UINT8 tile_bank = (base_spriteram[count+1] & 0x30) >> 4;
UINT16 tile = base_spriteram[count] | (tile_bank << 8);
@@ -140,7 +139,7 @@ void metlfrzr_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &clipr
int x = base_spriteram[count+3];
if(base_spriteram[count+1] & 0x80)
x-=256;
-
+
cur_gfx->transpen(bitmap,cliprect,tile,color,0,0,x,y,0xf);
}
}
@@ -148,7 +147,7 @@ void metlfrzr_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &clipr
UINT32 metlfrzr_state::screen_update_metlfrzr(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
bitmap.fill(m_palette->black_pen(), cliprect);
-
+
legacy_bg_draw(bitmap,cliprect);
legacy_obj_draw(bitmap,cliprect);
return 0;
@@ -168,7 +167,7 @@ WRITE8_MEMBER(metlfrzr_state::output_w)
m_fg_tilebank = (data & 0x10) >> 4;
membank("bank1")->set_entry((data & 0xc) >> 2);
m_rowscroll_enable = bool(BIT(data,1));
-
+
// popmessage("%02x %02x",m_fg_tilebank,data & 3);
}
@@ -249,14 +248,14 @@ static INPUT_PORTS_START( metlfrzr )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_START("DSW1")
- PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW1:1")
+ PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW1:1")
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
PORT_SERVICE_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW1:2" )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:3")
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:4,5,6")
+ PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:4,5,6")
PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
PORT_DIPSETTING( 0x20, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) )
@@ -265,35 +264,35 @@ static INPUT_PORTS_START( metlfrzr )
PORT_DIPSETTING( 0x18, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x28, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_5C ) )
- PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:7,8")
+ PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:7,8")
PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x40, DEF_STR( 1C_2C ) )
PORT_START("DSW2")
- PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
+ PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
PORT_DIPSETTING( 0x02, "A" )
PORT_DIPSETTING( 0x03, "B" )
PORT_DIPSETTING( 0x01, "C" )
PORT_DIPSETTING( 0x00, "D" )
// service mode returns these values divided by 10 (so 02/05/10 effectively means 20k, 50k, 100k)
// TODO: check if it extends
- PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:3,4")
+ PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:3,4")
PORT_DIPSETTING( 0x08, "20k, 50k, 100k" )
PORT_DIPSETTING( 0x0c, "30k, 80k, 150k" )
PORT_DIPSETTING( 0x04, "50k, 100k, 200k" )
PORT_DIPSETTING( 0x00, "100k, 200k, 400k" )
- PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:5,6")
+ PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:5,6")
PORT_DIPSETTING( 0x20, "1" )
PORT_DIPSETTING( 0x10, "2" )
PORT_DIPSETTING( 0x30, "3" )
PORT_DIPSETTING( 0x00, "4" )
// disabling following enables intro / how to play screens
- PORT_DIPNAME( 0x40, 0x40, DEF_STR( Level_Select ) ) PORT_DIPLOCATION("SW2:7")
+ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Level_Select ) ) PORT_DIPLOCATION("SW2:7")
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:8")
+ PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
diff --git a/src/mame/drivers/mgames.cpp b/src/mame/drivers/mgames.cpp
index 1dd83a56ff6..7cb3ec90378 100644
--- a/src/mame/drivers/mgames.cpp
+++ b/src/mame/drivers/mgames.cpp
@@ -652,7 +652,7 @@ static MACHINE_CONFIG_START( mgames, mgames_state )
MCFG_PALETTE_INIT_OWNER(mgames_state, mgames)
/* sound hardware */
- // to do...
+ // to do...
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/naomi.cpp b/src/mame/drivers/naomi.cpp
index f145354c4b3..882e905d2ca 100644
--- a/src/mame/drivers/naomi.cpp
+++ b/src/mame/drivers/naomi.cpp
@@ -5331,7 +5331,7 @@ ROM_START( samba )
NAOMI_DEFAULT_EEPROM
ROM_REGION( 0x8800000, "rom_board", ROMREGION_ERASEFF)
- ROM_LOAD("epr-22966b.ic22",0x0000000, 0x0400000, CRC(893116b8) SHA1(35cb4f40690ff21af5ab7cc5adbc53228d6fb0b3) ) // was also found in cartridge with Rev.A case label
+ ROM_LOAD("epr-22966b.ic22",0x0000000, 0x0400000, CRC(893116b8) SHA1(35cb4f40690ff21af5ab7cc5adbc53228d6fb0b3) ) // was also found in cartridge with Rev.A case label
ROM_LOAD("mpr-22950.ic1", 0x0800000, 0x0800000, CRC(16dee15c) SHA1(b46849e492756ff406bf8956303472255fcf55a5) )
ROM_LOAD("mpr-22951.ic2", 0x1000000, 0x0800000, CRC(f509496f) SHA1(41281576f7d58c8ede9c0a89bfd46a98d5b97033) )
ROM_LOAD("mpr-22952.ic3", 0x1800000, 0x0800000, CRC(fb9b3ef0) SHA1(e9d44b673c273e97445a12186496a0594e291542) )
@@ -9838,7 +9838,7 @@ GAME( 2003, puyofevp, naomi, naomim1, naomi, naomi_state, naomi, ROT0, "Sega", "
/* CDP-10001C*/ GAME( 2003, wccf116, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2001-2002 Ver. 2 (CDP-10001C)", GAME_FLAGS )
/* CDP-10003 */ GAME( 2002, wccf1dup, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2001-2002 DIMM FIRM Ver.3.03 (CDP-10003)", GAME_FLAGS )
/* CDV-10002 */ GAME( 2004, wccf212e, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2002-2003 Ver.2.12 (CDV-10002)", GAME_FLAGS )
-/* CDV-10007 */ GAME( 2004, wccf2chk, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2002-2003 Drive Checker (CDV-10007)", GAME_FLAGS ) // actually just disc ejector
+/* CDV-10007 */ GAME( 2004, wccf2chk, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2002-2003 Drive Checker (CDV-10007)", GAME_FLAGS ) // actually just disc ejector
/* CDV-10008 */ GAME( 2004, wccf234j, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Hitmaker / Sega", "World Club Champion Football Serie A 2002-2003 Ver.2.34 (CDV-10008)", GAME_FLAGS )
/* CDV-10013 */ GAME( 2005, wccf310j, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Sega", "World Club Champion Football European Clubs 2004-2005 (CDV-10013)", GAME_FLAGS )
/* CDV-10015 */ GAME( 2005, wccf331e, wccf322e,naomigd, naomi, naomi_state, naomigd, ROT0, "Sega", "World Club Champion Football European Clubs 2004-2005 Ver.1.1 (CDV-10015)", GAME_FLAGS )
diff --git a/src/mame/drivers/neogeo.cpp b/src/mame/drivers/neogeo.cpp
index 8bb9b8069d2..b990065dafb 100644
--- a/src/mame/drivers/neogeo.cpp
+++ b/src/mame/drivers/neogeo.cpp
@@ -1054,12 +1054,12 @@ void neogeo_state::init_cpu()
{
UINT8 *ROM = (!m_slots[m_curr_slot] || m_slots[m_curr_slot]->get_rom_size() == 0) ? m_region_maincpu->base() : (UINT8 *)m_slots[m_curr_slot]->get_rom_base();
UINT32 len = (!m_slots[m_curr_slot] || m_slots[m_curr_slot]->get_rom_size() == 0) ? m_region_maincpu->bytes() : m_slots[m_curr_slot]->get_rom_size();
-
+
if (len > 0x100000)
m_bank_base = 0x100000;
else
m_bank_base = 0;
-
+
m_bank_cartridge->set_base(ROM + m_bank_base);
}
diff --git a/src/mame/drivers/pasopia7.cpp b/src/mame/drivers/pasopia7.cpp
index 88f5a79b3df..eaf0bce140e 100644
--- a/src/mame/drivers/pasopia7.cpp
+++ b/src/mame/drivers/pasopia7.cpp
@@ -817,8 +817,8 @@ WRITE8_MEMBER( pasopia7_state::video_misc_w )
*/
//if(data & 2)
//{
- // printf("VIDEO MISC %02x\n",data);
- // machine().debug_break();
+ // printf("VIDEO MISC %02x\n",data);
+ // machine().debug_break();
//}
m_cursor_blink = data & 0x20;
m_attr_wrap = data & 0x10;
diff --git a/src/mame/drivers/patinho_feio.cpp b/src/mame/drivers/patinho_feio.cpp
index 65a1e5309ec..ae5218ded57 100644
--- a/src/mame/drivers/patinho_feio.cpp
+++ b/src/mame/drivers/patinho_feio.cpp
@@ -232,22 +232,22 @@ static INPUT_PORTS_START( patinho_feio )
PORT_BIT(0x800, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("RC bit 11") PORT_CODE(KEYCODE_1) PORT_TOGGLE
PORT_START("BUTTONS")
- /* Modo de Operação: EXECUÇÃO */
+ /* Modo de Operacao: EXECUCAO */
PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("NORMAL") PORT_CODE(KEYCODE_A)
- PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("CICLO ÚNICO") PORT_CODE(KEYCODE_S)
- PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("INSTRUÇÃO ÚNICA") PORT_CODE(KEYCODE_D)
- /* Modo de Operação: MEMÓRIA */
- PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENDEREÇAMENTO") PORT_CODE(KEYCODE_Z)
+ PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("CICLO UNICO") PORT_CODE(KEYCODE_S)
+ PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("INSTRUCAO UNICA") PORT_CODE(KEYCODE_D)
+ /* Modo de Operacao: MEMORIA */
+ PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENDERECAMENTO") PORT_CODE(KEYCODE_Z)
PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ARMAZENAMENTO") PORT_CODE(KEYCODE_X)
- PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("EXPOSIÇÃO") PORT_CODE(KEYCODE_C)
+ PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("EXPOSICAO") PORT_CODE(KEYCODE_C)
/* Comando: */
PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ESPERA") PORT_CODE(KEYCODE_Q)
- PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("INTERRUPÇÃO") PORT_CODE(KEYCODE_W)
+ PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("INTERRUPCAO") PORT_CODE(KEYCODE_W)
PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("PARTIDA") PORT_CODE(KEYCODE_E)
- PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("PREPARAÇÃO") PORT_CODE(KEYCODE_R)
+ PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("PREPARACAO") PORT_CODE(KEYCODE_R)
/* Switches */
- PORT_BIT(0x400, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENDEREÇAMENTO (Fixo/Sequencial)") PORT_CODE(KEYCODE_N) PORT_TOGGLE
- PORT_BIT(0x800, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("MEMÓRIA (Liberada/Protegida)") PORT_CODE(KEYCODE_M) PORT_TOGGLE
+ PORT_BIT(0x400, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ENDERECAMENTO (Fixo/Sequencial)") PORT_CODE(KEYCODE_N) PORT_TOGGLE
+ PORT_BIT(0x800, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("MEMORIA (Liberada/Protegida)") PORT_CODE(KEYCODE_M) PORT_TOGGLE
INPUT_PORTS_END
static MACHINE_CONFIG_START( patinho_feio, patinho_feio_state )
@@ -258,13 +258,13 @@ static MACHINE_CONFIG_START( patinho_feio, patinho_feio_state )
MCFG_PATINHO_BUTTONS_READ_CB(READ16(patinho_feio_state, buttons_r))
/* Printer */
-// MCFG_PATINHO_IODEV_WRITE_CB(0x5, WRITE8(patinho_feio_state, printer_data_w))
+// MCFG_PATINHO_IODEV_WRITE_CB(0x5, WRITE8(patinho_feio_state, printer_data_w))
/* Papertape Puncher */
-// MCFG_PATINHO_IODEV_WRITE_CB(0x8, WRITE8(patinho_feio_state, papertape_punch_data_w))
+// MCFG_PATINHO_IODEV_WRITE_CB(0x8, WRITE8(patinho_feio_state, papertape_punch_data_w))
/* Card Reader */
-// MCFG_PATINHO_IODEV_READ_CB(0x9, READ8(patinho_feio_state, cardreader_data_r))
+// MCFG_PATINHO_IODEV_READ_CB(0x9, READ8(patinho_feio_state, cardreader_data_r))
/* DECWRITER
(max. speed: ?) */
@@ -279,7 +279,7 @@ static MACHINE_CONFIG_START( patinho_feio, patinho_feio_state )
/* Papertape Reader
Hewlett-Packard HP-2737-A
Optical Papertape Reader (max. speed: 300 characteres per second) */
-// MCFG_PATINHO_IODEV_READ_CB(0xE, READ8(patinho_feio_state, papertapereader_data_r))
+// MCFG_PATINHO_IODEV_READ_CB(0xE, READ8(patinho_feio_state, papertapereader_data_r))
/* DECWRITER */
MCFG_DEVICE_ADD("decwriter", TELEPRINTER, 0)
@@ -297,7 +297,7 @@ static MACHINE_CONFIG_START( patinho_feio, patinho_feio_state )
MCFG_DEFAULT_LAYOUT(layout_patinho)
// software lists
-// MCFG_SOFTWARE_LIST_ADD("tape_list", "patinho")
+// MCFG_SOFTWARE_LIST_ADD("tape_list", "patinho")
MACHINE_CONFIG_END
ROM_START( patinho )
@@ -313,7 +313,7 @@ ROM_START( patinho )
/* Micro pre-loader:
This was re-created by professor Joao Jose Neto based on his vague
recollection of sequences of opcode values from almost 40 years ago :-) */
- ROM_REGION( 0x02a, "micro_pre_loader", 0 )
+ ROM_REGION( 0x02a, "micro_pre_loader", 0 )
ROM_LOAD( "micro-pre-loader.bin", 0x000, 0x02a, CRC(1921feab) SHA1(bb063102e44e9ab963f95b45710141dc2c5046b0) )
ROM_END
diff --git a/src/mame/drivers/pc9801.cpp b/src/mame/drivers/pc9801.cpp
index 846f87cb95e..1030b13298b 100644
--- a/src/mame/drivers/pc9801.cpp
+++ b/src/mame/drivers/pc9801.cpp
@@ -3185,7 +3185,7 @@ static MACHINE_CONFIG_FRAGMENT( pc9801_ide )
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(pc9801_state, ide1_irq_w))
MCFG_ATA_INTERFACE_ADD("ide2", pc9801_atapi_devices, "pc9801_cd", nullptr, false)
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(pc9801_state, ide2_irq_w))
-
+
MCFG_SOFTWARE_LIST_ADD("cd_list","pc98_cd")
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/rainbow.cpp b/src/mame/drivers/rainbow.cpp
index 31fa8996eee..1b88f4e9b83 100644
--- a/src/mame/drivers/rainbow.cpp
+++ b/src/mame/drivers/rainbow.cpp
@@ -24,7 +24,7 @@ BUGS / ISSUES
The former is used in startup tests, the latter seems less relevant (must use menu self test "S").
(2) serial ports do not work, so serial communication failure (ERROR 60) and ERROR 40 (serial
-printer interface) result.
+printer interface) result.
(3) while DOS 3 and UCSD systems (fort_sys, pas_sys) + diag disks boot, CPM 2.x and DOS 2.x die
in secondary boot loader with a RESTORE (seek track 0) when track 2 sector 1 should be loaded.
diff --git a/src/mame/drivers/sg1000.cpp b/src/mame/drivers/sg1000.cpp
index d83b0756b5e..881fb162b80 100644
--- a/src/mame/drivers/sg1000.cpp
+++ b/src/mame/drivers/sg1000.cpp
@@ -93,7 +93,7 @@ WRITE8_MEMBER( sg1000_state::omv_w )
READ8_MEMBER( sg1000_state::peripheral_r )
{
bool joy_ports_disabled = m_sgexpslot->is_readable(offset);
-
+
if (joy_ports_disabled)
{
return m_sgexpslot->read(space, offset);
@@ -110,7 +110,7 @@ READ8_MEMBER( sg1000_state::peripheral_r )
WRITE8_MEMBER( sg1000_state::peripheral_w )
{
bool joy_ports_disabled = m_sgexpslot->is_writeable(offset);
-
+
if (joy_ports_disabled)
{
m_sgexpslot->write(space, offset, data);
diff --git a/src/mame/drivers/sun2.cpp b/src/mame/drivers/sun2.cpp
index ec1611e494a..1fbc83e99e8 100644
--- a/src/mame/drivers/sun2.cpp
+++ b/src/mame/drivers/sun2.cpp
@@ -69,50 +69,50 @@
25/08/2009 Skeleton driver.
31/05/2016 Main screen turn on.
-
+
How the architecture works:
- - There are 3 address sub-spaces: CPU layer, MMU layer, and device layer
- - CPU layer uses MOVS instructions to output FC 3.
- - CPU layer: the low-order address bits A4-A1 specify the device
- 0100x = ID Prom
- 0101x = Diagnostic register (8 bits, 8 LEDs, bit = 0 for ON, 1 for OFF)
- 0110x = Bus error register
- 0111x = System enable register
-
- Bits A5+ address the actual individual parts of these things. ID Prom bytes
- are at 0x0008, 0x0808, 0x1008, 0x1808, 0x2008, 0x2808, 0x3008, etc.
-
- System enable bits:
- b0 = enable parity generation
- b1 = cause level 1 IRQ
- b2 = cause level 2 IRQ
- b3 = cause level 3 IRQ
- b4 = enable parity error checking
- b5 = enable DVMA
- b6 = enable all interrupts
- b7 = boot state (0 = boot, 1 = normal)
- In boot state, all supervisor program reads go to the EPROM.
-
- - MMU layer: also accessed via FC 3
- PAGE MAP at 0 + V
- SEGMENT MAP at 4 + V
- CONTEXT REG at 6 + V
-
- There are 8 hardware contexts. Supervisor and User FCs can have different contexts.
-
- Segment map is 4096 entries, from bits 23-15 of the virtual address + 3 context bits.
- Entries are 8 bits, which point to a page map entry group (PMEG), which is 16 consecutive
- page table entries (32 KB of space).
-
- Page map is 4096 entries each mapping a 2K page. There are 256 groups of 16 entries;
- the PMEG points to these 256 groups. The page map contains a 20-bit page number,
- which combines with the 11 low bits of the original address to get a 31-bit physical address.
- The entry from 0-15 is picked with bits 15-11 of the original address.
-
- Page map entries are written to the PMEG determined by their segment map entry; you must
- set the segment map validly in order to write to the page map. This is how they get away
- with having 16 MB of segment entries and only 8 MB of PMEGs.
-
+ - There are 3 address sub-spaces: CPU layer, MMU layer, and device layer
+ - CPU layer uses MOVS instructions to output FC 3.
+ - CPU layer: the low-order address bits A4-A1 specify the device
+ 0100x = ID Prom
+ 0101x = Diagnostic register (8 bits, 8 LEDs, bit = 0 for ON, 1 for OFF)
+ 0110x = Bus error register
+ 0111x = System enable register
+
+ Bits A5+ address the actual individual parts of these things. ID Prom bytes
+ are at 0x0008, 0x0808, 0x1008, 0x1808, 0x2008, 0x2808, 0x3008, etc.
+
+ System enable bits:
+ b0 = enable parity generation
+ b1 = cause level 1 IRQ
+ b2 = cause level 2 IRQ
+ b3 = cause level 3 IRQ
+ b4 = enable parity error checking
+ b5 = enable DVMA
+ b6 = enable all interrupts
+ b7 = boot state (0 = boot, 1 = normal)
+ In boot state, all supervisor program reads go to the EPROM.
+
+ - MMU layer: also accessed via FC 3
+ PAGE MAP at 0 + V
+ SEGMENT MAP at 4 + V
+ CONTEXT REG at 6 + V
+
+ There are 8 hardware contexts. Supervisor and User FCs can have different contexts.
+
+ Segment map is 4096 entries, from bits 23-15 of the virtual address + 3 context bits.
+ Entries are 8 bits, which point to a page map entry group (PMEG), which is 16 consecutive
+ page table entries (32 KB of space).
+
+ Page map is 4096 entries each mapping a 2K page. There are 256 groups of 16 entries;
+ the PMEG points to these 256 groups. The page map contains a 20-bit page number,
+ which combines with the 11 low bits of the original address to get a 31-bit physical address.
+ The entry from 0-15 is picked with bits 15-11 of the original address.
+
+ Page map entries are written to the PMEG determined by their segment map entry; you must
+ set the segment map validly in order to write to the page map. This is how they get away
+ with having 16 MB of segment entries and only 8 MB of PMEGs.
+
****************************************************************************/
#include "emu.h"
@@ -128,11 +128,11 @@ How the architecture works:
#define RS232B_TAG "rs232b"
// page table entry constants
-#define PM_VALID (0x80000000) // page is valid
-#define PM_PROTMASK (0x7e000000) // protection mask
-#define PM_TYPEMASK (0x01c00000) // type mask
-#define PM_ACCESSED (0x00200000) // accessed flag
-#define PM_MODIFIED (0x00100000) // modified flag
+#define PM_VALID (0x80000000) // page is valid
+#define PM_PROTMASK (0x7e000000) // protection mask
+#define PM_TYPEMASK (0x01c00000) // type mask
+#define PM_ACCESSED (0x00200000) // accessed flag
+#define PM_MODIFIED (0x00100000) // modified flag
class sun2_state : public driver_device
{
@@ -155,20 +155,20 @@ public:
required_device<ram_device> m_ram;
required_device<address_map_bank_device> m_type0space, m_type1space, m_type2space, m_type3space;
required_shared_ptr<UINT16> m_bw2_vram;
-
+
virtual void machine_start() override;
virtual void machine_reset() override;
-
+
DECLARE_READ16_MEMBER( tl_mmu_r );
DECLARE_WRITE16_MEMBER( tl_mmu_w );
DECLARE_READ16_MEMBER( video_ctrl_r );
DECLARE_WRITE16_MEMBER( video_ctrl_w );
DECLARE_READ16_MEMBER( ram_r );
DECLARE_WRITE16_MEMBER( ram_w );
-
+
UINT32 bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
-private:
+private:
UINT16 *m_rom_ptr, *m_ram_ptr;
UINT8 *m_idprom_ptr;
UINT16 m_diagreg, m_sysenable, m_buserror;
@@ -196,49 +196,49 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
if ((fc == 3) && !space.debugger_access())
{
- if (offset & 0x4) // set for CPU space
+ if (offset & 0x4) // set for CPU space
{
switch (offset & 7)
{
case 4:
//printf("sun2: Read IDPROM @ %x (PC=%x)\n", offset<<1, m_maincpu->pc);
return m_idprom_ptr[(offset>>10) & 0x1f]<<8;
-
+
case 5:
//printf("sun2: Read diag reg\n");
return m_diagreg;
-
+
case 6:
//printf("sun2: Read bus error @ PC %x\n", m_maincpu->pc);
return m_buserror;
-
+
case 7:
//printf("sun2: Read sysenable\n");
return m_sysenable;
}
}
- else // clear for MMU space
+ else // clear for MMU space
{
int page;
-
+
switch (offset & 3)
{
- case 0: // page map
+ case 0: // page map
case 1:
page = m_segmap[m_context & 7][offset >> 14] << 4;
page += ((offset >> 10) & 0xf);
-
+
//printf("sun2: Read page map at %x (entry %d)\n", offset<<1, page);
- if (offset & 1) // low-order 16 bits
+ if (offset & 1) // low-order 16 bits
{
return m_pagemap[page] & 0xffff;
}
return m_pagemap[page] >> 16;
-
+
case 2: // segment map
//printf("sun2: Read segment map at %x (entry %d, user ctx %d)\n", offset<<1, offset>>14, m_context & 7);
return m_segmap[m_context & 7][offset >> 14];
-
+
case 3: // context reg
//printf("sun2: Read context reg\n");
return m_context;
@@ -251,66 +251,66 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// debugger hack
if ((space.debugger_access()) && (offset >= (0xef0000>>1)) && (offset <= (0xef8000>>1)))
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// it's translation time
UINT8 context = (fc & 4) ? ((m_context >> 8) & 7) : (m_context & 7);
UINT8 pmeg = m_segmap[context][offset >> 14];
UINT32 entry = (pmeg << 4) + ((offset >> 10) & 0xf);
- // printf("sun2: Context = %d, pmeg = %d, offset >> 14 = %x, entry = %d, page = %d\n", context, pmeg, offset >> 14, entry, (offset >> 10) & 0xf);
+ // printf("sun2: Context = %d, pmeg = %d, offset >> 14 = %x, entry = %d, page = %d\n", context, pmeg, offset >> 14, entry, (offset >> 10) & 0xf);
if (m_pagemap[entry] & PM_VALID)
{
m_pagemap[entry] |= PM_ACCESSED;
-
+
// Sun2 implementations only use 12 bits from the page entry
UINT32 tmp = (m_pagemap[entry] & 0xfff) << 10;
tmp |= (offset & 0x3ff);
-
- // if (!space.debugger_access())
- // printf("sun2: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, entry, m_pagemap[entry], offset<<1, fc);
+
+ // if (!space.debugger_access())
+ // printf("sun2: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, entry, m_pagemap[entry], offset<<1, fc);
switch ((m_pagemap[entry] >> 22) & 7)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read16(space, tmp, mem_mask);
-
+
case 1: // type 1 space
// EPROM space is special: the MMU has a trap door
// where the original bits of the virtual address are
- // restored so that the entire 32K EPROM can be
+ // restored so that the entire 32K EPROM can be
// accessed via a 2K single page view. This isn't
- // obvious in the sun2 manual, but the sun3 manual
+ // obvious in the sun2 manual, but the sun3 manual
// (sun3 has the same mechanism) explains it well.
// the 2/50 ROM tests this specifically at $EF0DF0.
- if (m_idprom_ptr[1] == 0x02) // 2/50 VMEbus has EPROM at 0x7F0000
+ if (m_idprom_ptr[1] == 0x02) // 2/50 VMEbus has EPROM at 0x7F0000
{
if ((tmp >= (0x7f0000>>1)) && (tmp <= (0x7f07ff>>1)))
{
- return m_rom_ptr[offset & 0x3fff];
+ return m_rom_ptr[offset & 0x3fff];
}
}
- else // Multibus has EPROM at 0x000000
+ else // Multibus has EPROM at 0x000000
{
if (tmp <= (0x7ff>>1))
{
- return m_rom_ptr[offset & 0x3fff];
+ return m_rom_ptr[offset & 0x3fff];
}
}
-
+
//printf("read device space @ %x\n", tmp<<1);
return m_type1space->read16(space, tmp, mem_mask);
-
- case 2: // type 2 space
+
+ case 2: // type 2 space
return m_type2space->read16(space, tmp, mem_mask);
-
- case 3: // type 3 space
+
+ case 3: // type 3 space
return m_type3space->read16(space, tmp, mem_mask);
}
}
@@ -318,28 +318,28 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
{
if (!space.debugger_access()) printf("sun2: pagemap entry not valid!\n");
}
-
+
if (!space.debugger_access()) printf("sun2: Unmapped read @ %08x (FC %d, mask %04x, PC=%x, seg %x)\n", offset<<1, fc, mem_mask, m_maincpu->pc, offset>>15);
-
+
return 0xffff;
}
WRITE16_MEMBER( sun2_state::tl_mmu_w )
{
UINT8 fc = m_maincpu->get_fc();
-
+
//printf("sun2: Write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
-
+
if (fc == 3)
{
- if (offset & 0x4) // set for CPU space
+ if (offset & 0x4) // set for CPU space
{
switch (offset & 7)
{
case 4:
//printf("sun2: Write? IDPROM @ %x\n", offset<<1);
return;
-
+
case 5:
// XOR to match Table 2-1 in the 2/50 Field Service Manual
printf("sun2: CPU LEDs to %02x (PC=%x) => ", (data & 0xff) ^ 0xff, m_maincpu->pc);
@@ -357,30 +357,30 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
}
printf("\n");
return;
-
+
case 6:
//printf("sun2: Write %04x to bus error not allowed\n", data);
return;
-
+
case 7:
//printf("sun2: Write %04x to system enable\n", data);
COMBINE_DATA(&m_sysenable);
return;
}
}
- else // clear for MMU space
+ else // clear for MMU space
{
int page;
-
+
switch (offset & 3)
{
- case 0: // page map
+ case 0: // page map
case 1:
page = m_segmap[m_context & 7][offset >> 14] << 4;
page += ((offset >> 10) & 0xf);
-
+
//printf("sun2: Write %04x to page map at %x (entry %d), ", data, offset<<1, page);
- if (offset & 1) // low-order 16 bits
+ if (offset & 1) // low-order 16 bits
{
m_pagemap[page] &= 0xffff0000;
m_pagemap[page] |= data;
@@ -392,12 +392,12 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
}
//printf("entry now %08x (adr %08x PC=%x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 11, m_maincpu->pc);
return;
-
+
case 2: // segment map
//printf("sun2: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x)\n", data & 0xff, offset<<1, offset>>14, m_context & 7, m_maincpu->pc);
m_segmap[m_context & 7][offset >> 14] = data & 0xff;
return;
-
+
case 3: // context reg
//printf("sun2: Write %04x to context\n", data);
COMBINE_DATA(&m_context);
@@ -405,16 +405,16 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
}
}
}
-
+
// it's translation time
UINT8 context = (fc & 4) ? ((m_context >> 8) & 7) : (m_context & 7);
UINT8 pmeg = m_segmap[context][offset >> 14];
UINT32 entry = (pmeg << 4) + ((offset >> 10) & 0xf);
-
+
if (m_pagemap[entry] & PM_VALID)
{
m_pagemap[entry] |= (PM_ACCESSED | PM_MODIFIED);
-
+
// only 12 of the 20 bits in the page table entry are used on either Sun2 implementation
UINT32 tmp = (m_pagemap[entry] & 0xfff) << 10;
tmp |= (offset & 0x3ff);
@@ -423,20 +423,20 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
switch ((m_pagemap[entry] >> 22) & 7)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write16(space, tmp, data, mem_mask);
return;
-
+
case 1: // type 1
- //printf("write device space @ %x\n", tmp<<1);
+ //printf("write device space @ %x\n", tmp<<1);
m_type1space->write16(space, tmp, data, mem_mask);
return;
-
- case 2: // type 2
+
+ case 2: // type 2
m_type2space->write16(space, tmp, data, mem_mask);
return;
-
- case 3: // type 3
+
+ case 3: // type 3
m_type3space->write16(space, tmp, data, mem_mask);
return;
}
@@ -445,7 +445,7 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
{
if (!space.debugger_access()) printf("sun2: pagemap entry not valid!\n");
}
-
+
printf("sun2: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
}
@@ -475,7 +475,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(vmetype1space_map, AS_PROGRAM, 16, sun2_state)
AM_RANGE(0x000000, 0x01ffff) AM_RAM AM_SHARE("bw2_vram")
AM_RANGE(0x020000, 0x020001) AM_READWRITE( video_ctrl_r, video_ctrl_w )
- AM_RANGE(0x7f0000, 0x7f07ff) AM_ROM AM_REGION("bootprom", 0) // uses MMU loophole to read 32k from a 2k window
+ AM_RANGE(0x7f0000, 0x7f07ff) AM_ROM AM_REGION("bootprom", 0) // uses MMU loophole to read 32k from a 2k window
// 7f0800-7f0fff: Ethernet interface
// 7f1000-7f17ff: AM9518 encryption processor
//AM_RANGE(0x7f1800, 0x7f1801) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, cb_r, cb_w, 0xff00)
@@ -509,7 +509,7 @@ ADDRESS_MAP_END
// type 1 device space
static ADDRESS_MAP_START(mbustype1space_map, AS_PROGRAM, 16, sun2_state)
- AM_RANGE(0x000000, 0x0007ff) AM_ROM AM_REGION("bootprom", 0) // uses MMU loophole to read 32k from a 2k window
+ AM_RANGE(0x000000, 0x0007ff) AM_ROM AM_REGION("bootprom", 0) // uses MMU loophole to read 32k from a 2k window
// 001000-0017ff: AM9518 encryption processor
// 001800-001fff: Parallel port
AM_RANGE(0x002000, 0x0027ff) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00)
@@ -577,7 +577,7 @@ void sun2_state::machine_reset()
m_buserror = 0;
memset(m_segmap, 0, sizeof(m_segmap));
memset(m_pagemap, 0, sizeof(m_pagemap));
-
+
m_maincpu->reset();
}
@@ -585,46 +585,46 @@ static MACHINE_CONFIG_START( sun2vme, sun2_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68010, 16670000)
MCFG_CPU_PROGRAM_MAP(sun2_mem)
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("2M")
MCFG_RAM_EXTRA_OPTIONS("4M,6M,8M")
MCFG_RAM_DEFAULT_VALUE(0x00)
-
+
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
MCFG_SCREEN_ADD("bwtwo", RASTER)
MCFG_SCREEN_UPDATE_DRIVER(sun2_state, bw2_update)
MCFG_SCREEN_SIZE(1152,900)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -645,46 +645,46 @@ static MACHINE_CONFIG_START( sun2mbus, sun2_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68010, 16670000)
MCFG_CPU_PROGRAM_MAP(sun2_mem)
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("2M")
MCFG_RAM_EXTRA_OPTIONS("4M")
MCFG_RAM_DEFAULT_VALUE(0x00)
-
+
// MMU Type 0 device space
MCFG_DEVICE_ADD("type0", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype0space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(mbustype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000000)
-
+
MCFG_SCREEN_ADD("bwtwo", RASTER)
MCFG_SCREEN_UPDATE_DRIVER(sun2_state, bw2_update)
MCFG_SCREEN_SIZE(1152,900)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -707,7 +707,7 @@ ROM_START( sun2_120 )
ROM_LOAD16_WORD_SWAP( "sun2-multi-rev-r.bin", 0x0000, 0x8000, CRC(4df0df77) SHA1(4d6bcf09ddc9cc8f5823847b8ea88f98fe4a642e))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun2120-idprom.bin", 0x000000, 0x000020, CRC(eec8cd1d) SHA1(6a78dc0ea6f9cc7687cffea754d65864fb751ebf) )
+ ROM_LOAD( "sun2120-idprom.bin", 0x000000, 0x000020, CRC(eec8cd1d) SHA1(6a78dc0ea6f9cc7687cffea754d65864fb751ebf) )
ROM_END
ROM_START( sun2_50 )
@@ -716,7 +716,7 @@ ROM_START( sun2_50 )
ROM_LOAD16_BYTE( "250_q_0.rom", 0x0000, 0x4000, CRC(2ee29abe) SHA1(82f52b9f25e92387329581f7c8ba50a171784968))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun250-idprom.bin", 0x000000, 0x000020, CRC(927744ab) SHA1(d29302b69128165e69dd3a79b8c8d45f2163b88a) )
+ ROM_LOAD( "sun250-idprom.bin", 0x000000, 0x000020, CRC(927744ab) SHA1(d29302b69128165e69dd3a79b8c8d45f2163b88a) )
ROM_END
/* Driver */
diff --git a/src/mame/drivers/sun3.cpp b/src/mame/drivers/sun3.cpp
index 4d198c29399..eb76ef1adbb 100644
--- a/src/mame/drivers/sun3.cpp
+++ b/src/mame/drivers/sun3.cpp
@@ -158,7 +158,7 @@
factor. Serial and keyboard ports. External RAM,
framebuffer, and SCSI/ethernet boards
available.
-
+
3/60 ROM breakpoints of interest
fefb104 - bus error test
fefb18e - interrupt test
@@ -194,20 +194,20 @@ fefc34a - start of mem_size, which queries ECC registers for each memory board
#define RS232B_TAG "rs232b"
// page table entry constants
-#define PM_VALID (0x80000000) // page is valid
-#define PM_WRITEMASK (0x40000000) // writable?
-#define PM_SYSMASK (0x20000000) // system use only?
-#define PM_CACHE (0x10000000) // cachable?
-#define PM_TYPEMASK (0x0c000000) // type mask
-#define PM_ACCESSED (0x02000000) // accessed flag
-#define PM_MODIFIED (0x01000000) // modified flag
-
-#define BE_FPENABLE (0x04) // FPU not enabled
-#define BE_FPBERR (0x08) // FPU encountered a bus error
-#define BE_VMEBERR (0x10) // VME encountered a bus error
-#define BE_TIMEOUT (0x20) // timeout - memory doesn't exist
-#define BE_PROTERR (0x40) // protection failed on MMU page lookup
-#define BE_INVALID (0x80) // invalid entry on MMU page lookup
+#define PM_VALID (0x80000000) // page is valid
+#define PM_WRITEMASK (0x40000000) // writable?
+#define PM_SYSMASK (0x20000000) // system use only?
+#define PM_CACHE (0x10000000) // cachable?
+#define PM_TYPEMASK (0x0c000000) // type mask
+#define PM_ACCESSED (0x02000000) // accessed flag
+#define PM_MODIFIED (0x01000000) // modified flag
+
+#define BE_FPENABLE (0x04) // FPU not enabled
+#define BE_FPBERR (0x08) // FPU encountered a bus error
+#define BE_VMEBERR (0x10) // VME encountered a bus error
+#define BE_TIMEOUT (0x20) // timeout - memory doesn't exist
+#define BE_PROTERR (0x40) // protection failed on MMU page lookup
+#define BE_INVALID (0x80) // invalid entry on MMU page lookup
class sun3_state : public driver_device
{
@@ -270,7 +270,7 @@ private:
UINT32 m_pagemap[4096];
UINT32 m_ram_size, m_ram_size_words;
bool m_bInBusErr;
-
+
UINT32 m_cache_tags[0x4000], m_cache_data[0x4000];
};
@@ -280,17 +280,17 @@ READ32_MEMBER( sun3_state::ram_r )
{
//printf("ECC testing, RAM read ofs %x\n", offset);
m_ecc[1] &= 0x00ffffff;
-
- if (m_ecc[2] == 0x01000000) // single-bit error test
+
+ if (m_ecc[2] == 0x01000000) // single-bit error test
{
- m_ecc[1] |= 0x8f000000; // put in the syndrome code the first ECC test wants
-
+ m_ecc[1] |= 0x8f000000; // put in the syndrome code the first ECC test wants
+
if (offset == 0)
{
return 0x80000000;
}
}
- else if (m_ecc[2] == 0x01000200) // double-bit error test
+ else if (m_ecc[2] == 0x01000200) // double-bit error test
{
m_ecc[1] |= 0xfc000000;
}
@@ -305,7 +305,7 @@ READ32_MEMBER( sun3_state::ram_r )
m_buserr = BE_TIMEOUT;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
- }
+ }
return 0xffffffff;
}
@@ -353,10 +353,10 @@ WRITE32_MEMBER( sun3_state::ram_w )
m_parregs[0] |= 0x0f<<24;
break;
}
-
+
// indicate parity interrupt
m_parregs[0] |= 0x80000000;
-
+
// and can we take that now?
if (m_parregs[0] & 0x40000000)
{
@@ -365,7 +365,7 @@ WRITE32_MEMBER( sun3_state::ram_w )
}
}
- if (offset < m_ram_size_words)
+ if (offset < m_ram_size_words)
{
COMBINE_DATA(&m_ram_ptr[offset]);
return;
@@ -384,60 +384,60 @@ WRITE32_MEMBER( sun3_state::ram_w )
READ32_MEMBER( sun3_state::tl_mmu_r )
{
UINT8 fc = m_maincpu->get_fc();
-
+
if ((fc == 3) && !space.debugger_access())
- {
+ {
int page;
-
+
switch (offset >> 26)
{
case 0: // IDPROM
//printf("sun3: Read IDPROM at %x (mask %08x)\n", offset, mem_mask);
return m_idprom_ptr[(offset*4)] << 24 | m_idprom_ptr[(offset*4)+1]<<16 | m_idprom_ptr[(offset*4)+2]<<8 | m_idprom_ptr[(offset*4)+3];
-
- case 1: // page map
+
+ case 1: // page map
page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4;
- page += (offset >> 11) & 0xf;
- //printf("sun3: Read page map at %x (entry %d)\n", offset<<1, page);
+ page += (offset >> 11) & 0xf;
+ //printf("sun3: Read page map at %x (entry %d)\n", offset<<1, page);
return m_pagemap[page];
-
+
case 2: // segment map
//printf("sun3: Read segment map at %x (entry %d, user ctx %d mask %x)\n", offset<<2, (offset & ~0x3c000000) >> 15, m_context & 7, mem_mask);
return m_segmap[m_context & 7][(offset >> 15) & 0x7ff]<<24;
-
+
case 3: // context reg
//printf("sun3: Read context reg\n");
return m_context<<24;
-
+
case 4: // enable reg
return m_enable;
-
+
case 5: // DVMA enable
return m_dvma_enable<<24;
-
+
case 6: // bus error
m_bInBusErr = false;
//printf("Reading bus error: %02x\n", m_buserr);
return m_buserr<<24;
-
+
case 7: // diagnostic reg
return 0;
-
+
case 8: // cache tags
//printf("sun3: read cache tags @ %x, PC = %x\n", offset, m_maincpu->pc);
return m_cache_tags[(offset & 0x3fff) >> 2];
-
+
case 9: // cache data
//printf("sun3: read cache data @ %x, PC = %x\n", offset, m_maincpu->pc);
return m_cache_data[(offset & 0x3fff)];
-
+
case 10: // flush cache
return 0xffffffff;
-
+
case 11: // block copy
printf("sun3: read block copy @ %x, PC = %x\n", offset, m_maincpu->pc);
return 0xffffffff;
-
+
case 15: // UART bypass
//printf("sun3: read UART bypass @ %x, PC = %x, mask = %08x\n", offset, m_maincpu->pc, mem_mask);
return 0xffffffff;
@@ -449,13 +449,13 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// debugger hack
if ((space.debugger_access()) && (offset >= (0xfef0000>>2)) && (offset <= (0xfefffff>>2)))
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// it's translation time
UINT8 pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff];
UINT32 entry = (pmeg << 4) + ((offset >> 11) & 0xf);
@@ -472,40 +472,40 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
m_bInBusErr = true;
return 0xffffffff;
}
-
+
m_pagemap[entry] |= PM_ACCESSED;
-
+
UINT32 tmp = (m_pagemap[entry] & 0x7ffff) << 11;
tmp |= (offset & 0x7ff);
-
+
//printf("pmeg %d, entry %d = %08x, virt %08x => tmp %08x\n", pmeg, entry, m_pagemap[entry], offset << 2, tmp);
-
- // if (!space.debugger_access())
+
+ // if (!space.debugger_access())
//printf("sun3: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, entry, m_pagemap[entry], offset<<2, fc);
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read32(space, tmp, mem_mask);
-
+
case 1: // type 1 space
// magic ROM bypass
if ((tmp >= (0x100000>>2)) && (tmp <= (0x10ffff>>2)))
{
- return m_rom_ptr[offset & 0x3fff];
+ return m_rom_ptr[offset & 0x3fff];
}
return m_type1space->read32(space, tmp, mem_mask);
-
- case 2: // type 2 space
+
+ case 2: // type 2 space
return m_type2space->read32(space, tmp, mem_mask);
-
- case 3: // type 3 space
+
+ case 3: // type 3 space
return m_type3space->read32(space, tmp, mem_mask);
}
}
else
{
-// if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
+// if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
m_buserr = BE_INVALID;
@@ -514,59 +514,59 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
}
if (!space.debugger_access()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc, offset>>15);
-
+
return 0xffffffff;
}
WRITE32_MEMBER( sun3_state::tl_mmu_w )
{
UINT8 fc = m_maincpu->get_fc();
-
+
//printf("sun3: Write %08x (FC %d, mask %08x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
-
- if (fc == 3) // control space
+
+ if (fc == 3) // control space
{
int page;
-
+
switch (offset >> 26)
{
- case 0: // IDPROM
+ case 0: // IDPROM
return;
-
- case 1: // page map fefaf32
+
+ case 1: // page map fefaf32
page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4;
//printf("context = %d, segment = %d, PMEG = %d, add = %d\n", m_context & 7, (offset >> 15) & 0x7ff, page, (offset >> 11) & 0xf);
page += (offset >> 11) & 0xf;
-
+
//printf("sun3: Write %04x to page map at %x (entry %d), ", data, offset<<2, page);
COMBINE_DATA(&m_pagemap[page]);
-
+
//printf("entry now %08x (adr %08x PC=%x mask %x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 13, m_maincpu->pc, mem_mask);
return;
-
+
case 2: // segment map
//printf("sun3: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x mask %x)\n", (data>>24) & 0xff, offset<<2, (offset & ~0x3c000000)>>15, m_context & 7, m_maincpu->pc, mem_mask);
m_segmap[m_context & 7][(offset >> 15) & 0x7ff] = (data>>24) & 0xff;
//printf("segment map[%d][%d] now %x\n", m_context & 7, (offset & ~0x3c000000) >> 15, m_segmap[m_context & 7][(offset & ~0x3c000000) >> 15] = (data>>24) & 0xff);
return;
-
+
case 3: // context reg
//printf("sun3: Write (%x) %x to context\n", data, data>>24);
m_context = data >> 24;
return;
-
+
case 4: // enable reg
//printf("sun3: Write %x to enable, PC=%x\n", data, m_maincpu->pc);
COMBINE_DATA(&m_enable);
return;
-
+
case 5: // DVMA enable
m_dvma_enable = data>>24;
return;
-
+
case 6: // bus error (read-only)
return;
-
+
case 7: // diagnostic reg
m_diag = data >> 24;
#if 0
@@ -574,9 +574,9 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
for (int i = 0; i < 8; i++)
{
if (m_diag & (1<<i))
- {
- printf(".");
- }
+ {
+ printf(".");
+ }
else
{
printf("*");
@@ -585,34 +585,34 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
printf("\n");
#endif
return;
-
+
case 8: // cache tags
//printf("sun3: %08x to cache tags @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask);
m_cache_tags[(offset & 0x3fff) >> 2] = data;
return;
-
+
case 9: // cache data
//printf("sun3: %08x to cache data @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask);
m_cache_data[(offset & 0x3fff)] = data;
return;
-
+
case 10: // flush cache
return;
-
+
case 11: // block copy
printf("sun3: %08x to block copy @ %x, PC = %x\n", data, offset, m_maincpu->pc);
return;
-
+
case 15: // UART bypass
//printf("sun3: %08x to UART bypass @ %x, PC = %x\n", data, offset, m_maincpu->pc);
return;
}
}
-
+
// it's translation time
UINT8 pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff];
UINT32 entry = (pmeg << 4) + ((offset >> 11) & 0xf);
-
+
if (m_pagemap[entry] & PM_VALID)
{
if ((!(m_pagemap[entry] & PM_WRITEMASK)) ||
@@ -625,9 +625,9 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
m_bInBusErr = true;
return;
}
-
+
m_pagemap[entry] |= (PM_ACCESSED | PM_MODIFIED);
-
+
UINT32 tmp = (m_pagemap[entry] & 0x7ffff) << 11;
tmp |= (offset & 0x7ff);
@@ -635,20 +635,20 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write32(space, tmp, data, mem_mask);
return;
-
+
case 1: // type 1
- //printf("write device space @ %x\n", tmp<<1);
+ //printf("write device space @ %x\n", tmp<<1);
m_type1space->write32(space, tmp, data, mem_mask);
return;
-
- case 2: // type 2
+
+ case 2: // type 2
m_type2space->write32(space, tmp, data, mem_mask);
return;
-
- case 3: // type 3
+
+ case 3: // type 3
m_type3space->write32(space, tmp, data, mem_mask);
return;
}
@@ -662,15 +662,15 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
m_bInBusErr = true;
return;
}
-
+
logerror("sun3: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<2);
}
READ32_MEMBER(sun3_state::parity_r)
{
UINT32 rv = m_parregs[offset];
-
- if (offset == 0) // clear interrupt if any
+
+ if (offset == 0) // clear interrupt if any
{
m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
m_parregs[offset] &= ~0x8f000000;
@@ -682,16 +682,16 @@ READ32_MEMBER(sun3_state::parity_r)
WRITE32_MEMBER(sun3_state::parity_w)
{
//printf("sun3: %08x to parity registers @ %x (mask %08x)\n", data, offset, mem_mask);
-
+
if (offset == 0)
{
m_parregs[0] &= 0x8f000000;
-
+
if ((m_parregs[0] & 0x80000000) && (data & 0x40000000))
{
m_maincpu->set_input_line(M68K_IRQ_7, ASSERT_LINE);
}
-
+
m_parregs[0] |= (data & 0x70000000);
}
else
@@ -707,7 +707,7 @@ ADDRESS_MAP_END
// type 0 device space
static ADDRESS_MAP_START(vmetype0space_map, AS_PROGRAM, 32, sun3_state)
AM_RANGE(0x00000000, 0x08ffffff) AM_READWRITE(ram_r, ram_w)
- AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM // not sure what's going on here (3/110)
+ AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM // not sure what's going on here (3/110)
AM_RANGE(0xff000000, 0xff03ffff) AM_RAM AM_SHARE("bw2_vram")
ADDRESS_MAP_END
@@ -720,7 +720,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(vmetype1space_map, AS_PROGRAM, 32, sun3_state)
AM_RANGE(0x00000000, 0x0000000f) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
AM_RANGE(0x00020000, 0x0002000f) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
- AM_RANGE(0x00040000, 0x000407ff) AM_RAM AM_SHARE("nvram") // type 2816 parallel EEPROM
+ AM_RANGE(0x00040000, 0x000407ff) AM_RAM AM_SHARE("nvram") // type 2816 parallel EEPROM
AM_RANGE(0x00060000, 0x0006ffff) AM_READWRITE8(rtc7170_r, rtc7170_w, 0xffffffff)
AM_RANGE(0x00080000, 0x0008000f) AM_READWRITE(parity_r, parity_w)
AM_RANGE(0x000a0000, 0x000a0003) AM_READWRITE(irqctrl_r, irqctrl_w)
@@ -776,19 +776,19 @@ WRITE32_MEMBER(sun3_state::irqctrl_w)
READ8_MEMBER(sun3_state::rtc7170_r)
{
//printf("read 7170 @ %x, PC=%x\n", offset, m_maincpu->pc);
-
+
return 0xff;
}
WRITE8_MEMBER(sun3_state::rtc7170_w)
{
//printf("%02x to 7170 @ %x\n", data, offset);
-
+
if ((offset == 0x11) && (data == 0x1c))
{
if ((m_irqctrl & 0x21000000) == 0x21000000)
{
- m_maincpu->set_input_line(M68K_IRQ_5, ASSERT_LINE);
+ m_maincpu->set_input_line(M68K_IRQ_5, ASSERT_LINE);
}
}
}
@@ -799,27 +799,27 @@ READ32_MEMBER(sun3_state::ecc_r)
// fefc34a
int mbram = (m_ram_size / (1024*1024));
int beoff = (mbram / 32) * 0x10;
-
+
//printf("offset %x MB %d beoff %x\n", offset, mbram, beoff);
-
+
if (offset >= beoff)
{
m_buserr = BE_TIMEOUT;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
-
+
UINT32 rv = m_ecc[offset & 0xf];
-
- if ((offset & 0xf) == 0) rv |= 0x06000000; // indicate each ECC board is 32MB, for 128MB total
-
+
+ if ((offset & 0xf) == 0) rv |= 0x06000000; // indicate each ECC board is 32MB, for 128MB total
+
return rv;
}
WRITE32_MEMBER(sun3_state::ecc_w)
{
//printf("%08x to ecc @ %x, mask %08x\n", data, offset, mem_mask);
-
+
offset &= 0xf;
m_ecc[offset] = data;
}
@@ -928,11 +928,11 @@ void sun3_state::machine_start()
m_ram_ptr = (UINT32 *)m_ram->pointer();
m_idprom_ptr = (UINT8 *)m_idprom->base();
m_ram_size = m_ram->size();
- m_ram_size_words = m_ram_size >> 2;
+ m_ram_size_words = m_ram_size >> 2;
}
void sun3_state::machine_reset()
-{
+{
m_maincpu->reset();
m_enable = 0;
m_buserr = 0;
@@ -953,7 +953,7 @@ static MACHINE_CONFIG_START( sun3, sun3_state )
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("4M")
MCFG_RAM_EXTRA_OPTIONS("6M,8M,12M,16M,20M,24M,28M,32M")
@@ -967,30 +967,30 @@ static MACHINE_CONFIG_START( sun3, sun3_state )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100))
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -1011,7 +1011,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( sun3_60, sun3 )
MCFG_CPU_REPLACE("maincpu", M68020, 20000000)
MCFG_CPU_PROGRAM_MAP(sun3_mem)
-
+
MCFG_SCREEN_MODIFY("bwtwo")
MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_16x11_update)
MCFG_SCREEN_SIZE(1600,1100)
@@ -1029,13 +1029,13 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( sun3200, sun3 )
MCFG_CPU_REPLACE("maincpu", M68020, 25000000)
MCFG_CPU_PROGRAM_MAP(sun3_mem)
-
+
MCFG_SCREEN_MODIFY("bwtwo")
MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_16x11_update)
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1600-1, 0, 1100-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_RAM_MODIFY(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("32M")
MCFG_RAM_EXTRA_OPTIONS("64M,96M,128M")
@@ -1051,11 +1051,11 @@ static MACHINE_CONFIG_START( sun3_50, sun3_state )
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_NVRAM_ADD_0FILL("nvram")
-
+
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100))
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("4M")
MCFG_RAM_DEFAULT_VALUE(0x00)
@@ -1066,28 +1066,28 @@ static MACHINE_CONFIG_START( sun3_50, sun3_state )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -1133,7 +1133,7 @@ Sun 3/50 V2.8 Bootprom
ROMX_LOAD( "sun3_50_v1.6", 0x0000, 0x10000, CRC(8be20826) SHA1(2a4d73fcb7fe0f0c83eb0f4c91d957b7bf88b7ed), ROM_BIOS(5))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-50-idprom.bin", 0x000000, 0x000020, CRC(80610dbe) SHA1(0f37e31ed209b8905c5dc7c2663fa01a9b9baaba) )
+ ROM_LOAD( "sun3-50-idprom.bin", 0x000000, 0x000020, CRC(80610dbe) SHA1(0f37e31ed209b8905c5dc7c2663fa01a9b9baaba) )
ROM_END
ROM_START( sun3_60 )
@@ -1155,7 +1155,7 @@ Sun 3/60 V3.0.1 Bootprom
ROMX_LOAD( "sun_3.60v1.9", 0x0000, 0x10000, CRC(32b6d3a9) SHA1(307756ba5698611d51059881057f8086956ce895), ROM_BIOS(3))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-60-idprom.bin", 0x000000, 0x000020, CRC(117e766a) SHA1(f01547be0156bd4e06bbdee4c342d1b38c7646ae) )
+ ROM_LOAD( "sun3-60-idprom.bin", 0x000000, 0x000020, CRC(117e766a) SHA1(f01547be0156bd4e06bbdee4c342d1b38c7646ae) )
ROM_END
ROM_START( sun3_110 )
@@ -1228,7 +1228,7 @@ Sun 3/260/280 V3.0 Bootprom
ROMX_LOAD( "sun3_260_v2.6", 0x0000, 0x10000, CRC(e8b17951) SHA1(e1fdef42670a349d99b0eca9c50c8566b8bb7c56), ROM_BIOS(3))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-260-idprom.bin", 0x000000, 0x000020, CRC(d51794f3) SHA1(17930c773b6fe9a32819094ffaf69e5453d1ea4d) )
+ ROM_LOAD( "sun3-260-idprom.bin", 0x000000, 0x000020, CRC(d51794f3) SHA1(17930c773b6fe9a32819094ffaf69e5453d1ea4d) )
ROM_END
ROM_START( sun3_e )
@@ -1237,7 +1237,7 @@ ROM_START( sun3_e )
ROMX_LOAD( "sun3_e.32", 0x0000, 0x10000, CRC(acedde7e) SHA1(1ab6ec28f4365a613a5e326c34cb37585c3f0ecc), ROM_BIOS(1))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-e-idprom.bin", 0x000000, 0x000020, CRC(d1a92116) SHA1(4836f3188f2c3dd5ba49ab66e0b55caa6b1b1791) )
+ ROM_LOAD( "sun3-e-idprom.bin", 0x000000, 0x000020, CRC(d1a92116) SHA1(4836f3188f2c3dd5ba49ab66e0b55caa6b1b1791) )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
diff --git a/src/mame/drivers/sun4.cpp b/src/mame/drivers/sun4.cpp
index 7b3d00a240b..95551566d5e 100644
--- a/src/mame/drivers/sun4.cpp
+++ b/src/mame/drivers/sun4.cpp
@@ -381,15 +381,15 @@
21/11/2011 Skeleton driver.
20/06/2016 Much less skeletony.
-
+
4/60 ROM notes:
-
+
ffe809fc: call to print "Sizing Memory" to the UART
- ffe80a70: call to "Setting up RAM for monitor" that goes wrong
- ffe80210: testing memory
- ffe80274: loop that goes wobbly and fails
- ffe80dc4: switch off boot mode, MMU maps ROM to copy in RAM from here on
- ffe82000: start of FORTH (?) interpreter once decompressed
+ ffe80a70: call to "Setting up RAM for monitor" that goes wrong
+ ffe80210: testing memory
+ ffe80274: loop that goes wobbly and fails
+ ffe80dc4: switch off boot mode, MMU maps ROM to copy in RAM from here on
+ ffe82000: start of FORTH (?) interpreter once decompressed
text in decmopressed area claims to be FORTH-83 FCode, but the opcodes
do not match the documented OpenFirmware FCode ones at all.
@@ -415,26 +415,26 @@
#define RS232A_TAG "rs232a"
#define RS232B_TAG "rs232b"
-#define ENA_NOTBOOT (0x80)
-#define ENA_SDVMA (0x20)
-#define ENA_CACHE (0x10)
-#define ENA_RESET (0x04)
-#define ENA_DIAG (0x01)
+#define ENA_NOTBOOT (0x80)
+#define ENA_SDVMA (0x20)
+#define ENA_CACHE (0x10)
+#define ENA_RESET (0x04)
+#define ENA_DIAG (0x01)
// page table entry constants
-#define PM_VALID (0x80000000) // page is valid
-#define PM_WRITEMASK (0x40000000) // writable?
-#define PM_SYSMASK (0x20000000) // system use only?
-#define PM_CACHE (0x10000000) // cachable?
-#define PM_TYPEMASK (0x0c000000) // type mask
-#define PM_ACCESSED (0x02000000) // accessed flag
-#define PM_MODIFIED (0x01000000) // modified flag
+#define PM_VALID (0x80000000) // page is valid
+#define PM_WRITEMASK (0x40000000) // writable?
+#define PM_SYSMASK (0x20000000) // system use only?
+#define PM_CACHE (0x10000000) // cachable?
+#define PM_TYPEMASK (0x0c000000) // type mask
+#define PM_ACCESSED (0x02000000) // accessed flag
+#define PM_MODIFIED (0x01000000) // modified flag
namespace
{
const sparc_disassembler::asi_desc_map::value_type sun4_asi_desc[] = {
- { 0x10, { nullptr, "Flush I-Cache (Segment)" } },
- { 0x11, { nullptr, "Flush I-Cache (Page)" } },
+ { 0x10, { nullptr, "Flush I-Cache (Segment)" } },
+ { 0x11, { nullptr, "Flush I-Cache (Page)" } },
{ 0x02, { nullptr, "System Space" } }, { 0x12, { nullptr, "Flush I-Cache (Context)" } },
{ 0x03, { nullptr, "Segment Map" } }, { 0x13, { nullptr, "Flush I-Cache (User)" } },
{ 0x04, { nullptr, "Page Map" } }, { 0x14, { nullptr, "Flush D-Cache (Segment)" } },
@@ -452,16 +452,16 @@ const sparc_disassembler::asi_desc_map::value_type sun4_asi_desc[] = {
};
/* TODO: make SPARCstation-1 a different machine type so it can load its own ASI descriptions - it's a subset of Sun4
const sparc_disassembler::asi_desc_map::value_type sun4c_asi_desc[] = {
- { 0x02, { nullptr, "System Space" } },
- { 0x03, { nullptr, "Segment Map" } },
- { 0x04, { nullptr, "Page Map" } },
- { 0x08, { nullptr, "User Instruction" } },
- { 0x09, { nullptr, "Supervisor Instruction" } },
- { 0x0a, { nullptr, "User Data" } },
- { 0x0b, { nullptr, "Supervisor Data" } },
- { 0x0c, { nullptr, "Flush Cache (Segment)" } },
- { 0x0d, { nullptr, "Flush Cache (Page)" } },
- { 0x0e, { nullptr, "Flush Cache (Context)" } }
+ { 0x02, { nullptr, "System Space" } },
+ { 0x03, { nullptr, "Segment Map" } },
+ { 0x04, { nullptr, "Page Map" } },
+ { 0x08, { nullptr, "User Instruction" } },
+ { 0x09, { nullptr, "Supervisor Instruction" } },
+ { 0x0a, { nullptr, "User Data" } },
+ { 0x0b, { nullptr, "Supervisor Data" } },
+ { 0x0c, { nullptr, "Flush Cache (Segment)" } },
+ { 0x0d, { nullptr, "Flush Cache (Page)" } },
+ { 0x0e, { nullptr, "Flush Cache (Context)" } }
};
*/
}
@@ -492,7 +492,7 @@ public:
DECLARE_WRITE32_MEMBER( ram_w );
DECLARE_READ32_MEMBER( ss1_sl0_id );
DECLARE_READ32_MEMBER( ss1_sl3_id );
-
+
protected:
required_device<mb86901_device> m_maincpu;
required_device<z80scc_device> m_scc1;
@@ -510,7 +510,7 @@ private:
UINT8 m_segmap[8][4096];
UINT32 m_pagemap[8192];
UINT32 m_ram_size, m_ram_size_words;
-
+
void l2p_command(int ref, int params, const char **param);
};
@@ -521,18 +521,18 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
// make debugger fetches emulate supervisor program for best compatibility with boot PROM execution
if (space.debugger_access()) asi = 9;
-
+
// supervisor program fetches in boot state are special
if ((!(m_system_enable & ENA_NOTBOOT)) && (asi == 9))
{
return m_rom_ptr[offset & 0x1ffff];
}
-
+
switch (asi)
{
- case 2: // system space
+ case 2: // system space
switch (offset >> 26)
- {
+ {
case 3: // context reg
return m_context<<24;
@@ -550,8 +550,8 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
case 9: // (d-)cache data
logerror("sun4: read dcache data @ %x, PC = %x\n", offset, m_maincpu->pc());
return 0xffffffff;
-
- case 0xf: // UART bypass
+
+ case 0xf: // UART bypass
//printf("read UART bypass @ %x mask %08x\n", offset<<2, mem_mask);
switch (offset & 3)
{
@@ -566,7 +566,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
return 0;
}
break;
- case 3: // segment map
+ case 3: // segment map
//printf("sun4: read segment map @ %x (entry %d, mem_mask %08x, PC=%x)\n", offset << 2, (offset>>16) & 0xfff, mem_mask, m_maincpu->pc());
if (mem_mask == 0xffff0000)
{
@@ -576,9 +576,9 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
{
return m_segmap[m_context][(offset>>16) & 0xfff]<<24;
}
- else
+ else
{
- // printf("sun4: read segment map w/unk mask %08x\n", mem_mask);
+ // printf("sun4: read segment map w/unk mask %08x\n", mem_mask);
}
return 0x0;
@@ -588,7 +588,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
//printf("sun4: read page map @ %x (entry %d, mem_mask %08x, PC=%x)\n", offset << 2, page, mem_mask, m_maincpu->pc());
return m_pagemap[page];
break;
-
+
case 8:
case 9:
case 10:
@@ -601,26 +601,26 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
if (m_pagemap[entry] & PM_VALID)
{
m_pagemap[entry] |= PM_ACCESSED;
-
+
UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10;
tmp |= (offset & 0x3ff);
-
+
//printf("sun4: read translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc());
-
+
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read32(space, tmp, mem_mask);
-
+
case 1: // type 1 space
// magic EPROM bypass
if ((tmp >= (0x6000000>>2)) && (tmp <= (0x6ffffff>>2)))
{
- return m_rom_ptr[offset & 0x1ffff];
+ return m_rom_ptr[offset & 0x1ffff];
}
//printf("Read type 1 @ VA %08x, phys %08x\n", offset<<2, tmp<<2);
return m_type1space->read32(space, tmp, mem_mask);
-
+
default:
printf("sun4: access to memory type not defined in sun4c\n");
return 0;
@@ -632,19 +632,19 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
{
printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
- //m_buserror[0] = 0x88; // read, invalid PTE
+ //m_buserror[0] = 0x88; // read, invalid PTE
//m_buserror[1] = offset<<2;
}
return 0;
- }
+ }
}
break;
-
+
default:
if (!space.debugger_access()) printf("sun4: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
return 0;
}
-
+
printf("sun4: read asi %d byte offset %x, PC = %x\n", asi, offset << 2, m_maincpu->pc());
return 0;
@@ -678,8 +678,8 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
case 9: // cache data
logerror("sun4: %08x to cache data @ %x, PC = %x\n", data, offset, m_maincpu->pc());
return;
-
- case 0xf: // UART bypass
+
+ case 0xf: // UART bypass
//printf("%08x to UART @ %d, mask %08x\n", data, offset & 3, mem_mask);
switch (offset & 3)
{
@@ -701,18 +701,18 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
if (mem_mask == 0xffff0000) segdata = (data >> 16) & 0x7f;
else if (mem_mask == 0xff000000) segdata = (data >> 24) & 0x7f;
else logerror("sun4: writing segment map with unknown mask %08x, PC=%x\n", mem_mask, m_maincpu->pc());
-
+
//printf("sun4: %08x to segment map @ %x (entry %d, mem_mask %08x, PC=%x)\n", segdata, offset << 2, (offset>>16) & 0xfff, mem_mask, m_maincpu->pc());
- m_segmap[m_context & 7][(offset>>16) & 0xfff] = segdata; // only 7 bits of the segment are necessary
+ m_segmap[m_context & 7][(offset>>16) & 0xfff] = segdata; // only 7 bits of the segment are necessary
}
return;
-
+
case 4: // page map
- page = m_segmap[m_context & 7][(offset >> 16) & 0xfff] << 6; // get the PMEG
- page += (offset >> 10) & 0x3f; // add the offset
+ page = m_segmap[m_context & 7][(offset >> 16) & 0xfff] << 6; // get the PMEG
+ page += (offset >> 10) & 0x3f; // add the offset
//printf("sun4: %08x to page map @ %x (entry %d, mem_mask %08x, PC=%x)\n", data, offset << 2, page, mem_mask, m_maincpu->pc());
COMBINE_DATA(&m_pagemap[page]);
- m_pagemap[page] &= 0xff00ffff; // these 8 bits are cleared when written and tested as such
+ m_pagemap[page] &= 0xff00ffff; // these 8 bits are cleared when written and tested as such
return;
case 8:
case 9:
@@ -725,20 +725,20 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
if (m_pagemap[entry] & PM_VALID)
{
m_pagemap[entry] |= PM_ACCESSED;
-
+
UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10;
tmp |= (offset & 0x3ff);
-
+
//printf("sun4: write translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc());
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write32(space, tmp, data, mem_mask);
return;
-
+
case 1: // type 1
- //printf("write device space @ %x\n", tmp<<1);
+ //printf("write device space @ %x\n", tmp<<1);
m_type1space->write32(space, tmp, data, mem_mask);
return;
default:
@@ -750,26 +750,26 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
{
printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
- //m_buserror[0] = 0x8; // invalid PTE
+ //m_buserror[0] = 0x8; // invalid PTE
//m_buserror[1] = offset<<2;
return;
}
break;
-
+
}
printf("sun4: %08x to asi %d byte offset %x, PC = %x, mask = %08x\n", data, asi, offset << 2, m_maincpu->pc(), mem_mask);
}
void sun4_state::l2p_command(int ref, int params, const char **param)
-{
+{
UINT64 addr, offset;
-
+
if (!machine().debugger().commands().validate_number_parameter(param[0], &addr)) return;
-
+
addr &= 0xffffffff;
offset = addr >> 2;
-
+
UINT8 pmeg = m_segmap[m_context & 7][(offset >> 16) & 0xfff];
UINT32 entry = (pmeg << 6) + ((offset >> 10) & 0x3f);
UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10;
@@ -805,8 +805,8 @@ void sun4_state::machine_start()
m_rom_ptr = (UINT32 *)m_rom->base();
m_ram_ptr = (UINT32 *)m_ram->pointer();
m_ram_size = m_ram->size();
- m_ram_size_words = m_ram_size >> 2;
-
+ m_ram_size_words = m_ram_size >> 2;
+
if (machine().debug_flags & DEBUG_FLAG_ENABLED)
{
using namespace std::placeholders;
@@ -867,10 +867,10 @@ WRITE32_MEMBER( sun4_state::ram_w )
m_parregs[0] |= 0x0f<<24;
break;
}
-
+
// indicate parity interrupt
m_parregs[0] |= 0x80000000;
-
+
// and can we take that now?
if (m_parregs[0] & 0x40000000)
{
@@ -882,7 +882,7 @@ WRITE32_MEMBER( sun4_state::ram_w )
//if ((offset<<2) == 0xfb2000) printf("write %08x to %08x, mask %08x, PC=%x\n", data, offset<<2, mem_mask, m_maincpu->pc());
- if (offset < m_ram_size_words)
+ if (offset < m_ram_size_words)
{
COMBINE_DATA(&m_ram_ptr[offset]);
return;
@@ -897,9 +897,9 @@ static ADDRESS_MAP_START(type1space_map, AS_PROGRAM, 32, sun4_state)
AM_RANGE(0x00000000, 0x0000000f) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
AM_RANGE(0x01000000, 0x0100000f) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
AM_RANGE(0x02000000, 0x020007ff) AM_DEVREADWRITE8(TIMEKEEPER_TAG, timekeeper_device, read, write, 0xffffffff)
- AM_RANGE(0x06000000, 0x0607ffff) AM_ROM AM_REGION("user1", 0)
- AM_RANGE(0x08000000, 0x08000003) AM_READ(ss1_sl0_id) // slot 0 contains SCSI/DMA/Ethernet
- AM_RANGE(0x0e000000, 0x0e000003) AM_READ(ss1_sl3_id) // slot 3 contains video board
+ AM_RANGE(0x06000000, 0x0607ffff) AM_ROM AM_REGION("user1", 0)
+ AM_RANGE(0x08000000, 0x08000003) AM_READ(ss1_sl0_id) // slot 0 contains SCSI/DMA/Ethernet
+ AM_RANGE(0x0e000000, 0x0e000003) AM_READ(ss1_sl3_id) // slot 3 contains video board
ADDRESS_MAP_END
// indicate 4/60 SCSI/DMA/Ethernet card exists
@@ -932,7 +932,7 @@ static MACHINE_CONFIG_START( sun4, sun4_state )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(type1space_map)
diff --git a/src/mame/drivers/system16.cpp b/src/mame/drivers/system16.cpp
index 3291f592b37..2316b5b72f4 100644
--- a/src/mame/drivers/system16.cpp
+++ b/src/mame/drivers/system16.cpp
@@ -2090,7 +2090,7 @@ static MACHINE_CONFIG_DERIVED( shinobi_datsu, system16_base )
MCFG_VIDEO_START_OVERRIDE(segas1x_bootleg_state, s16a_bootleg_shinobi )
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(segas1x_bootleg_state, screen_update_s16a_bootleg)
-
+
MCFG_FRAGMENT_ADD(datsu_2x_ym2203)
MACHINE_CONFIG_END
@@ -2127,7 +2127,7 @@ static MACHINE_CONFIG_DERIVED( passsht4b, system16_base )
MCFG_VIDEO_START_OVERRIDE(segas1x_bootleg_state, s16a_bootleg_passsht )
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(segas1x_bootleg_state, screen_update_s16a_bootleg_passht4b)
-
+
MCFG_FRAGMENT_ADD(datsu_2x_ym2203)
MACHINE_CONFIG_END
@@ -2145,7 +2145,7 @@ static MACHINE_CONFIG_DERIVED( wb3bb, system16_base )
MCFG_VIDEO_START_OVERRIDE(segas1x_bootleg_state, s16a_bootleg_wb3bl )
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_UPDATE_DRIVER(segas1x_bootleg_state, screen_update_s16a_bootleg)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151)
MACHINE_CONFIG_END
@@ -2231,7 +2231,7 @@ static MACHINE_CONFIG_DERIVED( dduxbl, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-112)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151)
MACHINE_CONFIG_END
@@ -2243,7 +2243,7 @@ static MACHINE_CONFIG_DERIVED( eswatbl, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-124)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151_upd7759)
MACHINE_CONFIG_END
@@ -2257,7 +2257,7 @@ static MACHINE_CONFIG_DERIVED( tetrisbl, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-112)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151)
MACHINE_CONFIG_END
@@ -2268,7 +2268,7 @@ static MACHINE_CONFIG_DERIVED( altbeastbl, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-112)
-
+
MCFG_FRAGMENT_ADD(datsu_2x_ym2203)
MACHINE_CONFIG_END
@@ -2280,7 +2280,7 @@ static MACHINE_CONFIG_DERIVED( beautyb, system16_base )
MCFG_BOOTLEG_SYS16B_SPRITES_ADD("sprites")
MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(189-112)
-
+
MCFG_FRAGMENT_ADD(z80_ym2151)
MACHINE_CONFIG_END
@@ -3009,7 +3009,7 @@ ROM_START( mutantwarr )
ROM_REGION( 0x60000, "gfx1", ROMREGION_INVERT ) // tiles
ROM_LOAD( "16.bin", 0x00000, 0x10000, CRC(a4967d10) SHA1(537b9ea604a38a919c111ece5dd3e55a5070d346) ) // plane 1
- ROM_LOAD( "15.bin", 0x10000, 0x10000, CRC(e091ae2c) SHA1(5a129f2445d13c321cb3ad0eff7ab8ea3f6ddf43) )
+ ROM_LOAD( "15.bin", 0x10000, 0x10000, CRC(e091ae2c) SHA1(5a129f2445d13c321cb3ad0eff7ab8ea3f6ddf43) )
ROM_LOAD( "14.bin", 0x20000, 0x10000, CRC(1a26cf3f) SHA1(3a488ee485db7b3f27d5ed6c6e7d263d4840bd6a) ) // plane 2
ROM_LOAD( "13.bin", 0x30000, 0x10000, CRC(277ef086) SHA1(d7a5e944f5287aa15d14ff940d1aca8d1e649d26) )
ROM_LOAD( "12.bin", 0x40000, 0x10000, CRC(661225af) SHA1(115303efeb5676ab059600a48edf36b8a56f6c15) ) // plane 3
diff --git a/src/mame/drivers/tek440x.cpp b/src/mame/drivers/tek440x.cpp
index f56f9dbd306..8072e4f2cf9 100755
--- a/src/mame/drivers/tek440x.cpp
+++ b/src/mame/drivers/tek440x.cpp
@@ -3,48 +3,48 @@
/***************************************************************************
Tektronix 440x "AI Workstations"
-
+
skeleton by R. Belmont
Hardware overview:
* 68010 (4404) or 68020 (4405) with custom MMU
- * Intelligent floppy subsystem with 6502 driving a uPD765 controller
- * NS32081 FPU
- * 6551 debug console AICA
- * SN76496 PSG for sound
- * MC146818 RTC
- * MC68681 DUART / timer (3.6864 MHz clock) (serial channel A = keyboard, channel B = RS-232 port)
- * AM9513 timer (source of timer IRQ)
- * NCR5385 SCSI controller
-
- Video is a 640x480 1bpp window on a 1024x1024 VRAM area; smooth panning around that area
- is possible as is flat-out changing the scanout address.
-
- IRQ levels:
- 7 = Debug (NMI)
- 6 = VBL
- 5 = UART
- 4 = Spare (exp slots)
- 3 = SCSI
- 2 = DMA
- 1 = Timer
- 0 = Unused
-
- MMU info:
- Map control register (location unk): bit 15 = VM enable, bits 10-8 = process ID
-
- Map entries:
- bit 15 = dirty
- bit 14 = write enable
- bit 13-11 = process ID
- bits 10-0 = address bits 22-12 in the final address
+ * Intelligent floppy subsystem with 6502 driving a uPD765 controller
+ * NS32081 FPU
+ * 6551 debug console AICA
+ * SN76496 PSG for sound
+ * MC146818 RTC
+ * MC68681 DUART / timer (3.6864 MHz clock) (serial channel A = keyboard, channel B = RS-232 port)
+ * AM9513 timer (source of timer IRQ)
+ * NCR5385 SCSI controller
+
+ Video is a 640x480 1bpp window on a 1024x1024 VRAM area; smooth panning around that area
+ is possible as is flat-out changing the scanout address.
+
+ IRQ levels:
+ 7 = Debug (NMI)
+ 6 = VBL
+ 5 = UART
+ 4 = Spare (exp slots)
+ 3 = SCSI
+ 2 = DMA
+ 1 = Timer
+ 0 = Unused
+
+ MMU info:
+ Map control register (location unk): bit 15 = VM enable, bits 10-8 = process ID
+
+ Map entries:
+ bit 15 = dirty
+ bit 14 = write enable
+ bit 13-11 = process ID
+ bits 10-0 = address bits 22-12 in the final address
***************************************************************************/
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "cpu/m6502/m6502.h"
-#include "machine/mos6551.h" // debug tty
+#include "machine/mos6551.h" // debug tty
#include "machine/mc146818.h"
#include "bus/rs232/rs232.h"
@@ -58,7 +58,7 @@ public:
m_mainram(*this, "mainram"),
m_vram(*this, "vram")
{}
-
+
virtual void machine_start() override;
virtual void machine_reset() override;
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
@@ -92,8 +92,8 @@ void tek440x_state::machine_reset()
UINT8 *RAM = (UINT8 *)m_mainram.target();
memcpy(RAM, ROM, 256);
-
- m_maincpu->reset();
+
+ m_maincpu->reset();
}
@@ -183,7 +183,7 @@ static MACHINE_CONFIG_START( tek4404, tek440x_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68010, 166666666)
MCFG_CPU_PROGRAM_MAP(maincpu_map)
-
+
MCFG_CPU_ADD("fdccpu", M6502, 1000000)
MCFG_CPU_PROGRAM_MAP(fdccpu_map)
@@ -197,7 +197,7 @@ static MACHINE_CONFIG_START( tek4404, tek440x_state )
MCFG_SCREEN_UPDATE_DRIVER(tek440x_state, screen_update)
MCFG_SCREEN_PALETTE("palette")
MCFG_PALETTE_ADD_MONOCHROME("palette")
-
+
MCFG_DEVICE_ADD("aica", MOS6551, 0)
MCFG_MOS6551_XTAL(XTAL_1_8432MHz)
MCFG_MOS6551_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
@@ -219,14 +219,14 @@ MACHINE_CONFIG_END
ROM_START( tek4404 )
ROM_REGION( 0x8000, "maincpu", 0 )
- ROM_LOAD16_BYTE( "tek_u158.bin", 0x000000, 0x004000, CRC(9939e660) SHA1(66b4309e93e4ff20c1295dc2ec2a8d6389b2578c) )
- ROM_LOAD16_BYTE( "tek_u163.bin", 0x000001, 0x004000, CRC(a82dcbb1) SHA1(a7e4545e9ea57619faacc1556fa346b18f870084) )
-
+ ROM_LOAD16_BYTE( "tek_u158.bin", 0x000000, 0x004000, CRC(9939e660) SHA1(66b4309e93e4ff20c1295dc2ec2a8d6389b2578c) )
+ ROM_LOAD16_BYTE( "tek_u163.bin", 0x000001, 0x004000, CRC(a82dcbb1) SHA1(a7e4545e9ea57619faacc1556fa346b18f870084) )
+
ROM_REGION( 0x1000, "fdccpu", 0 )
- ROM_LOAD( "tek_u130.bin", 0x000000, 0x001000, CRC(2c11a3f1) SHA1(b29b3705692d50f15f7e8bbba12a24c69817d52e) )
-
+ ROM_LOAD( "tek_u130.bin", 0x000000, 0x001000, CRC(2c11a3f1) SHA1(b29b3705692d50f15f7e8bbba12a24c69817d52e) )
+
ROM_REGION( 0x2000, "scsimfm", 0 )
- ROM_LOAD( "scsi_mfm.bin", 0x000000, 0x002000, CRC(b4293435) SHA1(5e2b96c19c4f5c63a5afa2de504d29fe64a4c908) )
+ ROM_LOAD( "scsi_mfm.bin", 0x000000, 0x002000, CRC(b4293435) SHA1(5e2b96c19c4f5c63a5afa2de504d29fe64a4c908) )
ROM_END
/*************************************
diff --git a/src/mame/drivers/toaplan1.cpp b/src/mame/drivers/toaplan1.cpp
index 2bae7de4e7c..36ea7c5ec07 100644
--- a/src/mame/drivers/toaplan1.cpp
+++ b/src/mame/drivers/toaplan1.cpp
@@ -792,7 +792,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( outzonecv_main_map, AS_PROGRAM, 16, toaplan1_state )
AM_RANGE(0x000000, 0x03ffff) AM_ROM
-// AM_RANGE(0x040000, 0x07ffff) AM_ROM
+// AM_RANGE(0x040000, 0x07ffff) AM_ROM
AM_RANGE(0x080000, 0x087fff) AM_RAM
AM_RANGE(0x0c0000, 0x0c0003) AM_WRITE(toaplan1_tile_offsets_w)
AM_RANGE(0x0c0006, 0x0c0007) AM_WRITE(toaplan1_fcu_flipscreen_w)
diff --git a/src/mame/drivers/toaplan2.cpp b/src/mame/drivers/toaplan2.cpp
index d546fbe5786..afaf0db60da 100644
--- a/src/mame/drivers/toaplan2.cpp
+++ b/src/mame/drivers/toaplan2.cpp
@@ -3180,9 +3180,9 @@ static MACHINE_CONFIG_START( dogyuun, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_25MHz/2) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(v25_mem)
MCFG_V25_CONFIG(nitro_decryption_table)
- MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
MCFG_V25_PORT_P2_WRITE_CB(NOOP) // bit 0 is FAULT according to kbash schematic
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@@ -3228,9 +3228,9 @@ static MACHINE_CONFIG_START( kbash, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_16MHz) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(kbash_v25_mem)
MCFG_V25_CONFIG(nitro_decryption_table)
- MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
MCFG_V25_PORT_P2_WRITE_CB(NOOP) // bit 0 is FAULT according to kbash schematic
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@@ -3569,9 +3569,9 @@ static MACHINE_CONFIG_START( vfive, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_20MHz/2) /* Verified on pcb, NEC V25 type Toaplan mark scratched out */
MCFG_CPU_PROGRAM_MAP(vfive_v25_mem)
MCFG_V25_CONFIG(nitro_decryption_table)
- MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
MCFG_V25_PORT_P2_WRITE_CB(NOOP) // bit 0 is FAULT according to kbash schematic
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
@@ -3609,9 +3609,9 @@ static MACHINE_CONFIG_START( batsugun, toaplan2_state )
MCFG_CPU_ADD("audiocpu", V25, XTAL_32MHz/2) /* NEC V25 type Toaplan marked CPU ??? */
MCFG_CPU_PROGRAM_MAP(v25_mem)
- MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
- MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_PT_READ_CB(IOPORT("DSWA")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P0_READ_CB(IOPORT("DSWB")) MCFG_DEVCB_XOR(0xff)
+ MCFG_V25_PORT_P1_READ_CB(IOPORT("JMPR")) MCFG_DEVCB_XOR(0xff)
MCFG_V25_PORT_P2_WRITE_CB(NOOP) // bit 0 is FAULT according to kbash schematic
MCFG_MACHINE_START_OVERRIDE(toaplan2_state,toaplan2)
diff --git a/src/mame/drivers/toratora.cpp b/src/mame/drivers/toratora.cpp
index a3b1b92cedc..8bdea76b5ca 100644
--- a/src/mame/drivers/toratora.cpp
+++ b/src/mame/drivers/toratora.cpp
@@ -9,23 +9,23 @@ driver by Nicola Salmoria, qwijibo
deviations from schematics verified on set 2 pcb:
main pcb:
- - U33.3 connected to /IRQ line via inverter U67.9,
- providing timer IRQ for input polling.
+ - U33.3 connected to /IRQ line via inverter U67.9,
+ providing timer IRQ for input polling.
- - U43 removed from timer circuit, U52.9 wired directly to
- U32.5, increasing timer frequency to 250 Hz.
+ - U43 removed from timer circuit, U52.9 wired directly to
+ U32.5, increasing timer frequency to 250 Hz.
audio pcb:
- - U6.10 wired to U14.21, cut from R14/16
- - R16 wired to R1 in series, R1 cut from GND
- - R14 wired to GND instead of U6.10
+ - U6.10 wired to U14.21, cut from R14/16
+ - R16 wired to R1 in series, R1 cut from GND
+ - R14 wired to GND instead of U6.10
- - U5.10 wired to U15.21, cut from R13/15
- - R15 wired to R2 in series, R2 cut from GND
- - R13 wired to GND instead of U5.10
+ - U5.10 wired to U15.21, cut from R13/15
+ - R15 wired to R2 in series, R2 cut from GND
+ - R13 wired to GND instead of U5.10
- - EXT VCO DACs (U11, U12) and surrounding logic not placed
- - Numerous changes to SN74677 timing component R & C values
+ - EXT VCO DACs (U11, U12) and surrounding logic not placed
+ - Numerous changes to SN74677 timing component R & C values
TODO:
- The game reads some unmapped memory addresses, missing ROMs? There's an empty
diff --git a/src/mame/drivers/vegas.cpp b/src/mame/drivers/vegas.cpp
index aa3b43d4d25..71bfa6e06de 100644
--- a/src/mame/drivers/vegas.cpp
+++ b/src/mame/drivers/vegas.cpp
@@ -1057,7 +1057,7 @@ READ32_MEMBER( vegas_state::nile_r )
if (m_nile_regs[offset - 1] & 1)
{
//if (m_nile_regs[offset - 1] & 2)
- // logerror("Unexpected value: timer %d is prescaled\n", which);
+ // logerror("Unexpected value: timer %d is prescaled\n", which);
UINT32 scale = 1;
if (m_nile_regs[offset - 1] & 2) {
UINT32 scaleSrc = (m_nile_regs[offset - 1] >> 2) & 0x3;
@@ -1192,7 +1192,7 @@ WRITE32_MEMBER( vegas_state::nile_w )
{
UINT32 scale = m_nile_regs[offset - 1];
//if (m_nile_regs[offset] & 2)
- // logerror("Unexpected value: timer %d is prescaled\n", which);
+ // logerror("Unexpected value: timer %d is prescaled\n", which);
if (m_nile_regs[offset] & 2) {
UINT32 scaleSrc = (m_nile_regs[offset] >> 2) & 0x3;
scale *= m_nile_regs[NREG_T0CTRL + scaleSrc * 4];
@@ -1207,7 +1207,7 @@ WRITE32_MEMBER( vegas_state::nile_w )
else if ((olddata & 1) && !(m_nile_regs[offset] & 1))
{
//if (m_nile_regs[offset] & 2)
- // logerror("Unexpected value: timer %d is prescaled\n", which);
+ // logerror("Unexpected value: timer %d is prescaled\n", which);
UINT32 scale = 1;
if (m_nile_regs[offset] & 2) {
UINT32 scaleSrc = (m_nile_regs[offset] >> 2) & 0x3;
@@ -1230,7 +1230,7 @@ WRITE32_MEMBER( vegas_state::nile_w )
if (m_nile_regs[offset - 1] & 1)
{
//if (m_nile_regs[offset - 1] & 2)
- // logerror("Unexpected value: timer %d is prescaled\n", which);
+ // logerror("Unexpected value: timer %d is prescaled\n", which);
UINT32 scale = 1;
if (m_nile_regs[offset - 1] & 2) {
UINT32 scaleSrc = (m_nile_regs[offset - 1] >> 2) & 0x3;
diff --git a/src/mame/drivers/vsmilepro.cpp b/src/mame/drivers/vsmilepro.cpp
index a591f729882..a5110e4891f 100644
--- a/src/mame/drivers/vsmilepro.cpp
+++ b/src/mame/drivers/vsmilepro.cpp
@@ -6,13 +6,13 @@
30/05/2016
- Some information about the hardware can be found at
-
- http://www.x86-secret.com/dossier-64-VTech_V_Smile_Pro.html
+ Some information about the hardware can be found at
+ http://www.x86-secret.com/dossier-64-VTech_V_Smile_Pro.html
- In particular
- - It uses a LSI Zevio 1020 CPU + peripherals which comprises ARM926EJ-S CPU,
+
+ In particular
+ - It uses a LSI Zevio 1020 CPU + peripherals which comprises ARM926EJ-S CPU,
ZSP400 DPS, 3D graphics processor & 2D graphics processor
- The CD controller is a Sony CXD3059AR
diff --git a/src/mame/drivers/x1.cpp b/src/mame/drivers/x1.cpp
index cee20b3fbea..741f93a5c02 100644
--- a/src/mame/drivers/x1.cpp
+++ b/src/mame/drivers/x1.cpp
@@ -62,7 +62,7 @@
[0x01 to 0x0d] ROM header, i.e. title for the loader
[0x12 - 0x13] initial copy size
[0x14 - 0x15] destination address start address
- [0x16 to 0x17] start boot jump vector
+ [0x16 to 0x17] start boot jump vector
[0x1d to 0x1f] start boot data vector
- Gruppe: shows a random bitmap graphic then returns "program load error" ... it wants that the floppy has write protection enabled (!) (btanb)
- Maidum: you need to load BOTH disk with write protection disabled, otherwise it refuses to run. (btanb)
diff --git a/src/mame/includes/aerofgt.h b/src/mame/includes/aerofgt.h
index 75e9d14053e..85661959bdf 100644
--- a/src/mame/includes/aerofgt.h
+++ b/src/mame/includes/aerofgt.h
@@ -52,7 +52,7 @@ public:
optional_device<vsystem_spr2_device> m_spr_old; // every other (non-bootleg) uses this
optional_device<vsystem_spr2_device> m_spr_old2; // or a pair of them..
optional_device<generic_latch_8_device> m_soundlatch;
-
+
/* video-related */
diff --git a/src/mame/includes/atarigx2.h b/src/mame/includes/atarigx2.h
index 1cf61d8ecac..678b9c19b22 100644
--- a/src/mame/includes/atarigx2.h
+++ b/src/mame/includes/atarigx2.h
@@ -17,7 +17,7 @@ public:
atarigx2_state(const machine_config &mconfig, device_type type, const char *tag)
: atarigen_state(mconfig, type, tag),
m_jsa(*this, "jsa"),
- m_xga(*this, "xga"),
+ m_xga(*this, "xga"),
m_mo_command(*this, "mo_command"),
m_playfield_tilemap(*this, "playfield"),
m_alpha_tilemap(*this, "alpha"),
@@ -27,7 +27,7 @@ public:
UINT16 m_playfield_base;
required_device<atari_jsa_iiis_device> m_jsa;
- required_device<atari_xga_device> m_xga;
+ required_device<atari_xga_device> m_xga;
required_shared_ptr<UINT32> m_mo_command;
@@ -41,10 +41,10 @@ public:
UINT16 m_playfield_xscroll;
UINT16 m_playfield_yscroll;
- // LEGACY PROTECTION
+ // LEGACY PROTECTION
UINT16 m_last_write;
UINT16 m_last_write_offset;
- UINT32 m_protection_ram[0x1000];
+ UINT32 m_protection_ram[0x1000];
virtual void update_interrupts() override;
virtual void scanline_update(screen_device &screen, int scanline) override;
diff --git a/src/mame/includes/divebomb.h b/src/mame/includes/divebomb.h
index b254be2b5d0..c79a3774093 100644
--- a/src/mame/includes/divebomb.h
+++ b/src/mame/includes/divebomb.h
@@ -15,77 +15,77 @@
class divebomb_state : public driver_device
{
public:
- divebomb_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag),
- m_spritecpu(*this, "spritecpu"),
- m_fgcpu(*this, "fgcpu"),
- m_rozcpucpu(*this, "rozcpu"),
- m_bank1(*this, "bank1"),
- m_fgram(*this, "fgram"),
- m_spriteram(*this, "spriteram"),
- m_gfxdecode(*this, "gfxdecode"),
- m_palette(*this, "palette"),
- m_k051316_1(*this, "k051316_1"),
- m_k051316_2(*this, "k051316_2")
- { }
-
- required_device<cpu_device> m_spritecpu;
- required_device<cpu_device> m_fgcpu;
- required_device<cpu_device> m_rozcpucpu;
- required_memory_bank m_bank1;
- required_shared_ptr<UINT8> m_fgram;
- required_shared_ptr<UINT8> m_spriteram;
- required_device<gfxdecode_device> m_gfxdecode;
- required_device<palette_device> m_palette;
- required_device<k051316_device> m_k051316_1;
- required_device<k051316_device> m_k051316_2;
-
- tilemap_t *m_fg_tilemap;
- UINT8 to_spritecpu;
- UINT8 to_rozcpu;
- UINT8 from_sprite;
- UINT8 from_roz;
- bool has_fromsprite;
- bool has_fromroz;
+ divebomb_state(const machine_config &mconfig, device_type type, const char *tag)
+ : driver_device(mconfig, type, tag),
+ m_spritecpu(*this, "spritecpu"),
+ m_fgcpu(*this, "fgcpu"),
+ m_rozcpucpu(*this, "rozcpu"),
+ m_bank1(*this, "bank1"),
+ m_fgram(*this, "fgram"),
+ m_spriteram(*this, "spriteram"),
+ m_gfxdecode(*this, "gfxdecode"),
+ m_palette(*this, "palette"),
+ m_k051316_1(*this, "k051316_1"),
+ m_k051316_2(*this, "k051316_2")
+ { }
- UINT8 roz_pal;
- bool roz1_enable;
- bool roz2_enable;
- bool roz1_wrap;
- bool roz2_wrap;
-
- DECLARE_MACHINE_RESET(divebomb);
- DECLARE_MACHINE_START(divebomb);
- DECLARE_VIDEO_START(divebomb);
- DECLARE_PALETTE_INIT(divebomb);
+ required_device<cpu_device> m_spritecpu;
+ required_device<cpu_device> m_fgcpu;
+ required_device<cpu_device> m_rozcpucpu;
+ required_memory_bank m_bank1;
+ required_shared_ptr<UINT8> m_fgram;
+ required_shared_ptr<UINT8> m_spriteram;
+ required_device<gfxdecode_device> m_gfxdecode;
+ required_device<palette_device> m_palette;
+ required_device<k051316_device> m_k051316_1;
+ required_device<k051316_device> m_k051316_2;
- void update_irqs();
- void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
- void decode_proms(const UINT8* rgn, int size, int index, bool inv);
- UINT32 screen_update_divebomb(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
-
- K051316_CB_MEMBER(zoom_callback_1);
- K051316_CB_MEMBER(zoom_callback_2);
-
- TILE_GET_INFO_MEMBER(get_fg_tile_info);
+ tilemap_t *m_fg_tilemap;
+ UINT8 to_spritecpu;
+ UINT8 to_rozcpu;
+ UINT8 from_sprite;
+ UINT8 from_roz;
+ bool has_fromsprite;
+ bool has_fromroz;
- DECLARE_READ8_MEMBER(fgcpu_roz_comm_r);
- DECLARE_WRITE8_MEMBER(fgcpu_roz_comm_w);
- DECLARE_READ8_MEMBER(fgcpu_spr_comm_r);
- DECLARE_WRITE8_MEMBER(fgcpu_spr_comm_w);
- DECLARE_READ8_MEMBER(fgcpu_comm_flags_r);
- DECLARE_WRITE8_MEMBER(fgram_w);
-
- DECLARE_WRITE8_MEMBER(spritecpu_port00_w);
- DECLARE_READ8_MEMBER(spritecpu_comm_r);
- DECLARE_WRITE8_MEMBER(spritecpu_comm_w);
-
- DECLARE_WRITE8_MEMBER(rozcpu_bank_w);
- DECLARE_WRITE8_MEMBER(rozcpu_wrap1_enable_w);
- DECLARE_WRITE8_MEMBER(rozcpu_enable1_w);
- DECLARE_WRITE8_MEMBER(rozcpu_enable2_w);
- DECLARE_WRITE8_MEMBER(rozcpu_wrap2_enable_w);
- DECLARE_READ8_MEMBER(rozcpu_comm_r);
- DECLARE_WRITE8_MEMBER(rozcpu_comm_w);
- DECLARE_WRITE8_MEMBER(rozcpu_pal_w);
+ UINT8 roz_pal;
+ bool roz1_enable;
+ bool roz2_enable;
+ bool roz1_wrap;
+ bool roz2_wrap;
+
+ DECLARE_MACHINE_RESET(divebomb);
+ DECLARE_MACHINE_START(divebomb);
+ DECLARE_VIDEO_START(divebomb);
+ DECLARE_PALETTE_INIT(divebomb);
+
+ void update_irqs();
+ void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
+ void decode_proms(const UINT8* rgn, int size, int index, bool inv);
+ UINT32 screen_update_divebomb(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+
+ K051316_CB_MEMBER(zoom_callback_1);
+ K051316_CB_MEMBER(zoom_callback_2);
+
+ TILE_GET_INFO_MEMBER(get_fg_tile_info);
+
+ DECLARE_READ8_MEMBER(fgcpu_roz_comm_r);
+ DECLARE_WRITE8_MEMBER(fgcpu_roz_comm_w);
+ DECLARE_READ8_MEMBER(fgcpu_spr_comm_r);
+ DECLARE_WRITE8_MEMBER(fgcpu_spr_comm_w);
+ DECLARE_READ8_MEMBER(fgcpu_comm_flags_r);
+ DECLARE_WRITE8_MEMBER(fgram_w);
+
+ DECLARE_WRITE8_MEMBER(spritecpu_port00_w);
+ DECLARE_READ8_MEMBER(spritecpu_comm_r);
+ DECLARE_WRITE8_MEMBER(spritecpu_comm_w);
+
+ DECLARE_WRITE8_MEMBER(rozcpu_bank_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_wrap1_enable_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_enable1_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_enable2_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_wrap2_enable_w);
+ DECLARE_READ8_MEMBER(rozcpu_comm_r);
+ DECLARE_WRITE8_MEMBER(rozcpu_comm_w);
+ DECLARE_WRITE8_MEMBER(rozcpu_pal_w);
};
diff --git a/src/mame/includes/gameplan.h b/src/mame/includes/gameplan.h
index f668b23d338..b3968301d1e 100644
--- a/src/mame/includes/gameplan.h
+++ b/src/mame/includes/gameplan.h
@@ -70,7 +70,7 @@ public:
required_device<screen_device> m_screen;
optional_device<generic_latch_8_device> m_soundlatch;
-
+
DECLARE_WRITE8_MEMBER(io_select_w);
DECLARE_READ8_MEMBER(io_port_r);
DECLARE_WRITE_LINE_MEMBER(coin_w);
diff --git a/src/mame/includes/megasys1.h b/src/mame/includes/megasys1.h
index dcd8a6f5269..1e52cfc056c 100644
--- a/src/mame/includes/megasys1.h
+++ b/src/mame/includes/megasys1.h
@@ -143,7 +143,7 @@ public:
DECLARE_DRIVER_INIT(avspirit);
DECLARE_DRIVER_INIT(monkelf);
DECLARE_DRIVER_INIT(edf);
- DECLARE_DRIVER_INIT(edfp);
+ DECLARE_DRIVER_INIT(edfp);
DECLARE_DRIVER_INIT(bigstrik);
DECLARE_DRIVER_INIT(rodland);
DECLARE_DRIVER_INIT(edfbl);
diff --git a/src/mame/includes/namconb1.h b/src/mame/includes/namconb1.h
index e3f065361dc..9aeb6ddc251 100644
--- a/src/mame/includes/namconb1.h
+++ b/src/mame/includes/namconb1.h
@@ -95,7 +95,7 @@ public:
UINT32 screen_update_namconb2(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
TIMER_DEVICE_CALLBACK_MEMBER(scantimer);
-
+
int NB1objcode2tile(int code);
int NB2objcode2tile(int code);
};
diff --git a/src/mame/includes/nmk16.h b/src/mame/includes/nmk16.h
index 5ec3b51de31..91fd9563305 100644
--- a/src/mame/includes/nmk16.h
+++ b/src/mame/includes/nmk16.h
@@ -56,7 +56,7 @@ public:
optional_shared_ptr<UINT16> m_nmk_bgvideoram3;
optional_shared_ptr<UINT16> m_afega_scroll_0;
optional_shared_ptr<UINT16> m_afega_scroll_1;
-
+
int m_sprdma_base;
int mask[4*2];
diff --git a/src/mame/includes/plygonet.h b/src/mame/includes/plygonet.h
index 5b71fa27476..020cbe7621b 100644
--- a/src/mame/includes/plygonet.h
+++ b/src/mame/includes/plygonet.h
@@ -43,7 +43,7 @@ public:
required_device<generic_latch_8_device> m_soundlatch;
required_device<generic_latch_8_device> m_soundlatch2;
required_device<generic_latch_8_device> m_soundlatch3;
-
+
/* 68k-side shared ram */
required_shared_ptr<UINT32> m_shared_ram;
diff --git a/src/mame/includes/sg1000.h b/src/mame/includes/sg1000.h
index 6e496fed31b..efa24e6c683 100644
--- a/src/mame/includes/sg1000.h
+++ b/src/mame/includes/sg1000.h
@@ -77,7 +77,7 @@ public:
: sg1000_state(mconfig, type, tag)
{ }
- virtual void machine_start() override;
+ virtual void machine_start() override;
};
class sf7000_state : public sc3000_state
diff --git a/src/mame/includes/tsamurai.h b/src/mame/includes/tsamurai.h
index cd371126147..5d29d9e4d27 100644
--- a/src/mame/includes/tsamurai.h
+++ b/src/mame/includes/tsamurai.h
@@ -26,7 +26,7 @@ public:
optional_device<cpu_device> m_audio3;
required_device<gfxdecode_device> m_gfxdecode;
required_device<palette_device> m_palette;
- optional_device<generic_latch_8_device> m_soundlatch; // vsgongf only
+ optional_device<generic_latch_8_device> m_soundlatch; // vsgongf only
required_shared_ptr<UINT8> m_videoram;
optional_shared_ptr<UINT8> m_colorram;
diff --git a/src/mame/layout/patinho.lay b/src/mame/layout/patinho.lay
index 7c6296034bf..768b8283ac3 100644
--- a/src/mame/layout/patinho.lay
+++ b/src/mame/layout/patinho.lay
@@ -26,117 +26,117 @@
</disk>
</element>
- <element name="rectangle">
- <rect>
- <color red="0.3" green="0.9" blue="0.6" />
- </rect>
- </element>
-
- <element name="str_flags_t">
- <text string="TRANSBORDO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_flags_v">
- <text string="VAI - UM">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_ula">
- <text string="UNIDADE ARITMETICA E LÓGICA" >
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_rc">
- <text string="DADOS DO PAINEL">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_pc">
- <text string="ENDEREÇO DE INSTRUÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_mem_addr">
- <text string="ENDEREÇO DA MEMÓRIA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_acc">
- <text string="ACUMULADOR">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_opcode">
- <text string="CÓDIGO DE INSTRUÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_mem_data">
- <text string="DADOS DA MEMÓRIA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_mem">
- <text string="MEMÓRIA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
-
- <element name="str_NORMAL">
- <text string="NORMAL">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
-
- <element name="str_CICLOUNICO">
- <text string="CICLO
-ÚNICO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_INSTRUCAOUNICA">
- <text string="INSTRUÇÃO
-ÚNICA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_ENDERECAMENTO">
- <text string="ENDEREÇAMENTO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_ARMAZENAMENTO">
- <text string="ARMAZENAMENTO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_EXPOSICAO">
- <text string="EXPOSIÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
-
-
- <element name="str_ESPERA">
- <text string="ESPERA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_INTERRUPCAO">
- <text string="INTERRUPÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_PARTIDA">
- <text string="PARTIDA">
- <color red="0" green="0" blue="0" /></text>
- </element>
-
- <element name="str_PREPARACAO">
- <text string="PREPARAÇÃO">
- <color red="0" green="0" blue="0" /></text>
- </element>
+ <element name="rectangle">
+ <rect>
+ <color red="0.3" green="0.9" blue="0.6" />
+ </rect>
+ </element>
+
+ <element name="str_flags_t">
+ <text string="TRANSBORDO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_flags_v">
+ <text string="VAI - UM">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_ula">
+ <text string="UNIDADE ARITMETICA E LOGICA" >
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_rc">
+ <text string="DADOS DO PAINEL">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_pc">
+ <text string="ENDERECO DE INSTRUCAO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_mem_addr">
+ <text string="ENDERECO DA MEMORIA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_acc">
+ <text string="ACUMULADOR">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_opcode">
+ <text string="CODIGO DE INSTRUCAO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_mem_data">
+ <text string="DADOS DA MEMORIA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_mem">
+ <text string="MEMORIA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+
+ <element name="str_NORMAL">
+ <text string="NORMAL">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+
+ <element name="str_CICLOUNICO">
+ <text string="CICLO
+UNICO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_INSTRUCAOUNICA">
+ <text string="INSTRUCAO
+UNICA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_ENDERECAMENTO">
+ <text string="ENDERECAMENTO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_ARMAZENAMENTO">
+ <text string="ARMAZENAMENTO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_EXPOSICAO">
+ <text string="EXPOSICAO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+
+
+ <element name="str_ESPERA">
+ <text string="ESPERA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_INTERRUPCAO">
+ <text string="INTERRUP????O">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_PARTIDA">
+ <text string="PARTIDA">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
+
+ <element name="str_PREPARACAO">
+ <text string="PREPARACAO">
+ <color red="0" green="0" blue="0" /></text>
+ </element>
<!-- define background -->
@@ -148,7 +148,7 @@
<!-- define lamps -->
<bezel element="rectangle">
- <bounds x="150" y="100" width="625" height="450" />
+ <bounds x="150" y="100" width="625" height="450" />
</bezel>
<bezel name="mem_data7" element="bit_lamp" inputtag="mem_data" inputmask="0x080">
@@ -184,7 +184,7 @@
</bezel>
<bezel element="str_mem_data">
- <bounds x="200" y="470" width="200" height="20" />
+ <bounds x="200" y="470" width="200" height="20" />
</bezel>
<bezel name="opcode7" element="bit_lamp" inputtag="opcode" inputmask="0x080">
@@ -220,7 +220,7 @@
</bezel>
<bezel element="str_opcode">
- <bounds x="200" y="370" width="200" height="20" />
+ <bounds x="200" y="370" width="200" height="20" />
</bezel>
<bezel name="acc7" element="bit_lamp" inputtag="ACC" inputmask="0x080">
@@ -256,7 +256,7 @@
</bezel>
<bezel element="str_acc">
- <bounds x="200" y="270" width="200" height="20" />
+ <bounds x="200" y="270" width="200" height="20" />
</bezel>
<bezel name="rc11" element="bit_lamp" inputtag="RC" inputmask="0x800">
@@ -308,7 +308,7 @@
</bezel>
<bezel element="str_rc">
- <bounds x="450" y="520" width="299" height="20" />
+ <bounds x="450" y="520" width="299" height="20" />
</bezel>
<bezel name="flags1" element="bit_lamp" inputtag="FLAGS" inputmask="0x002">
@@ -320,11 +320,11 @@
</bezel>
<bezel element="str_flags_t">
- <bounds x="400" y="350" width="199" height="20" />
+ <bounds x="400" y="350" width="199" height="20" />
</bezel>
<bezel element="str_flags_v">
- <bounds x="650" y="350" width="99" height="20" />
+ <bounds x="650" y="350" width="99" height="20" />
</bezel>
<bezel name="pc11" element="bit_lamp" inputtag="PC" inputmask="0x800">
@@ -376,7 +376,7 @@
</bezel>
<bezel element="str_pc">
- <bounds x="450" y="270" width="299" height="20" />
+ <bounds x="450" y="270" width="299" height="20" />
</bezel>
<bezel name="mem_addr11" element="bit_lamp" inputtag="mem_addr" inputmask="0x800">
@@ -428,7 +428,7 @@
</bezel>
<bezel element="str_mem_addr">
- <bounds x="450" y="170" width="299" height="20" />
+ <bounds x="450" y="170" width="299" height="20" />
</bezel>
<bezel name="NORMAL" element="button" inputtag="BUTTONS" inputmask="0x001">
@@ -436,7 +436,7 @@
</bezel>
<bezel element="str_NORMAL">
- <bounds x="12" y="610" width="150" height="20" />
+ <bounds x="12" y="610" width="150" height="20" />
</bezel>
<bezel name="CICLOUNICO" element="button" inputtag="BUTTONS" inputmask="0x002">
@@ -444,7 +444,7 @@
</bezel>
<bezel element="str_CICLOUNICO">
- <bounds x="162" y="610" width="150" height="20" />
+ <bounds x="162" y="610" width="150" height="20" />
</bezel>
<bezel name="INSTRUCAOUNICA" element="button" inputtag="BUTTONS" inputmask="0x004">
@@ -452,7 +452,7 @@
</bezel>
<bezel element="str_INSTRUCAOUNICA">
- <bounds x="312" y="610" width="150" height="20" />
+ <bounds x="312" y="610" width="150" height="20" />
</bezel>
<bezel name="ENDERECAMENTO" element="button" inputtag="BUTTONS" inputmask="0x008">
@@ -460,7 +460,7 @@
</bezel>
<bezel element="str_ENDERECAMENTO">
- <bounds x="462" y="610" width="150" height="20" />
+ <bounds x="462" y="610" width="150" height="20" />
</bezel>
<bezel name="ARMAZENAMENTO" element="button" inputtag="BUTTONS" inputmask="0x010">
@@ -468,7 +468,7 @@
</bezel>
<bezel element="str_ARMAZENAMENTO">
- <bounds x="612" y="610" width="150" height="20" />
+ <bounds x="612" y="610" width="150" height="20" />
</bezel>
<bezel name="EXPOSICAO" element="button" inputtag="BUTTONS" inputmask="0x020">
@@ -476,7 +476,7 @@
</bezel>
<bezel element="str_EXPOSICAO">
- <bounds x="762" y="610" width="150" height="20" />
+ <bounds x="762" y="610" width="150" height="20" />
</bezel>
<bezel name="ESPERA" element="button" inputtag="BUTTONS" inputmask="0x040">
@@ -484,7 +484,7 @@
</bezel>
<bezel element="str_ESPERA">
- <bounds x="308" y="710" width="166" height="20" />
+ <bounds x="308" y="710" width="166" height="20" />
</bezel>
<bezel name="INTERRUPCAO" element="button" inputtag="BUTTONS" inputmask="0x080">
@@ -492,7 +492,7 @@
</bezel>
<bezel element="str_INTERRUPCAO">
- <bounds x="474" y="710" width="166" height="20" />
+ <bounds x="474" y="710" width="166" height="20" />
</bezel>
<bezel name="PARTIDA" element="button" inputtag="BUTTONS" inputmask="0x100">
@@ -500,7 +500,7 @@
</bezel>
<bezel element="str_PARTIDA">
- <bounds x="641" y="710" width="166" height="20" />
+ <bounds x="641" y="710" width="166" height="20" />
</bezel>
<bezel name="PREPARACAO" element="button" inputtag="BUTTONS" inputmask="0x200">
@@ -508,7 +508,7 @@
</bezel>
<bezel element="str_PREPARACAO">
- <bounds x="808" y="710" width="166" height="20" />
+ <bounds x="808" y="710" width="166" height="20" />
</bezel>
</view>
diff --git a/src/mame/machine/atarixga.h b/src/mame/machine/atarixga.h
index 710aedb22c2..8d6980a3ac3 100644
--- a/src/mame/machine/atarixga.h
+++ b/src/mame/machine/atarixga.h
@@ -3,7 +3,7 @@
/*************************************************************************
atarixga.h
-
+
Atari XGA encryption FPGA
*************************************************************************/
@@ -16,38 +16,38 @@ extern const device_type ATARI_XGA;
class atari_xga_device : public device_t
{
public:
- // construction/destruction
- atari_xga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
- DECLARE_WRITE32_MEMBER(write);
- DECLARE_READ32_MEMBER(read);
-
+ // construction/destruction
+ atari_xga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+ DECLARE_WRITE32_MEMBER(write);
+ DECLARE_READ32_MEMBER(read);
+
protected:
- virtual void device_start() override;
- virtual void device_reset() override;
-
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
private:
- static const size_t RAM_WORDS = 2048;
-
- enum fpga_mode
- {
- FPGA_RESET,
- FPGA_SETKEY,
- FPGA_DECIPHER
- };
-
- UINT16 powers2(UINT8 k, UINT16 x);
- UINT16 lfsr2(UINT16 x);
- UINT16 lfsr1(UINT16 x);
- UINT16 parity(UINT16 x);
- size_t popcount(UINT16 x);
- UINT16 ctz(UINT16 x);
- UINT16 decipher(UINT8 k, UINT16 c);
-
- fpga_mode m_mode;
- UINT16 m_address; // last written address
- UINT16 m_ciphertext; // last written ciphertext
- std::unique_ptr<UINT16[]> m_ram; // CY7C185-45PC, only 16-Kbit used
+ static const size_t RAM_WORDS = 2048;
+
+ enum fpga_mode
+ {
+ FPGA_RESET,
+ FPGA_SETKEY,
+ FPGA_DECIPHER
+ };
+
+ UINT16 powers2(UINT8 k, UINT16 x);
+ UINT16 lfsr2(UINT16 x);
+ UINT16 lfsr1(UINT16 x);
+ UINT16 parity(UINT16 x);
+ size_t popcount(UINT16 x);
+ UINT16 ctz(UINT16 x);
+ UINT16 decipher(UINT8 k, UINT16 c);
+
+ fpga_mode m_mode;
+ UINT16 m_address; // last written address
+ UINT16 m_ciphertext; // last written ciphertext
+ std::unique_ptr<UINT16[]> m_ram; // CY7C185-45PC, only 16-Kbit used
};
diff --git a/src/mame/machine/dccons.cpp b/src/mame/machine/dccons.cpp
index 776e6d8ead2..0a0792c14d6 100644
--- a/src/mame/machine/dccons.cpp
+++ b/src/mame/machine/dccons.cpp
@@ -126,12 +126,12 @@ READ32_MEMBER(dc_cons_state::dc_mess_g1_ctrl_r )
case SB_GDLEND:
//machine().debug_break();
return atapi_xferlen; // TODO: check me
- case SB_SECUR_EADR: // always read 0xFF on hardware
+ case SB_SECUR_EADR: // always read 0xFF on hardware
return 0x000000ff;
- case SB_SECUR_STATE: // state of BIOS checksum security system (R/O):
+ case SB_SECUR_STATE: // state of BIOS checksum security system (R/O):
// 3 - check passed OK, G1 ATA (5F70xx) registers area accessible
- // 2 - check failed, G1 ATA area blocked (read FFFFFFFFh)
- // 0 - check in progress, BIOS data summed, G1 ATA area blocked (read FFFFFFFFh)
+ // 2 - check failed, G1 ATA area blocked (read FFFFFFFFh)
+ // 0 - check in progress, BIOS data summed, G1 ATA area blocked (read FFFFFFFFh)
return 3;
default:
printf("G1CTRL: Unmapped read %08x\n", 0x5f7400+offset*4);
@@ -185,10 +185,10 @@ WRITE32_MEMBER(dc_cons_state::dc_mess_g1_ctrl_w )
if values doesn't match - security system switch to state 2 (check fail):
- G1 ATA locked
- - can be switched to state 0 by write to SB_SECUR_EADR register, however passing valid data block through security system set it back to state 2
+ - can be switched to state 0 by write to SB_SECUR_EADR register, however passing valid data block through security system set it back to state 2
- the only exit from this state - power off/on or reset;
- current state can be read from SB_SECUR_STATE register
+ current state can be read from SB_SECUR_STATE register
actual checksum algorithm is unknown, but its supposed to be simple and weak,
known few modded BIOSes which succesfully passes this CRC check, because of good luck
diff --git a/src/mame/machine/dec_lk201.cpp b/src/mame/machine/dec_lk201.cpp
index 353856f928c..0ba3d6a0fdc 100644
--- a/src/mame/machine/dec_lk201.cpp
+++ b/src/mame/machine/dec_lk201.cpp
@@ -3,7 +3,7 @@
/*
DEC LK-201 keyboard
Emulation by R. Belmont & M. Burke
-with contributions by Cracyc and Karl-Ludwig Deisenhofer (2016)
+with contributions by Cracyc and Karl-Ludwig Deisenhofer (2016)
This is the later "cost-reduced" 6805 version with green LEDs; there's also an 8048 version.
The LK-201 mechanical elements are described in US Patent 4,467,150
@@ -181,10 +181,10 @@ const device_type LK201 = &device_creator<lk201_device>;
ROM_START( lk201 )
ROM_REGION(0x2000, LK201_CPU_TAG, 0)
-// 23-001s9-00.bin is for the newer LK201 version (green LEDs, Motorola 6805)
+// 23-001s9-00.bin is for the newer LK201 version (green LEDs, Motorola 6805)
ROM_LOAD( "23-001s9-00.bin", 0x0000, 0x2000, CRC(be293c51) SHA1(a11ae004d2d6055d7279da3560c3e56610a19fdb) )
-// 23-004M1 or 23-004M2 are in the older LK201 keyboard with red LEDs (8051)
+// 23-004M1 or 23-004M2 are in the older LK201 keyboard with red LEDs (8051)
ROM_END
@@ -541,10 +541,10 @@ void lk201_device::device_timer(emu_timer &timer, device_timer_id id, int param,
{
switch (id)
{
- case 1:
- m_timer.tsr |= TSR_OCFL;
+ case 1:
+ m_timer.tsr |= TSR_OCFL;
- if ((m_timer.tcr & TCR_OCIE) && (m_timer.tsr & TSR_OCFL))
+ if ((m_timer.tcr & TCR_OCIE) && (m_timer.tsr & TSR_OCFL))
m_maincpu->set_input_line(M68HC05EG_INT_TIMER, ASSERT_LINE);
break;
@@ -567,7 +567,7 @@ void lk201_device::rcv_complete()
int data = get_received_char();
m_kbd_state = data;
-// printf("\nlk201 got %02x\n", m_kbd_state);
+// printf("\nlk201 got %02x\n", m_kbd_state);
}
void lk201_device::tra_complete()
@@ -602,7 +602,7 @@ READ8_MEMBER( lk201_device::timer_r )
switch (offset)
{
case 8: // ACRH (high value is stored and reused when reading low)
- count = (m_maincpu->total_cycles() / 4) & 0x0000ffff;
+ count = (m_maincpu->total_cycles() / 4) & 0x0000ffff;
ret = count >> 8;
break;
case 9: // ACRL
@@ -637,7 +637,7 @@ WRITE8_MEMBER( lk201_device::timer_w )
count |= m_timer.ocrl;
m_timer.ocrh = count >> 8;
- m_timer.tsr = save_tsr; // restore flags
+ m_timer.tsr = save_tsr; // restore flags
break;
}
}
@@ -675,7 +675,7 @@ WRITE8_MEMBER( lk201_device::ports_w )
UINT8 olddata = ports[offset];
ports[offset] = data; // "port writes are independent of DDRC"
send_port(space, offset, olddata & ddrs[offset]);
-// printf("\nPORT %c write %02x (OLD = %02x) (DDR = %02x) (PC=%x)\n", 'A' + offset, data, olddata, ddrs[offset], m_maincpu->pc());
+// printf("\nPORT %c write %02x (OLD = %02x) (DDR = %02x) (PC=%x)\n", 'A' + offset, data, olddata, ddrs[offset], m_maincpu->pc());
}
void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 olddata)
@@ -719,8 +719,8 @@ void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 olddata)
// Check for LED update strobe
if (((portc & 0x80) == 0) && (olddata & 0x80))
{
- if(ddrs[2] != 0x00)
- { // Lower nibble contains the LED values (1 = on, 0 = off)
+ if(ddrs[2] != 0x00)
+ { // Lower nibble contains the LED values (1 = on, 0 = off)
machine().output().set_value("led_wait" , (led_data & 0x1) == 1);
machine().output().set_value("led_compose", (led_data & 0x2) == 2);
machine().output().set_value("led_lock" , (led_data & 0x4) == 4);
@@ -731,11 +731,11 @@ void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 olddata)
m_speaker->set_state(1);
// Beeps < 20 ms are clipped. A key click on a LK201 lasts 2 ms...
if(m_kbd_state == LK_CMD_BELL)
- m_beeper->adjust(attotime::from_msec(125));
- else
+ m_beeper->adjust(attotime::from_msec(125));
+ else
m_beeper->adjust(attotime::from_msec(25)); // see note
}
- // Upper 4 bits of LED_DATA contain encoded volume info
+ // Upper 4 bits of LED_DATA contain encoded volume info
switch (led_data & 0xf0)
{
case 0xf0: // 8 - (see TABLE 4 in 68HC05xx ROM)
@@ -765,10 +765,10 @@ void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 olddata)
default:
;
} // switch (volume)
-
+
} // if (update_strobe)
-
- } // outer switch
+
+ } // outer switch
}
READ8_MEMBER( lk201_device::sci_r )
diff --git a/src/mame/machine/dec_lk201.h b/src/mame/machine/dec_lk201.h
index 1df36577b7b..3185a0a139f 100644
--- a/src/mame/machine/dec_lk201.h
+++ b/src/mame/machine/dec_lk201.h
@@ -24,12 +24,12 @@
#define LK_CMD_ENB_BELL 0x23 /* enable the bell - 1st param: volume */
#define LK_CMD_BELL 0xa7 /* emit a bell - 1st param: volume */
-// TCR - Timer Compare Register
+// TCR - Timer Compare Register
#define TCR_OCIE 0x40 // Bit 6 (output compare IRQ enable)
-#define TCR_OLVL 0x01 // Bit 1 (output level)
+#define TCR_OLVL 0x01 // Bit 1 (output level)
-// TSR - Timer Status Register
-#define TSR_OCFL 0x40 // TSR (68HC05 output compare flag)
+// TSR - Timer Status Register
+#define TSR_OCFL 0x40 // TSR (68HC05 output compare flag)
//**************************************************************************
// INTERFACE CONFIGURATION MACROS
diff --git a/src/mame/machine/fd1094.cpp b/src/mame/machine/fd1094.cpp
index ed358b97cc2..4a37174d306 100644
--- a/src/mame/machine/fd1094.cpp
+++ b/src/mame/machine/fd1094.cpp
@@ -816,7 +816,7 @@ UINT16 fd1094_device::decrypt_one(offs_t address, UINT16 val, const UINT8 *main_
val = BITSWAP16(val, 15, 9,10,13, 3,12, 0,14, 6, 5, 2,11, 8, 1, 4, 7);
if (!global_xor1) if (~val & 0x0800) val ^= 0x3002; // 1,12,13
- if (true) if (~val & 0x0020) val ^= 0x0044; // 2,6
+ if (true) if (~val & 0x0020) val ^= 0x0044; // 2,6
if (!key_1b) if (~val & 0x0400) val ^= 0x0890; // 4,7,11
if (!global_swap2) if (!key_0c) val ^= 0x0308; // 3,8,9
val ^= 0x6561;
diff --git a/src/mame/machine/kaneko_toybox.cpp b/src/mame/machine/kaneko_toybox.cpp
index ee863a303d7..0815db16863 100644
--- a/src/mame/machine/kaneko_toybox.cpp
+++ b/src/mame/machine/kaneko_toybox.cpp
@@ -192,7 +192,7 @@ void kaneko_toybox_device::mcu_run()
case 0x42: // Write to NVRAM
{
- eeprom_serial_93cxx_device *eeprom = machine().device<eeprom_serial_93cxx_device>(":eeprom");
+ eeprom_serial_93cxx_device *eeprom = machine().device<eeprom_serial_93cxx_device>(":eeprom");
UINT8* nvdat = (UINT8*)&m_mcuram[mcu_offset];
for (int i=0;i<0x80;i++)
{
diff --git a/src/mame/machine/m2comm.cpp b/src/mame/machine/m2comm.cpp
index 4b3f4dbe3c3..92756c75806 100644
--- a/src/mame/machine/m2comm.cpp
+++ b/src/mame/machine/m2comm.cpp
@@ -328,7 +328,7 @@ void m2comm_device::comm_init()
{
// TODO - check EPR-16726 on Daytona USA and Sega Rally Championship
// EPR-18643(A) - these are accessed by VirtuaON and Sega Touring Car Championship
-
+
// frameSize - 0xe00
m_shared[0x12] = 0x00;
m_shared[0x13] = 0x0e;
@@ -343,10 +343,10 @@ void m2comm_device::comm_tick()
if (m_linkenable == 0x01)
{
m_zfg ^= 1;
-
+
int frameSize = m_shared[0x13] << 8 | m_shared[0x12];
int frameOffset = m_shared[0x15] << 8 | m_shared[0x14];
-
+
int dataSize = frameSize + 1;
int togo = 0;
int recv = 0;
diff --git a/src/mame/machine/namcoic.cpp b/src/mame/machine/namcoic.cpp
index dc8c34c8645..4e49a755686 100644
--- a/src/mame/machine/namcoic.cpp
+++ b/src/mame/machine/namcoic.cpp
@@ -79,7 +79,7 @@ void namcos2_shared_state::namco_tilemap_init( int gfxbank, void *maskBaseAddr,
mTilemapInfo.tmap[i]->set_scrolldx( -dx, 288+dx );
mTilemapInfo.tmap[i]->set_scrolldy( -24, 224+24 );
}
-
+
save_item(NAME(mTilemapInfo.control));
save_pointer(NAME(mTilemapInfo.videoram.get()), 0x10000);
} /* namco_tilemap_init */
@@ -822,7 +822,7 @@ void namcos2_shared_state::c355_obj_init(int gfxbank, int pal_xor, c355_obj_code
memset(m_c355_obj_ram, 0, sizeof(m_c355_obj_ram)); // needed for Nebulas Ray
memset(m_c355_obj_position, 0, sizeof(m_c355_obj_position));
-
+
save_item(NAME(m_c355_obj_position));
save_item(NAME(m_c355_obj_ram));
save_item(NAME(m_player_mux));
diff --git a/src/mame/machine/pcecommn.h b/src/mame/machine/pcecommn.h
index 732b044768f..c4318f80230 100644
--- a/src/mame/machine/pcecommn.h
+++ b/src/mame/machine/pcecommn.h
@@ -33,7 +33,7 @@ public:
virtual UINT8 joy_read();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
required_device<huc6260_device> m_huc6260;
-
+
private:
UINT8 m_io_port_options; /*driver-specific options for the PCE*/
int m_joystick_port_select; /* internal index of joystick ports */
diff --git a/src/mame/machine/seibucop/seibucop.cpp b/src/mame/machine/seibucop/seibucop.cpp
index 1490ef5cd81..06f093a0d0d 100644
--- a/src/mame/machine/seibucop/seibucop.cpp
+++ b/src/mame/machine/seibucop/seibucop.cpp
@@ -2,63 +2,63 @@
// copyright-holders:Olivier Galibert, Angelo Salese, David Haywood, Tomasz Slanina
/***************************************************************************
- Seibu Cop (Co-Processor) device emulation
- a.k.a. known as Toshiba gate array TC25SC rebadged as:
- SEI300 - Legionnaire PCB
- [...]
- There's also a ROM labeled COP-Dx, which is probably used for some in-game maths:
- COP-D1 - Seibu Cup Soccer PCBs
- COP-D2 - legionna.cpp and raiden2.cpp, latter might use another component too
- COP-D3 - New Zero Team / Raiden 2 V33 HWs
- Raiden 2 first boss arms is known to behave strangely without this ROM on a real PCB
-
- TODO:
- - improve documentation, ffs!
- - split into files, still needed:
- - BCD;
- - collision detection;
- - command parser -> to cmd file;
- - sd gundam sprite dma -> to dma file;
- - convert to internal memory map, remove trampolines along the way.
- - DMA mode needs to be cleaned up;
- - improve class OO public/protected/private;
- - nuke legacy command implementations;
- - assert for something that needs actual playtesting is bad.
- - add better debug facilities in a new sub-class, including but not limited to:
- - disable collision detection;
- - printing facilities;
- - debugger break on pre-setted commands;
- - ...
-
- per-game TODO:
- Legionnaire
- - (fixed) player walks on spot on stage clear;
- - several if not all enemies definitely wants some sort of "axis aligned bounding box" in order to stop from going out of range
- (when i.e. first boss goes to bottom of the screen and become unreachable)
- - (btanb) Throw is made by quickly double jumping (!)
- Heated Barrel
- - gives random value to hi-score if you continue (only the first time, not a bug?);
- - (fixed?) throws random address exceptions at level 3 and above, a RAM address arrives corrupt in the snippet at 0x136a;
- - (fixed?) some corrupt sprites, probably a non-fatal version of the one above;
- - stage 2 boss attacks only in vertical (regressed with the 130e / 3b30 / 42c2 command merge);
- - (fixed) level 3+ boss movements looks wrong;
- - stage 3 "homing" missiles doesn't seem to like our 6200 hookup here, except it's NOT 6200!?
- - barrels seen in later levels seems to fail an axis aligned bounding box, not unlike Legionnaire.
- SD Gundam
- - stage 3 mid-boss still has the sprite garbage bug;
- - stage 4: has sprite stuck on bottom-left of screen;
- - palette dims too much on attract / continue screen.
+ Seibu Cop (Co-Processor) device emulation
+ a.k.a. known as Toshiba gate array TC25SC rebadged as:
+ SEI300 - Legionnaire PCB
+ [...]
+ There's also a ROM labeled COP-Dx, which is probably used for some in-game maths:
+ COP-D1 - Seibu Cup Soccer PCBs
+ COP-D2 - legionna.cpp and raiden2.cpp, latter might use another component too
+ COP-D3 - New Zero Team / Raiden 2 V33 HWs
+ Raiden 2 first boss arms is known to behave strangely without this ROM on a real PCB
+
+ TODO:
+ - improve documentation, ffs!
+ - split into files, still needed:
+ - BCD;
+ - collision detection;
+ - command parser -> to cmd file;
+ - sd gundam sprite dma -> to dma file;
+ - convert to internal memory map, remove trampolines along the way.
+ - DMA mode needs to be cleaned up;
+ - improve class OO public/protected/private;
+ - nuke legacy command implementations;
+ - assert for something that needs actual playtesting is bad.
+ - add better debug facilities in a new sub-class, including but not limited to:
+ - disable collision detection;
+ - printing facilities;
+ - debugger break on pre-setted commands;
+ - ...
+
+ per-game TODO:
+ Legionnaire
+ - (fixed) player walks on spot on stage clear;
+ - several if not all enemies definitely wants some sort of "axis aligned bounding box" in order to stop from going out of range
+ (when i.e. first boss goes to bottom of the screen and become unreachable)
+ - (btanb) Throw is made by quickly double jumping (!)
+ Heated Barrel
+ - gives random value to hi-score if you continue (only the first time, not a bug?);
+ - (fixed?) throws random address exceptions at level 3 and above, a RAM address arrives corrupt in the snippet at 0x136a;
+ - (fixed?) some corrupt sprites, probably a non-fatal version of the one above;
+ - stage 2 boss attacks only in vertical (regressed with the 130e / 3b30 / 42c2 command merge);
+ - (fixed) level 3+ boss movements looks wrong;
+ - stage 3 "homing" missiles doesn't seem to like our 6200 hookup here, except it's NOT 6200!?
+ - barrels seen in later levels seems to fail an axis aligned bounding box, not unlike Legionnaire.
+ SD Gundam
+ - stage 3 mid-boss still has the sprite garbage bug;
+ - stage 4: has sprite stuck on bottom-left of screen;
+ - palette dims too much on attract / continue screen.
It's known that the DMA data arrangement gives same results on a real Legionnaire board, so shrug?
-
- Tech notes (to move into mainpage):
- -----------
- [0x6fc] DMA mode bit scheme:
- ---1 ---1 ---- ---- fill op if true, else transfer
- ---- ---- x--- ---- palette brightness
- ---- ---- ---x ---- internal buffer selector
- ---- ---- ---- x--- size modifier? Bus transfer size actually?
- ---- ---- ---- -xxx select channel
-
+
+ Tech notes (to move into mainpage):
+ -----------
+ [0x6fc] DMA mode bit scheme:
+ ---1 ---1 ---- ---- fill op if true, else transfer
+ ---- ---- x--- ---- palette brightness
+ ---- ---- ---x ---- internal buffer selector
+ ---- ---- ---- x--- size modifier? Bus transfer size actually?
+ ---- ---- ---- -xxx select channel
+
***************************************************************************/
#include "emu.h"
@@ -242,7 +242,7 @@ void raiden2cop_device::device_start()
m_host_cpu = machine().device<cpu_device>("maincpu");
m_host_space = &m_host_cpu->space(AS_PROGRAM);
m_host_endian = m_host_space->endianness() == ENDIANNESS_BIG; // m_cpu_is_68k
-
+
m_byte_endian_val = m_host_endian ? 3 : 0;
m_word_endian_val = m_host_endian ? 2 : 0;
}
@@ -708,11 +708,11 @@ WRITE16_MEMBER(raiden2cop_device::cop_dma_trigger_w)
switch (cop_dma_mode)
{
case 0x14:
- {
+ {
dma_tilemap_buffer();
break;
}
-
+
case 0x15:
{
dma_palette_buffer();
@@ -727,10 +727,10 @@ WRITE16_MEMBER(raiden2cop_device::cop_dma_trigger_w)
case 0x85:
case 0x86:
case 0x87:
- { dma_palette_brightness();
+ { dma_palette_brightness();
break;
}
-
+
/********************************************************************************************************************/
case 0x09: {
UINT32 src, dst, size;
@@ -795,7 +795,7 @@ WRITE16_MEMBER(raiden2cop_device::cop_dma_trigger_w)
case 0x11c:
case 0x11d:
case 0x11e:
- case 0x11f:
+ case 0x11f:
{
dma_fill();
break;
@@ -843,7 +843,7 @@ WRITE16_MEMBER(raiden2cop_device::cop_itoa_low_w)
WRITE16_MEMBER(raiden2cop_device::cop_itoa_high_w)
{
cop_itoa = (cop_itoa & ~(mem_mask << 16)) | ((data & mem_mask) << 16);
-
+
// Godzilla cares, otherwise you get 2p score overflow in 1p vs 2p, TODO: might actually be HW endianness dependant?
bcd_update();
}
@@ -1553,7 +1553,7 @@ WRITE16_MEMBER(raiden2cop_device::LEGACY_cop_cmd_w)
{
if(data == 0xf105) // cupsoc transition from presentation to kick off
return;
-
+
printf("did not execute %04x\n", data); // cup soccer triggers this a lot (and others)
}
}
diff --git a/src/mame/machine/seibucop/seibucop.h b/src/mame/machine/seibucop/seibucop.h
index 1e6e2c4c9fa..fbf8ecced76 100644
--- a/src/mame/machine/seibucop/seibucop.h
+++ b/src/mame/machine/seibucop/seibucop.h
@@ -10,9 +10,9 @@
#ifndef RAIDEN2COP_H
#define RAIDEN2COP_H
-#define LOG_Commands 0
-#define LOG_Phytagoras 0
-#define LOG_Division 0
+#define LOG_Commands 0
+#define LOG_Phytagoras 0
+#define LOG_Division 0
#define LOG_Move0205 0
#define LOG_Move0905 0
@@ -211,14 +211,14 @@ private:
// internal state
devcb_write16 m_videoramout_cb;
required_device<palette_device> m_palette;
-
- cpu_device *m_host_cpu; /**< reference to the host cpu */
+
+ cpu_device *m_host_cpu; /**< reference to the host cpu */
address_space *m_host_space; /**< reference to the host cpu space */
- bool m_host_endian; /**< reference to the host cpu endianness, some commands cares! */
- UINT8 m_byte_endian_val; /**< 2 if m_host_endian is big (68k) else 0 */
- UINT8 m_word_endian_val; /**< 3 if m_host_endian is big (68k) else 0 */
+ bool m_host_endian; /**< reference to the host cpu endianness, some commands cares! */
+ UINT8 m_byte_endian_val; /**< 2 if m_host_endian is big (68k) else 0 */
+ UINT8 m_word_endian_val; /**< 3 if m_host_endian is big (68k) else 0 */
+
-
void cop_collision_read_pos(int slot, UINT32 spradr, bool allow_swap);
// commands, TODO: needs commenting!
@@ -257,15 +257,15 @@ private:
void LEGACY_execute_d104(int offset, UINT16 data);
void LEGACY_execute_6980(int offset, UINT16 data);
void LEGACY_execute_c480(int offset, UINT16 data);
-
+
void cop_collision_update_hitbox(UINT16 data, int slot, UINT32 hitadr);
void bcd_update();
-
+
UINT16 cop_read_word(int address);
UINT8 cop_read_byte(int address);
void cop_write_word(int address, UINT16 data);
void cop_write_byte(int address, UINT8 data);
-
+
void dma_tilemap_buffer();
void dma_palette_buffer();
void dma_fill();
diff --git a/src/mame/machine/sms.cpp b/src/mame/machine/sms.cpp
index 8941b2513f2..2a1f57da928 100644
--- a/src/mame/machine/sms.cpp
+++ b/src/mame/machine/sms.cpp
@@ -800,7 +800,7 @@ WRITE8_MEMBER(sms_state::sms_mem_control_w)
READ8_MEMBER(sms_state::sg1000m3_peripheral_r)
{
bool joy_ports_disabled = m_sgexpslot->is_readable(offset);
-
+
if (joy_ports_disabled)
{
return m_sgexpslot->read(space, offset);
@@ -818,7 +818,7 @@ READ8_MEMBER(sms_state::sg1000m3_peripheral_r)
WRITE8_MEMBER(sms_state::sg1000m3_peripheral_w)
{
bool joy_ports_disabled = m_sgexpslot->is_writeable(offset);
-
+
if (joy_ports_disabled)
{
m_sgexpslot->write(space, offset, data);
diff --git a/src/mame/machine/xbox.cpp b/src/mame/machine/xbox.cpp
index e4cdcee007b..35654e90b42 100644
--- a/src/mame/machine/xbox.cpp
+++ b/src/mame/machine/xbox.cpp
@@ -2362,17 +2362,17 @@ int xbox_base_state::smbus_cx25871(int command, int rw, int data)
// let's try to fake the missing eeprom, make sure its ntsc
static int dummyeeprom[256] = {
- 0x39, 0xe3, 0xcc, 0x81, 0xb0, 0xa9, 0x97, 0x09, 0x57, 0xac, 0x57, 0x12, 0xf7, 0xc2, 0xc0, 0x21, 0xce, 0x0d, 0x0a, 0xdb, 0x20, 0x7a, 0xf3, 0xff,
- 0xdf, 0x67, 0xed, 0xf4, 0xf8, 0x95, 0x5c, 0xd0, 0x9b, 0xef, 0x7b, 0x81, 0xda, 0xd5, 0x98, 0xc1, 0xb1, 0xb3, 0x74, 0x18, 0x86, 0x05, 0xe2, 0x7c,
- 0xd1, 0xad, 0xc9, 0x90, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x00, 0x00,
- 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, 0xab, 0xcd, 0xef, 0xba, 0xdc, 0xfe, 0xa1, 0xb2, 0xc3, 0xd3, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+ 0x39, 0xe3, 0xcc, 0x81, 0xb0, 0xa9, 0x97, 0x09, 0x57, 0xac, 0x57, 0x12, 0xf7, 0xc2, 0xc0, 0x21, 0xce, 0x0d, 0x0a, 0xdb, 0x20, 0x7a, 0xf3, 0xff,
+ 0xdf, 0x67, 0xed, 0xf4, 0xf8, 0x95, 0x5c, 0xd0, 0x9b, 0xef, 0x7b, 0x81, 0xda, 0xd5, 0x98, 0xc1, 0xb1, 0xb3, 0x74, 0x18, 0x86, 0x05, 0xe2, 0x7c,
+ 0xd1, 0xad, 0xc9, 0x90, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x00, 0x00,
+ 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, 0xab, 0xcd, 0xef, 0xba, 0xdc, 0xfe, 0xa1, 0xb2, 0xc3, 0xd3, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
int smbus_callback_eeprom(xbox_base_state &chs, int command, int rw, int data)
{
diff --git a/src/mame/mame.lst b/src/mame/mame.lst
index 559fd730b5e..4a723c60b12 100644
--- a/src/mame/mame.lst
+++ b/src/mame/mame.lst
@@ -9204,8 +9204,8 @@ dking // Crazy Kong Bootleg
guzzler // (c) 1983 Tehkan
guzzlers // (c) 1983 Tehkan (Swimmer Conversion)
monkeyd // bootleg
-rpatrol // (c) 1981.01 Orca
-rpatrola // bootleg
+rpatrol // (c) 1981.01 Orca
+rpatrola // bootleg
rpatrolb // bootleg
silvland // Falcon
swimmer // (c) 1982 Tehkan
@@ -14198,7 +14198,7 @@ mjkinjas // (c) 1991 Home Data
mjkojink // (c) 1989 Home Data
mjprivat // (c) 1991 Matoba
mjyougo // (c) 1989 Home Data
-mjjoship // (c) 1988 Home Data
+mjjoship // (c) 1988 Home Data
mrokumei // (c) 1988 Home Data
reikaids // (c) 1988 Home Data
vitaminc // (c) 1989 Home Data
diff --git a/src/mame/video/chihiro.cpp b/src/mame/video/chihiro.cpp
index 7ce95c67ff9..48cca5d119c 100644
--- a/src/mame/video/chihiro.cpp
+++ b/src/mame/video/chihiro.cpp
@@ -4617,7 +4617,7 @@ WRITE32_MEMBER(nv2a_renderer::geforce_w)
//printf("dmaget %08X dmaput %08X\n\r",*dmaget,*dmaput);
if (((*dmaput == 0x048cf000) && (*dmaget == 0x07f4d000)) || // only for outr2
((*dmaput == 0x07dca000) && (*dmaget == 0x07f4d000))) // only for crtaxihr
- {
+ {
*dmaget = *dmaput;
puller_waiting = 0;
puller_timer->enable(false);
diff --git a/src/mame/video/divebomb.cpp b/src/mame/video/divebomb.cpp
index 275ef64e173..1da5769aa31 100644
--- a/src/mame/video/divebomb.cpp
+++ b/src/mame/video/divebomb.cpp
@@ -20,13 +20,13 @@
TILE_GET_INFO_MEMBER(divebomb_state::get_fg_tile_info)
{
- UINT32 code = m_fgram[tile_index + 0x000];
- UINT32 attr = m_fgram[tile_index + 0x400];
- UINT32 colour = attr >> 4;
+ UINT32 code = m_fgram[tile_index + 0x000];
+ UINT32 attr = m_fgram[tile_index + 0x400];
+ UINT32 colour = attr >> 4;
- code |= (attr & 0x3) << 8;
+ code |= (attr & 0x3) << 8;
- SET_TILE_INFO_MEMBER(0, code, colour, 0);
+ SET_TILE_INFO_MEMBER(0, code, colour, 0);
}
@@ -39,15 +39,15 @@ TILE_GET_INFO_MEMBER(divebomb_state::get_fg_tile_info)
K051316_CB_MEMBER(divebomb_state::zoom_callback_1)
{
- *code |= (*color & 0x03) << 8;
- *color = 0 + ((roz_pal >> 4) & 3);
+ *code |= (*color & 0x03) << 8;
+ *color = 0 + ((roz_pal >> 4) & 3);
}
K051316_CB_MEMBER(divebomb_state::zoom_callback_2)
{
- *code |= (*color & 0x03) << 8;
- *color = 4 + (roz_pal & 3);
+ *code |= (*color & 0x03) << 8;
+ *color = 4 + (roz_pal & 3);
}
@@ -60,47 +60,47 @@ K051316_CB_MEMBER(divebomb_state::zoom_callback_2)
WRITE8_MEMBER(divebomb_state::fgram_w)
{
- m_fgram[offset] = data;
- m_fg_tilemap->mark_tile_dirty(offset & 0x3ff);
+ m_fgram[offset] = data;
+ m_fg_tilemap->mark_tile_dirty(offset & 0x3ff);
}
WRITE8_MEMBER(divebomb_state::rozcpu_wrap1_enable_w)
{
- roz1_wrap = !(data & 1);
+ roz1_wrap = !(data & 1);
}
WRITE8_MEMBER(divebomb_state::rozcpu_enable1_w)
{
- roz1_enable = !(data & 1);
+ roz1_enable = !(data & 1);
}
WRITE8_MEMBER(divebomb_state::rozcpu_enable2_w)
{
- roz2_enable = !(data & 1);
+ roz2_enable = !(data & 1);
}
WRITE8_MEMBER(divebomb_state::rozcpu_wrap2_enable_w)
{
- roz2_wrap = !(data & 1);
+ roz2_wrap = !(data & 1);
}
WRITE8_MEMBER(divebomb_state::rozcpu_pal_w)
{
- //.... ..xx K051316 1 palette select
- //..xx .... K051316 2 palette select
-
- roz_pal = data;
-
- m_k051316_2->mark_tmap_dirty();
- m_k051316_1->mark_tmap_dirty();
-
- if (data & 0xcc)
- logerror("rozcpu_port50_w %02x\n", data);
+ //.... ..xx K051316 1 palette select
+ //..xx .... K051316 2 palette select
+
+ roz_pal = data;
+
+ m_k051316_2->mark_tmap_dirty();
+ m_k051316_1->mark_tmap_dirty();
+
+ if (data & 0xcc)
+ logerror("rozcpu_port50_w %02x\n", data);
}
@@ -113,50 +113,50 @@ WRITE8_MEMBER(divebomb_state::rozcpu_pal_w)
void divebomb_state::decode_proms(const UINT8 * rgn, int size, int index, bool inv)
{
- static const int resistances[4] = { 2000, 1000, 470, 220 };
-
- double rweights[4], gweights[4], bweights[4];
-
- /* compute the color output resistor weights */
- compute_resistor_weights(0, 255, -1.0,
- 4, resistances, rweights, 0, 0,
- 4, resistances, gweights, 0, 0,
- 4, resistances, bweights, 0, 0);
-
- /* create a lookup table for the palette */
- for (UINT32 i = 0; i < size; ++i)
- {
- UINT32 rdata = rgn[i + size*2] & 0x0f;
- UINT32 r = combine_4_weights(rweights, BIT(rdata, 0), BIT(rdata, 1), BIT(rdata, 2), BIT(rdata, 3));
-
- UINT32 gdata = rgn[i + size] & 0x0f;
- UINT32 g = combine_4_weights(gweights, BIT(gdata, 0), BIT(gdata, 1), BIT(gdata, 2), BIT(gdata, 3));
-
- UINT32 bdata = rgn[i] & 0x0f;
- UINT32 b = combine_4_weights(bweights, BIT(bdata, 0), BIT(bdata, 1), BIT(bdata, 2), BIT(bdata, 3));
-
- if (!inv)
- m_palette->set_pen_color(index + i, rgb_t(r, g, b));
- else
- m_palette->set_pen_color(index + (i ^ 0xff), rgb_t(r, g, b));
- }
+ static const int resistances[4] = { 2000, 1000, 470, 220 };
+
+ double rweights[4], gweights[4], bweights[4];
+
+ /* compute the color output resistor weights */
+ compute_resistor_weights(0, 255, -1.0,
+ 4, resistances, rweights, 0, 0,
+ 4, resistances, gweights, 0, 0,
+ 4, resistances, bweights, 0, 0);
+
+ /* create a lookup table for the palette */
+ for (UINT32 i = 0; i < size; ++i)
+ {
+ UINT32 rdata = rgn[i + size*2] & 0x0f;
+ UINT32 r = combine_4_weights(rweights, BIT(rdata, 0), BIT(rdata, 1), BIT(rdata, 2), BIT(rdata, 3));
+
+ UINT32 gdata = rgn[i + size] & 0x0f;
+ UINT32 g = combine_4_weights(gweights, BIT(gdata, 0), BIT(gdata, 1), BIT(gdata, 2), BIT(gdata, 3));
+
+ UINT32 bdata = rgn[i] & 0x0f;
+ UINT32 b = combine_4_weights(bweights, BIT(bdata, 0), BIT(bdata, 1), BIT(bdata, 2), BIT(bdata, 3));
+
+ if (!inv)
+ m_palette->set_pen_color(index + i, rgb_t(r, g, b));
+ else
+ m_palette->set_pen_color(index + (i ^ 0xff), rgb_t(r, g, b));
+ }
}
PALETTE_INIT_MEMBER(divebomb_state, divebomb)
{
- decode_proms(memregion("spr_proms")->base(), 0x100, 0x400 + 0x400 + 0x400, false);
- decode_proms(memregion("fg_proms")->base(), 0x400, 0x400 + 0x400, false);
- decode_proms(memregion("k051316_1_pr")->base(), 0x400, 0, true);
- decode_proms(memregion("k051316_2_pr")->base(), 0x400, 0x400, true);
+ decode_proms(memregion("spr_proms")->base(), 0x100, 0x400 + 0x400 + 0x400, false);
+ decode_proms(memregion("fg_proms")->base(), 0x400, 0x400 + 0x400, false);
+ decode_proms(memregion("k051316_1_pr")->base(), 0x400, 0, true);
+ decode_proms(memregion("k051316_2_pr")->base(), 0x400, 0x400, true);
}
VIDEO_START_MEMBER(divebomb_state,divebomb)
{
- m_fg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(divebomb_state::get_fg_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
- m_fg_tilemap->set_transparent_pen(0);
- m_fg_tilemap->set_scrolly(0, 16);
+ m_fg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(divebomb_state::get_fg_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
+ m_fg_tilemap->set_transparent_pen(0);
+ m_fg_tilemap->set_scrolly(0, 16);
}
@@ -169,41 +169,41 @@ VIDEO_START_MEMBER(divebomb_state,divebomb)
void divebomb_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
{
- const UINT8 *spriteram = m_spriteram;
-
- for (UINT32 i = 0; i < m_spriteram.bytes(); i += 4)
- {
- UINT32 sy = spriteram[i + 3];
- UINT32 sx = spriteram[i + 0];
- UINT32 code = spriteram[i + 2];
- UINT32 attr = spriteram[i + 1];
-
- code += (attr & 0x0f) << 8;
-
- UINT32 colour = attr >> 4;
-
- m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, colour, 0, 0, sx, sy, 0);
- m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, colour, 0, 0, sx, sy-256, 0);
- }
+ const UINT8 *spriteram = m_spriteram;
+
+ for (UINT32 i = 0; i < m_spriteram.bytes(); i += 4)
+ {
+ UINT32 sy = spriteram[i + 3];
+ UINT32 sx = spriteram[i + 0];
+ UINT32 code = spriteram[i + 2];
+ UINT32 attr = spriteram[i + 1];
+
+ code += (attr & 0x0f) << 8;
+
+ UINT32 colour = attr >> 4;
+
+ m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, colour, 0, 0, sx, sy, 0);
+ m_gfxdecode->gfx(1)->transpen(bitmap, cliprect, code, colour, 0, 0, sx, sy-256, 0);
+ }
}
UINT32 divebomb_state::screen_update_divebomb(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
- m_k051316_1->wraparound_enable(roz1_wrap);
- m_k051316_2->wraparound_enable(roz2_wrap);
+ m_k051316_1->wraparound_enable(roz1_wrap);
+ m_k051316_2->wraparound_enable(roz2_wrap);
+
+ bitmap.fill(m_palette->black_pen(), cliprect);
- bitmap.fill(m_palette->black_pen(), cliprect);
+ if (roz2_enable)
+ m_k051316_2->zoom_draw(screen, bitmap, cliprect, 0, 0);
- if (roz2_enable)
- m_k051316_2->zoom_draw(screen, bitmap, cliprect, 0, 0);
-
- if (roz1_enable)
- m_k051316_1->zoom_draw(screen, bitmap, cliprect, 0, 0);
+ if (roz1_enable)
+ m_k051316_1->zoom_draw(screen, bitmap, cliprect, 0, 0);
- draw_sprites(bitmap, cliprect);
+ draw_sprites(bitmap, cliprect);
- m_fg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
+ m_fg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
- return 0;
+ return 0;
}
diff --git a/src/mame/video/exerion.cpp b/src/mame/video/exerion.cpp
index c2d30a8daac..df90f829362 100644
--- a/src/mame/video/exerion.cpp
+++ b/src/mame/video/exerion.cpp
@@ -389,11 +389,11 @@ UINT32 exerion_state::screen_update_exerion(screen_device &screen, bitmap_ind16
code &= ~0x10, code2 |= 0x10;
gfx->transmask(bitmap,cliprect, code2, color, xflip, yflip, x, y + gfx->height(),
- m_palette->transpen_mask(*gfx, color, 0x10));
+ m_palette->transpen_mask(*gfx, color, 0x10));
}
gfx->transmask(bitmap,cliprect, code, color, xflip, yflip, x, y,
- m_palette->transpen_mask(*gfx, color, 0x10));
+ m_palette->transpen_mask(*gfx, color, 0x10));
if (doubled) i += 4;
}
diff --git a/src/mame/video/gotya.cpp b/src/mame/video/gotya.cpp
index ca2070a70f1..54f549f8513 100644
--- a/src/mame/video/gotya.cpp
+++ b/src/mame/video/gotya.cpp
@@ -153,9 +153,9 @@ void gotya_state::draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect
m_gfxdecode->gfx(1)->transpen(bitmap,cliprect,
- code, color,
- flip_screen_x(), flip_screen_y(),
- sx, sy, 0);
+ code, color,
+ flip_screen_x(), flip_screen_y(),
+ sx, sy, 0);
}
}
diff --git a/src/mame/video/homedata.cpp b/src/mame/video/homedata.cpp
index 355cf3411c7..a77e534e821 100644
--- a/src/mame/video/homedata.cpp
+++ b/src/mame/video/homedata.cpp
@@ -949,7 +949,7 @@ UINT32 homedata_state::screen_update_pteacher(screen_device &screen, bitmap_ind1
246 = 96 17 ef db (mjjoship)
35*8 = bc 0b ef f0
51*8 = a6 07 ef db (mjikaga)
- 414 = b7 10 ef db (mjjoship, db becomes e8 after first loss)
+ 414 = b7 10 ef db (mjjoship, db becomes e8 after first loss)
54*8 = bc 07 ef e8
but in mjkinjas it's
@@ -987,17 +987,17 @@ UINT32 homedata_state::screen_update_pteacher(screen_device &screen, bitmap_ind1
}
else
{
- if (m_vreg[0x3] == 0xa6)
+ if (m_vreg[0x3] == 0xa6)
{
screen.set_visible_area(0*8, 51*8-1, 2*8, 30*8-1);
scroll_low = 7 - (m_vreg[0x4] & 0x0f);
}
- else if (m_vreg[0x3] == 0xb7)
+ else if (m_vreg[0x3] == 0xb7)
{
screen.set_visible_area(0*8, 52*8-3, 2*8, 30*8-1);
- scroll_low = 0;
+ scroll_low = 0;
}
- else
+ else
{
screen.set_visible_area(0*8, 54*8-1, 2*8, 30*8-1);
scroll_low = 7 - (m_vreg[0x4] & 0x0f);
diff --git a/src/mame/video/megasys1.cpp b/src/mame/video/megasys1.cpp
index 35d9f95cc3e..0d422feb0f4 100644
--- a/src/mame/video/megasys1.cpp
+++ b/src/mame/video/megasys1.cpp
@@ -447,7 +447,7 @@ WRITE16_MEMBER(megasys1_state::megasys1_vregs_A_w)
break;
case 0x308/2 : if (!m_hardware_type_z)
- {
+ {
m_soundlatch->write(space,0,new_data,0xffff);
m_audiocpu->set_input_line(4, HOLD_LINE);
}
diff --git a/src/mame/video/model3.cpp b/src/mame/video/model3.cpp
index 28b3a5efe11..0113e5dadcc 100644
--- a/src/mame/video/model3.cpp
+++ b/src/mame/video/model3.cpp
@@ -711,20 +711,20 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
- Color table (is this featured in Model 3?)
0x00: xxxxxxxx xxxxxxxx xxxxxx-- -------- Viewport number
- -------- -------- ------xx -------- Viewport select 0-3
- -------- -------- -------- x------- Display select
- -------- -------- -------- -x------ Fix point centroid
- -------- -------- -------- --x----- Viewport off
+ -------- -------- ------xx -------- Viewport select 0-3
+ -------- -------- -------- x------- Display select
+ -------- -------- -------- -x------ Fix point centroid
+ -------- -------- -------- --x----- Viewport off
-------- -------- -------- ---xx--- Viewport priority
- -------- -------- -------- -----x-- "clr_xlator_tbl_sel"
- -------- -------- -------- ------xx Node type
+ -------- -------- -------- -----x-- "clr_xlator_tbl_sel"
+ -------- -------- -------- ------xx Node type
0x01: -------x -------- -------- -------- Sibling null
- -------- xxxxxxxx xxxxxxxx xxxxxxxx Sibling pointer
+ -------- xxxxxxxx xxxxxxxx xxxxxxxx Sibling pointer
0x02: -----x-- -------- -------- -------- Child is sibling table
- -------x -------- -------- -------- Leaf node
- -------- xxxxxxxx xxxxxxxx xxxxxxxx Child pointer
+ -------x -------- -------- -------- Leaf node
+ -------- xxxxxxxx xxxxxxxx xxxxxxxx Child pointer
0x03: "cota" (float) Affected by frustum angles and viewport size
0x04: Sun light vector X-component (float)
@@ -763,7 +763,7 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
0x1b: Copy of word 0x00
0x1c: xxxxxxxx xxxxxxxx -------- -------- "lj"
- -------- -------- xxxxxxxx xxxxxxxx "li"
+ -------- -------- xxxxxxxx xxxxxxxx "li"
0x1d: -------- xxxxxxxx -------- -------- Spotlight Y size
-------- -------- xxxxxxxx xxxxxxxx Spotlight Y position (13.3 fixed-point?)
@@ -775,7 +775,7 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
0x20: xxxxxxxx -------- -------- -------- ?
-------- xxxxxxxx -------- -------- ?
- -------- -------- -x------ -------- Parallel projection
+ -------- -------- -x------ -------- Parallel projection
-------- -------- --xxx--- -------- Light RGB (RGB111?)
-------- -------- -----xxx -------- Light RGB Fog (RGB111?)
-------- -------- -------- xxxxxxxx Scroll Fog (0.8 fixed-point?) What is this???
@@ -789,15 +789,15 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
-------- -------- -------- xxxxxxxx Scroll attenuation (0.8 fixed-point) What is this???
0x25: -------- xxxxxxxx -------- -------- Ambient fog
- -------- -------- xxxxxxxx xxxxxxxx Fog offset
+ -------- -------- xxxxxxxx xxxxxxxx Fog offset
0x26: xxxxxxxx xxxxxxxx xxxxxxxx -------- Spot light
- -------- -------- -------- x------- Clear viewport
- -------- -------- -------- -x------ New sun parameters
+ -------- -------- -------- x------- Clear viewport
+ -------- -------- -------- -x------ New sun parameters
0x27: x------- -------- -------- -------- Valid spot light
- -x------ -------- -------- -------- Pro 1000 dummy
- -------- --xxxxxx xxxxxxxx xxxxxxxx "upgrade_wd_10"
+ -x------ -------- -------- -------- Pro 1000 dummy
+ -------- --xxxxxx xxxxxxxx xxxxxxxx "upgrade_wd_10"
0x28: Fog layer altitude (float)
@@ -806,7 +806,7 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
0x2a: Bottom fog density (float)
0x2b: Near clipping plane (float)
-
+
0x2c: Far clipping plane (float)
0x2d: Pfog offset top
@@ -851,22 +851,22 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
Instance Node?
0x00: x------- -------- -------- -------- Is UF ref
- -x------ -------- -------- -------- Is 3D model
- --x----- -------- -------- -------- Is point
- ---x---- -------- -------- -------- Is point ref
- ----x--- -------- -------- -------- Is animation
- -----x-- -------- -------- -------- Is billboard
- ------x- -------- -------- -------- Child is billboard
- -------x -------- -------- -------- Extra child pointer needed
- -------- -----xxx xxxxxx-- -------- Node ID
-
- -------- -------- -------- x------- Reset matrix
- -------- -------- -------- -x------ Use child pointer
- -------- -------- -------- --x----- Use sibling pointer
- -------- -------- -------- ---x---- No matrix
- -------- -------- -------- ----x--- Indirect child
- -------- -------- -------- -----x-- Valid color table
- -------- -------- -------- ------xx Node type (0 = viewport, 1 = root node, 2 = culling node)
+ -x------ -------- -------- -------- Is 3D model
+ --x----- -------- -------- -------- Is point
+ ---x---- -------- -------- -------- Is point ref
+ ----x--- -------- -------- -------- Is animation
+ -----x-- -------- -------- -------- Is billboard
+ ------x- -------- -------- -------- Child is billboard
+ -------x -------- -------- -------- Extra child pointer needed
+ -------- -----xxx xxxxxx-- -------- Node ID
+
+ -------- -------- -------- x------- Reset matrix
+ -------- -------- -------- -x------ Use child pointer
+ -------- -------- -------- --x----- Use sibling pointer
+ -------- -------- -------- ---x---- No matrix
+ -------- -------- -------- ----x--- Indirect child
+ -------- -------- -------- -----x-- Valid color table
+ -------- -------- -------- ------xx Node type (0 = viewport, 1 = root node, 2 = culling node)
0x01,0x02 only present on Step 2+
@@ -885,14 +885,14 @@ cached_texture *model3_state::get_texture(int page, int texx, int texy, int texw
0x06: Translation Z coordinate
0x07: xxxx---- -------- -------- -------- Color table address 2
- -----x-- -------- -------- -------- Sibling table
- ------x- -------- -------- -------- Point
- -------x -------- -------- -------- Leaf node
- -------- xxxxxxxx xxxxxxxx xxxxxxxx Child pointer
-
- 0x08: xxxxxxx- -------- -------- -------- Color table address 3
- -------x -------- -------- -------- Null sibling
- -------- xxxxxxxx xxxxxxxx xxxxxxxx Sibling pointer
+ -----x-- -------- -------- -------- Sibling table
+ ------x- -------- -------- -------- Point
+ -------x -------- -------- -------- Leaf node
+ -------- xxxxxxxx xxxxxxxx xxxxxxxx Child pointer
+
+ 0x08: xxxxxxx- -------- -------- -------- Color table address 3
+ -------x -------- -------- -------- Null sibling
+ -------- xxxxxxxx xxxxxxxx xxxxxxxx Sibling pointer
0x09: xxxxxxxx xxxxxxxx -------- -------- Blend radius
-------- -------- xxxxxxxx xxxxxxxx Culling radius
diff --git a/src/mame/video/namconb1.cpp b/src/mame/video/namconb1.cpp
index 20e6a501a08..b18246ec376 100644
--- a/src/mame/video/namconb1.cpp
+++ b/src/mame/video/namconb1.cpp
@@ -130,7 +130,7 @@ VIDEO_START_MEMBER(namconb1_state,namconb1)
{
namco_tilemap_init(NAMCONB1_TILEGFX, memregion(NAMCONB1_TILEMASKREGION)->base(), NB1TilemapCB );
c355_obj_init(NAMCONB1_SPRITEGFX,0x0,namcos2_shared_state::c355_obj_code2tile_delegate(FUNC(namconb1_state::NB1objcode2tile), this));
-
+
save_item(NAME(m_tilemap_tile_bank));
} /* namconb1 */
@@ -189,6 +189,6 @@ VIDEO_START_MEMBER(namconb1_state,namconb2)
namco_tilemap_init(NAMCONB1_TILEGFX, memregion(NAMCONB1_TILEMASKREGION)->base(), NB2TilemapCB );
c355_obj_init(NAMCONB1_SPRITEGFX,0x0,namcos2_shared_state::c355_obj_code2tile_delegate(FUNC(namconb1_state::NB2objcode2tile), this));
c169_roz_init(NAMCONB1_ROTGFX,NAMCONB1_ROTMASKREGION);
-
+
save_item(NAME(m_tilemap_tile_bank));
} /* namconb2_vh_start */
diff --git a/src/mame/video/namcos2.cpp b/src/mame/video/namcos2.cpp
index 21e1979caf0..89986aea6fe 100644
--- a/src/mame/video/namcos2.cpp
+++ b/src/mame/video/namcos2.cpp
@@ -294,7 +294,7 @@ WRITE16_MEMBER( namcos2_state::rozram_word_w )
m_tilemap_roz->mark_tile_dirty(offset);
//if( space.machine().input().code_pressed(KEYCODE_Q) )
//{
- // machine().debug_break();
+ // machine().debug_break();
//}
}
diff --git a/src/mame/video/powervr2.cpp b/src/mame/video/powervr2.cpp
index b2f05d94069..8e512a0f7e1 100644
--- a/src/mame/video/powervr2.cpp
+++ b/src/mame/video/powervr2.cpp
@@ -1024,7 +1024,7 @@ WRITE32_MEMBER( powervr2_device::startrender_w )
}
// printf("ISP START %d %d\n",sanitycount,m_screen->vpos());
/* Fire ISP irq after a set amount of time TODO: timing of this */
- endofrender_timer_isp->adjust(state->m_maincpu->cycles_to_attotime(sanitycount*25 + 500000)); // hacky end of render delay for Capcom games, otherwise they works at ~1/10 speed
+ endofrender_timer_isp->adjust(state->m_maincpu->cycles_to_attotime(sanitycount*25 + 500000)); // hacky end of render delay for Capcom games, otherwise they works at ~1/10 speed
break;
}
}
diff --git a/src/mame/video/seibu_crtc.cpp b/src/mame/video/seibu_crtc.cpp
index 511f3046ebf..99200dae945 100644
--- a/src/mame/video/seibu_crtc.cpp
+++ b/src/mame/video/seibu_crtc.cpp
@@ -21,7 +21,7 @@ Raiden later rev (probably the first game to use it)
TODO:
- Most registers are still a mystery;
-- Get the proper Seibu chip ID number.
+- Get the proper Seibu chip ID number.
Kold found that a Raiden alt set has irq request pin from a chip named SEI0160, which might be our man.
preliminary memory map:
diff --git a/src/mame/video/vtvideo.cpp b/src/mame/video/vtvideo.cpp
index cea29595dc2..1356efc70ca 100644
--- a/src/mame/video/vtvideo.cpp
+++ b/src/mame/video/vtvideo.cpp
@@ -249,15 +249,15 @@ WRITE8_MEMBER(vt100_video_device::dc012_w)
printf("MHFU ___ENABLED___ %05x \n", space.device().safe_pc());
MHFU_FLAG = true;
- MHFU_counter = 0;
+ MHFU_counter = 0;
}
if (!(data & 0x08))
{
if (!(data & 0x04))
{
- m_scroll_latch_valid = false;
- m_scroll_latch = data & 0x03; // LSB is written first.
+ m_scroll_latch_valid = false;
+ m_scroll_latch = data & 0x03; // LSB is written first.
}
else // set MSB of scroll_latch
{