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author 68bit <53298758+68bit@users.noreply.github.com>2019-08-21 03:35:55 +1000
committer R. Belmont <rb6502@users.noreply.github.com>2019-08-20 13:35:55 -0400
commit16edc9f13b02987627da1e7cc764c903770661ea (patch)
tree1cb2a9558e1c1b7cf5ecd046b81cad7784989791 /src/mame/drivers/swtpc.cpp
parent4369fe34f35fcc3ae2d3102da4b87d4778e965ce (diff)
SWTPC - add floppy disk support (#5513)
* ss-30 mps: default to 9600 baud * SWTPC - add floppy disk support Include the DC5 floppy disk controller on the expected SS-30 I/O positions of ports 5 and 6. Add a config option to select the CPU clock rate. Higher FDC clock rates need higher CPU rates to download the data fast enough without DMA. A couple of SWTBUG ROM patch config options are added to make disk booting more practical. Narrow the address range block used for the motherboard I/O to 0x8000 to 0x8fff, and also narrow the mirroring to potentially support two mother boards with twice as many I/O cards. Add documentation to explain these changes. Make 32K the default lower RAM size. Implement RAM from 0xa000 to 0xdfff, as FLEX needs much of that. Document the path to supporting Low and High PROMS. Emit a 9600 baud rate clock on the 150/9600 line. This was a practical rate at the time and screen based software is not practical at the prior rate of 1200 baud. This was a document option. The emulator now runs FLEX 2 on a range of disk formats. Disk driver software support is still an issue, another monitor PROM might be needed, there might be an issue with the FDC 'ready' input, but this is a big step forward.
Diffstat (limited to 'src/mame/drivers/swtpc.cpp')
-rw-r--r--src/mame/drivers/swtpc.cpp197
1 files changed, 168 insertions, 29 deletions
diff --git a/src/mame/drivers/swtpc.cpp b/src/mame/drivers/swtpc.cpp
index c4250611299..a1ca20ecef5 100644
--- a/src/mame/drivers/swtpc.cpp
+++ b/src/mame/drivers/swtpc.cpp
@@ -1,11 +1,9 @@
// license:BSD-3-Clause
-// copyright-holders:Robbbert
+// copyright-holders:Robbbert,68bit
/***************************************************************************
SWTPC 6800 Computer System
- 10/12/2009 Skeleton driver.
-
http://www.swtpc.com/mholley/swtpc_6800.htm
MIKBUG is made for a PIA (parallel) interface.
@@ -16,10 +14,68 @@
Note: All commands must be in uppercase. See the SWTBUG manual.
ToDo:
- - Add more SS-50 interface slot options
- Emulate MP-A2 revision of CPU board, with four 2716 ROM sockets
and allowance for extra RAM boards at A000-BFFF and C000-DFFF
+ The MP-B motherboard decodes 0x8000 to 0x9fff as being I/O on the
+ motherboard, but the MP-B2 motherboard narrowed this to 0x8000 to 0x8fff
+ allowing other boards to use the address range 0x9000 to 0x9fff, and this
+ narrower range is emulated here.
+
+ The MP-B2 motherboard decoded I/O address range can be relocate to any 4K
+ boundary from 0x8000 to 0xf000 with 0x8000 being the default, but
+ relocation requires an alternative monitor. TODO could add config options
+ for this choice if ever needed.
+
+ Within the 4K I/O address range only A2 to A5 are decoded, and A6 to A11
+ are not considered. By default A5 must be zero, but there is an option to
+ alternatively select the I/O when A5 is high to allow two motherboards to
+ be used together to support more cards, one for A5 low and the other for
+ A5 high. TODO might consider expanding the emulated SS30 bus to support
+ two banks of 8 I/O cards if anyone really need that many cards in the
+ emulator.
+
+ The address range 0x0000 to 0x7fff was used for memory expansion, off the
+ motherboard.
+
+ The MIKBUG or SWTBUG monitor ROMS required RAM in the address range 0xa000
+ to 0xa07f, which could be provided by a MCM6810 installed on the
+ MP-A. However FLEX 2 operating system requires RAM in the address range
+ 0xa000 to 0xbfff and the MCM6810 was disable and that RAM provided
+ externally to the MB and this larger RAM configuration is emulated here.
+
+ The address range 0xc000 to 0xdfff was usable for a 2K, 4K, 6K, or 8K
+ PROM (the Low PROM), or for RAM (MP-8M). This emulator implements RAM in
+ this region. TODO support a Low PROM.
+
+ The address range 0xe000 to 0xffff was usable for MIKBUG, SWTBUG (1K), or
+ a 2K, 4K, or 8K PROM (the High PROM). TODO support a High PROM.
+
+ Although the maximum baud rate generated by the MP-A is 1200 baud, the
+ documentation notes that the 14411 baud rate generator does generate other
+ rates up to 9600 baud and documents the pins to jumper to use these other
+ rates. This emulator implements such a modification supplying 9600 baud on
+ the otherwise 150 baud line, which consistent with the rate that the SWTPC
+ 6809 supplies on this bus line.
+
+ The FDC card, e.g. DC5, requires five addresses, four for the WD FDC and
+ one for a control register, which is one more than the 4 byte I/O
+ selection address range allows. On the 6800 the FDC was expected to be
+ installed in slot 6 and a jumper wire installed from the slot 5 select
+ line to the FDC card UD3 line input to select the control register. The
+ 6809 MB moved to 16 byte I/O ranges to cleanly address this
+ limitation. This hardware patch does not fit nicely in the emulator bus so
+ is implemented here by placing the card in slot 5 and adapting the FDC
+ card emulation to decode an 8 byte address range rather than 4
+ addresses. TODO reconsider if this can be handler better.
+
+ The DC5 FDC card offers an extra control register that can be used to set
+ the density and clock rate, see the DC5 source code for more
+ information. This might help booting disk images that are purely double
+ density with the SWTBUG disk boot support. E.g. For a 3.5" HD disk image
+ enter 'M 8016' which should show '02', the DC5 version, and then enter
+ '28' to select double density and a 2MHz clock. TODO include a better boot
+ ROM.
Commands:
B Breakpoint
@@ -44,7 +100,6 @@ Z Goto Prom (0xC000)
#include "machine/mc14411.h"
#include "machine/ram.h"
#include "bus/ss50/interface.h"
-#include "bus/ss50/mps.h"
class swtpc_state : public driver_device
{
@@ -54,12 +109,16 @@ public:
, m_maincpu(*this, "maincpu")
, m_ram(*this, "ram")
, m_brg(*this, "brg")
+ , m_maincpu_clock(*this, "maincpu_clock")
+ , m_swtbug_ready_wait(*this, "swtbug_ready_wait")
+ , m_swtbug_load_at_a100(*this, "swtbug_load_at_a100")
{ }
void swtpcm(machine_config &config);
void swtpc(machine_config &config);
private:
+ virtual void machine_reset() override;
virtual void machine_start() override;
void mem_map(address_map &map);
@@ -67,27 +126,100 @@ private:
required_device<cpu_device> m_maincpu;
required_device<ram_device> m_ram;
required_device<mc14411_device> m_brg;
+ required_ioport m_maincpu_clock;
+ required_ioport m_swtbug_ready_wait;
+ required_ioport m_swtbug_load_at_a100;
};
void swtpc_state::mem_map(address_map &map)
{
map.unmap_value_high();
- map(0x8000, 0x8003).mirror(0x1fc0).rw("io0", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
- map(0x8004, 0x8007).mirror(0x1fc0).rw("io1", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
- map(0x8008, 0x800b).mirror(0x1fc0).rw("io2", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
- map(0x800c, 0x800f).mirror(0x1fc0).rw("io3", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
- map(0x8010, 0x8013).mirror(0x1fc0).rw("io4", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
- map(0x8014, 0x8017).mirror(0x1fc0).rw("io5", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
- map(0x8018, 0x801b).mirror(0x1fc0).rw("io6", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
- map(0x801c, 0x801f).mirror(0x1fc0).rw("io7", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
- map(0xa000, 0xa07f).ram(); // MCM6810
+ map(0x8000, 0x8003).mirror(0x0fc0).rw("io0", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
+ map(0x8004, 0x8007).mirror(0x0fc0).rw("io1", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
+ map(0x8008, 0x800b).mirror(0x0fc0).rw("io2", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
+ map(0x800c, 0x800f).mirror(0x0fc0).rw("io3", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
+ map(0x8010, 0x8013).mirror(0x0fc0).rw("io4", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
+ // For the FDC a hardware patch was necesseary routing IO5 select to
+ // the FDC installed in slot 6. For the Emulator, give IO5 an 8 byte
+ // range for the FDC.
+ map(0x8014, 0x801b).mirror(0x0fc0).rw("io5", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
+ //map(0x8018, 0x801b).mirror(0x0fc0).rw("io6", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
+ map(0x801c, 0x801f).mirror(0x0fc0).rw("io7", FUNC(ss50_interface_port_device::read), FUNC(ss50_interface_port_device::write));
+ map(0xa000, 0xbfff).ram();
+ // TODO low prom, 2K, 4K, 6K, or 8K.
+ map(0xc000, 0xdfff).ram();
+ // TODO high prom, 1K, 2K, 4K, 8K.
map(0xe000, 0xe3ff).mirror(0x1c00).rom().region("mcm6830", 0);
}
/* Input ports */
static INPUT_PORTS_START( swtpc )
+ // Support some clock variations. The MP-A did not use a crystal for
+ // the CPU clock and the frequency was variable. The 6800 was
+ // available at speeds up to 2MHz so that might not have been
+ // impossible. An overclock option of 4MHz is also implemented.
+ PORT_START("maincpu_clock")
+ PORT_CONFNAME(0xffffff, 1000000, "CPU clock")
+ PORT_CONFSETTING( 898550, "0.89855 MHz") // MIKBUG
+ PORT_CONFSETTING( 921600, "0.92160 MHz") // SWTPC
+ PORT_CONFSETTING(1000000, "1.0 MHz")
+ PORT_CONFSETTING(2000000, "2.0 MHz")
+ PORT_CONFSETTING(4000000, "4.0 MHz")
+
+ // Patch the SWTBUG to wait for the motor to start. The SWTBUG
+ // accesses the FDC control register and then waits a period for the
+ // motor to start. Unfortunately the DC series of FDCs do not trigger
+ // the motor when accessing the control register, the drive does not
+ // have time to become ready before commands are issued and the boot
+ // fails. This workaround is necessary in practice.
+ PORT_START("swtbug_ready_wait")
+ PORT_CONFNAME(0x1, 1, "SWTBUG ready wait patch")
+ PORT_CONFSETTING(0, "No")
+ PORT_CONFSETTING(1, "Yes - apply patch")
+
+ // Patch SWTBUG to load the disk boot code at 0xa100 rather than
+ // 0x2400. The disk boot code is typically position dependent and many
+ // disk images expect to have their boot code loaded at 0xa100. TODO
+ // consider adding a separate machine using NEWBUG etc that loads at
+ // 0xa100 or perhaps better implement support for the high PROM to
+ // allow custom code to be used which is needed anyway as even NEWBUG
+ // appears to have issues and is not optimized for the DC5 FDC.
+ PORT_START("swtbug_load_at_a100")
+ PORT_CONFNAME(0x1, 1, "SWTBUG disk boot patch, to load at 0xa100")
+ PORT_CONFSETTING(0, "No")
+ PORT_CONFSETTING(1, "Yes - apply patch")
+
INPUT_PORTS_END
+static DEVICE_INPUT_DEFAULTS_START( dc5 )
+ DEVICE_INPUT_DEFAULTS("address_mode", 0xf, 0)
+DEVICE_INPUT_DEFAULTS_END
+
+void swtpc_state::machine_reset()
+{
+ uint32_t maincpu_clock = m_maincpu_clock->read();
+ if (maincpu_clock)
+ m_maincpu->set_clock(maincpu_clock);
+
+ // TODO make these SWTBUG patches conditional on using SWTBUG!
+
+ if (m_swtbug_ready_wait->read())
+ {
+ // Patch SWTBUG to also wait until the drive is ready.
+ uint8_t* swtbug = memregion("mcm6830")->base();
+ swtbug[0x029b] = 0x81;
+ }
+
+ if (m_swtbug_load_at_a100->read())
+ {
+ // Patch SWTBUG to load the disk boot sector at 0xa100.
+ uint8_t* swtbug = memregion("mcm6830")->base();
+ swtbug[0x02a7] = 0xa1; // Load address
+ swtbug[0x02a8] = 0x00;
+ swtbug[0x02bb] = 0xa1; // Entry address
+ swtbug[0x02bc] = 0x00;
+ }
+}
void swtpc_state::machine_start()
{
@@ -104,7 +236,8 @@ void swtpc_state::swtpc(machine_config &config)
m_maincpu->set_addrmap(AS_PROGRAM, &swtpc_state::mem_map);
MC14411(config, m_brg, XTAL(1'843'200));
- m_brg->out_f<7>().set("io0", FUNC(ss50_interface_port_device::f600_1200_w)); // 1200b
+ // 1200b
+ m_brg->out_f<7>().set("io0", FUNC(ss50_interface_port_device::f600_1200_w));
m_brg->out_f<7>().append("io1", FUNC(ss50_interface_port_device::f600_1200_w));
m_brg->out_f<7>().append("io2", FUNC(ss50_interface_port_device::f600_1200_w));
m_brg->out_f<7>().append("io3", FUNC(ss50_interface_port_device::f600_1200_w));
@@ -112,7 +245,8 @@ void swtpc_state::swtpc(machine_config &config)
m_brg->out_f<7>().append("io5", FUNC(ss50_interface_port_device::f600_1200_w));
m_brg->out_f<7>().append("io6", FUNC(ss50_interface_port_device::f600_1200_w));
m_brg->out_f<7>().append("io7", FUNC(ss50_interface_port_device::f600_1200_w));
- m_brg->out_f<8>().set("io0", FUNC(ss50_interface_port_device::f600_4800_w)); // 600b
+ // 600b
+ m_brg->out_f<8>().set("io0", FUNC(ss50_interface_port_device::f600_4800_w));
m_brg->out_f<8>().append("io1", FUNC(ss50_interface_port_device::f600_4800_w));
m_brg->out_f<8>().append("io2", FUNC(ss50_interface_port_device::f600_4800_w));
m_brg->out_f<8>().append("io3", FUNC(ss50_interface_port_device::f600_4800_w));
@@ -120,7 +254,8 @@ void swtpc_state::swtpc(machine_config &config)
m_brg->out_f<8>().append("io5", FUNC(ss50_interface_port_device::f600_4800_w));
m_brg->out_f<8>().append("io6", FUNC(ss50_interface_port_device::f600_4800_w));
m_brg->out_f<8>().append("io7", FUNC(ss50_interface_port_device::f600_4800_w));
- m_brg->out_f<9>().set("io0", FUNC(ss50_interface_port_device::f300_w)); // 300b
+ // 300b
+ m_brg->out_f<9>().set("io0", FUNC(ss50_interface_port_device::f300_w));
m_brg->out_f<9>().append("io1", FUNC(ss50_interface_port_device::f300_w));
m_brg->out_f<9>().append("io2", FUNC(ss50_interface_port_device::f300_w));
m_brg->out_f<9>().append("io3", FUNC(ss50_interface_port_device::f300_w));
@@ -128,15 +263,17 @@ void swtpc_state::swtpc(machine_config &config)
m_brg->out_f<9>().append("io5", FUNC(ss50_interface_port_device::f300_w));
m_brg->out_f<9>().append("io6", FUNC(ss50_interface_port_device::f300_w));
m_brg->out_f<9>().append("io7", FUNC(ss50_interface_port_device::f300_w));
- m_brg->out_f<11>().set("io0", FUNC(ss50_interface_port_device::f150_9600_w)); // 150b
- m_brg->out_f<11>().append("io1", FUNC(ss50_interface_port_device::f150_9600_w));
- m_brg->out_f<11>().append("io2", FUNC(ss50_interface_port_device::f150_9600_w));
- m_brg->out_f<11>().append("io3", FUNC(ss50_interface_port_device::f150_9600_w));
- m_brg->out_f<11>().append("io4", FUNC(ss50_interface_port_device::f150_9600_w));
- m_brg->out_f<11>().append("io5", FUNC(ss50_interface_port_device::f150_9600_w));
- m_brg->out_f<11>().append("io6", FUNC(ss50_interface_port_device::f150_9600_w));
- m_brg->out_f<11>().append("io7", FUNC(ss50_interface_port_device::f150_9600_w));
- m_brg->out_f<13>().set("io0", FUNC(ss50_interface_port_device::f110_w)); // 110b
+ // 150b pin 11, modified to wire the 14411 pin 1 to the f150 line for 9600b
+ m_brg->out_f<1>().set("io0", FUNC(ss50_interface_port_device::f150_9600_w));
+ m_brg->out_f<1>().append("io1", FUNC(ss50_interface_port_device::f150_9600_w));
+ m_brg->out_f<1>().append("io2", FUNC(ss50_interface_port_device::f150_9600_w));
+ m_brg->out_f<1>().append("io3", FUNC(ss50_interface_port_device::f150_9600_w));
+ m_brg->out_f<1>().append("io4", FUNC(ss50_interface_port_device::f150_9600_w));
+ m_brg->out_f<1>().append("io5", FUNC(ss50_interface_port_device::f150_9600_w));
+ m_brg->out_f<1>().append("io6", FUNC(ss50_interface_port_device::f150_9600_w));
+ m_brg->out_f<1>().append("io7", FUNC(ss50_interface_port_device::f150_9600_w));
+ // 110b
+ m_brg->out_f<13>().set("io0", FUNC(ss50_interface_port_device::f110_w));
m_brg->out_f<13>().append("io1", FUNC(ss50_interface_port_device::f110_w));
m_brg->out_f<13>().append("io2", FUNC(ss50_interface_port_device::f110_w));
m_brg->out_f<13>().append("io3", FUNC(ss50_interface_port_device::f110_w));
@@ -157,10 +294,10 @@ void swtpc_state::swtpc(machine_config &config)
ss50_interface_port_device &io3(SS50_INTERFACE(config, "io3", ss50_default_2rs_devices, nullptr));
io3.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<3>));
io3.firq_cb().set("mainnmi", FUNC(input_merger_device::in_w<3>));
- ss50_interface_port_device &io4(SS50_INTERFACE(config, "io4", ss50_default_2rs_devices, nullptr));
+ ss50_interface_port_device &io4(SS50_INTERFACE(config, "io4", ss50_default_2rs_devices, "mpt"));
io4.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<4>));
io4.firq_cb().set("mainnmi", FUNC(input_merger_device::in_w<4>));
- ss50_interface_port_device &io5(SS50_INTERFACE(config, "io5", ss50_default_2rs_devices, nullptr));
+ ss50_interface_port_device &io5(SS50_INTERFACE(config, "io5", ss50_default_2rs_devices, "dc5"));
io5.irq_cb().set("mainirq", FUNC(input_merger_device::in_w<5>));
io5.firq_cb().set("mainnmi", FUNC(input_merger_device::in_w<5>));
ss50_interface_port_device &io6(SS50_INTERFACE(config, "io6", ss50_default_2rs_devices, nullptr));
@@ -173,7 +310,9 @@ void swtpc_state::swtpc(machine_config &config)
INPUT_MERGER_ANY_HIGH(config, "mainirq").output_handler().set_inputline(m_maincpu, M6800_IRQ_LINE);
INPUT_MERGER_ANY_HIGH(config, "mainnmi").output_handler().set_inputline(m_maincpu, INPUT_LINE_NMI);
- RAM(config, RAM_TAG).set_default_size("2K").set_extra_options("4K,8K,12K,16K,20K,24K,28K,32K");
+ RAM(config, RAM_TAG).set_default_size("32K").set_extra_options("4K,8K,12K,16K,20K,24K,28K,32K");
+
+ io5.set_option_device_input_defaults("dc5", DEVICE_INPUT_DEFAULTS_NAME(dc5));
}
void swtpc_state::swtpcm(machine_config &config)