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author Miodrag Milanovic <mmicko@gmail.com>2016-06-29 08:34:30 +0200
committer Miodrag Milanovic <mmicko@gmail.com>2016-06-29 08:34:30 +0200
commit63f9a01f8c5d43b9cfe68c2d401a84647d19c10e (patch)
treea1f1874aa84850bddbebd2b0e0bfc3e1c77ce8c4 /src/mame/drivers/sun3.cpp
parent1f6f1bfd6cfb748d9c5e159d6bd014bab8d30944 (diff)
Cleanup and version bumpmame0175
Diffstat (limited to 'src/mame/drivers/sun3.cpp')
-rw-r--r--src/mame/drivers/sun3.cpp266
1 files changed, 133 insertions, 133 deletions
diff --git a/src/mame/drivers/sun3.cpp b/src/mame/drivers/sun3.cpp
index 4d198c29399..eb76ef1adbb 100644
--- a/src/mame/drivers/sun3.cpp
+++ b/src/mame/drivers/sun3.cpp
@@ -158,7 +158,7 @@
factor. Serial and keyboard ports. External RAM,
framebuffer, and SCSI/ethernet boards
available.
-
+
3/60 ROM breakpoints of interest
fefb104 - bus error test
fefb18e - interrupt test
@@ -194,20 +194,20 @@ fefc34a - start of mem_size, which queries ECC registers for each memory board
#define RS232B_TAG "rs232b"
// page table entry constants
-#define PM_VALID (0x80000000) // page is valid
-#define PM_WRITEMASK (0x40000000) // writable?
-#define PM_SYSMASK (0x20000000) // system use only?
-#define PM_CACHE (0x10000000) // cachable?
-#define PM_TYPEMASK (0x0c000000) // type mask
-#define PM_ACCESSED (0x02000000) // accessed flag
-#define PM_MODIFIED (0x01000000) // modified flag
-
-#define BE_FPENABLE (0x04) // FPU not enabled
-#define BE_FPBERR (0x08) // FPU encountered a bus error
-#define BE_VMEBERR (0x10) // VME encountered a bus error
-#define BE_TIMEOUT (0x20) // timeout - memory doesn't exist
-#define BE_PROTERR (0x40) // protection failed on MMU page lookup
-#define BE_INVALID (0x80) // invalid entry on MMU page lookup
+#define PM_VALID (0x80000000) // page is valid
+#define PM_WRITEMASK (0x40000000) // writable?
+#define PM_SYSMASK (0x20000000) // system use only?
+#define PM_CACHE (0x10000000) // cachable?
+#define PM_TYPEMASK (0x0c000000) // type mask
+#define PM_ACCESSED (0x02000000) // accessed flag
+#define PM_MODIFIED (0x01000000) // modified flag
+
+#define BE_FPENABLE (0x04) // FPU not enabled
+#define BE_FPBERR (0x08) // FPU encountered a bus error
+#define BE_VMEBERR (0x10) // VME encountered a bus error
+#define BE_TIMEOUT (0x20) // timeout - memory doesn't exist
+#define BE_PROTERR (0x40) // protection failed on MMU page lookup
+#define BE_INVALID (0x80) // invalid entry on MMU page lookup
class sun3_state : public driver_device
{
@@ -270,7 +270,7 @@ private:
UINT32 m_pagemap[4096];
UINT32 m_ram_size, m_ram_size_words;
bool m_bInBusErr;
-
+
UINT32 m_cache_tags[0x4000], m_cache_data[0x4000];
};
@@ -280,17 +280,17 @@ READ32_MEMBER( sun3_state::ram_r )
{
//printf("ECC testing, RAM read ofs %x\n", offset);
m_ecc[1] &= 0x00ffffff;
-
- if (m_ecc[2] == 0x01000000) // single-bit error test
+
+ if (m_ecc[2] == 0x01000000) // single-bit error test
{
- m_ecc[1] |= 0x8f000000; // put in the syndrome code the first ECC test wants
-
+ m_ecc[1] |= 0x8f000000; // put in the syndrome code the first ECC test wants
+
if (offset == 0)
{
return 0x80000000;
}
}
- else if (m_ecc[2] == 0x01000200) // double-bit error test
+ else if (m_ecc[2] == 0x01000200) // double-bit error test
{
m_ecc[1] |= 0xfc000000;
}
@@ -305,7 +305,7 @@ READ32_MEMBER( sun3_state::ram_r )
m_buserr = BE_TIMEOUT;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
- }
+ }
return 0xffffffff;
}
@@ -353,10 +353,10 @@ WRITE32_MEMBER( sun3_state::ram_w )
m_parregs[0] |= 0x0f<<24;
break;
}
-
+
// indicate parity interrupt
m_parregs[0] |= 0x80000000;
-
+
// and can we take that now?
if (m_parregs[0] & 0x40000000)
{
@@ -365,7 +365,7 @@ WRITE32_MEMBER( sun3_state::ram_w )
}
}
- if (offset < m_ram_size_words)
+ if (offset < m_ram_size_words)
{
COMBINE_DATA(&m_ram_ptr[offset]);
return;
@@ -384,60 +384,60 @@ WRITE32_MEMBER( sun3_state::ram_w )
READ32_MEMBER( sun3_state::tl_mmu_r )
{
UINT8 fc = m_maincpu->get_fc();
-
+
if ((fc == 3) && !space.debugger_access())
- {
+ {
int page;
-
+
switch (offset >> 26)
{
case 0: // IDPROM
//printf("sun3: Read IDPROM at %x (mask %08x)\n", offset, mem_mask);
return m_idprom_ptr[(offset*4)] << 24 | m_idprom_ptr[(offset*4)+1]<<16 | m_idprom_ptr[(offset*4)+2]<<8 | m_idprom_ptr[(offset*4)+3];
-
- case 1: // page map
+
+ case 1: // page map
page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4;
- page += (offset >> 11) & 0xf;
- //printf("sun3: Read page map at %x (entry %d)\n", offset<<1, page);
+ page += (offset >> 11) & 0xf;
+ //printf("sun3: Read page map at %x (entry %d)\n", offset<<1, page);
return m_pagemap[page];
-
+
case 2: // segment map
//printf("sun3: Read segment map at %x (entry %d, user ctx %d mask %x)\n", offset<<2, (offset & ~0x3c000000) >> 15, m_context & 7, mem_mask);
return m_segmap[m_context & 7][(offset >> 15) & 0x7ff]<<24;
-
+
case 3: // context reg
//printf("sun3: Read context reg\n");
return m_context<<24;
-
+
case 4: // enable reg
return m_enable;
-
+
case 5: // DVMA enable
return m_dvma_enable<<24;
-
+
case 6: // bus error
m_bInBusErr = false;
//printf("Reading bus error: %02x\n", m_buserr);
return m_buserr<<24;
-
+
case 7: // diagnostic reg
return 0;
-
+
case 8: // cache tags
//printf("sun3: read cache tags @ %x, PC = %x\n", offset, m_maincpu->pc);
return m_cache_tags[(offset & 0x3fff) >> 2];
-
+
case 9: // cache data
//printf("sun3: read cache data @ %x, PC = %x\n", offset, m_maincpu->pc);
return m_cache_data[(offset & 0x3fff)];
-
+
case 10: // flush cache
return 0xffffffff;
-
+
case 11: // block copy
printf("sun3: read block copy @ %x, PC = %x\n", offset, m_maincpu->pc);
return 0xffffffff;
-
+
case 15: // UART bypass
//printf("sun3: read UART bypass @ %x, PC = %x, mask = %08x\n", offset, m_maincpu->pc, mem_mask);
return 0xffffffff;
@@ -449,13 +449,13 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// debugger hack
if ((space.debugger_access()) && (offset >= (0xfef0000>>2)) && (offset <= (0xfefffff>>2)))
{
return m_rom_ptr[offset & 0x3fff];
}
-
+
// it's translation time
UINT8 pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff];
UINT32 entry = (pmeg << 4) + ((offset >> 11) & 0xf);
@@ -472,40 +472,40 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
m_bInBusErr = true;
return 0xffffffff;
}
-
+
m_pagemap[entry] |= PM_ACCESSED;
-
+
UINT32 tmp = (m_pagemap[entry] & 0x7ffff) << 11;
tmp |= (offset & 0x7ff);
-
+
//printf("pmeg %d, entry %d = %08x, virt %08x => tmp %08x\n", pmeg, entry, m_pagemap[entry], offset << 2, tmp);
-
- // if (!space.debugger_access())
+
+ // if (!space.debugger_access())
//printf("sun3: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, entry, m_pagemap[entry], offset<<2, fc);
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0 space
+ case 0: // type 0 space
return m_type0space->read32(space, tmp, mem_mask);
-
+
case 1: // type 1 space
// magic ROM bypass
if ((tmp >= (0x100000>>2)) && (tmp <= (0x10ffff>>2)))
{
- return m_rom_ptr[offset & 0x3fff];
+ return m_rom_ptr[offset & 0x3fff];
}
return m_type1space->read32(space, tmp, mem_mask);
-
- case 2: // type 2 space
+
+ case 2: // type 2 space
return m_type2space->read32(space, tmp, mem_mask);
-
- case 3: // type 3 space
+
+ case 3: // type 3 space
return m_type3space->read32(space, tmp, mem_mask);
}
}
else
{
-// if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
+// if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
m_buserr = BE_INVALID;
@@ -514,59 +514,59 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
}
if (!space.debugger_access()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc, offset>>15);
-
+
return 0xffffffff;
}
WRITE32_MEMBER( sun3_state::tl_mmu_w )
{
UINT8 fc = m_maincpu->get_fc();
-
+
//printf("sun3: Write %08x (FC %d, mask %08x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
-
- if (fc == 3) // control space
+
+ if (fc == 3) // control space
{
int page;
-
+
switch (offset >> 26)
{
- case 0: // IDPROM
+ case 0: // IDPROM
return;
-
- case 1: // page map fefaf32
+
+ case 1: // page map fefaf32
page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4;
//printf("context = %d, segment = %d, PMEG = %d, add = %d\n", m_context & 7, (offset >> 15) & 0x7ff, page, (offset >> 11) & 0xf);
page += (offset >> 11) & 0xf;
-
+
//printf("sun3: Write %04x to page map at %x (entry %d), ", data, offset<<2, page);
COMBINE_DATA(&m_pagemap[page]);
-
+
//printf("entry now %08x (adr %08x PC=%x mask %x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 13, m_maincpu->pc, mem_mask);
return;
-
+
case 2: // segment map
//printf("sun3: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x mask %x)\n", (data>>24) & 0xff, offset<<2, (offset & ~0x3c000000)>>15, m_context & 7, m_maincpu->pc, mem_mask);
m_segmap[m_context & 7][(offset >> 15) & 0x7ff] = (data>>24) & 0xff;
//printf("segment map[%d][%d] now %x\n", m_context & 7, (offset & ~0x3c000000) >> 15, m_segmap[m_context & 7][(offset & ~0x3c000000) >> 15] = (data>>24) & 0xff);
return;
-
+
case 3: // context reg
//printf("sun3: Write (%x) %x to context\n", data, data>>24);
m_context = data >> 24;
return;
-
+
case 4: // enable reg
//printf("sun3: Write %x to enable, PC=%x\n", data, m_maincpu->pc);
COMBINE_DATA(&m_enable);
return;
-
+
case 5: // DVMA enable
m_dvma_enable = data>>24;
return;
-
+
case 6: // bus error (read-only)
return;
-
+
case 7: // diagnostic reg
m_diag = data >> 24;
#if 0
@@ -574,9 +574,9 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
for (int i = 0; i < 8; i++)
{
if (m_diag & (1<<i))
- {
- printf(".");
- }
+ {
+ printf(".");
+ }
else
{
printf("*");
@@ -585,34 +585,34 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
printf("\n");
#endif
return;
-
+
case 8: // cache tags
//printf("sun3: %08x to cache tags @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask);
m_cache_tags[(offset & 0x3fff) >> 2] = data;
return;
-
+
case 9: // cache data
//printf("sun3: %08x to cache data @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask);
m_cache_data[(offset & 0x3fff)] = data;
return;
-
+
case 10: // flush cache
return;
-
+
case 11: // block copy
printf("sun3: %08x to block copy @ %x, PC = %x\n", data, offset, m_maincpu->pc);
return;
-
+
case 15: // UART bypass
//printf("sun3: %08x to UART bypass @ %x, PC = %x\n", data, offset, m_maincpu->pc);
return;
}
}
-
+
// it's translation time
UINT8 pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff];
UINT32 entry = (pmeg << 4) + ((offset >> 11) & 0xf);
-
+
if (m_pagemap[entry] & PM_VALID)
{
if ((!(m_pagemap[entry] & PM_WRITEMASK)) ||
@@ -625,9 +625,9 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
m_bInBusErr = true;
return;
}
-
+
m_pagemap[entry] |= (PM_ACCESSED | PM_MODIFIED);
-
+
UINT32 tmp = (m_pagemap[entry] & 0x7ffff) << 11;
tmp |= (offset & 0x7ff);
@@ -635,20 +635,20 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
switch ((m_pagemap[entry] >> 26) & 3)
{
- case 0: // type 0
+ case 0: // type 0
m_type0space->write32(space, tmp, data, mem_mask);
return;
-
+
case 1: // type 1
- //printf("write device space @ %x\n", tmp<<1);
+ //printf("write device space @ %x\n", tmp<<1);
m_type1space->write32(space, tmp, data, mem_mask);
return;
-
- case 2: // type 2
+
+ case 2: // type 2
m_type2space->write32(space, tmp, data, mem_mask);
return;
-
- case 3: // type 3
+
+ case 3: // type 3
m_type3space->write32(space, tmp, data, mem_mask);
return;
}
@@ -662,15 +662,15 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
m_bInBusErr = true;
return;
}
-
+
logerror("sun3: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<2);
}
READ32_MEMBER(sun3_state::parity_r)
{
UINT32 rv = m_parregs[offset];
-
- if (offset == 0) // clear interrupt if any
+
+ if (offset == 0) // clear interrupt if any
{
m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
m_parregs[offset] &= ~0x8f000000;
@@ -682,16 +682,16 @@ READ32_MEMBER(sun3_state::parity_r)
WRITE32_MEMBER(sun3_state::parity_w)
{
//printf("sun3: %08x to parity registers @ %x (mask %08x)\n", data, offset, mem_mask);
-
+
if (offset == 0)
{
m_parregs[0] &= 0x8f000000;
-
+
if ((m_parregs[0] & 0x80000000) && (data & 0x40000000))
{
m_maincpu->set_input_line(M68K_IRQ_7, ASSERT_LINE);
}
-
+
m_parregs[0] |= (data & 0x70000000);
}
else
@@ -707,7 +707,7 @@ ADDRESS_MAP_END
// type 0 device space
static ADDRESS_MAP_START(vmetype0space_map, AS_PROGRAM, 32, sun3_state)
AM_RANGE(0x00000000, 0x08ffffff) AM_READWRITE(ram_r, ram_w)
- AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM // not sure what's going on here (3/110)
+ AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM // not sure what's going on here (3/110)
AM_RANGE(0xff000000, 0xff03ffff) AM_RAM AM_SHARE("bw2_vram")
ADDRESS_MAP_END
@@ -720,7 +720,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(vmetype1space_map, AS_PROGRAM, 32, sun3_state)
AM_RANGE(0x00000000, 0x0000000f) AM_DEVREADWRITE8(SCC1_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
AM_RANGE(0x00020000, 0x0002000f) AM_DEVREADWRITE8(SCC2_TAG, z80scc_device, ba_cd_inv_r, ba_cd_inv_w, 0xff00ff00)
- AM_RANGE(0x00040000, 0x000407ff) AM_RAM AM_SHARE("nvram") // type 2816 parallel EEPROM
+ AM_RANGE(0x00040000, 0x000407ff) AM_RAM AM_SHARE("nvram") // type 2816 parallel EEPROM
AM_RANGE(0x00060000, 0x0006ffff) AM_READWRITE8(rtc7170_r, rtc7170_w, 0xffffffff)
AM_RANGE(0x00080000, 0x0008000f) AM_READWRITE(parity_r, parity_w)
AM_RANGE(0x000a0000, 0x000a0003) AM_READWRITE(irqctrl_r, irqctrl_w)
@@ -776,19 +776,19 @@ WRITE32_MEMBER(sun3_state::irqctrl_w)
READ8_MEMBER(sun3_state::rtc7170_r)
{
//printf("read 7170 @ %x, PC=%x\n", offset, m_maincpu->pc);
-
+
return 0xff;
}
WRITE8_MEMBER(sun3_state::rtc7170_w)
{
//printf("%02x to 7170 @ %x\n", data, offset);
-
+
if ((offset == 0x11) && (data == 0x1c))
{
if ((m_irqctrl & 0x21000000) == 0x21000000)
{
- m_maincpu->set_input_line(M68K_IRQ_5, ASSERT_LINE);
+ m_maincpu->set_input_line(M68K_IRQ_5, ASSERT_LINE);
}
}
}
@@ -799,27 +799,27 @@ READ32_MEMBER(sun3_state::ecc_r)
// fefc34a
int mbram = (m_ram_size / (1024*1024));
int beoff = (mbram / 32) * 0x10;
-
+
//printf("offset %x MB %d beoff %x\n", offset, mbram, beoff);
-
+
if (offset >= beoff)
{
m_buserr = BE_TIMEOUT;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}
-
+
UINT32 rv = m_ecc[offset & 0xf];
-
- if ((offset & 0xf) == 0) rv |= 0x06000000; // indicate each ECC board is 32MB, for 128MB total
-
+
+ if ((offset & 0xf) == 0) rv |= 0x06000000; // indicate each ECC board is 32MB, for 128MB total
+
return rv;
}
WRITE32_MEMBER(sun3_state::ecc_w)
{
//printf("%08x to ecc @ %x, mask %08x\n", data, offset, mem_mask);
-
+
offset &= 0xf;
m_ecc[offset] = data;
}
@@ -928,11 +928,11 @@ void sun3_state::machine_start()
m_ram_ptr = (UINT32 *)m_ram->pointer();
m_idprom_ptr = (UINT8 *)m_idprom->base();
m_ram_size = m_ram->size();
- m_ram_size_words = m_ram_size >> 2;
+ m_ram_size_words = m_ram_size >> 2;
}
void sun3_state::machine_reset()
-{
+{
m_maincpu->reset();
m_enable = 0;
m_buserr = 0;
@@ -953,7 +953,7 @@ static MACHINE_CONFIG_START( sun3, sun3_state )
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("4M")
MCFG_RAM_EXTRA_OPTIONS("6M,8M,12M,16M,20M,24M,28M,32M")
@@ -967,30 +967,30 @@ static MACHINE_CONFIG_START( sun3, sun3_state )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100))
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -1011,7 +1011,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( sun3_60, sun3 )
MCFG_CPU_REPLACE("maincpu", M68020, 20000000)
MCFG_CPU_PROGRAM_MAP(sun3_mem)
-
+
MCFG_SCREEN_MODIFY("bwtwo")
MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_16x11_update)
MCFG_SCREEN_SIZE(1600,1100)
@@ -1029,13 +1029,13 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( sun3200, sun3 )
MCFG_CPU_REPLACE("maincpu", M68020, 25000000)
MCFG_CPU_PROGRAM_MAP(sun3_mem)
-
+
MCFG_SCREEN_MODIFY("bwtwo")
MCFG_SCREEN_UPDATE_DRIVER(sun3_state, bw2_16x11_update)
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1600-1, 0, 1100-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_RAM_MODIFY(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("32M")
MCFG_RAM_EXTRA_OPTIONS("64M,96M,128M")
@@ -1051,11 +1051,11 @@ static MACHINE_CONFIG_START( sun3_50, sun3_state )
MCFG_SCREEN_SIZE(1600,1100)
MCFG_SCREEN_VISIBLE_AREA(0, 1152-1, 0, 900-1)
MCFG_SCREEN_REFRESH_RATE(72)
-
+
MCFG_NVRAM_ADD_0FILL("nvram")
-
+
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer", sun3_state, sun3_timer, attotime::from_hz(100))
-
+
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("4M")
MCFG_RAM_DEFAULT_VALUE(0x00)
@@ -1066,28 +1066,28 @@ static MACHINE_CONFIG_START( sun3_50, sun3_state )
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 1 device space
MCFG_DEVICE_ADD("type1", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype1space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 2 device space
MCFG_DEVICE_ADD("type2", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype2space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
// MMU Type 3 device space
MCFG_DEVICE_ADD("type3", ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(vmetype3space_map)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x80000000)
-
+
MCFG_SCC8530_ADD(SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_SCC8530_ADD(SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(RS232A_TAG, rs232_port_device, write_txd))
@@ -1133,7 +1133,7 @@ Sun 3/50 V2.8 Bootprom
ROMX_LOAD( "sun3_50_v1.6", 0x0000, 0x10000, CRC(8be20826) SHA1(2a4d73fcb7fe0f0c83eb0f4c91d957b7bf88b7ed), ROM_BIOS(5))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-50-idprom.bin", 0x000000, 0x000020, CRC(80610dbe) SHA1(0f37e31ed209b8905c5dc7c2663fa01a9b9baaba) )
+ ROM_LOAD( "sun3-50-idprom.bin", 0x000000, 0x000020, CRC(80610dbe) SHA1(0f37e31ed209b8905c5dc7c2663fa01a9b9baaba) )
ROM_END
ROM_START( sun3_60 )
@@ -1155,7 +1155,7 @@ Sun 3/60 V3.0.1 Bootprom
ROMX_LOAD( "sun_3.60v1.9", 0x0000, 0x10000, CRC(32b6d3a9) SHA1(307756ba5698611d51059881057f8086956ce895), ROM_BIOS(3))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-60-idprom.bin", 0x000000, 0x000020, CRC(117e766a) SHA1(f01547be0156bd4e06bbdee4c342d1b38c7646ae) )
+ ROM_LOAD( "sun3-60-idprom.bin", 0x000000, 0x000020, CRC(117e766a) SHA1(f01547be0156bd4e06bbdee4c342d1b38c7646ae) )
ROM_END
ROM_START( sun3_110 )
@@ -1228,7 +1228,7 @@ Sun 3/260/280 V3.0 Bootprom
ROMX_LOAD( "sun3_260_v2.6", 0x0000, 0x10000, CRC(e8b17951) SHA1(e1fdef42670a349d99b0eca9c50c8566b8bb7c56), ROM_BIOS(3))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-260-idprom.bin", 0x000000, 0x000020, CRC(d51794f3) SHA1(17930c773b6fe9a32819094ffaf69e5453d1ea4d) )
+ ROM_LOAD( "sun3-260-idprom.bin", 0x000000, 0x000020, CRC(d51794f3) SHA1(17930c773b6fe9a32819094ffaf69e5453d1ea4d) )
ROM_END
ROM_START( sun3_e )
@@ -1237,7 +1237,7 @@ ROM_START( sun3_e )
ROMX_LOAD( "sun3_e.32", 0x0000, 0x10000, CRC(acedde7e) SHA1(1ab6ec28f4365a613a5e326c34cb37585c3f0ecc), ROM_BIOS(1))
ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
- ROM_LOAD( "sun3-e-idprom.bin", 0x000000, 0x000020, CRC(d1a92116) SHA1(4836f3188f2c3dd5ba49ab66e0b55caa6b1b1791) )
+ ROM_LOAD( "sun3-e-idprom.bin", 0x000000, 0x000020, CRC(d1a92116) SHA1(4836f3188f2c3dd5ba49ab66e0b55caa6b1b1791) )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */