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author Olivier Galibert <galibert@pobox.com>2018-03-13 07:36:43 +0100
committer Olivier Galibert <galibert@pobox.com>2018-03-14 14:07:14 +0100
commit115bb9936c5cd3faf955d7eb1e251a94e4744b7b (patch)
treef0230f547f6c750f9974c61479eef28cbe4ad571 /src/mame/drivers/pgm2.cpp
parentf155992daab88ad024cec995428a67108218b51d (diff)
Address maps macros removal, pass 1 [O. Galibert]
Diffstat (limited to 'src/mame/drivers/pgm2.cpp')
-rw-r--r--src/mame/drivers/pgm2.cpp108
1 files changed, 56 insertions, 52 deletions
diff --git a/src/mame/drivers/pgm2.cpp b/src/mame/drivers/pgm2.cpp
index 5f4de7ad041..f92f37405a5 100644
--- a/src/mame/drivers/pgm2.cpp
+++ b/src/mame/drivers/pgm2.cpp
@@ -513,88 +513,92 @@ READ32_MEMBER(pgm2_state::pio_pdsr_r)
return (module_data_r() == ASSERT_LINE ? 1 : 0) << 8; // fpga data read and status (bit 7, must be 0)
}
-ADDRESS_MAP_START(pgm2_state::pgm2_map)
- AM_RANGE(0x00000000, 0x00003fff) AM_ROM //AM_REGION("user1", 0x00000) // internal ROM
+void pgm2_state::pgm2_map(address_map &map)
+{
+ map(0x00000000, 0x00003fff).rom(); //AM_REGION("user1", 0x00000) // internal ROM
- AM_RANGE(0x02000000, 0x0200ffff) AM_RAM AM_SHARE("sram") // 'battery ram' (in CPU?)
+ map(0x02000000, 0x0200ffff).ram().share("sram"); // 'battery ram' (in CPU?)
- AM_RANGE(0x03600000, 0x036bffff) AM_READWRITE(mcu_r, mcu_w)
+ map(0x03600000, 0x036bffff).rw(this, FUNC(pgm2_state::mcu_r), FUNC(pgm2_state::mcu_w));
- AM_RANGE(0x03900000, 0x03900003) AM_READ_PORT("INPUTS0")
- AM_RANGE(0x03a00000, 0x03a00003) AM_READ_PORT("INPUTS1")
+ map(0x03900000, 0x03900003).portr("INPUTS0");
+ map(0x03a00000, 0x03a00003).portr("INPUTS1");
- AM_RANGE(0x20000000, 0x2007ffff) AM_RAM AM_SHARE("mainram")
+ map(0x20000000, 0x2007ffff).ram().share("mainram");
- AM_RANGE(0x30000000, 0x30001fff) AM_RAM AM_SHARE("sp_videoram") // spriteram ('move' ram in test mode)
+ map(0x30000000, 0x30001fff).ram().share("sp_videoram"); // spriteram ('move' ram in test mode)
- AM_RANGE(0x30020000, 0x30021fff) AM_RAM_WRITE(bg_videoram_w) AM_SHARE("bg_videoram")
- AM_RANGE(0x30040000, 0x30045fff) AM_RAM_WRITE(fg_videoram_w) AM_SHARE("fg_videoram")
+ map(0x30020000, 0x30021fff).ram().w(this, FUNC(pgm2_state::bg_videoram_w)).share("bg_videoram");
+ map(0x30040000, 0x30045fff).ram().w(this, FUNC(pgm2_state::fg_videoram_w)).share("fg_videoram");
- AM_RANGE(0x30060000, 0x30063fff) AM_RAM_DEVWRITE("sp_palette", palette_device, write32) AM_SHARE("sp_palette")
+ map(0x30060000, 0x30063fff).ram().w(m_sp_palette, FUNC(palette_device::write32)).share("sp_palette");
- AM_RANGE(0x30080000, 0x30081fff) AM_RAM_DEVWRITE("bg_palette", palette_device, write32) AM_SHARE("bg_palette")
+ map(0x30080000, 0x30081fff).ram().w(m_bg_palette, FUNC(palette_device::write32)).share("bg_palette");
- AM_RANGE(0x300a0000, 0x300a07ff) AM_RAM_DEVWRITE("tx_palette", palette_device, write32) AM_SHARE("tx_palette")
+ map(0x300a0000, 0x300a07ff).ram().w(m_tx_palette, FUNC(palette_device::write32)).share("tx_palette");
- AM_RANGE(0x300c0000, 0x300c01ff) AM_RAM AM_SHARE("sp_zoom") // sprite zoom table - it uploads the same data 4x, maybe xshrink,xgrow,yshrink,ygrow or just redundant mirrors
+ map(0x300c0000, 0x300c01ff).ram().share("sp_zoom"); // sprite zoom table - it uploads the same data 4x, maybe xshrink,xgrow,yshrink,ygrow or just redundant mirrors
/* linescroll ram - it clears to 0x3bf on startup which is enough bytes for 240 lines if each rowscroll value was 8 bytes, but each row is 4,
so only half of this is used? or tx can do it too (unlikely, as orl2 writes 256 lines of data) maybe just bad mem check bounds on orleg2.
It reports pass even if it fails the first byte but if the first byte passes it attempts to test 0x10000 bytes, which is far too big so
what is the real size? */
- AM_RANGE(0x300e0000, 0x300e03ff) AM_RAM AM_SHARE("lineram") AM_MIRROR(0x000fc00)
+ map(0x300e0000, 0x300e03ff).ram().share("lineram").mirror(0x000fc00);
- AM_RANGE(0x30100000, 0x301000ff) AM_READWRITE8(shareram_r, shareram_w, 0x00ff00ff)
+ map(0x30100000, 0x301000ff).rw(this, FUNC(pgm2_state::shareram_r), FUNC(pgm2_state::shareram_w)).umask32(0x00ff00ff);
- AM_RANGE(0x30120000, 0x30120003) AM_RAM AM_SHARE("bgscroll") // scroll
- AM_RANGE(0x30120008, 0x3012000b) AM_RAM AM_SHARE("fgscroll")
- AM_RANGE(0x3012000c, 0x3012000f) AM_RAM AM_SHARE("vidmode")
- AM_RANGE(0x30120014, 0x30120017) AM_WRITE16(unk30120014_w, 0xffffffff)
- AM_RANGE(0x30120018, 0x3012001b) AM_WRITE16(vbl_ack_w, 0x0000ffff)
- AM_RANGE(0x30120030, 0x30120033) AM_WRITE16(share_bank_w, 0xffff0000)
- AM_RANGE(0x30120038, 0x3012003b) AM_WRITE(sprite_encryption_w)
+ map(0x30120000, 0x30120003).ram().share("bgscroll"); // scroll
+ map(0x30120008, 0x3012000b).ram().share("fgscroll");
+ map(0x3012000c, 0x3012000f).ram().share("vidmode");
+ map(0x30120014, 0x30120017).w(this, FUNC(pgm2_state::unk30120014_w));
+ map(0x30120018, 0x30120019).w(this, FUNC(pgm2_state::vbl_ack_w));
+ map(0x30120032, 0x30120033).w(this, FUNC(pgm2_state::share_bank_w));
+ map(0x30120038, 0x3012003b).w(this, FUNC(pgm2_state::sprite_encryption_w));
// there are other 0x301200xx regs
- AM_RANGE(0x40000000, 0x40000003) AM_DEVREAD8("ymz774", ymz774_device, read, 0xffffffff) AM_DEVWRITE8("ymz774", ymz774_device, write, 0xffffffff)
+ map(0x40000000, 0x40000003).r("ymz774", FUNC(ymz774_device::read)).w("ymz774", FUNC(ymz774_device::write));
// internal IGS036 - most of them is standard ATMEL peripherals followed by custom bits
// AM_RANGE(0xfffa0000, 0xfffa00ff) TC (Timer Counter) not used, mentioned in disabled / unused code
// AM_RANGE(0xffffec00, 0xffffec7f) SMC (Static Memory Controller)
// AM_RANGE(0xffffee00, 0xffffee57) MATRIX (Bus Matrix)
- AM_RANGE(0xfffff000, 0xfffff14b) AM_DEVICE("arm_aic", arm_aic_device, regs_map)
+ map(0xfffff000, 0xfffff14b).m(m_arm_aic, FUNC(arm_aic_device::regs_map));
// AM_RANGE(0xfffff200, 0xfffff247) DBGU (Debug Unit)
// AM_RANGE(0xfffff400, 0xfffff4af) PIO (Parallel Input Output Controller)
- AM_RANGE(0xfffff430, 0xfffff437) AM_WRITENOP // often
+ map(0xfffff430, 0xfffff437).nopw(); // often
// AM_RANGE(0xfffffd00, 0xfffffd0b) RSTC (Reset Controller)
// AM_RANGE(0xfffffd20, 0xfffffd2f) RTTC (Real Time Timer)
- AM_RANGE(0xfffffd28, 0xfffffd2b) AM_READ(rtc_r)
+ map(0xfffffd28, 0xfffffd2b).r(this, FUNC(pgm2_state::rtc_r));
// AM_RANGE(0xfffffd40, 0xfffffd4b) WDTC (Watch Dog Timer)
// custom IGS036 stuff starts here
- AM_RANGE(0xfffffa08, 0xfffffa0b) AM_WRITE(encryption_do_w) // after uploading encryption? table might actually send it or enable external ROM? when read bits0-1 called FUSE 0 and 1, must be 0
- AM_RANGE(0xfffffa0c, 0xfffffa0f) AM_READ(unk_startup_r) // written 0, then 0x1c, then expected to return (result&0x180)==0x180, then written 0x7c
- AM_RANGE(0xfffffc00, 0xfffffcff) AM_READWRITE8(encryption_r, encryption_w, 0xffffffff)
-ADDRESS_MAP_END
-
-
-ADDRESS_MAP_START(pgm2_state::pgm2_rom_map)
- AM_IMPORT_FROM(pgm2_map)
- AM_RANGE(0x10000000, 0x10ffffff) AM_ROM AM_REGION("user1", 0) // external ROM
-ADDRESS_MAP_END
-
-ADDRESS_MAP_START(pgm2_state::pgm2_ram_rom_map)
- AM_IMPORT_FROM(pgm2_map)
- AM_RANGE(0x10000000, 0x101fffff) AM_RAM AM_SHARE("romboard_ram") // we should also probably decrypt writes once the encryption is enabled, but the game never writes with it turned on anyway
- AM_RANGE(0x10200000, 0x103fffff) AM_ROM AM_REGION("user1", 0) // external ROM
-ADDRESS_MAP_END
-
-ADDRESS_MAP_START(pgm2_state::pgm2_module_rom_map)
- AM_IMPORT_FROM(pgm2_rom_map)
- AM_RANGE(0x10000000, 0x107fffff) AM_WRITE16(module_rom_w, 0xffffffff)
- AM_RANGE(0x10000000, 0x1000000f) AM_READ16(module_rom_r, 0xffffffff)
- AM_RANGE(0xfffff430, 0xfffff433) AM_WRITE(pio_sodr_w)
- AM_RANGE(0xfffff434, 0xfffff437) AM_WRITE(pio_codr_w)
- AM_RANGE(0xfffff43c, 0xfffff43f) AM_READ(pio_pdsr_r)
-ADDRESS_MAP_END
+ map(0xfffffa08, 0xfffffa0b).w(this, FUNC(pgm2_state::encryption_do_w)); // after uploading encryption? table might actually send it or enable external ROM? when read bits0-1 called FUSE 0 and 1, must be 0
+ map(0xfffffa0c, 0xfffffa0f).r(this, FUNC(pgm2_state::unk_startup_r)); // written 0, then 0x1c, then expected to return (result&0x180)==0x180, then written 0x7c
+ map(0xfffffc00, 0xfffffcff).rw(this, FUNC(pgm2_state::encryption_r), FUNC(pgm2_state::encryption_w));
+}
+
+
+void pgm2_state::pgm2_rom_map(address_map &map)
+{
+ pgm2_map(map);
+ map(0x10000000, 0x10ffffff).rom().region("user1", 0); // external ROM
+}
+
+void pgm2_state::pgm2_ram_rom_map(address_map &map)
+{
+ pgm2_map(map);
+ map(0x10000000, 0x101fffff).ram().share("romboard_ram"); // we should also probably decrypt writes once the encryption is enabled, but the game never writes with it turned on anyway
+ map(0x10200000, 0x103fffff).rom().region("user1", 0); // external ROM
+}
+
+void pgm2_state::pgm2_module_rom_map(address_map &map)
+{
+ pgm2_rom_map(map);
+ map(0x10000000, 0x107fffff).w(this, FUNC(pgm2_state::module_rom_w));
+ map(0x10000000, 0x1000000f).r(this, FUNC(pgm2_state::module_rom_r));
+ map(0xfffff430, 0xfffff433).w(this, FUNC(pgm2_state::pio_sodr_w));
+ map(0xfffff434, 0xfffff437).w(this, FUNC(pgm2_state::pio_codr_w));
+ map(0xfffff43c, 0xfffff43f).r(this, FUNC(pgm2_state::pio_pdsr_r));
+}
static INPUT_PORTS_START( pgm2 )
PORT_START("INPUTS0")