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author Patrick Mackinlay <pmackinlay@hotmail.com>2018-11-06 13:53:11 +0700
committer Patrick Mackinlay <pmackinlay@hotmail.com>2018-11-06 17:21:00 +0700
commitd2fe91f89c1daf5e0c8be41eea134f6cd560e3c3 (patch)
treeeca28d32f712c1558d893b03f17d32f0d5f6ec56 /src/mame/drivers/mips.cpp
parent8625e6d93b42f3ec89fbe07944e01b4036b7ab99 (diff)
r3000: modernize, add tlb support
* replaced memory accessors * implemented tlb and address translation * corrected exception vector logic * improved cache isolation behaviour * comments/formatting
Diffstat (limited to 'src/mame/drivers/mips.cpp')
-rw-r--r--src/mame/drivers/mips.cpp20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mame/drivers/mips.cpp b/src/mame/drivers/mips.cpp
index ed9b67ef0b5..cc55820f6e8 100644
--- a/src/mame/drivers/mips.cpp
+++ b/src/mame/drivers/mips.cpp
@@ -234,10 +234,10 @@ void rx2030_state::iop_io_map(address_map &map)
{
switch (data)
{
- case 0: LOG("cpu interrupt 0 asserted\n"); m_cpu->set_input_line(R3000_IRQ0, ASSERT_LINE); break;
- case 1: LOG("cpu interrupt 1 asserted\n"); m_cpu->set_input_line(R3000_IRQ1, ASSERT_LINE); break;
- case 2: LOG("cpu interrupt 2 asserted\n"); m_cpu->set_input_line(R3000_IRQ2, ASSERT_LINE); break;
- case 3: LOG("cpu interrupt 4 asserted\n"); m_cpu->set_input_line(R3000_IRQ4, ASSERT_LINE); break;
+ case 0: LOG("cpu interrupt 0 asserted\n"); m_cpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE); break;
+ case 1: LOG("cpu interrupt 1 asserted\n"); m_cpu->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE); break;
+ case 2: LOG("cpu interrupt 2 asserted\n"); m_cpu->set_input_line(INPUT_LINE_IRQ2, ASSERT_LINE); break;
+ case 3: LOG("cpu interrupt 4 asserted\n"); m_cpu->set_input_line(INPUT_LINE_IRQ4, ASSERT_LINE); break;
case 4:
if (m_cpu->suspended())
@@ -274,10 +274,10 @@ void rx2030_state::rx2030_map(address_map &map)
{
switch (data)
{
- case 0: LOG("cpu interrupt 0 cleared\n"); m_cpu->set_input_line(R3000_IRQ0, CLEAR_LINE); break;
- case 1: LOG("cpu interrupt 1 cleared\n"); m_cpu->set_input_line(R3000_IRQ1, CLEAR_LINE); break;
- case 2: LOG("cpu interrupt 2 cleared\n"); m_cpu->set_input_line(R3000_IRQ2, CLEAR_LINE); break;
- case 3: LOG("cpu interrupt 4 cleared\n"); m_cpu->set_input_line(R3000_IRQ4, CLEAR_LINE); break;
+ case 0: LOG("cpu interrupt 0 cleared\n"); m_cpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE); break;
+ case 1: LOG("cpu interrupt 1 cleared\n"); m_cpu->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE); break;
+ case 2: LOG("cpu interrupt 2 cleared\n"); m_cpu->set_input_line(INPUT_LINE_IRQ2, CLEAR_LINE); break;
+ case 3: LOG("cpu interrupt 4 cleared\n"); m_cpu->set_input_line(INPUT_LINE_IRQ4, CLEAR_LINE); break;
break;
case 4:
@@ -344,7 +344,7 @@ void rx2030_state::rx2030(machine_config &config)
{
R2000A(config, m_cpu, 33.333_MHz_XTAL / 2, 32768, 32768);
m_cpu->set_fpurev(0x0315); // 0x0315 == R2010A v1.5
- m_cpu->in_brcond0().set([this]() { logerror("brcond0 sampled (%s)\n", machine().describe_context()); return ASSERT_LINE; });
+ m_cpu->in_brcond<0>().set([this]() { logerror("brcond0 sampled (%s)\n", machine().describe_context()); return ASSERT_LINE; });
V50(config, m_iop, 20_MHz_XTAL / 2);
m_iop->set_addrmap(AS_PROGRAM, &rx2030_state::iop_program_map);
@@ -480,7 +480,7 @@ void rx2030_state::rs2030(machine_config &config)
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(pixclock, 1688, 248, 1528, 1066, 38, 1062);
m_screen->set_screen_update(FUNC(rx2030_state::screen_update));
- m_screen->screen_vblank().set_inputline(m_cpu, R3000_IRQ5);
+ m_screen->screen_vblank().set_inputline(m_cpu, INPUT_LINE_IRQ5);
BT458(config, m_ramdac, pixclock);
}