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author Miodrag Milanovic <mmicko@gmail.com>2012-04-11 14:10:06 +0000
committer Miodrag Milanovic <mmicko@gmail.com>2012-04-11 14:10:06 +0000
commit83f070ea3b3f354577f5fc2e54ca6196249eb477 (patch)
tree00d278b578e8f4cc3debe2203a92f96470e7066b /src/mame/drivers/luckgrln.c
parenta1ee0822d64c54a810231c19cd21bf2046cf5b88 (diff)
AM_BASE and AM_BASE_SIZE to AM_SHARE by request from Aaron (no whatsnew)
Diffstat (limited to 'src/mame/drivers/luckgrln.c')
-rw-r--r--src/mame/drivers/luckgrln.c78
1 files changed, 47 insertions, 31 deletions
diff --git a/src/mame/drivers/luckgrln.c b/src/mame/drivers/luckgrln.c
index c5aab11dbaa..045955b9873 100644
--- a/src/mame/drivers/luckgrln.c
+++ b/src/mame/drivers/luckgrln.c
@@ -87,28 +87,44 @@ class luckgrln_state : public driver_device
{
public:
luckgrln_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag) { }
+ : driver_device(mconfig, type, tag) ,
+ m_reel1_ram(*this, "reel1_ram"),
+ m_reel1_attr(*this, "reel1_attr"),
+ m_reel1_scroll(*this, "reel1_scroll"),
+ m_reel2_ram(*this, "reel2_ram"),
+ m_reel2_attr(*this, "reel2_attr"),
+ m_reel2_scroll(*this, "reel2_scroll"),
+ m_reel3_ram(*this, "reel3_ram"),
+ m_reel3_attr(*this, "reel3_attr"),
+ m_reel3_scroll(*this, "reel3_scroll"),
+ m_reel4_ram(*this, "reel4_ram"),
+ m_reel4_attr(*this, "reel4_attr"),
+ m_reel4_scroll(*this, "reel4_scroll"),
+ m_luck_vram1(*this, "luck_vram1"),
+ m_luck_vram2(*this, "luck_vram2"),
+ m_luck_vram3(*this, "luck_vram3"){ }
- UINT8 *m_luck_vram1;
- UINT8 *m_luck_vram2;
- UINT8 *m_luck_vram3;
UINT8 m_nmi_enable;
tilemap_t *m_reel1_tilemap;
tilemap_t *m_reel2_tilemap;
tilemap_t *m_reel3_tilemap;
tilemap_t *m_reel4_tilemap;
- UINT8* m_reel1_ram;
- UINT8* m_reel2_ram;
- UINT8* m_reel3_ram;
- UINT8* m_reel4_ram;
- UINT8* m_reel1_scroll;
- UINT8* m_reel2_scroll;
- UINT8* m_reel3_scroll;
- UINT8* m_reel4_scroll;
- UINT8* m_reel1_attr;
- UINT8* m_reel2_attr;
- UINT8* m_reel3_attr;
- UINT8* m_reel4_attr;
+ required_shared_ptr<UINT8> m_reel1_ram;
+ required_shared_ptr<UINT8> m_reel1_attr;
+ required_shared_ptr<UINT8> m_reel1_scroll;
+ required_shared_ptr<UINT8> m_reel2_ram;
+ required_shared_ptr<UINT8> m_reel2_attr;
+ required_shared_ptr<UINT8> m_reel2_scroll;
+ required_shared_ptr<UINT8> m_reel3_ram;
+ required_shared_ptr<UINT8> m_reel3_attr;
+ required_shared_ptr<UINT8> m_reel3_scroll;
+ required_shared_ptr<UINT8> m_reel4_ram;
+ required_shared_ptr<UINT8> m_reel4_attr;
+ required_shared_ptr<UINT8> m_reel4_scroll;
+ required_shared_ptr<UINT8> m_luck_vram1;
+ required_shared_ptr<UINT8> m_luck_vram2;
+ required_shared_ptr<UINT8> m_luck_vram3;
+
int m_palette_count;
UINT8 m_palette_ram[0x10000];
DECLARE_WRITE8_MEMBER(luckgrln_reel1_ram_w);
@@ -372,30 +388,30 @@ static ADDRESS_MAP_START( mainmap, AS_PROGRAM, 8, luckgrln_state )
AM_RANGE(0x10000, 0x1ffff) AM_ROM AM_REGION("rom_data",0x10000)
AM_RANGE(0x20000, 0x2ffff) AM_ROM AM_REGION("rom_data",0x00000)
- AM_RANGE(0x0c000, 0x0c1ff) AM_RAM_WRITE(luckgrln_reel1_ram_w) AM_BASE(m_reel1_ram) // only written to half way
- AM_RANGE(0x0c800, 0x0c9ff) AM_RAM_WRITE(luckgrln_reel1_attr_w) AM_BASE(m_reel1_attr)
- AM_RANGE(0x0d000, 0x0d03f) AM_RAM AM_BASE(m_reel1_scroll) AM_MIRROR(0x000c0)
+ AM_RANGE(0x0c000, 0x0c1ff) AM_RAM_WRITE(luckgrln_reel1_ram_w) AM_SHARE("reel1_ram") // only written to half way
+ AM_RANGE(0x0c800, 0x0c9ff) AM_RAM_WRITE(luckgrln_reel1_attr_w) AM_SHARE("reel1_attr")
+ AM_RANGE(0x0d000, 0x0d03f) AM_RAM AM_SHARE("reel1_scroll") AM_MIRROR(0x000c0)
- AM_RANGE(0x0c200, 0x0c3ff) AM_RAM_WRITE(luckgrln_reel2_ram_w) AM_BASE(m_reel2_ram)
- AM_RANGE(0x0ca00, 0x0cbff) AM_RAM_WRITE(luckgrln_reel2_attr_w) AM_BASE(m_reel2_attr)
- AM_RANGE(0x0d200, 0x0d23f) AM_RAM AM_BASE(m_reel2_scroll) AM_MIRROR(0x000c0)
+ AM_RANGE(0x0c200, 0x0c3ff) AM_RAM_WRITE(luckgrln_reel2_ram_w) AM_SHARE("reel2_ram")
+ AM_RANGE(0x0ca00, 0x0cbff) AM_RAM_WRITE(luckgrln_reel2_attr_w) AM_SHARE("reel2_attr")
+ AM_RANGE(0x0d200, 0x0d23f) AM_RAM AM_SHARE("reel2_scroll") AM_MIRROR(0x000c0)
- AM_RANGE(0x0c400, 0x0c5ff) AM_RAM_WRITE(luckgrln_reel3_ram_w ) AM_BASE(m_reel3_ram)
- AM_RANGE(0x0cc00, 0x0cdff) AM_RAM_WRITE(luckgrln_reel3_attr_w) AM_BASE(m_reel3_attr)
- AM_RANGE(0x0d400, 0x0d43f) AM_RAM AM_BASE(m_reel3_scroll) AM_MIRROR(0x000c0)
+ AM_RANGE(0x0c400, 0x0c5ff) AM_RAM_WRITE(luckgrln_reel3_ram_w ) AM_SHARE("reel3_ram")
+ AM_RANGE(0x0cc00, 0x0cdff) AM_RAM_WRITE(luckgrln_reel3_attr_w) AM_SHARE("reel3_attr")
+ AM_RANGE(0x0d400, 0x0d43f) AM_RAM AM_SHARE("reel3_scroll") AM_MIRROR(0x000c0)
- AM_RANGE(0x0c600, 0x0c7ff) AM_RAM_WRITE(luckgrln_reel4_ram_w ) AM_BASE(m_reel4_ram)
- AM_RANGE(0x0ce00, 0x0cfff) AM_RAM_WRITE(luckgrln_reel4_attr_w) AM_BASE(m_reel4_attr)
- AM_RANGE(0x0d600, 0x0d63f) AM_RAM AM_BASE(m_reel4_scroll)
+ AM_RANGE(0x0c600, 0x0c7ff) AM_RAM_WRITE(luckgrln_reel4_ram_w ) AM_SHARE("reel4_ram")
+ AM_RANGE(0x0ce00, 0x0cfff) AM_RAM_WRITE(luckgrln_reel4_attr_w) AM_SHARE("reel4_attr")
+ AM_RANGE(0x0d600, 0x0d63f) AM_RAM AM_SHARE("reel4_scroll")
// AM_RANGE(0x0d200, 0x0d2ff) AM_RAM
AM_RANGE(0x0d800, 0x0dfff) AM_RAM // nvram
- AM_RANGE(0x0e000, 0x0e7ff) AM_RAM AM_BASE(m_luck_vram1)
- AM_RANGE(0x0e800, 0x0efff) AM_RAM AM_BASE(m_luck_vram2)
- AM_RANGE(0x0f000, 0x0f7ff) AM_RAM AM_BASE(m_luck_vram3)
+ AM_RANGE(0x0e000, 0x0e7ff) AM_RAM AM_SHARE("luck_vram1")
+ AM_RANGE(0x0e800, 0x0efff) AM_RAM AM_SHARE("luck_vram2")
+ AM_RANGE(0x0f000, 0x0f7ff) AM_RAM AM_SHARE("luck_vram3")
AM_RANGE(0x0f800, 0x0ffff) AM_RAM