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author Ivan Vangelista <mesgnet@yahoo.it>2020-06-08 17:17:27 +0200
committer Ivan Vangelista <mesgnet@yahoo.it>2020-06-08 17:17:27 +0200
commit65d282d19ed5985d8e9925cdf5cb168e5f4aa09d (patch)
treecb0f2d561c22d547fe398839cbcfb36341512ad4 /src/mame/drivers/djmain.cpp
parentddc7ec4db26d6cc88330a96006643878dc42ce8c (diff)
drivers starting with c and d: completed read* and write* macros removal (nw)
Diffstat (limited to 'src/mame/drivers/djmain.cpp')
-rw-r--r--src/mame/drivers/djmain.cpp34
1 files changed, 17 insertions, 17 deletions
diff --git a/src/mame/drivers/djmain.cpp b/src/mame/drivers/djmain.cpp
index 07562467680..5cccc63dbfe 100644
--- a/src/mame/drivers/djmain.cpp
+++ b/src/mame/drivers/djmain.cpp
@@ -88,7 +88,7 @@ hard drive 3.5 adapter long 3.5 IDE cable 3.5 adapter PCB
*
*************************************/
-WRITE32_MEMBER(djmain_state::sndram_bank_w)
+void djmain_state::sndram_bank_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@@ -96,7 +96,7 @@ WRITE32_MEMBER(djmain_state::sndram_bank_w)
}
}
-READ32_MEMBER(djmain_state::sndram_r)
+uint32_t djmain_state::sndram_r(offs_t offset, uint32_t mem_mask)
{
uint32_t data = 0;
@@ -116,7 +116,7 @@ READ32_MEMBER(djmain_state::sndram_r)
return data;
}
-WRITE32_MEMBER(djmain_state::sndram_w)
+void djmain_state::sndram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
offset |= 0x20000 * m_sndram_bank;
if (ACCESSING_BITS_24_31)
@@ -135,7 +135,7 @@ WRITE32_MEMBER(djmain_state::sndram_w)
//---------
-READ32_MEMBER(djmain_state::obj_ctrl_r)
+uint32_t djmain_state::obj_ctrl_r(offs_t offset)
{
// read m_obj_regs[0x0c/4]: unknown
// read m_obj_regs[0x24/4]: unknown
@@ -143,14 +143,14 @@ READ32_MEMBER(djmain_state::obj_ctrl_r)
return m_obj_regs[offset];
}
-WRITE32_MEMBER(djmain_state::obj_ctrl_w)
+void djmain_state::obj_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// write m_obj_regs[0x28/4]: bank for rom readthrough
COMBINE_DATA(&m_obj_regs[offset]);
}
-READ32_MEMBER(djmain_state::obj_rom_r)
+uint32_t djmain_state::obj_rom_r(offs_t offset, uint32_t mem_mask)
{
uint8_t *mem8 = memregion("gfx1")->base();
int bank = m_obj_regs[0x28/4] >> 16;
@@ -170,7 +170,7 @@ READ32_MEMBER(djmain_state::obj_rom_r)
//---------
-WRITE32_MEMBER(djmain_state::v_ctrl_w)
+void djmain_state::v_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@@ -186,7 +186,7 @@ WRITE32_MEMBER(djmain_state::v_ctrl_w)
}
}
-READ32_MEMBER(djmain_state::v_rom_r)
+uint32_t djmain_state::v_rom_r(offs_t offset, uint32_t mem_mask)
{
uint8_t *mem8 = memregion("k056832")->base();
int bank = m_k056832->word_r(0x34/2);
@@ -207,19 +207,19 @@ READ32_MEMBER(djmain_state::v_rom_r)
//---------
-READ8_MEMBER(djmain_state::inp1_r)
+uint8_t djmain_state::inp1_r(offs_t offset)
{
static const char *const portnames[] = { "DSW3", "BTN3", "BTN2", "BTN1" };
return ioport(portnames[ offset & 0x03 ])->read();
}
-READ8_MEMBER(djmain_state::inp2_r)
+uint8_t djmain_state::inp2_r(offs_t offset)
{
static const char *const portnames[] = { "DSW1", "DSW2", "UNK2", "UNK1" };
return ioport(portnames[ offset & 0x03 ])->read();
}
-READ32_MEMBER(djmain_state::turntable_r)
+uint32_t djmain_state::turntable_r(offs_t offset, uint32_t mem_mask)
{
uint32_t result = 0;
@@ -244,7 +244,7 @@ READ32_MEMBER(djmain_state::turntable_r)
return result;
}
-WRITE32_MEMBER(djmain_state::turntable_select_w)
+void djmain_state::turntable_select_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_23)
m_turntable_select = (data >> 19) & 1;
@@ -284,7 +284,7 @@ WRITE32_MEMBER(djmain_state::turntable_select_w)
15: not used? (always low)
*/
-WRITE32_MEMBER(djmain_state::light_ctrl_1_w)
+void djmain_state::light_ctrl_1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@@ -295,7 +295,7 @@ WRITE32_MEMBER(djmain_state::light_ctrl_1_w)
}
}
-WRITE32_MEMBER(djmain_state::light_ctrl_2_w)
+void djmain_state::light_ctrl_2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@@ -312,17 +312,17 @@ WRITE32_MEMBER(djmain_state::light_ctrl_2_w)
// unknown ports :-(
-WRITE32_MEMBER(djmain_state::unknown590000_w)
+void djmain_state::unknown590000_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//logerror("%08X: unknown 590000 write %08X: %08X & %08X\n", m_maincpu->pcbase(), offset, data, mem_mask);
}
-WRITE32_MEMBER(djmain_state::unknown802000_w)
+void djmain_state::unknown802000_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//logerror("%08X: unknown 802000 write %08X: %08X & %08X\n", m_maincpu->pcbase(), offset, data, mem_mask);
}
-WRITE32_MEMBER(djmain_state::unknownc02000_w)
+void djmain_state::unknownc02000_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//logerror("%08X: unknown c02000 write %08X: %08X & %08X\n", m_maincpu->pcbase(), offset, data, mem_mask);
}