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author Lord-Nightmare <Lord-Nightmare@users.noreply.github.com>2017-03-07 12:15:56 -0500
committer Lord-Nightmare <Lord-Nightmare@users.noreply.github.com>2017-03-07 12:15:56 -0500
commit39164d40e2c9233037d0809a5c927c615cbc6a79 (patch)
treeaf7973abfd7d5174dd5d244baeb14e737befad8c /src/mame/drivers/cat.cpp
parente7aa308c302457b70d38d70cb68a71e85382ea8b (diff)
more long line cleanup (nw)
Diffstat (limited to 'src/mame/drivers/cat.cpp')
-rw-r--r--src/mame/drivers/cat.cpp22
1 files changed, 18 insertions, 4 deletions
diff --git a/src/mame/drivers/cat.cpp b/src/mame/drivers/cat.cpp
index 7b8cd8a35c9..75d7aab846b 100644
--- a/src/mame/drivers/cat.cpp
+++ b/src/mame/drivers/cat.cpp
@@ -431,7 +431,10 @@ WRITE16_MEMBER( cat_state::cat_video_control_w )
* Suffice to say, whatever bit combination 0b00011100000x does, it enables both horiz and vert sync and both are positive
*/
#ifdef DEBUG_VIDEO_CONTROL_W
- static const char *const regDest[16] = { "VSE (End of frame)", "VST (End of VSync)", "VSS (Start of VSync)", "VDE (Active Lines)", "unknown 620xxx", "unknown 628xxx", "unknown 630xxx", "unknown 638xxx", "HSE (end of horizontal line)", "HST (end of HSync)", "HSS (HSync Start)", "VOC (Video Control)", "unknown 660xxx", "unknown 668xxx", "unknown 670xxx", "unknown 678xxx" };
+ static const char *const regDest[16] = { "VSE (End of frame)", "VST (End of VSync)", "VSS (Start of VSync)", "VDE (Active Lines)",
+ "unknown 620xxx", "unknown 628xxx", "unknown 630xxx", "unknown 638xxx",
+ "HSE (end of horizontal line)", "HST (end of HSync)", "HSS (HSync Start)", "VOC (Video Control)",
+ "unknown 660xxx", "unknown 668xxx", "unknown 670xxx", "unknown 678xxx" };
fprintf(stderr,"Write to video chip address %06X; %02X -> register %s with data %04X\n", 0x600000+(offset<<1), offset&0xFF, regDest[(offset&0x3C000)>>14], data);
#endif
}
@@ -715,7 +718,9 @@ a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4
0 0 1 x x 0 * * * * * * * * * * * * * * * * * 1 R SVROM 0 ic6 (MASK ROM tc531000) [controlled via GA2 /SVCS0]
0 0 1 x x 1 * * * * * * * * * * * * * * * * * 0 O OPEN BUS (reads as 0x2e) [controlled via GA2 /SVCS1] *SEE BELOW*
0 0 1 x x 1 * * * * * * * * * * * * * * * * * 1 R SVROM 1 ic8 (not present on cat as sold, open bus reads as 0x80) [controlled via GA2 /SVCS1] *SEE BELOW*
- *NOTE: on Dwight E's user-made developer unit, two 128K SRAMS are mapped in place of the two entries immediately above!* (this involves some creative wiring+sockets); the official IAI 'shadow ram board' maps the ram to the A00000-A3FFFF area instead)
+ *NOTE: on Dwight E's user-made developer unit, two 128K SRAMS are mapped in place of the
+ two entries immediately above!* (this involves some creative wiring+sockets); the official
+ IAI 'shadow ram board' maps the ram to the A00000-A3FFFF area instead)
0 1 * * * * * * * * * * * * * * * * * * * * * * *BOTH GATE ARRAYS 1 and 2 DECODE THIS AREA; 2 DEALS WITH ADDR AND 1 WITH DATA/CAS/RAS*
0 1 0 x x a b * * * * * * * * * * * * * * * * * RW VIDEO/SYSTEM DRAM (ab: 00=row 0, ic26-29; 01=row 1, ic22-25; 10=row 2; ic18-21; 11=row 3; ic14-17)
*NOTE: DRAM rows 2 and 3 above are only usually populated in cat developer units!*
@@ -995,8 +1000,17 @@ WRITE_LINE_MEMBER(cat_state::cat_duart_txb) // memit sends stuff here; connects
/* mc68681 DUART Input pins:
* IP0: CTS [using the DUART builtin hardware-CTS feature?]
- * IP1: Centronics /ACK (pin 10) positive edge detect (IP1 changes state 0->1 or 1->0 on the rising edge of /ACK using a 74ls74a d-flipflop)
- * IP2: KTOBF (IP2 changes state 0->1 or 1->0 on the rising edge of KTOBF using a 74ls74a d-flipflop; KTOBF is a 6.5536ms-period squarewave generated by one of the gate arrays, I need to check with a scope to see whether it is a single spike/pulse every 6.5536ms or if from the gate array it inverts every 6.5536ms, documentation isn't 100% clear but I suspect the former) [uses the Delta IP2 state change detection feature to generate an interrupt; I'm not sure if IP2 is used as a counter clock source but given the beep frequency of the real unit I very much doubt it, 6.5536ms is too slow]
+ * IP1: Centronics /ACK (pin 10) positive edge detect (IP1 changes state 0->1
+ or 1->0 on the rising edge of /ACK using a 74ls74a d-flipflop)
+ * IP2: KTOBF (IP2 changes state 0->1 or 1->0 on the rising edge of KTOBF
+ using a 74ls74a d-flipflop; KTOBF is a 6.5536ms-period squarewave
+ generated by one of the gate arrays, I need to check with a scope to
+ see whether it is a single spike/pulse every 6.5536ms or if from the
+ gate array it inverts every 6.5536ms, documentation isn't 100% clear
+ but I suspect the former) [uses the Delta IP2 state change detection
+ feature to generate an interrupt; I'm not sure if IP2 is used as a
+ counter clock source but given the beep frequency of the real unit I
+ very much doubt it, 6.5536ms is too slow]
* IP3: RG ("ring" input)
* IP4: Centronics BUSY (pin 11), inverted
* IP5: DSR