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author AJR <ajrhacker@users.noreply.github.com>2018-03-03 21:30:05 -0500
committer AJR <ajrhacker@users.noreply.github.com>2018-03-03 21:30:05 -0500
commitbd37173bf6cdd23b8ec7fb28de39343c648c3598 (patch)
tree695ae904735c05e2d793233a8d04e396ea097015 /src/mame/drivers/calchase.cpp
parent0fde40b5e0d09deb3facd5e6b1ffe6a8386a2036 (diff)
lpci: De-staticize callbacks and remove both device parameters (nw)
Diffstat (limited to 'src/mame/drivers/calchase.cpp')
-rw-r--r--src/mame/drivers/calchase.cpp89
1 files changed, 47 insertions, 42 deletions
diff --git a/src/mame/drivers/calchase.cpp b/src/mame/drivers/calchase.cpp
index 29ce5813fe8..65d317f4d90 100644
--- a/src/mame/drivers/calchase.cpp
+++ b/src/mame/drivers/calchase.cpp
@@ -177,23 +177,30 @@ public:
void hostinv(machine_config &config);
void calchase_io(address_map &map);
void calchase_map(address_map &map);
+
+ uint8_t mtxc_config_r(int function, int reg);
+ void mtxc_config_w(int function, int reg, uint8_t data);
+ uint32_t intel82439tx_pci_r(int function, int reg, uint32_t mem_mask);
+ void intel82439tx_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
+ uint8_t piix4_config_r(int function, int reg);
+ void piix4_config_w(int function, int reg, uint8_t data);
+ uint32_t intel82371ab_pci_r(int function, int reg, uint32_t mem_mask);
+ void intel82371ab_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
};
// Intel 82439TX System Controller (MTXC)
// TODO: change with a VIA82C585VPX (North Bridge - APOLLO Chipset)
-static uint8_t mtxc_config_r(device_t *busdevice, device_t *device, int function, int reg)
+uint8_t calchase_state::mtxc_config_r(int function, int reg)
{
- calchase_state *state = busdevice->machine().driver_data<calchase_state>();
// osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
- return state->m_mtxc_config_reg[reg];
+ return m_mtxc_config_reg[reg];
}
-static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, uint8_t data)
+void calchase_state::mtxc_config_w(int function, int reg, uint8_t data)
{
- calchase_state *state = busdevice->machine().driver_data<calchase_state>();
-// osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
+// osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine().describe_context(), function, reg, data);
/*
memory banking with North Bridge:
@@ -208,16 +215,16 @@ static void mtxc_config_w(device_t *busdevice, device_t *device, int function, i
if (reg == 0x63)
{
if (data & 0x20) // enable RAM access to region 0xf0000 - 0xfffff
- state->membank("bios_bank")->set_base(state->m_bios_ram.get());
+ membank("bios_bank")->set_base(m_bios_ram.get());
else // disable RAM access (reads go to BIOS ROM)
- state->membank("bios_bank")->set_base(state->memregion("bios")->base() + 0x10000);
+ membank("bios_bank")->set_base(memregion("bios")->base() + 0x10000);
if (data & 0x80) // enable RAM access to region 0xe0000 - 0xeffff
- state->membank("bios_ext")->set_base(state->m_bios_ext_ram.get());
+ membank("bios_ext")->set_base(m_bios_ext_ram.get());
else
- state->membank("bios_ext")->set_base(state->memregion("bios")->base() + 0);
+ membank("bios_ext")->set_base(memregion("bios")->base() + 0);
}
- state->m_mtxc_config_reg[reg] = data;
+ m_mtxc_config_reg[reg] = data;
}
void calchase_state::intel82439tx_init()
@@ -230,7 +237,7 @@ void calchase_state::intel82439tx_init()
m_mtxc_config_reg[0x65] = 0x02;
}
-static uint32_t intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, uint32_t mem_mask)
+uint32_t calchase_state::intel82439tx_pci_r(int function, int reg, uint32_t mem_mask)
{
uint32_t r = 0;
@@ -239,61 +246,59 @@ static uint32_t intel82439tx_pci_r(device_t *busdevice, device_t *device, int fu
if (ACCESSING_BITS_24_31)
{
- r |= mtxc_config_r(busdevice, device, function, reg + 3) << 24;
+ r |= mtxc_config_r(function, reg + 3) << 24;
}
if (ACCESSING_BITS_16_23)
{
- r |= mtxc_config_r(busdevice, device, function, reg + 2) << 16;
+ r |= mtxc_config_r(function, reg + 2) << 16;
}
if (ACCESSING_BITS_8_15)
{
- r |= mtxc_config_r(busdevice, device, function, reg + 1) << 8;
+ r |= mtxc_config_r(function, reg + 1) << 8;
}
if (ACCESSING_BITS_0_7)
{
- r |= mtxc_config_r(busdevice, device, function, reg + 0) << 0;
+ r |= mtxc_config_r(function, reg + 0) << 0;
}
return r;
}
-static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int function, int reg, uint32_t data, uint32_t mem_mask)
+void calchase_state::intel82439tx_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_24_31)
{
- mtxc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
+ mtxc_config_w(function, reg + 3, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
- mtxc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
+ mtxc_config_w(function, reg + 2, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
- mtxc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
+ mtxc_config_w(function, reg + 1, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
- mtxc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
+ mtxc_config_w(function, reg + 0, (data >> 0) & 0xff);
}
}
// Intel 82371AB PCI-to-ISA / IDE bridge (PIIX4)
//TODO: change with VIA82C586B (South Bridge - APOLLO Chipset)
-static uint8_t piix4_config_r(device_t *busdevice, device_t *device, int function, int reg)
+uint8_t calchase_state::piix4_config_r(int function, int reg)
{
- calchase_state *state = busdevice->machine().driver_data<calchase_state>();
// osd_printf_debug("PIIX4: read %d, %02X\n", function, reg);
- return state->m_piix4_config_reg[function][reg];
+ return m_piix4_config_reg[function][reg];
}
-static void piix4_config_w(device_t *busdevice, device_t *device, int function, int reg, uint8_t data)
+void calchase_state::piix4_config_w(int function, int reg, uint8_t data)
{
- calchase_state *state = busdevice->machine().driver_data<calchase_state>();
-// osd_printf_debug("%s:PIIX4: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
- state->m_piix4_config_reg[function][reg] = data;
+// osd_printf_debug("%s:PIIX4: write %d, %02X, %02X\n", machine().describe_context(), function, reg, data);
+ m_piix4_config_reg[function][reg] = data;
}
-static uint32_t intel82371ab_pci_r(device_t *busdevice, device_t *device, int function, int reg, uint32_t mem_mask)
+uint32_t calchase_state::intel82371ab_pci_r(int function, int reg, uint32_t mem_mask)
{
uint32_t r = 0;
@@ -302,40 +307,40 @@ static uint32_t intel82371ab_pci_r(device_t *busdevice, device_t *device, int fu
if (ACCESSING_BITS_24_31)
{
- r |= piix4_config_r(busdevice, device, function, reg + 3) << 24;
+ r |= piix4_config_r(function, reg + 3) << 24;
}
if (ACCESSING_BITS_16_23)
{
- r |= piix4_config_r(busdevice, device, function, reg + 2) << 16;
+ r |= piix4_config_r(function, reg + 2) << 16;
}
if (ACCESSING_BITS_8_15)
{
- r |= piix4_config_r(busdevice, device, function, reg + 1) << 8;
+ r |= piix4_config_r(function, reg + 1) << 8;
}
if (ACCESSING_BITS_0_7)
{
- r |= piix4_config_r(busdevice, device, function, reg + 0) << 0;
+ r |= piix4_config_r(function, reg + 0) << 0;
}
return r;
}
-static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int function, int reg, uint32_t data, uint32_t mem_mask)
+void calchase_state::intel82371ab_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_24_31)
{
- piix4_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
+ piix4_config_w(function, reg + 3, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
- piix4_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
+ piix4_config_w(function, reg + 2, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
- piix4_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
+ piix4_config_w(function, reg + 1, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
- piix4_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
+ piix4_config_w(function, reg + 0, (data >> 0) & 0xff);
}
}
@@ -685,8 +690,8 @@ MACHINE_CONFIG_START(calchase_state::calchase)
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
- MCFG_PCI_BUS_LEGACY_DEVICE(0, nullptr, intel82439tx_pci_r, intel82439tx_pci_w)
- MCFG_PCI_BUS_LEGACY_DEVICE(7, nullptr, intel82371ab_pci_r, intel82371ab_pci_w)
+ MCFG_PCI_BUS_LEGACY_DEVICE(0, DEVICE_SELF, calchase_state, intel82439tx_pci_r, intel82439tx_pci_w)
+ MCFG_PCI_BUS_LEGACY_DEVICE(7, DEVICE_SELF, calchase_state, intel82371ab_pci_r, intel82371ab_pci_w)
/* video hardware */
pcvideo_trident_vga(config);
@@ -717,8 +722,8 @@ MACHINE_CONFIG_START(calchase_state::hostinv)
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
- MCFG_PCI_BUS_LEGACY_DEVICE(0, nullptr, intel82439tx_pci_r, intel82439tx_pci_w)
- MCFG_PCI_BUS_LEGACY_DEVICE(7, nullptr, intel82371ab_pci_r, intel82371ab_pci_w)
+ MCFG_PCI_BUS_LEGACY_DEVICE(0, DEVICE_SELF, calchase_state, intel82439tx_pci_r, intel82439tx_pci_w)
+ MCFG_PCI_BUS_LEGACY_DEVICE(7, DEVICE_SELF, calchase_state, intel82371ab_pci_r, intel82371ab_pci_w)
/* video hardware */
pcvideo_trident_vga(config);