diff options
author | 2011-09-10 16:24:41 +0000 | |
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committer | 2011-09-10 16:24:41 +0000 | |
commit | 7f2a5e0aca0973477ecffee0fc6e4964e2dfada4 (patch) | |
tree | 9d954224ae938127f2bb294aabe5558b7e1a752d /src/emu | |
parent | cf52707d1a5024ce4b28843691bfca271d5d29ed (diff) |
Added rol_ext, rol_indx, rol_indy to the HC11 CPU core [Angelo Salese]
Diffstat (limited to 'src/emu')
-rw-r--r-- | src/emu/cpu/mc68hc11/hc11ops.c | 69 | ||||
-rw-r--r-- | src/emu/cpu/mc68hc11/hc11ops.h | 6 |
2 files changed, 71 insertions, 4 deletions
diff --git a/src/emu/cpu/mc68hc11/hc11ops.c b/src/emu/cpu/mc68hc11/hc11ops.c index da0f9672696..d2e8b54dddc 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.c +++ b/src/emu/cpu/mc68hc11/hc11ops.c @@ -2569,7 +2569,7 @@ static void HC11OP(rola)(hc11_state *cpustate) static void HC11OP(rolb)(hc11_state *cpustate) { UINT8 c = (REG_B & 0x80); - UINT16 r = (REG_B << 1) | (cpustate->ccr & CC_C ? 1 : 0); + UINT16 r = ((REG_B & 0x7f) << 1) | (cpustate->ccr & CC_C ? 1 : 0); CLEAR_NZVC(cpustate); cpustate->ccr |= (c & 0x80) ? CC_C : 0; REG_B = (UINT16)(r); @@ -2585,6 +2585,73 @@ static void HC11OP(rolb)(hc11_state *cpustate) CYCLES(cpustate, 2); } +/* ROL EXT 0x79 */ +static void HC11OP(rol_ext)(hc11_state *cpustate) +{ + UINT16 adr = FETCH16(cpustate); + UINT8 r = READ8(cpustate, adr); + UINT8 c = (r & 0x80); + r = ((r & 0x7f) << 1) | (cpustate->ccr & CC_C ? 1 : 0); + CLEAR_NZVC(cpustate); + cpustate->ccr |= (c & 0x80) ? CC_C : 0; + SET_N8(r); + SET_Z8(r); + WRITE8(cpustate, adr, r); + + if (((cpustate->ccr & CC_N) == CC_N && (cpustate->ccr & CC_C) == 0) || + ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C) == CC_C)) + { + cpustate->ccr |= CC_V; + } + + CYCLES(cpustate, 6); +} + +/* ROL INDX 0x69 */ +static void HC11OP(rol_indx)(hc11_state *cpustate) +{ + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + UINT8 c = (i & 0x80); + i = ((i & 0x7f) << 1) | (cpustate->ccr & CC_C ? 1 : 0); + CLEAR_NZVC(cpustate); + cpustate->ccr |= (c & 0x80) ? CC_C : 0; + SET_N8(i); + SET_Z8(i); + WRITE8(cpustate, cpustate->ix + offset, i); + + if (((cpustate->ccr & CC_N) == CC_N && (cpustate->ccr & CC_C) == 0) || + ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C) == CC_C)) + { + cpustate->ccr |= CC_V; + } + + CYCLES(cpustate, 6); +} + +/* ROL INDY 0x18 0x69 */ +static void HC11OP(rol_indy)(hc11_state *cpustate) +{ + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); + UINT8 c = (i & 0x80); + i = ((i & 0x7f) << 1) | (cpustate->ccr & CC_C ? 1 : 0); + CLEAR_NZVC(cpustate); + cpustate->ccr |= (c & 0x80) ? CC_C : 0; + SET_N8(i); + SET_Z8(i); + WRITE8(cpustate, cpustate->iy + offset, i); + + if (((cpustate->ccr & CC_N) == CC_N && (cpustate->ccr & CC_C) == 0) || + ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C) == CC_C)) + { + cpustate->ccr |= CC_V; + } + + CYCLES(cpustate, 6); +} + + /* RORA 0x46 */ static void HC11OP(rora)(hc11_state *cpustate) { diff --git a/src/emu/cpu/mc68hc11/hc11ops.h b/src/emu/cpu/mc68hc11/hc11ops.h index 9e2a2f0044e..76b38a74640 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.h +++ b/src/emu/cpu/mc68hc11/hc11ops.h @@ -235,9 +235,9 @@ static const hc11_opcode_list_struct hc11_opcode_list[] = { 0x18, 0x38, HC11OP(puly) }, { 0, 0x49, HC11OP(rola) }, { 0, 0x59, HC11OP(rolb) }, -// { 0, 0x79, HC11OP(rol_ext) }, -// { 0, 0x69, HC11OP(rol_indx) }, -// { 0x18, 0x69, HC11OP(rol_indy) }, + { 0, 0x79, HC11OP(rol_ext) }, + { 0, 0x69, HC11OP(rol_indx) }, + { 0x18, 0x69, HC11OP(rol_indy) }, { 0, 0x46, HC11OP(rora) }, { 0, 0x56, HC11OP(rorb) }, // { 0, 0x76, HC11OP(ror_ext) }, |