diff options
author | Joakim Larsson Edström <joakimlarsson42@gmail.com> | 2015-07-11 21:10:00 +0200 |
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committer | Joakim Larsson Edström <joakimlarsson42@gmail.com> | 2015-07-20 18:07:07 +0200 |
commit | 338f3b14350164d118f973e43a103f973f0e0f66 (patch) | |
tree | f6536c920452a1b844173d32b154c11f482bb299 /src/emu/machine | |
parent | 27d9db181114af3ebe999c5420243603e997342b (diff) |
Compiles but produces printouts only when used from fccpu1 driver for needed registers only
Diffstat (limited to 'src/emu/machine')
-rw-r--r-- | src/emu/machine/68230pit.c | 144 | ||||
-rw-r--r-- | src/emu/machine/68230pit.h | 151 |
2 files changed, 109 insertions, 186 deletions
diff --git a/src/emu/machine/68230pit.c b/src/emu/machine/68230pit.c index 7ad79764bf5..161fe414490 100644 --- a/src/emu/machine/68230pit.c +++ b/src/emu/machine/68230pit.c @@ -4,41 +4,30 @@ Motorola MC68230 PI/T Parallell Interface and Timer +Revisions + 2015-07-15 JLE initial + +Todo + - Add clock and timers + - Add all missing registers + - Add configuration **********************************************************************/ /* - Registers ------------------------------------------------------------------------ - Offset Reset R/W - RS1-RS5 Name Value Reset Description ------------------------------------------------------------------------ - 0x00 RW PGCR No Port General Control register - 0x01 RW PSRR No Port Service Request register - 0x02 RW PADDR No Port A Data Direction register - 0x03 RW PBDDR No Port B Data Direction register - 0x04 RW PCDDR No Port C Data Direction register - 0x05 RW PIVR No Port Interrupt vector register - 0x06 RW PACR No Port A Control register - 0x07 RW PBCR No Port B Control register - 0x08 RW PADR May Port A Data register - 0x09 RW PBDR May Port B Data register - 0x0a RO PAAR No Port A Alternate register - 0x0b RO PBAR No Port B Alternate register - 0x0c RW PCDR No Port C Data register - 0x0d RW PSR May Port Status register - 0x0e n/a - 0x0f n/a - 0x10 RW TCR No Timer Control Register - 0x11 RW TIVR No Timer Interrupt Vector Register - 0x12 n/a - 0x13 RW CPRH No Counter Preload Register High - 0x14 RW CPRM No Counter Preload Register Middle - 0x15 RW CPRL No Counter Preload Register Low - 0x17 RO CNTRH No Counter Register High - 0x18 RO CNTRM No Counter Register Middle - 0x19 RO CNTRL No Counter Register Low - 0x1A RW TSR May Timer Status Register - +Force CPU-1 init sequence +0801EA 0E0000 W 0000 PGCR data_w: 0000 -> 0000 & 00ff +0801EA 0E0002 W 0000 PSRR data_w: 0000 -> 0001 & 00ff +0801EA 0E0004 W FFFF PADDR data_w: 00ff -> 0002 & 00ff +0801EA 0E0006 W 0000 PBDDR data_w: 0000 -> 0003 & 00ff +0801F0 0E000C W 6060 PACR data_w: 0060 -> 0006 & 00ff +0801F6 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff +0801FC 0E0000 W 3030 PGCR data_w: 0030 -> 0000 & 00ff +080202 0E000E W A8A8 PBCR data_w: 00a8 -> 0007 & 00ff +080210 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff + +Force CPU-1 after one keypress in terminal +081DC0 0E000C W 6868 PACR +081DC8 0E000C W 6060 PACR */ @@ -57,55 +46,66 @@ const device_type PIT68230 = &device_creator<pit68230_device>; //------------------------------------------------- pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, PIT68230, "68230 PI/T", tag, owner, clock, "pit68230", __FILE__), - m_internal_clock(0.0), - m_out0_cb(*this), - m_out1_cb(*this), - m_out2_cb(*this), - m_irq_cb(*this) + : device_t(mconfig, PIT68230, "Motorola 68230 PI/T", tag, owner, clock, "pit68230", __FILE__), + m_internal_clock(0.0) { - m_external_clock = 0.0; } -//------------------------------------------------- -// tick -//------------------------------------------------- - -void ptm6840_device::tick(int counter, int count) +void pit68230_device::device_start() { - if (counter == 2) - { - m_t3_scaler += count; - - if ( m_t3_scaler > m_t3_divisor - 1) - { - subtract_from_counter(counter, 1); - m_t3_scaler = 0; - } - } - else - { - subtract_from_counter(counter, count); - } + printf("PIT68230 device started\n"); } +void pit68230_device::device_reset() +{ + printf("PIT68230 device reseted\n"); + m_pgcr = 0; + m_psrr = 0; + m_paddr = 0; + m_pbddr = 0; + m_pacr = 0; + m_pbcr = 0; +} -//------------------------------------------------- -// set_clock - set clock status (0 or 1) -//------------------------------------------------- +WRITE8_MEMBER( pit68230_device::data_w ) +{ + printf("data_w: %04x -> ", data); + switch (offset) + { + case PIT_68230_PGCR: + printf("PGCR"); + m_pgcr = data; + break; + case PIT_68230_PSRR: + printf("PSRR"); + m_psrr = data; + break; + case PIT_68230_PADDR: + printf("PADDR"); + m_paddr = data; + break; + case PIT_68230_PBDDR: + printf("PBDDR"); + m_pbddr = data; + break; + case PIT_68230_PACR: + printf("PACR"); + m_pacr = data; + break; + case PIT_68230_PBCR: + printf("PBCR"); + m_pbcr = data; + break; + default: + printf("unhandled register %02x", offset); + } + printf("\n"); +} -void ptm6840_device::set_clock(int idx, int state) +READ8_MEMBER( pit68230_device::data_r ) { - m_clk[idx] = state; - - if (!(m_control_reg[idx] & 0x02)) - { - if (state) - { - tick(idx, 1); - } - } + printf("data_r: %04x & %04x\n", offset, mem_mask); + return (UINT8) 0; } -WRITE_LINE_MEMBER( pit68230_device::set_c1 ) { set_clock(state); } diff --git a/src/emu/machine/68230pit.h b/src/emu/machine/68230pit.h index 412b4af1979..84d5d667510 100644 --- a/src/emu/machine/68230pit.h +++ b/src/emu/machine/68230pit.h @@ -7,143 +7,66 @@ **********************************************************************/ #pragma once -#ifndef __68230PTI_H__ -#define __68230PTI_H__ +#ifndef __68230PIT_H__ +#define __68230PIT_H__ #include "emu.h" -#define PIT_68230_PGCR 0x00 /* Port General Control register */ -#define PIT_68230_PSRR 0x01 /* Port Service Request register */ -#define PIT_68230_PADDR 0x02 /* Port A Data Direction register */ -#define PIT_68230_PBDDR 0x03 /* Port B Data Direction register */ -#define PIT_68230_PCDDR 0x04 /* Port C Data Direction register */ -#define PIT_68230_PIVR 0x05 /* Port Interrupt vector register */ -#define PIT_68230_PACR 0x06 /* Port A Control register */ -#define PIT_68230_PBCR 0x07 /* Port B Control register */ -#define PIT_68230_PADR 0x08 /* Port A Data register */ -#define PIT_68230_PBDR 0x09 /* Port B Data register */ -#define PIT_68230_PAAR 0x0a /* Port A Alternate register */ -#define PIT_68230_PBAR 0x0b /* Port B Alternate register */ -#define PIT_68230_PCDR 0x0c /* Port C Data register */ -#define PIT_68230_PSR 0x0d /* Port Status register */ -#define PIT_68230_TCR 0x10 /* Timer Control Register */ -#define PIT_68230_TIVR 0x11 /* Timer Interrupt Vector Register */ -#define PIT_68230_CPRH 0x13 /* Counter Preload Register High */ -#define PIT_68230_CPRM 0x14 /* Counter Preload Register Middle */ -#define PIT_68230_CPRL 0x15 /* Counter Preload Register Low */ -#define PIT_68230_CNTRH 0x17 /* Counter Register High */ -#define PIT_68230_CNTRM 0x18 /* Counter Register Middle */ -#define PIT_68230_CNTRL 0x19 /* Counter Register Low */ -#define PIT_68230_TSR 0x1A /* Timer Status Register */ +/*----------------------------------------------------------------------- + Registers RS1-RS5 R/W Description +-------------------------------------------------------------------------*/ +#define PIT_68230_PGCR 0x00 /* RW Port General Control register */ +#define PIT_68230_PSRR 0x01 /* RW Port Service Request register */ +#define PIT_68230_PADDR 0x02 /* RW Port A Data Direction register */ +#define PIT_68230_PBDDR 0x03 /* RW Port B Data Direction register */ +#define PIT_68230_PCDDR 0x04 /* RW Port C Data Direction register */ +#define PIT_68230_PIVR 0x05 /* RW Port Interrupt vector register */ +#define PIT_68230_PACR 0x06 /* RW Port A Control register */ +#define PIT_68230_PBCR 0x07 /* RW Port B Control register */ +#define PIT_68230_PADR 0x08 /* RW Port A Data register */ +#define PIT_68230_PBDR 0x09 /* RW Port B Data register */ +#define PIT_68230_PAAR 0x0a /* RO Port A Alternate register */ +#define PIT_68230_PBAR 0x0b /* RO Port B Alternate register */ +#define PIT_68230_PCDR 0x0c /* RW Port C Data register */ +#define PIT_68230_PSR 0x0d /* RW Port Status register */ +#define PIT_68230_TCR 0x10 /* RW Timer Control Register */ +#define PIT_68230_TIVR 0x11 /* RW Timer Interrupt Vector Register */ +#define PIT_68230_CPRH 0x13 /* RW Counter Preload Register High */ +#define PIT_68230_CPRM 0x14 /* RW Counter Preload Register Middle */ +#define PIT_68230_CPRL 0x15 /* RW Counter Preload Register Low */ +#define PIT_68230_CNTRH 0x17 /* RO Counter Register High */ +#define PIT_68230_CNTRM 0x18 /* RO Counter Register Middle */ +#define PIT_68230_CNTRL 0x19 /* RO Counter Register Low */ +#define PIT_68230_TSR 0x1A /* RW Timer Status Register */ //************************************************************************** // TYPE DEFINITIONS //************************************************************************** - -// ======================> pit68230_device - class pit68230_device : public device_t { public: // construction/destruction pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - - static void set_internal_clock(device_t &device, double clock) { downcast<pit68230_device &>(device).m_internal_clock = clock; } - static void set_external_clock(device_t &device, double clock) { downcast<pit68230_device &>(device).m_external_clock = clock; } - - template<class _Object> static devcb_base &set_out0_callback(device_t &device, _Object object) { return downcast<pit68230_device &>(device).m_out0_cb.set_callback(object); } - template<class _Object> static devcb_base &set_out1_callback(device_t &device, _Object object) { return downcast<pit68230_device &>(device).m_out1_cb.set_callback(object); } - template<class _Object> static devcb_base &set_out2_callback(device_t &device, _Object object) { return downcast<pit68230_device &>(device).m_out2_cb.set_callback(object); } - template<class _Object> static devcb_base &set_irq_callback(device_t &device, _Object object) { return downcast<pit68230_device &>(device).m_irq_cb.set_callback(object); } - - int status(int clock) const { return m_enabled[clock]; } // get whether timer is enabled - int irq_state() const { return m_IRQ; } // get IRQ state - UINT16 count(int counter) const { return compute_counter(counter); } // get counter value - void set_ext_clock(int counter, double clock); // set clock frequency - int ext_clock(int counter) const { return m_external_clock[counter]; } // get clock frequency - - DECLARE_WRITE8_MEMBER( write ); - void write(offs_t offset, UINT8 data) { write(machine().driver_data()->generic_space(), offset, data); } - DECLARE_READ8_MEMBER( read ); - UINT8 read(offs_t offset) { return read(machine().driver_data()->generic_space(), offset); } - - void set_gate(int idx, int state); - DECLARE_WRITE_LINE_MEMBER( set_g1 ); - DECLARE_WRITE_LINE_MEMBER( set_g2 ); - DECLARE_WRITE_LINE_MEMBER( set_g3 ); - - void set_clock(int idx, int state); - DECLARE_WRITE_LINE_MEMBER( set_c1 ); - DECLARE_WRITE_LINE_MEMBER( set_c2 ); - DECLARE_WRITE_LINE_MEMBER( set_c3 ); - - void update_interrupts(); + DECLARE_WRITE8_MEMBER( data_w ); + DECLARE_READ8_MEMBER( data_r ); protected: // device-level overrides virtual void device_start(); virtual void device_reset(); - virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr); private: - void subtract_from_counter(int counter, int count); - void tick(int counter, int count); - void timeout(int idx); - - UINT16 compute_counter(int counter) const; - void reload_count(int idx); - -/* - enum - { - PTM_6840_CTRL1 = 0, - PTM_6840_CTRL2 = 1, - PTM_6840_STATUS = 1, - PTM_6840_MSBBUF1 = 2, - PTM_6840_LSB1 = 3, - PTM_6840_MSBBUF2 = 4, - PTM_6840_LSB2 = 5, - PTM_6840_MSBBUF3 = 6, - PTM_6840_LSB3 = 7, - }; -*/ double m_internal_clock; - double m_external_clock[3]; - - devcb_write8 m_out0_cb; - devcb_write8 m_out1_cb; - devcb_write8 m_out2_cb; - devcb_write_line m_irq_cb; // function called if IRQ line changes - - UINT8 m_control_reg[3]; - UINT8 m_output[3]; // Output states - UINT8 m_gate[3]; // Input gate states - UINT8 m_clk; // Clock states - UINT8 m_enabled[3]; - UINT8 m_mode[3]; - UINT8 m_fired[3]; - UINT8 m_t3_divisor; - UINT8 m_t3_scaler; - UINT8 m_IRQ; - UINT8 m_status_reg; - UINT8 m_status_read_since_int; - UINT8 m_lsb_buffer; - UINT8 m_msb_buffer; - - // Each PTM has 3 timers - emu_timer *m_timer[3]; - - UINT16 m_latch[3]; - UINT16 m_counter[3]; - - static const char *const opmode[]; + UINT8 m_pgcr; // Port General Control register + UINT8 m_psrr; // Port Service Request register + UINT8 m_paddr; // Port A Data Direction register + UINT8 m_pbddr; // Port B Data Direction register + UINT8 m_pacr; // Port A Control register + UINT8 m_pbcr; // Port B Control register }; // device type definition extern const device_type PIT68230; - - - -#endif // __68230PTI__ +#endif // __68230PIT__ |