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author | 2014-03-18 11:46:44 +0000 | |
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committer | 2014-03-18 11:46:44 +0000 | |
commit | f65e037141714318cfd32ecf988a7993f6cd9b3f (patch) | |
tree | 4c9a58e4b763733d3e2e80a409da026626978cc7 /src/emu/machine/ncr5380.h | |
parent | 15b2c80c62e9eddad3a6322fdef9c22039ce1eaa (diff) |
(MESS) Moved common machine and video chips to emu. (nw)
Diffstat (limited to 'src/emu/machine/ncr5380.h')
-rw-r--r-- | src/emu/machine/ncr5380.h | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/src/emu/machine/ncr5380.h b/src/emu/machine/ncr5380.h new file mode 100644 index 00000000000..24f33f9334f --- /dev/null +++ b/src/emu/machine/ncr5380.h @@ -0,0 +1,78 @@ +/* + * ncr5380.h SCSI controller + * + */ + +#ifndef _NCR5380_H_ +#define _NCR5380_H_ + +#include "machine/scsihle.h" + +struct NCR5380interface +{ + devcb_write_line m_irq_cb; /* irq callback */ +}; + +// 5380 registers +enum +{ + R5380_CURDATA = 0, // current SCSI data (read only) + R5380_OUTDATA = 0, // output data (write only) + R5380_INICOMMAND, // initiator command + R5380_MODE, // mode + R5380_TARGETCMD, // target command + R5380_SELENABLE, // select enable (write only) + R5380_BUSSTATUS = R5380_SELENABLE, // bus status (read only) + R5380_STARTDMA, // start DMA send (write only) + R5380_BUSANDSTAT = R5380_STARTDMA, // bus and status (read only) + R5380_DMATARGET, // DMA target (write only) + R5380_INPUTDATA = R5380_DMATARGET, // input data (read only) + R5380_DMAINIRECV, // DMA initiator receive (write only) + R5380_RESETPARITY = R5380_DMAINIRECV // reset parity/interrupt (read only) +}; + +// special Mac Plus registers - they implemented it weird +#define R5380_OUTDATA_DTACK (R5380_OUTDATA | 0x10) +#define R5380_CURDATA_DTACK (R5380_CURDATA | 0x10) + +// device stuff +#define MCFG_NCR5380_ADD(_tag, _clock, _intrf) \ + MCFG_DEVICE_ADD(_tag, NCR5380, _clock) \ + MCFG_DEVICE_CONFIG(_intrf) + +class ncr5380_device : public device_t, + public NCR5380interface +{ +public: + // construction/destruction + ncr5380_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + // our API + UINT8 ncr5380_read_reg(UINT32 offset); + void ncr5380_write_reg(UINT32 offset, UINT8 data); + + void ncr5380_read_data(int bytes, UINT8 *pData); + void ncr5380_write_data(int bytes, UINT8 *pData); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + virtual void device_stop(); + virtual void device_config_complete(); + +private: + scsihle_device *m_scsi_devices[8]; + + UINT8 m_5380_Registers[8]; + UINT8 m_last_id; + UINT8 m_5380_Command[32]; + INT32 m_cmd_ptr, m_d_ptr, m_d_limit, m_next_req_flag; + UINT8 m_5380_Data[512]; + devcb_resolved_write_line m_irq_func; +}; + +// device type definition +extern const device_type NCR5380; + +#endif |