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author Oliver Stöneberg <firewave@users.noreply.github.com>2014-08-10 03:43:22 +0000
committer Oliver Stöneberg <firewave@users.noreply.github.com>2014-08-10 03:43:22 +0000
commite440c631ed446b50984155ef95f508a88988cfaf (patch)
tree23bbfa8602a97a767f43b8a84f83745b918f178e /src/emu/machine/68307tmu.c
parentad4088d3c4d6bf866cce15c98b66a9dde173f96e (diff)
added assert for index out-of-bounds access with sc4dnda (nw)
Diffstat (limited to 'src/emu/machine/68307tmu.c')
-rw-r--r--src/emu/machine/68307tmu.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/emu/machine/68307tmu.c b/src/emu/machine/68307tmu.c
index 65b480aace2..ac64bf01614 100644
--- a/src/emu/machine/68307tmu.c
+++ b/src/emu/machine/68307tmu.c
@@ -155,6 +155,7 @@ UINT16 m68307_timer::read_tcn(UINT16 mem_mask, int which)
void m68307_timer::write_ter(UINT16 data, UINT16 mem_mask, int which)
{
+ assert(which >= 0 && which < ARRAY_LENGTH(singletimer));
m68307_single_timer* tptr = &singletimer[which];
if (data & 0x2) tptr->regs[m68307TIMER_TMR] &= ~0x2;
}
@@ -212,6 +213,7 @@ void m68307_timer::write_tmr(UINT16 data, UINT16 mem_mask, int which)
void m68307_timer::write_trr(UINT16 data, UINT16 mem_mask, int which)
{
+ assert(which >= 0 && which < ARRAY_LENGTH(singletimer));
m68307_single_timer* tptr = &singletimer[which];
COMBINE_DATA(&tptr->regs[m68307TIMER_TRR]);