diff options
author | 2013-01-11 07:32:46 +0000 | |
---|---|---|
committer | 2013-01-11 07:32:46 +0000 | |
commit | 0e19f641d3186cdbf51f8ca857e2b07ab95779c2 (patch) | |
tree | 234109de1123b13f217494af4b3f8efad346d5cc /src/emu/cpu/z8000 | |
parent | 111157ca09a9ff60fe4a9ba49173c315e94314fa (diff) |
Cleanups and version bumpmame0148
Diffstat (limited to 'src/emu/cpu/z8000')
-rw-r--r-- | src/emu/cpu/z8000/8000dasm.c | 21 | ||||
-rw-r--r-- | src/emu/cpu/z8000/makedab.c | 58 | ||||
-rw-r--r-- | src/emu/cpu/z8000/z8000.c | 828 | ||||
-rw-r--r-- | src/emu/cpu/z8000/z8000.h | 16 | ||||
-rw-r--r-- | src/emu/cpu/z8000/z8000cpu.h | 204 | ||||
-rw-r--r-- | src/emu/cpu/z8000/z8000ops.c | 1058 | ||||
-rw-r--r-- | src/emu/cpu/z8000/z8000tbl.c | 1055 |
7 files changed, 1619 insertions, 1621 deletions
diff --git a/src/emu/cpu/z8000/8000dasm.c b/src/emu/cpu/z8000/8000dasm.c index c3fc111235d..d88c4f8c862 100644 --- a/src/emu/cpu/z8000/8000dasm.c +++ b/src/emu/cpu/z8000/8000dasm.c @@ -48,9 +48,9 @@ #include "z8000.h" #include "z8000cpu.h" -static int n[16]; /* opcode nibbles */ -static int b[8]; /* opcode bytes */ -static int w[4]; /* opcode words */ +static int n[16]; /* opcode nibbles */ +static int b[8]; /* opcode bytes */ +static int w[4]; /* opcode words */ static void GET_OP(const UINT8 *oprom, int i, unsigned offset) { @@ -93,7 +93,7 @@ CPU_DISASSEMBLE( z8000 ) if(z8000_exec == NULL) z8000_init_tables(); - GET_OP(oprom, 0, new_pc - pc); + GET_OP(oprom, 0, new_pc - pc); new_pc += 2; switch (pc) { @@ -102,10 +102,10 @@ CPU_DISASSEMBLE( z8000 ) break; case 0x0002: dst += sprintf(dst, ".word #%%%04x ;RST FCW", w[0]); - break; + break; case 0x0004: dst += sprintf(dst, ".word #%%%04x ;RST PC", w[0]); - break; + break; default: o = &z8000_exec[w[0]]; if (o->size > 1) { GET_OP(oprom, 1, new_pc - pc); new_pc += 2; } @@ -220,11 +220,11 @@ CPU_DISASSEMBLE( z8000 ) case 0x1a8: dst += sprintf(dst, "outd "); break; case 0x1b0: dst += sprintf(dst, "soutd "); break; case 0x1b8: dst += sprintf(dst, "sotdr "); flags = DASMFLAG_STEP_OVER; break; - default: + default: dst += sprintf(dst, "unk(0x%x)", tmp); } - break; - case 'a': + break; + case 'a': /* address */ src++; i = *src++ - '0'; @@ -248,7 +248,7 @@ CPU_DISASSEMBLE( z8000 ) /* condition code */ src++; i = *src++ - '0'; - if (n[i] == 8) { /* always? */ + if (n[i] == 8) { /* always? */ /* skip following comma */ if (*src == ',') src++; @@ -346,4 +346,3 @@ CPU_DISASSEMBLE( z8000 ) } return (new_pc - pc) | flags | DASMFLAG_SUPPORTED; } - diff --git a/src/emu/cpu/z8000/makedab.c b/src/emu/cpu/z8000/makedab.c index e9ec0fe91c6..cebce6e42c5 100644 --- a/src/emu/cpu/z8000/makedab.c +++ b/src/emu/cpu/z8000/makedab.c @@ -1,8 +1,8 @@ #include <stdio.h> -#define CF 0x100 -#define HF 0x200 -#define DF 0x400 +#define CF 0x100 +#define HF 0x200 +#define DF 0x400 int dab[0x800]; @@ -36,52 +36,52 @@ int main(int ac, char **av) return 1; } - } - } + } + } - if (i & CF) { + if (i & CF) { if (i & HF) { dab[DF+i] = CF | ((i + 0x9a) & 0xff); } else { dab[DF+i] = CF | ((i + 0xa0) & 0xff); - } + } } else { if (i & HF) { dab[DF+i] = CF | ((i + 0xfa) & 0xff); - } else { + } else { dab[DF+i] = (i & 0xff); - } - } - } + } + } + } printf("/************************************************ \n"); - printf(" * Result table for Z8000 DAB instruction \n"); - printf(" * \n"); - printf(" * bits description \n"); - printf(" * ---------------------------------------------- \n"); - printf(" * 0..7 destination value \n"); - printf(" * 8 carry flag before \n"); - printf(" * 9 half carry flag before \n"); - printf(" * 10 D flag (0 add/adc, 1 sub/sbc) \n"); - printf(" * \n"); - printf(" * result description \n"); - printf(" * ---------------------------------------------- \n"); - printf(" * 0..7 result value \n"); - printf(" * 8 carry flag after \n"); - printf(" ************************************************/\n"); - printf("static const UINT16 Z8000_dab[0x800] = {\n"); - for (i = 0; i < 0x800; i++) { + printf(" * Result table for Z8000 DAB instruction \n"); + printf(" * \n"); + printf(" * bits description \n"); + printf(" * ---------------------------------------------- \n"); + printf(" * 0..7 destination value \n"); + printf(" * 8 carry flag before \n"); + printf(" * 9 half carry flag before \n"); + printf(" * 10 D flag (0 add/adc, 1 sub/sbc) \n"); + printf(" * \n"); + printf(" * result description \n"); + printf(" * ---------------------------------------------- \n"); + printf(" * 0..7 result value \n"); + printf(" * 8 carry flag after \n"); + printf(" ************************************************/\n"); + printf("static const UINT16 Z8000_dab[0x800] = {\n"); + for (i = 0; i < 0x800; i++) { if ((i & 0x3ff) == 0) { if (i & 0x400) printf("\t/* sub/sbc results */\n"); else printf("\t/* add/adc results */\n"); } - if ((i & 7) == 0) printf("\t"); + if ((i & 7) == 0) printf("\t"); printf("0x%03x,",dab[i]); if ((i & 7) == 7) printf("\n"); } printf("};\n"); - return 0; + return 0; } diff --git a/src/emu/cpu/z8000/z8000.c b/src/emu/cpu/z8000/z8000.c index 725b6b03f81..51814ab745a 100644 --- a/src/emu/cpu/z8000/z8000.c +++ b/src/emu/cpu/z8000/z8000.c @@ -54,34 +54,34 @@ #define VERBOSE 0 -#define LOG(x) do { if (VERBOSE) logerror x; } while (0) +#define LOG(x) do { if (VERBOSE) logerror x; } while (0) union z8000_reg_file { - UINT8 B[16]; /* RL0,RH0,RL1,RH1...RL7,RH7 */ - UINT16 W[16]; /* R0,R1,R2...R15 */ - UINT32 L[8]; /* RR0,RR2,RR4..RR14 */ - UINT64 Q[4]; /* RQ0,RQ4,..RQ12 */ + UINT8 B[16]; /* RL0,RH0,RL1,RH1...RL7,RH7 */ + UINT16 W[16]; /* R0,R1,R2...R15 */ + UINT32 L[8]; /* RR0,RR2,RR4..RR14 */ + UINT64 Q[4]; /* RQ0,RQ4,..RQ12 */ }; struct z8000_state { - UINT32 op[4]; /* opcodes/data of current instruction */ - UINT32 ppc; /* previous program counter */ - UINT32 pc; /* program counter */ - UINT16 psapseg; /* program status pointer, segment (Z8001 only) */ - UINT16 psapoff; /* program status pointer, offset */ - UINT16 fcw; /* flags and control word */ - UINT16 refresh; /* refresh timer/counter */ - UINT16 nspseg; /* system stack pointer, segment (Z8001 only) */ - UINT16 nspoff; /* system stack pointer, offset */ - UINT16 irq_req; /* CPU is halted, interrupt or trap request */ - UINT16 irq_srv; /* serviced interrupt request */ - UINT16 irq_vec; /* interrupt vector */ - unsigned int op_valid; /* bit field indicating if given op[] field is already initialized */ - z8000_reg_file regs;/* registers */ - int nmi_state; /* NMI line state */ - int irq_state[2]; /* IRQ line states (NVI, VI) */ + UINT32 op[4]; /* opcodes/data of current instruction */ + UINT32 ppc; /* previous program counter */ + UINT32 pc; /* program counter */ + UINT16 psapseg; /* program status pointer, segment (Z8001 only) */ + UINT16 psapoff; /* program status pointer, offset */ + UINT16 fcw; /* flags and control word */ + UINT16 refresh; /* refresh timer/counter */ + UINT16 nspseg; /* system stack pointer, segment (Z8001 only) */ + UINT16 nspoff; /* system stack pointer, offset */ + UINT16 irq_req; /* CPU is halted, interrupt or trap request */ + UINT16 irq_srv; /* serviced interrupt request */ + UINT16 irq_vec; /* interrupt vector */ + unsigned int op_valid; /* bit field indicating if given op[] field is already initialized */ + z8000_reg_file regs;/* registers */ + int nmi_state; /* NMI line state */ + int irq_state[2]; /* IRQ line states (NVI, VI) */ device_irq_acknowledge_callback irq_callback; legacy_cpu_device *device; address_space *program; @@ -129,83 +129,83 @@ INLINE UINT32 addr_sub(z8000_state *cpustate, UINT32 addr, UINT32 subtrahend) INLINE UINT16 RDOP(z8000_state *cpustate) { UINT16 res = cpustate->program->read_word(cpustate->pc); - cpustate->pc += 2; - return res; + cpustate->pc += 2; + return res; } INLINE UINT32 get_operand (z8000_state *cpustate, int opnum) { - int i; - assert (cpustate->device->type() == Z8001 || cpustate->device->type() == Z8002); + int i; + assert (cpustate->device->type() == Z8001 || cpustate->device->type() == Z8002); - for (i = 0; i < opnum; i++) - assert (cpustate->op_valid & (1 << i)); + for (i = 0; i < opnum; i++) + assert (cpustate->op_valid & (1 << i)); - if (! (cpustate->op_valid & (1 << opnum))) - { - cpustate->op[opnum] = cpustate->program->read_word(cpustate->pc); - cpustate->pc += 2; - cpustate->op_valid |= (1 << opnum); - } - return cpustate->op[opnum]; + if (! (cpustate->op_valid & (1 << opnum))) + { + cpustate->op[opnum] = cpustate->program->read_word(cpustate->pc); + cpustate->pc += 2; + cpustate->op_valid |= (1 << opnum); + } + return cpustate->op[opnum]; } INLINE UINT32 get_addr_operand (z8000_state *cpustate, int opnum) { - int i; - assert (cpustate->device->type() == Z8001 || cpustate->device->type() == Z8002); - - for (i = 0; i < opnum; i++) - assert (cpustate->op_valid & (1 << i)); - - if (! (cpustate->op_valid & (1 << opnum))) - { - UINT32 seg = cpustate->program->read_word(cpustate->pc); - cpustate->pc += 2; - if (segmented_mode(cpustate)) - { - if (seg & 0x8000) - { - cpustate->op[opnum] = ((seg & 0x7f00) << 8) | cpustate->program->read_word(cpustate->pc); - cpustate->pc += 2; - } - else - cpustate->op[opnum] = ((seg & 0x7f00) << 8) | (seg & 0xff); - } - else - cpustate->op[opnum] = seg; - cpustate->op_valid |= (1 << opnum); - } - return cpustate->op[opnum]; + int i; + assert (cpustate->device->type() == Z8001 || cpustate->device->type() == Z8002); + + for (i = 0; i < opnum; i++) + assert (cpustate->op_valid & (1 << i)); + + if (! (cpustate->op_valid & (1 << opnum))) + { + UINT32 seg = cpustate->program->read_word(cpustate->pc); + cpustate->pc += 2; + if (segmented_mode(cpustate)) + { + if (seg & 0x8000) + { + cpustate->op[opnum] = ((seg & 0x7f00) << 8) | cpustate->program->read_word(cpustate->pc); + cpustate->pc += 2; + } + else + cpustate->op[opnum] = ((seg & 0x7f00) << 8) | (seg & 0xff); + } + else + cpustate->op[opnum] = seg; + cpustate->op_valid |= (1 << opnum); + } + return cpustate->op[opnum]; } INLINE UINT32 get_raw_addr_operand (z8000_state *cpustate, int opnum) { - int i; - assert (cpustate->device->type() == Z8001 || cpustate->device->type() == Z8002); - - for (i = 0; i < opnum; i++) - assert (cpustate->op_valid & (1 << i)); - - if (! (cpustate->op_valid & (1 << opnum))) - { - UINT32 seg = cpustate->program->read_word(cpustate->pc); - cpustate->pc += 2; - if (segmented_mode(cpustate)) - { - if (seg & 0x8000) - { - cpustate->op[opnum] = (seg << 16) | cpustate->program->read_word(cpustate->pc); - cpustate->pc += 2; - } - else - cpustate->op[opnum] = (seg << 16) | (seg & 0xff); - } - else - cpustate->op[opnum] = seg; - cpustate->op_valid |= (1 << opnum); - } - return cpustate->op[opnum]; + int i; + assert (cpustate->device->type() == Z8001 || cpustate->device->type() == Z8002); + + for (i = 0; i < opnum; i++) + assert (cpustate->op_valid & (1 << i)); + + if (! (cpustate->op_valid & (1 << opnum))) + { + UINT32 seg = cpustate->program->read_word(cpustate->pc); + cpustate->pc += 2; + if (segmented_mode(cpustate)) + { + if (seg & 0x8000) + { + cpustate->op[opnum] = (seg << 16) | cpustate->program->read_word(cpustate->pc); + cpustate->pc += 2; + } + else + cpustate->op[opnum] = (seg << 16) | (seg & 0xff); + } + else + cpustate->op[opnum] = seg; + cpustate->op_valid |= (1 << opnum); + } + return cpustate->op[opnum]; } INLINE UINT32 adjust_addr_for_nonseg_mode(z8000_state *cpustate, UINT32 addr) @@ -230,11 +230,11 @@ INLINE UINT16 RDMEM_W(z8000_state *cpustate, address_spacenum spacenum, UINT32 a { addr = adjust_addr_for_nonseg_mode(cpustate, addr); addr &= ~1; - /* hack for m20 driver: BIOS accesses 0x7f0000 and expects a segmentation violation */ - if (addr >= 0x7f0000) { - cpustate->irq_req = Z8000_SEGTRAP; - return 0xffff; - } + /* hack for m20 driver: BIOS accesses 0x7f0000 and expects a segmentation violation */ + if (addr >= 0x7f0000) { + cpustate->irq_req = Z8000_SEGTRAP; + return 0xffff; + } if (spacenum == AS_PROGRAM) return cpustate->program->read_word(addr); else @@ -310,15 +310,15 @@ INLINE UINT16 RDPORT_W(z8000_state *cpustate, int mode, UINT16 addr) { if(mode == 0) { - if (cpustate->device->type() == Z8001) - { - return cpustate->io->read_word((UINT16)addr); - } - else - { - return cpustate->io->read_byte((UINT16)(addr)) + - (cpustate->io->read_byte((UINT16)(addr+1)) << 8); - } + if (cpustate->device->type() == Z8001) + { + return cpustate->io->read_word((UINT16)addr); + } + else + { + return cpustate->io->read_byte((UINT16)(addr)) + + (cpustate->io->read_byte((UINT16)(addr+1)) << 8); + } } else { @@ -331,32 +331,32 @@ INLINE void WRPORT_B(z8000_state *cpustate, int mode, UINT16 addr, UINT8 value) { if(mode == 0) { - cpustate->io->write_byte(addr,value); + cpustate->io->write_byte(addr,value); } else { /* how to handle MMU writes? */ - } + } } INLINE void WRPORT_W(z8000_state *cpustate, int mode, UINT16 addr, UINT16 value) { if(mode == 0) { - if (cpustate->device->type() == Z8001) - { - cpustate->io->write_word((UINT16)addr, value); - } - else - { - cpustate->io->write_byte((UINT16)(addr),value & 0xff); - cpustate->io->write_byte((UINT16)(addr+1),(value >> 8) & 0xff); - } + if (cpustate->device->type() == Z8001) + { + cpustate->io->write_word((UINT16)addr, value); + } + else + { + cpustate->io->write_byte((UINT16)(addr),value & 0xff); + cpustate->io->write_byte((UINT16)(addr+1),(value >> 8) & 0xff); + } } else { /* how to handle MMU writes? */ - } + } } INLINE void cycles(z8000_state *cpustate, int cycles) @@ -369,55 +369,55 @@ INLINE void cycles(z8000_state *cpustate, int cycles) INLINE void set_irq(z8000_state *cpustate, int type) { - switch ((type >> 8) & 255) - { - case Z8000_EPU >> 8: - if (cpustate->irq_srv >= Z8000_EPU) - return; - cpustate->irq_req = type; - break; - case Z8000_TRAP >> 8: - if (cpustate->irq_srv >= Z8000_TRAP) - return; /* double TRAP.. very bad :( */ - cpustate->irq_req = type; - break; - case Z8000_NMI >> 8: - if (cpustate->irq_srv >= Z8000_NMI) - return; /* no NMIs inside trap */ - cpustate->irq_req = type; - break; - case Z8000_SEGTRAP >> 8: - if (cpustate->irq_srv >= Z8000_SEGTRAP) - return; /* no SEGTRAPs inside NMI/TRAP */ - cpustate->irq_req = type; - break; - case Z8000_NVI >> 8: - if (cpustate->irq_srv >= Z8000_NVI) - return; /* no NVIs inside SEGTRAP/NMI/TRAP */ - cpustate->irq_req = type; - break; - case Z8000_VI >> 8: - if (cpustate->irq_srv >= Z8000_VI) - return; /* no VIs inside NVI/SEGTRAP/NMI/TRAP */ - cpustate->irq_req = type; - break; - case Z8000_SYSCALL >> 8: - LOG(("Z8K '%s' SYSCALL $%02x\n", cpustate->device->tag(), type & 0xff)); - cpustate->irq_req = type; - break; - default: - logerror("Z8000 invalid Cause_Interrupt %04x\n", type); - return; - } - /* set interrupt request flag, reset HALT flag */ - cpustate->irq_req = type & ~Z8000_HALT; + switch ((type >> 8) & 255) + { + case Z8000_EPU >> 8: + if (cpustate->irq_srv >= Z8000_EPU) + return; + cpustate->irq_req = type; + break; + case Z8000_TRAP >> 8: + if (cpustate->irq_srv >= Z8000_TRAP) + return; /* double TRAP.. very bad :( */ + cpustate->irq_req = type; + break; + case Z8000_NMI >> 8: + if (cpustate->irq_srv >= Z8000_NMI) + return; /* no NMIs inside trap */ + cpustate->irq_req = type; + break; + case Z8000_SEGTRAP >> 8: + if (cpustate->irq_srv >= Z8000_SEGTRAP) + return; /* no SEGTRAPs inside NMI/TRAP */ + cpustate->irq_req = type; + break; + case Z8000_NVI >> 8: + if (cpustate->irq_srv >= Z8000_NVI) + return; /* no NVIs inside SEGTRAP/NMI/TRAP */ + cpustate->irq_req = type; + break; + case Z8000_VI >> 8: + if (cpustate->irq_srv >= Z8000_VI) + return; /* no VIs inside NVI/SEGTRAP/NMI/TRAP */ + cpustate->irq_req = type; + break; + case Z8000_SYSCALL >> 8: + LOG(("Z8K '%s' SYSCALL $%02x\n", cpustate->device->tag(), type & 0xff)); + cpustate->irq_req = type; + break; + default: + logerror("Z8000 invalid Cause_Interrupt %04x\n", type); + return; + } + /* set interrupt request flag, reset HALT flag */ + cpustate->irq_req = type & ~Z8000_HALT; } #define PUSH_PC() do { \ if (cpustate->device->type() == Z8001) \ - PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); /* save current cpustate->pc */ \ - else \ - PUSHW(cpustate, SP, cpustate->pc); /* save current cpustate->pc */ \ + PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); /* save current cpustate->pc */ \ + else \ + PUSHW(cpustate, SP, cpustate->pc); /* save current cpustate->pc */ \ } while (0) #define GET_PC(VEC) (cpustate->device->type() == Z8001 ? segmented_addr(RDMEM_L(cpustate, AS_PROGRAM, VEC + 4)) : RDMEM_W(cpustate, AS_PROGRAM, VEC + 2)) @@ -426,116 +426,116 @@ if (cpustate->device->type() == Z8001) \ INLINE void Interrupt(z8000_state *cpustate) { - UINT16 fcw = cpustate->fcw; - - if (cpustate->irq_req & Z8000_NVI) - { - int type = (*cpustate->irq_callback)(cpustate->device, 0); - set_irq(cpustate, type | Z8000_NVI); - } - - if (cpustate->irq_req & Z8000_VI) - { - int type = (*cpustate->irq_callback)(cpustate->device, 1); - set_irq(cpustate, type | Z8000_VI); - } - - /* trap ? */ - if (cpustate->irq_req & Z8000_EPU) - { - CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ - PUSH_PC(); - PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ - PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ - cpustate->irq_srv = cpustate->irq_req; - cpustate->irq_req &= ~Z8000_EPU; - CHANGE_FCW(cpustate, GET_FCW(EPU)); - cpustate->pc = GET_PC(EPU); - LOG(("Z8K '%s' ext instr trap $%04x\n", cpustate->device->tag(), cpustate->pc)); - } - else - if (cpustate->irq_req & Z8000_TRAP) - { - CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ - PUSH_PC(); - PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ - PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ - cpustate->irq_srv = cpustate->irq_req; - cpustate->irq_req &= ~Z8000_TRAP; - CHANGE_FCW(cpustate, GET_FCW(TRAP)); - cpustate->pc = GET_PC(TRAP); - LOG(("Z8K '%s' priv instr trap $%04x\n", cpustate->device->tag(), cpustate->pc)); - } - else - if (cpustate->irq_req & Z8000_SYSCALL) - { - CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ - PUSH_PC(); - PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ - PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ - cpustate->irq_srv = cpustate->irq_req; - cpustate->irq_req &= ~Z8000_SYSCALL; - CHANGE_FCW(cpustate, GET_FCW(SYSCALL)); - cpustate->pc = GET_PC(SYSCALL); - LOG(("Z8K '%s' syscall $%04x\n", cpustate->device->tag(), cpustate->pc)); - } - else - if (cpustate->irq_req & Z8000_SEGTRAP) - { - CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ - PUSH_PC(); - PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ - PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ - cpustate->irq_srv = cpustate->irq_req; - cpustate->irq_req &= ~Z8000_SEGTRAP; - CHANGE_FCW(cpustate, GET_FCW(SEGTRAP)); - cpustate->pc = GET_PC(SEGTRAP); - LOG(("Z8K '%s' segtrap $%04x\n", cpustate->device->tag(), cpustate->pc)); - } - else - if (cpustate->irq_req & Z8000_NMI) - { - CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ - PUSH_PC(); - PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ - PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ - cpustate->irq_srv = cpustate->irq_req; - cpustate->pc = RDMEM_W(cpustate, AS_PROGRAM, NMI); - cpustate->irq_req &= ~Z8000_NMI; - CHANGE_FCW(cpustate, GET_FCW(NMI)); - cpustate->pc = GET_PC(NMI); - LOG(("Z8K '%s' NMI $%04x\n", cpustate->device->tag(), cpustate->pc)); - } - else - if ((cpustate->irq_req & Z8000_NVI) && (cpustate->fcw & F_NVIE)) - { - CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ - PUSH_PC(); - PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ - PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ - cpustate->irq_srv = cpustate->irq_req; - cpustate->pc = GET_PC(NVI); - cpustate->irq_req &= ~Z8000_NVI; - CHANGE_FCW(cpustate, GET_FCW(NVI)); - LOG(("Z8K '%s' NVI $%04x\n", cpustate->device->tag(), cpustate->pc)); - } - else - if ((cpustate->irq_req & Z8000_VI) && (cpustate->fcw & F_VIE)) - { - CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ - PUSH_PC(); - PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ - PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ - cpustate->irq_srv = cpustate->irq_req; + UINT16 fcw = cpustate->fcw; + + if (cpustate->irq_req & Z8000_NVI) + { + int type = (*cpustate->irq_callback)(cpustate->device, 0); + set_irq(cpustate, type | Z8000_NVI); + } + + if (cpustate->irq_req & Z8000_VI) + { + int type = (*cpustate->irq_callback)(cpustate->device, 1); + set_irq(cpustate, type | Z8000_VI); + } + + /* trap ? */ + if (cpustate->irq_req & Z8000_EPU) + { + CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ + PUSH_PC(); + PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ + PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ + cpustate->irq_srv = cpustate->irq_req; + cpustate->irq_req &= ~Z8000_EPU; + CHANGE_FCW(cpustate, GET_FCW(EPU)); + cpustate->pc = GET_PC(EPU); + LOG(("Z8K '%s' ext instr trap $%04x\n", cpustate->device->tag(), cpustate->pc)); + } + else + if (cpustate->irq_req & Z8000_TRAP) + { + CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ + PUSH_PC(); + PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ + PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ + cpustate->irq_srv = cpustate->irq_req; + cpustate->irq_req &= ~Z8000_TRAP; + CHANGE_FCW(cpustate, GET_FCW(TRAP)); + cpustate->pc = GET_PC(TRAP); + LOG(("Z8K '%s' priv instr trap $%04x\n", cpustate->device->tag(), cpustate->pc)); + } + else + if (cpustate->irq_req & Z8000_SYSCALL) + { + CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ + PUSH_PC(); + PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ + PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ + cpustate->irq_srv = cpustate->irq_req; + cpustate->irq_req &= ~Z8000_SYSCALL; + CHANGE_FCW(cpustate, GET_FCW(SYSCALL)); + cpustate->pc = GET_PC(SYSCALL); + LOG(("Z8K '%s' syscall $%04x\n", cpustate->device->tag(), cpustate->pc)); + } + else + if (cpustate->irq_req & Z8000_SEGTRAP) + { + CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ + PUSH_PC(); + PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ + PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ + cpustate->irq_srv = cpustate->irq_req; + cpustate->irq_req &= ~Z8000_SEGTRAP; + CHANGE_FCW(cpustate, GET_FCW(SEGTRAP)); + cpustate->pc = GET_PC(SEGTRAP); + LOG(("Z8K '%s' segtrap $%04x\n", cpustate->device->tag(), cpustate->pc)); + } + else + if (cpustate->irq_req & Z8000_NMI) + { + CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ + PUSH_PC(); + PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ + PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ + cpustate->irq_srv = cpustate->irq_req; + cpustate->pc = RDMEM_W(cpustate, AS_PROGRAM, NMI); + cpustate->irq_req &= ~Z8000_NMI; + CHANGE_FCW(cpustate, GET_FCW(NMI)); + cpustate->pc = GET_PC(NMI); + LOG(("Z8K '%s' NMI $%04x\n", cpustate->device->tag(), cpustate->pc)); + } + else + if ((cpustate->irq_req & Z8000_NVI) && (cpustate->fcw & F_NVIE)) + { + CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ + PUSH_PC(); + PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ + PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ + cpustate->irq_srv = cpustate->irq_req; + cpustate->pc = GET_PC(NVI); + cpustate->irq_req &= ~Z8000_NVI; + CHANGE_FCW(cpustate, GET_FCW(NVI)); + LOG(("Z8K '%s' NVI $%04x\n", cpustate->device->tag(), cpustate->pc)); + } + else + if ((cpustate->irq_req & Z8000_VI) && (cpustate->fcw & F_VIE)) + { + CHANGE_FCW(cpustate, fcw | F_S_N | F_SEG_Z8001);/* switch to segmented (on Z8001) system mode */ + PUSH_PC(); + PUSHW(cpustate, SP, fcw); /* save current cpustate->fcw */ + PUSHW(cpustate, SP, cpustate->irq_req); /* save interrupt/trap type tag */ + cpustate->irq_srv = cpustate->irq_req; if (cpustate->device->type() == Z8001) cpustate->pc = segmented_addr(RDMEM_L(cpustate, AS_PROGRAM, VEC00 + 4 * (cpustate->irq_req & 0xff))); else cpustate->pc = RDMEM_W(cpustate, AS_PROGRAM, VEC00 + 2 * (cpustate->irq_req & 0xff)); - cpustate->irq_req &= ~Z8000_VI; - CHANGE_FCW(cpustate, GET_FCW(VI)); - //printf ("z8k VI (vec 0x%x)\n", cpustate->irq_req & 0xff); - LOG(("Z8K '%s' VI [$%04x/$%04x] fcw $%04x, pc $%04x\n", cpustate->device->tag(), cpustate->irq_vec, VEC00 + (cpustate->device->type() == Z8001 ? 4 : 2) * (cpustate->irq_req & 0xff), cpustate->fcw, cpustate->pc)); - } + cpustate->irq_req &= ~Z8000_VI; + CHANGE_FCW(cpustate, GET_FCW(VI)); + //printf ("z8k VI (vec 0x%x)\n", cpustate->irq_req & 0xff); + LOG(("Z8K '%s' VI [$%04x/$%04x] fcw $%04x, pc $%04x\n", cpustate->device->tag(), cpustate->irq_vec, VEC00 + (cpustate->device->type() == Z8001 ? 4 : 2) * (cpustate->irq_req & 0xff), cpustate->fcw, cpustate->pc)); + } } static CPU_INIT( z8001 ) @@ -548,7 +548,7 @@ static CPU_INIT( z8001 ) cpustate->device = device; cpustate->program = &device->space(AS_PROGRAM); /* If the system decodes STn lines to distinguish between data and program memory fetches, - install the data space. If it doesn't, install the program memory into data memory space. */ + install the data space. If it doesn't, install the program memory into data memory space. */ if (device->has_space(AS_DATA)) cpustate->data = &device->space(AS_DATA); else @@ -571,7 +571,7 @@ static CPU_INIT( z8002 ) cpustate->device = device; cpustate->program = &device->space(AS_PROGRAM); /* If the system decodes STn lines to distinguish between data and program memory fetches, - install the data space. If it doesn't, install the program memory into data memory space. */ + install the data space. If it doesn't, install the program memory into data memory space. */ if (device->has_space(AS_DATA)) cpustate->data = &device->space(AS_DATA); else @@ -616,31 +616,31 @@ static CPU_EXECUTE( z8000 ) { z8000_state *cpustate = get_safe_token(device); - do - { - /* any interrupt request pending? */ - if (cpustate->irq_req) + do + { + /* any interrupt request pending? */ + if (cpustate->irq_req) Interrupt(cpustate); debugger_instruction_hook(device, cpustate->pc); if (cpustate->irq_req & Z8000_HALT) - { - cpustate->icount = 0; - } - else - { - Z8000_exec *exec; + { + cpustate->icount = 0; + } + else + { + Z8000_exec *exec; - cpustate->op[0] = RDOP(cpustate); - cpustate->op_valid = 1; - exec = &z8000_exec[cpustate->op[0]]; + cpustate->op[0] = RDOP(cpustate); + cpustate->op_valid = 1; + exec = &z8000_exec[cpustate->op[0]]; - cpustate->icount -= exec->cycles; - (*exec->opcode)(cpustate); - cpustate->op_valid = 0; - } - } while (cpustate->icount > 0); + cpustate->icount -= exec->cycles; + (*exec->opcode)(cpustate); + cpustate->op_valid = 0; + } + } while (cpustate->icount > 0); } @@ -651,11 +651,11 @@ static void set_irq_line(z8000_state *cpustate, int irqline, int state) if (cpustate->nmi_state == state) return; - cpustate->nmi_state = state; + cpustate->nmi_state = state; - if (state != CLEAR_LINE) + if (state != CLEAR_LINE) { - if (cpustate->irq_srv >= Z8000_NMI) /* no NMIs inside trap */ + if (cpustate->irq_srv >= Z8000_NMI) /* no NMIs inside trap */ return; cpustate->irq_req = Z8000_NMI; cpustate->irq_vec = NMI; @@ -675,7 +675,7 @@ static void set_irq_line(z8000_state *cpustate, int irqline, int state) { if (cpustate->fcw & F_NVIE) cpustate->irq_req |= Z8000_NVI; - } + } } else { @@ -706,36 +706,36 @@ static CPU_SET_INFO( z8002 ) switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break; - case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(cpustate, 1, info->i); break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; + case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break; + case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(cpustate, 1, info->i); break; - case CPUINFO_INT_PC: cpustate->pc = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_PC: cpustate->pc = info->i; break; + case CPUINFO_INT_PC: cpustate->pc = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_PC: cpustate->pc = info->i; break; case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + Z8000_NSP: cpustate->nspoff = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_FCW: cpustate->fcw = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_PSAP: cpustate->psapoff = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_REFRESH: cpustate->refresh = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_IRQ_REQ: cpustate->irq_req = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_IRQ_SRV: cpustate->irq_srv = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_IRQ_VEC: cpustate->irq_vec = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R0: cpustate->RW( 0) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R1: cpustate->RW( 1) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R2: cpustate->RW( 2) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R3: cpustate->RW( 3) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R4: cpustate->RW( 4) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R5: cpustate->RW( 5) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R6: cpustate->RW( 6) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R7: cpustate->RW( 7) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R8: cpustate->RW( 8) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R9: cpustate->RW( 9) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R10: cpustate->RW(10) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R11: cpustate->RW(11) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R12: cpustate->RW(12) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R13: cpustate->RW(13) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R14: cpustate->RW(14) = info->i; break; - case CPUINFO_INT_REGISTER + Z8000_R15: cpustate->RW(15) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_NSP: cpustate->nspoff = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_FCW: cpustate->fcw = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_PSAP: cpustate->psapoff = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_REFRESH: cpustate->refresh = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_IRQ_REQ: cpustate->irq_req = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_IRQ_SRV: cpustate->irq_srv = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_IRQ_VEC: cpustate->irq_vec = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R0: cpustate->RW( 0) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R1: cpustate->RW( 1) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R2: cpustate->RW( 2) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R3: cpustate->RW( 3) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R4: cpustate->RW( 4) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R5: cpustate->RW( 5) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R6: cpustate->RW( 6) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R7: cpustate->RW( 7) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R8: cpustate->RW( 8) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R9: cpustate->RW( 9) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R10: cpustate->RW(10) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R11: cpustate->RW(11) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R12: cpustate->RW(12) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R13: cpustate->RW(13) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R14: cpustate->RW(14) = info->i; break; + case CPUINFO_INT_REGISTER + Z8000_R15: cpustate->RW(15) = info->i; break; } } @@ -752,76 +752,76 @@ CPU_GET_INFO( z8002 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(z8000_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 6; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 2; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 744; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break; - case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_state[0]; break; /* NVI */ - case CPUINFO_INT_INPUT_STATE + 1: info->i = cpustate->irq_state[1]; break; /* VI */ - - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc; break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(z8000_state); break; + case CPUINFO_INT_INPUT_LINES: info->i = 2; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 6; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 2; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 744; break; + + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break; + case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_state[0]; break; /* NVI */ + case CPUINFO_INT_INPUT_STATE + 1: info->i = cpustate->irq_state[1]; break; /* VI */ + + case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc; break; case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + Z8000_PC: info->i = cpustate->pc; break; + case CPUINFO_INT_REGISTER + Z8000_PC: info->i = cpustate->pc; break; case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + Z8000_NSP: info->i = cpustate->nspoff; break; - case CPUINFO_INT_REGISTER + Z8000_FCW: info->i = cpustate->fcw; break; - case CPUINFO_INT_REGISTER + Z8000_PSAP: info->i = cpustate->psapoff; break; - case CPUINFO_INT_REGISTER + Z8000_REFRESH: info->i = cpustate->refresh; break; - case CPUINFO_INT_REGISTER + Z8000_IRQ_REQ: info->i = cpustate->irq_req; break; - case CPUINFO_INT_REGISTER + Z8000_IRQ_SRV: info->i = cpustate->irq_srv; break; - case CPUINFO_INT_REGISTER + Z8000_IRQ_VEC: info->i = cpustate->irq_vec; break; - case CPUINFO_INT_REGISTER + Z8000_R0: info->i = cpustate->RW( 0); break; - case CPUINFO_INT_REGISTER + Z8000_R1: info->i = cpustate->RW( 1); break; - case CPUINFO_INT_REGISTER + Z8000_R2: info->i = cpustate->RW( 2); break; - case CPUINFO_INT_REGISTER + Z8000_R3: info->i = cpustate->RW( 3); break; - case CPUINFO_INT_REGISTER + Z8000_R4: info->i = cpustate->RW( 4); break; - case CPUINFO_INT_REGISTER + Z8000_R5: info->i = cpustate->RW( 5); break; - case CPUINFO_INT_REGISTER + Z8000_R6: info->i = cpustate->RW( 6); break; - case CPUINFO_INT_REGISTER + Z8000_R7: info->i = cpustate->RW( 7); break; - case CPUINFO_INT_REGISTER + Z8000_R8: info->i = cpustate->RW( 8); break; - case CPUINFO_INT_REGISTER + Z8000_R9: info->i = cpustate->RW( 9); break; - case CPUINFO_INT_REGISTER + Z8000_R10: info->i = cpustate->RW(10); break; - case CPUINFO_INT_REGISTER + Z8000_R11: info->i = cpustate->RW(11); break; - case CPUINFO_INT_REGISTER + Z8000_R12: info->i = cpustate->RW(12); break; - case CPUINFO_INT_REGISTER + Z8000_R13: info->i = cpustate->RW(13); break; - case CPUINFO_INT_REGISTER + Z8000_R14: info->i = cpustate->RW(14); break; - case CPUINFO_INT_REGISTER + Z8000_R15: info->i = cpustate->RW(15); break; + case CPUINFO_INT_REGISTER + Z8000_NSP: info->i = cpustate->nspoff; break; + case CPUINFO_INT_REGISTER + Z8000_FCW: info->i = cpustate->fcw; break; + case CPUINFO_INT_REGISTER + Z8000_PSAP: info->i = cpustate->psapoff; break; + case CPUINFO_INT_REGISTER + Z8000_REFRESH: info->i = cpustate->refresh; break; + case CPUINFO_INT_REGISTER + Z8000_IRQ_REQ: info->i = cpustate->irq_req; break; + case CPUINFO_INT_REGISTER + Z8000_IRQ_SRV: info->i = cpustate->irq_srv; break; + case CPUINFO_INT_REGISTER + Z8000_IRQ_VEC: info->i = cpustate->irq_vec; break; + case CPUINFO_INT_REGISTER + Z8000_R0: info->i = cpustate->RW( 0); break; + case CPUINFO_INT_REGISTER + Z8000_R1: info->i = cpustate->RW( 1); break; + case CPUINFO_INT_REGISTER + Z8000_R2: info->i = cpustate->RW( 2); break; + case CPUINFO_INT_REGISTER + Z8000_R3: info->i = cpustate->RW( 3); break; + case CPUINFO_INT_REGISTER + Z8000_R4: info->i = cpustate->RW( 4); break; + case CPUINFO_INT_REGISTER + Z8000_R5: info->i = cpustate->RW( 5); break; + case CPUINFO_INT_REGISTER + Z8000_R6: info->i = cpustate->RW( 6); break; + case CPUINFO_INT_REGISTER + Z8000_R7: info->i = cpustate->RW( 7); break; + case CPUINFO_INT_REGISTER + Z8000_R8: info->i = cpustate->RW( 8); break; + case CPUINFO_INT_REGISTER + Z8000_R9: info->i = cpustate->RW( 9); break; + case CPUINFO_INT_REGISTER + Z8000_R10: info->i = cpustate->RW(10); break; + case CPUINFO_INT_REGISTER + Z8000_R11: info->i = cpustate->RW(11); break; + case CPUINFO_INT_REGISTER + Z8000_R12: info->i = cpustate->RW(12); break; + case CPUINFO_INT_REGISTER + Z8000_R13: info->i = cpustate->RW(13); break; + case CPUINFO_INT_REGISTER + Z8000_R14: info->i = cpustate->RW(14); break; + case CPUINFO_INT_REGISTER + Z8000_R15: info->i = cpustate->RW(15); break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(z8002); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(z8002); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(z8002); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(z8000); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(z8000); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(z8000);break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(z8002); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(z8002); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(z8002); break; + case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(z8000); break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(z8000); break; + case CPUINFO_FCT_BURN: info->burn = NULL; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(z8000);break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "Z8002"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Zilog Z8000"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.1"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break; + case CPUINFO_STR_NAME: strcpy(info->s, "Z8002"); break; + case CPUINFO_STR_FAMILY: strcpy(info->s, "Zilog Z8000"); break; + case CPUINFO_STR_VERSION: strcpy(info->s, "1.1"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break; case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c", @@ -841,32 +841,32 @@ CPU_GET_INFO( z8002 ) cpustate->fcw & 0x0004 ? 'H':'.', cpustate->fcw & 0x0002 ? '?':'.', cpustate->fcw & 0x0001 ? '?':'.'); - break; - - case CPUINFO_STR_REGISTER + Z8000_PC: sprintf(info->s, "pc :%08X", cpustate->pc); break; - case CPUINFO_STR_REGISTER + Z8000_NSP: sprintf(info->s, "SP :%04X", cpustate->nspoff); break; - case CPUINFO_STR_REGISTER + Z8000_FCW: sprintf(info->s, "fcw:%04X", cpustate->fcw); break; - case CPUINFO_STR_REGISTER + Z8000_PSAP: sprintf(info->s, "psapoff:%04X", cpustate->psapoff); break; - case CPUINFO_STR_REGISTER + Z8000_REFRESH: sprintf(info->s, "REFR:%04X", cpustate->refresh); break; - case CPUINFO_STR_REGISTER + Z8000_IRQ_REQ: sprintf(info->s, "IRQR:%04X", cpustate->irq_req); break; - case CPUINFO_STR_REGISTER + Z8000_IRQ_SRV: sprintf(info->s, "IRQS:%04X", cpustate->irq_srv); break; - case CPUINFO_STR_REGISTER + Z8000_IRQ_VEC: sprintf(info->s, "IRQV:%04X", cpustate->irq_vec); break; - case CPUINFO_STR_REGISTER + Z8000_R0: sprintf(info->s, "R0 :%04X", cpustate->RW(0)); break; - case CPUINFO_STR_REGISTER + Z8000_R1: sprintf(info->s, "R1 :%04X", cpustate->RW(1)); break; - case CPUINFO_STR_REGISTER + Z8000_R2: sprintf(info->s, "R2 :%04X", cpustate->RW(2)); break; - case CPUINFO_STR_REGISTER + Z8000_R3: sprintf(info->s, "R3 :%04X", cpustate->RW(3)); break; - case CPUINFO_STR_REGISTER + Z8000_R4: sprintf(info->s, "R4 :%04X", cpustate->RW(4)); break; - case CPUINFO_STR_REGISTER + Z8000_R5: sprintf(info->s, "R5 :%04X", cpustate->RW(5)); break; - case CPUINFO_STR_REGISTER + Z8000_R6: sprintf(info->s, "R6 :%04X", cpustate->RW(6)); break; - case CPUINFO_STR_REGISTER + Z8000_R7: sprintf(info->s, "R7 :%04X", cpustate->RW(7)); break; - case CPUINFO_STR_REGISTER + Z8000_R8: sprintf(info->s, "R8 :%04X", cpustate->RW(8)); break; - case CPUINFO_STR_REGISTER + Z8000_R9: sprintf(info->s, "R9 :%04X", cpustate->RW(9)); break; - case CPUINFO_STR_REGISTER + Z8000_R10: sprintf(info->s, "R10:%04X", cpustate->RW(10)); break; - case CPUINFO_STR_REGISTER + Z8000_R11: sprintf(info->s, "R11:%04X", cpustate->RW(11)); break; - case CPUINFO_STR_REGISTER + Z8000_R12: sprintf(info->s, "R12:%04X", cpustate->RW(12)); break; - case CPUINFO_STR_REGISTER + Z8000_R13: sprintf(info->s, "R13:%04X", cpustate->RW(13)); break; - case CPUINFO_STR_REGISTER + Z8000_R14: sprintf(info->s, "R14:%04X", cpustate->RW(14)); break; - case CPUINFO_STR_REGISTER + Z8000_R15: sprintf(info->s, "R15:%04X", cpustate->RW(15)); break; + break; + + case CPUINFO_STR_REGISTER + Z8000_PC: sprintf(info->s, "pc :%08X", cpustate->pc); break; + case CPUINFO_STR_REGISTER + Z8000_NSP: sprintf(info->s, "SP :%04X", cpustate->nspoff); break; + case CPUINFO_STR_REGISTER + Z8000_FCW: sprintf(info->s, "fcw:%04X", cpustate->fcw); break; + case CPUINFO_STR_REGISTER + Z8000_PSAP: sprintf(info->s, "psapoff:%04X", cpustate->psapoff); break; + case CPUINFO_STR_REGISTER + Z8000_REFRESH: sprintf(info->s, "REFR:%04X", cpustate->refresh); break; + case CPUINFO_STR_REGISTER + Z8000_IRQ_REQ: sprintf(info->s, "IRQR:%04X", cpustate->irq_req); break; + case CPUINFO_STR_REGISTER + Z8000_IRQ_SRV: sprintf(info->s, "IRQS:%04X", cpustate->irq_srv); break; + case CPUINFO_STR_REGISTER + Z8000_IRQ_VEC: sprintf(info->s, "IRQV:%04X", cpustate->irq_vec); break; + case CPUINFO_STR_REGISTER + Z8000_R0: sprintf(info->s, "R0 :%04X", cpustate->RW(0)); break; + case CPUINFO_STR_REGISTER + Z8000_R1: sprintf(info->s, "R1 :%04X", cpustate->RW(1)); break; + case CPUINFO_STR_REGISTER + Z8000_R2: sprintf(info->s, "R2 :%04X", cpustate->RW(2)); break; + case CPUINFO_STR_REGISTER + Z8000_R3: sprintf(info->s, "R3 :%04X", cpustate->RW(3)); break; + case CPUINFO_STR_REGISTER + Z8000_R4: sprintf(info->s, "R4 :%04X", cpustate->RW(4)); break; + case CPUINFO_STR_REGISTER + Z8000_R5: sprintf(info->s, "R5 :%04X", cpustate->RW(5)); break; + case CPUINFO_STR_REGISTER + Z8000_R6: sprintf(info->s, "R6 :%04X", cpustate->RW(6)); break; + case CPUINFO_STR_REGISTER + Z8000_R7: sprintf(info->s, "R7 :%04X", cpustate->RW(7)); break; + case CPUINFO_STR_REGISTER + Z8000_R8: sprintf(info->s, "R8 :%04X", cpustate->RW(8)); break; + case CPUINFO_STR_REGISTER + Z8000_R9: sprintf(info->s, "R9 :%04X", cpustate->RW(9)); break; + case CPUINFO_STR_REGISTER + Z8000_R10: sprintf(info->s, "R10:%04X", cpustate->RW(10)); break; + case CPUINFO_STR_REGISTER + Z8000_R11: sprintf(info->s, "R11:%04X", cpustate->RW(11)); break; + case CPUINFO_STR_REGISTER + Z8000_R12: sprintf(info->s, "R12:%04X", cpustate->RW(12)); break; + case CPUINFO_STR_REGISTER + Z8000_R13: sprintf(info->s, "R13:%04X", cpustate->RW(13)); break; + case CPUINFO_STR_REGISTER + Z8000_R14: sprintf(info->s, "R14:%04X", cpustate->RW(14)); break; + case CPUINFO_STR_REGISTER + Z8000_R15: sprintf(info->s, "R15:%04X", cpustate->RW(15)); break; } } @@ -878,24 +878,24 @@ CPU_GET_INFO( z8001 ) { switch (state) { - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 20; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 20; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 20; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 20; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 16; break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(z8001); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(z8001); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(z8001); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(z8001); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "Zilog Z8001"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "Zilog Z8001"); break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 8; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 8; break; - default: CPU_GET_INFO_CALL(z8002); break; + default: CPU_GET_INFO_CALL(z8002); break; } } diff --git a/src/emu/cpu/z8000/z8000.h b/src/emu/cpu/z8000/z8000.h index f61a6e4e801..e752a9d6f9c 100644 --- a/src/emu/cpu/z8000/z8000.h +++ b/src/emu/cpu/z8000/z8000.h @@ -15,14 +15,14 @@ enum }; /* Interrupt Types that can be generated by outside sources */ -#define Z8000_EPU 0x8000 /* extended instruction trap */ -#define Z8000_TRAP 0x4000 /* privileged instruction trap */ -#define Z8000_NMI 0x2000 /* non maskable interrupt */ -#define Z8000_SEGTRAP 0x1000 /* segment trap (Z8001) */ -#define Z8000_NVI 0x0800 /* non vectored interrupt */ -#define Z8000_VI 0x0400 /* vectored interrupt (LSB is vector) */ -#define Z8000_SYSCALL 0x0200 /* system call (lsb is vector) */ -#define Z8000_HALT 0x0100 /* halted flag */ +#define Z8000_EPU 0x8000 /* extended instruction trap */ +#define Z8000_TRAP 0x4000 /* privileged instruction trap */ +#define Z8000_NMI 0x2000 /* non maskable interrupt */ +#define Z8000_SEGTRAP 0x1000 /* segment trap (Z8001) */ +#define Z8000_NVI 0x0800 /* non vectored interrupt */ +#define Z8000_VI 0x0400 /* vectored interrupt (LSB is vector) */ +#define Z8000_SYSCALL 0x0200 /* system call (lsb is vector) */ +#define Z8000_HALT 0x0100 /* halted flag */ /* PUBLIC FUNCTIONS */ DECLARE_LEGACY_CPU_DEVICE(Z8001, z8001); diff --git a/src/emu/cpu/z8000/z8000cpu.h b/src/emu/cpu/z8000/z8000cpu.h index ffdad4be074..3063b77d092 100644 --- a/src/emu/cpu/z8000/z8000cpu.h +++ b/src/emu/cpu/z8000/z8000cpu.h @@ -60,45 +60,45 @@ #define PSA_ADDR (cpustate->device->type() == Z8001 ? segmented_addr((cpustate->psapseg << 16) | cpustate->psapoff) : cpustate->psapoff) /* these vectors are based on cpustate->psap @@@*/ -#define RST (PSA_ADDR + 0) /* start up cpustate->fcw and cpustate->pc */ -#define EPU (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0008 : 0x0004)) /* extension processor unit? trap */ -#define TRAP (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0010 : 0x0008)) /* privilege violation trap */ -#define SYSCALL (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0018 : 0x000c)) /* system call SC */ -#define SEGTRAP (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0020 : 0x0010)) /* segment trap */ -#define NMI (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0028 : 0x0014)) /* non maskable interrupt */ -#define NVI (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0030 : 0x0018)) /* non vectored interrupt */ -#define VI (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0038 : 0x001c)) /* vectored interrupt */ -#define VEC00 (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x003c : 0x001e)) /* vector n cpustate->pc value */ +#define RST (PSA_ADDR + 0) /* start up cpustate->fcw and cpustate->pc */ +#define EPU (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0008 : 0x0004)) /* extension processor unit? trap */ +#define TRAP (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0010 : 0x0008)) /* privilege violation trap */ +#define SYSCALL (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0018 : 0x000c)) /* system call SC */ +#define SEGTRAP (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0020 : 0x0010)) /* segment trap */ +#define NMI (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0028 : 0x0014)) /* non maskable interrupt */ +#define NVI (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0030 : 0x0018)) /* non vectored interrupt */ +#define VI (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x0038 : 0x001c)) /* vectored interrupt */ +#define VEC00 (PSA_ADDR + (cpustate->device->type() == Z8001 ? 0x003c : 0x001e)) /* vector n cpustate->pc value */ /* bits of the cpustate->fcw */ -#define F_SEG 0x8000 /* segmented mode (Z8001 only) */ -#define F_S_N 0x4000 /* system / normal mode */ -#define F_EPU 0x2000 /* extension processor unit? */ -#define F_VIE 0x1000 /* vectored interrupt enable */ -#define F_NVIE 0x0800 /* non vectored interrupt enable */ -#define F_10 0x0400 /* unused */ -#define F_9 0x0200 /* unused */ -#define F_8 0x0100 /* unused */ -#define F_C 0x0080 /* carry flag */ -#define F_Z 0x0040 /* zero flag */ -#define F_S 0x0020 /* sign flag */ -#define F_PV 0x0010 /* parity/overflow flag */ -#define F_DA 0x0008 /* decimal adjust flag (0 add/adc, 1 sub/sbc) */ -#define F_H 0x0004 /* half carry flag (byte arithmetic only) */ -#define F_1 0x0002 /* unused */ -#define F_0 0x0001 /* unused */ +#define F_SEG 0x8000 /* segmented mode (Z8001 only) */ +#define F_S_N 0x4000 /* system / normal mode */ +#define F_EPU 0x2000 /* extension processor unit? */ +#define F_VIE 0x1000 /* vectored interrupt enable */ +#define F_NVIE 0x0800 /* non vectored interrupt enable */ +#define F_10 0x0400 /* unused */ +#define F_9 0x0200 /* unused */ +#define F_8 0x0100 /* unused */ +#define F_C 0x0080 /* carry flag */ +#define F_Z 0x0040 /* zero flag */ +#define F_S 0x0020 /* sign flag */ +#define F_PV 0x0010 /* parity/overflow flag */ +#define F_DA 0x0008 /* decimal adjust flag (0 add/adc, 1 sub/sbc) */ +#define F_H 0x0004 /* half carry flag (byte arithmetic only) */ +#define F_1 0x0002 /* unused */ +#define F_0 0x0001 /* unused */ /* opcode word numbers in cpustate->op[] array */ -#define OP0 0 +#define OP0 0 #define OP1 1 #define OP2 2 /* nibble shift factors for an opcode word */ /* left to right: 0x1340 -> NIB0=1, NIB1=3, NIB2=4, NIB3=0 */ #define NIB0 12 -#define NIB1 8 -#define NIB2 4 -#define NIB3 0 +#define NIB1 8 +#define NIB2 4 +#define NIB3 0 /* sign bit masks for byte, word and long */ #define S08 0x80 @@ -107,107 +107,107 @@ /* get a single flag bit 0/1 */ #define GET_C ((cpustate->fcw >> 7) & 1) -#define GET_Z ((cpustate->fcw >> 6) & 1) -#define GET_S ((cpustate->fcw >> 5) & 1) -#define GET_PV ((cpustate->fcw >> 4) & 1) -#define GET_DA ((cpustate->fcw >> 3) & 1) -#define GET_H ((cpustate->fcw >> 2) & 1) +#define GET_Z ((cpustate->fcw >> 6) & 1) +#define GET_S ((cpustate->fcw >> 5) & 1) +#define GET_PV ((cpustate->fcw >> 4) & 1) +#define GET_DA ((cpustate->fcw >> 3) & 1) +#define GET_H ((cpustate->fcw >> 2) & 1) /* clear a single flag bit */ #define CLR_C cpustate->fcw &= ~F_C -#define CLR_Z cpustate->fcw &= ~F_Z -#define CLR_S cpustate->fcw &= ~F_S -#define CLR_P cpustate->fcw &= ~F_PV -#define CLR_V cpustate->fcw &= ~F_PV -#define CLR_DA cpustate->fcw &= ~F_DA -#define CLR_H cpustate->fcw &= ~F_H +#define CLR_Z cpustate->fcw &= ~F_Z +#define CLR_S cpustate->fcw &= ~F_S +#define CLR_P cpustate->fcw &= ~F_PV +#define CLR_V cpustate->fcw &= ~F_PV +#define CLR_DA cpustate->fcw &= ~F_DA +#define CLR_H cpustate->fcw &= ~F_H /* clear a flag bit combination */ #define CLR_CZS cpustate->fcw &= ~(F_C|F_Z|F_S) -#define CLR_CZSP cpustate->fcw &= ~(F_C|F_Z|F_S|F_PV) -#define CLR_CZSV cpustate->fcw &= ~(F_C|F_Z|F_S|F_PV) -#define CLR_CZSVH cpustate->fcw &= ~(F_C|F_Z|F_S|F_PV|F_H) -#define CLR_ZS cpustate->fcw &= ~(F_Z|F_S) -#define CLR_ZSV cpustate->fcw &= ~(F_Z|F_S|F_PV) -#define CLR_ZSP cpustate->fcw &= ~(F_Z|F_S|F_PV) +#define CLR_CZSP cpustate->fcw &= ~(F_C|F_Z|F_S|F_PV) +#define CLR_CZSV cpustate->fcw &= ~(F_C|F_Z|F_S|F_PV) +#define CLR_CZSVH cpustate->fcw &= ~(F_C|F_Z|F_S|F_PV|F_H) +#define CLR_ZS cpustate->fcw &= ~(F_Z|F_S) +#define CLR_ZSV cpustate->fcw &= ~(F_Z|F_S|F_PV) +#define CLR_ZSP cpustate->fcw &= ~(F_Z|F_S|F_PV) /* set a single flag bit */ #define SET_C cpustate->fcw |= F_C -#define SET_Z cpustate->fcw |= F_Z -#define SET_S cpustate->fcw |= F_S -#define SET_P cpustate->fcw |= F_PV -#define SET_V cpustate->fcw |= F_PV -#define SET_DA cpustate->fcw |= F_DA -#define SET_H cpustate->fcw |= F_H +#define SET_Z cpustate->fcw |= F_Z +#define SET_S cpustate->fcw |= F_S +#define SET_P cpustate->fcw |= F_PV +#define SET_V cpustate->fcw |= F_PV +#define SET_DA cpustate->fcw |= F_DA +#define SET_H cpustate->fcw |= F_H /* set a flag bit combination */ #define SET_SC cpustate->fcw |= F_C | F_S /* check condition codes */ -#define CC0 (0) /* always false */ -#define CC1 (GET_PV^GET_S) /* less than */ -#define CC2 (GET_Z|(GET_PV^GET_S)) /* less than or equal */ -#define CC3 (GET_Z|GET_C) /* unsigned less than or equal */ -#define CC4 GET_PV /* parity even / overflow */ -#define CC5 GET_S /* minus (signed) */ -#define CC6 GET_Z /* zero / equal */ -#define CC7 GET_C /* carry / unsigned less than */ - -#define CC8 (1) /* always true */ -#define CC9 !(GET_PV^GET_S) /* greater than or equal */ -#define CCA !(GET_Z|(GET_PV^GET_S)) /* greater than */ -#define CCB !(GET_Z|GET_C) /* unsigned greater than */ -#define CCC !GET_PV /* parity odd / no overflow */ -#define CCD !GET_S /* plus (not signed) */ -#define CCE !GET_Z /* not zero / not equal */ -#define CCF !GET_C /* not carry / unsigned greater than */ +#define CC0 (0) /* always false */ +#define CC1 (GET_PV^GET_S) /* less than */ +#define CC2 (GET_Z|(GET_PV^GET_S)) /* less than or equal */ +#define CC3 (GET_Z|GET_C) /* unsigned less than or equal */ +#define CC4 GET_PV /* parity even / overflow */ +#define CC5 GET_S /* minus (signed) */ +#define CC6 GET_Z /* zero / equal */ +#define CC7 GET_C /* carry / unsigned less than */ + +#define CC8 (1) /* always true */ +#define CC9 !(GET_PV^GET_S) /* greater than or equal */ +#define CCA !(GET_Z|(GET_PV^GET_S)) /* greater than */ +#define CCB !(GET_Z|GET_C) /* unsigned greater than */ +#define CCC !GET_PV /* parity odd / no overflow */ +#define CCD !GET_S /* plus (not signed) */ +#define CCE !GET_Z /* not zero / not equal */ +#define CCF !GET_C /* not carry / unsigned greater than */ /* get data from the opcode words */ /* o is the opcode word offset */ /* s is a nibble shift factor */ #define GET_BIT(o) UINT16 bit = 1 << (get_operand(cpustate, o) & 15) -#define GET_CCC(o,s) UINT8 cc = (get_operand(cpustate, o) >> (s)) & 15 - -#define GET_DST(o,s) UINT8 dst = (get_operand(cpustate, o) >> (s)) & 15 -#define GET_SRC(o,s) UINT8 src = (get_operand(cpustate, o) >> (s)) & 15 -#define GET_IDX(o,s) UINT8 idx = (get_operand(cpustate, o) >> (s)) & 15 -#define GET_CNT(o,s) INT8 cnt = (get_operand(cpustate, o) >> (s)) & 15 -#define GET_IMM4(o,s) UINT8 imm4 = (get_operand(cpustate, o) >> (s)) & 15 - -#define GET_I4M1(o,s) UINT8 i4p1 = ((get_operand(cpustate, o) >> (s)) & 15) + 1 -#define GET_IMM1(o,s) UINT8 imm1 = (get_operand(cpustate, o) >> (s)) & 2 -#define GET_IMM2(o,s) UINT8 imm2 = (get_operand(cpustate, o) >> (s)) & 3 -#define GET_IMM3(o,s) UINT8 imm3 = (get_operand(cpustate, o) >> (s)) & 7 - -#define GET_IMM8(o) UINT8 imm8 = (UINT8)get_operand(cpustate, o) - -#define GET_IMM16(o) UINT16 imm16 = get_operand(cpustate, o) -#define GET_IDX16(o) UINT32 idx16 = get_operand(cpustate, o) -#define GET_IMM32 UINT32 imm32 = (get_operand(cpustate, 1) << 16) + get_operand(cpustate, 2) -#define GET_DSP7 UINT8 dsp7 = get_operand(cpustate, 0) & 127 -#define GET_DSP8 INT8 dsp8 = (INT8)get_operand(cpustate, 0) -#define GET_DSP16 UINT32 dsp16 = addr_add(cpustate, cpustate->pc, (INT16)get_operand(cpustate, 1)) -#define GET_ADDR(o) UINT32 addr = (UINT32)get_addr_operand(cpustate, o) -#define GET_ADDR_RAW(o) UINT32 addr = (UINT32)get_raw_addr_operand(cpustate, o) +#define GET_CCC(o,s) UINT8 cc = (get_operand(cpustate, o) >> (s)) & 15 + +#define GET_DST(o,s) UINT8 dst = (get_operand(cpustate, o) >> (s)) & 15 +#define GET_SRC(o,s) UINT8 src = (get_operand(cpustate, o) >> (s)) & 15 +#define GET_IDX(o,s) UINT8 idx = (get_operand(cpustate, o) >> (s)) & 15 +#define GET_CNT(o,s) INT8 cnt = (get_operand(cpustate, o) >> (s)) & 15 +#define GET_IMM4(o,s) UINT8 imm4 = (get_operand(cpustate, o) >> (s)) & 15 + +#define GET_I4M1(o,s) UINT8 i4p1 = ((get_operand(cpustate, o) >> (s)) & 15) + 1 +#define GET_IMM1(o,s) UINT8 imm1 = (get_operand(cpustate, o) >> (s)) & 2 +#define GET_IMM2(o,s) UINT8 imm2 = (get_operand(cpustate, o) >> (s)) & 3 +#define GET_IMM3(o,s) UINT8 imm3 = (get_operand(cpustate, o) >> (s)) & 7 + +#define GET_IMM8(o) UINT8 imm8 = (UINT8)get_operand(cpustate, o) + +#define GET_IMM16(o) UINT16 imm16 = get_operand(cpustate, o) +#define GET_IDX16(o) UINT32 idx16 = get_operand(cpustate, o) +#define GET_IMM32 UINT32 imm32 = (get_operand(cpustate, 1) << 16) + get_operand(cpustate, 2) +#define GET_DSP7 UINT8 dsp7 = get_operand(cpustate, 0) & 127 +#define GET_DSP8 INT8 dsp8 = (INT8)get_operand(cpustate, 0) +#define GET_DSP16 UINT32 dsp16 = addr_add(cpustate, cpustate->pc, (INT16)get_operand(cpustate, 1)) +#define GET_ADDR(o) UINT32 addr = (UINT32)get_addr_operand(cpustate, o) +#define GET_ADDR_RAW(o) UINT32 addr = (UINT32)get_raw_addr_operand(cpustate, o) struct z8000_state; /* structure for the opcode definition table */ struct Z8000_init { - int beg, end, step; - int size, cycles; - void (*opcode)(z8000_state *cpustate); - const char *dasm; - UINT32 dasmflags; + int beg, end, step; + int size, cycles; + void (*opcode)(z8000_state *cpustate); + const char *dasm; + UINT32 dasmflags; }; /* structure for the opcode execution table / disassembler */ struct Z8000_exec { - void (*opcode)(z8000_state *cpustate); - int cycles; - int size; - const char *dasm; - UINT32 dasmflags; + void (*opcode)(z8000_state *cpustate); + int cycles; + int size; + const char *dasm; + UINT32 dasmflags; }; /* opcode execution table */ diff --git a/src/emu/cpu/z8000/z8000ops.c b/src/emu/cpu/z8000/z8000ops.c index c2736c7ad1b..0802d54a6f5 100644 --- a/src/emu/cpu/z8000/z8000ops.c +++ b/src/emu/cpu/z8000/z8000ops.c @@ -32,62 +32,62 @@ ******************************************/ INLINE void CHANGE_FCW(z8000_state *cpustate, UINT16 fcw) { - if (fcw & F_S_N) { /* system mode now? */ - if (!(cpustate->fcw & F_S_N)) { /* and not before? */ - if (cpustate->device->type() == Z8001) { - UINT16 tmp = cpustate->RW(15); - cpustate->RW(15) = cpustate->nspoff; - cpustate->nspoff = tmp; - tmp = cpustate->RW(14); - cpustate->RW(14) = cpustate->nspseg; - cpustate->nspseg = tmp; - } - else { - UINT16 tmp = cpustate->RW(SP); - cpustate->RW(SP) = cpustate->nspoff; - cpustate->nspoff = tmp; - } + if (fcw & F_S_N) { /* system mode now? */ + if (!(cpustate->fcw & F_S_N)) { /* and not before? */ + if (cpustate->device->type() == Z8001) { + UINT16 tmp = cpustate->RW(15); + cpustate->RW(15) = cpustate->nspoff; + cpustate->nspoff = tmp; + tmp = cpustate->RW(14); + cpustate->RW(14) = cpustate->nspseg; + cpustate->nspseg = tmp; + } + else { + UINT16 tmp = cpustate->RW(SP); + cpustate->RW(SP) = cpustate->nspoff; + cpustate->nspoff = tmp; + } } - } else { /* user mode now */ - if (cpustate->fcw & F_S_N) { /* and not before? */ - if (cpustate->device->type() == Z8001) { - UINT16 tmp = cpustate->RW(15); - cpustate->RW(15) = cpustate->nspoff; - cpustate->nspoff = tmp; - tmp = cpustate->RW(14); - cpustate->RW(14) = cpustate->nspseg; - cpustate->nspseg = tmp; - } - else { - UINT16 tmp = cpustate->RW(SP); - cpustate->RW(SP) = cpustate->nspoff; - cpustate->nspoff = tmp; - } - } - } - if (!(cpustate->fcw & F_NVIE) && (fcw & F_NVIE) && (cpustate->irq_state[0] != CLEAR_LINE)) + } else { /* user mode now */ + if (cpustate->fcw & F_S_N) { /* and not before? */ + if (cpustate->device->type() == Z8001) { + UINT16 tmp = cpustate->RW(15); + cpustate->RW(15) = cpustate->nspoff; + cpustate->nspoff = tmp; + tmp = cpustate->RW(14); + cpustate->RW(14) = cpustate->nspseg; + cpustate->nspseg = tmp; + } + else { + UINT16 tmp = cpustate->RW(SP); + cpustate->RW(SP) = cpustate->nspoff; + cpustate->nspoff = tmp; + } + } + } + if (!(cpustate->fcw & F_NVIE) && (fcw & F_NVIE) && (cpustate->irq_state[0] != CLEAR_LINE)) cpustate->irq_req |= Z8000_NVI; if (!(cpustate->fcw & F_VIE) && (fcw & F_VIE) && (cpustate->irq_state[1] != CLEAR_LINE)) cpustate->irq_req |= Z8000_VI; - cpustate->fcw = fcw; /* set new cpustate->fcw */ + cpustate->fcw = fcw; /* set new cpustate->fcw */ } INLINE UINT32 make_segmented_addr(UINT32 addr) { - return ((addr & 0x007f0000) << 8) | 0x80000000 | (addr & 0xffff); + return ((addr & 0x007f0000) << 8) | 0x80000000 | (addr & 0xffff); } INLINE UINT32 segmented_addr(UINT32 addr) { - return ((addr & 0x7f000000) >> 8) | (addr & 0xffff); + return ((addr & 0x7f000000) >> 8) | (addr & 0xffff); } INLINE UINT32 addr_from_reg(z8000_state *cpustate, int regno) { - if (segmented_mode(cpustate)) - return segmented_addr(cpustate->RL(regno)); - else - return cpustate->RW(regno); + if (segmented_mode(cpustate)) + return segmented_addr(cpustate->RL(regno)); + else + return cpustate->RW(regno); } INLINE void addr_to_reg(z8000_state *cpustate, int regno, UINT32 addr) @@ -97,8 +97,8 @@ INLINE void addr_to_reg(z8000_state *cpustate, int regno, UINT32 addr) cpustate->RW(regno) = (cpustate->RW(regno) & 0x80ff) | ((segaddr >> 16) & 0x7f00); cpustate->RW(regno | 1) = segaddr & 0xffff; } - else - cpustate->RW(regno) = addr; + else + cpustate->RW(regno) = addr; } INLINE void add_to_addr_reg(z8000_state *cpustate, int regno, UINT16 addend) @@ -125,39 +125,39 @@ INLINE void set_pc(z8000_state *cpustate, UINT32 addr) INLINE void PUSHW(z8000_state *cpustate, UINT8 dst, UINT16 value) { - if (segmented_mode(cpustate)) - cpustate->RW(dst | 1) -= 2; - else - cpustate->RW(dst) -= 2; + if (segmented_mode(cpustate)) + cpustate->RW(dst | 1) -= 2; + else + cpustate->RW(dst) -= 2; WRMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, dst), value); } INLINE UINT16 POPW(z8000_state *cpustate, UINT8 src) { UINT16 result = RDMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, src)); - if (segmented_mode(cpustate)) - cpustate->RW(src | 1) += 2; - else - cpustate->RW(src) += 2; + if (segmented_mode(cpustate)) + cpustate->RW(src | 1) += 2; + else + cpustate->RW(src) += 2; return result; } INLINE void PUSHL(z8000_state *cpustate, UINT8 dst, UINT32 value) { - if (segmented_mode(cpustate)) - cpustate->RW(dst | 1) -= 4; - else - cpustate->RW(dst) -= 4; + if (segmented_mode(cpustate)) + cpustate->RW(dst | 1) -= 4; + else + cpustate->RW(dst) -= 4; WRMEM_L(cpustate, AS_DATA, addr_from_reg(cpustate, dst), value); } INLINE UINT32 POPL(z8000_state *cpustate, UINT8 src) { UINT32 result = RDMEM_L(cpustate, AS_DATA, addr_from_reg(cpustate, src)); - if (segmented_mode(cpustate)) - cpustate->RW(src | 1) += 4; - else - cpustate->RW(src) += 4; + if (segmented_mode(cpustate)) + cpustate->RW(src | 1) += 4; + else + cpustate->RW(src) += 4; return result; } @@ -178,10 +178,10 @@ INLINE UINT32 POPL(z8000_state *cpustate, UINT8 src) /* check half carry for A addition and S subtraction */ #define CHK_ADDB_H if ((result & 15) < (dest & 15)) SET_H -#define CHK_ADCB_H if ((result & 15) < (dest & 15) || ((result & 15) == (dest & 15) && (value & 15))) SET_H +#define CHK_ADCB_H if ((result & 15) < (dest & 15) || ((result & 15) == (dest & 15) && (value & 15))) SET_H #define CHK_SUBB_H if ((result & 15) > (dest & 15)) SET_H -#define CHK_SBCB_H if ((result & 15) > (dest & 15) || ((result & 15) == (dest & 15) && (value & 15))) SET_H +#define CHK_SBCB_H if ((result & 15) > (dest & 15) || ((result & 15) == (dest & 15) && (value & 15))) SET_H /* check overflow for addition for byte, word and long */ #define CHK_ADDB_V if (((value & dest & ~result) | (~value & ~dest & result)) & S08) SET_V @@ -207,12 +207,12 @@ INLINE UINT32 POPL(z8000_state *cpustate, UINT8 src) INLINE UINT8 ADDB(z8000_state *cpustate, UINT8 dest, UINT8 value) { UINT8 result = dest + value; - CLR_CZSVH; /* first clear C, Z, S, P/V and H flags */ - CLR_DA; /* clear DA (decimal adjust) flag for addb */ - CHK_XXXB_ZS; /* set Z and S flags for result byte */ - CHK_ADDX_C; /* set C if result overflowed */ - CHK_ADDB_V; /* set V if result has incorrect sign */ - CHK_ADDB_H; /* set H if lower nibble overflowed */ + CLR_CZSVH; /* first clear C, Z, S, P/V and H flags */ + CLR_DA; /* clear DA (decimal adjust) flag for addb */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_ADDX_C; /* set C if result overflowed */ + CHK_ADDB_V; /* set V if result has incorrect sign */ + CHK_ADDB_H; /* set H if lower nibble overflowed */ return result; } @@ -223,10 +223,10 @@ INLINE UINT8 ADDB(z8000_state *cpustate, UINT8 dest, UINT8 value) INLINE UINT16 ADDW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT16 result = dest + value; - CLR_CZSV; /* first clear C, Z, S, P/V flags */ - CHK_XXXW_ZS; /* set Z and S flags for result word */ - CHK_ADDX_C; /* set C if result overflowed */ - CHK_ADDW_V; /* set V if result has incorrect sign */ + CLR_CZSV; /* first clear C, Z, S, P/V flags */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_ADDX_C; /* set C if result overflowed */ + CHK_ADDW_V; /* set V if result has incorrect sign */ return result; } @@ -237,10 +237,10 @@ INLINE UINT16 ADDW(z8000_state *cpustate, UINT16 dest, UINT16 value) INLINE UINT32 ADDL(z8000_state *cpustate, UINT32 dest, UINT32 value) { UINT32 result = dest + value; - CLR_CZSV; /* first clear C, Z, S, P/V flags */ - CHK_XXXL_ZS; /* set Z and S flags for result long */ - CHK_ADDX_C; /* set C if result overflowed */ - CHK_ADDL_V; /* set V if result has incorrect sign */ + CLR_CZSV; /* first clear C, Z, S, P/V flags */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_ADDX_C; /* set C if result overflowed */ + CHK_ADDL_V; /* set V if result has incorrect sign */ return result; } @@ -251,12 +251,12 @@ INLINE UINT32 ADDL(z8000_state *cpustate, UINT32 dest, UINT32 value) INLINE UINT8 ADCB(z8000_state *cpustate, UINT8 dest, UINT8 value) { UINT8 result = dest + value + GET_C; - CLR_CZSVH; /* first clear C, Z, S, P/V and H flags */ - CLR_DA; /* clear DA (decimal adjust) flag for adcb */ - CHK_XXXB_ZS; /* set Z and S flags for result byte */ - CHK_ADCX_C; /* set C if result overflowed */ - CHK_ADDB_V; /* set V if result has incorrect sign */ - CHK_ADCB_H; /* set H if lower nibble overflowed */ + CLR_CZSVH; /* first clear C, Z, S, P/V and H flags */ + CLR_DA; /* clear DA (decimal adjust) flag for adcb */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_ADCX_C; /* set C if result overflowed */ + CHK_ADDB_V; /* set V if result has incorrect sign */ + CHK_ADCB_H; /* set H if lower nibble overflowed */ return result; } @@ -267,10 +267,10 @@ INLINE UINT8 ADCB(z8000_state *cpustate, UINT8 dest, UINT8 value) INLINE UINT16 ADCW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT16 result = dest + value + GET_C; - CLR_CZSV; /* first clear C, Z, S, P/V flags */ - CHK_XXXW_ZS; /* set Z and S flags for result word */ - CHK_ADCX_C; /* set C if result overflowed */ - CHK_ADDW_V; /* set V if result has incorrect sign */ + CLR_CZSV; /* first clear C, Z, S, P/V flags */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_ADCX_C; /* set C if result overflowed */ + CHK_ADDW_V; /* set V if result has incorrect sign */ return result; } @@ -281,12 +281,12 @@ INLINE UINT16 ADCW(z8000_state *cpustate, UINT16 dest, UINT16 value) INLINE UINT8 SUBB(z8000_state *cpustate, UINT8 dest, UINT8 value) { UINT8 result = dest - value; - CLR_CZSVH; /* first clear C, Z, S, P/V and H flags */ - SET_DA; /* set DA (decimal adjust) flag for subb */ - CHK_XXXB_ZS; /* set Z and S flags for result byte */ - CHK_SUBX_C; /* set C if result underflowed */ - CHK_SUBB_V; /* set V if result has incorrect sign */ - CHK_SUBB_H; /* set H if lower nibble underflowed */ + CLR_CZSVH; /* first clear C, Z, S, P/V and H flags */ + SET_DA; /* set DA (decimal adjust) flag for subb */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_SUBX_C; /* set C if result underflowed */ + CHK_SUBB_V; /* set V if result has incorrect sign */ + CHK_SUBB_H; /* set H if lower nibble underflowed */ return result; } @@ -297,10 +297,10 @@ INLINE UINT8 SUBB(z8000_state *cpustate, UINT8 dest, UINT8 value) INLINE UINT16 SUBW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT16 result = dest - value; - CLR_CZSV; /* first clear C, Z, S, P/V flags */ - CHK_XXXW_ZS; /* set Z and S flags for result word */ - CHK_SUBX_C; /* set C if result underflowed */ - CHK_SUBW_V; /* set V if result has incorrect sign */ + CLR_CZSV; /* first clear C, Z, S, P/V flags */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_SUBX_C; /* set C if result underflowed */ + CHK_SUBW_V; /* set V if result has incorrect sign */ return result; } @@ -311,10 +311,10 @@ INLINE UINT16 SUBW(z8000_state *cpustate, UINT16 dest, UINT16 value) INLINE UINT32 SUBL(z8000_state *cpustate, UINT32 dest, UINT32 value) { UINT32 result = dest - value; - CLR_CZSV; /* first clear C, Z, S, P/V flags */ - CHK_XXXL_ZS; /* set Z and S flags for result long */ - CHK_SUBX_C; /* set C if result underflowed */ - CHK_SUBL_V; /* set V if result has incorrect sign */ + CLR_CZSV; /* first clear C, Z, S, P/V flags */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_SUBX_C; /* set C if result underflowed */ + CHK_SUBL_V; /* set V if result has incorrect sign */ return result; } @@ -325,12 +325,12 @@ INLINE UINT32 SUBL(z8000_state *cpustate, UINT32 dest, UINT32 value) INLINE UINT8 SBCB(z8000_state *cpustate, UINT8 dest, UINT8 value) { UINT8 result = dest - value - GET_C; - CLR_CZSVH; /* first clear C, Z, S, P/V and H flags */ - SET_DA; /* set DA (decimal adjust) flag for sbcb */ - CHK_XXXB_ZS; /* set Z and S flags for result byte */ - CHK_SBCX_C; /* set C if result underflowed */ - CHK_SUBB_V; /* set V if result has incorrect sign */ - CHK_SBCB_H; /* set H if lower nibble underflowed */ + CLR_CZSVH; /* first clear C, Z, S, P/V and H flags */ + SET_DA; /* set DA (decimal adjust) flag for sbcb */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_SBCX_C; /* set C if result underflowed */ + CHK_SUBB_V; /* set V if result has incorrect sign */ + CHK_SBCB_H; /* set H if lower nibble underflowed */ return result; } @@ -341,10 +341,10 @@ INLINE UINT8 SBCB(z8000_state *cpustate, UINT8 dest, UINT8 value) INLINE UINT16 SBCW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT16 result = dest - value - GET_C; - CLR_CZSV; /* first clear C, Z, S, P/V flags */ - CHK_XXXW_ZS; /* set Z and S flags for result word */ - CHK_SBCX_C; /* set C if result underflowed */ - CHK_SUBW_V; /* set V if result has incorrect sign */ + CLR_CZSV; /* first clear C, Z, S, P/V flags */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_SBCX_C; /* set C if result underflowed */ + CHK_SUBW_V; /* set V if result has incorrect sign */ return result; } @@ -355,8 +355,8 @@ INLINE UINT16 SBCW(z8000_state *cpustate, UINT16 dest, UINT16 value) INLINE UINT8 ORB(z8000_state *cpustate, UINT8 dest, UINT8 value) { UINT8 result = dest | value; - CLR_ZSP; /* first clear Z, S, P/V flags */ - CHK_XXXB_ZSP; /* set Z, S and P flags for result byte */ + CLR_ZSP; /* first clear Z, S, P/V flags */ + CHK_XXXB_ZSP; /* set Z, S and P flags for result byte */ return result; } @@ -367,8 +367,8 @@ INLINE UINT8 ORB(z8000_state *cpustate, UINT8 dest, UINT8 value) INLINE UINT16 ORW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT16 result = dest | value; - CLR_ZS; /* first clear Z, and S flags */ - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CLR_ZS; /* first clear Z, and S flags */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ return result; } @@ -379,8 +379,8 @@ INLINE UINT16 ORW(z8000_state *cpustate, UINT16 dest, UINT16 value) INLINE UINT8 ANDB(z8000_state *cpustate, UINT8 dest, UINT8 value) { UINT8 result = dest & value; - CLR_ZSP; /* first clear Z,S and P/V flags */ - CHK_XXXB_ZSP; /* set Z, S and P flags for result byte */ + CLR_ZSP; /* first clear Z,S and P/V flags */ + CHK_XXXB_ZSP; /* set Z, S and P flags for result byte */ return result; } @@ -391,8 +391,8 @@ INLINE UINT8 ANDB(z8000_state *cpustate, UINT8 dest, UINT8 value) INLINE UINT16 ANDW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT16 result = dest & value; - CLR_ZS; /* first clear Z and S flags */ - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CLR_ZS; /* first clear Z and S flags */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ return result; } @@ -403,8 +403,8 @@ INLINE UINT16 ANDW(z8000_state *cpustate, UINT16 dest, UINT16 value) INLINE UINT8 XORB(z8000_state *cpustate, UINT8 dest, UINT8 value) { UINT8 result = dest ^ value; - CLR_ZSP; /* first clear Z, S and P/V flags */ - CHK_XXXB_ZSP; /* set Z, S and P flags for result byte */ + CLR_ZSP; /* first clear Z, S and P/V flags */ + CHK_XXXB_ZSP; /* set Z, S and P flags for result byte */ return result; } @@ -415,8 +415,8 @@ INLINE UINT8 XORB(z8000_state *cpustate, UINT8 dest, UINT8 value) INLINE UINT16 XORW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT16 result = dest ^ value; - CLR_ZS; /* first clear Z and S flags */ - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CLR_ZS; /* first clear Z and S flags */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ return result; } @@ -428,9 +428,9 @@ INLINE UINT16 XORW(z8000_state *cpustate, UINT16 dest, UINT16 value) INLINE void CPB(z8000_state *cpustate, UINT8 dest, UINT8 value) { UINT8 result = dest - value; - CLR_CZSV; /* first clear C, Z, S and P/V flags */ - CHK_XXXB_ZS; /* set Z and S flags for result byte */ - CHK_SUBX_C; /* set C if result underflowed */ + CLR_CZSV; /* first clear C, Z, S and P/V flags */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_SUBX_C; /* set C if result underflowed */ CHK_SUBB_V; } @@ -442,8 +442,8 @@ INLINE void CPW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT16 result = dest - value; CLR_CZSV; - CHK_XXXW_ZS; /* set Z and S flags for result word */ - CHK_SUBX_C; /* set C if result underflowed */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_SUBX_C; /* set C if result underflowed */ CHK_SUBW_V; } @@ -455,8 +455,8 @@ INLINE void CPL(z8000_state *cpustate, UINT32 dest, UINT32 value) { UINT32 result = dest - value; CLR_CZSV; - CHK_XXXL_ZS; /* set Z and S flags for result long */ - CHK_SUBX_C; /* set C if result underflowed */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_SUBX_C; /* set C if result underflowed */ CHK_SUBL_V; } @@ -468,7 +468,7 @@ INLINE UINT8 COMB(z8000_state *cpustate, UINT8 dest) { UINT8 result = ~dest; CLR_ZSP; - CHK_XXXB_ZSP; /* set Z, S and P flags for result byte */ + CHK_XXXB_ZSP; /* set Z, S and P flags for result byte */ return result; } @@ -480,7 +480,7 @@ INLINE UINT16 COMW(z8000_state *cpustate, UINT16 dest) { UINT16 result = ~dest; CLR_ZS; - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ return result; } @@ -492,9 +492,9 @@ INLINE UINT8 NEGB(z8000_state *cpustate, UINT8 dest) { UINT8 result = (UINT8) -dest; CLR_CZSV; - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (result > 0) SET_C; - if (result == S08) SET_V; + if (result == S08) SET_V; return result; } @@ -506,9 +506,9 @@ INLINE UINT16 NEGW(z8000_state *cpustate, UINT16 dest) { UINT16 result = (UINT16) -dest; CLR_CZSV; - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (result > 0) SET_C; - if (result == S16) SET_V; + if (result == S16) SET_V; return result; } @@ -519,7 +519,7 @@ INLINE UINT16 NEGW(z8000_state *cpustate, UINT16 dest) INLINE void TESTB(z8000_state *cpustate, UINT8 result) { CLR_ZSP; - CHK_XXXB_ZSP; /* set Z and S flags for result byte */ + CHK_XXXB_ZSP; /* set Z and S flags for result byte */ } /****************************************** @@ -529,7 +529,7 @@ INLINE void TESTB(z8000_state *cpustate, UINT8 result) INLINE void TESTW(z8000_state *cpustate, UINT16 dest) { CLR_ZS; - if (!dest) SET_Z; else if (dest & S16) SET_S; + if (!dest) SET_Z; else if (dest & S16) SET_S; } /****************************************** @@ -548,10 +548,10 @@ INLINE void TESTL(z8000_state *cpustate, UINT32 dest) ******************************************/ INLINE UINT8 INCB(z8000_state *cpustate, UINT8 dest, UINT8 value) { - UINT8 result = dest + value; + UINT8 result = dest + value; CLR_ZSV; - CHK_XXXB_ZS; /* set Z and S flags for result byte */ - CHK_ADDB_V; /* set V if result overflowed */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_ADDB_V; /* set V if result overflowed */ return result; } @@ -561,10 +561,10 @@ INLINE UINT8 INCB(z8000_state *cpustate, UINT8 dest, UINT8 value) ******************************************/ INLINE UINT16 INCW(z8000_state *cpustate, UINT16 dest, UINT16 value) { - UINT16 result = dest + value; + UINT16 result = dest + value; CLR_ZSV; - CHK_XXXW_ZS; /* set Z and S flags for result byte */ - CHK_ADDW_V; /* set V if result overflowed */ + CHK_XXXW_ZS; /* set Z and S flags for result byte */ + CHK_ADDW_V; /* set V if result overflowed */ return result; } @@ -574,10 +574,10 @@ INLINE UINT16 INCW(z8000_state *cpustate, UINT16 dest, UINT16 value) ******************************************/ INLINE UINT8 DECB(z8000_state *cpustate, UINT8 dest, UINT8 value) { - UINT8 result = dest - value; + UINT8 result = dest - value; CLR_ZSV; - CHK_XXXB_ZS; /* set Z and S flags for result byte */ - CHK_SUBB_V; /* set V if result overflowed */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_SUBB_V; /* set V if result overflowed */ return result; } @@ -587,10 +587,10 @@ INLINE UINT8 DECB(z8000_state *cpustate, UINT8 dest, UINT8 value) ******************************************/ INLINE UINT16 DECW(z8000_state *cpustate, UINT16 dest, UINT16 value) { - UINT16 result = dest - value; + UINT16 result = dest - value; CLR_ZSV; - CHK_XXXW_ZS; /* set Z and S flags for result word */ - CHK_SUBW_V; /* set V if result overflowed */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_SUBW_V; /* set V if result overflowed */ return result; } @@ -602,11 +602,11 @@ INLINE UINT32 MULTW(z8000_state *cpustate, UINT16 dest, UINT16 value) { UINT32 result = (INT32)(INT16)dest * (INT16)value; CLR_CZSV; - CHK_XXXL_ZS; + CHK_XXXL_ZS; if(!value) { /* multiplication with zero is faster */ - cpustate->icount += (70-18); + cpustate->icount += (70-18); } if((INT32)result < -0x7fff || (INT32)result >= 0x7fff) SET_C; return result; @@ -619,7 +619,7 @@ INLINE UINT32 MULTW(z8000_state *cpustate, UINT16 dest, UINT16 value) INLINE UINT64 MULTL(z8000_state *cpustate, UINT32 dest, UINT32 value) { UINT64 result = (INT64)(INT32)dest * (INT32)value; - if(!value) + if(!value) { /* multiplication with zero is faster */ cpustate->icount += (282 - 30); @@ -629,8 +629,8 @@ INLINE UINT64 MULTL(z8000_state *cpustate, UINT32 dest, UINT32 value) int n; for(n = 0; n < 32; n++) if(dest & (1L << n)) cpustate->icount -= 7; - } - CLR_CZSV; + } + CLR_CZSV; CHK_XXXQ_ZS; if((INT64)result < -0x7fffffffL || (INT64)result >= 0x7fffffffL) SET_C; return result; @@ -671,12 +671,12 @@ INLINE UINT32 DIVW(z8000_state *cpustate, UINT32 dest, UINT16 value) CHK_XXXW_ZS; } result = ((UINT32)remainder << 16) | (result & 0xffff); - } - else - { + } + else + { SET_Z; - SET_V; - } + SET_V; + } return result; } @@ -715,12 +715,12 @@ INLINE UINT64 DIVL(z8000_state *cpustate, UINT64 dest, UINT32 value) CHK_XXXL_ZS; } result = ((UINT64)remainder << 32) | (result & 0xffffffff); - } - else - { + } + else + { SET_Z; - SET_V; - } + SET_V; + } return result; } @@ -733,9 +733,9 @@ INLINE UINT8 RLB(z8000_state *cpustate, UINT8 dest, UINT8 twice) UINT8 result = (dest << 1) | (dest >> 7); CLR_CZSV; if (twice) result = (result << 1) | (result >> 7); - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (result & 0x01) SET_C; - if ((result ^ dest) & S08) SET_V; + if ((result ^ dest) & S08) SET_V; return result; } @@ -748,9 +748,9 @@ INLINE UINT16 RLW(z8000_state *cpustate, UINT16 dest, UINT8 twice) UINT16 result = (dest << 1) | (dest >> 15); CLR_CZSV; if (twice) result = (result << 1) | (result >> 15); - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (result & 0x0001) SET_C; - if ((result ^ dest) & S16) SET_V; + if ((result ^ dest) & S16) SET_V; return result; } @@ -760,17 +760,17 @@ INLINE UINT16 RLW(z8000_state *cpustate, UINT16 dest, UINT8 twice) ******************************************/ INLINE UINT8 RLCB(z8000_state *cpustate, UINT8 dest, UINT8 twice) { - UINT8 c = dest & S08; + UINT8 c = dest & S08; UINT8 result = (dest << 1) | GET_C; CLR_CZSV; if (twice) { UINT8 c1 = c >> 7; - c = result & S08; + c = result & S08; result = (result << 1) | c1; } - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (c) SET_C; - if ((result ^ dest) & S08) SET_V; + if ((result ^ dest) & S08) SET_V; return result; } @@ -780,17 +780,17 @@ INLINE UINT8 RLCB(z8000_state *cpustate, UINT8 dest, UINT8 twice) ******************************************/ INLINE UINT16 RLCW(z8000_state *cpustate, UINT16 dest, UINT8 twice) { - UINT16 c = dest & S16; + UINT16 c = dest & S16; UINT16 result = (dest << 1) | GET_C; CLR_CZSV; if (twice) { UINT16 c1 = c >> 15; - c = result & S16; + c = result & S16; result = (result << 1) | c1; - } - CHK_XXXW_ZS; /* set Z and S flags for result word */ + } + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (c) SET_C; - if ((result ^ dest) & S16) SET_V; + if ((result ^ dest) & S16) SET_V; return result; } @@ -803,8 +803,8 @@ INLINE UINT8 RRB(z8000_state *cpustate, UINT8 dest, UINT8 twice) UINT8 result = (dest >> 1) | (dest << 7); CLR_CZSV; if (twice) result = (result >> 1) | (result << 7); - if (!result) SET_Z; else if (result & S08) SET_SC; - if ((result ^ dest) & S08) SET_V; + if (!result) SET_Z; else if (result & S08) SET_SC; + if ((result ^ dest) & S08) SET_V; return result; } @@ -817,8 +817,8 @@ INLINE UINT16 RRW(z8000_state *cpustate, UINT16 dest, UINT8 twice) UINT16 result = (dest >> 1) | (dest << 15); CLR_CZSV; if (twice) result = (result >> 1) | (result << 15); - if (!result) SET_Z; else if (result & S16) SET_SC; - if ((result ^ dest) & S16) SET_V; + if (!result) SET_Z; else if (result & S16) SET_SC; + if ((result ^ dest) & S16) SET_V; return result; } @@ -836,9 +836,9 @@ INLINE UINT8 RRCB(z8000_state *cpustate, UINT8 dest, UINT8 twice) c = result & 1; result = (result >> 1) | c1; } - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (c) SET_C; - if ((result ^ dest) & S08) SET_V; + if ((result ^ dest) & S08) SET_V; return result; } @@ -855,10 +855,10 @@ INLINE UINT16 RRCW(z8000_state *cpustate, UINT16 dest, UINT8 twice) UINT16 c1 = c << 15; c = result & 1; result = (result >> 1) | c1; - } - CHK_XXXW_ZS; /* set Z and S flags for result word */ + } + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (c) SET_C; - if ((result ^ dest) & S16) SET_V; + if ((result ^ dest) & S16) SET_V; return result; } @@ -872,7 +872,7 @@ INLINE UINT8 SDAB(z8000_state *cpustate, UINT8 dest, INT8 count) UINT8 c = 0; CLR_CZSV; while (count > 0) { - c = result & S08; + c = result & S08; result <<= 1; count--; } @@ -881,9 +881,9 @@ INLINE UINT8 SDAB(z8000_state *cpustate, UINT8 dest, INT8 count) result >>= 1; count++; } - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (c) SET_C; - if ((result ^ dest) & S08) SET_V; + if ((result ^ dest) & S08) SET_V; return (UINT8)result; } @@ -897,7 +897,7 @@ INLINE UINT16 SDAW(z8000_state *cpustate, UINT16 dest, INT8 count) UINT16 c = 0; CLR_CZSV; while (count > 0) { - c = result & S16; + c = result & S16; result <<= 1; count--; } @@ -906,9 +906,9 @@ INLINE UINT16 SDAW(z8000_state *cpustate, UINT16 dest, INT8 count) result >>= 1; count++; } - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (c) SET_C; - if ((result ^ dest) & S16) SET_V; + if ((result ^ dest) & S16) SET_V; return (UINT16)result; } @@ -922,7 +922,7 @@ INLINE UINT32 SDAL(z8000_state *cpustate, UINT32 dest, INT8 count) UINT32 c = 0; CLR_CZSV; while (count > 0) { - c = result & S32; + c = result & S32; result <<= 1; count--; } @@ -931,9 +931,9 @@ INLINE UINT32 SDAL(z8000_state *cpustate, UINT32 dest, INT8 count) result >>= 1; count++; } - CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ if (c) SET_C; - if ((result ^ dest) & S32) SET_V; + if ((result ^ dest) & S32) SET_V; return (UINT32) result; } @@ -947,7 +947,7 @@ INLINE UINT8 SDLB(z8000_state *cpustate, UINT8 dest, INT8 count) UINT8 c = 0; CLR_CZSV; while (count > 0) { - c = result & S08; + c = result & S08; result <<= 1; count--; } @@ -956,9 +956,9 @@ INLINE UINT8 SDLB(z8000_state *cpustate, UINT8 dest, INT8 count) result >>= 1; count++; } - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (c) SET_C; - if ((result ^ dest) & S08) SET_V; + if ((result ^ dest) & S08) SET_V; return result; } @@ -970,9 +970,9 @@ INLINE UINT16 SDLW(z8000_state *cpustate, UINT16 dest, INT8 count) { UINT16 result = dest; UINT16 c = 0; - CLR_CZSV; + CLR_CZSV; while (count > 0) { - c = result & S16; + c = result & S16; result <<= 1; count--; } @@ -981,9 +981,9 @@ INLINE UINT16 SDLW(z8000_state *cpustate, UINT16 dest, INT8 count) result >>= 1; count++; } - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (c) SET_C; - if ((result ^ dest) & S16) SET_V; + if ((result ^ dest) & S16) SET_V; return result; } @@ -995,9 +995,9 @@ INLINE UINT32 SDLL(z8000_state *cpustate, UINT32 dest, INT8 count) { UINT32 result = dest; UINT32 c = 0; - CLR_CZSV; + CLR_CZSV; while (count > 0) { - c = result & S32; + c = result & S32; result <<= 1; count--; } @@ -1006,9 +1006,9 @@ INLINE UINT32 SDLL(z8000_state *cpustate, UINT32 dest, INT8 count) result >>= 1; count++; } - CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ if (c) SET_C; - if ((result ^ dest) & S32) SET_V; + if ((result ^ dest) & S32) SET_V; return result; } @@ -1018,12 +1018,12 @@ INLINE UINT32 SDLL(z8000_state *cpustate, UINT32 dest, INT8 count) ******************************************/ INLINE UINT8 SLAB(z8000_state *cpustate, UINT8 dest, UINT8 count) { - UINT8 c = (count) ? (dest << (count - 1)) & S08 : 0; + UINT8 c = (count) ? (dest << (count - 1)) & S08 : 0; UINT8 result = (UINT8)((INT8)dest << count); CLR_CZSV; - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (c) SET_C; - if ((result ^ dest) & S08) SET_V; + if ((result ^ dest) & S08) SET_V; return result; } @@ -1033,12 +1033,12 @@ INLINE UINT8 SLAB(z8000_state *cpustate, UINT8 dest, UINT8 count) ******************************************/ INLINE UINT16 SLAW(z8000_state *cpustate, UINT16 dest, UINT8 count) { - UINT16 c = (count) ? (dest << (count - 1)) & S16 : 0; + UINT16 c = (count) ? (dest << (count - 1)) & S16 : 0; UINT16 result = (UINT16)((INT16)dest << count); CLR_CZSV; - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (c) SET_C; - if ((result ^ dest) & S16) SET_V; + if ((result ^ dest) & S16) SET_V; return result; } @@ -1048,12 +1048,12 @@ INLINE UINT16 SLAW(z8000_state *cpustate, UINT16 dest, UINT8 count) ******************************************/ INLINE UINT32 SLAL(z8000_state *cpustate, UINT32 dest, UINT8 count) { - UINT32 c = (count) ? (dest << (count - 1)) & S32 : 0; + UINT32 c = (count) ? (dest << (count - 1)) & S32 : 0; UINT32 result = (UINT32)((INT32)dest << count); CLR_CZSV; - CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ if (c) SET_C; - if ((result ^ dest) & S32) SET_V; + if ((result ^ dest) & S32) SET_V; return result; } @@ -1063,10 +1063,10 @@ INLINE UINT32 SLAL(z8000_state *cpustate, UINT32 dest, UINT8 count) ******************************************/ INLINE UINT8 SLLB(z8000_state *cpustate, UINT8 dest, UINT8 count) { - UINT8 c = (count) ? (dest << (count - 1)) & S08 : 0; + UINT8 c = (count) ? (dest << (count - 1)) & S08 : 0; UINT8 result = dest << count; CLR_CZS; - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (c) SET_C; return result; } @@ -1077,10 +1077,10 @@ INLINE UINT8 SLLB(z8000_state *cpustate, UINT8 dest, UINT8 count) ******************************************/ INLINE UINT16 SLLW(z8000_state *cpustate, UINT16 dest, UINT8 count) { - UINT16 c = (count) ? (dest << (count - 1)) & S16 : 0; + UINT16 c = (count) ? (dest << (count - 1)) & S16 : 0; UINT16 result = dest << count; CLR_CZS; - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (c) SET_C; return result; } @@ -1091,10 +1091,10 @@ INLINE UINT16 SLLW(z8000_state *cpustate, UINT16 dest, UINT8 count) ******************************************/ INLINE UINT32 SLLL(z8000_state *cpustate, UINT32 dest, UINT8 count) { - UINT32 c = (count) ? (dest << (count - 1)) & S32 : 0; + UINT32 c = (count) ? (dest << (count - 1)) & S32 : 0; UINT32 result = dest << count; CLR_CZS; - CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ if (c) SET_C; return result; } @@ -1108,7 +1108,7 @@ INLINE UINT8 SRAB(z8000_state *cpustate, UINT8 dest, UINT8 count) UINT8 c = (count) ? ((INT8)dest >> (count - 1)) & 1 : 0; UINT8 result = (UINT8)((INT8)dest >> count); CLR_CZSV; - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (c) SET_C; return result; } @@ -1122,7 +1122,7 @@ INLINE UINT16 SRAW(z8000_state *cpustate, UINT16 dest, UINT8 count) UINT8 c = (count) ? ((INT16)dest >> (count - 1)) & 1 : 0; UINT16 result = (UINT16)((INT16)dest >> count); CLR_CZSV; - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (c) SET_C; return result; } @@ -1136,7 +1136,7 @@ INLINE UINT32 SRAL(z8000_state *cpustate, UINT32 dest, UINT8 count) UINT8 c = (count) ? ((INT32)dest >> (count - 1)) & 1 : 0; UINT32 result = (UINT32)((INT32)dest >> count); CLR_CZSV; - CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ if (c) SET_C; return result; } @@ -1150,7 +1150,7 @@ INLINE UINT8 SRLB(z8000_state *cpustate, UINT8 dest, UINT8 count) UINT8 c = (count) ? (dest >> (count - 1)) & 1 : 0; UINT8 result = dest >> count; CLR_CZS; - CHK_XXXB_ZS; /* set Z and S flags for result byte */ + CHK_XXXB_ZS; /* set Z and S flags for result byte */ if (c) SET_C; return result; } @@ -1164,7 +1164,7 @@ INLINE UINT16 SRLW(z8000_state *cpustate, UINT16 dest, UINT8 count) UINT8 c = (count) ? (dest >> (count - 1)) & 1 : 0; UINT16 result = dest >> count; CLR_CZS; - CHK_XXXW_ZS; /* set Z and S flags for result word */ + CHK_XXXW_ZS; /* set Z and S flags for result word */ if (c) SET_C; return result; } @@ -1178,7 +1178,7 @@ INLINE UINT32 SRLL(z8000_state *cpustate, UINT32 dest, UINT8 count) UINT8 c = (count) ? (dest >> (count - 1)) & 1 : 0; UINT32 result = dest >> count; CLR_CZS; - CHK_XXXL_ZS; /* set Z and S flags for result long */ + CHK_XXXL_ZS; /* set Z and S flags for result long */ if (c) SET_C; return result; } @@ -1485,7 +1485,7 @@ static void Z0C_ddN0_0001_imm8(z8000_state *cpustate) static void Z0C_ddN0_0010(z8000_state *cpustate) { GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_B(cpustate, AS_DATA, addr, NEGB(cpustate, RDMEM_B(cpustate, AS_DATA, addr))); } @@ -1517,9 +1517,9 @@ static void Z0C_ddN0_0101_imm8(z8000_state *cpustate) static void Z0C_ddN0_0110(z8000_state *cpustate) { GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); - if (RDMEM_B(cpustate, AS_DATA, addr) & S08) SET_S; else CLR_S; - WRMEM_B(cpustate, AS_DATA, addr, 0xff); + UINT32 addr = addr_from_reg(cpustate, dst); + if (RDMEM_B(cpustate, AS_DATA, addr) & S08) SET_S; else CLR_S; + WRMEM_B(cpustate, AS_DATA, addr, 0xff); } /****************************************** @@ -1539,7 +1539,7 @@ static void Z0C_ddN0_1000(z8000_state *cpustate) static void Z0D_ddN0_0000(z8000_state *cpustate) { GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_W(cpustate, AS_DATA, addr, COMW(cpustate, RDMEM_W(cpustate, AS_DATA, addr))); } @@ -1561,7 +1561,7 @@ static void Z0D_ddN0_0001_imm16(z8000_state *cpustate) static void Z0D_ddN0_0010(z8000_state *cpustate) { GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_W(cpustate, AS_DATA, addr, NEGW(cpustate, RDMEM_W(cpustate, AS_DATA, addr))); } @@ -1593,9 +1593,9 @@ static void Z0D_ddN0_0101_imm16(z8000_state *cpustate) static void Z0D_ddN0_0110(z8000_state *cpustate) { GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); - if (RDMEM_W(cpustate, AS_DATA, addr) & S16) SET_S; else CLR_S; - WRMEM_W(cpustate, AS_DATA, addr, 0xffff); + UINT32 addr = addr_from_reg(cpustate, dst); + if (RDMEM_W(cpustate, AS_DATA, addr) & S16) SET_S; else CLR_S; + WRMEM_W(cpustate, AS_DATA, addr, 0xffff); } /****************************************** @@ -1625,10 +1625,10 @@ static void Z0D_ddN0_1001_imm16(z8000_state *cpustate) ******************************************/ static void Z0E_imm8(z8000_state *cpustate) { - CHECK_EXT_INSTR(); + CHECK_EXT_INSTR(); GET_IMM8(0); LOG(("Z8K '%s' %04x: ext0e $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; } @@ -1640,13 +1640,13 @@ static void Z0E_imm8(z8000_state *cpustate) ******************************************/ static void Z0F_imm8(z8000_state *cpustate) { - CHECK_EXT_INSTR(); + CHECK_EXT_INSTR(); GET_IMM8(0); LOG(("Z8K '%s' %04x: ext0f $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -1885,15 +1885,15 @@ static void Z1C_ddN0_1000(z8000_state *cpustate) ******************************************/ static void Z1C_ddN0_1001_0000_ssss_0000_nmin1(z8000_state *cpustate) { - GET_DST(OP0,NIB2); - GET_CNT(OP1,NIB3); - GET_SRC(OP1,NIB1); + GET_DST(OP0,NIB2); + GET_CNT(OP1,NIB3); + GET_SRC(OP1,NIB1); UINT32 addr = addr_from_reg(cpustate, dst); - while (cnt-- >= 0) { - WRMEM_W(cpustate, AS_DATA, addr, cpustate->RW(src)); + while (cnt-- >= 0) { + WRMEM_W(cpustate, AS_DATA, addr, cpustate->RW(src)); addr = addr_add(cpustate, addr, 2); src = (src+1) & 15; - } + } } /****************************************** @@ -1910,7 +1910,7 @@ static void Z1C_ssN0_0001_0000_dddd_0000_nmin1(z8000_state *cpustate) cpustate->RW(dst) = RDMEM_W(cpustate, AS_DATA, addr); addr = addr_add(cpustate, addr, 2); dst = (dst+1) & 15; - } + } } /****************************************** @@ -1959,11 +1959,11 @@ static void Z1E_ddN0_cccc(z8000_state *cpustate) static void Z1F_ddN0_0000(z8000_state *cpustate) { GET_DST(OP0,NIB2); - if (segmented_mode(cpustate)) - PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); - else - PUSHW(cpustate, SP, cpustate->pc); - set_pc(cpustate, addr_from_reg(cpustate, dst)); + if (segmented_mode(cpustate)) + PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); + else + PUSHW(cpustate, SP, cpustate->pc); + set_pc(cpustate, addr_from_reg(cpustate, dst)); } /****************************************** @@ -1974,7 +1974,7 @@ static void Z20_ssN0_dddd(z8000_state *cpustate) { GET_DST(OP0,NIB3); GET_SRC(OP0,NIB2); - cpustate->RB(dst) = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src)); + cpustate->RB(dst) = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src)); } /****************************************** @@ -2018,7 +2018,7 @@ static void Z22_ddN0_imm4(z8000_state *cpustate) { GET_BIT(OP0); GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_B(cpustate, AS_DATA, addr, RDMEM_B(cpustate, AS_DATA, addr) & ~bit); } @@ -2041,7 +2041,7 @@ static void Z23_ddN0_imm4(z8000_state *cpustate) { GET_BIT(OP0); GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_W(cpustate, AS_DATA, addr, RDMEM_W(cpustate, AS_DATA, addr) & ~bit); } @@ -2064,7 +2064,7 @@ static void Z24_ddN0_imm4(z8000_state *cpustate) { GET_BIT(OP0); GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_B(cpustate, AS_DATA, addr, RDMEM_B(cpustate, AS_DATA, addr) | bit); } @@ -2087,7 +2087,7 @@ static void Z25_ddN0_imm4(z8000_state *cpustate) { GET_BIT(OP0); GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_W(cpustate, AS_DATA, addr, RDMEM_W(cpustate, AS_DATA, addr) | bit); } @@ -2143,7 +2143,7 @@ static void Z28_ddN0_imm4m1(z8000_state *cpustate) { GET_I4M1(OP0,NIB3); GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_B(cpustate, AS_DATA, addr, INCB(cpustate, RDMEM_B(cpustate, AS_DATA, addr), i4p1)); } @@ -2155,7 +2155,7 @@ static void Z29_ddN0_imm4m1(z8000_state *cpustate) { GET_I4M1(OP0,NIB3); GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_W(cpustate, AS_DATA, addr, INCW(cpustate, RDMEM_W(cpustate, AS_DATA, addr), i4p1)); } @@ -2167,7 +2167,7 @@ static void Z2A_ddN0_imm4m1(z8000_state *cpustate) { GET_I4M1(OP0,NIB3); GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_B(cpustate, AS_DATA, addr, DECB(cpustate, RDMEM_B(cpustate, AS_DATA, addr), i4p1)); } @@ -2179,7 +2179,7 @@ static void Z2B_ddN0_imm4m1(z8000_state *cpustate) { GET_I4M1(OP0,NIB3); GET_DST(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, dst); + UINT32 addr = addr_from_reg(cpustate, dst); WRMEM_W(cpustate, AS_DATA, addr, DECW(cpustate, RDMEM_W(cpustate, AS_DATA, addr), i4p1)); } @@ -2191,7 +2191,7 @@ static void Z2C_ssN0_dddd(z8000_state *cpustate) { GET_DST(OP0,NIB3); GET_SRC(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, src); + UINT32 addr = addr_from_reg(cpustate, src); UINT8 tmp = RDMEM_B(cpustate, AS_DATA, addr); WRMEM_B(cpustate, AS_DATA, addr, cpustate->RB(dst)); cpustate->RB(dst) = tmp; @@ -2205,7 +2205,7 @@ static void Z2D_ssN0_dddd(z8000_state *cpustate) { GET_DST(OP0,NIB3); GET_SRC(OP0,NIB2); - UINT32 addr = addr_from_reg(cpustate, src); + UINT32 addr = addr_from_reg(cpustate, src); UINT16 tmp = RDMEM_W(cpustate, AS_DATA, addr); WRMEM_W(cpustate, AS_DATA, addr, cpustate->RW(dst)); cpustate->RW(dst) = tmp; @@ -2400,10 +2400,10 @@ static void Z36_imm8(z8000_state *cpustate) { GET_IMM8(0); LOG(("Z8K '%s' %04x: rsvd36 $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -2438,10 +2438,10 @@ static void Z38_imm8(z8000_state *cpustate) { GET_IMM8(0); LOG(("Z8K '%s' %04x: rsvd38 $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -2450,18 +2450,18 @@ static void Z38_imm8(z8000_state *cpustate) ******************************************/ static void Z39_ssN0_0000(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); UINT16 fcw; - if (segmented_mode(cpustate)) { - UINT32 addr = addr_from_reg(cpustate, src); - fcw = RDMEM_W(cpustate, AS_DATA, addr + 2); - set_pc(cpustate, segmented_addr(RDMEM_L(cpustate, AS_DATA, addr + 4))); - } - else { - fcw = RDMEM_W(cpustate, AS_DATA, cpustate->RW(src)); - set_pc(cpustate, RDMEM_W(cpustate, AS_DATA, (UINT16)(cpustate->RW(src) + 2))); - } + if (segmented_mode(cpustate)) { + UINT32 addr = addr_from_reg(cpustate, src); + fcw = RDMEM_W(cpustate, AS_DATA, addr + 2); + set_pc(cpustate, segmented_addr(RDMEM_L(cpustate, AS_DATA, addr + 4))); + } + else { + fcw = RDMEM_W(cpustate, AS_DATA, cpustate->RW(src)); + set_pc(cpustate, RDMEM_W(cpustate, AS_DATA, (UINT16)(cpustate->RW(src) + 2))); + } if ((fcw ^ cpustate->fcw) & F_SEG) printf("ldps 1 (0x%05x): changing from %ssegmented mode to %ssegmented mode\n", cpustate->pc, (fcw & F_SEG) ? "non-" : "", (fcw & F_SEG) ? "" : "non-"); CHANGE_FCW(cpustate, fcw); /* check for user/system mode change */ } @@ -2472,12 +2472,12 @@ static void Z39_ssN0_0000(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_0000_0000_aaaa_dddd_x000(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); - GET_DST(OP1,NIB2); - GET_CCC(OP1,NIB3); - WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), RDPORT_B(cpustate, 0, cpustate->RW(src))); + CHECK_PRIVILEGED_INSTR(); + GET_SRC(OP0,NIB2); + GET_CNT(OP1,NIB1); + GET_DST(OP1,NIB2); + GET_CCC(OP1,NIB3); + WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), RDPORT_B(cpustate, 0, cpustate->RW(src))); add_to_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; } @@ -2489,14 +2489,14 @@ static void Z3A_ssss_0000_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_0001_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@@ - CHECK_PRIVILEGED_INSTR(); - GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); - GET_DST(OP1,NIB2); - GET_CCC(OP1,NIB3); - WRMEM_B(cpustate, AS_DATA, cpustate->RW(dst), RDPORT_B(cpustate, 1, cpustate->RW(src))); - cpustate->RW(dst)++; - cpustate->RW(src)++; + CHECK_PRIVILEGED_INSTR(); + GET_SRC(OP0,NIB2); + GET_CNT(OP1,NIB1); + GET_DST(OP1,NIB2); + GET_CCC(OP1,NIB3); + WRMEM_B(cpustate, AS_DATA, cpustate->RW(dst), RDPORT_B(cpustate, 1, cpustate->RW(src))); + cpustate->RW(dst)++; + cpustate->RW(src)++; if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; } @@ -2507,12 +2507,12 @@ static void Z3A_ssss_0001_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_0010_0000_aaaa_dddd_x000(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); - GET_DST(OP1,NIB2); - GET_CCC(OP1,NIB3); - WRPORT_B(cpustate, 0, cpustate->RW(dst), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); + CHECK_PRIVILEGED_INSTR(); + GET_SRC(OP0,NIB2); + GET_CNT(OP1,NIB1); + GET_DST(OP1,NIB2); + GET_CCC(OP1,NIB3); + WRPORT_B(cpustate, 0, cpustate->RW(dst), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); add_to_addr_reg(cpustate, src, 1); if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; } @@ -2524,14 +2524,14 @@ static void Z3A_ssss_0010_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_0011_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@@ - CHECK_PRIVILEGED_INSTR(); - GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); - GET_DST(OP1,NIB2); - GET_CCC(OP1,NIB3); - WRPORT_B(cpustate, 1, cpustate->RW(dst), RDMEM_B(cpustate, AS_DATA, cpustate->RW(src))); - cpustate->RW(dst)++; - cpustate->RW(src)++; + CHECK_PRIVILEGED_INSTR(); + GET_SRC(OP0,NIB2); + GET_CNT(OP1,NIB1); + GET_DST(OP1,NIB2); + GET_CCC(OP1,NIB3); + WRPORT_B(cpustate, 1, cpustate->RW(dst), RDMEM_B(cpustate, AS_DATA, cpustate->RW(src))); + cpustate->RW(dst)++; + cpustate->RW(src)++; if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; } @@ -2541,10 +2541,10 @@ static void Z3A_ssss_0011_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3A_dddd_0100_imm16(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_DST(OP0,NIB2); - GET_IMM16(OP1); - cpustate->RB(dst) = RDPORT_B(cpustate, 0, imm16); + CHECK_PRIVILEGED_INSTR(); + GET_DST(OP0,NIB2); + GET_IMM16(OP1); + cpustate->RB(dst) = RDPORT_B(cpustate, 0, imm16); } /****************************************** @@ -2553,10 +2553,10 @@ static void Z3A_dddd_0100_imm16(z8000_state *cpustate) ******************************************/ static void Z3A_dddd_0101_imm16(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_DST(OP0,NIB2); - GET_IMM16(OP1); - cpustate->RB(dst) = RDPORT_B(cpustate, 1, imm16); + CHECK_PRIVILEGED_INSTR(); + GET_DST(OP0,NIB2); + GET_IMM16(OP1); + cpustate->RB(dst) = RDPORT_B(cpustate, 1, imm16); } /****************************************** @@ -2565,10 +2565,10 @@ static void Z3A_dddd_0101_imm16(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_0110_imm16(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_SRC(OP0,NIB2); - GET_IMM16(OP1); - WRPORT_B(cpustate, 0, imm16, cpustate->RB(src)); + CHECK_PRIVILEGED_INSTR(); + GET_SRC(OP0,NIB2); + GET_IMM16(OP1); + WRPORT_B(cpustate, 0, imm16, cpustate->RB(src)); } /****************************************** @@ -2577,10 +2577,10 @@ static void Z3A_ssss_0110_imm16(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_0111_imm16(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_SRC(OP0,NIB2); - GET_IMM16(OP1); - WRPORT_B(cpustate, 1, imm16, cpustate->RB(src)); + CHECK_PRIVILEGED_INSTR(); + GET_SRC(OP0,NIB2); + GET_IMM16(OP1); + WRPORT_B(cpustate, 1, imm16, cpustate->RB(src)); } /****************************************** @@ -2590,7 +2590,7 @@ static void Z3A_ssss_0111_imm16(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_1000_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); @@ -2608,7 +2608,7 @@ static void Z3A_ssss_1000_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_1001_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); @@ -2626,7 +2626,7 @@ static void Z3A_ssss_1001_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_1010_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); @@ -2644,7 +2644,7 @@ static void Z3A_ssss_1010_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3A_ssss_1011_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); @@ -2662,9 +2662,9 @@ static void Z3A_ssss_1011_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_0000_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRMEM_W(cpustate, AS_DATA, cpustate->RW(dst), RDPORT_W(cpustate, 0, cpustate->RW(src))); @@ -2680,9 +2680,9 @@ static void Z3B_ssss_0000_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_0001_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRMEM_W(cpustate, AS_DATA, cpustate->RW(dst), RDPORT_W(cpustate, 1, cpustate->RW(src))); @@ -2698,9 +2698,9 @@ static void Z3B_ssss_0001_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_0010_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRPORT_W(cpustate, 0, cpustate->RW(dst), RDMEM_W(cpustate, AS_DATA, cpustate->RW(src))); @@ -2716,9 +2716,9 @@ static void Z3B_ssss_0010_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_0011_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRPORT_W(cpustate, 1, cpustate->RW(dst), RDMEM_W(cpustate, AS_DATA, cpustate->RW(src))); @@ -2733,9 +2733,9 @@ static void Z3B_ssss_0011_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3B_dddd_0100_imm16(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_DST(OP0,NIB2); - GET_IMM16(OP1); + CHECK_PRIVILEGED_INSTR(); + GET_DST(OP0,NIB2); + GET_IMM16(OP1); cpustate->RW(dst) = RDPORT_W(cpustate, 0, imm16); } @@ -2745,9 +2745,9 @@ static void Z3B_dddd_0100_imm16(z8000_state *cpustate) ******************************************/ static void Z3B_dddd_0101_imm16(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_DST(OP0,NIB2); - GET_IMM16(OP1); + CHECK_PRIVILEGED_INSTR(); + GET_DST(OP0,NIB2); + GET_IMM16(OP1); cpustate->RW(dst) = RDPORT_W(cpustate, 1, imm16); } @@ -2757,9 +2757,9 @@ static void Z3B_dddd_0101_imm16(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_0110_imm16(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_SRC(OP0,NIB2); - GET_IMM16(OP1); + CHECK_PRIVILEGED_INSTR(); + GET_SRC(OP0,NIB2); + GET_IMM16(OP1); WRPORT_W(cpustate, 0, imm16, cpustate->RW(src)); } @@ -2769,9 +2769,9 @@ static void Z3B_ssss_0110_imm16(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_0111_imm16(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); - GET_SRC(OP0,NIB2); - GET_IMM16(OP1); + CHECK_PRIVILEGED_INSTR(); + GET_SRC(OP0,NIB2); + GET_IMM16(OP1); WRPORT_W(cpustate, 1, imm16, cpustate->RW(src)); } @@ -2782,9 +2782,9 @@ static void Z3B_ssss_0111_imm16(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_1000_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRMEM_W(cpustate, AS_DATA, cpustate->RW(dst), RDPORT_W(cpustate, 0, cpustate->RW(src))); @@ -2800,9 +2800,9 @@ static void Z3B_ssss_1000_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_1001_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRMEM_W(cpustate, AS_DATA, cpustate->RW(dst), RDPORT_W(cpustate, 1, cpustate->RW(src))); @@ -2818,9 +2818,9 @@ static void Z3B_ssss_1001_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_1010_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRPORT_W(cpustate, 0, cpustate->RW(dst), RDMEM_W(cpustate, AS_DATA, cpustate->RW(src))); @@ -2836,9 +2836,9 @@ static void Z3B_ssss_1010_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3B_ssss_1011_0000_aaaa_dddd_x000(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRPORT_W(cpustate, 1, cpustate->RW(dst), RDMEM_W(cpustate, AS_DATA, cpustate->RW(src))); @@ -2853,7 +2853,7 @@ static void Z3B_ssss_1011_0000_aaaa_dddd_x000(z8000_state *cpustate) ******************************************/ static void Z3C_ssss_dddd(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); GET_DST(OP0,NIB3); cpustate->RB(dst) = RDPORT_B(cpustate, 0, cpustate->RW(src)); @@ -2865,7 +2865,7 @@ static void Z3C_ssss_dddd(z8000_state *cpustate) ******************************************/ static void Z3D_ssss_dddd(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); GET_DST(OP0,NIB3); cpustate->RW(dst) = RDPORT_W(cpustate, 0, cpustate->RW(src)); @@ -2877,7 +2877,7 @@ static void Z3D_ssss_dddd(z8000_state *cpustate) ******************************************/ static void Z3E_dddd_ssss(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_DST(OP0,NIB2); GET_SRC(OP0,NIB3); WRPORT_B(cpustate, 0, cpustate->RW(dst), cpustate->RB(src)); @@ -2889,7 +2889,7 @@ static void Z3E_dddd_ssss(z8000_state *cpustate) ******************************************/ static void Z3F_dddd_ssss(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_DST(OP0,NIB2); GET_SRC(OP0,NIB3); WRPORT_W(cpustate, 0, cpustate->RW(dst), cpustate->RW(src)); @@ -2940,7 +2940,7 @@ static void Z41_ssN0_dddd_addr(z8000_state *cpustate) GET_SRC(OP0,NIB2); GET_ADDR(OP1); addr = addr_add(cpustate, addr, cpustate->RW(src)); - cpustate->RW(dst) = ADDW(cpustate, cpustate->RW(dst), RDMEM_W(cpustate, AS_DATA, addr)); /* ASG */ + cpustate->RW(dst) = ADDW(cpustate, cpustate->RW(dst), RDMEM_W(cpustate, AS_DATA, addr)); /* ASG */ } /****************************************** @@ -3242,8 +3242,8 @@ static void Z4C_0000_0101_addr_imm8(z8000_state *cpustate) static void Z4C_0000_0110_addr(z8000_state *cpustate) { GET_ADDR(OP1); - if (RDMEM_B(cpustate, AS_DATA, addr) & S08) SET_S; else CLR_S; - WRMEM_B(cpustate, AS_DATA, addr, 0xff); + if (RDMEM_B(cpustate, AS_DATA, addr) & S08) SET_S; else CLR_S; + WRMEM_B(cpustate, AS_DATA, addr, 0xff); } /****************************************** @@ -3327,8 +3327,8 @@ static void Z4C_ddN0_0110_addr(z8000_state *cpustate) GET_DST(OP0,NIB2); GET_ADDR(OP1); addr = addr_add(cpustate, addr, cpustate->RW(dst)); - if (RDMEM_B(cpustate, AS_DATA, addr) & S08) SET_S; else CLR_S; - WRMEM_B(cpustate, AS_DATA, addr, 0xff); + if (RDMEM_B(cpustate, AS_DATA, addr) & S08) SET_S; else CLR_S; + WRMEM_B(cpustate, AS_DATA, addr, 0xff); } /****************************************** @@ -3402,8 +3402,8 @@ static void Z4D_0000_0101_addr_imm16(z8000_state *cpustate) static void Z4D_0000_0110_addr(z8000_state *cpustate) { GET_ADDR(OP1); - if (RDMEM_W(cpustate, AS_DATA, addr) & S16) SET_S; else CLR_S; - WRMEM_W(cpustate, AS_DATA, addr, 0xffff); + if (RDMEM_W(cpustate, AS_DATA, addr) & S16) SET_S; else CLR_S; + WRMEM_W(cpustate, AS_DATA, addr, 0xffff); } /****************************************** @@ -3487,8 +3487,8 @@ static void Z4D_ddN0_0110_addr(z8000_state *cpustate) GET_DST(OP0,NIB2); GET_ADDR(OP1); addr = addr_add(cpustate, addr, cpustate->RW(dst)); - if (RDMEM_W(cpustate, AS_DATA, addr) & S16) SET_S; else CLR_S; - WRMEM_W(cpustate, AS_DATA, addr, 0xffff); + if (RDMEM_W(cpustate, AS_DATA, addr) & S16) SET_S; else CLR_S; + WRMEM_W(cpustate, AS_DATA, addr, 0xffff); } /****************************************** @@ -3816,7 +3816,7 @@ static void Z5C_0000_0001_0000_dddd_0000_nmin1_addr(z8000_state *cpustate) while (cnt-- >= 0) { cpustate->RW(dst) = RDMEM_W(cpustate, AS_DATA, addr); dst = (dst+1) & 15; - addr = addr_add (cpustate, addr, 2); + addr = addr_add (cpustate, addr, 2); } } @@ -3842,7 +3842,7 @@ static void Z5C_0000_1001_0000_ssss_0000_nmin1_addr(z8000_state *cpustate) while (cnt-- >= 0) { WRMEM_W(cpustate, AS_DATA, addr, cpustate->RW(src)); src = (src+1) & 15; - addr = addr_add (cpustate, addr, 2); + addr = addr_add (cpustate, addr, 2); } } @@ -3983,10 +3983,10 @@ static void Z5E_ddN0_cccc_addr(z8000_state *cpustate) static void Z5F_0000_0000_addr(z8000_state *cpustate) { GET_ADDR(OP1); - if (segmented_mode(cpustate)) - PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); - else - PUSHW(cpustate, SP, cpustate->pc); + if (segmented_mode(cpustate)) + PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); + else + PUSHW(cpustate, SP, cpustate->pc); set_pc(cpustate, addr); } @@ -3998,10 +3998,10 @@ static void Z5F_ddN0_0000_addr(z8000_state *cpustate) { GET_DST(OP0,NIB2); GET_ADDR(OP1); - if (segmented_mode(cpustate)) - PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); - else - PUSHW(cpustate, SP, cpustate->pc); + if (segmented_mode(cpustate)) + PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); + else + PUSHW(cpustate, SP, cpustate->pc); addr = addr_add(cpustate, addr, cpustate->RW(dst)); set_pc(cpustate, addr); } @@ -4171,7 +4171,7 @@ static void Z66_ddN0_imm4_addr(z8000_state *cpustate) GET_DST(OP0,NIB2); GET_ADDR(OP1); addr = addr_add(cpustate, addr, cpustate->RW(dst)); - if (RDMEM_B(cpustate, AS_DATA, addr) & bit) CLR_Z; else SET_Z; + if (RDMEM_B(cpustate, AS_DATA, addr) & bit) CLR_Z; else SET_Z; } /****************************************** @@ -4320,7 +4320,7 @@ static void Z6C_ssN0_dddd_addr(z8000_state *cpustate) addr = addr_add(cpustate, addr, cpustate->RW(src)); tmp = RDMEM_B(cpustate, AS_DATA, addr); WRMEM_B(cpustate, AS_DATA, addr, cpustate->RB(dst)); - cpustate->RB(dst) = tmp; + cpustate->RB(dst) = tmp; } /****************************************** @@ -4349,7 +4349,7 @@ static void Z6D_ssN0_dddd_addr(z8000_state *cpustate) addr = addr_add(cpustate, addr, cpustate->RW(src)); tmp = RDMEM_W(cpustate, AS_DATA, addr); WRMEM_W(cpustate, AS_DATA, addr, cpustate->RW(dst)); - cpustate->RW(dst) = tmp; + cpustate->RW(dst) = tmp; } /****************************************** @@ -4532,10 +4532,10 @@ static void Z78_imm8(z8000_state *cpustate) { GET_IMM8(0); LOG(("Z8K '%s' %04x: rsvd78 $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -4544,7 +4544,7 @@ static void Z78_imm8(z8000_state *cpustate) ******************************************/ static void Z79_0000_0000_addr(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_ADDR(OP1); UINT16 fcw; if (segmented_mode(cpustate)) { @@ -4564,19 +4564,19 @@ static void Z79_0000_0000_addr(z8000_state *cpustate) ******************************************/ static void Z79_ssN0_0000_addr(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_SRC(OP0,NIB2); GET_ADDR(OP1); UINT16 fcw; addr = addr_add(cpustate, addr, cpustate->RW(src)); - if (segmented_mode(cpustate)) { - fcw = RDMEM_W(cpustate, AS_DATA, addr + 2); - set_pc(cpustate, segmented_addr(RDMEM_L(cpustate, AS_DATA, addr + 4))); - } - else { - fcw = RDMEM_W(cpustate, AS_DATA, addr); - cpustate->pc = RDMEM_W(cpustate, AS_DATA, (UINT16)(addr + 2)); - } + if (segmented_mode(cpustate)) { + fcw = RDMEM_W(cpustate, AS_DATA, addr + 2); + set_pc(cpustate, segmented_addr(RDMEM_L(cpustate, AS_DATA, addr + 4))); + } + else { + fcw = RDMEM_W(cpustate, AS_DATA, addr); + cpustate->pc = RDMEM_W(cpustate, AS_DATA, (UINT16)(addr + 2)); + } if ((fcw ^ cpustate->fcw) & F_SEG) printf("ldps 3 (0x%05x): changing from %ssegmented mode to %ssegmented mode\n", cpustate->pc, (fcw & F_SEG) ? "non-" : "", (fcw & F_SEG) ? "" : "non-"); CHANGE_FCW(cpustate, fcw); /* check for user/system mode change */ } @@ -4587,7 +4587,7 @@ static void Z79_ssN0_0000_addr(z8000_state *cpustate) ******************************************/ static void Z7A_0000_0000(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); cpustate->irq_req |= Z8000_HALT; if (cpustate->icount > 0) cpustate->icount = 0; } @@ -4599,15 +4599,15 @@ static void Z7A_0000_0000(z8000_state *cpustate) static void Z7B_0000_0000(z8000_state *cpustate) { UINT16 tag, fcw; - CHECK_PRIVILEGED_INSTR(); - tag = POPW(cpustate, SP); /* get type tag */ - fcw = POPW(cpustate, SP); /* get cpustate->fcw */ - if (segmented_mode(cpustate)) - set_pc(cpustate, segmented_addr(POPL(cpustate, SP))); - else - cpustate->pc = POPW(cpustate, SP); /* get cpustate->pc */ - cpustate->irq_srv &= ~tag; /* remove IRQ serviced flag */ - CHANGE_FCW(cpustate, fcw); /* check for user/system mode change */ + CHECK_PRIVILEGED_INSTR(); + tag = POPW(cpustate, SP); /* get type tag */ + fcw = POPW(cpustate, SP); /* get cpustate->fcw */ + if (segmented_mode(cpustate)) + set_pc(cpustate, segmented_addr(POPL(cpustate, SP))); + else + cpustate->pc = POPW(cpustate, SP); /* get cpustate->pc */ + cpustate->irq_srv &= ~tag; /* remove IRQ serviced flag */ + CHANGE_FCW(cpustate, fcw); /* check for user/system mode change */ LOG(("Z8K '%s' IRET tag $%04x, fcw $%04x, pc $%04x\n", cpustate->device->tag(), tag, fcw, cpustate->pc)); } @@ -4617,7 +4617,7 @@ static void Z7B_0000_0000(z8000_state *cpustate) ******************************************/ static void Z7B_0000_1000(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); /* set mu-0 line */ } @@ -4627,7 +4627,7 @@ static void Z7B_0000_1000(z8000_state *cpustate) ******************************************/ static void Z7B_0000_1001(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); /* reset mu-0 line */ } @@ -4637,7 +4637,7 @@ static void Z7B_0000_1001(z8000_state *cpustate) ******************************************/ static void Z7B_0000_1010(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); /* test mu-I line */ } @@ -4647,7 +4647,7 @@ static void Z7B_0000_1010(z8000_state *cpustate) ******************************************/ static void Z7B_dddd_1101(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); /* test mu-I line, invert cascade to mu-0 */ } @@ -4657,7 +4657,7 @@ static void Z7B_dddd_1101(z8000_state *cpustate) ******************************************/ static void Z7C_0000_00ii(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_IMM2(OP0,NIB3); UINT16 fcw = cpustate->fcw; fcw &= (imm2 << 11) | 0xe7ff; @@ -4670,7 +4670,7 @@ static void Z7C_0000_00ii(z8000_state *cpustate) ******************************************/ static void Z7C_0000_01ii(z8000_state *cpustate) { - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_IMM2(OP0,NIB3); UINT16 fcw = cpustate->fcw; fcw |= ((~imm2) << 11) & 0x1800; @@ -4683,7 +4683,7 @@ static void Z7C_0000_01ii(z8000_state *cpustate) ******************************************/ static void Z7D_dddd_0ccc(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_IMM3(OP0,NIB3); GET_DST(OP0,NIB2); switch (imm3) { @@ -4707,7 +4707,7 @@ static void Z7D_dddd_0ccc(z8000_state *cpustate) break; default: LOG(("Z8K '%s' LDCTL R%d,%d\n", cpustate->device->tag(), dst, imm3)); - } + } } /****************************************** @@ -4716,7 +4716,7 @@ static void Z7D_dddd_0ccc(z8000_state *cpustate) ******************************************/ static void Z7D_ssss_1ccc(z8000_state *cpustate) {//@@@ - CHECK_PRIVILEGED_INSTR(); + CHECK_PRIVILEGED_INSTR(); GET_IMM3(OP0,NIB3); GET_SRC(OP0,NIB2); switch (imm3) { @@ -4726,7 +4726,7 @@ static void Z7D_ssss_1ccc(z8000_state *cpustate) fcw = cpustate->RW(src); CHANGE_FCW(cpustate, fcw); /* check for user/system mode change */ } - break; + break; case 3: cpustate->refresh = cpustate->RW(src); break; @@ -4744,7 +4744,7 @@ static void Z7D_ssss_1ccc(z8000_state *cpustate) break; default: LOG(("Z8K '%s' LDCTL %d,R%d\n", cpustate->device->tag(), imm3, src)); - } + } } /****************************************** @@ -4755,10 +4755,10 @@ static void Z7E_imm8(z8000_state *cpustate) { GET_IMM8(0); LOG(("Z8K '%s' %04x: rsvd7e $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -4767,7 +4767,7 @@ static void Z7E_imm8(z8000_state *cpustate) ******************************************/ static void Z7F_imm8(z8000_state *cpustate) { - GET_IMM8(0); + GET_IMM8(0); /* execute system call via IRQ */ cpustate->irq_req = Z8000_SYSCALL | imm8; @@ -4942,8 +4942,8 @@ static void Z8C_dddd_0100(z8000_state *cpustate) static void Z8C_dddd_0110(z8000_state *cpustate) { GET_DST(OP0,NIB2); - if (cpustate->RB(dst) & S08) SET_S; else CLR_S; - cpustate->RB(dst) = 0xff; + if (cpustate->RB(dst) & S08) SET_S; else CLR_S; + cpustate->RB(dst) = 0xff; } /****************************************** @@ -4973,8 +4973,8 @@ static void Z8C_dddd_1000(z8000_state *cpustate) static void Z8C_dddd_1001(z8000_state *cpustate) { GET_DST(OP0,NIB2); - cpustate->fcw &= ~0x00fc; - cpustate->fcw |= (cpustate->RB(dst) & 0xfc); + cpustate->fcw &= ~0x00fc; + cpustate->fcw |= (cpustate->RB(dst) & 0xfc); } /****************************************** @@ -5023,8 +5023,8 @@ static void Z8D_dddd_0100(z8000_state *cpustate) static void Z8D_dddd_0110(z8000_state *cpustate) { GET_DST(OP0,NIB2); - if (cpustate->RW(dst) & S16) SET_S; else CLR_S; - cpustate->RW(dst) = 0xffff; + if (cpustate->RW(dst) & S16) SET_S; else CLR_S; + cpustate->RW(dst) = 0xffff; } /****************************************** @@ -5070,13 +5070,13 @@ static void Z8D_imm4_0101(z8000_state *cpustate) ******************************************/ static void Z8E_imm8(z8000_state *cpustate) { - CHECK_EXT_INSTR(); + CHECK_EXT_INSTR(); GET_IMM8(0); LOG(("Z8K '%s' %04x: ext8e $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -5085,13 +5085,13 @@ static void Z8E_imm8(z8000_state *cpustate) ******************************************/ static void Z8F_imm8(z8000_state *cpustate) { - CHECK_EXT_INSTR(); + CHECK_EXT_INSTR(); GET_IMM8(0); LOG(("Z8K '%s' %04x: ext8f $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -5100,9 +5100,9 @@ static void Z8F_imm8(z8000_state *cpustate) ******************************************/ static void Z90_ssss_dddd(z8000_state *cpustate) { - GET_DST(OP0,NIB3); - GET_SRC(OP0,NIB2); - CPL(cpustate, cpustate->RL(dst), cpustate->RL(src)); + GET_DST(OP0,NIB3); + GET_SRC(OP0,NIB2); + CPL(cpustate, cpustate->RL(dst), cpustate->RL(src)); } /****************************************** @@ -5111,9 +5111,9 @@ static void Z90_ssss_dddd(z8000_state *cpustate) ******************************************/ static void Z91_ddN0_ssss(z8000_state *cpustate) { - GET_SRC(OP0,NIB3); - GET_DST(OP0,NIB2); - PUSHL(cpustate, dst, cpustate->RL(src)); + GET_SRC(OP0,NIB3); + GET_DST(OP0,NIB2); + PUSHL(cpustate, dst, cpustate->RL(src)); } /****************************************** @@ -5122,9 +5122,9 @@ static void Z91_ddN0_ssss(z8000_state *cpustate) ******************************************/ static void Z92_ssss_dddd(z8000_state *cpustate) { - GET_DST(OP0,NIB3); - GET_SRC(OP0,NIB2); - cpustate->RL(dst) = SUBL(cpustate, cpustate->RL(dst), cpustate->RL(src)); + GET_DST(OP0,NIB3); + GET_SRC(OP0,NIB2); + cpustate->RL(dst) = SUBL(cpustate, cpustate->RL(dst), cpustate->RL(src)); } /****************************************** @@ -5155,9 +5155,9 @@ static void Z94_ssss_dddd(z8000_state *cpustate) ******************************************/ static void Z95_ssN0_dddd(z8000_state *cpustate) { - GET_DST(OP0,NIB3); - GET_SRC(OP0,NIB2); - cpustate->RL(dst) = POPL(cpustate, src); + GET_DST(OP0,NIB3); + GET_SRC(OP0,NIB2); + cpustate->RL(dst) = POPL(cpustate, src); } /****************************************** @@ -5177,9 +5177,9 @@ static void Z96_ssss_dddd(z8000_state *cpustate) ******************************************/ static void Z97_ssN0_dddd(z8000_state *cpustate) { - GET_DST(OP0,NIB3); - GET_SRC(OP0,NIB2); - cpustate->RW(dst) = POPW(cpustate, src); + GET_DST(OP0,NIB3); + GET_SRC(OP0,NIB2); + cpustate->RW(dst) = POPW(cpustate, src); } /****************************************** @@ -5188,8 +5188,8 @@ static void Z97_ssN0_dddd(z8000_state *cpustate) ******************************************/ static void Z98_ssss_dddd(z8000_state *cpustate) { - GET_DST(OP0,NIB3); - GET_SRC(OP0,NIB2); + GET_DST(OP0,NIB3); + GET_SRC(OP0,NIB2); cpustate->RQ(dst) = MULTL(cpustate, cpustate->RQ(dst), cpustate->RL(src)); } @@ -5199,8 +5199,8 @@ static void Z98_ssss_dddd(z8000_state *cpustate) ******************************************/ static void Z99_ssss_dddd(z8000_state *cpustate) { - GET_DST(OP0,NIB3); - GET_SRC(OP0,NIB2); + GET_DST(OP0,NIB3); + GET_SRC(OP0,NIB2); cpustate->RL(dst) = MULTW(cpustate, cpustate->RL(dst), cpustate->RW(src)); } @@ -5210,9 +5210,9 @@ static void Z99_ssss_dddd(z8000_state *cpustate) ******************************************/ static void Z9A_ssss_dddd(z8000_state *cpustate) { - GET_DST(OP0,NIB3); - GET_SRC(OP0,NIB2); - cpustate->RQ(dst) = DIVL(cpustate, cpustate->RQ(dst), cpustate->RL(src)); + GET_DST(OP0,NIB3); + GET_SRC(OP0,NIB2); + cpustate->RQ(dst) = DIVL(cpustate, cpustate->RQ(dst), cpustate->RL(src)); } /****************************************** @@ -5221,9 +5221,9 @@ static void Z9A_ssss_dddd(z8000_state *cpustate) ******************************************/ static void Z9B_ssss_dddd(z8000_state *cpustate) { - GET_DST(OP0,NIB3); - GET_SRC(OP0,NIB2); - cpustate->RL(dst) = DIVW(cpustate, cpustate->RL(dst), cpustate->RW(src)); + GET_DST(OP0,NIB3); + GET_SRC(OP0,NIB2); + cpustate->RL(dst) = DIVW(cpustate, cpustate->RL(dst), cpustate->RW(src)); } /****************************************** @@ -5235,7 +5235,7 @@ static void Z9C_dddd_1000(z8000_state *cpustate) GET_DST(OP0,NIB2); CLR_ZS; if (!cpustate->RL(dst)) SET_Z; - else if (cpustate->RL(dst) & S32) SET_S; + else if (cpustate->RL(dst) & S32) SET_S; } /****************************************** @@ -5246,10 +5246,10 @@ static void Z9D_imm8(z8000_state *cpustate) { GET_IMM8(0); LOG(("Z8K '%s' %04x: rsvd9d $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -5259,8 +5259,8 @@ static void Z9D_imm8(z8000_state *cpustate) static void Z9E_0000_cccc(z8000_state *cpustate) { GET_CCC(OP0,NIB3); - if (segmented_mode(cpustate)) - switch (cc) { + if (segmented_mode(cpustate)) + switch (cc) { case 0: if (CC0) set_pc(cpustate, segmented_addr(POPL(cpustate, SP))); break; case 1: if (CC1) set_pc(cpustate, segmented_addr(POPL(cpustate, SP))); break; case 2: if (CC2) set_pc(cpustate, segmented_addr(POPL(cpustate, SP))); break; @@ -5277,9 +5277,9 @@ static void Z9E_0000_cccc(z8000_state *cpustate) case 13: if (CCD) set_pc(cpustate, segmented_addr(POPL(cpustate, SP))); break; case 14: if (CCE) set_pc(cpustate, segmented_addr(POPL(cpustate, SP))); break; case 15: if (CCF) set_pc(cpustate, segmented_addr(POPL(cpustate, SP))); break; - } - else - switch (cc) { + } + else + switch (cc) { case 0: if (CC0) set_pc(cpustate, POPW(cpustate, SP)); break; case 1: if (CC1) set_pc(cpustate, POPW(cpustate, SP)); break; case 2: if (CC2) set_pc(cpustate, POPW(cpustate, SP)); break; @@ -5296,7 +5296,7 @@ static void Z9E_0000_cccc(z8000_state *cpustate) case 13: if (CCD) set_pc(cpustate, POPW(cpustate, SP)); break; case 14: if (CCE) set_pc(cpustate, POPW(cpustate, SP)); break; case 15: if (CCF) set_pc(cpustate, POPW(cpustate, SP)); break; - } + } } /****************************************** @@ -5307,10 +5307,10 @@ static void Z9F_imm8(z8000_state *cpustate) { GET_IMM8(0); LOG(("Z8K '%s' %04x: rsvd9f $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } } /****************************************** @@ -5497,7 +5497,7 @@ static void ZAE_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) tmp |= 1; break; case 14: if (CCE) tmp |= 1; break; case 15: if (CCF) tmp |= 1; break; - } + } cpustate->RB(dst) = tmp; } @@ -5527,7 +5527,7 @@ static void ZAF_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) tmp |= 1; break; case 14: if (CCE) tmp |= 1; break; case 15: if (CCF) tmp |= 1; break; - } + } cpustate->RW(dst) = tmp; } @@ -5540,8 +5540,8 @@ static void ZB0_dddd_0000(z8000_state *cpustate) GET_DST(OP0,NIB2); UINT8 result; UINT16 idx = cpustate->RB(dst); - if (cpustate->fcw & F_C) idx |= 0x100; - if (cpustate->fcw & F_H) idx |= 0x200; + if (cpustate->fcw & F_C) idx |= 0x100; + if (cpustate->fcw & F_H) idx |= 0x200; if (cpustate->fcw & F_DA) idx |= 0x400; result = Z8000_dab[idx]; CLR_CZS; @@ -5557,7 +5557,7 @@ static void ZB0_dddd_0000(z8000_state *cpustate) static void ZB1_dddd_0000(z8000_state *cpustate) { GET_DST(OP0,NIB2); - cpustate->RW(dst) = (cpustate->RW(dst) & 0xff) | ((cpustate->RW(dst) & S08) ? 0xff00 : 0x0000); + cpustate->RW(dst) = (cpustate->RW(dst) & 0xff) | ((cpustate->RW(dst) & S08) ? 0xff00 : 0x0000); } /****************************************** @@ -5578,7 +5578,7 @@ static void ZB1_dddd_0111(z8000_state *cpustate) static void ZB1_dddd_1010(z8000_state *cpustate) { GET_DST(OP0,NIB2); - cpustate->RL(dst) = (cpustate->RL(dst) & 0xffff) | ((cpustate->RL(dst) & S16) ? + cpustate->RL(dst) = (cpustate->RL(dst) & 0xffff) | ((cpustate->RL(dst) & S16) ? 0xffff0000ul : 0x00000000ul); } @@ -5693,7 +5693,7 @@ static void ZB3_dddd_0001_imm8(z8000_state *cpustate) if (imm16 & S16) cpustate->RW(dst) = SRLW(cpustate, cpustate->RW(dst), -(INT16)imm16); else - cpustate->RW(dst) = SLLW(cpustate, cpustate->RW(dst), imm16); + cpustate->RW(dst) = SLLW(cpustate, cpustate->RW(dst), imm16); } /****************************************** @@ -5769,7 +5769,7 @@ static void ZB3_dddd_1001_imm8(z8000_state *cpustate) if (imm16 & S16) cpustate->RW(dst) = SRAW(cpustate, cpustate->RW(dst), -(INT16)imm16); else - cpustate->RW(dst) = SLAW(cpustate, cpustate->RW(dst), imm16); + cpustate->RW(dst) = SLAW(cpustate, cpustate->RW(dst), imm16); } /****************************************** @@ -5886,7 +5886,7 @@ static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate) GET_SRC(OP1,NIB2); GET_CNT(OP1,NIB1); UINT8 xlt = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst))); - cpustate->RB(1) = xlt; /* load RH1 */ + cpustate->RB(1) = xlt; /* load RH1 */ if (xlt) CLR_Z; else SET_Z; add_to_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) CLR_V; else SET_V; @@ -5902,13 +5902,13 @@ static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate) GET_SRC(OP1,NIB2); GET_CNT(OP1,NIB1); UINT8 xlt = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst))); - cpustate->RB(1) = xlt; /* load RH1 */ + cpustate->RB(1) = xlt; /* load RH1 */ if (xlt) CLR_Z; else SET_Z; add_to_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) { - CLR_V; - if (!xlt) - cpustate->pc -= 4; + CLR_V; + if (!xlt) + cpustate->pc -= 4; } else SET_V; } @@ -5923,7 +5923,7 @@ static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate) GET_SRC(OP1,NIB2); GET_CNT(OP1,NIB1); UINT8 xlt = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst))); - cpustate->RB(1) = xlt; /* load RH1 */ + cpustate->RB(1) = xlt; /* load RH1 */ if (xlt) CLR_Z; else SET_Z; sub_from_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) CLR_V; else SET_V; @@ -5939,13 +5939,13 @@ static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate) GET_SRC(OP1,NIB2); GET_CNT(OP1,NIB1); UINT8 xlt = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst))); - cpustate->RB(1) = xlt; /* load RH1 */ + cpustate->RB(1) = xlt; /* load RH1 */ if (xlt) CLR_Z; else SET_Z; sub_from_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) { - CLR_V; - if (!xlt) - cpustate->pc -= 4; + CLR_V; + if (!xlt) + cpustate->pc -= 4; } else SET_V; } @@ -5961,7 +5961,7 @@ static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate) GET_CNT(OP1,NIB1); UINT8 xlt = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst))); WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), xlt); - cpustate->RB(1) = xlt; /* destroy RH1 */ + cpustate->RB(1) = xlt; /* destroy RH1 */ add_to_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) CLR_V; else SET_V; } @@ -5977,7 +5977,7 @@ static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate) GET_CNT(OP1,NIB1); UINT8 xlt = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst))); WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), xlt); - cpustate->RB(1) = xlt; /* destroy RH1 */ + cpustate->RB(1) = xlt; /* destroy RH1 */ add_to_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) { CLR_V; cpustate->pc -= 4; } else SET_V; } @@ -5993,7 +5993,7 @@ static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate) GET_CNT(OP1,NIB1); UINT8 xlt = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst))); WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), xlt); - cpustate->RB(1) = xlt; /* destroy RH1 */ + cpustate->RB(1) = xlt; /* destroy RH1 */ sub_from_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) CLR_V; else SET_V; } @@ -6009,7 +6009,7 @@ static void ZB8_ddN0_1100_0000_rrrr_ssN0_0000(z8000_state *cpustate) GET_CNT(OP1,NIB1); UINT8 xlt = RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src) + RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst))); WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), xlt); - cpustate->RB(1) = xlt; /* destroy RH1 */ + cpustate->RB(1) = xlt; /* destroy RH1 */ sub_from_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) { CLR_V; cpustate->pc -= 4; } else SET_V; } @@ -6022,10 +6022,10 @@ static void ZB9_imm8(z8000_state *cpustate) { GET_IMM8(0); LOG(("Z8K '%s' %04x: rsvdb9 $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } (void)imm8; } @@ -6057,7 +6057,7 @@ static void ZBA_ssN0_0000_0000_rrrr_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } add_to_addr_reg(cpustate, src, 1); if (--cpustate->RW(cnt)) CLR_V; else SET_V; } @@ -6070,10 +6070,10 @@ static void ZBA_ssN0_0000_0000_rrrr_dddd_cccc(z8000_state *cpustate) static void ZBA_ssN0_0001_0000_rrrr_ddN0_x000(z8000_state *cpustate) { GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); - GET_CCC(OP1,NIB3); /* repeat? */ - WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); + GET_CCC(OP1,NIB3); /* repeat? */ + WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); add_to_addr_reg(cpustate, src, 1); add_to_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; @@ -6107,7 +6107,7 @@ static void ZBA_ssN0_0010_0000_rrrr_ddN0_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } add_to_addr_reg(cpustate, src, 1); add_to_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; @@ -6141,7 +6141,7 @@ static void ZBA_ssN0_0100_0000_rrrr_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } add_to_addr_reg(cpustate, src, 1); if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; } @@ -6174,7 +6174,7 @@ static void ZBA_ssN0_0110_0000_rrrr_ddN0_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } add_to_addr_reg(cpustate, src, 1); add_to_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; @@ -6190,8 +6190,8 @@ static void ZBA_ssN0_1000_0000_rrrr_dddd_cccc(z8000_state *cpustate) GET_CCC(OP1,NIB3); GET_DST(OP1,NIB2); GET_CNT(OP1,NIB1); - CPB(cpustate, cpustate->RB(dst), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); - switch (cc) { + CPB(cpustate, cpustate->RB(dst), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); + switch (cc) { case 0: if (CC0) SET_Z; else CLR_Z; break; case 1: if (CC1) SET_Z; else CLR_Z; break; case 2: if (CC2) SET_Z; else CLR_Z; break; @@ -6208,7 +6208,7 @@ static void ZBA_ssN0_1000_0000_rrrr_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } sub_from_addr_reg(cpustate, src, 1); if (--cpustate->RW(cnt)) CLR_V; else SET_V; } @@ -6221,7 +6221,7 @@ static void ZBA_ssN0_1000_0000_rrrr_dddd_cccc(z8000_state *cpustate) static void ZBA_ssN0_1001_0000_rrrr_ddN0_x000(z8000_state *cpustate) { GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); @@ -6240,7 +6240,7 @@ static void ZBA_ssN0_1010_0000_rrrr_ddN0_cccc(z8000_state *cpustate) GET_CCC(OP1,NIB3); GET_DST(OP1,NIB2); GET_CNT(OP1,NIB1); - CPB(cpustate, RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst)), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); + CPB(cpustate, RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst)), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); switch (cc) { case 0: if (CC0) SET_Z; else CLR_Z; break; case 1: if (CC1) SET_Z; else CLR_Z; break; @@ -6258,7 +6258,7 @@ static void ZBA_ssN0_1010_0000_rrrr_ddN0_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } sub_from_addr_reg(cpustate, src, 1); sub_from_addr_reg(cpustate, dst, 1); if (--cpustate->RW(cnt)) CLR_V; else SET_V; @@ -6292,7 +6292,7 @@ static void ZBA_ssN0_1100_0000_rrrr_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } sub_from_addr_reg(cpustate, src, 1); if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; } @@ -6307,7 +6307,7 @@ static void ZBA_ssN0_1110_0000_rrrr_ddN0_cccc(z8000_state *cpustate) GET_CCC(OP1,NIB3); GET_DST(OP1,NIB2); GET_CNT(OP1,NIB1); - CPB(cpustate, RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst)), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); + CPB(cpustate, RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, dst)), RDMEM_B(cpustate, AS_DATA, addr_from_reg(cpustate, src))); switch (cc) { case 0: if (CC0) SET_Z; else CLR_Z; break; case 1: if (CC1) SET_Z; else CLR_Z; break; @@ -6342,7 +6342,7 @@ static void ZBB_ssN0_0000_0000_rrrr_dddd_cccc(z8000_state *cpustate) GET_DST(OP1,NIB2); GET_CNT(OP1,NIB1); CPW(cpustate, cpustate->RW(dst), RDMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, src))); - switch (cc) { + switch (cc) { case 0: if (CC0) SET_Z; else CLR_Z; break; case 1: if (CC1) SET_Z; else CLR_Z; break; case 2: if (CC2) SET_Z; else CLR_Z; break; @@ -6359,7 +6359,7 @@ static void ZBB_ssN0_0000_0000_rrrr_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } add_to_addr_reg(cpustate, src, 2); if (--cpustate->RW(cnt)) CLR_V; else SET_V; } @@ -6372,7 +6372,7 @@ static void ZBB_ssN0_0000_0000_rrrr_dddd_cccc(z8000_state *cpustate) static void ZBB_ssN0_0001_0000_rrrr_ddN0_x000(z8000_state *cpustate) { GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); + GET_CNT(OP1,NIB1); GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); WRMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, dst), RDMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, src))); @@ -6409,7 +6409,7 @@ static void ZBB_ssN0_0010_0000_rrrr_ddN0_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } add_to_addr_reg(cpustate, src, 2); add_to_addr_reg(cpustate, dst, 2); if (--cpustate->RW(cnt)) CLR_V; else SET_V; @@ -6443,7 +6443,7 @@ static void ZBB_ssN0_0100_0000_rrrr_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } add_to_addr_reg(cpustate, src, 2); if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; } @@ -6476,7 +6476,7 @@ static void ZBB_ssN0_0110_0000_rrrr_ddN0_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } add_to_addr_reg(cpustate, src, 2); add_to_addr_reg(cpustate, dst, 2); if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; @@ -6493,7 +6493,7 @@ static void ZBB_ssN0_1000_0000_rrrr_dddd_cccc(z8000_state *cpustate) GET_DST(OP1,NIB2); GET_CNT(OP1,NIB1); CPW(cpustate, cpustate->RW(dst), RDMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, src))); - switch (cc) { + switch (cc) { case 0: if (CC0) SET_Z; else CLR_Z; break; case 1: if (CC1) SET_Z; else CLR_Z; break; case 2: if (CC2) SET_Z; else CLR_Z; break; @@ -6510,7 +6510,7 @@ static void ZBB_ssN0_1000_0000_rrrr_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } sub_from_addr_reg(cpustate, src, 2); if (--cpustate->RW(cnt)) CLR_V; else SET_V; } @@ -6522,11 +6522,11 @@ static void ZBB_ssN0_1000_0000_rrrr_dddd_cccc(z8000_state *cpustate) ******************************************/ static void ZBB_ssN0_1001_0000_rrrr_ddN0_x000(z8000_state *cpustate) { - GET_SRC(OP0,NIB2); - GET_CNT(OP1,NIB1); - GET_DST(OP1,NIB2); + GET_SRC(OP0,NIB2); + GET_CNT(OP1,NIB1); + GET_DST(OP1,NIB2); GET_CCC(OP1,NIB3); - WRMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, dst), RDMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, src))); + WRMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, dst), RDMEM_W(cpustate, AS_DATA, addr_from_reg(cpustate, src))); sub_from_addr_reg(cpustate, src, 2); sub_from_addr_reg(cpustate, dst, 2); if (--cpustate->RW(cnt)) { CLR_V; if (cc == 0) cpustate->pc -= 4; } else SET_V; @@ -6560,7 +6560,7 @@ static void ZBB_ssN0_1010_0000_rrrr_ddN0_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } sub_from_addr_reg(cpustate, src, 2); sub_from_addr_reg(cpustate, dst, 2); if (--cpustate->RW(cnt)) CLR_V; else SET_V; @@ -6594,7 +6594,7 @@ static void ZBB_ssN0_1100_0000_rrrr_dddd_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } sub_from_addr_reg(cpustate, src, 2); if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; } @@ -6627,7 +6627,7 @@ static void ZBB_ssN0_1110_0000_rrrr_ddN0_cccc(z8000_state *cpustate) case 13: if (CCD) SET_Z; else CLR_Z; break; case 14: if (CCE) SET_Z; else CLR_Z; break; case 15: if (CCF) SET_Z; else CLR_Z; break; - } + } sub_from_addr_reg(cpustate, src, 2); sub_from_addr_reg(cpustate, dst, 2); if (--cpustate->RW(cnt)) { CLR_V; if (!(cpustate->fcw & F_Z)) cpustate->pc -= 4; } else SET_V; @@ -6644,7 +6644,7 @@ static void ZBC_aaaa_bbbb(z8000_state *cpustate) UINT8 tmp = cpustate->RB(b); cpustate->RB(a) = (cpustate->RB(a) >> 4) | (cpustate->RB(b) << 4); cpustate->RB(b) = (cpustate->RB(b) & 0xf0) | (tmp & 0x0f); - if (cpustate->RB(b)) CLR_Z; else SET_Z; + if (cpustate->RB(b)) CLR_Z; else SET_Z; } /****************************************** @@ -6680,10 +6680,10 @@ static void ZBF_imm8(z8000_state *cpustate) { GET_IMM8(0); LOG(("Z8K '%s' %04x: rsvdbf $%02x\n", cpustate->device->tag(), cpustate->pc, imm8)); - if (cpustate->fcw & F_EPU) { + if (cpustate->fcw & F_EPU) { /* Z8001 EPU code goes here */ (void)imm8; - } + } (void)imm8; } @@ -6705,10 +6705,10 @@ static void ZC_dddd_imm8(z8000_state *cpustate) static void ZD_dsp12(z8000_state *cpustate) { INT16 dsp12 = cpustate->op[0] & 0xfff; - if (segmented_mode(cpustate)) - PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); - else - PUSHW(cpustate, SP, cpustate->pc); + if (segmented_mode(cpustate)) + PUSHL(cpustate, SP, make_segmented_addr(cpustate->pc)); + else + PUSHW(cpustate, SP, cpustate->pc); dsp12 = (dsp12 & 2048) ? 4096 - 2 * (dsp12 & 2047) : -2 * (dsp12 & 2047); set_pc(cpustate, addr_add(cpustate, cpustate->pc, dsp12)); } @@ -6748,11 +6748,11 @@ static void ZE_cccc_dsp8(z8000_state *cpustate) static void ZF_dddd_0dsp7(z8000_state *cpustate) { GET_DST(OP0,NIB1); - GET_DSP7; - cpustate->RB(dst) -= 1; - if (cpustate->RB(dst)) { - set_pc(cpustate, addr_sub(cpustate, cpustate->pc, 2 * dsp7)); - } + GET_DSP7; + cpustate->RB(dst) -= 1; + if (cpustate->RB(dst)) { + set_pc(cpustate, addr_sub(cpustate, cpustate->pc, 2 * dsp7)); + } } /****************************************** @@ -6765,6 +6765,6 @@ static void ZF_dddd_1dsp7(z8000_state *cpustate) GET_DSP7; cpustate->RW(dst) -= 1; if (cpustate->RW(dst)) { - set_pc(cpustate, addr_sub(cpustate, cpustate->pc, 2 * dsp7)); + set_pc(cpustate, addr_sub(cpustate, cpustate->pc, 2 * dsp7)); } } diff --git a/src/emu/cpu/z8000/z8000tbl.c b/src/emu/cpu/z8000/z8000tbl.c index 03ada404ff7..4cd5adf1242 100644 --- a/src/emu/cpu/z8000/z8000tbl.c +++ b/src/emu/cpu/z8000/z8000tbl.c @@ -22,524 +22,524 @@ *****************************************************************************/ static const Z8000_init table[] = { -{0x0000,0x000f, 1,2, 7,Z00_0000_dddd_imm8, "addb %rb3,%#b3", 0}, -{0x0010,0x00ff, 1,1, 7,Z00_ssN0_dddd, "addb %rb3,@%rw2", 0}, -{0x0100,0x010f, 1,2, 7,Z01_0000_dddd_imm16, "add %rw3,%#w1", 0}, -{0x0110,0x01ff, 1,1, 7,Z01_ssN0_dddd, "add %rw3,@%rw2", 0}, -{0x0200,0x020f, 1,2, 7,Z02_0000_dddd_imm8, "subb %rb3,%#b3", 0}, -{0x0210,0x02ff, 1,1, 7,Z02_ssN0_dddd, "subb %rb3,@%rw2", 0}, -{0x0300,0x030f, 1,2, 7,Z03_0000_dddd_imm16, "sub %rw3,%#w1", 0}, -{0x0310,0x03ff, 1,1, 7,Z03_ssN0_dddd, "sub %rw3,@%rw2", 0}, -{0x0400,0x040f, 1,2, 7,Z04_0000_dddd_imm8, "orb %rb3,%#b3", 0}, -{0x0410,0x04ff, 1,1, 7,Z04_ssN0_dddd, "orb %rb3,@%rw2", 0}, -{0x0500,0x050f, 1,2, 7,Z05_0000_dddd_imm16, "or %rw3,%#w1", 0}, -{0x0510,0x05ff, 1,1, 7,Z05_ssN0_dddd, "or %rw3,@%rw2", 0}, -{0x0600,0x060f, 1,2, 7,Z06_0000_dddd_imm8, "andb %rb3,%#b3", 0}, -{0x0610,0x06ff, 1,1, 7,Z06_ssN0_dddd, "andb %rb3,@%rw2", 0}, -{0x0700,0x070f, 1,2, 7,Z07_0000_dddd_imm16, "and %rw3,%#w1", 0}, -{0x0710,0x07ff, 1,1, 7,Z07_ssN0_dddd, "and %rw3,@%rw2", 0}, -{0x0800,0x080f, 1,2, 7,Z08_0000_dddd_imm8, "xorb %rb3,%#b3", 0}, -{0x0810,0x08ff, 1,1, 7,Z08_ssN0_dddd, "xorb %rb3,@%rw2", 0}, -{0x0900,0x090f, 1,2, 7,Z09_0000_dddd_imm16, "xor %rw3,%#w1", 0}, -{0x0910,0x09ff, 1,1, 7,Z09_ssN0_dddd, "xor %rw3,@%rw2", 0}, -{0x0a00,0x0a0f, 1,2, 7,Z0A_0000_dddd_imm8, "cpb %rb3,%#b3", 0}, -{0x0a10,0x0aff, 1,1, 7,Z0A_ssN0_dddd, "cpb %rb3,@%rw2", 0}, -{0x0b00,0x0b0f, 1,2, 7,Z0B_0000_dddd_imm16, "cp %rw3,%#w1", 0}, -{0x0b10,0x0bff, 1,1, 7,Z0B_ssN0_dddd, "cp %rw3,@%rw2", 0}, -{0x0c10,0x0cf0,16,1, 12,Z0C_ddN0_0000, "comb @%rw2", 0}, -{0x0c11,0x0cf1,16,2, 11,Z0C_ddN0_0001_imm8, "cpb @%rw2,%#b3", 0}, -{0x0c12,0x0cf2,16,1, 12,Z0C_ddN0_0010, "negb @%rw2", 0}, -{0x0c14,0x0cf4,16,1, 8,Z0C_ddN0_0100, "testb @%rw2", 0}, -{0x0c15,0x0cf5,16,2, 7,Z0C_ddN0_0101_imm8, "ldb @%rw2,%#b3", 0}, -{0x0c16,0x0cf6,16,1, 11,Z0C_ddN0_0110, "tsetb @%rw2", 0}, -{0x0c18,0x0cf8,16,1, 8,Z0C_ddN0_1000, "clrb @%rw2", 0}, -{0x0d10,0x0df0,16,1, 12,Z0D_ddN0_0000, "com @%rw2", 0}, -{0x0d11,0x0df1,16,2, 11,Z0D_ddN0_0001_imm16, "cp @%rw2,%#w1", 0}, -{0x0d12,0x0df2,16,1, 12,Z0D_ddN0_0010, "neg @%rw2", 0}, -{0x0d14,0x0df4,16,1, 8,Z0D_ddN0_0100, "test @%rw2", 0}, -{0x0d15,0x0df5,16,2, 11,Z0D_ddN0_0101_imm16, "ld @%rw2,%#w1", 0}, /* fix cycles ld IR,IM */ -{0x0d16,0x0df6,16,1, 11,Z0D_ddN0_0110, "tset @%rw2", 0}, -{0x0d18,0x0df8,16,1, 8,Z0D_ddN0_1000, "clr @%rw2", 0}, -{0x0d19,0x0df9,16,2, 12,Z0D_ddN0_1001_imm16, "push @%rw2,%#w1", 0}, -{0x0e00,0x0eff, 1,1, 10,Z0E_imm8, "ext0e %#b1", 0}, -{0x0f00,0x0fff, 1,1, 10,Z0F_imm8, "ext0f %#b1", 0}, -{0x1000,0x100f, 1,3, 14,Z10_0000_dddd_imm32, "cpl %rl3,%#l1", 0}, -{0x1010,0x10ff, 1,1, 14,Z10_ssN0_dddd, "cpl %rl3,@%rw2", 0}, -{0x1111,0x11ff, 1,1, 20,Z11_ddN0_ssN0, "pushl @%rw2,@%rw3", 0}, -{0x1200,0x120f, 1,3, 14,Z12_0000_dddd_imm32, "subl %rl3,%#l1", 0}, -{0x1210,0x12ff, 1,1, 14,Z12_ssN0_dddd, "subl %rl3,@%rw2", 0}, -{0x1311,0x13ff, 1,1, 13,Z13_ddN0_ssN0, "push @%rw2,@%rw3", 0}, -{0x1400,0x140f, 1,3, 11,Z14_0000_dddd_imm32, "ldl %rl3,%#l1", 0}, -{0x1410,0x14ff, 1,1, 11,Z14_ssN0_dddd, "ldl %rl3,@%rw2", 0}, -{0x1511,0x15ff, 1,1, 19,Z15_ssN0_ddN0, "popl @%rw3,@%rw2", 0}, -{0x1600,0x160f, 1,3, 14,Z16_0000_dddd_imm32, "addl %rl3,%#l1", 0}, -{0x1610,0x16ff, 1,1, 14,Z16_ssN0_dddd, "addl %rl3,@%rw2", 0}, -{0x1711,0x17ff, 1,1, 12,Z17_ssN0_ddN0, "pop @%rw3,@%rw2", 0}, -{0x1800,0x180f, 1,1,282,Z18_00N0_dddd_imm32, "multl %rq3,@%l#1", 0}, -{0x1810,0x18ff, 1,1,282,Z18_ssN0_dddd, "multl %rq3,@%rw2", 0}, -{0x1900,0x190f, 1,2, 70,Z19_0000_dddd_imm16, "mult %rl3,%#w1", 0}, -{0x1910,0x19ff, 1,1, 70,Z19_ssN0_dddd, "mult %rl3,@%rw2", 0}, -{0x1a00,0x1a0f, 1,3,744,Z1A_0000_dddd_imm32, "divl %rq3,%#l1", 0}, -{0x1a10,0x1aff, 1,1,744,Z1A_ssN0_dddd, "divl %rq3,@%rw2", 0}, -{0x1b00,0x1b0f, 1,2,107,Z1B_0000_dddd_imm16, "div %rl3,%#w1", 0}, -{0x1b10,0x1bff, 1,1,107,Z1B_ssN0_dddd, "div %rl3,@%rw2", 0}, -{0x1c11,0x1cf1,16,2, 11,Z1C_ssN0_0001_0000_dddd_0000_nmin1, "ldm %rw5,@%rw2,#%n", 0}, -{0x1c18,0x1cf8,16,1, 13,Z1C_ddN0_1000, "testl @%rw2", 0}, -{0x1c19,0x1cf9,16,2, 11,Z1C_ddN0_1001_0000_ssss_0000_nmin1, "ldm @%rw2,%rw5,#%n", 0}, -{0x1d10,0x1dff, 1,1, 11,Z1D_ddN0_ssss, "ldl @%rw2,%rl3", 0}, -{0x1e10,0x1eff, 1,1, 10,Z1E_ddN0_cccc, "jp %c3,@%rl2", 0}, -{0x1f10,0x1ff0,16,1, 10,Z1F_ddN0_0000, "call %rw2", DASMFLAG_STEP_OVER}, -{0x2010,0x20ff, 1,1, 7,Z20_ssN0_dddd, "ldb %rb3,@%rw2", 0}, -{0x2100,0x210f, 1,2, 7,Z21_0000_dddd_imm16, "ld %rw3,%#w1", 0}, -{0x2110,0x21ff, 1,1, 7,Z21_ssN0_dddd, "ld %rw3,@%rw2", 0}, -{0x2200,0x220f, 1,2, 10,Z22_0000_ssss_0000_dddd_0000_0000, "resb %rb5,%rw3", 0}, -{0x2210,0x22ff, 1,1, 11,Z22_ddN0_imm4, "resb @%rw3,%3", 0}, -{0x2300,0x230f, 1,2, 10,Z23_0000_ssss_0000_dddd_0000_0000, "res %rw5,%rw3", 0}, -{0x2310,0x23ff, 1,1, 11,Z23_ddN0_imm4, "res @%rw3,%3", 0}, -{0x2400,0x240f, 1,2, 10,Z24_0000_ssss_0000_dddd_0000_0000, "setb %rb5,%rw3", 0}, -{0x2410,0x24ff, 1,1, 11,Z24_ddN0_imm4, "setb @%rw3,%3", 0}, -{0x2500,0x250f, 1,2, 10,Z25_0000_ssss_0000_dddd_0000_0000, "set %rw5,%rw3", 0}, -{0x2510,0x25ff, 1,1, 11,Z25_ddN0_imm4, "set @%rw3,%3", 0}, -{0x2600,0x260f, 1,2, 10,Z26_0000_ssss_0000_dddd_0000_0000, "bitb %rb5,%rw3", 0}, -{0x2610,0x26ff, 1,1, 8,Z26_ddN0_imm4, "bitb @%rw3,%3", 0}, -{0x2700,0x270f, 1,2, 10,Z27_0000_ssss_0000_dddd_0000_0000, "bit %rw5,%rw3", 0}, -{0x2710,0x27ff, 1,1, 8,Z27_ddN0_imm4, "bit @%rw2,%3", 0}, -{0x2810,0x28ff, 1,1, 11,Z28_ddN0_imm4m1, "incb @%rw2,%+3", 0}, -{0x2910,0x29ff, 1,1, 11,Z29_ddN0_imm4m1, "inc @%rw2,%+3", 0}, -{0x2a10,0x2aff, 1,1, 11,Z2A_ddN0_imm4m1, "decb @%rw2,%+3", 0}, -{0x2b10,0x2bff, 1,1, 11,Z2B_ddN0_imm4m1, "dec @%rw2,%+3", 0}, -{0x2c10,0x2cff, 1,1, 12,Z2C_ssN0_dddd, "exb %rb3,@%rw2", 0}, -{0x2d10,0x2dff, 1,1, 12,Z2D_ssN0_dddd, "ex %rw3,@%rw2", 0}, -{0x2e10,0x2eff, 1,1, 8,Z2E_ddN0_ssss, "ldb @%rw2,%rb3", 0}, -{0x2f10,0x2fff, 1,1, 8,Z2F_ddN0_ssss, "ld @%rw2,%rw3", 0}, -{0x3000,0x300f, 1,2, 14,Z30_0000_dddd_dsp16, "ldrb %rb3,%p1", 0}, -{0x3010,0x30ff, 1,2, 14,Z30_ssN0_dddd_imm16, "ldb %rb3,%rw2(%#w1)", 0}, -{0x3100,0x310f, 1,2, 14,Z31_0000_dddd_dsp16, "ldr %rw3,%p1", 0}, -{0x3110,0x31ff, 1,2, 14,Z31_ssN0_dddd_imm16, "ld %rw3,%rw2(%#w1)", 0}, -{0x3200,0x320f, 1,2, 14,Z32_0000_ssss_dsp16, "ldrb %p1,%rb3", 0}, -{0x3210,0x32ff, 1,2, 14,Z32_ddN0_ssss_imm16, "ldb %rw2(%#w1),%rb3", 0}, -{0x3300,0x330f, 1,2, 14,Z33_0000_ssss_dsp16, "ldr %p1,%rw3", 0}, -{0x3310,0x33ff, 1,2, 14,Z33_ddN0_ssss_imm16, "ld %rw2(%#w1),%rw3", 0}, -{0x3400,0x340f, 1,2, 15,Z34_0000_dddd_dsp16, "ldar p%rw3,%p1", 0}, -{0x3410,0x34ff, 1,2, 15,Z34_ssN0_dddd_imm16, "lda p%rw3,%rw2(%#w1)", 0}, -{0x3500,0x350f, 1,2, 17,Z35_0000_dddd_dsp16, "ldrl %rl3,%p1", 0}, -{0x3510,0x35ff, 1,2, 17,Z35_ssN0_dddd_imm16, "ldl %rl3,%rw2(%#w1)", 0}, -{0x3600,0x3600, 1,1, 2,Z36_0000_0000, "bpt", 0}, -{0x3601,0x36ff, 1,1, 10,Z36_imm8, "rsvd36", 0}, -{0x3700,0x370f, 1,2, 17,Z37_0000_ssss_dsp16, "ldrl %p1,%rl3", 0}, -{0x3710,0x37ff, 1,2, 17,Z37_ddN0_ssss_imm16, "ldl %rw2(%#w1),%rl3", 0}, -{0x3800,0x38ff, 1,1, 10,Z38_imm8, "rsvd38", 0}, -{0x3910,0x39f0,16,1, 12,Z39_ssN0_0000, "ldps @%rw2", 0}, -{0x3a00,0x3af0,16,2, 21,Z3A_ssss_0000_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3a01,0x3af1,16,2, 21,Z3A_ssss_0001_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3a02,0x3af2,16,2, 21,Z3A_ssss_0010_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3a03,0x3af3,16,2, 21,Z3A_ssss_0011_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3a04,0x3af4,16,2, 10,Z3A_dddd_0100_imm16, "%R %rb2,%#w1", 0}, -{0x3a05,0x3af5,16,2, 10,Z3A_dddd_0101_imm16, "%R %rb2,%#w1", 0}, -{0x3a06,0x3af6,16,2, 12,Z3A_ssss_0110_imm16, "%R %#w1,%rb2", 0}, -{0x3a07,0x3af7,16,2, 12,Z3A_ssss_0111_imm16, "%R %#w1,%rb2", 0}, -{0x3a08,0x3af8,16,2, 21,Z3A_ssss_1000_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3a09,0x3af9,16,2, 21,Z3A_ssss_1001_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3a0a,0x3afa,16,2, 21,Z3A_ssss_1010_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3a0b,0x3afb,16,2, 21,Z3A_ssss_1011_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3b00,0x3bf0,16,2, 21,Z3B_ssss_0000_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3b01,0x3bf1,16,2, 21,Z3B_ssss_0001_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3b02,0x3bf2,16,2, 21,Z3B_ssss_0010_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3b03,0x3bf3,16,2, 21,Z3B_ssss_0011_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3b04,0x3bf4,16,2, 12,Z3B_dddd_0100_imm16, "%R %rw2,%#w1", 0}, -{0x3b05,0x3bf5,16,2, 12,Z3B_dddd_0101_imm16, "%R %rw2,%#w1", 0}, -{0x3b06,0x3bf6,16,2, 12,Z3B_ssss_0110_imm16, "%R %#w1,%rw2", 0}, -{0x3b07,0x3bf7,16,2, 12,Z3B_ssss_0111_imm16, "%R %#w1,%rw2", 0}, -{0x3b08,0x3bf8,16,2, 21,Z3B_ssss_1000_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3b09,0x3bf9,16,2, 21,Z3B_ssss_1001_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, -{0x3b0a,0x3bfa,16,2, 21,Z3B_ssss_1010_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rb5", 0}, -{0x3b0b,0x3bfb,16,2, 21,Z3B_ssss_1011_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rb5", 0}, -{0x3c00,0x3cff, 1,1, 10,Z3C_ssss_dddd, "inb %rb3,@%rw2", 0}, -{0x3d00,0x3dff, 1,1, 10,Z3D_ssss_dddd, "in %rw3,@%rw2", 0}, -{0x3e00,0x3eff, 1,1, 12,Z3E_dddd_ssss, "outb @%rw2,%rb3", 0}, -{0x3f00,0x3fff, 1,1, 12,Z3F_dddd_ssss, "out @%rw2,%rw3", 0}, -{0x4000,0x400f, 1,2, 9,Z40_0000_dddd_addr, "addb %rb3,%a1", 0}, -{0x4010,0x40ff, 1,2, 10,Z40_ssN0_dddd_addr, "addb %rb3,%a1(%rw2)", 0}, -{0x4100,0x410f, 1,2, 9,Z41_0000_dddd_addr, "add %rw3,%a1", 0}, -{0x4110,0x41ff, 1,2, 10,Z41_ssN0_dddd_addr, "add %rw3,%a1(%rw2)", 0}, -{0x4200,0x420f, 1,2, 9,Z42_0000_dddd_addr, "subb %rb3,%a1", 0}, -{0x4210,0x42ff, 1,2, 10,Z42_ssN0_dddd_addr, "subb %rb3,%a1(%rw2)", 0}, -{0x4300,0x430f, 1,2, 9,Z43_0000_dddd_addr, "sub %rw3,%a1", 0}, -{0x4310,0x43ff, 1,2, 10,Z43_ssN0_dddd_addr, "sub %rw3,%a1(%rw2)", 0}, -{0x4400,0x440f, 1,2, 9,Z44_0000_dddd_addr, "orb %rb3,%a1", 0}, -{0x4410,0x44ff, 1,2, 10,Z44_ssN0_dddd_addr, "orb %rb3,%a1(%rw2)", 0}, -{0x4500,0x450f, 1,2, 9,Z45_0000_dddd_addr, "or %rw3,%a1", 0}, -{0x4510,0x45ff, 1,2, 10,Z45_ssN0_dddd_addr, "or %rw3,%a1(%rw2)", 0}, -{0x4600,0x460f, 1,2, 9,Z46_0000_dddd_addr, "andb %rb3,%a1", 0}, -{0x4610,0x46ff, 1,2, 10,Z46_ssN0_dddd_addr, "andb %rb3,%a1(%rw2)", 0}, -{0x4700,0x470f, 1,2, 9,Z47_0000_dddd_addr, "and %rw3,%a1", 0}, -{0x4710,0x47ff, 1,2, 10,Z47_ssN0_dddd_addr, "and %rw3,%a1(%rw2)", 0}, -{0x4800,0x480f, 1,2, 9,Z48_0000_dddd_addr, "xorb %rb3,%a1", 0}, -{0x4810,0x48ff, 1,2, 10,Z48_ssN0_dddd_addr, "xorb %rb3,%a1(%rw2)", 0}, -{0x4900,0x490f, 1,2, 9,Z49_0000_dddd_addr, "xor %rw3,%a1", 0}, -{0x4910,0x49ff, 1,2, 10,Z49_ssN0_dddd_addr, "xor %rw3,%a1(%rw2)", 0}, -{0x4a00,0x4a0f, 1,2, 9,Z4A_0000_dddd_addr, "cpb %rb3,%a1", 0}, -{0x4a10,0x4aff, 1,2, 10,Z4A_ssN0_dddd_addr, "cpb %rb3,%a1(%rw2)", 0}, -{0x4b00,0x4b0f, 1,2, 9,Z4B_0000_dddd_addr, "cp %rw3,%a1", 0}, -{0x4b10,0x4bff, 1,2, 10,Z4B_ssN0_dddd_addr, "cp %rw3,%a1(%rw2)", 0}, -{0x4c00,0x4c00, 1,2, 15,Z4C_0000_0000_addr, "comb %a1", 0}, -{0x4c01,0x4c01, 1,3, 14,Z4C_0000_0001_addr_imm8, "cpb %a1,%#b3", 0}, -{0x4c02,0x4c02, 1,2, 15,Z4C_0000_0010_addr, "negb %a1", 0}, -{0x4c04,0x4c04, 1,2, 11,Z4C_0000_0100_addr, "testb %a1", 0}, -{0x4c05,0x4c05, 1,3, 14,Z4C_0000_0101_addr_imm8, "ldb %a1,%#b3", 0}, -{0x4c06,0x4c06, 1,2, 14,Z4C_0000_0110_addr, "tsetb %a1", 0}, -{0x4c08,0x4c08, 1,2, 11,Z4C_0000_1000_addr, "clrb %a1", 0}, -{0x4c10,0x4cf0,16,2, 16,Z4C_ddN0_0000_addr, "comb %a1(%rw2)", 0}, -{0x4c11,0x4cf1,16,3, 15,Z4C_ddN0_0001_addr_imm8, "cpb %a1(%rw2),%#b3", 0}, -{0x4c12,0x4cf2,16,2, 16,Z4C_ddN0_0010_addr, "negb %a1(%rw2)", 0}, -{0x4c14,0x4cf4,16,2, 12,Z4C_ddN0_0100_addr, "testb %a1(%rw2)", 0}, -{0x4c15,0x4cf5,16,3, 15,Z4C_ddN0_0101_addr_imm8, "ldb %a1(%rw2),%#b3", 0}, -{0x4c16,0x4cf6,16,2, 15,Z4C_ddN0_0110_addr, "tsetb %a1(%rw2)", 0}, -{0x4c18,0x4cf8,16,2, 12,Z4C_ddN0_1000_addr, "clrb %a1(%rw2)", 0}, -{0x4d00,0x4d00, 1,2, 15,Z4D_0000_0000_addr, "com %a1", 0}, -{0x4d01,0x4d01, 1,3, 14,Z4D_0000_0001_addr_imm16, "cp %a1,%#w2", 0}, -{0x4d02,0x4d02, 1,2, 15,Z4D_0000_0010_addr, "neg %a1", 0}, -{0x4d04,0x4d04, 1,2, 11,Z4D_0000_0100_addr, "test %a1", 0}, -{0x4d05,0x4d05, 1,3, 14,Z4D_0000_0101_addr_imm16, "ld %a1,%#w2", 0}, -{0x4d06,0x4d06, 1,2, 14,Z4D_0000_0110_addr, "tset %a1", 0}, -{0x4d08,0x4d08, 1,2, 11,Z4D_0000_1000_addr, "clr %a1", 0}, -{0x4d10,0x4df0,16,2, 16,Z4D_ddN0_0000_addr, "com %a1(%rw2)", 0}, -{0x4d11,0x4df1,16,3, 15,Z4D_ddN0_0001_addr_imm16, "cp %a1(%rw2),%#w2", 0}, -{0x4d12,0x4df2,16,2, 16,Z4D_ddN0_0010_addr, "neg %a1(%rw2)", 0}, -{0x4d14,0x4df4,16,2, 12,Z4D_ddN0_0100_addr, "test %a1(%rw2)", 0}, -{0x4d15,0x4df5,16,3, 15,Z4D_ddN0_0101_addr_imm16, "ld %a1(%rw2),%#w2", 0}, -{0x4d16,0x4df6,16,2, 15,Z4D_ddN0_0110_addr, "tset %a1(%rw2)", 0}, -{0x4d18,0x4df8,16,2, 12,Z4D_ddN0_1000_addr, "clr %a1(%rw2)", 0}, -{0x4e11,0x4ef0,16,2, 12,Z4E_ddN0_ssN0_addr, "ldb %a1(%rw2),%rb3", 0}, -{0x5000,0x500f, 1,2, 15,Z50_0000_dddd_addr, "cpl %rl3,%a1", 0}, -{0x5010,0x50ff, 1,2, 16,Z50_ssN0_dddd_addr, "cpl %rl3,%a1(%rw2)", 0}, -{0x5110,0x51f0,16,2, 21,Z51_ddN0_0000_addr, "pushl @%rw2,%a1", 0}, -{0x5111,0x51f1,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5112,0x51f2,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5113,0x51f3,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5114,0x51f4,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5115,0x51f5,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5116,0x51f6,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5117,0x51f7,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5118,0x51f8,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5119,0x51f9,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x511a,0x51fa,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x511b,0x51fb,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x511c,0x51fc,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x511d,0x51fd,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x511e,0x51fe,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x511f,0x51ff,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, -{0x5200,0x520f, 1,2, 15,Z52_0000_dddd_addr, "subl %rl3,%a1", 0}, -{0x5210,0x52ff, 1,2, 16,Z52_ssN0_dddd_addr, "subl %rl3,%a1(%rw2)", 0}, -{0x5310,0x53f0,16,2, 14,Z53_ddN0_0000_addr, "push @%rw2,%a1", 0}, -{0x5311,0x53f1,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5312,0x53f2,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5313,0x53f3,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5314,0x53f4,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5315,0x53f5,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5316,0x53f6,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5317,0x53f7,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5318,0x53f8,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5319,0x53f9,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x531a,0x53fa,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x531b,0x53fb,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x531c,0x53fc,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x531d,0x53fd,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x531e,0x53fe,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x531f,0x53ff,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, -{0x5400,0x540f, 1,2, 12,Z54_0000_dddd_addr, "ldl %rl3,%a1", 0}, -{0x5410,0x54ff, 1,2, 13,Z54_ssN0_dddd_addr, "ldl %rl3,%a1(%rw2)", 0}, -{0x5510,0x55f0,16,2, 23,Z55_ssN0_0000_addr, "popl %a1,@%rw2", 0}, -{0x5511,0x55f1,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5512,0x55f2,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5513,0x55f3,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5514,0x55f4,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5515,0x55f5,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5516,0x55f6,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5517,0x55f7,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5518,0x55f8,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5519,0x55f9,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x551a,0x55fa,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x551b,0x55fb,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x551c,0x55fc,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x551d,0x55fd,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x551e,0x55fe,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x551f,0x55ff,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, -{0x5600,0x560f, 1,2, 15,Z56_0000_dddd_addr, "addl %rl3,%a1", 0}, -{0x5610,0x56ff, 1,2, 16,Z56_ssN0_dddd_addr, "addl %rl3,%a1(%rw2)", 0}, -{0x5710,0x57f0,16,2, 16,Z57_ssN0_0000_addr, "pop %a1,@%rw2", 0}, -{0x5711,0x57f1,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5712,0x57f2,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5713,0x57f3,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5714,0x57f4,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5715,0x57f5,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5716,0x57f6,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5717,0x57f7,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5718,0x57f8,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5719,0x57f9,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x571a,0x57fa,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x571b,0x57fb,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x571c,0x57fc,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x571d,0x57fd,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x571e,0x57fe,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x571f,0x57ff,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, -{0x5800,0x580f, 1,2,283,Z58_0000_dddd_addr, "multl %rq3,%a1", 0}, -{0x5810,0x58ff, 1,2,284,Z58_ssN0_dddd_addr, "multl %rq3,%a1(%rw2)", 0}, -{0x5900,0x590f, 1,2, 71,Z59_0000_dddd_addr, "mult %rl3,%a1", 0}, -{0x5910,0x59ff, 1,2, 72,Z59_ssN0_dddd_addr, "mult %rl3,%a1(%rw2)", 0}, -{0x5a00,0x5a0f, 1,2,745,Z5A_0000_dddd_addr, "divl %rq3,%a1", 0}, -{0x5a10,0x5aff, 1,2,746,Z5A_ssN0_dddd_addr, "divl %rq3,%a1(%rw2)", 0}, -{0x5b00,0x5b0f, 1,2,108,Z5B_0000_dddd_addr, "div %rl3,%a1", 0}, -{0x5b10,0x5bff, 1,2,109,Z5B_ssN0_dddd_addr, "div %rl3,%a1(%rw2)", 0}, -{0x5c01,0x5c01, 1,3, 14,Z5C_0000_0001_0000_dddd_0000_nmin1_addr, "ldm %rw5,%a2,#%n", 0}, -{0x5c08,0x5c08, 1,2, 16,Z5C_0000_1000_addr, "testl %a1", 0}, -{0x5c09,0x5c09, 1,3, 14,Z5C_0000_1001_0000_ssss_0000_nmin1_addr, "ldm %a2,%rw5,#%n", 0}, -{0x5c11,0x5cf1,16,3, 15,Z5C_ssN0_0001_0000_dddd_0000_nmin1_addr, "ldm %rw5,%a2(%rw2),#%n", 0}, -{0x5c18,0x5cf8,16,2, 17,Z5C_ddN0_1000_addr, "testl %a1(%rw2)", 0}, -{0x5c19,0x5cf9,16,3, 15,Z5C_ddN0_1001_0000_ssN0_0000_nmin1_addr, "ldm %a2(%rw2),%rw5,#%n", 0}, -{0x5d00,0x5d0f, 1,2, 15,Z5D_0000_ssss_addr, "ldl %a1,%rl3", 0}, -{0x5d10,0x5dff, 1,2, 14,Z5D_ddN0_ssss_addr, "ldl %a1(%rw2),%rl3", 0}, -{0x5e00,0x5e0f, 1,2, 7,Z5E_0000_cccc_addr, "jp %c3,%a1", 0}, -{0x5e10,0x5eff, 1,2, 8,Z5E_ddN0_cccc_addr, "jp %c3,%a1(%rw2)", 0}, -{0x5f00,0x5f00, 1,2, 12,Z5F_0000_0000_addr, "call %a1", DASMFLAG_STEP_OVER}, -{0x5f10,0x5ff0,16,2, 13,Z5F_ddN0_0000_addr, "call %a1(%rw2)", DASMFLAG_STEP_OVER}, -{0x6000,0x600f, 1,2, 9,Z60_0000_dddd_addr, "ldb %rb3,%a1", 0}, -{0x6010,0x60ff, 1,2, 10,Z60_ssN0_dddd_addr, "ldb %rb3,%a1(%rw2)", 0}, -{0x6100,0x610f, 1,2, 9,Z61_0000_dddd_addr, "ld %rw3,%a1", 0}, -{0x6110,0x61ff, 1,2, 10,Z61_ssN0_dddd_addr, "ld %rw3,%a1(%rw2)", 0}, -{0x6200,0x620f, 1,2, 13,Z62_0000_imm4_addr, "resb %a1,%3", 0}, -{0x6210,0x62ff, 1,2, 14,Z62_ddN0_imm4_addr, "resb %a1(%rw2),%3", 0}, -{0x6300,0x630f, 1,2, 13,Z63_0000_imm4_addr, "res %a1,%3", 0}, -{0x6310,0x63ff, 1,2, 14,Z63_ddN0_imm4_addr, "res %a1(%rw2),%3", 0}, -{0x6400,0x640f, 1,2, 13,Z64_0000_imm4_addr, "setb %a1,%3", 0}, -{0x6410,0x64ff, 1,2, 14,Z64_ddN0_imm4_addr, "setb %a1(%rw2),%3", 0}, -{0x6500,0x650f, 1,2, 13,Z65_0000_imm4_addr, "set %a1,%3", 0}, -{0x6510,0x65ff, 1,2, 14,Z65_ddN0_imm4_addr, "set %a1(%rw2),%3", 0}, -{0x6600,0x660f, 1,2, 10,Z66_0000_imm4_addr, "bitb %a1,%3", 0}, -{0x6610,0x66ff, 1,2, 11,Z66_ddN0_imm4_addr, "bitb %a1(%rw2),%3", 0}, -{0x6700,0x670f, 1,2, 10,Z67_0000_imm4_addr, "bit %a1,%3", 0}, -{0x6710,0x67ff, 1,2, 11,Z67_ddN0_imm4_addr, "bit %a1(%rw2),%3", 0}, -{0x6800,0x680f, 1,2, 13,Z68_0000_imm4m1_addr, "incb %a1,%+3", 0}, -{0x6810,0x68ff, 1,2, 14,Z68_ddN0_imm4m1_addr, "incb %a1(%rw2),%+3", 0}, -{0x6900,0x690f, 1,2, 13,Z69_0000_imm4m1_addr, "inc %a1,%+3", 0}, -{0x6910,0x69ff, 1,2, 14,Z69_ddN0_imm4m1_addr, "inc %a1(%rw2),%+3", 0}, -{0x6a00,0x6a0f, 1,2, 13,Z6A_0000_imm4m1_addr, "decb %a1,%+3", 0}, -{0x6a10,0x6aff, 1,2, 14,Z6A_ddN0_imm4m1_addr, "decb %a1(%rw2),%+3", 0}, -{0x6b00,0x6b0f, 1,2, 13,Z6B_0000_imm4m1_addr, "dec %a1,%+3", 0}, -{0x6b10,0x6bff, 1,2, 14,Z6B_ddN0_imm4m1_addr, "dec %a1(%rw2),%+3", 0}, -{0x6c00,0x6c0f, 1,2, 15,Z6C_0000_dddd_addr, "exb %rb3,%a1", 0}, -{0x6c10,0x6cff, 1,2, 16,Z6C_ssN0_dddd_addr, "exb %rb3,%a1(%rw2)", 0}, -{0x6d00,0x6d0f, 1,2, 15,Z6D_0000_dddd_addr, "ex %rw3,%a1", 0}, -{0x6d10,0x6dff, 1,2, 16,Z6D_ssN0_dddd_addr, "ex %rw3,%a1(%rw2)", 0}, -{0x6e00,0x6e0f, 1,2, 11,Z6E_0000_ssss_addr, "ldb %a1,%rb3", 0}, -{0x6e10,0x6eff, 1,2, 11,Z6E_ddN0_ssss_addr, "ldb %a1(%rw2),%rb3", 0}, -{0x6f00,0x6f0f, 1,2, 11,Z6F_0000_ssss_addr, "ld %a1,%rw3", 0}, -{0x6f10,0x6fff, 1,2, 12,Z6F_ddN0_ssss_addr, "ld %a1(%rw2),%rw3", 0}, -{0x7010,0x70ff, 1,2, 14,Z70_ssN0_dddd_0000_xxxx_0000_0000, "ldb %rb3,%rw2(%rw5)", 0}, -{0x7110,0x71ff, 1,2, 14,Z71_ssN0_dddd_0000_xxxx_0000_0000, "ld %rw3,%rw2(%rw5)", 0}, -{0x7210,0x72ff, 1,2, 14,Z72_ddN0_ssss_0000_xxxx_0000_0000, "ldb %rw2(%rw5),%rb3", 0}, -{0x7310,0x73ff, 1,2, 14,Z73_ddN0_ssss_0000_xxxx_0000_0000, "ld %rw2(%rw5),%rw3", 0}, -{0x7410,0x74ff, 1,2, 15,Z74_ssN0_dddd_0000_xxxx_0000_0000, "lda p%rw3,%rw2(%rw5)", 0}, -{0x7510,0x75ff, 1,2, 17,Z75_ssN0_dddd_0000_xxxx_0000_0000, "ldl %rl3,%rw2(%rw5)", 0}, -{0x7600,0x760f, 1,2, 12,Z76_0000_dddd_addr, "lda p%rw3,%a1", 0}, -{0x7610,0x76ff, 1,2, 13,Z76_ssN0_dddd_addr, "lda p%rw3,%a1(%rw2)", 0}, -{0x7710,0x77ff, 1,2, 17,Z77_ddN0_ssss_0000_xxxx_0000_0000, "ldl %rw2(%rw5),%rl3", 0}, -{0x7800,0x78ff, 1,1, 10,Z78_imm8, "rsvd78", 0}, -{0x7900,0x7900, 1,2, 16,Z79_0000_0000_addr, "ldps %a1", 0}, -{0x7910,0x79f0,16,2, 17,Z79_ssN0_0000_addr, "ldps %a1(%rw2)", 0}, -{0x7a00,0x7a00, 1,1, 8,Z7A_0000_0000, "halt", DASMFLAG_STEP_OVER}, -{0x7b00,0x7b00, 1,1, 13,Z7B_0000_0000, "iret", DASMFLAG_STEP_OUT}, -{0x7b08,0x7b08, 1,1, 5,Z7B_0000_1000, "mset", 0}, -{0x7b09,0x7b09, 1,1, 5,Z7B_0000_1001, "mres", 0}, -{0x7b0a,0x7b0a, 1,1, 7,Z7B_0000_1010, "mbit", 0}, -{0x7b0d,0x7bfd,16,1, 12,Z7B_dddd_1101, "mreq %rw2", 0}, -{0x7c00,0x7c03, 1,1, 7,Z7C_0000_00ii, "di %i3", 0}, -{0x7c04,0x7c07, 1,1, 7,Z7C_0000_01ii, "ei %i3", 0}, -{0x7d00,0x7df0,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,ctrl0", 0}, -{0x7d01,0x7df1,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,ctrl1", 0}, -{0x7d02,0x7df2,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,fcw", 0}, -{0x7d03,0x7df3,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,refresh", 0}, -{0x7d04,0x7df4,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,psapseg", 0}, -{0x7d05,0x7df5,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,psapoff", 0}, -{0x7d06,0x7df6,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,nspseg", 0}, -{0x7d07,0x7df7,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,nspoff", 0}, -{0x7d08,0x7df8,16,1, 7,Z7D_ssss_1ccc, "ldctl ctrl0,%rw2", 0}, -{0x7d09,0x7df9,16,1, 7,Z7D_ssss_1ccc, "ldctl ctrl1,%rw2", 0}, -{0x7d0a,0x7dfa,16,1, 7,Z7D_ssss_1ccc, "ldctl fcw,%rw2", 0}, -{0x7d0b,0x7dfb,16,1, 7,Z7D_ssss_1ccc, "ldctl refresh,%rw2", 0}, -{0x7d0c,0x7dfc,16,1, 7,Z7D_ssss_1ccc, "ldctl psapseg,%rw2", 0}, -{0x7d0d,0x7dfd,16,1, 7,Z7D_ssss_1ccc, "ldctl psapoff,%rw2", 0}, -{0x7d0e,0x7dfe,16,1, 7,Z7D_ssss_1ccc, "ldctl nspseg,%rw2", 0}, -{0x7d0f,0x7dff,16,1, 7,Z7D_ssss_1ccc, "ldctl nspoff,%rw2", 0}, -{0x7e00,0x7eff, 1,1, 10,Z7E_imm8, "rsvd7e %#b1", 0}, -{0x7f00,0x7fff, 1,1, 33,Z7F_imm8, "sc %#b1", 0}, -{0x8000,0x80ff, 1,1, 4,Z80_ssss_dddd, "addb %rb3,%rb2", 0}, -{0x8100,0x81ff, 1,1, 4,Z81_ssss_dddd, "add %rw3,%rw2", 0}, -{0x8200,0x82ff, 1,1, 4,Z82_ssss_dddd, "subb %rb3,%rb2", 0}, -{0x8300,0x83ff, 1,1, 4,Z83_ssss_dddd, "sub %rw3,%rw2", 0}, -{0x8400,0x84ff, 1,1, 4,Z84_ssss_dddd, "orb %rb3,%rb2", 0}, -{0x8500,0x85ff, 1,1, 4,Z85_ssss_dddd, "or %rw3,%rw2", 0}, -{0x8600,0x86ff, 1,1, 4,Z86_ssss_dddd, "andb %rb3,%rb2", 0}, -{0x8700,0x87ff, 1,1, 4,Z87_ssss_dddd, "and %rw3,%rw2", 0}, -{0x8800,0x88ff, 1,1, 4,Z88_ssss_dddd, "xorb %rb3,%rb2", 0}, -{0x8900,0x89ff, 1,1, 4,Z89_ssss_dddd, "xor %rw3,%rw2", 0}, -{0x8a00,0x8aff, 1,1, 4,Z8A_ssss_dddd, "cpb %rb3,%rb2", 0}, -{0x8b00,0x8bff, 1,1, 4,Z8B_ssss_dddd, "cp %rw3,%rw2", 0}, -{0x8c00,0x8cf0,16,1, 7,Z8C_dddd_0000, "comb %rb2", 0}, -{0x8c02,0x8cf2,16,1, 7,Z8C_dddd_0010, "negb %rb2", 0}, -{0x8c04,0x8cf4,16,1, 7,Z8C_dddd_0100, "testb %rb2", 0}, -{0x8c06,0x8cf6,16,1, 7,Z8C_dddd_0110, "tsetb %rb2", 0}, -{0x8c01,0x8cf1,16,1, 7,Z8C_dddd_0001, "ldctlb %rb2,flags", 0}, -{0x8c08,0x8cf8,16,1, 7,Z8C_dddd_1000, "clrb %rb2", 0}, -{0x8c09,0x8cf9,16,1, 7,Z8C_dddd_1001, "ldctlb flags,%rb2", 0}, -{0x8d00,0x8df0,16,1, 7,Z8D_dddd_0000, "com %rw2", 0}, -{0x8d01,0x8df1,16,1, 7,Z8D_imm4_0001, "setflg %f2", 0}, -{0x8d02,0x8df2,16,1, 7,Z8D_dddd_0010, "neg %rw2", 0}, -{0x8d03,0x8df3,16,1, 7,Z8D_imm4_0011, "resflg %f2", 0}, -{0x8d04,0x8df4,16,1, 7,Z8D_dddd_0100, "test %rw2", 0}, -{0x8d05,0x8df5,16,1, 7,Z8D_imm4_0101, "comflg %f2", 0}, -{0x8d06,0x8df6,16,1, 7,Z8D_dddd_0110, "tset %rw2", 0}, -{0x8d07,0x8d07, 1,1, 7,Z8D_0000_0111, "nop", 0}, -{0x8d08,0x8df8,16,1, 7,Z8D_dddd_1000, "clr %rw2", 0}, -{0x8e00,0x8eff, 1,1, 10,Z8E_imm8, "ext8e %#b1", 0}, -{0x8f00,0x8fff, 1,1, 10,Z8F_imm8, "ext8f %#b1", 0}, -{0x9000,0x90ff, 1,1, 8,Z90_ssss_dddd, "cpl %rl3,%rl2", 0}, -{0x9110,0x91ff, 1,1, 12,Z91_ddN0_ssss, "pushl @%rw2,%rl3", 0}, -{0x9200,0x92ff, 1,1, 8,Z92_ssss_dddd, "subl %rl3,%rl2", 0}, -{0x9310,0x93ff, 1,1, 9,Z93_ddN0_ssss, "push @%rw2,%rw3", 0}, -{0x9400,0x94ff, 1,1, 5,Z94_ssss_dddd, "ldl %rl3,%rl2", 0}, -{0x9510,0x95ff, 1,1, 12,Z95_ssN0_dddd, "popl %rl3,@%rw2", 0}, -{0x9600,0x96ff, 1,1, 8,Z96_ssss_dddd, "addl %rl3,%rl2", 0}, -{0x9710,0x97ff, 1,1, 8,Z97_ssN0_dddd, "pop %rw3,@%rw2", 0}, -{0x9800,0x98ff, 1,1,282,Z98_ssss_dddd, "multl %rq3,%rl2", 0}, -{0x9900,0x99ff, 1,1, 70,Z99_ssss_dddd, "mult %rl3,%rw2", 0}, -{0x9a00,0x9aff, 1,1,744,Z9A_ssss_dddd, "divl %rq3,%rl2", 0}, -{0x9b00,0x9bff, 1,1,107,Z9B_ssss_dddd, "div %rl3,%rw2", 0}, -{0x9c08,0x9cf8,16,1, 13,Z9C_dddd_1000, "testl %rl2", 0}, -{0x9d00,0x9dff, 1,1, 10,Z9D_imm8, "rsvd9d", 0}, -{0x9e00,0x9e0f, 1,1, 10,Z9E_0000_cccc, "ret %c3", DASMFLAG_STEP_OUT}, -{0x9f00,0x9fff, 1,1, 10,Z9F_imm8, "rsvd9f", 0}, -{0xa000,0xa0ff, 1,1, 3,ZA0_ssss_dddd, "ldb %rb3,%rb2", 0}, -{0xa100,0xa1ff, 1,1, 3,ZA1_ssss_dddd, "ld %rw3,%rw2", 0}, -{0xa200,0xa2ff, 1,1, 4,ZA2_dddd_imm4, "resb %rb2,%3", 0}, -{0xa300,0xa3ff, 1,1, 4,ZA3_dddd_imm4, "res %rw2,%3", 0}, -{0xa400,0xa4ff, 1,1, 4,ZA4_dddd_imm4, "setb %rb2,%3", 0}, -{0xa500,0xa5ff, 1,1, 4,ZA5_dddd_imm4, "set %rw2,%3", 0}, -{0xa600,0xa6ff, 1,1, 4,ZA6_dddd_imm4, "bitb %rb2,%3", 0}, -{0xa700,0xa7ff, 1,1, 4,ZA7_dddd_imm4, "bit %rw2,%3", 0}, -{0xa800,0xa8ff, 1,1, 4,ZA8_dddd_imm4m1, "incb %rb2,%+3", 0}, -{0xa900,0xa9ff, 1,1, 4,ZA9_dddd_imm4m1, "inc %rw2,%+3", 0}, -{0xaa00,0xaaff, 1,1, 4,ZAA_dddd_imm4m1, "decb %rb2,%+3", 0}, -{0xab00,0xabff, 1,1, 4,ZAB_dddd_imm4m1, "dec %rw2,%+3", 0}, -{0xac00,0xacff, 1,1, 6,ZAC_ssss_dddd, "exb %rb3,%rb2", 0}, -{0xad00,0xadff, 1,1, 6,ZAD_ssss_dddd, "ex %rw3,%rw2", 0}, -{0xae00,0xaeff, 1,1, 5,ZAE_dddd_cccc, "tccb %c3,%rb2", 0}, -{0xaf00,0xafff, 1,1, 5,ZAF_dddd_cccc, "tcc %c3,%rw2", 0}, -{0xb000,0xb0f0,16,1, 5,ZB0_dddd_0000, "dab %rb2", 0}, -{0xb100,0xb1f0,16,1, 11,ZB1_dddd_0000, "extsb %rw2", 0}, -{0xb107,0xb1f7,16,1, 11,ZB1_dddd_0111, "extsl %rq2", 0}, -{0xb10a,0xb1fa,16,1, 11,ZB1_dddd_1010, "exts %rl2", 0}, -{0xb200,0xb2f0,16,1, 6,ZB2_dddd_00I0, "rlb %rb2,%?3", 0}, -{0xb201,0xb2f1,16,2, 13,ZB2_dddd_0001_imm8, "s%*lb %rb2,%$3", 0}, -{0xb202,0xb2f2,16,1, 6,ZB2_dddd_00I0, "rlb %rb2,%?3", 0}, -{0xb203,0xb2f3,16,2, 15,ZB2_dddd_0011_0000_ssss_0000_0000, "sdlb %rb2,%rw5", 0}, -{0xb204,0xb2f4,16,1, 6,ZB2_dddd_01I0, "rrb %rb2,%?3", 0}, -{0xb206,0xb2f6,16,1, 6,ZB2_dddd_01I0, "rrb %rb2,%?3", 0}, -{0xb208,0xb2f8,16,1, 9,ZB2_dddd_10I0, "rlcb %rb2,%?3", 0}, -{0xb209,0xb2f9,16,2, 13,ZB2_dddd_1001_imm8, "s%*ab %rb2,%$3", 0}, -{0xb20a,0xb2fa,16,1, 9,ZB2_dddd_10I0, "rlcb %rb2,%?3", 0}, -{0xb20b,0xb2fb,16,2, 15,ZB2_dddd_1011_0000_ssss_0000_0000, "sdab %rb2,%rw5", 0}, -{0xb20c,0xb2fc,16,1, 9,ZB2_dddd_11I0, "rrcb %rb2,%?3", 0}, -{0xb20e,0xb2fe,16,1, 9,ZB2_dddd_11I0, "rrcb %rb2,%?3", 0}, -{0xb300,0xb3f0,16,1, 6,ZB3_dddd_00I0, "rl %rw2,%?3", 0}, -{0xb301,0xb3f1,16,2, 13,ZB3_dddd_0001_imm8, "s%*l %rw2,%$3", 0}, -{0xb302,0xb3f2,16,1, 6,ZB3_dddd_00I0, "rl %rw2,%?3", 0}, -{0xb303,0xb3f3,16,2, 15,ZB3_dddd_0011_0000_ssss_0000_0000, "sdl %rw2,%rw5", 0}, -{0xb304,0xb3f4,16,1, 6,ZB3_dddd_01I0, "rr %rw2,%?3", 0}, -{0xb305,0xb3f5,16,2, 13,ZB3_dddd_0101_imm8, "s%*ll %rl2,%$3", 0}, -{0xb306,0xb3f6,16,1, 6,ZB3_dddd_01I0, "rr %rw2,%?3", 0}, -{0xb307,0xb3f7,16,2, 15,ZB3_dddd_0111_0000_ssss_0000_0000, "sdll %rl2,%rw5", 0}, -{0xb308,0xb3f8,16,1, 6,ZB3_dddd_10I0, "rlc %rw2,%?3", 0}, -{0xb309,0xb3f9,16,2, 13,ZB3_dddd_1001_imm8, "s%*a %rw2,%$3", 0}, -{0xb30a,0xb3fa,16,1, 6,ZB3_dddd_10I0, "rlc %rw2,%?3", 0}, -{0xb30b,0xb3fb,16,2, 15,ZB3_dddd_1011_0000_ssss_0000_0000, "sda %rw2,%rw5", 0}, -{0xb30c,0xb3fc,16,1, 6,ZB3_dddd_11I0, "rrc %rw2,%?3", 0}, -{0xb30d,0xb3fd,16,2, 13,ZB3_dddd_1101_imm8, "s%*al %rl2,%$3", 0}, -{0xb30e,0xb3fe,16,1, 6,ZB3_dddd_11I0, "rrc %rw2,%?3", 0}, -{0xb30f,0xb3ff,16,2, 15,ZB3_dddd_1111_0000_ssss_0000_0000, "sdal %rl2,%rw5", 0}, -{0xb400,0xb4ff, 1,1, 5,ZB4_ssss_dddd, "adcb %rb3,%rb2", 0}, -{0xb500,0xb5ff, 1,1, 5,ZB5_ssss_dddd, "adc %rw3,%rw2", 0}, -{0xb600,0xb6ff, 1,1, 5,ZB6_ssss_dddd, "sbcb %rb3,%rb2", 0}, -{0xb700,0xb7ff, 1,1, 5,ZB7_ssss_dddd, "sbc %rw3,%rw2", 0}, -{0xb810,0xb8f0,16,2, 25,ZB8_ddN0_0000_0000_rrrr_ssN0_0000, "trib @%rw2,@%rw6,%rb5", 0}, -{0xb812,0xb8f2,16,2, 25,ZB8_ddN0_0010_0000_rrrr_ssN0_0000, "trtib @%rw2,@%rw6,%rb5", 0}, -{0xb814,0xb8f4,16,2, 25,ZB8_ddN0_0100_0000_rrrr_ssN0_0000, "trirb @%rw2,@%rw6,%rb5", 0}, -{0xb816,0xb8f6,16,2, 25,ZB8_ddN0_0110_0000_rrrr_ssN0_1110, "trtirb @%rw2,@%rw6,%rb5", 0}, -{0xb818,0xb8f8,16,2, 25,ZB8_ddN0_1000_0000_rrrr_ssN0_0000, "trdb @%rw2,@%rw6,%rb5", 0}, -{0xb81a,0xb8fa,16,2, 25,ZB8_ddN0_1010_0000_rrrr_ssN0_0000, "trtrb @%rw2,@%rw6,%rb5", 0}, -{0xb81c,0xb8fc,16,2, 25,ZB8_ddN0_1100_0000_rrrr_ssN0_0000, "trdrb @%rw2,@%rw6,%rb5", 0}, -{0xb81e,0xb8fe,16,2, 25,ZB8_ddN0_1110_0000_rrrr_ssN0_1110, "trtdrb @%rw2,@%rw6,%rb5", 0}, -{0xb900,0xb9ff,16,1, 10,ZB9_imm8, "rsvdb9", 0}, -{0xba10,0xbaf0,16,2, 11,ZBA_ssN0_0000_0000_rrrr_dddd_cccc, "cpib %rb6,@%rw2,%rw5,%c7", 0}, -{0xba11,0xbaf1,16,2, 11,ZBA_ssN0_0001_0000_rrrr_ddN0_x000, "ldirb @%rw6,@%rw2,%rw5", DASMFLAG_STEP_OVER}, -{0xba12,0xbaf2,16,2, 11,ZBA_ssN0_0010_0000_rrrr_ddN0_cccc, "cpsib @%rw6,@%rw2,%rw5,%c7", 0}, -{0xba14,0xbaf4,16,2, 11,ZBA_ssN0_0100_0000_rrrr_dddd_cccc, "cpirb %rb6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, -{0xba16,0xbaf6,16,2, 11,ZBA_ssN0_0110_0000_rrrr_ddN0_cccc, "cpsirb @%rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, -{0xba18,0xbaf8,16,2, 11,ZBA_ssN0_1000_0000_rrrr_dddd_cccc, "cpdb %rb6,@%rw2,%rw5,%c7", 0}, -{0xba19,0xbaf9,16,2, 11,ZBA_ssN0_1001_0000_rrrr_ddN0_x000, "lddrb @%rw2,@%rw6,%rw5", DASMFLAG_STEP_OVER}, -{0xba1a,0xbafa,16,2, 11,ZBA_ssN0_1010_0000_rrrr_ddN0_cccc, "cpsdb @%rw6,@%rw2,%rw5,%c7", 0}, -{0xba1c,0xbafc,16,2, 11,ZBA_ssN0_1100_0000_rrrr_dddd_cccc, "cpdrb %rb6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, -{0xba1e,0xbafe,16,2, 11,ZBA_ssN0_1110_0000_rrrr_ddN0_cccc, "cpsdrb @%rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, -{0xbb10,0xbbf0,16,2, 11,ZBB_ssN0_0000_0000_rrrr_dddd_cccc, "cpi %rw6,@%rw2,%rw5,%c7", 0}, -{0xbb11,0xbbf1,16,2, 11,ZBB_ssN0_0001_0000_rrrr_ddN0_x000, "ldir @%rw6,@%rw2,%rw5", DASMFLAG_STEP_OVER}, -{0xbb12,0xbbf2,16,2, 11,ZBB_ssN0_0010_0000_rrrr_ddN0_cccc, "cpsi @%rw6,@%rw2,%rw5,%c7", 0}, -{0xbb14,0xbbf4,16,2, 11,ZBB_ssN0_0100_0000_rrrr_dddd_cccc, "cpir %rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, -{0xbb16,0xbbf6,16,2, 11,ZBB_ssN0_0110_0000_rrrr_ddN0_cccc, "cpsir @%rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, -{0xbb18,0xbbf8,16,2, 11,ZBB_ssN0_1000_0000_rrrr_dddd_cccc, "cpd %rw6,@%rw2,%rw5,%c7", 0}, -{0xbb19,0xbbf9,16,2, 11,ZBB_ssN0_1001_0000_rrrr_ddN0_x000, "lddr @%rw2,@%rw6,%rw5", DASMFLAG_STEP_OVER}, -{0xbb1a,0xbbfa,16,2, 11,ZBB_ssN0_1010_0000_rrrr_ddN0_cccc, "cpsd @%rw6,@%rw2,%rw5,%c7", 0}, -{0xbb1c,0xbbfc,16,2, 11,ZBB_ssN0_1100_0000_rrrr_dddd_cccc, "cpdr %rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, -{0xbb1e,0xbbfe,16,2, 11,ZBB_ssN0_1110_0000_rrrr_ddN0_cccc, "cpsdr @%rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, -{0xbc00,0xbcff, 1,1, 9,ZBC_aaaa_bbbb, "rrdb %rb3,%rb2", 0}, -{0xbd00,0xbdff, 1,1, 5,ZBD_dddd_imm4, "ldk %rw2,%3", 0}, -{0xbe00,0xbeff, 1,1, 9,ZBE_aaaa_bbbb, "rldb %rb3,%rb2", 0}, -{0xbf00,0xbfff, 1,1, 10,ZBF_imm8, "rsvdbf", 0}, -{0xc000,0xcfff, 1,1, 5,ZC_dddd_imm8, "ldb %rb1,%#b1", 0}, -{0xd000,0xdfff, 1,1, 10,ZD_dsp12, "calr %d2", DASMFLAG_STEP_OVER}, -{0xe000,0xefff, 1,1, 6,ZE_cccc_dsp8, "jr %c1,%d1", 0}, -{0xf000,0xf07f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf100,0xf17f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf200,0xf27f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf300,0xf37f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf400,0xf47f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf500,0xf57f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf600,0xf67f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf700,0xf77f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf800,0xf87f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf900,0xf97f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xfa00,0xfa7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xfb00,0xfb7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xfc00,0xfc7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xfd00,0xfd7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xfe00,0xfe7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xff00,0xff7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, -{0xf080,0xf0ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf180,0xf1ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf280,0xf2ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf380,0xf3ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf480,0xf4ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf580,0xf5ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf680,0xf6ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf780,0xf7ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf880,0xf8ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xf980,0xf9ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xfa80,0xfaff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xfb80,0xfbff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xfc80,0xfcff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xfd80,0xfdff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xfe80,0xfeff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0xff80,0xffff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, -{0, 0, 0,0, 0,NULL, NULL, 0} +{0x0000,0x000f, 1,2, 7,Z00_0000_dddd_imm8, "addb %rb3,%#b3", 0}, +{0x0010,0x00ff, 1,1, 7,Z00_ssN0_dddd, "addb %rb3,@%rw2", 0}, +{0x0100,0x010f, 1,2, 7,Z01_0000_dddd_imm16, "add %rw3,%#w1", 0}, +{0x0110,0x01ff, 1,1, 7,Z01_ssN0_dddd, "add %rw3,@%rw2", 0}, +{0x0200,0x020f, 1,2, 7,Z02_0000_dddd_imm8, "subb %rb3,%#b3", 0}, +{0x0210,0x02ff, 1,1, 7,Z02_ssN0_dddd, "subb %rb3,@%rw2", 0}, +{0x0300,0x030f, 1,2, 7,Z03_0000_dddd_imm16, "sub %rw3,%#w1", 0}, +{0x0310,0x03ff, 1,1, 7,Z03_ssN0_dddd, "sub %rw3,@%rw2", 0}, +{0x0400,0x040f, 1,2, 7,Z04_0000_dddd_imm8, "orb %rb3,%#b3", 0}, +{0x0410,0x04ff, 1,1, 7,Z04_ssN0_dddd, "orb %rb3,@%rw2", 0}, +{0x0500,0x050f, 1,2, 7,Z05_0000_dddd_imm16, "or %rw3,%#w1", 0}, +{0x0510,0x05ff, 1,1, 7,Z05_ssN0_dddd, "or %rw3,@%rw2", 0}, +{0x0600,0x060f, 1,2, 7,Z06_0000_dddd_imm8, "andb %rb3,%#b3", 0}, +{0x0610,0x06ff, 1,1, 7,Z06_ssN0_dddd, "andb %rb3,@%rw2", 0}, +{0x0700,0x070f, 1,2, 7,Z07_0000_dddd_imm16, "and %rw3,%#w1", 0}, +{0x0710,0x07ff, 1,1, 7,Z07_ssN0_dddd, "and %rw3,@%rw2", 0}, +{0x0800,0x080f, 1,2, 7,Z08_0000_dddd_imm8, "xorb %rb3,%#b3", 0}, +{0x0810,0x08ff, 1,1, 7,Z08_ssN0_dddd, "xorb %rb3,@%rw2", 0}, +{0x0900,0x090f, 1,2, 7,Z09_0000_dddd_imm16, "xor %rw3,%#w1", 0}, +{0x0910,0x09ff, 1,1, 7,Z09_ssN0_dddd, "xor %rw3,@%rw2", 0}, +{0x0a00,0x0a0f, 1,2, 7,Z0A_0000_dddd_imm8, "cpb %rb3,%#b3", 0}, +{0x0a10,0x0aff, 1,1, 7,Z0A_ssN0_dddd, "cpb %rb3,@%rw2", 0}, +{0x0b00,0x0b0f, 1,2, 7,Z0B_0000_dddd_imm16, "cp %rw3,%#w1", 0}, +{0x0b10,0x0bff, 1,1, 7,Z0B_ssN0_dddd, "cp %rw3,@%rw2", 0}, +{0x0c10,0x0cf0,16,1, 12,Z0C_ddN0_0000, "comb @%rw2", 0}, +{0x0c11,0x0cf1,16,2, 11,Z0C_ddN0_0001_imm8, "cpb @%rw2,%#b3", 0}, +{0x0c12,0x0cf2,16,1, 12,Z0C_ddN0_0010, "negb @%rw2", 0}, +{0x0c14,0x0cf4,16,1, 8,Z0C_ddN0_0100, "testb @%rw2", 0}, +{0x0c15,0x0cf5,16,2, 7,Z0C_ddN0_0101_imm8, "ldb @%rw2,%#b3", 0}, +{0x0c16,0x0cf6,16,1, 11,Z0C_ddN0_0110, "tsetb @%rw2", 0}, +{0x0c18,0x0cf8,16,1, 8,Z0C_ddN0_1000, "clrb @%rw2", 0}, +{0x0d10,0x0df0,16,1, 12,Z0D_ddN0_0000, "com @%rw2", 0}, +{0x0d11,0x0df1,16,2, 11,Z0D_ddN0_0001_imm16, "cp @%rw2,%#w1", 0}, +{0x0d12,0x0df2,16,1, 12,Z0D_ddN0_0010, "neg @%rw2", 0}, +{0x0d14,0x0df4,16,1, 8,Z0D_ddN0_0100, "test @%rw2", 0}, +{0x0d15,0x0df5,16,2, 11,Z0D_ddN0_0101_imm16, "ld @%rw2,%#w1", 0}, /* fix cycles ld IR,IM */ +{0x0d16,0x0df6,16,1, 11,Z0D_ddN0_0110, "tset @%rw2", 0}, +{0x0d18,0x0df8,16,1, 8,Z0D_ddN0_1000, "clr @%rw2", 0}, +{0x0d19,0x0df9,16,2, 12,Z0D_ddN0_1001_imm16, "push @%rw2,%#w1", 0}, +{0x0e00,0x0eff, 1,1, 10,Z0E_imm8, "ext0e %#b1", 0}, +{0x0f00,0x0fff, 1,1, 10,Z0F_imm8, "ext0f %#b1", 0}, +{0x1000,0x100f, 1,3, 14,Z10_0000_dddd_imm32, "cpl %rl3,%#l1", 0}, +{0x1010,0x10ff, 1,1, 14,Z10_ssN0_dddd, "cpl %rl3,@%rw2", 0}, +{0x1111,0x11ff, 1,1, 20,Z11_ddN0_ssN0, "pushl @%rw2,@%rw3", 0}, +{0x1200,0x120f, 1,3, 14,Z12_0000_dddd_imm32, "subl %rl3,%#l1", 0}, +{0x1210,0x12ff, 1,1, 14,Z12_ssN0_dddd, "subl %rl3,@%rw2", 0}, +{0x1311,0x13ff, 1,1, 13,Z13_ddN0_ssN0, "push @%rw2,@%rw3", 0}, +{0x1400,0x140f, 1,3, 11,Z14_0000_dddd_imm32, "ldl %rl3,%#l1", 0}, +{0x1410,0x14ff, 1,1, 11,Z14_ssN0_dddd, "ldl %rl3,@%rw2", 0}, +{0x1511,0x15ff, 1,1, 19,Z15_ssN0_ddN0, "popl @%rw3,@%rw2", 0}, +{0x1600,0x160f, 1,3, 14,Z16_0000_dddd_imm32, "addl %rl3,%#l1", 0}, +{0x1610,0x16ff, 1,1, 14,Z16_ssN0_dddd, "addl %rl3,@%rw2", 0}, +{0x1711,0x17ff, 1,1, 12,Z17_ssN0_ddN0, "pop @%rw3,@%rw2", 0}, +{0x1800,0x180f, 1,1,282,Z18_00N0_dddd_imm32, "multl %rq3,@%l#1", 0}, +{0x1810,0x18ff, 1,1,282,Z18_ssN0_dddd, "multl %rq3,@%rw2", 0}, +{0x1900,0x190f, 1,2, 70,Z19_0000_dddd_imm16, "mult %rl3,%#w1", 0}, +{0x1910,0x19ff, 1,1, 70,Z19_ssN0_dddd, "mult %rl3,@%rw2", 0}, +{0x1a00,0x1a0f, 1,3,744,Z1A_0000_dddd_imm32, "divl %rq3,%#l1", 0}, +{0x1a10,0x1aff, 1,1,744,Z1A_ssN0_dddd, "divl %rq3,@%rw2", 0}, +{0x1b00,0x1b0f, 1,2,107,Z1B_0000_dddd_imm16, "div %rl3,%#w1", 0}, +{0x1b10,0x1bff, 1,1,107,Z1B_ssN0_dddd, "div %rl3,@%rw2", 0}, +{0x1c11,0x1cf1,16,2, 11,Z1C_ssN0_0001_0000_dddd_0000_nmin1, "ldm %rw5,@%rw2,#%n", 0}, +{0x1c18,0x1cf8,16,1, 13,Z1C_ddN0_1000, "testl @%rw2", 0}, +{0x1c19,0x1cf9,16,2, 11,Z1C_ddN0_1001_0000_ssss_0000_nmin1, "ldm @%rw2,%rw5,#%n", 0}, +{0x1d10,0x1dff, 1,1, 11,Z1D_ddN0_ssss, "ldl @%rw2,%rl3", 0}, +{0x1e10,0x1eff, 1,1, 10,Z1E_ddN0_cccc, "jp %c3,@%rl2", 0}, +{0x1f10,0x1ff0,16,1, 10,Z1F_ddN0_0000, "call %rw2", DASMFLAG_STEP_OVER}, +{0x2010,0x20ff, 1,1, 7,Z20_ssN0_dddd, "ldb %rb3,@%rw2", 0}, +{0x2100,0x210f, 1,2, 7,Z21_0000_dddd_imm16, "ld %rw3,%#w1", 0}, +{0x2110,0x21ff, 1,1, 7,Z21_ssN0_dddd, "ld %rw3,@%rw2", 0}, +{0x2200,0x220f, 1,2, 10,Z22_0000_ssss_0000_dddd_0000_0000, "resb %rb5,%rw3", 0}, +{0x2210,0x22ff, 1,1, 11,Z22_ddN0_imm4, "resb @%rw3,%3", 0}, +{0x2300,0x230f, 1,2, 10,Z23_0000_ssss_0000_dddd_0000_0000, "res %rw5,%rw3", 0}, +{0x2310,0x23ff, 1,1, 11,Z23_ddN0_imm4, "res @%rw3,%3", 0}, +{0x2400,0x240f, 1,2, 10,Z24_0000_ssss_0000_dddd_0000_0000, "setb %rb5,%rw3", 0}, +{0x2410,0x24ff, 1,1, 11,Z24_ddN0_imm4, "setb @%rw3,%3", 0}, +{0x2500,0x250f, 1,2, 10,Z25_0000_ssss_0000_dddd_0000_0000, "set %rw5,%rw3", 0}, +{0x2510,0x25ff, 1,1, 11,Z25_ddN0_imm4, "set @%rw3,%3", 0}, +{0x2600,0x260f, 1,2, 10,Z26_0000_ssss_0000_dddd_0000_0000, "bitb %rb5,%rw3", 0}, +{0x2610,0x26ff, 1,1, 8,Z26_ddN0_imm4, "bitb @%rw3,%3", 0}, +{0x2700,0x270f, 1,2, 10,Z27_0000_ssss_0000_dddd_0000_0000, "bit %rw5,%rw3", 0}, +{0x2710,0x27ff, 1,1, 8,Z27_ddN0_imm4, "bit @%rw2,%3", 0}, +{0x2810,0x28ff, 1,1, 11,Z28_ddN0_imm4m1, "incb @%rw2,%+3", 0}, +{0x2910,0x29ff, 1,1, 11,Z29_ddN0_imm4m1, "inc @%rw2,%+3", 0}, +{0x2a10,0x2aff, 1,1, 11,Z2A_ddN0_imm4m1, "decb @%rw2,%+3", 0}, +{0x2b10,0x2bff, 1,1, 11,Z2B_ddN0_imm4m1, "dec @%rw2,%+3", 0}, +{0x2c10,0x2cff, 1,1, 12,Z2C_ssN0_dddd, "exb %rb3,@%rw2", 0}, +{0x2d10,0x2dff, 1,1, 12,Z2D_ssN0_dddd, "ex %rw3,@%rw2", 0}, +{0x2e10,0x2eff, 1,1, 8,Z2E_ddN0_ssss, "ldb @%rw2,%rb3", 0}, +{0x2f10,0x2fff, 1,1, 8,Z2F_ddN0_ssss, "ld @%rw2,%rw3", 0}, +{0x3000,0x300f, 1,2, 14,Z30_0000_dddd_dsp16, "ldrb %rb3,%p1", 0}, +{0x3010,0x30ff, 1,2, 14,Z30_ssN0_dddd_imm16, "ldb %rb3,%rw2(%#w1)", 0}, +{0x3100,0x310f, 1,2, 14,Z31_0000_dddd_dsp16, "ldr %rw3,%p1", 0}, +{0x3110,0x31ff, 1,2, 14,Z31_ssN0_dddd_imm16, "ld %rw3,%rw2(%#w1)", 0}, +{0x3200,0x320f, 1,2, 14,Z32_0000_ssss_dsp16, "ldrb %p1,%rb3", 0}, +{0x3210,0x32ff, 1,2, 14,Z32_ddN0_ssss_imm16, "ldb %rw2(%#w1),%rb3", 0}, +{0x3300,0x330f, 1,2, 14,Z33_0000_ssss_dsp16, "ldr %p1,%rw3", 0}, +{0x3310,0x33ff, 1,2, 14,Z33_ddN0_ssss_imm16, "ld %rw2(%#w1),%rw3", 0}, +{0x3400,0x340f, 1,2, 15,Z34_0000_dddd_dsp16, "ldar p%rw3,%p1", 0}, +{0x3410,0x34ff, 1,2, 15,Z34_ssN0_dddd_imm16, "lda p%rw3,%rw2(%#w1)", 0}, +{0x3500,0x350f, 1,2, 17,Z35_0000_dddd_dsp16, "ldrl %rl3,%p1", 0}, +{0x3510,0x35ff, 1,2, 17,Z35_ssN0_dddd_imm16, "ldl %rl3,%rw2(%#w1)", 0}, +{0x3600,0x3600, 1,1, 2,Z36_0000_0000, "bpt", 0}, +{0x3601,0x36ff, 1,1, 10,Z36_imm8, "rsvd36", 0}, +{0x3700,0x370f, 1,2, 17,Z37_0000_ssss_dsp16, "ldrl %p1,%rl3", 0}, +{0x3710,0x37ff, 1,2, 17,Z37_ddN0_ssss_imm16, "ldl %rw2(%#w1),%rl3", 0}, +{0x3800,0x38ff, 1,1, 10,Z38_imm8, "rsvd38", 0}, +{0x3910,0x39f0,16,1, 12,Z39_ssN0_0000, "ldps @%rw2", 0}, +{0x3a00,0x3af0,16,2, 21,Z3A_ssss_0000_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3a01,0x3af1,16,2, 21,Z3A_ssss_0001_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3a02,0x3af2,16,2, 21,Z3A_ssss_0010_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3a03,0x3af3,16,2, 21,Z3A_ssss_0011_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3a04,0x3af4,16,2, 10,Z3A_dddd_0100_imm16, "%R %rb2,%#w1", 0}, +{0x3a05,0x3af5,16,2, 10,Z3A_dddd_0101_imm16, "%R %rb2,%#w1", 0}, +{0x3a06,0x3af6,16,2, 12,Z3A_ssss_0110_imm16, "%R %#w1,%rb2", 0}, +{0x3a07,0x3af7,16,2, 12,Z3A_ssss_0111_imm16, "%R %#w1,%rb2", 0}, +{0x3a08,0x3af8,16,2, 21,Z3A_ssss_1000_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3a09,0x3af9,16,2, 21,Z3A_ssss_1001_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3a0a,0x3afa,16,2, 21,Z3A_ssss_1010_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3a0b,0x3afb,16,2, 21,Z3A_ssss_1011_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3b00,0x3bf0,16,2, 21,Z3B_ssss_0000_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3b01,0x3bf1,16,2, 21,Z3B_ssss_0001_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3b02,0x3bf2,16,2, 21,Z3B_ssss_0010_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3b03,0x3bf3,16,2, 21,Z3B_ssss_0011_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3b04,0x3bf4,16,2, 12,Z3B_dddd_0100_imm16, "%R %rw2,%#w1", 0}, +{0x3b05,0x3bf5,16,2, 12,Z3B_dddd_0101_imm16, "%R %rw2,%#w1", 0}, +{0x3b06,0x3bf6,16,2, 12,Z3B_ssss_0110_imm16, "%R %#w1,%rw2", 0}, +{0x3b07,0x3bf7,16,2, 12,Z3B_ssss_0111_imm16, "%R %#w1,%rw2", 0}, +{0x3b08,0x3bf8,16,2, 21,Z3B_ssss_1000_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3b09,0x3bf9,16,2, 21,Z3B_ssss_1001_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rw5", 0}, +{0x3b0a,0x3bfa,16,2, 21,Z3B_ssss_1010_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rb5", 0}, +{0x3b0b,0x3bfb,16,2, 21,Z3B_ssss_1011_0000_aaaa_dddd_x000, "%R @%rw6,@%rw2,%rb5", 0}, +{0x3c00,0x3cff, 1,1, 10,Z3C_ssss_dddd, "inb %rb3,@%rw2", 0}, +{0x3d00,0x3dff, 1,1, 10,Z3D_ssss_dddd, "in %rw3,@%rw2", 0}, +{0x3e00,0x3eff, 1,1, 12,Z3E_dddd_ssss, "outb @%rw2,%rb3", 0}, +{0x3f00,0x3fff, 1,1, 12,Z3F_dddd_ssss, "out @%rw2,%rw3", 0}, +{0x4000,0x400f, 1,2, 9,Z40_0000_dddd_addr, "addb %rb3,%a1", 0}, +{0x4010,0x40ff, 1,2, 10,Z40_ssN0_dddd_addr, "addb %rb3,%a1(%rw2)", 0}, +{0x4100,0x410f, 1,2, 9,Z41_0000_dddd_addr, "add %rw3,%a1", 0}, +{0x4110,0x41ff, 1,2, 10,Z41_ssN0_dddd_addr, "add %rw3,%a1(%rw2)", 0}, +{0x4200,0x420f, 1,2, 9,Z42_0000_dddd_addr, "subb %rb3,%a1", 0}, +{0x4210,0x42ff, 1,2, 10,Z42_ssN0_dddd_addr, "subb %rb3,%a1(%rw2)", 0}, +{0x4300,0x430f, 1,2, 9,Z43_0000_dddd_addr, "sub %rw3,%a1", 0}, +{0x4310,0x43ff, 1,2, 10,Z43_ssN0_dddd_addr, "sub %rw3,%a1(%rw2)", 0}, +{0x4400,0x440f, 1,2, 9,Z44_0000_dddd_addr, "orb %rb3,%a1", 0}, +{0x4410,0x44ff, 1,2, 10,Z44_ssN0_dddd_addr, "orb %rb3,%a1(%rw2)", 0}, +{0x4500,0x450f, 1,2, 9,Z45_0000_dddd_addr, "or %rw3,%a1", 0}, +{0x4510,0x45ff, 1,2, 10,Z45_ssN0_dddd_addr, "or %rw3,%a1(%rw2)", 0}, +{0x4600,0x460f, 1,2, 9,Z46_0000_dddd_addr, "andb %rb3,%a1", 0}, +{0x4610,0x46ff, 1,2, 10,Z46_ssN0_dddd_addr, "andb %rb3,%a1(%rw2)", 0}, +{0x4700,0x470f, 1,2, 9,Z47_0000_dddd_addr, "and %rw3,%a1", 0}, +{0x4710,0x47ff, 1,2, 10,Z47_ssN0_dddd_addr, "and %rw3,%a1(%rw2)", 0}, +{0x4800,0x480f, 1,2, 9,Z48_0000_dddd_addr, "xorb %rb3,%a1", 0}, +{0x4810,0x48ff, 1,2, 10,Z48_ssN0_dddd_addr, "xorb %rb3,%a1(%rw2)", 0}, +{0x4900,0x490f, 1,2, 9,Z49_0000_dddd_addr, "xor %rw3,%a1", 0}, +{0x4910,0x49ff, 1,2, 10,Z49_ssN0_dddd_addr, "xor %rw3,%a1(%rw2)", 0}, +{0x4a00,0x4a0f, 1,2, 9,Z4A_0000_dddd_addr, "cpb %rb3,%a1", 0}, +{0x4a10,0x4aff, 1,2, 10,Z4A_ssN0_dddd_addr, "cpb %rb3,%a1(%rw2)", 0}, +{0x4b00,0x4b0f, 1,2, 9,Z4B_0000_dddd_addr, "cp %rw3,%a1", 0}, +{0x4b10,0x4bff, 1,2, 10,Z4B_ssN0_dddd_addr, "cp %rw3,%a1(%rw2)", 0}, +{0x4c00,0x4c00, 1,2, 15,Z4C_0000_0000_addr, "comb %a1", 0}, +{0x4c01,0x4c01, 1,3, 14,Z4C_0000_0001_addr_imm8, "cpb %a1,%#b3", 0}, +{0x4c02,0x4c02, 1,2, 15,Z4C_0000_0010_addr, "negb %a1", 0}, +{0x4c04,0x4c04, 1,2, 11,Z4C_0000_0100_addr, "testb %a1", 0}, +{0x4c05,0x4c05, 1,3, 14,Z4C_0000_0101_addr_imm8, "ldb %a1,%#b3", 0}, +{0x4c06,0x4c06, 1,2, 14,Z4C_0000_0110_addr, "tsetb %a1", 0}, +{0x4c08,0x4c08, 1,2, 11,Z4C_0000_1000_addr, "clrb %a1", 0}, +{0x4c10,0x4cf0,16,2, 16,Z4C_ddN0_0000_addr, "comb %a1(%rw2)", 0}, +{0x4c11,0x4cf1,16,3, 15,Z4C_ddN0_0001_addr_imm8, "cpb %a1(%rw2),%#b3", 0}, +{0x4c12,0x4cf2,16,2, 16,Z4C_ddN0_0010_addr, "negb %a1(%rw2)", 0}, +{0x4c14,0x4cf4,16,2, 12,Z4C_ddN0_0100_addr, "testb %a1(%rw2)", 0}, +{0x4c15,0x4cf5,16,3, 15,Z4C_ddN0_0101_addr_imm8, "ldb %a1(%rw2),%#b3", 0}, +{0x4c16,0x4cf6,16,2, 15,Z4C_ddN0_0110_addr, "tsetb %a1(%rw2)", 0}, +{0x4c18,0x4cf8,16,2, 12,Z4C_ddN0_1000_addr, "clrb %a1(%rw2)", 0}, +{0x4d00,0x4d00, 1,2, 15,Z4D_0000_0000_addr, "com %a1", 0}, +{0x4d01,0x4d01, 1,3, 14,Z4D_0000_0001_addr_imm16, "cp %a1,%#w2", 0}, +{0x4d02,0x4d02, 1,2, 15,Z4D_0000_0010_addr, "neg %a1", 0}, +{0x4d04,0x4d04, 1,2, 11,Z4D_0000_0100_addr, "test %a1", 0}, +{0x4d05,0x4d05, 1,3, 14,Z4D_0000_0101_addr_imm16, "ld %a1,%#w2", 0}, +{0x4d06,0x4d06, 1,2, 14,Z4D_0000_0110_addr, "tset %a1", 0}, +{0x4d08,0x4d08, 1,2, 11,Z4D_0000_1000_addr, "clr %a1", 0}, +{0x4d10,0x4df0,16,2, 16,Z4D_ddN0_0000_addr, "com %a1(%rw2)", 0}, +{0x4d11,0x4df1,16,3, 15,Z4D_ddN0_0001_addr_imm16, "cp %a1(%rw2),%#w2", 0}, +{0x4d12,0x4df2,16,2, 16,Z4D_ddN0_0010_addr, "neg %a1(%rw2)", 0}, +{0x4d14,0x4df4,16,2, 12,Z4D_ddN0_0100_addr, "test %a1(%rw2)", 0}, +{0x4d15,0x4df5,16,3, 15,Z4D_ddN0_0101_addr_imm16, "ld %a1(%rw2),%#w2", 0}, +{0x4d16,0x4df6,16,2, 15,Z4D_ddN0_0110_addr, "tset %a1(%rw2)", 0}, +{0x4d18,0x4df8,16,2, 12,Z4D_ddN0_1000_addr, "clr %a1(%rw2)", 0}, +{0x4e11,0x4ef0,16,2, 12,Z4E_ddN0_ssN0_addr, "ldb %a1(%rw2),%rb3", 0}, +{0x5000,0x500f, 1,2, 15,Z50_0000_dddd_addr, "cpl %rl3,%a1", 0}, +{0x5010,0x50ff, 1,2, 16,Z50_ssN0_dddd_addr, "cpl %rl3,%a1(%rw2)", 0}, +{0x5110,0x51f0,16,2, 21,Z51_ddN0_0000_addr, "pushl @%rw2,%a1", 0}, +{0x5111,0x51f1,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5112,0x51f2,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5113,0x51f3,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5114,0x51f4,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5115,0x51f5,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5116,0x51f6,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5117,0x51f7,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5118,0x51f8,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5119,0x51f9,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x511a,0x51fa,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x511b,0x51fb,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x511c,0x51fc,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x511d,0x51fd,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x511e,0x51fe,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x511f,0x51ff,16,2, 21,Z51_ddN0_ssN0_addr, "pushl @%rw2,%a1(%rw3)", 0}, +{0x5200,0x520f, 1,2, 15,Z52_0000_dddd_addr, "subl %rl3,%a1", 0}, +{0x5210,0x52ff, 1,2, 16,Z52_ssN0_dddd_addr, "subl %rl3,%a1(%rw2)", 0}, +{0x5310,0x53f0,16,2, 14,Z53_ddN0_0000_addr, "push @%rw2,%a1", 0}, +{0x5311,0x53f1,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5312,0x53f2,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5313,0x53f3,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5314,0x53f4,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5315,0x53f5,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5316,0x53f6,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5317,0x53f7,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5318,0x53f8,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5319,0x53f9,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x531a,0x53fa,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x531b,0x53fb,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x531c,0x53fc,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x531d,0x53fd,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x531e,0x53fe,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x531f,0x53ff,16,2, 14,Z53_ddN0_ssN0_addr, "push @%rw2,%a1(%rw3)", 0}, +{0x5400,0x540f, 1,2, 12,Z54_0000_dddd_addr, "ldl %rl3,%a1", 0}, +{0x5410,0x54ff, 1,2, 13,Z54_ssN0_dddd_addr, "ldl %rl3,%a1(%rw2)", 0}, +{0x5510,0x55f0,16,2, 23,Z55_ssN0_0000_addr, "popl %a1,@%rw2", 0}, +{0x5511,0x55f1,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5512,0x55f2,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5513,0x55f3,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5514,0x55f4,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5515,0x55f5,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5516,0x55f6,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5517,0x55f7,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5518,0x55f8,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5519,0x55f9,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x551a,0x55fa,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x551b,0x55fb,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x551c,0x55fc,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x551d,0x55fd,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x551e,0x55fe,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x551f,0x55ff,16,2, 23,Z55_ssN0_ddN0_addr, "popl %a1(%rw3),@%rw2", 0}, +{0x5600,0x560f, 1,2, 15,Z56_0000_dddd_addr, "addl %rl3,%a1", 0}, +{0x5610,0x56ff, 1,2, 16,Z56_ssN0_dddd_addr, "addl %rl3,%a1(%rw2)", 0}, +{0x5710,0x57f0,16,2, 16,Z57_ssN0_0000_addr, "pop %a1,@%rw2", 0}, +{0x5711,0x57f1,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5712,0x57f2,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5713,0x57f3,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5714,0x57f4,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5715,0x57f5,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5716,0x57f6,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5717,0x57f7,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5718,0x57f8,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5719,0x57f9,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x571a,0x57fa,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x571b,0x57fb,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x571c,0x57fc,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x571d,0x57fd,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x571e,0x57fe,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x571f,0x57ff,16,2, 16,Z57_ssN0_ddN0_addr, "pop %a1(%rw3),@%rw2", 0}, +{0x5800,0x580f, 1,2,283,Z58_0000_dddd_addr, "multl %rq3,%a1", 0}, +{0x5810,0x58ff, 1,2,284,Z58_ssN0_dddd_addr, "multl %rq3,%a1(%rw2)", 0}, +{0x5900,0x590f, 1,2, 71,Z59_0000_dddd_addr, "mult %rl3,%a1", 0}, +{0x5910,0x59ff, 1,2, 72,Z59_ssN0_dddd_addr, "mult %rl3,%a1(%rw2)", 0}, +{0x5a00,0x5a0f, 1,2,745,Z5A_0000_dddd_addr, "divl %rq3,%a1", 0}, +{0x5a10,0x5aff, 1,2,746,Z5A_ssN0_dddd_addr, "divl %rq3,%a1(%rw2)", 0}, +{0x5b00,0x5b0f, 1,2,108,Z5B_0000_dddd_addr, "div %rl3,%a1", 0}, +{0x5b10,0x5bff, 1,2,109,Z5B_ssN0_dddd_addr, "div %rl3,%a1(%rw2)", 0}, +{0x5c01,0x5c01, 1,3, 14,Z5C_0000_0001_0000_dddd_0000_nmin1_addr, "ldm %rw5,%a2,#%n", 0}, +{0x5c08,0x5c08, 1,2, 16,Z5C_0000_1000_addr, "testl %a1", 0}, +{0x5c09,0x5c09, 1,3, 14,Z5C_0000_1001_0000_ssss_0000_nmin1_addr, "ldm %a2,%rw5,#%n", 0}, +{0x5c11,0x5cf1,16,3, 15,Z5C_ssN0_0001_0000_dddd_0000_nmin1_addr, "ldm %rw5,%a2(%rw2),#%n", 0}, +{0x5c18,0x5cf8,16,2, 17,Z5C_ddN0_1000_addr, "testl %a1(%rw2)", 0}, +{0x5c19,0x5cf9,16,3, 15,Z5C_ddN0_1001_0000_ssN0_0000_nmin1_addr, "ldm %a2(%rw2),%rw5,#%n", 0}, +{0x5d00,0x5d0f, 1,2, 15,Z5D_0000_ssss_addr, "ldl %a1,%rl3", 0}, +{0x5d10,0x5dff, 1,2, 14,Z5D_ddN0_ssss_addr, "ldl %a1(%rw2),%rl3", 0}, +{0x5e00,0x5e0f, 1,2, 7,Z5E_0000_cccc_addr, "jp %c3,%a1", 0}, +{0x5e10,0x5eff, 1,2, 8,Z5E_ddN0_cccc_addr, "jp %c3,%a1(%rw2)", 0}, +{0x5f00,0x5f00, 1,2, 12,Z5F_0000_0000_addr, "call %a1", DASMFLAG_STEP_OVER}, +{0x5f10,0x5ff0,16,2, 13,Z5F_ddN0_0000_addr, "call %a1(%rw2)", DASMFLAG_STEP_OVER}, +{0x6000,0x600f, 1,2, 9,Z60_0000_dddd_addr, "ldb %rb3,%a1", 0}, +{0x6010,0x60ff, 1,2, 10,Z60_ssN0_dddd_addr, "ldb %rb3,%a1(%rw2)", 0}, +{0x6100,0x610f, 1,2, 9,Z61_0000_dddd_addr, "ld %rw3,%a1", 0}, +{0x6110,0x61ff, 1,2, 10,Z61_ssN0_dddd_addr, "ld %rw3,%a1(%rw2)", 0}, +{0x6200,0x620f, 1,2, 13,Z62_0000_imm4_addr, "resb %a1,%3", 0}, +{0x6210,0x62ff, 1,2, 14,Z62_ddN0_imm4_addr, "resb %a1(%rw2),%3", 0}, +{0x6300,0x630f, 1,2, 13,Z63_0000_imm4_addr, "res %a1,%3", 0}, +{0x6310,0x63ff, 1,2, 14,Z63_ddN0_imm4_addr, "res %a1(%rw2),%3", 0}, +{0x6400,0x640f, 1,2, 13,Z64_0000_imm4_addr, "setb %a1,%3", 0}, +{0x6410,0x64ff, 1,2, 14,Z64_ddN0_imm4_addr, "setb %a1(%rw2),%3", 0}, +{0x6500,0x650f, 1,2, 13,Z65_0000_imm4_addr, "set %a1,%3", 0}, +{0x6510,0x65ff, 1,2, 14,Z65_ddN0_imm4_addr, "set %a1(%rw2),%3", 0}, +{0x6600,0x660f, 1,2, 10,Z66_0000_imm4_addr, "bitb %a1,%3", 0}, +{0x6610,0x66ff, 1,2, 11,Z66_ddN0_imm4_addr, "bitb %a1(%rw2),%3", 0}, +{0x6700,0x670f, 1,2, 10,Z67_0000_imm4_addr, "bit %a1,%3", 0}, +{0x6710,0x67ff, 1,2, 11,Z67_ddN0_imm4_addr, "bit %a1(%rw2),%3", 0}, +{0x6800,0x680f, 1,2, 13,Z68_0000_imm4m1_addr, "incb %a1,%+3", 0}, +{0x6810,0x68ff, 1,2, 14,Z68_ddN0_imm4m1_addr, "incb %a1(%rw2),%+3", 0}, +{0x6900,0x690f, 1,2, 13,Z69_0000_imm4m1_addr, "inc %a1,%+3", 0}, +{0x6910,0x69ff, 1,2, 14,Z69_ddN0_imm4m1_addr, "inc %a1(%rw2),%+3", 0}, +{0x6a00,0x6a0f, 1,2, 13,Z6A_0000_imm4m1_addr, "decb %a1,%+3", 0}, +{0x6a10,0x6aff, 1,2, 14,Z6A_ddN0_imm4m1_addr, "decb %a1(%rw2),%+3", 0}, +{0x6b00,0x6b0f, 1,2, 13,Z6B_0000_imm4m1_addr, "dec %a1,%+3", 0}, +{0x6b10,0x6bff, 1,2, 14,Z6B_ddN0_imm4m1_addr, "dec %a1(%rw2),%+3", 0}, +{0x6c00,0x6c0f, 1,2, 15,Z6C_0000_dddd_addr, "exb %rb3,%a1", 0}, +{0x6c10,0x6cff, 1,2, 16,Z6C_ssN0_dddd_addr, "exb %rb3,%a1(%rw2)", 0}, +{0x6d00,0x6d0f, 1,2, 15,Z6D_0000_dddd_addr, "ex %rw3,%a1", 0}, +{0x6d10,0x6dff, 1,2, 16,Z6D_ssN0_dddd_addr, "ex %rw3,%a1(%rw2)", 0}, +{0x6e00,0x6e0f, 1,2, 11,Z6E_0000_ssss_addr, "ldb %a1,%rb3", 0}, +{0x6e10,0x6eff, 1,2, 11,Z6E_ddN0_ssss_addr, "ldb %a1(%rw2),%rb3", 0}, +{0x6f00,0x6f0f, 1,2, 11,Z6F_0000_ssss_addr, "ld %a1,%rw3", 0}, +{0x6f10,0x6fff, 1,2, 12,Z6F_ddN0_ssss_addr, "ld %a1(%rw2),%rw3", 0}, +{0x7010,0x70ff, 1,2, 14,Z70_ssN0_dddd_0000_xxxx_0000_0000, "ldb %rb3,%rw2(%rw5)", 0}, +{0x7110,0x71ff, 1,2, 14,Z71_ssN0_dddd_0000_xxxx_0000_0000, "ld %rw3,%rw2(%rw5)", 0}, +{0x7210,0x72ff, 1,2, 14,Z72_ddN0_ssss_0000_xxxx_0000_0000, "ldb %rw2(%rw5),%rb3", 0}, +{0x7310,0x73ff, 1,2, 14,Z73_ddN0_ssss_0000_xxxx_0000_0000, "ld %rw2(%rw5),%rw3", 0}, +{0x7410,0x74ff, 1,2, 15,Z74_ssN0_dddd_0000_xxxx_0000_0000, "lda p%rw3,%rw2(%rw5)", 0}, +{0x7510,0x75ff, 1,2, 17,Z75_ssN0_dddd_0000_xxxx_0000_0000, "ldl %rl3,%rw2(%rw5)", 0}, +{0x7600,0x760f, 1,2, 12,Z76_0000_dddd_addr, "lda p%rw3,%a1", 0}, +{0x7610,0x76ff, 1,2, 13,Z76_ssN0_dddd_addr, "lda p%rw3,%a1(%rw2)", 0}, +{0x7710,0x77ff, 1,2, 17,Z77_ddN0_ssss_0000_xxxx_0000_0000, "ldl %rw2(%rw5),%rl3", 0}, +{0x7800,0x78ff, 1,1, 10,Z78_imm8, "rsvd78", 0}, +{0x7900,0x7900, 1,2, 16,Z79_0000_0000_addr, "ldps %a1", 0}, +{0x7910,0x79f0,16,2, 17,Z79_ssN0_0000_addr, "ldps %a1(%rw2)", 0}, +{0x7a00,0x7a00, 1,1, 8,Z7A_0000_0000, "halt", DASMFLAG_STEP_OVER}, +{0x7b00,0x7b00, 1,1, 13,Z7B_0000_0000, "iret", DASMFLAG_STEP_OUT}, +{0x7b08,0x7b08, 1,1, 5,Z7B_0000_1000, "mset", 0}, +{0x7b09,0x7b09, 1,1, 5,Z7B_0000_1001, "mres", 0}, +{0x7b0a,0x7b0a, 1,1, 7,Z7B_0000_1010, "mbit", 0}, +{0x7b0d,0x7bfd,16,1, 12,Z7B_dddd_1101, "mreq %rw2", 0}, +{0x7c00,0x7c03, 1,1, 7,Z7C_0000_00ii, "di %i3", 0}, +{0x7c04,0x7c07, 1,1, 7,Z7C_0000_01ii, "ei %i3", 0}, +{0x7d00,0x7df0,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,ctrl0", 0}, +{0x7d01,0x7df1,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,ctrl1", 0}, +{0x7d02,0x7df2,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,fcw", 0}, +{0x7d03,0x7df3,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,refresh", 0}, +{0x7d04,0x7df4,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,psapseg", 0}, +{0x7d05,0x7df5,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,psapoff", 0}, +{0x7d06,0x7df6,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,nspseg", 0}, +{0x7d07,0x7df7,16,1, 7,Z7D_dddd_0ccc, "ldctl %rw2,nspoff", 0}, +{0x7d08,0x7df8,16,1, 7,Z7D_ssss_1ccc, "ldctl ctrl0,%rw2", 0}, +{0x7d09,0x7df9,16,1, 7,Z7D_ssss_1ccc, "ldctl ctrl1,%rw2", 0}, +{0x7d0a,0x7dfa,16,1, 7,Z7D_ssss_1ccc, "ldctl fcw,%rw2", 0}, +{0x7d0b,0x7dfb,16,1, 7,Z7D_ssss_1ccc, "ldctl refresh,%rw2", 0}, +{0x7d0c,0x7dfc,16,1, 7,Z7D_ssss_1ccc, "ldctl psapseg,%rw2", 0}, +{0x7d0d,0x7dfd,16,1, 7,Z7D_ssss_1ccc, "ldctl psapoff,%rw2", 0}, +{0x7d0e,0x7dfe,16,1, 7,Z7D_ssss_1ccc, "ldctl nspseg,%rw2", 0}, +{0x7d0f,0x7dff,16,1, 7,Z7D_ssss_1ccc, "ldctl nspoff,%rw2", 0}, +{0x7e00,0x7eff, 1,1, 10,Z7E_imm8, "rsvd7e %#b1", 0}, +{0x7f00,0x7fff, 1,1, 33,Z7F_imm8, "sc %#b1", 0}, +{0x8000,0x80ff, 1,1, 4,Z80_ssss_dddd, "addb %rb3,%rb2", 0}, +{0x8100,0x81ff, 1,1, 4,Z81_ssss_dddd, "add %rw3,%rw2", 0}, +{0x8200,0x82ff, 1,1, 4,Z82_ssss_dddd, "subb %rb3,%rb2", 0}, +{0x8300,0x83ff, 1,1, 4,Z83_ssss_dddd, "sub %rw3,%rw2", 0}, +{0x8400,0x84ff, 1,1, 4,Z84_ssss_dddd, "orb %rb3,%rb2", 0}, +{0x8500,0x85ff, 1,1, 4,Z85_ssss_dddd, "or %rw3,%rw2", 0}, +{0x8600,0x86ff, 1,1, 4,Z86_ssss_dddd, "andb %rb3,%rb2", 0}, +{0x8700,0x87ff, 1,1, 4,Z87_ssss_dddd, "and %rw3,%rw2", 0}, +{0x8800,0x88ff, 1,1, 4,Z88_ssss_dddd, "xorb %rb3,%rb2", 0}, +{0x8900,0x89ff, 1,1, 4,Z89_ssss_dddd, "xor %rw3,%rw2", 0}, +{0x8a00,0x8aff, 1,1, 4,Z8A_ssss_dddd, "cpb %rb3,%rb2", 0}, +{0x8b00,0x8bff, 1,1, 4,Z8B_ssss_dddd, "cp %rw3,%rw2", 0}, +{0x8c00,0x8cf0,16,1, 7,Z8C_dddd_0000, "comb %rb2", 0}, +{0x8c02,0x8cf2,16,1, 7,Z8C_dddd_0010, "negb %rb2", 0}, +{0x8c04,0x8cf4,16,1, 7,Z8C_dddd_0100, "testb %rb2", 0}, +{0x8c06,0x8cf6,16,1, 7,Z8C_dddd_0110, "tsetb %rb2", 0}, +{0x8c01,0x8cf1,16,1, 7,Z8C_dddd_0001, "ldctlb %rb2,flags", 0}, +{0x8c08,0x8cf8,16,1, 7,Z8C_dddd_1000, "clrb %rb2", 0}, +{0x8c09,0x8cf9,16,1, 7,Z8C_dddd_1001, "ldctlb flags,%rb2", 0}, +{0x8d00,0x8df0,16,1, 7,Z8D_dddd_0000, "com %rw2", 0}, +{0x8d01,0x8df1,16,1, 7,Z8D_imm4_0001, "setflg %f2", 0}, +{0x8d02,0x8df2,16,1, 7,Z8D_dddd_0010, "neg %rw2", 0}, +{0x8d03,0x8df3,16,1, 7,Z8D_imm4_0011, "resflg %f2", 0}, +{0x8d04,0x8df4,16,1, 7,Z8D_dddd_0100, "test %rw2", 0}, +{0x8d05,0x8df5,16,1, 7,Z8D_imm4_0101, "comflg %f2", 0}, +{0x8d06,0x8df6,16,1, 7,Z8D_dddd_0110, "tset %rw2", 0}, +{0x8d07,0x8d07, 1,1, 7,Z8D_0000_0111, "nop", 0}, +{0x8d08,0x8df8,16,1, 7,Z8D_dddd_1000, "clr %rw2", 0}, +{0x8e00,0x8eff, 1,1, 10,Z8E_imm8, "ext8e %#b1", 0}, +{0x8f00,0x8fff, 1,1, 10,Z8F_imm8, "ext8f %#b1", 0}, +{0x9000,0x90ff, 1,1, 8,Z90_ssss_dddd, "cpl %rl3,%rl2", 0}, +{0x9110,0x91ff, 1,1, 12,Z91_ddN0_ssss, "pushl @%rw2,%rl3", 0}, +{0x9200,0x92ff, 1,1, 8,Z92_ssss_dddd, "subl %rl3,%rl2", 0}, +{0x9310,0x93ff, 1,1, 9,Z93_ddN0_ssss, "push @%rw2,%rw3", 0}, +{0x9400,0x94ff, 1,1, 5,Z94_ssss_dddd, "ldl %rl3,%rl2", 0}, +{0x9510,0x95ff, 1,1, 12,Z95_ssN0_dddd, "popl %rl3,@%rw2", 0}, +{0x9600,0x96ff, 1,1, 8,Z96_ssss_dddd, "addl %rl3,%rl2", 0}, +{0x9710,0x97ff, 1,1, 8,Z97_ssN0_dddd, "pop %rw3,@%rw2", 0}, +{0x9800,0x98ff, 1,1,282,Z98_ssss_dddd, "multl %rq3,%rl2", 0}, +{0x9900,0x99ff, 1,1, 70,Z99_ssss_dddd, "mult %rl3,%rw2", 0}, +{0x9a00,0x9aff, 1,1,744,Z9A_ssss_dddd, "divl %rq3,%rl2", 0}, +{0x9b00,0x9bff, 1,1,107,Z9B_ssss_dddd, "div %rl3,%rw2", 0}, +{0x9c08,0x9cf8,16,1, 13,Z9C_dddd_1000, "testl %rl2", 0}, +{0x9d00,0x9dff, 1,1, 10,Z9D_imm8, "rsvd9d", 0}, +{0x9e00,0x9e0f, 1,1, 10,Z9E_0000_cccc, "ret %c3", DASMFLAG_STEP_OUT}, +{0x9f00,0x9fff, 1,1, 10,Z9F_imm8, "rsvd9f", 0}, +{0xa000,0xa0ff, 1,1, 3,ZA0_ssss_dddd, "ldb %rb3,%rb2", 0}, +{0xa100,0xa1ff, 1,1, 3,ZA1_ssss_dddd, "ld %rw3,%rw2", 0}, +{0xa200,0xa2ff, 1,1, 4,ZA2_dddd_imm4, "resb %rb2,%3", 0}, +{0xa300,0xa3ff, 1,1, 4,ZA3_dddd_imm4, "res %rw2,%3", 0}, +{0xa400,0xa4ff, 1,1, 4,ZA4_dddd_imm4, "setb %rb2,%3", 0}, +{0xa500,0xa5ff, 1,1, 4,ZA5_dddd_imm4, "set %rw2,%3", 0}, +{0xa600,0xa6ff, 1,1, 4,ZA6_dddd_imm4, "bitb %rb2,%3", 0}, +{0xa700,0xa7ff, 1,1, 4,ZA7_dddd_imm4, "bit %rw2,%3", 0}, +{0xa800,0xa8ff, 1,1, 4,ZA8_dddd_imm4m1, "incb %rb2,%+3", 0}, +{0xa900,0xa9ff, 1,1, 4,ZA9_dddd_imm4m1, "inc %rw2,%+3", 0}, +{0xaa00,0xaaff, 1,1, 4,ZAA_dddd_imm4m1, "decb %rb2,%+3", 0}, +{0xab00,0xabff, 1,1, 4,ZAB_dddd_imm4m1, "dec %rw2,%+3", 0}, +{0xac00,0xacff, 1,1, 6,ZAC_ssss_dddd, "exb %rb3,%rb2", 0}, +{0xad00,0xadff, 1,1, 6,ZAD_ssss_dddd, "ex %rw3,%rw2", 0}, +{0xae00,0xaeff, 1,1, 5,ZAE_dddd_cccc, "tccb %c3,%rb2", 0}, +{0xaf00,0xafff, 1,1, 5,ZAF_dddd_cccc, "tcc %c3,%rw2", 0}, +{0xb000,0xb0f0,16,1, 5,ZB0_dddd_0000, "dab %rb2", 0}, +{0xb100,0xb1f0,16,1, 11,ZB1_dddd_0000, "extsb %rw2", 0}, +{0xb107,0xb1f7,16,1, 11,ZB1_dddd_0111, "extsl %rq2", 0}, +{0xb10a,0xb1fa,16,1, 11,ZB1_dddd_1010, "exts %rl2", 0}, +{0xb200,0xb2f0,16,1, 6,ZB2_dddd_00I0, "rlb %rb2,%?3", 0}, +{0xb201,0xb2f1,16,2, 13,ZB2_dddd_0001_imm8, "s%*lb %rb2,%$3", 0}, +{0xb202,0xb2f2,16,1, 6,ZB2_dddd_00I0, "rlb %rb2,%?3", 0}, +{0xb203,0xb2f3,16,2, 15,ZB2_dddd_0011_0000_ssss_0000_0000, "sdlb %rb2,%rw5", 0}, +{0xb204,0xb2f4,16,1, 6,ZB2_dddd_01I0, "rrb %rb2,%?3", 0}, +{0xb206,0xb2f6,16,1, 6,ZB2_dddd_01I0, "rrb %rb2,%?3", 0}, +{0xb208,0xb2f8,16,1, 9,ZB2_dddd_10I0, "rlcb %rb2,%?3", 0}, +{0xb209,0xb2f9,16,2, 13,ZB2_dddd_1001_imm8, "s%*ab %rb2,%$3", 0}, +{0xb20a,0xb2fa,16,1, 9,ZB2_dddd_10I0, "rlcb %rb2,%?3", 0}, +{0xb20b,0xb2fb,16,2, 15,ZB2_dddd_1011_0000_ssss_0000_0000, "sdab %rb2,%rw5", 0}, +{0xb20c,0xb2fc,16,1, 9,ZB2_dddd_11I0, "rrcb %rb2,%?3", 0}, +{0xb20e,0xb2fe,16,1, 9,ZB2_dddd_11I0, "rrcb %rb2,%?3", 0}, +{0xb300,0xb3f0,16,1, 6,ZB3_dddd_00I0, "rl %rw2,%?3", 0}, +{0xb301,0xb3f1,16,2, 13,ZB3_dddd_0001_imm8, "s%*l %rw2,%$3", 0}, +{0xb302,0xb3f2,16,1, 6,ZB3_dddd_00I0, "rl %rw2,%?3", 0}, +{0xb303,0xb3f3,16,2, 15,ZB3_dddd_0011_0000_ssss_0000_0000, "sdl %rw2,%rw5", 0}, +{0xb304,0xb3f4,16,1, 6,ZB3_dddd_01I0, "rr %rw2,%?3", 0}, +{0xb305,0xb3f5,16,2, 13,ZB3_dddd_0101_imm8, "s%*ll %rl2,%$3", 0}, +{0xb306,0xb3f6,16,1, 6,ZB3_dddd_01I0, "rr %rw2,%?3", 0}, +{0xb307,0xb3f7,16,2, 15,ZB3_dddd_0111_0000_ssss_0000_0000, "sdll %rl2,%rw5", 0}, +{0xb308,0xb3f8,16,1, 6,ZB3_dddd_10I0, "rlc %rw2,%?3", 0}, +{0xb309,0xb3f9,16,2, 13,ZB3_dddd_1001_imm8, "s%*a %rw2,%$3", 0}, +{0xb30a,0xb3fa,16,1, 6,ZB3_dddd_10I0, "rlc %rw2,%?3", 0}, +{0xb30b,0xb3fb,16,2, 15,ZB3_dddd_1011_0000_ssss_0000_0000, "sda %rw2,%rw5", 0}, +{0xb30c,0xb3fc,16,1, 6,ZB3_dddd_11I0, "rrc %rw2,%?3", 0}, +{0xb30d,0xb3fd,16,2, 13,ZB3_dddd_1101_imm8, "s%*al %rl2,%$3", 0}, +{0xb30e,0xb3fe,16,1, 6,ZB3_dddd_11I0, "rrc %rw2,%?3", 0}, +{0xb30f,0xb3ff,16,2, 15,ZB3_dddd_1111_0000_ssss_0000_0000, "sdal %rl2,%rw5", 0}, +{0xb400,0xb4ff, 1,1, 5,ZB4_ssss_dddd, "adcb %rb3,%rb2", 0}, +{0xb500,0xb5ff, 1,1, 5,ZB5_ssss_dddd, "adc %rw3,%rw2", 0}, +{0xb600,0xb6ff, 1,1, 5,ZB6_ssss_dddd, "sbcb %rb3,%rb2", 0}, +{0xb700,0xb7ff, 1,1, 5,ZB7_ssss_dddd, "sbc %rw3,%rw2", 0}, +{0xb810,0xb8f0,16,2, 25,ZB8_ddN0_0000_0000_rrrr_ssN0_0000, "trib @%rw2,@%rw6,%rb5", 0}, +{0xb812,0xb8f2,16,2, 25,ZB8_ddN0_0010_0000_rrrr_ssN0_0000, "trtib @%rw2,@%rw6,%rb5", 0}, +{0xb814,0xb8f4,16,2, 25,ZB8_ddN0_0100_0000_rrrr_ssN0_0000, "trirb @%rw2,@%rw6,%rb5", 0}, +{0xb816,0xb8f6,16,2, 25,ZB8_ddN0_0110_0000_rrrr_ssN0_1110, "trtirb @%rw2,@%rw6,%rb5", 0}, +{0xb818,0xb8f8,16,2, 25,ZB8_ddN0_1000_0000_rrrr_ssN0_0000, "trdb @%rw2,@%rw6,%rb5", 0}, +{0xb81a,0xb8fa,16,2, 25,ZB8_ddN0_1010_0000_rrrr_ssN0_0000, "trtrb @%rw2,@%rw6,%rb5", 0}, +{0xb81c,0xb8fc,16,2, 25,ZB8_ddN0_1100_0000_rrrr_ssN0_0000, "trdrb @%rw2,@%rw6,%rb5", 0}, +{0xb81e,0xb8fe,16,2, 25,ZB8_ddN0_1110_0000_rrrr_ssN0_1110, "trtdrb @%rw2,@%rw6,%rb5", 0}, +{0xb900,0xb9ff,16,1, 10,ZB9_imm8, "rsvdb9", 0}, +{0xba10,0xbaf0,16,2, 11,ZBA_ssN0_0000_0000_rrrr_dddd_cccc, "cpib %rb6,@%rw2,%rw5,%c7", 0}, +{0xba11,0xbaf1,16,2, 11,ZBA_ssN0_0001_0000_rrrr_ddN0_x000, "ldirb @%rw6,@%rw2,%rw5", DASMFLAG_STEP_OVER}, +{0xba12,0xbaf2,16,2, 11,ZBA_ssN0_0010_0000_rrrr_ddN0_cccc, "cpsib @%rw6,@%rw2,%rw5,%c7", 0}, +{0xba14,0xbaf4,16,2, 11,ZBA_ssN0_0100_0000_rrrr_dddd_cccc, "cpirb %rb6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, +{0xba16,0xbaf6,16,2, 11,ZBA_ssN0_0110_0000_rrrr_ddN0_cccc, "cpsirb @%rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, +{0xba18,0xbaf8,16,2, 11,ZBA_ssN0_1000_0000_rrrr_dddd_cccc, "cpdb %rb6,@%rw2,%rw5,%c7", 0}, +{0xba19,0xbaf9,16,2, 11,ZBA_ssN0_1001_0000_rrrr_ddN0_x000, "lddrb @%rw2,@%rw6,%rw5", DASMFLAG_STEP_OVER}, +{0xba1a,0xbafa,16,2, 11,ZBA_ssN0_1010_0000_rrrr_ddN0_cccc, "cpsdb @%rw6,@%rw2,%rw5,%c7", 0}, +{0xba1c,0xbafc,16,2, 11,ZBA_ssN0_1100_0000_rrrr_dddd_cccc, "cpdrb %rb6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, +{0xba1e,0xbafe,16,2, 11,ZBA_ssN0_1110_0000_rrrr_ddN0_cccc, "cpsdrb @%rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, +{0xbb10,0xbbf0,16,2, 11,ZBB_ssN0_0000_0000_rrrr_dddd_cccc, "cpi %rw6,@%rw2,%rw5,%c7", 0}, +{0xbb11,0xbbf1,16,2, 11,ZBB_ssN0_0001_0000_rrrr_ddN0_x000, "ldir @%rw6,@%rw2,%rw5", DASMFLAG_STEP_OVER}, +{0xbb12,0xbbf2,16,2, 11,ZBB_ssN0_0010_0000_rrrr_ddN0_cccc, "cpsi @%rw6,@%rw2,%rw5,%c7", 0}, +{0xbb14,0xbbf4,16,2, 11,ZBB_ssN0_0100_0000_rrrr_dddd_cccc, "cpir %rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, +{0xbb16,0xbbf6,16,2, 11,ZBB_ssN0_0110_0000_rrrr_ddN0_cccc, "cpsir @%rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, +{0xbb18,0xbbf8,16,2, 11,ZBB_ssN0_1000_0000_rrrr_dddd_cccc, "cpd %rw6,@%rw2,%rw5,%c7", 0}, +{0xbb19,0xbbf9,16,2, 11,ZBB_ssN0_1001_0000_rrrr_ddN0_x000, "lddr @%rw2,@%rw6,%rw5", DASMFLAG_STEP_OVER}, +{0xbb1a,0xbbfa,16,2, 11,ZBB_ssN0_1010_0000_rrrr_ddN0_cccc, "cpsd @%rw6,@%rw2,%rw5,%c7", 0}, +{0xbb1c,0xbbfc,16,2, 11,ZBB_ssN0_1100_0000_rrrr_dddd_cccc, "cpdr %rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, +{0xbb1e,0xbbfe,16,2, 11,ZBB_ssN0_1110_0000_rrrr_ddN0_cccc, "cpsdr @%rw6,@%rw2,%rw5,%c7", DASMFLAG_STEP_OVER}, +{0xbc00,0xbcff, 1,1, 9,ZBC_aaaa_bbbb, "rrdb %rb3,%rb2", 0}, +{0xbd00,0xbdff, 1,1, 5,ZBD_dddd_imm4, "ldk %rw2,%3", 0}, +{0xbe00,0xbeff, 1,1, 9,ZBE_aaaa_bbbb, "rldb %rb3,%rb2", 0}, +{0xbf00,0xbfff, 1,1, 10,ZBF_imm8, "rsvdbf", 0}, +{0xc000,0xcfff, 1,1, 5,ZC_dddd_imm8, "ldb %rb1,%#b1", 0}, +{0xd000,0xdfff, 1,1, 10,ZD_dsp12, "calr %d2", DASMFLAG_STEP_OVER}, +{0xe000,0xefff, 1,1, 6,ZE_cccc_dsp8, "jr %c1,%d1", 0}, +{0xf000,0xf07f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf100,0xf17f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf200,0xf27f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf300,0xf37f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf400,0xf47f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf500,0xf57f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf600,0xf67f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf700,0xf77f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf800,0xf87f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf900,0xf97f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xfa00,0xfa7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xfb00,0xfb7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xfc00,0xfc7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xfd00,0xfd7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xfe00,0xfe7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xff00,0xff7f, 1,1, 11,ZF_dddd_0dsp7, "dbjnz %rb1,%d0", DASMFLAG_STEP_OVER}, +{0xf080,0xf0ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf180,0xf1ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf280,0xf2ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf380,0xf3ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf480,0xf4ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf580,0xf5ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf680,0xf6ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf780,0xf7ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf880,0xf8ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xf980,0xf9ff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xfa80,0xfaff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xfb80,0xfbff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xfc80,0xfcff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xfd80,0xfdff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xfe80,0xfeff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0xff80,0xffff, 1,1, 11,ZF_dddd_1dsp7, "djnz %rw1,%d0", DASMFLAG_STEP_OVER}, +{0, 0, 0,0, 0,NULL, NULL, 0} }; @@ -552,22 +552,22 @@ void z8000_init_tables(void) z8000_exec = global_alloc_array(Z8000_exec, 0x10000); /* set up the zero, sign, parity lookup table */ - for (i = 0; i < 256; i++) + for (i = 0; i < 256; i++) z8000_zsp[i] = ((i == 0) ? F_Z : 0) | - ((i & 128) ? F_S : 0) | - ((((i>>7)^(i>>6)^(i>>5)^(i>>4)^(i>>3)^(i>>2)^(i>>1)^i) & 1) ? F_PV : 0); + ((i & 128) ? F_S : 0) | + ((((i>>7)^(i>>6)^(i>>5)^(i>>4)^(i>>3)^(i>>2)^(i>>1)^i) & 1) ? F_PV : 0); - /* first set all 64K opcodes to invalid */ + /* first set all 64K opcodes to invalid */ for (i = 0; i < 0x10000; i++) { z8000_exec[i].opcode = zinvalid; z8000_exec[i].cycles = 4; - z8000_exec[i].size = 1; - z8000_exec[i].dasm = ".word %#w0"; + z8000_exec[i].size = 1; + z8000_exec[i].dasm = ".word %#w0"; z8000_exec[i].dasmflags = 0; } - /* now decompose the initialization table */ + /* now decompose the initialization table */ for (init = table; init->size; init++) { for (i = init->beg; i <= init->end; i += init->step) @@ -577,8 +577,8 @@ void z8000_init_tables(void) z8000_exec[i].opcode = init->opcode; z8000_exec[i].cycles = init->cycles; - z8000_exec[i].size = init->size; - z8000_exec[i].dasm = init->dasm; + z8000_exec[i].size = init->size; + z8000_exec[i].dasm = init->dasm; z8000_exec[i].dasmflags = init->dasmflags; } } @@ -589,4 +589,3 @@ void z8000_deinit_tables(void) global_free( z8000_exec ); z8000_exec = 0; } - |