diff options
author | Wilbert Pol <wilbert@jdg.info> | 2014-02-21 22:43:53 +0000 |
---|---|---|
committer | Wilbert Pol <wilbert@jdg.info> | 2014-02-21 22:43:53 +0000 |
commit | 9694b53c0aaf47fac3b634effb0a4509de02d22f (patch) | |
tree | 2028f246e193c1ad43013f01b0855eddef5c8e35 /src/emu/cpu/upd7810 | |
parent | 48bce760eef67f8f8c35a26e7c6eef7d2c8e336c (diff) |
upd7810.c: Modernized cpu core. [Wilbert Pol]
Diffstat (limited to 'src/emu/cpu/upd7810')
-rw-r--r-- | src/emu/cpu/upd7810/7810ops.c | 2521 | ||||
-rw-r--r-- | src/emu/cpu/upd7810/7810tbl.c | 12521 | ||||
-rw-r--r-- | src/emu/cpu/upd7810/upd7810.c | 2002 | ||||
-rw-r--r-- | src/emu/cpu/upd7810/upd7810.h | 1300 |
4 files changed, 9160 insertions, 9184 deletions
diff --git a/src/emu/cpu/upd7810/7810ops.c b/src/emu/cpu/upd7810/7810ops.c index 1e0efff8510..4db50203d68 100644 --- a/src/emu/cpu/upd7810/7810ops.c +++ b/src/emu/cpu/upd7810/7810ops.c @@ -7,20 +7,20 @@ * *****************************************************************************/ -static void illegal(upd7810_state *cpustate) +void upd7810_device::illegal() { - logerror("uPD7810 '%s': illegal opcode %02x at PC:%04x\n", cpustate->device->tag(), OP, PC); + logerror("uPD7810 '%s': illegal opcode %02x at PC:%04x\n", tag(), OP, PC); } -static void illegal2(upd7810_state *cpustate) +void upd7810_device::illegal2() { - logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", cpustate->device->tag(), OP, OP2, PC); + logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, OP2, PC); } /* prefix 48 */ /* 48 01: 0100 1000 0000 0001 */ -static void SLRC_A(upd7810_state *cpustate) +void upd7810_device::SLRC_A() { PSW = (PSW & ~CY) | (A & CY); A >>= 1; @@ -28,7 +28,7 @@ static void SLRC_A(upd7810_state *cpustate) } /* 48 02: 0100 1000 0000 0010 */ -static void SLRC_B(upd7810_state *cpustate) +void upd7810_device::SLRC_B() { PSW = (PSW & ~CY) | (B & CY); B >>= 1; @@ -36,7 +36,7 @@ static void SLRC_B(upd7810_state *cpustate) } /* 48 03: 0100 1000 0000 0011 */ -static void SLRC_C(upd7810_state *cpustate) +void upd7810_device::SLRC_C() { PSW = (PSW & ~CY) | (C & CY); C >>= 1; @@ -45,7 +45,7 @@ static void SLRC_C(upd7810_state *cpustate) /* 48 05: 0100 1000 0000 0101 */ -static void SLLC_A(upd7810_state *cpustate) +void upd7810_device::SLLC_A() { PSW = (PSW & ~CY) | ((A >> 7) & CY); A <<= 1; @@ -53,7 +53,7 @@ static void SLLC_A(upd7810_state *cpustate) } /* 48 06: 0100 1000 0000 0110 */ -static void SLLC_B(upd7810_state *cpustate) +void upd7810_device::SLLC_B() { PSW = (PSW & ~CY) | ((B >> 7) & CY); B <<= 1; @@ -61,7 +61,7 @@ static void SLLC_B(upd7810_state *cpustate) } /* 48 07: 0100 1000 0000 0111 */ -static void SLLC_C(upd7810_state *cpustate) +void upd7810_device::SLLC_C() { PSW = (PSW & ~CY) | ((C >> 7) & CY); C <<= 1; @@ -69,110 +69,110 @@ static void SLLC_C(upd7810_state *cpustate) } /* 48 08: 0100 1000 0000 1000 */ -static void SK_NV(upd7810_state *cpustate) +void upd7810_device::SK_NV() { /* 48 skip never */ } /* 48 0a: 0100 1000 0000 1010 */ -static void SK_CY(upd7810_state *cpustate) +void upd7810_device::SK_CY() { if (CY == (PSW & CY)) PSW |= SK; } /* 48 0b: 0100 1000 0000 1011 */ -static void SK_HC(upd7810_state *cpustate) +void upd7810_device::SK_HC() { if (HC == (PSW & HC)) PSW |= SK; } /* 48 0c: 0100 1000 0000 1100 */ -static void SK_Z(upd7810_state *cpustate) +void upd7810_device::SK_Z() { if (Z == (PSW & Z)) PSW |= SK; } /* 48 18: 0100 1000 0001 1000 */ -static void SKN_NV(upd7810_state *cpustate) +void upd7810_device::SKN_NV() { /* skip not never -> skip always ;-) */ PSW |= SK; } /* 48 1a: 0100 1000 0001 1010 */ -static void SKN_CY(upd7810_state *cpustate) +void upd7810_device::SKN_CY() { if (0 == (PSW & CY)) PSW |= SK; } /* 48 1b: 0100 1000 0001 1011 */ -static void SKN_HC(upd7810_state *cpustate) +void upd7810_device::SKN_HC() { if (0 == (PSW & HC)) PSW |= SK; } /* 48 1c: 0100 1000 0001 1100 */ -static void SKN_Z(upd7810_state *cpustate) +void upd7810_device::SKN_Z() { if (0 == (PSW & Z)) PSW |= SK; } /* 48 21: 0100 1000 0010 0001 */ -static void SLR_A(upd7810_state *cpustate) +void upd7810_device::SLR_A() { PSW = (PSW & ~CY) | (A & CY); A >>= 1; } /* 48 22: 0100 1000 0010 0010 */ -static void SLR_B(upd7810_state *cpustate) +void upd7810_device::SLR_B() { PSW = (PSW & ~CY) | (B & CY); B >>= 1; } /* 48 23: 0100 1000 0010 0011 */ -static void SLR_C(upd7810_state *cpustate) +void upd7810_device::SLR_C() { PSW = (PSW & ~CY) | (C & CY); C >>= 1; } /* 48 25: 0100 1000 0010 0101 */ -static void SLL_A(upd7810_state *cpustate) +void upd7810_device::SLL_A() { PSW = (PSW & ~CY) | ((A >> 7) & CY); A <<= 1; } /* 48 26: 0100 1000 0010 0110 */ -static void SLL_B(upd7810_state *cpustate) +void upd7810_device::SLL_B() { PSW = (PSW & ~CY) | ((B >> 7) & CY); B <<= 1; } /* 48 27: 0100 1000 0010 0111 */ -static void SLL_C(upd7810_state *cpustate) +void upd7810_device::SLL_C() { PSW = (PSW & ~CY) | ((C >> 7) & CY); C <<= 1; } /* 48 28: 0100 1000 0010 1000 */ -static void JEA(upd7810_state *cpustate) +void upd7810_device::JEA() { PC = EA; } /* 48 29: 0100 1000 0010 1001 */ -static void CALB(upd7810_state *cpustate) +void upd7810_device::CALB() { SP--; WM( SPD, PCH ); @@ -183,37 +183,37 @@ static void CALB(upd7810_state *cpustate) } /* 48 2a: 0100 1000 0010 1010 */ -static void CLC(upd7810_state *cpustate) +void upd7810_device::CLC() { PSW &= ~CY; } /* 48 2b: 0100 1000 0010 1011 */ -static void STC(upd7810_state *cpustate) +void upd7810_device::STC() { PSW |= CY; } /* 48 2d: 0100 1000 0010 1101 */ -static void MUL_A(upd7810_state *cpustate) +void upd7810_device::MUL_A() { EA = A * A; } /* 48 2e: 0100 1000 0010 1110 */ -static void MUL_B(upd7810_state *cpustate) +void upd7810_device::MUL_B() { EA = A * B; } /* 48 2f: 0100 1000 0010 1111 */ -static void MUL_C(upd7810_state *cpustate) +void upd7810_device::MUL_C() { EA = A * C; } /* 48 31: 0100 1000 0011 0001 */ -static void RLR_A(upd7810_state *cpustate) +void upd7810_device::RLR_A() { UINT8 carry=(PSW&CY)<<7; PSW = (PSW & ~CY) | (A & CY); @@ -221,7 +221,7 @@ static void RLR_A(upd7810_state *cpustate) } /* 48 32: 0100 1000 0011 0010 */ -static void RLR_B(upd7810_state *cpustate) +void upd7810_device::RLR_B() { UINT8 carry=(PSW&CY)<<7; PSW = (PSW & ~CY) | (B & CY); @@ -229,7 +229,7 @@ static void RLR_B(upd7810_state *cpustate) } /* 48 33: 0100 1000 0011 0011 */ -static void RLR_C(upd7810_state *cpustate) +void upd7810_device::RLR_C() { UINT8 carry=(PSW&CY)<<7; PSW = (PSW & ~CY) | (C & CY); @@ -237,7 +237,7 @@ static void RLR_C(upd7810_state *cpustate) } /* 48 35: 0100 1000 0011 0101 */ -static void RLL_A(upd7810_state *cpustate) +void upd7810_device::RLL_A() { UINT8 carry=PSW&CY; PSW = (PSW & ~CY) | ((A >> 7) & CY); @@ -245,7 +245,7 @@ static void RLL_A(upd7810_state *cpustate) } /* 48 36: 0100 1000 0011 0110 */ -static void RLL_B(upd7810_state *cpustate) +void upd7810_device::RLL_B() { UINT8 carry=PSW&CY; PSW = (PSW & ~CY) | ((B >> 7) & CY); @@ -253,7 +253,7 @@ static void RLL_B(upd7810_state *cpustate) } /* 48 37: 0100 1000 0011 0111 */ -static void RLL_C(upd7810_state *cpustate) +void upd7810_device::RLL_C() { UINT8 carry=PSW&CY; PSW = (PSW & ~CY) | ((C >> 7) & CY); @@ -261,7 +261,7 @@ static void RLL_C(upd7810_state *cpustate) } /* 48 38: 0100 1000 0011 1000 */ -static void RLD(upd7810_state *cpustate) +void upd7810_device::RLD() { UINT8 m = RM( HL ), tmp; tmp = (m << 4) | (A & 0x0f); @@ -270,7 +270,7 @@ static void RLD(upd7810_state *cpustate) } /* 48 39: 0100 1000 0011 1001 */ -static void RRD(upd7810_state *cpustate) +void upd7810_device::RRD() { UINT8 m = RM( HL ), tmp; tmp = (A << 4) | (m >> 4); @@ -279,22 +279,22 @@ static void RRD(upd7810_state *cpustate) } /* 48 3a: 0100 1000 0011 1010 */ -static void NEGA(upd7810_state *cpustate) +void upd7810_device::NEGA() { A = ~A + 1; } /* 48 3b: 0100 1000 0011 1011 */ -static void HALT(upd7810_state *cpustate) +void upd7810_device::HALT() { - int cycles = (cpustate->icount / 4) * 4; - cpustate->icount -= cycles; - cpustate->handle_timers(cpustate, cycles); + int cycles = (m_icount / 4) * 4; + m_icount -= cycles; + handle_timers(cycles); PC -= 1; /* continue executing HALT */ } /* 48 3d: 0100 1000 0011 1101 */ -static void DIV_A(upd7810_state *cpustate) +void upd7810_device::DIV_A() { if (A) { @@ -308,7 +308,7 @@ static void DIV_A(upd7810_state *cpustate) } /* 48 3e: 0100 1000 0011 1110 */ -static void DIV_B(upd7810_state *cpustate) +void upd7810_device::DIV_B() { if (B) { @@ -322,7 +322,7 @@ static void DIV_B(upd7810_state *cpustate) } /* 48 3f: 0100 1000 0011 1111 */ -static void DIV_C(upd7810_state *cpustate) +void upd7810_device::DIV_C() { if (C) { @@ -336,7 +336,7 @@ static void DIV_C(upd7810_state *cpustate) } /* 48 40: 0100 1000 0100 0000 */ -static void SKIT_NMI(upd7810_state *cpustate) +void upd7810_device::SKIT_NMI() { if (IRR & INTNMI) PSW |= SK; @@ -344,7 +344,7 @@ static void SKIT_NMI(upd7810_state *cpustate) } /* 48 41: 0100 1000 0100 0001 */ -static void SKIT_FT0(upd7810_state *cpustate) +void upd7810_device::SKIT_FT0() { if (IRR & INTFT0) PSW |= SK; @@ -352,7 +352,7 @@ static void SKIT_FT0(upd7810_state *cpustate) } /* 48 42: 0100 1000 0100 0010 */ -static void SKIT_FT1(upd7810_state *cpustate) +void upd7810_device::SKIT_FT1() { if (IRR & INTFT1) PSW |= SK; @@ -360,7 +360,7 @@ static void SKIT_FT1(upd7810_state *cpustate) } /* 48 43: 0100 1000 0100 0011 */ -static void SKIT_F1(upd7810_state *cpustate) +void upd7810_device::SKIT_F1() { if (IRR & INTF1) PSW |= SK; @@ -368,7 +368,7 @@ static void SKIT_F1(upd7810_state *cpustate) } /* 48 44: 0100 1000 0100 0100 */ -static void SKIT_F2(upd7810_state *cpustate) +void upd7810_device::SKIT_F2() { if (IRR & INTF2) PSW |= SK; @@ -376,7 +376,7 @@ static void SKIT_F2(upd7810_state *cpustate) } /* 48 45: 0100 1000 0100 0101 */ -static void SKIT_FE0(upd7810_state *cpustate) +void upd7810_device::SKIT_FE0() { if (IRR & INTFE0) PSW |= SK; @@ -384,7 +384,7 @@ static void SKIT_FE0(upd7810_state *cpustate) } /* 48 46: 0100 1000 0100 0110 */ -static void SKIT_FE1(upd7810_state *cpustate) +void upd7810_device::SKIT_FE1() { if (IRR & INTFE1) PSW |= SK; @@ -392,7 +392,7 @@ static void SKIT_FE1(upd7810_state *cpustate) } /* 48 47: 0100 1000 0100 0111 */ -static void SKIT_FEIN(upd7810_state *cpustate) +void upd7810_device::SKIT_FEIN() { if (IRR & INTFEIN) PSW |= SK; @@ -400,7 +400,7 @@ static void SKIT_FEIN(upd7810_state *cpustate) } /* 48 48: 0100 1000 0100 1000 */ -static void SKIT_FAD(upd7810_state *cpustate) +void upd7810_device::SKIT_FAD() { if (IRR & INTFAD) PSW |= SK; @@ -408,7 +408,7 @@ static void SKIT_FAD(upd7810_state *cpustate) } /* 48 49: 0100 1000 0100 1001 */ -static void SKIT_FSR(upd7810_state *cpustate) +void upd7810_device::SKIT_FSR() { if (IRR & INTFSR) PSW |= SK; @@ -416,7 +416,7 @@ static void SKIT_FSR(upd7810_state *cpustate) } /* 48 4a: 0100 1000 0100 1010 */ -static void SKIT_FST(upd7810_state *cpustate) +void upd7810_device::SKIT_FST() { if (IRR & INTFST) PSW |= SK; @@ -424,7 +424,7 @@ static void SKIT_FST(upd7810_state *cpustate) } /* 48 4b: 0100 1000 0100 1011 */ -static void SKIT_ER(upd7810_state *cpustate) +void upd7810_device::SKIT_ER() { if (IRR & INTER) PSW |= SK; @@ -432,7 +432,7 @@ static void SKIT_ER(upd7810_state *cpustate) } /* 48 4c: 0100 1000 0100 1100 */ -static void SKIT_OV(upd7810_state *cpustate) +void upd7810_device::SKIT_OV() { if (IRR & INTOV) PSW |= SK; @@ -440,7 +440,7 @@ static void SKIT_OV(upd7810_state *cpustate) } /* 48 50: 0100 1000 0101 0000 */ -static void SKIT_AN4(upd7810_state *cpustate) +void upd7810_device::SKIT_AN4() { if (ITF & INTAN4) PSW |= SK; @@ -448,7 +448,7 @@ static void SKIT_AN4(upd7810_state *cpustate) } /* 48 51: 0100 1000 0101 0001 */ -static void SKIT_AN5(upd7810_state *cpustate) +void upd7810_device::SKIT_AN5() { if (ITF & INTAN5) PSW |= SK; @@ -456,7 +456,7 @@ static void SKIT_AN5(upd7810_state *cpustate) } /* 48 52: 0100 1000 0101 0010 */ -static void SKIT_AN6(upd7810_state *cpustate) +void upd7810_device::SKIT_AN6() { if (ITF & INTAN6) PSW |= SK; @@ -464,7 +464,7 @@ static void SKIT_AN6(upd7810_state *cpustate) } /* 48 53: 0100 1000 0101 0011 */ -static void SKIT_AN7(upd7810_state *cpustate) +void upd7810_device::SKIT_AN7() { if (ITF & INTAN7) PSW |= SK; @@ -472,7 +472,7 @@ static void SKIT_AN7(upd7810_state *cpustate) } /* 48 54: 0100 1000 0101 0100 */ -static void SKIT_SB(upd7810_state *cpustate) +void upd7810_device::SKIT_SB() { if (ITF & INTSB) PSW |= SK; @@ -480,7 +480,7 @@ static void SKIT_SB(upd7810_state *cpustate) } /* 48 60: 0100 1000 0110 0000 */ -static void SKNIT_NMI(upd7810_state *cpustate) +void upd7810_device::SKNIT_NMI() { if (0 == (IRR & INTNMI)) PSW |= SK; @@ -488,7 +488,7 @@ static void SKNIT_NMI(upd7810_state *cpustate) } /* 48 61: 0100 1000 0110 0001 */ -static void SKNIT_FT0(upd7810_state *cpustate) +void upd7810_device::SKNIT_FT0() { if (0 == (IRR & INTFT0)) PSW |= SK; @@ -496,7 +496,7 @@ static void SKNIT_FT0(upd7810_state *cpustate) } /* 48 62: 0100 1000 0110 0010 */ -static void SKNIT_FT1(upd7810_state *cpustate) +void upd7810_device::SKNIT_FT1() { if (0 == (IRR & INTFT1)) PSW |= SK; @@ -504,7 +504,7 @@ static void SKNIT_FT1(upd7810_state *cpustate) } /* 48 63: 0100 1000 0110 0011 */ -static void SKNIT_F1(upd7810_state *cpustate) +void upd7810_device::SKNIT_F1() { if (0 == (IRR & INTF1)) PSW |= SK; @@ -512,7 +512,7 @@ static void SKNIT_F1(upd7810_state *cpustate) } /* 48 64: 0100 1000 0110 0100 */ -static void SKNIT_F2(upd7810_state *cpustate) +void upd7810_device::SKNIT_F2() { if (0 == (IRR & INTF2)) PSW |= SK; @@ -520,7 +520,7 @@ static void SKNIT_F2(upd7810_state *cpustate) } /* 48 65: 0100 1000 0110 0101 */ -static void SKNIT_FE0(upd7810_state *cpustate) +void upd7810_device::SKNIT_FE0() { if (0 == (IRR & INTFE0)) PSW |= SK; @@ -528,7 +528,7 @@ static void SKNIT_FE0(upd7810_state *cpustate) } /* 48 66: 0100 1000 0110 0110 */ -static void SKNIT_FE1(upd7810_state *cpustate) +void upd7810_device::SKNIT_FE1() { if (0 == (IRR & INTFE1)) PSW |= SK; @@ -536,7 +536,7 @@ static void SKNIT_FE1(upd7810_state *cpustate) } /* 48 67: 0100 1000 0110 0111 */ -static void SKNIT_FEIN(upd7810_state *cpustate) +void upd7810_device::SKNIT_FEIN() { if (0 == (IRR & INTFEIN)) PSW |= SK; @@ -544,7 +544,7 @@ static void SKNIT_FEIN(upd7810_state *cpustate) } /* 48 68: 0100 1000 0110 1000 */ -static void SKNIT_FAD(upd7810_state *cpustate) +void upd7810_device::SKNIT_FAD() { if (0 == (IRR & INTFAD)) PSW |= SK; @@ -552,7 +552,7 @@ static void SKNIT_FAD(upd7810_state *cpustate) } /* 48 69: 0100 1000 0110 1001 */ -static void SKNIT_FSR(upd7810_state *cpustate) +void upd7810_device::SKNIT_FSR() { if (0 == (IRR & INTFSR)) PSW |= SK; @@ -560,7 +560,7 @@ static void SKNIT_FSR(upd7810_state *cpustate) } /* 48 6a: 0100 1000 0110 1010 */ -static void SKNIT_FST(upd7810_state *cpustate) +void upd7810_device::SKNIT_FST() { if (0 == (IRR & INTFST)) PSW |= SK; @@ -568,7 +568,7 @@ static void SKNIT_FST(upd7810_state *cpustate) } /* 48 6b: 0100 1000 0110 1011 */ -static void SKNIT_ER(upd7810_state *cpustate) +void upd7810_device::SKNIT_ER() { if (0 == (IRR & INTER)) PSW |= SK; @@ -576,7 +576,7 @@ static void SKNIT_ER(upd7810_state *cpustate) } /* 48 6c: 0100 1000 0110 1100 */ -static void SKNIT_OV(upd7810_state *cpustate) +void upd7810_device::SKNIT_OV() { if (0 == (IRR & INTOV)) PSW |= SK; @@ -584,7 +584,7 @@ static void SKNIT_OV(upd7810_state *cpustate) } /* 48 70: 0100 1000 0111 0000 */ -static void SKNIT_AN4(upd7810_state *cpustate) +void upd7810_device::SKNIT_AN4() { if (0 == (ITF & INTAN4)) PSW |= SK; @@ -592,7 +592,7 @@ static void SKNIT_AN4(upd7810_state *cpustate) } /* 48 71: 0100 1000 0111 0001 */ -static void SKNIT_AN5(upd7810_state *cpustate) +void upd7810_device::SKNIT_AN5() { if (0 == (ITF & INTAN5)) PSW |= SK; @@ -600,7 +600,7 @@ static void SKNIT_AN5(upd7810_state *cpustate) } /* 48 72: 0100 1000 0111 0010 */ -static void SKNIT_AN6(upd7810_state *cpustate) +void upd7810_device::SKNIT_AN6() { if (0 == (ITF & INTAN6)) PSW |= SK; @@ -608,7 +608,7 @@ static void SKNIT_AN6(upd7810_state *cpustate) } /* 48 73: 0100 1000 0111 0011 */ -static void SKNIT_AN7(upd7810_state *cpustate) +void upd7810_device::SKNIT_AN7() { if (0 == (ITF & INTAN7)) PSW |= SK; @@ -616,7 +616,7 @@ static void SKNIT_AN7(upd7810_state *cpustate) } /* 48 74: 0100 1000 0111 0100 */ -static void SKNIT_SB(upd7810_state *cpustate) +void upd7810_device::SKNIT_SB() { if (0 == (ITF & INTSB)) PSW |= SK; @@ -624,21 +624,21 @@ static void SKNIT_SB(upd7810_state *cpustate) } /* 48 82: 0100 1000 1000 0010 */ -static void LDEAX_D(upd7810_state *cpustate) +void upd7810_device::LDEAX_D() { EAL = RM( DE ); EAH = RM( DE + 1 ); } /* 48 83: 0100 1000 1000 0011 */ -static void LDEAX_H(upd7810_state *cpustate) +void upd7810_device::LDEAX_H() { EAL = RM( HL ); EAH = RM( HL + 1 ); } /* 48 84: 0100 1000 1000 0100 */ -static void LDEAX_Dp(upd7810_state *cpustate) +void upd7810_device::LDEAX_Dp() { EAL = RM( DE ); EAH = RM( DE + 1 ); @@ -646,7 +646,7 @@ static void LDEAX_Dp(upd7810_state *cpustate) } /* 48 85: 0100 1000 1000 0101 */ -static void LDEAX_Hp(upd7810_state *cpustate) +void upd7810_device::LDEAX_Hp() { EAL = RM( HL ); EAH = RM( HL + 1 ); @@ -654,7 +654,7 @@ static void LDEAX_Hp(upd7810_state *cpustate) } /* 48 8b: 0100 1000 1000 1011 xxxx xxxx */ -static void LDEAX_D_xx(upd7810_state *cpustate) +void upd7810_device::LDEAX_D_xx() { UINT16 ea; RDOPARG( ea ); @@ -664,7 +664,7 @@ static void LDEAX_D_xx(upd7810_state *cpustate) } /* 48 8c: 0100 1000 1000 1100 */ -static void LDEAX_H_A(upd7810_state *cpustate) +void upd7810_device::LDEAX_H_A() { UINT16 ea = HL + A; EAL = RM( ea ); @@ -672,7 +672,7 @@ static void LDEAX_H_A(upd7810_state *cpustate) } /* 48 8d: 0100 1000 1000 1101 */ -static void LDEAX_H_B(upd7810_state *cpustate) +void upd7810_device::LDEAX_H_B() { UINT16 ea = HL + B; EAL = RM( ea ); @@ -680,7 +680,7 @@ static void LDEAX_H_B(upd7810_state *cpustate) } /* 48 8e: 0100 1000 1000 1110 */ -static void LDEAX_H_EA(upd7810_state *cpustate) +void upd7810_device::LDEAX_H_EA() { UINT16 ea = HL + EA; EAL = RM( ea ); @@ -688,7 +688,7 @@ static void LDEAX_H_EA(upd7810_state *cpustate) } /* 48 8f: 0100 1000 1000 1111 xxxx xxxx */ -static void LDEAX_H_xx(upd7810_state *cpustate) +void upd7810_device::LDEAX_H_xx() { UINT16 ea; RDOPARG( ea ); @@ -698,21 +698,21 @@ static void LDEAX_H_xx(upd7810_state *cpustate) } /* 48 92: 0100 1000 1000 0010 */ -static void STEAX_D(upd7810_state *cpustate) +void upd7810_device::STEAX_D() { WM( DE, EAL ); WM( DE + 1, EAH ); } /* 48 93: 0100 1000 1000 0011 */ -static void STEAX_H(upd7810_state *cpustate) +void upd7810_device::STEAX_H() { WM( HL, EAL ); WM( HL + 1, EAH ); } /* 48 94: 0100 1000 1000 0100 */ -static void STEAX_Dp(upd7810_state *cpustate) +void upd7810_device::STEAX_Dp() { WM( DE, EAL ); WM( DE + 1, EAH ); @@ -720,7 +720,7 @@ static void STEAX_Dp(upd7810_state *cpustate) } /* 48 95: 0100 1000 1000 0101 */ -static void STEAX_Hp(upd7810_state *cpustate) +void upd7810_device::STEAX_Hp() { WM( HL, EAL ); WM( HL + 1, EAH ); @@ -728,7 +728,7 @@ static void STEAX_Hp(upd7810_state *cpustate) } /* 48 9b: 0100 1000 1000 1011 xxxx xxxx */ -static void STEAX_D_xx(upd7810_state *cpustate) +void upd7810_device::STEAX_D_xx() { UINT16 ea; RDOPARG( ea ); @@ -738,7 +738,7 @@ static void STEAX_D_xx(upd7810_state *cpustate) } /* 48 9c: 0100 1000 1000 1100 */ -static void STEAX_H_A(upd7810_state *cpustate) +void upd7810_device::STEAX_H_A() { UINT16 ea = HL + A; WM( ea, EAL ); @@ -746,7 +746,7 @@ static void STEAX_H_A(upd7810_state *cpustate) } /* 48 9d: 0100 1000 1000 1101 */ -static void STEAX_H_B(upd7810_state *cpustate) +void upd7810_device::STEAX_H_B() { UINT16 ea = HL + B; WM( ea, EAL ); @@ -754,7 +754,7 @@ static void STEAX_H_B(upd7810_state *cpustate) } /* 48 9e: 0100 1000 1000 1110 */ -static void STEAX_H_EA(upd7810_state *cpustate) +void upd7810_device::STEAX_H_EA() { UINT16 ea = HL + EA; WM( ea, EAL ); @@ -762,7 +762,7 @@ static void STEAX_H_EA(upd7810_state *cpustate) } /* 48 9f: 0100 1000 1000 1111 xxxx xxxx */ -static void STEAX_H_xx(upd7810_state *cpustate) +void upd7810_device::STEAX_H_xx() { UINT16 ea; RDOPARG( ea ); @@ -772,21 +772,21 @@ static void STEAX_H_xx(upd7810_state *cpustate) } /* 48 a0: 0100 1000 1010 0000 */ -static void DSLR_EA(upd7810_state *cpustate) +void upd7810_device::DSLR_EA() { PSW = (PSW & ~CY) | (EA & CY); EA >>= 1; } /* 48 a4: 0100 1000 1010 0100 */ -static void DSLL_EA(upd7810_state *cpustate) +void upd7810_device::DSLL_EA() { PSW = (PSW & ~CY) | ((EA >> 15) & CY); EA <<= 1; } /* 48 a8: 0100 1000 1010 1000 */ -static void TABLE(upd7810_state *cpustate) +void upd7810_device::TABLE() { UINT16 ea = PC + A + 1; C = RM( ea ); @@ -794,7 +794,7 @@ static void TABLE(upd7810_state *cpustate) } /* 48 b0: 0100 1000 1011 0000 */ -static void DRLR_EA(upd7810_state *cpustate) +void upd7810_device::DRLR_EA() { UINT8 carry=PSW&CY; PSW = (PSW & ~CY) | (EA & CY); @@ -802,7 +802,7 @@ static void DRLR_EA(upd7810_state *cpustate) } /* 48 b4: 0100 1000 1011 0100 */ -static void DRLL_EA(upd7810_state *cpustate) +void upd7810_device::DRLL_EA() { UINT8 carry=PSW&CY; PSW = (PSW & ~CY) | ((EA >> 15) & CY); @@ -810,95 +810,95 @@ static void DRLL_EA(upd7810_state *cpustate) } /* 48 bb: 0100 1000 1011 1011 */ -static void STOP(upd7810_state *cpustate) +void upd7810_device::STOP() { - int cycles = (cpustate->icount / 4) * 4; - cpustate->icount -= cycles; - cpustate->handle_timers(cpustate, cycles); + int cycles = (m_icount / 4) * 4; + m_icount -= cycles; + handle_timers(cycles); PC -= 1; } /* 48 c0: 0100 1000 1100 0000 */ -static void DMOV_EA_ECNT(upd7810_state *cpustate) +void upd7810_device::DMOV_EA_ECNT() { EA = ECNT; } /* 48 c1: 0100 1000 1100 0001 */ -static void DMOV_EA_ECPT(upd7810_state *cpustate) +void upd7810_device::DMOV_EA_ECPT() { EA = ECPT; } /* 48 d2: 0100 1000 1101 0010 */ -static void DMOV_ETM0_EA(upd7810_state *cpustate) +void upd7810_device::DMOV_ETM0_EA() { ETM0 = EA; } /* 48 d3: 0100 1000 1101 0011 */ -static void DMOV_ETM1_EA(upd7810_state *cpustate) +void upd7810_device::DMOV_ETM1_EA() { ETM1 = EA; } /* prefix 4C */ /* 4c c0: 0100 1100 1100 0000 */ -static void MOV_A_PA(upd7810_state *cpustate) +void upd7810_device::MOV_A_PA() { - A = RP( cpustate, UPD7810_PORTA ); + A = RP( UPD7810_PORTA ); } /* 4c c1: 0100 1100 1100 0001 */ -static void MOV_A_PB(upd7810_state *cpustate) +void upd7810_device::MOV_A_PB() { - A = RP( cpustate, UPD7810_PORTB ); + A = RP( UPD7810_PORTB ); } /* 4c c2: 0100 1100 1100 0010 */ -static void MOV_A_PC(upd7810_state *cpustate) +void upd7810_device::MOV_A_PC() { - A = RP( cpustate, UPD7810_PORTC ); + A = RP( UPD7810_PORTC ); } /* 4c c3: 0100 1100 1100 0011 */ -static void MOV_A_PD(upd7810_state *cpustate) +void upd7810_device::MOV_A_PD() { - A = RP( cpustate, UPD7810_PORTD ); + A = RP( UPD7810_PORTD ); } /* 4c c5: 0100 1100 1100 0101 */ -static void MOV_A_PF(upd7810_state *cpustate) +void upd7810_device::MOV_A_PF() { - A = RP( cpustate, UPD7810_PORTF ); + A = RP( UPD7810_PORTF ); } /* 4c c6: 0100 1100 1100 0110 */ -static void MOV_A_MKH(upd7810_state *cpustate) +void upd7810_device::MOV_A_MKH() { A = MKH; } /* 4c c7: 0100 1100 1100 0111 */ -static void MOV_A_MKL(upd7810_state *cpustate) +void upd7810_device::MOV_A_MKL() { A = MKL; } /* 4c c8: 0100 1100 1100 1000 */ -static void MOV_A_ANM(upd7810_state *cpustate) +void upd7810_device::MOV_A_ANM() { A = ANM; } /* 4c c9: 0100 1100 1100 1001 */ -static void MOV_A_SMH(upd7810_state *cpustate) +void upd7810_device::MOV_A_SMH() { A = SMH; } /* 4c cb: 0100 1100 1100 1011 */ -static void MOV_A_EOM(upd7810_state *cpustate) +void upd7810_device::MOV_A_EOM() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -906,359 +906,359 @@ static void MOV_A_EOM(upd7810_state *cpustate) } /* 4c cd: 0100 1100 1100 1101 */ -static void MOV_A_TMM(upd7810_state *cpustate) +void upd7810_device::MOV_A_TMM() { A = TMM; } /* 4c ce: 0100 1100 1110 0000 (7807 only) */ -static void MOV_A_PT(upd7810_state *cpustate) +void upd7810_device::MOV_A_PT() { - A = RP( cpustate, UPD7807_PORTT ); + A = RP( UPD7807_PORTT ); } /* 4c d9: 0100 1100 1101 1001 */ -static void MOV_A_RXB(upd7810_state *cpustate) +void upd7810_device::MOV_A_RXB() { A = RXB; } /* 4c e0: 0100 1100 1110 0000 */ -static void MOV_A_CR0(upd7810_state *cpustate) +void upd7810_device::MOV_A_CR0() { A = CR0; } /* 4c e1: 0100 1100 1110 0001 */ -static void MOV_A_CR1(upd7810_state *cpustate) +void upd7810_device::MOV_A_CR1() { A = CR1; } /* 4c e2: 0100 1100 1110 0010 */ -static void MOV_A_CR2(upd7810_state *cpustate) +void upd7810_device::MOV_A_CR2() { A = CR2; } /* 4c e3: 0100 1100 1110 0011 */ -static void MOV_A_CR3(upd7810_state *cpustate) +void upd7810_device::MOV_A_CR3() { A = CR3; } /* prefix 4D */ /* 4d c0: 0100 1101 1100 0000 */ -static void MOV_PA_A(upd7810_state *cpustate) +void upd7810_device::MOV_PA_A() { - WP( cpustate, UPD7810_PORTA, A ); + WP( UPD7810_PORTA, A ); } /* 4d c1: 0100 1101 1100 0001 */ -static void MOV_PB_A(upd7810_state *cpustate) +void upd7810_device::MOV_PB_A() { - WP( cpustate, UPD7810_PORTB, A ); + WP( UPD7810_PORTB, A ); } /* 4d c2: 0100 1101 1100 0010 */ -static void MOV_PC_A(upd7810_state *cpustate) +void upd7810_device::MOV_PC_A() { - WP( cpustate, UPD7810_PORTC, A ); + WP( UPD7810_PORTC, A ); } /* 4d c3: 0100 1101 1100 0011 */ -static void MOV_PD_A(upd7810_state *cpustate) +void upd7810_device::MOV_PD_A() { - WP( cpustate, UPD7810_PORTD, A ); + WP( UPD7810_PORTD, A ); } /* 4d c5: 0100 1101 1100 0101 */ -static void MOV_PF_A(upd7810_state *cpustate) +void upd7810_device::MOV_PF_A() { - WP( cpustate, UPD7810_PORTF, A ); + WP( UPD7810_PORTF, A ); } /* 4d c6: 0100 1101 1100 0110 */ -static void MOV_MKH_A(upd7810_state *cpustate) +void upd7810_device::MOV_MKH_A() { MKH = A; } /* 4d c7: 0100 1101 1100 0111 */ -static void MOV_MKL_A(upd7810_state *cpustate) +void upd7810_device::MOV_MKL_A() { MKL = A; } /* 4d c8: 0100 1101 1100 1000 */ -static void MOV_ANM_A(upd7810_state *cpustate) +void upd7810_device::MOV_ANM_A() { ANM = A; } /* 4d c9: 0100 1101 1100 1001 */ -static void MOV_SMH_A(upd7810_state *cpustate) +void upd7810_device::MOV_SMH_A() { SMH = A; } /* 4d ca: 0100 1101 1100 1010 */ -static void MOV_SML_A(upd7810_state *cpustate) +void upd7810_device::MOV_SML_A() { SML = A; } /* 4d cb: 0100 1101 1100 1011 */ -static void MOV_EOM_A(upd7810_state *cpustate) +void upd7810_device::MOV_EOM_A() { EOM = A; - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 4d cc: 0100 1101 1100 1100 */ -static void MOV_ETMM_A(upd7810_state *cpustate) +void upd7810_device::MOV_ETMM_A() { ETMM = A; } /* 4d cd: 0100 1101 1100 1101 */ -static void MOV_TMM_A(upd7810_state *cpustate) +void upd7810_device::MOV_TMM_A() { TMM = A; } /* 4d d0: 0100 1101 1101 0000 */ -static void MOV_MM_A(upd7810_state *cpustate) +void upd7810_device::MOV_MM_A() { MM = A; } /* 4d d1: 0100 1101 1101 0001 */ -static void MOV_MCC_A(upd7810_state *cpustate) +void upd7810_device::MOV_MCC_A() { MCC = A; } /* 4d d2: 0100 1101 1101 0010 */ -static void MOV_MA_A(upd7810_state *cpustate) +void upd7810_device::MOV_MA_A() { MA = A; } /* 4d d3: 0100 1101 1101 0011 */ -static void MOV_MB_A(upd7810_state *cpustate) +void upd7810_device::MOV_MB_A() { MB = A; } /* 4d d4: 0100 1101 1101 0100 */ -static void MOV_MC_A(upd7810_state *cpustate) +void upd7810_device::MOV_MC_A() { MC = A; } /* 4d d7: 0100 1101 1101 0111 */ -static void MOV_MF_A(upd7810_state *cpustate) +void upd7810_device::MOV_MF_A() { MF = A; } /* 4d d8: 0100 1101 1101 1000 */ -static void MOV_TXB_A(upd7810_state *cpustate) +void upd7810_device::MOV_TXB_A() { TXB = A; - upd7810_write_TXB(cpustate); + upd7810_write_TXB(); } /* 4d da: 0100 1101 1101 1010 */ -static void MOV_TM0_A(upd7810_state *cpustate) +void upd7810_device::MOV_TM0_A() { TM0 = A; } /* 4d db: 0100 1101 1101 1011 */ -static void MOV_TM1_A(upd7810_state *cpustate) +void upd7810_device::MOV_TM1_A() { TM1 = A; } /* 4d e8: 0100 1101 1110 1000 */ -static void MOV_ZCM_A(upd7810_state *cpustate) +void upd7810_device::MOV_ZCM_A() { ZCM = A; } /* prefix 60 */ /* 60 08: 0110 0000 0000 1000 */ -static void ANA_V_A(upd7810_state *cpustate) +void upd7810_device::ANA_V_A() { V &= A; SET_Z(V); } /* 60 09: 0110 0000 0000 1001 */ -static void ANA_A_A(upd7810_state *cpustate) +void upd7810_device::ANA_A_A() { A &= A; SET_Z(A); } /* 60 0a: 0110 0000 0000 1010 */ -static void ANA_B_A(upd7810_state *cpustate) +void upd7810_device::ANA_B_A() { B &= A; SET_Z(B); } /* 60 0b: 0110 0000 0000 1011 */ -static void ANA_C_A(upd7810_state *cpustate) +void upd7810_device::ANA_C_A() { C &= A; SET_Z(C); } /* 60 0c: 0110 0000 0000 1100 */ -static void ANA_D_A(upd7810_state *cpustate) +void upd7810_device::ANA_D_A() { D &= A; SET_Z(D); } /* 60 0d: 0110 0000 0000 1101 */ -static void ANA_E_A(upd7810_state *cpustate) +void upd7810_device::ANA_E_A() { E &= A; SET_Z(E); } /* 60 0e: 0110 0000 0000 1110 */ -static void ANA_H_A(upd7810_state *cpustate) +void upd7810_device::ANA_H_A() { H &= A; SET_Z(H); } /* 60 0f: 0110 0000 0000 1111 */ -static void ANA_L_A(upd7810_state *cpustate) +void upd7810_device::ANA_L_A() { L &= A; SET_Z(L); } /* 60 10: 0110 0000 0001 0000 */ -static void XRA_V_A(upd7810_state *cpustate) +void upd7810_device::XRA_V_A() { V ^= A; SET_Z(V); } /* 60 11: 0110 0000 0001 0001 */ -static void XRA_A_A(upd7810_state *cpustate) +void upd7810_device::XRA_A_A() { A ^= A; SET_Z(A); } /* 60 12: 0110 0000 0001 0010 */ -static void XRA_B_A(upd7810_state *cpustate) +void upd7810_device::XRA_B_A() { B ^= A; SET_Z(B); } /* 60 13: 0110 0000 0001 0011 */ -static void XRA_C_A(upd7810_state *cpustate) +void upd7810_device::XRA_C_A() { C ^= A; SET_Z(C); } /* 60 14: 0110 0000 0001 0100 */ -static void XRA_D_A(upd7810_state *cpustate) +void upd7810_device::XRA_D_A() { D ^= A; SET_Z(D); } /* 60 15: 0110 0000 0001 0101 */ -static void XRA_E_A(upd7810_state *cpustate) +void upd7810_device::XRA_E_A() { E ^= A; SET_Z(E); } /* 60 16: 0110 0000 0001 0110 */ -static void XRA_H_A(upd7810_state *cpustate) +void upd7810_device::XRA_H_A() { H ^= A; SET_Z(H); } /* 60 17: 0110 0000 0001 0111 */ -static void XRA_L_A(upd7810_state *cpustate) +void upd7810_device::XRA_L_A() { L ^= A; SET_Z(L); } /* 60 18: 0110 0000 0001 1000 */ -static void ORA_V_A(upd7810_state *cpustate) +void upd7810_device::ORA_V_A() { V |= A; SET_Z(V); } /* 60 19: 0110 0000 0001 1001 */ -static void ORA_A_A(upd7810_state *cpustate) +void upd7810_device::ORA_A_A() { A |= A; SET_Z(A); } /* 60 1a: 0110 0000 0001 1010 */ -static void ORA_B_A(upd7810_state *cpustate) +void upd7810_device::ORA_B_A() { B |= A; SET_Z(B); } /* 60 1b: 0110 0000 0001 1011 */ -static void ORA_C_A(upd7810_state *cpustate) +void upd7810_device::ORA_C_A() { C |= A; SET_Z(C); } /* 60 1c: 0110 0000 0001 1100 */ -static void ORA_D_A(upd7810_state *cpustate) +void upd7810_device::ORA_D_A() { D |= A; SET_Z(D); } /* 60 1d: 0110 0000 0001 1101 */ -static void ORA_E_A(upd7810_state *cpustate) +void upd7810_device::ORA_E_A() { E |= A; SET_Z(E); } /* 60 1e: 0110 0000 0001 1110 */ -static void ORA_H_A(upd7810_state *cpustate) +void upd7810_device::ORA_H_A() { H |= A; SET_Z(H); } /* 60 1f: 0110 0000 0001 1111 */ -static void ORA_L_A(upd7810_state *cpustate) +void upd7810_device::ORA_L_A() { L |= A; SET_Z(L); } /* 60 20: 0110 0000 0010 0000 */ -static void ADDNC_V_A(upd7810_state *cpustate) +void upd7810_device::ADDNC_V_A() { UINT8 tmp = V + A; ZHC_ADD( tmp, V, 0 ); @@ -1267,7 +1267,7 @@ static void ADDNC_V_A(upd7810_state *cpustate) } /* 60 21: 0110 0000 0010 0001 */ -static void ADDNC_A_A(upd7810_state *cpustate) +void upd7810_device::ADDNC_A_A() { UINT8 tmp = A + A; ZHC_ADD( tmp, A, 0 ); @@ -1276,7 +1276,7 @@ static void ADDNC_A_A(upd7810_state *cpustate) } /* 60 22: 0110 0000 0010 0010 */ -static void ADDNC_B_A(upd7810_state *cpustate) +void upd7810_device::ADDNC_B_A() { UINT8 tmp = B + A; ZHC_ADD( tmp, B, 0 ); @@ -1285,7 +1285,7 @@ static void ADDNC_B_A(upd7810_state *cpustate) } /* 60 23: 0110 0000 0010 0011 */ -static void ADDNC_C_A(upd7810_state *cpustate) +void upd7810_device::ADDNC_C_A() { UINT8 tmp = C + A; ZHC_ADD( tmp, C, 0 ); @@ -1294,7 +1294,7 @@ static void ADDNC_C_A(upd7810_state *cpustate) } /* 60 24: 0110 0000 0010 0100 */ -static void ADDNC_D_A(upd7810_state *cpustate) +void upd7810_device::ADDNC_D_A() { UINT8 tmp = D + A; ZHC_ADD( tmp, D, 0 ); @@ -1303,7 +1303,7 @@ static void ADDNC_D_A(upd7810_state *cpustate) } /* 60 25: 0110 0000 0010 0101 */ -static void ADDNC_E_A(upd7810_state *cpustate) +void upd7810_device::ADDNC_E_A() { UINT8 tmp = E + A; ZHC_ADD( tmp, E, 0 ); @@ -1312,7 +1312,7 @@ static void ADDNC_E_A(upd7810_state *cpustate) } /* 60 26: 0110 0000 0010 0110 */ -static void ADDNC_H_A(upd7810_state *cpustate) +void upd7810_device::ADDNC_H_A() { UINT8 tmp = H + A; ZHC_ADD( tmp, H, 0 ); @@ -1321,7 +1321,7 @@ static void ADDNC_H_A(upd7810_state *cpustate) } /* 60 27: 0110 0000 0010 0111 */ -static void ADDNC_L_A(upd7810_state *cpustate) +void upd7810_device::ADDNC_L_A() { UINT8 tmp = L + A; ZHC_ADD( tmp, L, 0 ); @@ -1330,7 +1330,7 @@ static void ADDNC_L_A(upd7810_state *cpustate) } /* 60 28: 0110 0000 0010 1000 */ -static void GTA_V_A(upd7810_state *cpustate) +void upd7810_device::GTA_V_A() { UINT16 tmp = V - A - 1; ZHC_SUB( tmp, V, 0 ); @@ -1338,7 +1338,7 @@ static void GTA_V_A(upd7810_state *cpustate) } /* 60 29: 0110 0000 0010 1001 */ -static void GTA_A_A(upd7810_state *cpustate) +void upd7810_device::GTA_A_A() { UINT16 tmp = A - A - 1; ZHC_SUB( tmp, A, 0 ); @@ -1346,7 +1346,7 @@ static void GTA_A_A(upd7810_state *cpustate) } /* 60 2a: 0110 0000 0010 1010 */ -static void GTA_B_A(upd7810_state *cpustate) +void upd7810_device::GTA_B_A() { UINT16 tmp = B - A - 1; ZHC_SUB( tmp, B, 0 ); @@ -1354,7 +1354,7 @@ static void GTA_B_A(upd7810_state *cpustate) } /* 60 2b: 0110 0000 0010 1011 */ -static void GTA_C_A(upd7810_state *cpustate) +void upd7810_device::GTA_C_A() { UINT16 tmp = C - A - 1; ZHC_SUB( tmp, C, 0 ); @@ -1362,7 +1362,7 @@ static void GTA_C_A(upd7810_state *cpustate) } /* 60 2c: 0110 0000 0010 1100 */ -static void GTA_D_A(upd7810_state *cpustate) +void upd7810_device::GTA_D_A() { UINT16 tmp = D - A - 1; ZHC_SUB( tmp, D, 0 ); @@ -1370,7 +1370,7 @@ static void GTA_D_A(upd7810_state *cpustate) } /* 60 2d: 0110 0000 0010 1101 */ -static void GTA_E_A(upd7810_state *cpustate) +void upd7810_device::GTA_E_A() { UINT16 tmp = E - A - 1; ZHC_SUB( tmp, E, 0 ); @@ -1378,7 +1378,7 @@ static void GTA_E_A(upd7810_state *cpustate) } /* 60 2e: 0110 0000 0010 1110 */ -static void GTA_H_A(upd7810_state *cpustate) +void upd7810_device::GTA_H_A() { UINT16 tmp = H - A - 1; ZHC_SUB( tmp, H, 0 ); @@ -1386,7 +1386,7 @@ static void GTA_H_A(upd7810_state *cpustate) } /* 60 2f: 0110 0000 0010 1111 */ -static void GTA_L_A(upd7810_state *cpustate) +void upd7810_device::GTA_L_A() { UINT16 tmp = L - A - 1; ZHC_SUB( tmp, L, 0 ); @@ -1394,7 +1394,7 @@ static void GTA_L_A(upd7810_state *cpustate) } /* 60 30: 0110 0000 0011 0000 */ -static void SUBNB_V_A(upd7810_state *cpustate) +void upd7810_device::SUBNB_V_A() { UINT8 tmp = V - A; ZHC_SUB( tmp, V, 0 ); @@ -1403,7 +1403,7 @@ static void SUBNB_V_A(upd7810_state *cpustate) } /* 60 31: 0110 0000 0011 0001 */ -static void SUBNB_A_A(upd7810_state *cpustate) +void upd7810_device::SUBNB_A_A() { UINT8 tmp = A - A; ZHC_SUB( tmp, A, 0 ); @@ -1412,7 +1412,7 @@ static void SUBNB_A_A(upd7810_state *cpustate) } /* 60 32: 0110 0000 0011 0010 */ -static void SUBNB_B_A(upd7810_state *cpustate) +void upd7810_device::SUBNB_B_A() { UINT8 tmp = B - A; ZHC_SUB( tmp, B, 0 ); @@ -1421,7 +1421,7 @@ static void SUBNB_B_A(upd7810_state *cpustate) } /* 60 33: 0110 0000 0011 0011 */ -static void SUBNB_C_A(upd7810_state *cpustate) +void upd7810_device::SUBNB_C_A() { UINT8 tmp = C - A; ZHC_SUB( tmp, C, 0 ); @@ -1430,7 +1430,7 @@ static void SUBNB_C_A(upd7810_state *cpustate) } /* 60 34: 0110 0000 0011 0100 */ -static void SUBNB_D_A(upd7810_state *cpustate) +void upd7810_device::SUBNB_D_A() { UINT8 tmp = D - A; ZHC_SUB( tmp, D, 0 ); @@ -1439,7 +1439,7 @@ static void SUBNB_D_A(upd7810_state *cpustate) } /* 60 35: 0110 0000 0011 0101 */ -static void SUBNB_E_A(upd7810_state *cpustate) +void upd7810_device::SUBNB_E_A() { UINT8 tmp = E - A; ZHC_SUB( tmp, E, 0 ); @@ -1448,7 +1448,7 @@ static void SUBNB_E_A(upd7810_state *cpustate) } /* 60 36: 0110 0000 0011 0110 */ -static void SUBNB_H_A(upd7810_state *cpustate) +void upd7810_device::SUBNB_H_A() { UINT8 tmp = H - A; ZHC_SUB( tmp, H, 0 ); @@ -1457,7 +1457,7 @@ static void SUBNB_H_A(upd7810_state *cpustate) } /* 60 37: 0110 0000 0011 0111 */ -static void SUBNB_L_A(upd7810_state *cpustate) +void upd7810_device::SUBNB_L_A() { UINT8 tmp = L - A; ZHC_SUB( tmp, L, 0 ); @@ -1466,7 +1466,7 @@ static void SUBNB_L_A(upd7810_state *cpustate) } /* 60 38: 0110 0000 0011 1000 */ -static void LTA_V_A(upd7810_state *cpustate) +void upd7810_device::LTA_V_A() { UINT8 tmp = V - A; ZHC_SUB( tmp, V, 0 ); @@ -1474,7 +1474,7 @@ static void LTA_V_A(upd7810_state *cpustate) } /* 60 39: 0110 0000 0011 1001 */ -static void LTA_A_A(upd7810_state *cpustate) +void upd7810_device::LTA_A_A() { UINT8 tmp = A - A; ZHC_SUB( tmp, A, 0 ); @@ -1482,7 +1482,7 @@ static void LTA_A_A(upd7810_state *cpustate) } /* 60 3a: 0110 0000 0011 1010 */ -static void LTA_B_A(upd7810_state *cpustate) +void upd7810_device::LTA_B_A() { UINT8 tmp = B - A; ZHC_SUB( tmp, B, 0 ); @@ -1490,7 +1490,7 @@ static void LTA_B_A(upd7810_state *cpustate) } /* 60 3b: 0110 0000 0011 1011 */ -static void LTA_C_A(upd7810_state *cpustate) +void upd7810_device::LTA_C_A() { UINT8 tmp = C - A; ZHC_SUB( tmp, C, 0 ); @@ -1498,7 +1498,7 @@ static void LTA_C_A(upd7810_state *cpustate) } /* 60 3c: 0110 0000 0011 1100 */ -static void LTA_D_A(upd7810_state *cpustate) +void upd7810_device::LTA_D_A() { UINT8 tmp = D - A; ZHC_SUB( tmp, D, 0 ); @@ -1506,7 +1506,7 @@ static void LTA_D_A(upd7810_state *cpustate) } /* 60 3d: 0110 0000 0011 1101 */ -static void LTA_E_A(upd7810_state *cpustate) +void upd7810_device::LTA_E_A() { UINT8 tmp = E - A; ZHC_SUB( tmp, E, 0 ); @@ -1514,7 +1514,7 @@ static void LTA_E_A(upd7810_state *cpustate) } /* 60 3e: 0110 0000 0011 1110 */ -static void LTA_H_A(upd7810_state *cpustate) +void upd7810_device::LTA_H_A() { UINT8 tmp = H - A; ZHC_SUB( tmp, H, 0 ); @@ -1522,7 +1522,7 @@ static void LTA_H_A(upd7810_state *cpustate) } /* 60 3f: 0110 0000 0011 1111 */ -static void LTA_L_A(upd7810_state *cpustate) +void upd7810_device::LTA_L_A() { UINT8 tmp = L - A; ZHC_SUB( tmp, L, 0 ); @@ -1530,7 +1530,7 @@ static void LTA_L_A(upd7810_state *cpustate) } /* 60 40: 0110 0000 0100 0000 */ -static void ADD_V_A(upd7810_state *cpustate) +void upd7810_device::ADD_V_A() { UINT8 tmp = V + A; ZHC_ADD( tmp, V, 0 ); @@ -1538,7 +1538,7 @@ static void ADD_V_A(upd7810_state *cpustate) } /* 60 41: 0110 0000 0100 0001 */ -static void ADD_A_A(upd7810_state *cpustate) +void upd7810_device::ADD_A_A() { UINT8 tmp = A + A; ZHC_ADD( tmp, A, 0 ); @@ -1546,7 +1546,7 @@ static void ADD_A_A(upd7810_state *cpustate) } /* 60 42: 0110 0000 0100 0010 */ -static void ADD_B_A(upd7810_state *cpustate) +void upd7810_device::ADD_B_A() { UINT8 tmp = B + A; ZHC_ADD( tmp, B, 0 ); @@ -1554,7 +1554,7 @@ static void ADD_B_A(upd7810_state *cpustate) } /* 60 43: 0110 0000 0100 0011 */ -static void ADD_C_A(upd7810_state *cpustate) +void upd7810_device::ADD_C_A() { UINT8 tmp = C + A; ZHC_ADD( tmp, C, 0 ); @@ -1562,7 +1562,7 @@ static void ADD_C_A(upd7810_state *cpustate) } /* 60 44: 0110 0000 0100 0100 */ -static void ADD_D_A(upd7810_state *cpustate) +void upd7810_device::ADD_D_A() { UINT8 tmp = D + A; ZHC_ADD( tmp, D, 0 ); @@ -1570,7 +1570,7 @@ static void ADD_D_A(upd7810_state *cpustate) } /* 60 45: 0110 0000 0100 0101 */ -static void ADD_E_A(upd7810_state *cpustate) +void upd7810_device::ADD_E_A() { UINT8 tmp = E + A; ZHC_ADD( tmp, E, 0 ); @@ -1578,7 +1578,7 @@ static void ADD_E_A(upd7810_state *cpustate) } /* 60 46: 0110 0000 0100 0110 */ -static void ADD_H_A(upd7810_state *cpustate) +void upd7810_device::ADD_H_A() { UINT8 tmp = H + A; ZHC_ADD( tmp, H, 0 ); @@ -1586,7 +1586,7 @@ static void ADD_H_A(upd7810_state *cpustate) } /* 60 47: 0110 0000 0100 0111 */ -static void ADD_L_A(upd7810_state *cpustate) +void upd7810_device::ADD_L_A() { UINT8 tmp = L + A; ZHC_ADD( tmp, L, 0 ); @@ -1594,7 +1594,7 @@ static void ADD_L_A(upd7810_state *cpustate) } /* 60 50: 0110 0000 0101 0000 */ -static void ADC_V_A(upd7810_state *cpustate) +void upd7810_device::ADC_V_A() { UINT8 tmp = V + A + (PSW & CY); ZHC_ADD( tmp, V, (PSW & CY) ); @@ -1602,7 +1602,7 @@ static void ADC_V_A(upd7810_state *cpustate) } /* 60 51: 0110 0000 0101 0001 */ -static void ADC_A_A(upd7810_state *cpustate) +void upd7810_device::ADC_A_A() { UINT8 tmp = A + A + (PSW & CY); ZHC_ADD( tmp, A, (PSW & CY) ); @@ -1610,7 +1610,7 @@ static void ADC_A_A(upd7810_state *cpustate) } /* 60 52: 0110 0000 0101 0010 */ -static void ADC_B_A(upd7810_state *cpustate) +void upd7810_device::ADC_B_A() { UINT8 tmp = B + A + (PSW & CY); ZHC_ADD( tmp, B, (PSW & CY) ); @@ -1618,7 +1618,7 @@ static void ADC_B_A(upd7810_state *cpustate) } /* 60 53: 0110 0000 0101 0011 */ -static void ADC_C_A(upd7810_state *cpustate) +void upd7810_device::ADC_C_A() { UINT8 tmp = C + A + (PSW & CY); ZHC_ADD( tmp, C, (PSW & CY) ); @@ -1626,7 +1626,7 @@ static void ADC_C_A(upd7810_state *cpustate) } /* 60 54: 0110 0000 0101 0100 */ -static void ADC_D_A(upd7810_state *cpustate) +void upd7810_device::ADC_D_A() { UINT8 tmp = D + A + (PSW & CY); ZHC_ADD( tmp, D, (PSW & CY) ); @@ -1634,7 +1634,7 @@ static void ADC_D_A(upd7810_state *cpustate) } /* 60 55: 0110 0000 0101 0101 */ -static void ADC_E_A(upd7810_state *cpustate) +void upd7810_device::ADC_E_A() { UINT8 tmp = E + A + (PSW & CY); ZHC_ADD( tmp, E, (PSW & CY) ); @@ -1642,7 +1642,7 @@ static void ADC_E_A(upd7810_state *cpustate) } /* 60 56: 0110 0000 0101 0110 */ -static void ADC_H_A(upd7810_state *cpustate) +void upd7810_device::ADC_H_A() { UINT8 tmp = H + A + (PSW & CY); ZHC_ADD( tmp, H, (PSW & CY) ); @@ -1650,7 +1650,7 @@ static void ADC_H_A(upd7810_state *cpustate) } /* 60 57: 0110 0000 0101 0111 */ -static void ADC_L_A(upd7810_state *cpustate) +void upd7810_device::ADC_L_A() { UINT8 tmp = L + A + (PSW & CY); ZHC_ADD( tmp, L, (PSW & CY) ); @@ -1658,7 +1658,7 @@ static void ADC_L_A(upd7810_state *cpustate) } /* 60 60: 0110 0000 0110 0000 */ -static void SUB_V_A(upd7810_state *cpustate) +void upd7810_device::SUB_V_A() { UINT8 tmp = V - A; ZHC_SUB( tmp, V, 0 ); @@ -1666,7 +1666,7 @@ static void SUB_V_A(upd7810_state *cpustate) } /* 60 61: 0110 0000 0110 0001 */ -static void SUB_A_A(upd7810_state *cpustate) +void upd7810_device::SUB_A_A() { UINT8 tmp = A - A; ZHC_SUB( tmp, A, 0 ); @@ -1674,7 +1674,7 @@ static void SUB_A_A(upd7810_state *cpustate) } /* 60 62: 0110 0000 0110 0010 */ -static void SUB_B_A(upd7810_state *cpustate) +void upd7810_device::SUB_B_A() { UINT8 tmp = B - A; ZHC_SUB( tmp, B, 0 ); @@ -1682,7 +1682,7 @@ static void SUB_B_A(upd7810_state *cpustate) } /* 60 63: 0110 0000 0110 0011 */ -static void SUB_C_A(upd7810_state *cpustate) +void upd7810_device::SUB_C_A() { UINT8 tmp = C - A; ZHC_SUB( tmp, C, 0 ); @@ -1690,7 +1690,7 @@ static void SUB_C_A(upd7810_state *cpustate) } /* 60 64: 0110 0000 0110 0100 */ -static void SUB_D_A(upd7810_state *cpustate) +void upd7810_device::SUB_D_A() { UINT8 tmp = D - A; ZHC_SUB( tmp, D, 0 ); @@ -1698,7 +1698,7 @@ static void SUB_D_A(upd7810_state *cpustate) } /* 60 65: 0110 0000 0110 0101 */ -static void SUB_E_A(upd7810_state *cpustate) +void upd7810_device::SUB_E_A() { UINT8 tmp = E - A; ZHC_SUB( tmp, E, 0 ); @@ -1706,7 +1706,7 @@ static void SUB_E_A(upd7810_state *cpustate) } /* 60 66: 0110 0000 0110 0110 */ -static void SUB_H_A(upd7810_state *cpustate) +void upd7810_device::SUB_H_A() { UINT8 tmp = H - A; ZHC_SUB( tmp, H, 0 ); @@ -1714,7 +1714,7 @@ static void SUB_H_A(upd7810_state *cpustate) } /* 60 67: 0110 0000 0110 0111 */ -static void SUB_L_A(upd7810_state *cpustate) +void upd7810_device::SUB_L_A() { UINT8 tmp = L - A; ZHC_SUB( tmp, L, 0 ); @@ -1722,7 +1722,7 @@ static void SUB_L_A(upd7810_state *cpustate) } /* 60 68: 0110 0000 0110 1000 */ -static void NEA_V_A(upd7810_state *cpustate) +void upd7810_device::NEA_V_A() { UINT8 tmp = V - A; ZHC_SUB( tmp, V, 0 ); @@ -1730,7 +1730,7 @@ static void NEA_V_A(upd7810_state *cpustate) } /* 60 69: 0110 0000 0110 1001 */ -static void NEA_A_A(upd7810_state *cpustate) +void upd7810_device::NEA_A_A() { UINT8 tmp = A - A; ZHC_SUB( tmp, A, 0 ); @@ -1738,7 +1738,7 @@ static void NEA_A_A(upd7810_state *cpustate) } /* 60 6a: 0110 0000 0110 1010 */ -static void NEA_B_A(upd7810_state *cpustate) +void upd7810_device::NEA_B_A() { UINT8 tmp = B - A; ZHC_SUB( tmp, B, 0 ); @@ -1746,7 +1746,7 @@ static void NEA_B_A(upd7810_state *cpustate) } /* 60 6b: 0110 0000 0110 1011 */ -static void NEA_C_A(upd7810_state *cpustate) +void upd7810_device::NEA_C_A() { UINT8 tmp = C - A; ZHC_SUB( tmp, C, 0 ); @@ -1754,7 +1754,7 @@ static void NEA_C_A(upd7810_state *cpustate) } /* 60 6c: 0110 0000 0110 1100 */ -static void NEA_D_A(upd7810_state *cpustate) +void upd7810_device::NEA_D_A() { UINT8 tmp = D - A; ZHC_SUB( tmp, D, 0 ); @@ -1762,7 +1762,7 @@ static void NEA_D_A(upd7810_state *cpustate) } /* 60 6d: 0110 0000 0110 1101 */ -static void NEA_E_A(upd7810_state *cpustate) +void upd7810_device::NEA_E_A() { UINT8 tmp = E - A; ZHC_SUB( tmp, E, 0 ); @@ -1770,7 +1770,7 @@ static void NEA_E_A(upd7810_state *cpustate) } /* 60 6e: 0110 0000 0110 1110 */ -static void NEA_H_A(upd7810_state *cpustate) +void upd7810_device::NEA_H_A() { UINT8 tmp = H - A; ZHC_SUB( tmp, H, 0 ); @@ -1778,7 +1778,7 @@ static void NEA_H_A(upd7810_state *cpustate) } /* 60 6f: 0110 0000 0110 1111 */ -static void NEA_L_A(upd7810_state *cpustate) +void upd7810_device::NEA_L_A() { UINT8 tmp = L - A; ZHC_SUB( tmp, L, 0 ); @@ -1786,7 +1786,7 @@ static void NEA_L_A(upd7810_state *cpustate) } /* 60 70: 0110 0000 0111 0000 */ -static void SBB_V_A(upd7810_state *cpustate) +void upd7810_device::SBB_V_A() { UINT8 tmp = V - A - (PSW & CY); ZHC_SUB( tmp, V, (PSW & CY) ); @@ -1794,7 +1794,7 @@ static void SBB_V_A(upd7810_state *cpustate) } /* 60 71: 0110 0000 0111 0001 */ -static void SBB_A_A(upd7810_state *cpustate) +void upd7810_device::SBB_A_A() { UINT8 tmp = A - A - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -1802,7 +1802,7 @@ static void SBB_A_A(upd7810_state *cpustate) } /* 60 72: 0110 0000 0111 0010 */ -static void SBB_B_A(upd7810_state *cpustate) +void upd7810_device::SBB_B_A() { UINT8 tmp = B - A - (PSW & CY); ZHC_SUB( tmp, B, (PSW & CY) ); @@ -1810,7 +1810,7 @@ static void SBB_B_A(upd7810_state *cpustate) } /* 60 73: 0110 0000 0111 0011 */ -static void SBB_C_A(upd7810_state *cpustate) +void upd7810_device::SBB_C_A() { UINT8 tmp = C - A - (PSW & CY); ZHC_SUB( tmp, C, (PSW & CY) ); @@ -1818,7 +1818,7 @@ static void SBB_C_A(upd7810_state *cpustate) } /* 60 74: 0110 0000 0111 0100 */ -static void SBB_D_A(upd7810_state *cpustate) +void upd7810_device::SBB_D_A() { UINT8 tmp = D - A - (PSW & CY); ZHC_SUB( tmp, D, (PSW & CY) ); @@ -1826,7 +1826,7 @@ static void SBB_D_A(upd7810_state *cpustate) } /* 60 75: 0110 0000 0111 0101 */ -static void SBB_E_A(upd7810_state *cpustate) +void upd7810_device::SBB_E_A() { UINT8 tmp = E - A - (PSW & CY); ZHC_SUB( tmp, E, (PSW & CY) ); @@ -1834,7 +1834,7 @@ static void SBB_E_A(upd7810_state *cpustate) } /* 60 76: 0110 0000 0111 0110 */ -static void SBB_H_A(upd7810_state *cpustate) +void upd7810_device::SBB_H_A() { UINT8 tmp = H - A - (PSW & CY); ZHC_SUB( tmp, H, (PSW & CY) ); @@ -1842,7 +1842,7 @@ static void SBB_H_A(upd7810_state *cpustate) } /* 60 77: 0110 0000 0111 0111 */ -static void SBB_L_A(upd7810_state *cpustate) +void upd7810_device::SBB_L_A() { UINT8 tmp = L - A - (PSW & CY); ZHC_SUB( tmp, L, (PSW & CY) ); @@ -1850,7 +1850,7 @@ static void SBB_L_A(upd7810_state *cpustate) } /* 60 78: 0110 0000 0111 1000 */ -static void EQA_V_A(upd7810_state *cpustate) +void upd7810_device::EQA_V_A() { UINT8 tmp = V - A; ZHC_SUB( tmp, V, 0 ); @@ -1858,7 +1858,7 @@ static void EQA_V_A(upd7810_state *cpustate) } /* 60 79: 0110 0000 0111 1001 */ -static void EQA_A_A(upd7810_state *cpustate) +void upd7810_device::EQA_A_A() { UINT8 tmp = A - A; ZHC_SUB( tmp, A, 0 ); @@ -1866,7 +1866,7 @@ static void EQA_A_A(upd7810_state *cpustate) } /* 60 7a: 0110 0000 0111 1010 */ -static void EQA_B_A(upd7810_state *cpustate) +void upd7810_device::EQA_B_A() { UINT8 tmp = B - A; ZHC_SUB( tmp, B, 0 ); @@ -1874,7 +1874,7 @@ static void EQA_B_A(upd7810_state *cpustate) } /* 60 7b: 0110 0000 0111 1011 */ -static void EQA_C_A(upd7810_state *cpustate) +void upd7810_device::EQA_C_A() { UINT8 tmp = C - A; ZHC_SUB( tmp, C, 0 ); @@ -1882,7 +1882,7 @@ static void EQA_C_A(upd7810_state *cpustate) } /* 60 7c: 0110 0000 0111 1100 */ -static void EQA_D_A(upd7810_state *cpustate) +void upd7810_device::EQA_D_A() { UINT8 tmp = D - A; ZHC_SUB( tmp, D, 0 ); @@ -1890,7 +1890,7 @@ static void EQA_D_A(upd7810_state *cpustate) } /* 60 7d: 0110 0000 0111 1101 */ -static void EQA_E_A(upd7810_state *cpustate) +void upd7810_device::EQA_E_A() { UINT8 tmp = E - A; ZHC_SUB( tmp, E, 0 ); @@ -1898,7 +1898,7 @@ static void EQA_E_A(upd7810_state *cpustate) } /* 60 7e: 0110 0000 0111 1110 */ -static void EQA_H_A(upd7810_state *cpustate) +void upd7810_device::EQA_H_A() { UINT8 tmp = H - A; ZHC_SUB( tmp, H, 0 ); @@ -1906,7 +1906,7 @@ static void EQA_H_A(upd7810_state *cpustate) } /* 60 7f: 0110 0000 0111 1111 */ -static void EQA_L_A(upd7810_state *cpustate) +void upd7810_device::EQA_L_A() { UINT8 tmp = L - A; ZHC_SUB( tmp, L, 0 ); @@ -1914,7 +1914,7 @@ static void EQA_L_A(upd7810_state *cpustate) } /* 60 88: 0110 0000 1000 1000 */ -static void ANA_A_V(upd7810_state *cpustate) +void upd7810_device::ANA_A_V() { A &= V; SET_Z(A); @@ -1924,49 +1924,49 @@ static void ANA_A_V(upd7810_state *cpustate) /* ANA_A_A already defined */ /* 60 8a: 0110 0000 1000 1010 */ -static void ANA_A_B(upd7810_state *cpustate) +void upd7810_device::ANA_A_B() { A &= B; SET_Z(A); } /* 60 8b: 0110 0000 1000 1011 */ -static void ANA_A_C(upd7810_state *cpustate) +void upd7810_device::ANA_A_C() { A &= C; SET_Z(A); } /* 60 8c: 0110 0000 1000 1100 */ -static void ANA_A_D(upd7810_state *cpustate) +void upd7810_device::ANA_A_D() { A &= D; SET_Z(A); } /* 60 8d: 0110 0000 1000 1101 */ -static void ANA_A_E(upd7810_state *cpustate) +void upd7810_device::ANA_A_E() { A &= E; SET_Z(A); } /* 60 8e: 0110 0000 1000 1110 */ -static void ANA_A_H(upd7810_state *cpustate) +void upd7810_device::ANA_A_H() { A &= H; SET_Z(A); } /* 60 8f: 0110 0000 1000 1111 */ -static void ANA_A_L(upd7810_state *cpustate) +void upd7810_device::ANA_A_L() { A &= L; SET_Z(A); } /* 60 90: 0110 0000 1001 0000 */ -static void XRA_A_V(upd7810_state *cpustate) +void upd7810_device::XRA_A_V() { A ^= V; SET_Z(A); @@ -1976,49 +1976,49 @@ static void XRA_A_V(upd7810_state *cpustate) /* XRA_A_A already defined */ /* 60 92: 0110 0000 1001 0010 */ -static void XRA_A_B(upd7810_state *cpustate) +void upd7810_device::XRA_A_B() { A ^= B; SET_Z(A); } /* 60 93: 0110 0000 1001 0011 */ -static void XRA_A_C(upd7810_state *cpustate) +void upd7810_device::XRA_A_C() { A ^= C; SET_Z(A); } /* 60 94: 0110 0000 1001 0100 */ -static void XRA_A_D(upd7810_state *cpustate) +void upd7810_device::XRA_A_D() { A ^= D; SET_Z(A); } /* 60 95: 0110 0000 1001 0101 */ -static void XRA_A_E(upd7810_state *cpustate) +void upd7810_device::XRA_A_E() { A ^= E; SET_Z(A); } /* 60 96: 0110 0000 1001 0110 */ -static void XRA_A_H(upd7810_state *cpustate) +void upd7810_device::XRA_A_H() { A ^= H; SET_Z(A); } /* 60 97: 0110 0000 1001 0111 */ -static void XRA_A_L(upd7810_state *cpustate) +void upd7810_device::XRA_A_L() { A ^= L; SET_Z(A); } /* 60 98: 0110 0000 1001 1000 */ -static void ORA_A_V(upd7810_state *cpustate) +void upd7810_device::ORA_A_V() { A |= V; SET_Z(A); @@ -2028,49 +2028,49 @@ static void ORA_A_V(upd7810_state *cpustate) /* ORA_A_A already defined */ /* 60 9a: 0110 0000 1001 1010 */ -static void ORA_A_B(upd7810_state *cpustate) +void upd7810_device::ORA_A_B() { A |= B; SET_Z(A); } /* 60 9b: 0110 0000 1001 1011 */ -static void ORA_A_C(upd7810_state *cpustate) +void upd7810_device::ORA_A_C() { A |= C; SET_Z(A); } /* 60 9c: 0110 0000 1001 1100 */ -static void ORA_A_D(upd7810_state *cpustate) +void upd7810_device::ORA_A_D() { A |= D; SET_Z(A); } /* 60 9d: 0110 0000 1001 1101 */ -static void ORA_A_E(upd7810_state *cpustate) +void upd7810_device::ORA_A_E() { A |= E; SET_Z(A); } /* 60 9e: 0110 0000 1001 1110 */ -static void ORA_A_H(upd7810_state *cpustate) +void upd7810_device::ORA_A_H() { A |= H; SET_Z(A); } /* 60 9f: 0110 0000 1001 1111 */ -static void ORA_A_L(upd7810_state *cpustate) +void upd7810_device::ORA_A_L() { A |= L; SET_Z(A); } /* 60 a0: 0110 0000 1010 0000 */ -static void ADDNC_A_V(upd7810_state *cpustate) +void upd7810_device::ADDNC_A_V() { UINT8 tmp = A + V; ZHC_ADD( tmp, A, 0 ); @@ -2082,7 +2082,7 @@ static void ADDNC_A_V(upd7810_state *cpustate) /* ADDNC_A_A already defined */ /* 60 a2: 0110 0000 1010 0010 */ -static void ADDNC_A_B(upd7810_state *cpustate) +void upd7810_device::ADDNC_A_B() { UINT8 tmp = A + B; ZHC_ADD( tmp, A, 0 ); @@ -2091,7 +2091,7 @@ static void ADDNC_A_B(upd7810_state *cpustate) } /* 60 a3: 0110 0000 1010 0011 */ -static void ADDNC_A_C(upd7810_state *cpustate) +void upd7810_device::ADDNC_A_C() { UINT8 tmp = A + C; ZHC_ADD( tmp, A, 0 ); @@ -2100,7 +2100,7 @@ static void ADDNC_A_C(upd7810_state *cpustate) } /* 60 a4: 0110 0000 1010 0100 */ -static void ADDNC_A_D(upd7810_state *cpustate) +void upd7810_device::ADDNC_A_D() { UINT8 tmp = A + D; ZHC_ADD( tmp, A, 0 ); @@ -2109,7 +2109,7 @@ static void ADDNC_A_D(upd7810_state *cpustate) } /* 60 a5: 0110 0000 1010 0101 */ -static void ADDNC_A_E(upd7810_state *cpustate) +void upd7810_device::ADDNC_A_E() { UINT8 tmp = A + E; ZHC_ADD( tmp, A, 0 ); @@ -2118,7 +2118,7 @@ static void ADDNC_A_E(upd7810_state *cpustate) } /* 60 a6: 0110 0000 1010 0110 */ -static void ADDNC_A_H(upd7810_state *cpustate) +void upd7810_device::ADDNC_A_H() { UINT8 tmp = A + H; ZHC_ADD( tmp, A, 0 ); @@ -2127,7 +2127,7 @@ static void ADDNC_A_H(upd7810_state *cpustate) } /* 60 a7: 0110 0000 1010 0111 */ -static void ADDNC_A_L(upd7810_state *cpustate) +void upd7810_device::ADDNC_A_L() { UINT8 tmp = A + L; ZHC_ADD( tmp, A, 0 ); @@ -2136,7 +2136,7 @@ static void ADDNC_A_L(upd7810_state *cpustate) } /* 60 a8: 0110 0000 1010 1000 */ -static void GTA_A_V(upd7810_state *cpustate) +void upd7810_device::GTA_A_V() { UINT16 tmp = A - V - 1; ZHC_SUB( tmp, A, 0 ); @@ -2147,7 +2147,7 @@ static void GTA_A_V(upd7810_state *cpustate) /* GTA_A_A already defined */ /* 60 aa: 0110 0000 1010 1010 */ -static void GTA_A_B(upd7810_state *cpustate) +void upd7810_device::GTA_A_B() { UINT16 tmp = A - B - 1; ZHC_SUB( tmp, A, 0 ); @@ -2155,7 +2155,7 @@ static void GTA_A_B(upd7810_state *cpustate) } /* 60 ab: 0110 0000 1010 1011 */ -static void GTA_A_C(upd7810_state *cpustate) +void upd7810_device::GTA_A_C() { UINT16 tmp = A - C - 1; ZHC_SUB( tmp, A, 0 ); @@ -2163,7 +2163,7 @@ static void GTA_A_C(upd7810_state *cpustate) } /* 60 ac: 0110 0000 1010 1100 */ -static void GTA_A_D(upd7810_state *cpustate) +void upd7810_device::GTA_A_D() { UINT16 tmp = A - D - 1; ZHC_SUB( tmp, A, 0 ); @@ -2171,7 +2171,7 @@ static void GTA_A_D(upd7810_state *cpustate) } /* 60 ad: 0110 0000 1010 1101 */ -static void GTA_A_E(upd7810_state *cpustate) +void upd7810_device::GTA_A_E() { UINT16 tmp = A - E - 1; ZHC_SUB( tmp, A, 0 ); @@ -2179,7 +2179,7 @@ static void GTA_A_E(upd7810_state *cpustate) } /* 60 ae: 0110 0000 1010 1110 */ -static void GTA_A_H(upd7810_state *cpustate) +void upd7810_device::GTA_A_H() { UINT16 tmp = A - H - 1; ZHC_SUB( tmp, A, 0 ); @@ -2187,7 +2187,7 @@ static void GTA_A_H(upd7810_state *cpustate) } /* 60 af: 0110 0000 1010 1111 */ -static void GTA_A_L(upd7810_state *cpustate) +void upd7810_device::GTA_A_L() { UINT16 tmp = A - L - 1; ZHC_SUB( tmp, A, 0 ); @@ -2195,7 +2195,7 @@ static void GTA_A_L(upd7810_state *cpustate) } /* 60 b0: 0110 0000 1011 0000 */ -static void SUBNB_A_V(upd7810_state *cpustate) +void upd7810_device::SUBNB_A_V() { UINT8 tmp = A - V; ZHC_SUB( tmp, A, 0 ); @@ -2207,7 +2207,7 @@ static void SUBNB_A_V(upd7810_state *cpustate) /* SUBNB_A_A already defined */ /* 60 b2: 0110 0000 1011 0010 */ -static void SUBNB_A_B(upd7810_state *cpustate) +void upd7810_device::SUBNB_A_B() { UINT8 tmp = A - B; ZHC_SUB( tmp, A, 0 ); @@ -2216,7 +2216,7 @@ static void SUBNB_A_B(upd7810_state *cpustate) } /* 60 b3: 0110 0000 1011 0011 */ -static void SUBNB_A_C(upd7810_state *cpustate) +void upd7810_device::SUBNB_A_C() { UINT8 tmp = A - C; ZHC_SUB( tmp, A, 0 ); @@ -2225,7 +2225,7 @@ static void SUBNB_A_C(upd7810_state *cpustate) } /* 60 b4: 0110 0000 1011 0100 */ -static void SUBNB_A_D(upd7810_state *cpustate) +void upd7810_device::SUBNB_A_D() { UINT8 tmp = A - D; ZHC_SUB( tmp, A, 0 ); @@ -2234,7 +2234,7 @@ static void SUBNB_A_D(upd7810_state *cpustate) } /* 60 b5: 0110 0000 1011 0101 */ -static void SUBNB_A_E(upd7810_state *cpustate) +void upd7810_device::SUBNB_A_E() { UINT8 tmp = A - E; ZHC_SUB( tmp, A, 0 ); @@ -2243,7 +2243,7 @@ static void SUBNB_A_E(upd7810_state *cpustate) } /* 60 b6: 0110 0000 1011 0110 */ -static void SUBNB_A_H(upd7810_state *cpustate) +void upd7810_device::SUBNB_A_H() { UINT8 tmp = A - H; ZHC_SUB( tmp, A, 0 ); @@ -2252,7 +2252,7 @@ static void SUBNB_A_H(upd7810_state *cpustate) } /* 60 b7: 0110 0000 1011 0111 */ -static void SUBNB_A_L(upd7810_state *cpustate) +void upd7810_device::SUBNB_A_L() { UINT8 tmp = A - L; ZHC_SUB( tmp, A, 0 ); @@ -2261,7 +2261,7 @@ static void SUBNB_A_L(upd7810_state *cpustate) } /* 60 b8: 0110 0000 1011 1000 */ -static void LTA_A_V(upd7810_state *cpustate) +void upd7810_device::LTA_A_V() { UINT8 tmp = A - V; ZHC_SUB( tmp, A, 0 ); @@ -2272,7 +2272,7 @@ static void LTA_A_V(upd7810_state *cpustate) /* LTA_A_A already defined */ /* 60 ba: 0110 0000 1011 1010 */ -static void LTA_A_B(upd7810_state *cpustate) +void upd7810_device::LTA_A_B() { UINT8 tmp = A - B; ZHC_SUB( tmp, A, 0 ); @@ -2280,7 +2280,7 @@ static void LTA_A_B(upd7810_state *cpustate) } /* 60 bb: 0110 0000 1011 1011 */ -static void LTA_A_C(upd7810_state *cpustate) +void upd7810_device::LTA_A_C() { UINT8 tmp = A - C; ZHC_SUB( tmp, A, 0 ); @@ -2288,7 +2288,7 @@ static void LTA_A_C(upd7810_state *cpustate) } /* 60 bc: 0110 0000 1011 1100 */ -static void LTA_A_D(upd7810_state *cpustate) +void upd7810_device::LTA_A_D() { UINT8 tmp = A - D; ZHC_SUB( tmp, A, 0 ); @@ -2296,7 +2296,7 @@ static void LTA_A_D(upd7810_state *cpustate) } /* 60 bd: 0110 0000 1011 1101 */ -static void LTA_A_E(upd7810_state *cpustate) +void upd7810_device::LTA_A_E() { UINT8 tmp = A - E; ZHC_SUB( tmp, A, 0 ); @@ -2304,7 +2304,7 @@ static void LTA_A_E(upd7810_state *cpustate) } /* 60 be: 0110 0000 1011 1110 */ -static void LTA_A_H(upd7810_state *cpustate) +void upd7810_device::LTA_A_H() { UINT8 tmp = A - H; ZHC_SUB( tmp, A, 0 ); @@ -2312,7 +2312,7 @@ static void LTA_A_H(upd7810_state *cpustate) } /* 60 bf: 0110 0000 1011 1111 */ -static void LTA_A_L(upd7810_state *cpustate) +void upd7810_device::LTA_A_L() { UINT8 tmp = A - L; ZHC_SUB( tmp, A, 0 ); @@ -2320,7 +2320,7 @@ static void LTA_A_L(upd7810_state *cpustate) } /* 60 c0: 0110 0000 1100 0000 */ -static void ADD_A_V(upd7810_state *cpustate) +void upd7810_device::ADD_A_V() { UINT8 tmp = A + V; ZHC_ADD( tmp, A, 0 ); @@ -2331,7 +2331,7 @@ static void ADD_A_V(upd7810_state *cpustate) /* ADD_A_A already defined */ /* 60 c2: 0110 0000 1100 0010 */ -static void ADD_A_B(upd7810_state *cpustate) +void upd7810_device::ADD_A_B() { UINT8 tmp = A + B; ZHC_ADD( tmp, A, 0 ); @@ -2339,7 +2339,7 @@ static void ADD_A_B(upd7810_state *cpustate) } /* 60 c3: 0110 0000 1100 0011 */ -static void ADD_A_C(upd7810_state *cpustate) +void upd7810_device::ADD_A_C() { UINT8 tmp = A + C; ZHC_ADD( tmp, A, 0 ); @@ -2347,7 +2347,7 @@ static void ADD_A_C(upd7810_state *cpustate) } /* 60 c4: 0110 0000 1100 0100 */ -static void ADD_A_D(upd7810_state *cpustate) +void upd7810_device::ADD_A_D() { UINT8 tmp = A + D; ZHC_ADD( tmp, A, 0 ); @@ -2355,7 +2355,7 @@ static void ADD_A_D(upd7810_state *cpustate) } /* 60 c5: 0110 0000 1100 0101 */ -static void ADD_A_E(upd7810_state *cpustate) +void upd7810_device::ADD_A_E() { UINT8 tmp = A + E; ZHC_ADD( tmp, A, 0 ); @@ -2363,7 +2363,7 @@ static void ADD_A_E(upd7810_state *cpustate) } /* 60 c6: 0110 0000 1100 0110 */ -static void ADD_A_H(upd7810_state *cpustate) +void upd7810_device::ADD_A_H() { UINT8 tmp = A + H; ZHC_ADD( tmp, A, 0 ); @@ -2371,7 +2371,7 @@ static void ADD_A_H(upd7810_state *cpustate) } /* 60 c7: 0110 0000 1100 0111 */ -static void ADD_A_L(upd7810_state *cpustate) +void upd7810_device::ADD_A_L() { UINT8 tmp = A + L; ZHC_ADD( tmp, A, 0 ); @@ -2379,7 +2379,7 @@ static void ADD_A_L(upd7810_state *cpustate) } /* 60 c8: 0110 0000 1100 1000 */ -static void ONA_A_V(upd7810_state *cpustate) +void upd7810_device::ONA_A_V() { if (A & V) PSW = (PSW & ~Z) | SK; @@ -2388,7 +2388,7 @@ static void ONA_A_V(upd7810_state *cpustate) } /* 60 c9: 0110 0000 1100 1001 */ -static void ONA_A_A(upd7810_state *cpustate) +void upd7810_device::ONA_A_A() { if (A & A) PSW = (PSW & ~Z) | SK; @@ -2397,7 +2397,7 @@ static void ONA_A_A(upd7810_state *cpustate) } /* 60 ca: 0110 0000 1100 1010 */ -static void ONA_A_B(upd7810_state *cpustate) +void upd7810_device::ONA_A_B() { if (A & B) PSW = (PSW & ~Z) | SK; @@ -2406,7 +2406,7 @@ static void ONA_A_B(upd7810_state *cpustate) } /* 60 cb: 0110 0000 1100 1011 */ -static void ONA_A_C(upd7810_state *cpustate) +void upd7810_device::ONA_A_C() { if (A & C) PSW = (PSW & ~Z) | SK; @@ -2415,7 +2415,7 @@ static void ONA_A_C(upd7810_state *cpustate) } /* 60 cc: 0110 0000 1100 1100 */ -static void ONA_A_D(upd7810_state *cpustate) +void upd7810_device::ONA_A_D() { if (A & D) PSW = (PSW & ~Z) | SK; @@ -2424,7 +2424,7 @@ static void ONA_A_D(upd7810_state *cpustate) } /* 60 cd: 0110 0000 1100 1101 */ -static void ONA_A_E(upd7810_state *cpustate) +void upd7810_device::ONA_A_E() { if (A & E) PSW = (PSW & ~Z) | SK; @@ -2433,7 +2433,7 @@ static void ONA_A_E(upd7810_state *cpustate) } /* 60 ce: 0110 0000 1100 1110 */ -static void ONA_A_H(upd7810_state *cpustate) +void upd7810_device::ONA_A_H() { if (A & H) PSW = (PSW & ~Z) | SK; @@ -2442,7 +2442,7 @@ static void ONA_A_H(upd7810_state *cpustate) } /* 60 cf: 0110 0000 1100 1111 */ -static void ONA_A_L(upd7810_state *cpustate) +void upd7810_device::ONA_A_L() { if (A & L) PSW = (PSW & ~Z) | SK; @@ -2451,7 +2451,7 @@ static void ONA_A_L(upd7810_state *cpustate) } /* 60 d0: 0110 0000 1101 0000 */ -static void ADC_A_V(upd7810_state *cpustate) +void upd7810_device::ADC_A_V() { UINT8 tmp = A + V + (PSW & CY); ZHC_ADD( tmp, A, (PSW & CY) ); @@ -2462,7 +2462,7 @@ static void ADC_A_V(upd7810_state *cpustate) /* ADC_A_A already defined */ /* 60 d2: 0110 0000 1101 0010 */ -static void ADC_A_B(upd7810_state *cpustate) +void upd7810_device::ADC_A_B() { UINT8 tmp = A + B + (PSW & CY); ZHC_ADD( tmp, A, (PSW & CY) ); @@ -2470,7 +2470,7 @@ static void ADC_A_B(upd7810_state *cpustate) } /* 60 d3: 0110 0000 1101 0011 */ -static void ADC_A_C(upd7810_state *cpustate) +void upd7810_device::ADC_A_C() { UINT8 tmp = A + C + (PSW & CY); ZHC_ADD( tmp, A, (PSW & CY) ); @@ -2478,7 +2478,7 @@ static void ADC_A_C(upd7810_state *cpustate) } /* 60 d4: 0110 0000 1101 0100 */ -static void ADC_A_D(upd7810_state *cpustate) +void upd7810_device::ADC_A_D() { UINT8 tmp = A + D + (PSW & CY); ZHC_ADD( tmp, A, (PSW & CY) ); @@ -2486,7 +2486,7 @@ static void ADC_A_D(upd7810_state *cpustate) } /* 60 d5: 0110 0000 1101 0101 */ -static void ADC_A_E(upd7810_state *cpustate) +void upd7810_device::ADC_A_E() { UINT8 tmp = A + E + (PSW & CY); ZHC_ADD( tmp, A, (PSW & CY) ); @@ -2494,7 +2494,7 @@ static void ADC_A_E(upd7810_state *cpustate) } /* 60 d6: 0110 0000 1101 0110 */ -static void ADC_A_H(upd7810_state *cpustate) +void upd7810_device::ADC_A_H() { UINT8 tmp = A + H + (PSW & CY); ZHC_ADD( tmp, A, (PSW & CY) ); @@ -2502,7 +2502,7 @@ static void ADC_A_H(upd7810_state *cpustate) } /* 60 d7: 0110 0000 1101 0111 */ -static void ADC_A_L(upd7810_state *cpustate) +void upd7810_device::ADC_A_L() { UINT8 tmp = A + L + (PSW & CY); ZHC_ADD( tmp, A, (PSW & CY) ); @@ -2510,7 +2510,7 @@ static void ADC_A_L(upd7810_state *cpustate) } /* 60 d8: 0110 0000 1101 1000 */ -static void OFFA_A_V(upd7810_state *cpustate) +void upd7810_device::OFFA_A_V() { if ( A & V ) PSW &= ~Z; @@ -2519,7 +2519,7 @@ static void OFFA_A_V(upd7810_state *cpustate) } /* 60 d9: 0110 0000 1101 1001 */ -static void OFFA_A_A(upd7810_state *cpustate) +void upd7810_device::OFFA_A_A() { if ( A & A ) PSW &= ~Z; @@ -2528,7 +2528,7 @@ static void OFFA_A_A(upd7810_state *cpustate) } /* 60 da: 0110 0000 1101 1010 */ -static void OFFA_A_B(upd7810_state *cpustate) +void upd7810_device::OFFA_A_B() { if ( A & B ) PSW &= ~Z; @@ -2537,7 +2537,7 @@ static void OFFA_A_B(upd7810_state *cpustate) } /* 60 db: 0110 0000 1101 1011 */ -static void OFFA_A_C(upd7810_state *cpustate) +void upd7810_device::OFFA_A_C() { if ( A & C ) PSW &= ~Z; @@ -2546,7 +2546,7 @@ static void OFFA_A_C(upd7810_state *cpustate) } /* 60 dc: 0110 0000 1101 1100 */ -static void OFFA_A_D(upd7810_state *cpustate) +void upd7810_device::OFFA_A_D() { if ( A & D ) PSW &= ~Z; @@ -2555,7 +2555,7 @@ static void OFFA_A_D(upd7810_state *cpustate) } /* 60 dd: 0110 0000 1101 1101 */ -static void OFFA_A_E(upd7810_state *cpustate) +void upd7810_device::OFFA_A_E() { if ( A & E ) PSW &= ~Z; @@ -2564,7 +2564,7 @@ static void OFFA_A_E(upd7810_state *cpustate) } /* 60 de: 0110 0000 1101 1110 */ -static void OFFA_A_H(upd7810_state *cpustate) +void upd7810_device::OFFA_A_H() { if ( A & H ) PSW &= ~Z; @@ -2573,7 +2573,7 @@ static void OFFA_A_H(upd7810_state *cpustate) } /* 60 df: 0110 0000 1101 1111 */ -static void OFFA_A_L(upd7810_state *cpustate) +void upd7810_device::OFFA_A_L() { if ( A & L ) PSW &= ~Z; @@ -2582,7 +2582,7 @@ static void OFFA_A_L(upd7810_state *cpustate) } /* 60 e0: 0110 0000 1110 0000 */ -static void SUB_A_V(upd7810_state *cpustate) +void upd7810_device::SUB_A_V() { UINT8 tmp = A - V; ZHC_SUB( tmp, A, 0 ); @@ -2593,7 +2593,7 @@ static void SUB_A_V(upd7810_state *cpustate) /* SUB_A_A already defined */ /* 60 e2: 0110 0000 1110 0010 */ -static void SUB_A_B(upd7810_state *cpustate) +void upd7810_device::SUB_A_B() { UINT8 tmp = A - B; ZHC_SUB( tmp, A, 0 ); @@ -2601,7 +2601,7 @@ static void SUB_A_B(upd7810_state *cpustate) } /* 60 e3: 0110 0000 1110 0011 */ -static void SUB_A_C(upd7810_state *cpustate) +void upd7810_device::SUB_A_C() { UINT8 tmp = A - C; ZHC_SUB( tmp, A, 0 ); @@ -2609,7 +2609,7 @@ static void SUB_A_C(upd7810_state *cpustate) } /* 60 e4: 0110 0000 1110 0100 */ -static void SUB_A_D(upd7810_state *cpustate) +void upd7810_device::SUB_A_D() { UINT8 tmp = A - D; ZHC_SUB( tmp, A, 0 ); @@ -2617,7 +2617,7 @@ static void SUB_A_D(upd7810_state *cpustate) } /* 60 e5: 0110 0000 1110 0101 */ -static void SUB_A_E(upd7810_state *cpustate) +void upd7810_device::SUB_A_E() { UINT8 tmp = A - E; ZHC_SUB( tmp, A, 0 ); @@ -2625,7 +2625,7 @@ static void SUB_A_E(upd7810_state *cpustate) } /* 60 e6: 0110 0000 1110 0110 */ -static void SUB_A_H(upd7810_state *cpustate) +void upd7810_device::SUB_A_H() { UINT8 tmp = A - H; ZHC_SUB( tmp, A, 0 ); @@ -2633,7 +2633,7 @@ static void SUB_A_H(upd7810_state *cpustate) } /* 60 e7: 0110 0000 1110 0111 */ -static void SUB_A_L(upd7810_state *cpustate) +void upd7810_device::SUB_A_L() { UINT8 tmp = A - L; ZHC_SUB( tmp, A, 0 ); @@ -2641,7 +2641,7 @@ static void SUB_A_L(upd7810_state *cpustate) } /* 60 e8: 0110 0000 1110 1000 */ -static void NEA_A_V(upd7810_state *cpustate) +void upd7810_device::NEA_A_V() { UINT8 tmp = A - V; ZHC_SUB( tmp, A, 0 ); @@ -2652,7 +2652,7 @@ static void NEA_A_V(upd7810_state *cpustate) /* NEA_A_A already defined */ /* 60 ea: 0110 0000 1110 1010 */ -static void NEA_A_B(upd7810_state *cpustate) +void upd7810_device::NEA_A_B() { UINT8 tmp = A - B; ZHC_SUB( tmp, A, 0 ); @@ -2660,7 +2660,7 @@ static void NEA_A_B(upd7810_state *cpustate) } /* 60 eb: 0110 0000 1110 1011 */ -static void NEA_A_C(upd7810_state *cpustate) +void upd7810_device::NEA_A_C() { UINT8 tmp = A - C; ZHC_SUB( tmp, A, 0 ); @@ -2668,7 +2668,7 @@ static void NEA_A_C(upd7810_state *cpustate) } /* 60 ec: 0110 0000 1110 1100 */ -static void NEA_A_D(upd7810_state *cpustate) +void upd7810_device::NEA_A_D() { UINT8 tmp = A - D; ZHC_SUB( tmp, A, 0 ); @@ -2676,7 +2676,7 @@ static void NEA_A_D(upd7810_state *cpustate) } /* 60 ed: 0110 0000 1110 1101 */ -static void NEA_A_E(upd7810_state *cpustate) +void upd7810_device::NEA_A_E() { UINT8 tmp = A - E; ZHC_SUB( tmp, A, 0 ); @@ -2684,7 +2684,7 @@ static void NEA_A_E(upd7810_state *cpustate) } /* 60 ee: 0110 0000 1110 1110 */ -static void NEA_A_H(upd7810_state *cpustate) +void upd7810_device::NEA_A_H() { UINT8 tmp = A - H; ZHC_SUB( tmp, A, 0 ); @@ -2692,7 +2692,7 @@ static void NEA_A_H(upd7810_state *cpustate) } /* 60 ef: 0110 0000 1110 1111 */ -static void NEA_A_L(upd7810_state *cpustate) +void upd7810_device::NEA_A_L() { UINT8 tmp = A - L; ZHC_SUB( tmp, A, 0 ); @@ -2700,7 +2700,7 @@ static void NEA_A_L(upd7810_state *cpustate) } /* 60 f0: 0110 0000 1111 0000 */ -static void SBB_A_V(upd7810_state *cpustate) +void upd7810_device::SBB_A_V() { UINT8 tmp = A - V - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -2711,7 +2711,7 @@ static void SBB_A_V(upd7810_state *cpustate) /* SBB_A_A already defined */ /* 60 f2: 0110 0000 1111 0010 */ -static void SBB_A_B(upd7810_state *cpustate) +void upd7810_device::SBB_A_B() { UINT8 tmp = A - B - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -2719,7 +2719,7 @@ static void SBB_A_B(upd7810_state *cpustate) } /* 60 f3: 0110 0000 1111 0011 */ -static void SBB_A_C(upd7810_state *cpustate) +void upd7810_device::SBB_A_C() { UINT8 tmp = A - C - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -2727,7 +2727,7 @@ static void SBB_A_C(upd7810_state *cpustate) } /* 60 f4: 0110 0000 1111 0100 */ -static void SBB_A_D(upd7810_state *cpustate) +void upd7810_device::SBB_A_D() { UINT8 tmp = A - D - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -2735,7 +2735,7 @@ static void SBB_A_D(upd7810_state *cpustate) } /* 60 f5: 0110 0000 1111 0101 */ -static void SBB_A_E(upd7810_state *cpustate) +void upd7810_device::SBB_A_E() { UINT8 tmp = A - E - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -2743,7 +2743,7 @@ static void SBB_A_E(upd7810_state *cpustate) } /* 60 f6: 0110 0000 1111 0110 */ -static void SBB_A_H(upd7810_state *cpustate) +void upd7810_device::SBB_A_H() { UINT8 tmp = A - H - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -2751,7 +2751,7 @@ static void SBB_A_H(upd7810_state *cpustate) } /* 60 f7: 0110 0000 1111 0111 */ -static void SBB_A_L(upd7810_state *cpustate) +void upd7810_device::SBB_A_L() { UINT8 tmp = A - L - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -2759,7 +2759,7 @@ static void SBB_A_L(upd7810_state *cpustate) } /* 60 f8: 0110 0000 1111 1000 */ -static void EQA_A_V(upd7810_state *cpustate) +void upd7810_device::EQA_A_V() { UINT8 tmp = A - V; ZHC_SUB( tmp, A, 0 ); @@ -2770,7 +2770,7 @@ static void EQA_A_V(upd7810_state *cpustate) /* EQA_A_A already defined */ /* 60 fa: 0110 0000 1111 1010 */ -static void EQA_A_B(upd7810_state *cpustate) +void upd7810_device::EQA_A_B() { UINT8 tmp = A - B; ZHC_SUB( tmp, A, 0 ); @@ -2778,7 +2778,7 @@ static void EQA_A_B(upd7810_state *cpustate) } /* 60 fb: 0110 0000 1111 1011 */ -static void EQA_A_C(upd7810_state *cpustate) +void upd7810_device::EQA_A_C() { UINT8 tmp = A - C; ZHC_SUB( tmp, A, 0 ); @@ -2786,7 +2786,7 @@ static void EQA_A_C(upd7810_state *cpustate) } /* 60 fc: 0110 0000 1111 1100 */ -static void EQA_A_D(upd7810_state *cpustate) +void upd7810_device::EQA_A_D() { UINT8 tmp = A - D; ZHC_SUB( tmp, A, 0 ); @@ -2794,7 +2794,7 @@ static void EQA_A_D(upd7810_state *cpustate) } /* 60 fd: 0110 0000 1111 1101 */ -static void EQA_A_E(upd7810_state *cpustate) +void upd7810_device::EQA_A_E() { UINT8 tmp = A - E; ZHC_SUB( tmp, A, 0 ); @@ -2802,7 +2802,7 @@ static void EQA_A_E(upd7810_state *cpustate) } /* 60 fe: 0110 0000 1111 1110 */ -static void EQA_A_H(upd7810_state *cpustate) +void upd7810_device::EQA_A_H() { UINT8 tmp = A - H; ZHC_SUB( tmp, A, 0 ); @@ -2810,7 +2810,7 @@ static void EQA_A_H(upd7810_state *cpustate) } /* 60 ff: 0110 0000 1111 1111 */ -static void EQA_A_L(upd7810_state *cpustate) +void upd7810_device::EQA_A_L() { UINT8 tmp = A - L; ZHC_SUB( tmp, A, 0 ); @@ -2819,109 +2819,109 @@ static void EQA_A_L(upd7810_state *cpustate) /* prefix 64 */ /* 64 00: 0110 0100 0000 0000 xxxx xxxx */ -static void MVI_PA_xx(upd7810_state *cpustate) +void upd7810_device::MVI_PA_xx() { UINT8 imm; RDOPARG( imm ); - WP( cpustate, UPD7810_PORTA, imm ); + WP( UPD7810_PORTA, imm ); } /* 64 01: 0110 0100 0000 0001 xxxx xxxx */ -static void MVI_PB_xx(upd7810_state *cpustate) +void upd7810_device::MVI_PB_xx() { UINT8 imm; RDOPARG( imm ); - WP( cpustate, UPD7810_PORTB, imm ); + WP( UPD7810_PORTB, imm ); } /* 64 02: 0110 0100 0000 0010 xxxx xxxx */ -static void MVI_PC_xx(upd7810_state *cpustate) +void upd7810_device::MVI_PC_xx() { UINT8 imm; RDOPARG( imm ); - WP( cpustate, UPD7810_PORTC, imm ); + WP( UPD7810_PORTC, imm ); } /* 64 03: 0110 0100 0000 0011 xxxx xxxx */ -static void MVI_PD_xx(upd7810_state *cpustate) +void upd7810_device::MVI_PD_xx() { UINT8 imm; RDOPARG( imm ); - WP( cpustate, UPD7810_PORTD, imm ); + WP( UPD7810_PORTD, imm ); } /* 64 05: 0110 0100 0000 0101 xxxx xxxx */ -static void MVI_PF_xx(upd7810_state *cpustate) +void upd7810_device::MVI_PF_xx() { UINT8 imm; RDOPARG( imm ); - WP( cpustate, UPD7810_PORTF, imm ); + WP( UPD7810_PORTF, imm ); } /* 64 06: 0110 0100 0000 0110 xxxx xxxx */ -static void MVI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::MVI_MKH_xx() { RDOPARG( MKH ); } /* 64 07: 0110 0100 0000 0111 xxxx xxxx */ -static void MVI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::MVI_MKL_xx() { RDOPARG( MKL ); } /* 64 08: 0110 0100 0000 1000 xxxx xxxx */ -static void ANI_PA_xx(upd7810_state *cpustate) +void upd7810_device::ANI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA), imm; + UINT8 pa = RP( UPD7810_PORTA), imm; RDOPARG( imm ); pa &= imm; - WP( cpustate, UPD7810_PORTA, pa ); + WP( UPD7810_PORTA, pa ); SET_Z(pa); } /* 64 09: 0110 0100 0000 1001 xxxx xxxx */ -static void ANI_PB_xx(upd7810_state *cpustate) +void upd7810_device::ANI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB), imm; + UINT8 pb = RP( UPD7810_PORTB), imm; RDOPARG( imm ); pb &= imm; - WP( cpustate, UPD7810_PORTB, pb ); + WP( UPD7810_PORTB, pb ); SET_Z(pb); } /* 64 0a: 0110 0100 0000 1010 xxxx xxxx */ -static void ANI_PC_xx(upd7810_state *cpustate) +void upd7810_device::ANI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC), imm; + UINT8 pc = RP( UPD7810_PORTC), imm; RDOPARG( imm ); pc &= imm; - WP( cpustate, UPD7810_PORTC, pc ); + WP( UPD7810_PORTC, pc ); SET_Z(pc); } /* 64 0b: 0110 0100 0000 1011 xxxx xxxx */ -static void ANI_PD_xx(upd7810_state *cpustate) +void upd7810_device::ANI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), imm; + UINT8 pd = RP( UPD7810_PORTD ), imm; RDOPARG( imm ); pd &= imm; - WP( cpustate, UPD7810_PORTD, pd ); + WP( UPD7810_PORTD, pd ); SET_Z(pd); } /* 64 0d: 0110 0100 0000 1101 xxxx xxxx */ -static void ANI_PF_xx(upd7810_state *cpustate) +void upd7810_device::ANI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), imm; + UINT8 pf = RP( UPD7810_PORTF ), imm; RDOPARG( imm ); pf &= imm; - WP( cpustate, UPD7810_PORTF, pf ); + WP( UPD7810_PORTF, pf ); SET_Z(pf); } /* 64 0e: 0110 0100 0000 1110 xxxx xxxx */ -static void ANI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::ANI_MKH_xx() { UINT8 imm; RDOPARG( imm ); @@ -2930,7 +2930,7 @@ static void ANI_MKH_xx(upd7810_state *cpustate) } /* 64 0f: 0110 0100 0000 1111 xxxx xxxx */ -static void ANI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::ANI_MKL_xx() { UINT8 imm; RDOPARG( imm ); @@ -2939,57 +2939,57 @@ static void ANI_MKL_xx(upd7810_state *cpustate) } /* 64 10: 0110 0100 0001 0000 xxxx xxxx */ -static void XRI_PA_xx(upd7810_state *cpustate) +void upd7810_device::XRI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), imm; + UINT8 pa = RP( UPD7810_PORTA ), imm; RDOPARG( imm ); pa ^= imm; - WP( cpustate, UPD7810_PORTA, pa ); + WP( UPD7810_PORTA, pa ); SET_Z(pa); } /* 64 11: 0110 0100 0001 0001 xxxx xxxx */ -static void XRI_PB_xx(upd7810_state *cpustate) +void upd7810_device::XRI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), imm; + UINT8 pb = RP( UPD7810_PORTB ), imm; RDOPARG( imm ); pb ^= imm; - WP( cpustate, UPD7810_PORTB, pb ); + WP( UPD7810_PORTB, pb ); SET_Z(pb); } /* 64 12: 0110 0100 0001 0010 xxxx xxxx */ -static void XRI_PC_xx(upd7810_state *cpustate) +void upd7810_device::XRI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), imm; + UINT8 pc = RP( UPD7810_PORTC ), imm; RDOPARG( imm ); pc ^= imm; - WP( cpustate, UPD7810_PORTC, pc ); + WP( UPD7810_PORTC, pc ); SET_Z(pc); } /* 64 13: 0110 0100 0001 0011 xxxx xxxx */ -static void XRI_PD_xx(upd7810_state *cpustate) +void upd7810_device::XRI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), imm; + UINT8 pd = RP( UPD7810_PORTD ), imm; RDOPARG( imm ); pd ^= imm; - WP( cpustate, UPD7810_PORTD, pd ); + WP( UPD7810_PORTD, pd ); SET_Z(pd); } /* 64 15: 0110 0100 0001 0101 xxxx xxxx */ -static void XRI_PF_xx(upd7810_state *cpustate) +void upd7810_device::XRI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), imm; + UINT8 pf = RP( UPD7810_PORTF ), imm; RDOPARG( imm ); pf ^= imm; - WP( cpustate, UPD7810_PORTF, pf ); + WP( UPD7810_PORTF, pf ); SET_Z(pf); } /* 64 16: 0110 0100 0001 0110 xxxx xxxx */ -static void XRI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::XRI_MKH_xx() { UINT8 imm; RDOPARG( imm ); @@ -2998,7 +2998,7 @@ static void XRI_MKH_xx(upd7810_state *cpustate) } /* 64 17: 0110 0100 0001 0111 xxxx xxxx */ -static void XRI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::XRI_MKL_xx() { UINT8 imm; RDOPARG( imm ); @@ -3007,57 +3007,57 @@ static void XRI_MKL_xx(upd7810_state *cpustate) } /* 64 18: 0110 0100 0001 1000 xxxx xxxx */ -static void ORI_PA_xx(upd7810_state *cpustate) +void upd7810_device::ORI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), imm; + UINT8 pa = RP( UPD7810_PORTA ), imm; RDOPARG( imm ); pa |= imm; - WP( cpustate, UPD7810_PORTA, pa ); + WP( UPD7810_PORTA, pa ); SET_Z(pa); } /* 64 19: 0110 0100 0001 1001 xxxx xxxx */ -static void ORI_PB_xx(upd7810_state *cpustate) +void upd7810_device::ORI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), imm; + UINT8 pb = RP( UPD7810_PORTB ), imm; RDOPARG( imm ); pb |= imm; - WP( cpustate, UPD7810_PORTB, pb ); + WP( UPD7810_PORTB, pb ); SET_Z(pb); } /* 64 1a: 0110 0100 0001 1010 xxxx xxxx */ -static void ORI_PC_xx(upd7810_state *cpustate) +void upd7810_device::ORI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), imm; + UINT8 pc = RP( UPD7810_PORTC ), imm; RDOPARG( imm ); pc |= imm; - WP( cpustate, UPD7810_PORTC, pc ); + WP( UPD7810_PORTC, pc ); SET_Z(pc); } /* 64 1b: 0110 0100 0001 1011 xxxx xxxx */ -static void ORI_PD_xx(upd7810_state *cpustate) +void upd7810_device::ORI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), imm; + UINT8 pd = RP( UPD7810_PORTD ), imm; RDOPARG( imm ); pd |= imm; - WP( cpustate, UPD7810_PORTD, pd ); + WP( UPD7810_PORTD, pd ); SET_Z(pd); } /* 64 1d: 0110 0100 0001 1101 xxxx xxxx */ -static void ORI_PF_xx(upd7810_state *cpustate) +void upd7810_device::ORI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), imm; + UINT8 pf = RP( UPD7810_PORTF ), imm; RDOPARG( imm ); pf |= imm; - WP( cpustate, UPD7810_PORTF, pf ); + WP( UPD7810_PORTF, pf ); SET_Z(pf); } /* 64 1e: 0110 0100 0001 1110 xxxx xxxx */ -static void ORI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::ORI_MKH_xx() { UINT8 imm; RDOPARG( imm ); @@ -3066,7 +3066,7 @@ static void ORI_MKH_xx(upd7810_state *cpustate) } /* 64 1f: 0110 0100 0001 1111 xxxx xxxx */ -static void ORI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::ORI_MKL_xx() { UINT8 imm; RDOPARG( imm ); @@ -3075,77 +3075,77 @@ static void ORI_MKL_xx(upd7810_state *cpustate) } /* 64 20: 0110 0100 0010 0000 xxxx xxxx */ -static void ADINC_PA_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ); + UINT8 pa = RP( UPD7810_PORTA ); UINT8 tmp, imm; RDOPARG( imm ); tmp = pa + imm; ZHC_ADD( tmp, pa, 0 ); - WP( cpustate, UPD7810_PORTA , tmp ); + WP( UPD7810_PORTA , tmp ); SKIP_NC; } /* 64 21: 0110 0100 0010 0001 xxxx xxxx */ -static void ADINC_PB_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ); + UINT8 pb = RP( UPD7810_PORTB ); UINT8 tmp, imm; RDOPARG( imm ); tmp = pb + imm; ZHC_ADD( tmp, pb, 0 ); - WP( cpustate, UPD7810_PORTB, tmp ); + WP( UPD7810_PORTB, tmp ); SKIP_NC; } /* 64 22: 0110 0100 0010 0010 xxxx xxxx */ -static void ADINC_PC_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ); + UINT8 pc = RP( UPD7810_PORTC ); UINT8 tmp, imm; RDOPARG( imm ); tmp = pc + imm; ZHC_ADD( tmp, pc, 0 ); - WP( cpustate, UPD7810_PORTC, tmp ); + WP( UPD7810_PORTC, tmp ); SKIP_NC; } /* 64 23: 0110 0100 0010 0011 xxxx xxxx */ -static void ADINC_PD_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ); + UINT8 pd = RP( UPD7810_PORTD ); UINT8 tmp, imm; RDOPARG( imm ); tmp = pd + imm; ZHC_ADD( tmp, pd, 0 ); - WP( cpustate, UPD7810_PORTD, tmp ); + WP( UPD7810_PORTD, tmp ); SKIP_NC; } /* 64 25: 0110 0100 0010 0101 xxxx xxxx */ -static void ADINC_PF_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ); + UINT8 pf = RP( UPD7810_PORTF ); UINT8 tmp, imm; RDOPARG( imm ); tmp = pf + imm; ZHC_ADD( tmp, pf, 0 ); - WP( cpustate, UPD7810_PORTF, tmp ); + WP( UPD7810_PORTF, tmp ); SKIP_NC; } /* 64 26: 0110 0100 0010 0110 xxxx xxxx */ -static void ADINC_MKH_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_MKH_xx() { UINT8 tmp, imm; @@ -3158,7 +3158,7 @@ static void ADINC_MKH_xx(upd7810_state *cpustate) } /* 64 27: 0110 0100 0010 0111 xxxx xxxx */ -static void ADINC_MKL_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_MKL_xx() { UINT8 tmp, imm; @@ -3171,9 +3171,9 @@ static void ADINC_MKL_xx(upd7810_state *cpustate) } /* 64 28: 0110 0100 0010 1000 xxxx xxxx */ -static void GTI_PA_xx(upd7810_state *cpustate) +void upd7810_device::GTI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), imm; + UINT8 pa = RP( UPD7810_PORTA ), imm; UINT16 tmp; RDOPARG( imm ); @@ -3184,9 +3184,9 @@ static void GTI_PA_xx(upd7810_state *cpustate) } /* 64 29: 0110 0100 0010 1001 xxxx xxxx */ -static void GTI_PB_xx(upd7810_state *cpustate) +void upd7810_device::GTI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), imm; + UINT8 pb = RP( UPD7810_PORTB ), imm; UINT16 tmp; RDOPARG( imm ); @@ -3197,9 +3197,9 @@ static void GTI_PB_xx(upd7810_state *cpustate) } /* 64 2a: 0110 0100 0010 1010 xxxx xxxx */ -static void GTI_PC_xx(upd7810_state *cpustate) +void upd7810_device::GTI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), imm; + UINT8 pc = RP( UPD7810_PORTC ), imm; UINT16 tmp; RDOPARG( imm ); @@ -3210,9 +3210,9 @@ static void GTI_PC_xx(upd7810_state *cpustate) } /* 64 2b: 0110 0100 0010 1011 xxxx xxxx */ -static void GTI_PD_xx(upd7810_state *cpustate) +void upd7810_device::GTI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), imm; + UINT8 pd = RP( UPD7810_PORTD ), imm; UINT16 tmp; RDOPARG( imm ); @@ -3223,9 +3223,9 @@ static void GTI_PD_xx(upd7810_state *cpustate) } /* 64 2d: 0110 0100 0010 1101 xxxx xxxx */ -static void GTI_PF_xx(upd7810_state *cpustate) +void upd7810_device::GTI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), imm; + UINT8 pf = RP( UPD7810_PORTF ), imm; UINT16 tmp; RDOPARG( imm ); @@ -3236,7 +3236,7 @@ static void GTI_PF_xx(upd7810_state *cpustate) } /* 64 2e: 0110 0100 0010 1110 xxxx xxxx */ -static void GTI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::GTI_MKH_xx() { UINT8 imm; UINT16 tmp; @@ -3249,7 +3249,7 @@ static void GTI_MKH_xx(upd7810_state *cpustate) } /* 64 2f: 0110 0100 0010 1111 xxxx xxxx */ -static void GTI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::GTI_MKL_xx() { UINT8 imm; UINT16 tmp; @@ -3262,72 +3262,72 @@ static void GTI_MKL_xx(upd7810_state *cpustate) } /* 64 30: 0110 0100 0011 0000 xxxx xxxx */ -static void SUINB_PA_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), tmp, imm; + UINT8 pa = RP( UPD7810_PORTA ), tmp, imm; RDOPARG( imm ); tmp = pa - imm; ZHC_SUB( tmp, pa, 0 ); pa = tmp; - WP( cpustate, UPD7810_PORTA, pa ); + WP( UPD7810_PORTA, pa ); SKIP_NC; } /* 64 31: 0110 0100 0011 0001 xxxx xxxx */ -static void SUINB_PB_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), tmp, imm; + UINT8 pb = RP( UPD7810_PORTB ), tmp, imm; RDOPARG( imm ); tmp = pb - imm; ZHC_SUB( tmp, pb, 0 ); pb = tmp; - WP( cpustate, UPD7810_PORTB, pb ); + WP( UPD7810_PORTB, pb ); SKIP_NC; } /* 64 32: 0110 0100 0011 0010 xxxx xxxx */ -static void SUINB_PC_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), tmp, imm; + UINT8 pc = RP( UPD7810_PORTC ), tmp, imm; RDOPARG( imm ); tmp = pc - imm; ZHC_SUB( tmp, pc, 0 ); pc = tmp; - WP( cpustate, UPD7810_PORTC, pc ); + WP( UPD7810_PORTC, pc ); SKIP_NC; } /* 64 33: 0110 0100 0011 0011 xxxx xxxx */ -static void SUINB_PD_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), tmp, imm; + UINT8 pd = RP( UPD7810_PORTD ), tmp, imm; RDOPARG( imm ); tmp = pd - imm; ZHC_SUB( tmp, pd, 0 ); pd = tmp; - WP( cpustate, UPD7810_PORTD, pd ); + WP( UPD7810_PORTD, pd ); SKIP_NC; } /* 64 35: 0110 0100 0011 0101 xxxx xxxx */ -static void SUINB_PF_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), tmp, imm; + UINT8 pf = RP( UPD7810_PORTF ), tmp, imm; RDOPARG( imm ); tmp = pf - imm; ZHC_SUB( tmp, pf, 0 ); pf = tmp; - WP( cpustate, UPD7810_PORTF, pf ); + WP( UPD7810_PORTF, pf ); SKIP_NC; } /* 64 36: 0110 0100 0011 0110 xxxx xxxx */ -static void SUINB_MKH_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_MKH_xx() { UINT8 tmp, imm; @@ -3339,7 +3339,7 @@ static void SUINB_MKH_xx(upd7810_state *cpustate) } /* 64 37: 0110 0100 0011 0111 xxxx xxxx */ -static void SUINB_MKL_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_MKL_xx() { UINT8 tmp, imm; @@ -3351,9 +3351,9 @@ static void SUINB_MKL_xx(upd7810_state *cpustate) } /* 64 38: 0110 0100 0011 1000 xxxx xxxx */ -static void LTI_PA_xx(upd7810_state *cpustate) +void upd7810_device::LTI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), tmp, imm; + UINT8 pa = RP( UPD7810_PORTA ), tmp, imm; RDOPARG( imm ); tmp = pa - imm; ZHC_SUB( tmp, pa, 0 ); @@ -3361,9 +3361,9 @@ static void LTI_PA_xx(upd7810_state *cpustate) } /* 64 39: 0110 0100 0011 1001 xxxx xxxx */ -static void LTI_PB_xx(upd7810_state *cpustate) +void upd7810_device::LTI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), tmp, imm; + UINT8 pb = RP( UPD7810_PORTB ), tmp, imm; RDOPARG( imm ); tmp = pb - imm; ZHC_SUB( tmp, pb, 0 ); @@ -3371,9 +3371,9 @@ static void LTI_PB_xx(upd7810_state *cpustate) } /* 64 3a: 0110 0100 0011 1010 xxxx xxxx */ -static void LTI_PC_xx(upd7810_state *cpustate) +void upd7810_device::LTI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), tmp, imm; + UINT8 pc = RP( UPD7810_PORTC ), tmp, imm; RDOPARG( imm ); tmp = pc - imm; ZHC_SUB( tmp, pc, 0 ); @@ -3381,9 +3381,9 @@ static void LTI_PC_xx(upd7810_state *cpustate) } /* 64 3b: 0110 0100 0011 1011 xxxx xxxx */ -static void LTI_PD_xx(upd7810_state *cpustate) +void upd7810_device::LTI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), tmp, imm; + UINT8 pd = RP( UPD7810_PORTD ), tmp, imm; RDOPARG( imm ); tmp = pd - imm; ZHC_SUB( tmp, pd, 0 ); @@ -3391,9 +3391,9 @@ static void LTI_PD_xx(upd7810_state *cpustate) } /* 64 3d: 0110 0100 0011 1101 xxxx xxxx */ -static void LTI_PF_xx(upd7810_state *cpustate) +void upd7810_device::LTI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), tmp, imm; + UINT8 pf = RP( UPD7810_PORTF ), tmp, imm; RDOPARG( imm ); tmp = pf - imm; ZHC_SUB( tmp, pf, 0 ); @@ -3401,7 +3401,7 @@ static void LTI_PF_xx(upd7810_state *cpustate) } /* 64 3e: 0110 0100 0011 1110 xxxx xxxx */ -static void LTI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::LTI_MKH_xx() { UINT8 tmp, imm; @@ -3412,7 +3412,7 @@ static void LTI_MKH_xx(upd7810_state *cpustate) } /* 64 3f: 0110 0100 0011 1111 xxxx xxxx */ -static void LTI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::LTI_MKL_xx() { UINT8 tmp, imm; @@ -3423,67 +3423,67 @@ static void LTI_MKL_xx(upd7810_state *cpustate) } /* 64 40: 0110 0100 0100 0000 xxxx xxxx */ -static void ADI_PA_xx(upd7810_state *cpustate) +void upd7810_device::ADI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), tmp, imm; + UINT8 pa = RP( UPD7810_PORTA ), tmp, imm; RDOPARG( imm ); tmp = pa + imm; ZHC_ADD( tmp, pa, 0 ); pa = tmp; - WP( cpustate, UPD7810_PORTA, pa ); + WP( UPD7810_PORTA, pa ); } /* 64 41: 0110 0100 0100 0001 xxxx xxxx */ -static void ADI_PB_xx(upd7810_state *cpustate) +void upd7810_device::ADI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), tmp, imm; + UINT8 pb = RP( UPD7810_PORTB ), tmp, imm; RDOPARG( imm ); tmp = pb + imm; ZHC_ADD( tmp, pb, 0 ); pb = tmp; - WP( cpustate, UPD7810_PORTB, pb ); + WP( UPD7810_PORTB, pb ); } /* 64 42: 0110 0100 0100 0010 xxxx xxxx */ -static void ADI_PC_xx(upd7810_state *cpustate) +void upd7810_device::ADI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), tmp, imm; + UINT8 pc = RP( UPD7810_PORTC ), tmp, imm; RDOPARG( imm ); tmp = pc + imm; ZHC_ADD( tmp, pc, 0 ); pc = tmp; - WP( cpustate, UPD7810_PORTC, pc ); + WP( UPD7810_PORTC, pc ); } /* 64 43: 0110 0100 0100 0011 xxxx xxxx */ -static void ADI_PD_xx(upd7810_state *cpustate) +void upd7810_device::ADI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), tmp, imm; + UINT8 pd = RP( UPD7810_PORTD ), tmp, imm; RDOPARG( imm ); tmp = pd + imm; ZHC_ADD( tmp, pd, 0 ); pd = tmp; - WP( cpustate, UPD7810_PORTD, pd ); + WP( UPD7810_PORTD, pd ); } /* 64 45: 0110 0100 0100 0101 xxxx xxxx */ -static void ADI_PF_xx(upd7810_state *cpustate) +void upd7810_device::ADI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), tmp, imm; + UINT8 pf = RP( UPD7810_PORTF ), tmp, imm; RDOPARG( imm ); tmp = pf + imm; ZHC_ADD( tmp, pf, 0 ); pf = tmp; - WP( cpustate, UPD7810_PORTF, pf ); + WP( UPD7810_PORTF, pf ); } /* 64 46: 0110 0100 0100 0110 xxxx xxxx */ -static void ADI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::ADI_MKH_xx() { UINT8 tmp, imm; @@ -3494,7 +3494,7 @@ static void ADI_MKH_xx(upd7810_state *cpustate) } /* 64 47: 0110 0100 0100 0111 xxxx xxxx */ -static void ADI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::ADI_MKL_xx() { UINT8 tmp, imm; @@ -3505,9 +3505,9 @@ static void ADI_MKL_xx(upd7810_state *cpustate) } /* 64 48: 0110 0100 0100 1000 xxxx xxxx */ -static void ONI_PA_xx(upd7810_state *cpustate) +void upd7810_device::ONI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), imm; + UINT8 pa = RP( UPD7810_PORTA ), imm; RDOPARG( imm ); if (pa & imm) @@ -3515,9 +3515,9 @@ static void ONI_PA_xx(upd7810_state *cpustate) } /* 64 49: 0110 0100 0100 1001 xxxx xxxx */ -static void ONI_PB_xx(upd7810_state *cpustate) +void upd7810_device::ONI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), imm; + UINT8 pb = RP( UPD7810_PORTB ), imm; RDOPARG( imm ); if (pb & imm) @@ -3525,9 +3525,9 @@ static void ONI_PB_xx(upd7810_state *cpustate) } /* 64 4a: 0110 0100 0100 1010 xxxx xxxx */ -static void ONI_PC_xx(upd7810_state *cpustate) +void upd7810_device::ONI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), imm; + UINT8 pc = RP( UPD7810_PORTC ), imm; RDOPARG( imm ); if (pc & imm) @@ -3535,9 +3535,9 @@ static void ONI_PC_xx(upd7810_state *cpustate) } /* 64 4b: 0110 0100 0100 1011 xxxx xxxx */ -static void ONI_PD_xx(upd7810_state *cpustate) +void upd7810_device::ONI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), imm; + UINT8 pd = RP( UPD7810_PORTD ), imm; RDOPARG( imm ); if (pd & imm) @@ -3545,9 +3545,9 @@ static void ONI_PD_xx(upd7810_state *cpustate) } /* 64 4d: 0110 0100 0100 1101 xxxx xxxx */ -static void ONI_PF_xx(upd7810_state *cpustate) +void upd7810_device::ONI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), imm; + UINT8 pf = RP( UPD7810_PORTF ), imm; RDOPARG( imm ); if (pf & imm) @@ -3555,7 +3555,7 @@ static void ONI_PF_xx(upd7810_state *cpustate) } /* 64 4e: 0110 0100 0100 1110 xxxx xxxx */ -static void ONI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::ONI_MKH_xx() { UINT8 imm; @@ -3565,7 +3565,7 @@ static void ONI_MKH_xx(upd7810_state *cpustate) } /* 64 4f: 0110 0100 0100 1111 xxxx xxxx */ -static void ONI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::ONI_MKL_xx() { UINT8 imm; @@ -3575,67 +3575,67 @@ static void ONI_MKL_xx(upd7810_state *cpustate) } /* 64 50: 0110 0100 0101 0000 xxxx xxxx */ -static void ACI_PA_xx(upd7810_state *cpustate) +void upd7810_device::ACI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), tmp, imm; + UINT8 pa = RP( UPD7810_PORTA ), tmp, imm; RDOPARG( imm ); tmp = pa + imm + (PSW & CY); ZHC_ADD( tmp, pa, (PSW & CY) ); pa = tmp; - WP( cpustate, UPD7810_PORTA, pa ); + WP( UPD7810_PORTA, pa ); } /* 64 51: 0110 0100 0101 0001 xxxx xxxx */ -static void ACI_PB_xx(upd7810_state *cpustate) +void upd7810_device::ACI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), tmp, imm; + UINT8 pb = RP( UPD7810_PORTB ), tmp, imm; RDOPARG( imm ); tmp = pb + imm + (PSW & CY); ZHC_ADD( tmp, pb, (PSW & CY) ); pb = tmp; - WP( cpustate, UPD7810_PORTB, pb ); + WP( UPD7810_PORTB, pb ); } /* 64 52: 0110 0100 0101 0010 xxxx xxxx */ -static void ACI_PC_xx(upd7810_state *cpustate) +void upd7810_device::ACI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), tmp, imm; + UINT8 pc = RP( UPD7810_PORTC ), tmp, imm; RDOPARG( imm ); tmp = pc + imm + (PSW & CY); ZHC_ADD( tmp, pc, (PSW & CY) ); pc = tmp; - WP( cpustate, UPD7810_PORTC, pc ); + WP( UPD7810_PORTC, pc ); } /* 64 53: 0110 0100 0101 0011 xxxx xxxx */ -static void ACI_PD_xx(upd7810_state *cpustate) +void upd7810_device::ACI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), tmp, imm; + UINT8 pd = RP( UPD7810_PORTD ), tmp, imm; RDOPARG( imm ); tmp = pd + imm + (PSW & CY); ZHC_ADD( tmp, pd, (PSW & CY) ); pd = tmp; - WP( cpustate, UPD7810_PORTD, pd ); + WP( UPD7810_PORTD, pd ); } /* 64 55: 0110 0100 0101 0101 xxxx xxxx */ -static void ACI_PF_xx(upd7810_state *cpustate) +void upd7810_device::ACI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), tmp, imm; + UINT8 pf = RP( UPD7810_PORTF ), tmp, imm; RDOPARG( imm ); tmp = pf + imm + (PSW & CY); ZHC_ADD( tmp, pf, (PSW & CY) ); pf = tmp; - WP( cpustate, UPD7810_PORTF, pf ); + WP( UPD7810_PORTF, pf ); } /* 64 56: 0110 0100 0101 0110 xxxx xxxx */ -static void ACI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::ACI_MKH_xx() { UINT8 imm, tmp; @@ -3646,7 +3646,7 @@ static void ACI_MKH_xx(upd7810_state *cpustate) } /* 64 57: 0110 0100 0101 0111 xxxx xxxx */ -static void ACI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::ACI_MKL_xx() { UINT8 imm, tmp; @@ -3657,9 +3657,9 @@ static void ACI_MKL_xx(upd7810_state *cpustate) } /* 64 58: 0110 0100 0101 1000 xxxx xxxx */ -static void OFFI_PA_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), imm; + UINT8 pa = RP( UPD7810_PORTA ), imm; RDOPARG( imm ); if (0 == (pa & imm)) @@ -3667,9 +3667,9 @@ static void OFFI_PA_xx(upd7810_state *cpustate) } /* 64 59: 0110 0100 0101 1001 xxxx xxxx */ -static void OFFI_PB_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), imm; + UINT8 pb = RP( UPD7810_PORTB ), imm; RDOPARG( imm ); if (0 == (pb & imm)) @@ -3677,9 +3677,9 @@ static void OFFI_PB_xx(upd7810_state *cpustate) } /* 64 5a: 0110 0100 0101 1010 xxxx xxxx */ -static void OFFI_PC_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), imm; + UINT8 pc = RP( UPD7810_PORTC ), imm; RDOPARG( imm ); if (0 == (pc & imm)) @@ -3687,9 +3687,9 @@ static void OFFI_PC_xx(upd7810_state *cpustate) } /* 64 5b: 0110 0100 0101 1011 xxxx xxxx */ -static void OFFI_PD_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), imm; + UINT8 pd = RP( UPD7810_PORTD ), imm; RDOPARG( imm ); if (0 == (pd & imm)) @@ -3697,9 +3697,9 @@ static void OFFI_PD_xx(upd7810_state *cpustate) } /* 64 5d: 0110 0100 0101 1101 xxxx xxxx */ -static void OFFI_PF_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), imm; + UINT8 pf = RP( UPD7810_PORTF ), imm; RDOPARG( imm ); if (0 == (pf & imm)) @@ -3707,7 +3707,7 @@ static void OFFI_PF_xx(upd7810_state *cpustate) } /* 64 5e: 0110 0100 0101 1110 xxxx xxxx */ -static void OFFI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_MKH_xx() { UINT8 imm; @@ -3717,7 +3717,7 @@ static void OFFI_MKH_xx(upd7810_state *cpustate) } /* 64 5f: 0110 0100 0101 1111 xxxx xxxx */ -static void OFFI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_MKL_xx() { UINT8 imm; @@ -3727,67 +3727,67 @@ static void OFFI_MKL_xx(upd7810_state *cpustate) } /* 64 60: 0110 0100 0110 0000 xxxx xxxx */ -static void SUI_PA_xx(upd7810_state *cpustate) +void upd7810_device::SUI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), tmp, imm; + UINT8 pa = RP( UPD7810_PORTA ), tmp, imm; RDOPARG( imm ); tmp = pa - imm; ZHC_SUB( tmp, pa, 0 ); pa = tmp; - WP( cpustate, UPD7810_PORTA, pa ); + WP( UPD7810_PORTA, pa ); } /* 64 61: 0110 0100 0110 0001 xxxx xxxx */ -static void SUI_PB_xx(upd7810_state *cpustate) +void upd7810_device::SUI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), tmp, imm; + UINT8 pb = RP( UPD7810_PORTB ), tmp, imm; RDOPARG( imm ); tmp = pb - imm; ZHC_SUB( tmp, pb, 0 ); pb = tmp; - WP( cpustate, UPD7810_PORTB, pb ); + WP( UPD7810_PORTB, pb ); } /* 64 62: 0110 0100 0110 0010 xxxx xxxx */ -static void SUI_PC_xx(upd7810_state *cpustate) +void upd7810_device::SUI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), tmp, imm; + UINT8 pc = RP( UPD7810_PORTC ), tmp, imm; RDOPARG( imm ); tmp = pc - imm; ZHC_SUB( tmp, pc, 0 ); pc = tmp; - WP( cpustate, UPD7810_PORTC, pc ); + WP( UPD7810_PORTC, pc ); } /* 64 63: 0110 0100 0110 0011 xxxx xxxx */ -static void SUI_PD_xx(upd7810_state *cpustate) +void upd7810_device::SUI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), tmp, imm; + UINT8 pd = RP( UPD7810_PORTD ), tmp, imm; RDOPARG( imm ); tmp = pd - imm; ZHC_SUB( tmp, pd, 0 ); pd = tmp; - WP( cpustate, UPD7810_PORTD, pd ); + WP( UPD7810_PORTD, pd ); } /* 64 65: 0110 0100 0110 0101 xxxx xxxx */ -static void SUI_PF_xx(upd7810_state *cpustate) +void upd7810_device::SUI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), tmp, imm; + UINT8 pf = RP( UPD7810_PORTF ), tmp, imm; RDOPARG( imm ); tmp = pf - imm; ZHC_SUB( tmp, pf, 0 ); pf = tmp; - WP( cpustate, UPD7810_PORTF, pf ); + WP( UPD7810_PORTF, pf ); } /* 64 66: 0110 0100 0110 0110 xxxx xxxx */ -static void SUI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::SUI_MKH_xx() { UINT8 tmp, imm; @@ -3798,7 +3798,7 @@ static void SUI_MKH_xx(upd7810_state *cpustate) } /* 64 67: 0110 0100 0110 0111 xxxx xxxx */ -static void SUI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::SUI_MKL_xx() { UINT8 tmp, imm; @@ -3809,9 +3809,9 @@ static void SUI_MKL_xx(upd7810_state *cpustate) } /* 64 68: 0110 0100 0110 1000 xxxx xxxx */ -static void NEI_PA_xx(upd7810_state *cpustate) +void upd7810_device::NEI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), tmp, imm; + UINT8 pa = RP( UPD7810_PORTA ), tmp, imm; RDOPARG( imm ); tmp = pa - imm; @@ -3820,9 +3820,9 @@ static void NEI_PA_xx(upd7810_state *cpustate) } /* 64 69: 0110 0100 0110 1001 xxxx xxxx */ -static void NEI_PB_xx(upd7810_state *cpustate) +void upd7810_device::NEI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), tmp, imm; + UINT8 pb = RP( UPD7810_PORTB ), tmp, imm; RDOPARG( imm ); tmp = pb - imm; @@ -3831,9 +3831,9 @@ static void NEI_PB_xx(upd7810_state *cpustate) } /* 64 6a: 0110 0100 0110 1010 xxxx xxxx */ -static void NEI_PC_xx(upd7810_state *cpustate) +void upd7810_device::NEI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), tmp, imm; + UINT8 pc = RP( UPD7810_PORTC ), tmp, imm; RDOPARG( imm ); tmp = pc - imm; @@ -3842,9 +3842,9 @@ static void NEI_PC_xx(upd7810_state *cpustate) } /* 64 6b: 0110 0100 0110 1011 xxxx xxxx */ -static void NEI_PD_xx(upd7810_state *cpustate) +void upd7810_device::NEI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), tmp, imm; + UINT8 pd = RP( UPD7810_PORTD ), tmp, imm; RDOPARG( imm ); tmp = pd - imm; @@ -3853,9 +3853,9 @@ static void NEI_PD_xx(upd7810_state *cpustate) } /* 64 6d: 0110 0100 0110 1101 xxxx xxxx */ -static void NEI_PF_xx(upd7810_state *cpustate) +void upd7810_device::NEI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), tmp, imm; + UINT8 pf = RP( UPD7810_PORTF ), tmp, imm; RDOPARG( imm ); tmp = pf - imm; @@ -3864,7 +3864,7 @@ static void NEI_PF_xx(upd7810_state *cpustate) } /* 64 6e: 0110 0100 0110 1110 xxxx xxxx */ -static void NEI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::NEI_MKH_xx() { UINT8 tmp, imm; @@ -3875,7 +3875,7 @@ static void NEI_MKH_xx(upd7810_state *cpustate) } /* 64 6f: 0110 0100 0110 1111 xxxx xxxx */ -static void NEI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::NEI_MKL_xx() { UINT8 tmp, imm; @@ -3886,67 +3886,67 @@ static void NEI_MKL_xx(upd7810_state *cpustate) } /* 64 70: 0110 0100 0111 0000 xxxx xxxx */ -static void SBI_PA_xx(upd7810_state *cpustate) +void upd7810_device::SBI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), tmp, imm; + UINT8 pa = RP( UPD7810_PORTA ), tmp, imm; RDOPARG( imm ); tmp = pa - imm - (PSW & CY); ZHC_SUB( tmp, pa, (PSW & CY) ); pa = tmp; - WP( cpustate, UPD7810_PORTA, pa ); + WP( UPD7810_PORTA, pa ); } /* 64 71: 0110 0100 0111 0001 xxxx xxxx */ -static void SBI_PB_xx(upd7810_state *cpustate) +void upd7810_device::SBI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), tmp, imm; + UINT8 pb = RP( UPD7810_PORTB ), tmp, imm; RDOPARG( imm ); tmp = pb - imm - (PSW & CY); ZHC_SUB( tmp, pb, (PSW & CY) ); pb = tmp; - WP( cpustate, UPD7810_PORTB, pb ); + WP( UPD7810_PORTB, pb ); } /* 64 72: 0110 0100 0111 0010 xxxx xxxx */ -static void SBI_PC_xx(upd7810_state *cpustate) +void upd7810_device::SBI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), tmp, imm; + UINT8 pc = RP( UPD7810_PORTC ), tmp, imm; RDOPARG( imm ); tmp = pc - imm - (PSW & CY); ZHC_SUB( tmp, pc, (PSW & CY) ); pc = tmp; - WP( cpustate, UPD7810_PORTC, pc ); + WP( UPD7810_PORTC, pc ); } /* 64 73: 0110 0100 0111 0011 xxxx xxxx */ -static void SBI_PD_xx(upd7810_state *cpustate) +void upd7810_device::SBI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), tmp, imm; + UINT8 pd = RP( UPD7810_PORTD ), tmp, imm; RDOPARG( imm ); tmp = pd - imm - (PSW & CY); ZHC_SUB( tmp, pd, (PSW & CY) ); pd = tmp; - WP( cpustate, UPD7810_PORTD, pd ); + WP( UPD7810_PORTD, pd ); } /* 64 75: 0110 0100 0111 0101 xxxx xxxx */ -static void SBI_PF_xx(upd7810_state *cpustate) +void upd7810_device::SBI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), tmp, imm; + UINT8 pf = RP( UPD7810_PORTF ), tmp, imm; RDOPARG( imm ); tmp = pf - imm - (PSW & CY); ZHC_SUB( tmp, pf, (PSW & CY) ); pf = tmp; - WP( cpustate, UPD7810_PORTF, pf ); + WP( UPD7810_PORTF, pf ); } /* 64 76: 0110 0100 0111 0110 xxxx xxxx */ -static void SBI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::SBI_MKH_xx() { UINT8 tmp, imm; @@ -3957,7 +3957,7 @@ static void SBI_MKH_xx(upd7810_state *cpustate) } /* 64 77: 0110 0100 0111 0111 xxxx xxxx */ -static void SBI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::SBI_MKL_xx() { UINT8 tmp, imm; @@ -3968,9 +3968,9 @@ static void SBI_MKL_xx(upd7810_state *cpustate) } /* 64 78: 0110 0100 0111 1000 xxxx xxxx */ -static void EQI_PA_xx(upd7810_state *cpustate) +void upd7810_device::EQI_PA_xx() { - UINT8 pa = RP( cpustate, UPD7810_PORTA ), tmp, imm; + UINT8 pa = RP( UPD7810_PORTA ), tmp, imm; RDOPARG( imm ); tmp = pa - imm; @@ -3979,9 +3979,9 @@ static void EQI_PA_xx(upd7810_state *cpustate) } /* 64 79: 0110 0100 0111 1001 xxxx xxxx */ -static void EQI_PB_xx(upd7810_state *cpustate) +void upd7810_device::EQI_PB_xx() { - UINT8 pb = RP( cpustate, UPD7810_PORTB ), tmp, imm; + UINT8 pb = RP( UPD7810_PORTB ), tmp, imm; RDOPARG( imm ); tmp = pb - imm; @@ -3990,9 +3990,9 @@ static void EQI_PB_xx(upd7810_state *cpustate) } /* 64 7a: 0110 0100 0111 1010 xxxx xxxx */ -static void EQI_PC_xx(upd7810_state *cpustate) +void upd7810_device::EQI_PC_xx() { - UINT8 pc = RP( cpustate, UPD7810_PORTC ), tmp, imm; + UINT8 pc = RP( UPD7810_PORTC ), tmp, imm; RDOPARG( imm ); tmp = pc - imm; @@ -4001,9 +4001,9 @@ static void EQI_PC_xx(upd7810_state *cpustate) } /* 64 7b: 0110 0100 0111 1011 xxxx xxxx */ -static void EQI_PD_xx(upd7810_state *cpustate) +void upd7810_device::EQI_PD_xx() { - UINT8 pd = RP( cpustate, UPD7810_PORTD ), tmp, imm; + UINT8 pd = RP( UPD7810_PORTD ), tmp, imm; RDOPARG( imm ); tmp = pd - imm; @@ -4012,9 +4012,9 @@ static void EQI_PD_xx(upd7810_state *cpustate) } /* 64 7d: 0110 0100 0111 1101 xxxx xxxx */ -static void EQI_PF_xx(upd7810_state *cpustate) +void upd7810_device::EQI_PF_xx() { - UINT8 pf = RP( cpustate, UPD7810_PORTF ), tmp, imm; + UINT8 pf = RP( UPD7810_PORTF ), tmp, imm; RDOPARG( imm ); tmp = pf - imm; @@ -4023,7 +4023,7 @@ static void EQI_PF_xx(upd7810_state *cpustate) } /* 64 7e: 0110 0100 0111 1110 xxxx xxxx */ -static void EQI_MKH_xx(upd7810_state *cpustate) +void upd7810_device::EQI_MKH_xx() { UINT8 tmp, imm; @@ -4034,7 +4034,7 @@ static void EQI_MKH_xx(upd7810_state *cpustate) } /* 64 7f: 0110 0100 0111 1111 xxxx xxxx */ -static void EQI_MKL_xx(upd7810_state *cpustate) +void upd7810_device::EQI_MKL_xx() { UINT8 tmp, imm; @@ -4045,32 +4045,32 @@ static void EQI_MKL_xx(upd7810_state *cpustate) } /* 64 80: 0110 0100 1000 0000 xxxx xxxx */ -static void MVI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::MVI_ANM_xx() { RDOPARG( ANM ); } /* 64 81: 0110 0100 1000 0001 xxxx xxxx */ -static void MVI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::MVI_SMH_xx() { RDOPARG( SMH ); } /* 64 83: 0110 0100 1000 0011 xxxx xxxx */ -static void MVI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::MVI_EOM_xx() { RDOPARG( EOM ); - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 85: 0110 0100 1000 0101 xxxx xxxx */ -static void MVI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::MVI_TMM_xx() { RDOPARG( TMM ); } /* 64 88: 0110 0100 1000 1000 xxxx xxxx */ -static void ANI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::ANI_ANM_xx() { UINT8 imm; @@ -4080,7 +4080,7 @@ static void ANI_ANM_xx(upd7810_state *cpustate) } /* 64 89: 0110 0100 1000 1001 xxxx xxxx */ -static void ANI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::ANI_SMH_xx() { UINT8 imm; @@ -4090,7 +4090,7 @@ static void ANI_SMH_xx(upd7810_state *cpustate) } /* 64 8b: 0110 0100 1000 1011 xxxx xxxx */ -static void ANI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::ANI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4100,11 +4100,11 @@ static void ANI_EOM_xx(upd7810_state *cpustate) /* only bits #1 and #5 can be read */ EOM = eom & imm; SET_Z(EOM); - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 8d: 0110 0100 1000 1101 xxxx xxxx */ -static void ANI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::ANI_TMM_xx() { UINT8 imm; @@ -4114,7 +4114,7 @@ static void ANI_TMM_xx(upd7810_state *cpustate) } /* 64 90: 0110 0100 1001 0000 xxxx xxxx */ -static void XRI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::XRI_ANM_xx() { UINT8 imm; @@ -4124,7 +4124,7 @@ static void XRI_ANM_xx(upd7810_state *cpustate) } /* 64 91: 0110 0100 1001 0001 xxxx xxxx */ -static void XRI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::XRI_SMH_xx() { UINT8 imm; @@ -4134,7 +4134,7 @@ static void XRI_SMH_xx(upd7810_state *cpustate) } /* 64 93: 0110 0100 1001 0011 xxxx xxxx */ -static void XRI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::XRI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4144,11 +4144,11 @@ static void XRI_EOM_xx(upd7810_state *cpustate) /* only bits #1 and #5 can be read */ EOM = eom ^ imm; SET_Z(EOM); - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 95: 0110 0100 1001 0101 xxxx xxxx */ -static void XRI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::XRI_TMM_xx() { UINT8 imm; @@ -4158,7 +4158,7 @@ static void XRI_TMM_xx(upd7810_state *cpustate) } /* 64 98: 0110 0100 1001 1000 xxxx xxxx */ -static void ORI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::ORI_ANM_xx() { UINT8 imm; @@ -4168,7 +4168,7 @@ static void ORI_ANM_xx(upd7810_state *cpustate) } /* 64 99: 0110 0100 1001 1001 xxxx xxxx */ -static void ORI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::ORI_SMH_xx() { UINT8 imm; @@ -4178,7 +4178,7 @@ static void ORI_SMH_xx(upd7810_state *cpustate) } /* 64 9b: 0110 0100 1001 1011 xxxx xxxx */ -static void ORI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::ORI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4188,11 +4188,11 @@ static void ORI_EOM_xx(upd7810_state *cpustate) /* only bits #1 and #5 can be read */ EOM = eom | imm; SET_Z(EOM); - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 9d: 0110 0100 1001 1101 xxxx xxxx */ -static void ORI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::ORI_TMM_xx() { UINT8 imm; @@ -4202,7 +4202,7 @@ static void ORI_TMM_xx(upd7810_state *cpustate) } /* 64 a0: 0110 0100 1010 0000 xxxx xxxx */ -static void ADINC_ANM_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_ANM_xx() { UINT8 tmp, imm; @@ -4215,7 +4215,7 @@ static void ADINC_ANM_xx(upd7810_state *cpustate) } /* 64 a1: 0110 0100 1010 0001 xxxx xxxx */ -static void ADINC_SMH_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_SMH_xx() { UINT8 tmp, imm; @@ -4228,7 +4228,7 @@ static void ADINC_SMH_xx(upd7810_state *cpustate) } /* 64 a3: 0110 0100 1010 0011 xxxx xxxx */ -static void ADINC_EOM_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4241,11 +4241,11 @@ static void ADINC_EOM_xx(upd7810_state *cpustate) ZHC_ADD( tmp, eom, 0 ); EOM = tmp; SKIP_NC; - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 a5: 0110 0100 1010 0101 xxxx xxxx */ -static void ADINC_TMM_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_TMM_xx() { UINT8 tmp, imm; @@ -4258,7 +4258,7 @@ static void ADINC_TMM_xx(upd7810_state *cpustate) } /* 64 a8: 0110 0100 1010 1000 xxxx xxxx */ -static void GTI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::GTI_ANM_xx() { UINT8 imm; UINT16 tmp; @@ -4271,7 +4271,7 @@ static void GTI_ANM_xx(upd7810_state *cpustate) } /* 64 a9: 0110 0100 1010 1001 xxxx xxxx */ -static void GTI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::GTI_SMH_xx() { UINT8 imm; UINT16 tmp; @@ -4284,7 +4284,7 @@ static void GTI_SMH_xx(upd7810_state *cpustate) } /* 64 ab: 0110 0100 1010 1011 xxxx xxxx */ -static void GTI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::GTI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4299,7 +4299,7 @@ static void GTI_EOM_xx(upd7810_state *cpustate) } /* 64 ad: 0110 0100 1010 1101 xxxx xxxx */ -static void GTI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::GTI_TMM_xx() { UINT8 imm; UINT16 tmp; @@ -4312,7 +4312,7 @@ static void GTI_TMM_xx(upd7810_state *cpustate) } /* 64 b0: 0110 0100 1011 0000 xxxx xxxx */ -static void SUINB_ANM_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_ANM_xx() { UINT8 tmp, imm; @@ -4324,7 +4324,7 @@ static void SUINB_ANM_xx(upd7810_state *cpustate) } /* 64 b1: 0110 0100 1011 0001 xxxx xxxx */ -static void SUINB_SMH_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_SMH_xx() { UINT8 tmp, imm; @@ -4336,7 +4336,7 @@ static void SUINB_SMH_xx(upd7810_state *cpustate) } /* 64 b3: 0110 0100 1011 0011 xxxx xxxx */ -static void SUINB_EOM_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4347,11 +4347,11 @@ static void SUINB_EOM_xx(upd7810_state *cpustate) ZHC_SUB( tmp, eom, 0 ); EOM = tmp; SKIP_NC; - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 b5: 0110 0100 1011 0101 xxxx xxxx */ -static void SUINB_TMM_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_TMM_xx() { UINT8 tmp, imm; @@ -4363,7 +4363,7 @@ static void SUINB_TMM_xx(upd7810_state *cpustate) } /* 64 b8: 0110 0100 1011 1000 xxxx xxxx */ -static void LTI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::LTI_ANM_xx() { UINT8 tmp, imm; @@ -4374,7 +4374,7 @@ static void LTI_ANM_xx(upd7810_state *cpustate) } /* 64 b9: 0110 0100 1011 1001 xxxx xxxx */ -static void LTI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::LTI_SMH_xx() { UINT8 tmp, imm; @@ -4385,7 +4385,7 @@ static void LTI_SMH_xx(upd7810_state *cpustate) } /* 64 bb: 0110 0100 1011 1011 xxxx xxxx */ -static void LTI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::LTI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4398,7 +4398,7 @@ static void LTI_EOM_xx(upd7810_state *cpustate) } /* 64 bd: 0110 0100 1011 1101 xxxx xxxx */ -static void LTI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::LTI_TMM_xx() { UINT8 tmp, imm; @@ -4409,7 +4409,7 @@ static void LTI_TMM_xx(upd7810_state *cpustate) } /* 64 c0: 0110 0100 1100 0000 xxxx xxxx */ -static void ADI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::ADI_ANM_xx() { UINT8 tmp, imm; @@ -4421,7 +4421,7 @@ static void ADI_ANM_xx(upd7810_state *cpustate) } /* 64 c1: 0110 0100 1100 0001 xxxx xxxx */ -static void ADI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::ADI_SMH_xx() { UINT8 tmp, imm; @@ -4433,7 +4433,7 @@ static void ADI_SMH_xx(upd7810_state *cpustate) } /* 64 c3: 0110 0100 1100 0011 xxxx xxxx */ -static void ADI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::ADI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4444,11 +4444,11 @@ static void ADI_EOM_xx(upd7810_state *cpustate) ZHC_ADD( tmp, eom, 0 ); EOM = tmp; - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 c5: 0110 0100 1100 0101 xxxx xxxx */ -static void ADI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::ADI_TMM_xx() { UINT8 tmp, imm; @@ -4460,7 +4460,7 @@ static void ADI_TMM_xx(upd7810_state *cpustate) } /* 64 c8: 0110 0100 1100 1000 xxxx xxxx */ -static void ONI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::ONI_ANM_xx() { UINT8 imm; @@ -4470,7 +4470,7 @@ static void ONI_ANM_xx(upd7810_state *cpustate) } /* 64 c9: 0110 0100 1100 1001 xxxx xxxx */ -static void ONI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::ONI_SMH_xx() { UINT8 imm; @@ -4480,7 +4480,7 @@ static void ONI_SMH_xx(upd7810_state *cpustate) } /* 64 cb: 0110 0100 1100 1011 xxxx xxxx */ -static void ONI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::ONI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4492,7 +4492,7 @@ static void ONI_EOM_xx(upd7810_state *cpustate) } /* 64 cd: 0110 0100 1100 1101 xxxx xxxx */ -static void ONI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::ONI_TMM_xx() { UINT8 imm; @@ -4502,7 +4502,7 @@ static void ONI_TMM_xx(upd7810_state *cpustate) } /* 64 d0: 0110 0100 1101 0000 xxxx xxxx */ -static void ACI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::ACI_ANM_xx() { UINT8 tmp, imm; @@ -4514,7 +4514,7 @@ static void ACI_ANM_xx(upd7810_state *cpustate) } /* 64 d1: 0110 0100 1101 0001 xxxx xxxx */ -static void ACI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::ACI_SMH_xx() { UINT8 tmp, imm; @@ -4526,7 +4526,7 @@ static void ACI_SMH_xx(upd7810_state *cpustate) } /* 64 d3: 0110 0100 1101 0011 xxxx xxxx */ -static void ACI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::ACI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4537,11 +4537,11 @@ static void ACI_EOM_xx(upd7810_state *cpustate) ZHC_ADD( tmp, eom, (PSW & CY) ); EOM = tmp; - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 d5: 0110 0100 1101 0101 xxxx xxxx */ -static void ACI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::ACI_TMM_xx() { UINT8 tmp, imm; @@ -4553,7 +4553,7 @@ static void ACI_TMM_xx(upd7810_state *cpustate) } /* 64 d8: 0110 0100 1101 1000 xxxx xxxx */ -static void OFFI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_ANM_xx() { UINT8 imm; @@ -4563,7 +4563,7 @@ static void OFFI_ANM_xx(upd7810_state *cpustate) } /* 64 d9: 0110 0100 1101 1001 xxxx xxxx */ -static void OFFI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_SMH_xx() { UINT8 imm; @@ -4573,7 +4573,7 @@ static void OFFI_SMH_xx(upd7810_state *cpustate) } /* 64 db: 0110 0100 1101 1011 xxxx xxxx */ -static void OFFI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4585,7 +4585,7 @@ static void OFFI_EOM_xx(upd7810_state *cpustate) } /* 64 dd: 0110 0100 1101 1101 xxxx xxxx */ -static void OFFI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_TMM_xx() { UINT8 imm; @@ -4595,7 +4595,7 @@ static void OFFI_TMM_xx(upd7810_state *cpustate) } /* 64 e0: 0110 0100 1110 0000 xxxx xxxx */ -static void SUI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::SUI_ANM_xx() { UINT8 tmp, imm; @@ -4606,7 +4606,7 @@ static void SUI_ANM_xx(upd7810_state *cpustate) } /* 64 e1: 0110 0100 1110 0001 xxxx xxxx */ -static void SUI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::SUI_SMH_xx() { UINT8 tmp, imm; @@ -4617,7 +4617,7 @@ static void SUI_SMH_xx(upd7810_state *cpustate) } /* 64 e3: 0110 0100 1110 0011 xxxx xxxx */ -static void SUI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::SUI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4627,11 +4627,11 @@ static void SUI_EOM_xx(upd7810_state *cpustate) tmp = eom - imm; ZHC_SUB( tmp, eom, 0 ); EOM = tmp; - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 e5: 0110 0100 1110 0101 xxxx xxxx */ -static void SUI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::SUI_TMM_xx() { UINT8 tmp, imm; @@ -4642,7 +4642,7 @@ static void SUI_TMM_xx(upd7810_state *cpustate) } /* 64 e8: 0110 0100 1110 1000 xxxx xxxx */ -static void NEI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::NEI_ANM_xx() { UINT8 tmp, imm; @@ -4653,7 +4653,7 @@ static void NEI_ANM_xx(upd7810_state *cpustate) } /* 64 e9: 0110 0100 1110 1001 xxxx xxxx */ -static void NEI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::NEI_SMH_xx() { UINT8 tmp, imm; @@ -4664,7 +4664,7 @@ static void NEI_SMH_xx(upd7810_state *cpustate) } /* 64 eb: 0110 0100 1110 1011 xxxx xxxx */ -static void NEI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::NEI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4677,7 +4677,7 @@ static void NEI_EOM_xx(upd7810_state *cpustate) } /* 64 ed: 0110 0100 1110 1101 xxxx xxxx */ -static void NEI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::NEI_TMM_xx() { UINT8 tmp, imm; @@ -4688,7 +4688,7 @@ static void NEI_TMM_xx(upd7810_state *cpustate) } /* 64 f0: 0110 0100 1111 0000 xxxx xxxx */ -static void SBI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::SBI_ANM_xx() { UINT8 tmp, imm; @@ -4699,7 +4699,7 @@ static void SBI_ANM_xx(upd7810_state *cpustate) } /* 64 f1: 0110 0100 1111 0001 xxxx xxxx */ -static void SBI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::SBI_SMH_xx() { UINT8 tmp, imm; @@ -4710,7 +4710,7 @@ static void SBI_SMH_xx(upd7810_state *cpustate) } /* 64 f3: 0110 0100 1111 0011 xxxx xxxx */ -static void SBI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::SBI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4720,11 +4720,11 @@ static void SBI_EOM_xx(upd7810_state *cpustate) tmp = eom - imm - (PSW & CY); ZHC_SUB( tmp, eom, (PSW & CY) ); EOM = tmp; - upd7810_write_EOM(cpustate); + upd7810_write_EOM(); } /* 64 f5: 0110 0100 1111 0101 xxxx xxxx */ -static void SBI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::SBI_TMM_xx() { UINT8 tmp, imm; @@ -4735,7 +4735,7 @@ static void SBI_TMM_xx(upd7810_state *cpustate) } /* 64 f8: 0110 0100 1111 1000 xxxx xxxx */ -static void EQI_ANM_xx(upd7810_state *cpustate) +void upd7810_device::EQI_ANM_xx() { UINT8 tmp, imm; @@ -4746,7 +4746,7 @@ static void EQI_ANM_xx(upd7810_state *cpustate) } /* 64 f9: 0110 0100 1111 1001 xxxx xxxx */ -static void EQI_SMH_xx(upd7810_state *cpustate) +void upd7810_device::EQI_SMH_xx() { UINT8 tmp, imm; @@ -4757,7 +4757,7 @@ static void EQI_SMH_xx(upd7810_state *cpustate) } /* 64 fb: 0110 0100 1111 1011 xxxx xxxx */ -static void EQI_EOM_xx(upd7810_state *cpustate) +void upd7810_device::EQI_EOM_xx() { /* only bits #1 and #5 can be read */ UINT8 eom = EOM & 0x22; @@ -4770,7 +4770,7 @@ static void EQI_EOM_xx(upd7810_state *cpustate) } /* 64 fd: 0110 0100 1111 1101 xxxx xxxx */ -static void EQI_TMM_xx(upd7810_state *cpustate) +void upd7810_device::EQI_TMM_xx() { UINT8 tmp, imm; @@ -4782,7 +4782,7 @@ static void EQI_TMM_xx(upd7810_state *cpustate) /* prefix 70 */ /* 70 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */ -static void SSPD_w(upd7810_state *cpustate) +void upd7810_device::SSPD_w() { PAIR ea; ea.d = 0; @@ -4794,7 +4794,7 @@ static void SSPD_w(upd7810_state *cpustate) } /* 70 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */ -static void LSPD_w(upd7810_state *cpustate) +void upd7810_device::LSPD_w() { PAIR ea; ea.d = 0; @@ -4806,7 +4806,7 @@ static void LSPD_w(upd7810_state *cpustate) } /* 70 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */ -static void SBCD_w(upd7810_state *cpustate) +void upd7810_device::SBCD_w() { PAIR ea; ea.d = 0; @@ -4818,7 +4818,7 @@ static void SBCD_w(upd7810_state *cpustate) } /* 70 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */ -static void LBCD_w(upd7810_state *cpustate) +void upd7810_device::LBCD_w() { PAIR ea; ea.d = 0; @@ -4830,7 +4830,7 @@ static void LBCD_w(upd7810_state *cpustate) } /* 70 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */ -static void SDED_w(upd7810_state *cpustate) +void upd7810_device::SDED_w() { PAIR ea; ea.d = 0; @@ -4842,7 +4842,7 @@ static void SDED_w(upd7810_state *cpustate) } /* 70 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */ -static void LDED_w(upd7810_state *cpustate) +void upd7810_device::LDED_w() { PAIR ea; ea.d = 0; @@ -4854,7 +4854,7 @@ static void LDED_w(upd7810_state *cpustate) } /* 70 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */ -static void SHLD_w(upd7810_state *cpustate) +void upd7810_device::SHLD_w() { PAIR ea; ea.d = 0; @@ -4866,7 +4866,7 @@ static void SHLD_w(upd7810_state *cpustate) } /* 70 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */ -static void LHLD_w(upd7810_state *cpustate) +void upd7810_device::LHLD_w() { PAIR ea; ea.d = 0; @@ -4878,7 +4878,7 @@ static void LHLD_w(upd7810_state *cpustate) } /* 70 41: 0111 0000 0100 0001 */ -static void EADD_EA_A(upd7810_state *cpustate) +void upd7810_device::EADD_EA_A() { UINT16 tmp; tmp = EA + A; @@ -4887,7 +4887,7 @@ static void EADD_EA_A(upd7810_state *cpustate) } /* 70 42: 0111 0000 0100 0010 */ -static void EADD_EA_B(upd7810_state *cpustate) +void upd7810_device::EADD_EA_B() { UINT16 tmp; tmp = EA + B; @@ -4896,7 +4896,7 @@ static void EADD_EA_B(upd7810_state *cpustate) } /* 70 43: 0111 0000 0100 0011 */ -static void EADD_EA_C(upd7810_state *cpustate) +void upd7810_device::EADD_EA_C() { UINT16 tmp; tmp = EA + C; @@ -4905,7 +4905,7 @@ static void EADD_EA_C(upd7810_state *cpustate) } /* 70 61: 0111 0000 0110 0001 */ -static void ESUB_EA_A(upd7810_state *cpustate) +void upd7810_device::ESUB_EA_A() { UINT16 tmp; tmp = EA - A; @@ -4914,7 +4914,7 @@ static void ESUB_EA_A(upd7810_state *cpustate) } /* 70 62: 0111 0000 0110 0010 */ -static void ESUB_EA_B(upd7810_state *cpustate) +void upd7810_device::ESUB_EA_B() { UINT16 tmp; tmp = EA - B; @@ -4923,7 +4923,7 @@ static void ESUB_EA_B(upd7810_state *cpustate) } /* 70 63: 0111 0000 0110 0011 */ -static void ESUB_EA_C(upd7810_state *cpustate) +void upd7810_device::ESUB_EA_C() { UINT16 tmp; tmp = EA - C; @@ -4932,7 +4932,7 @@ static void ESUB_EA_C(upd7810_state *cpustate) } /* 70 68: 0111 0000 0110 1000 llll llll hhhh hhhh */ -static void MOV_V_w(upd7810_state *cpustate) +void upd7810_device::MOV_V_w() { PAIR ea; ea.d = 0; @@ -4943,7 +4943,7 @@ static void MOV_V_w(upd7810_state *cpustate) } /* 70 69: 0111 0000 0110 1001 llll llll hhhh hhhh */ -static void MOV_A_w(upd7810_state *cpustate) +void upd7810_device::MOV_A_w() { PAIR ea; ea.d = 0; @@ -4954,7 +4954,7 @@ static void MOV_A_w(upd7810_state *cpustate) } /* 70 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */ -static void MOV_B_w(upd7810_state *cpustate) +void upd7810_device::MOV_B_w() { PAIR ea; ea.d = 0; @@ -4965,7 +4965,7 @@ static void MOV_B_w(upd7810_state *cpustate) } /* 70 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */ -static void MOV_C_w(upd7810_state *cpustate) +void upd7810_device::MOV_C_w() { PAIR ea; ea.d = 0; @@ -4976,7 +4976,7 @@ static void MOV_C_w(upd7810_state *cpustate) } /* 70 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */ -static void MOV_D_w(upd7810_state *cpustate) +void upd7810_device::MOV_D_w() { PAIR ea; ea.d = 0; @@ -4987,7 +4987,7 @@ static void MOV_D_w(upd7810_state *cpustate) } /* 70 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */ -static void MOV_E_w(upd7810_state *cpustate) +void upd7810_device::MOV_E_w() { PAIR ea; ea.d = 0; @@ -4998,7 +4998,7 @@ static void MOV_E_w(upd7810_state *cpustate) } /* 70 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */ -static void MOV_H_w(upd7810_state *cpustate) +void upd7810_device::MOV_H_w() { PAIR ea; ea.d = 0; @@ -5009,7 +5009,7 @@ static void MOV_H_w(upd7810_state *cpustate) } /* 70 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */ -static void MOV_L_w(upd7810_state *cpustate) +void upd7810_device::MOV_L_w() { PAIR ea; ea.d = 0; @@ -5020,7 +5020,7 @@ static void MOV_L_w(upd7810_state *cpustate) } /* 70 78: 0111 0000 0111 1000 llll llll hhhh hhhh */ -static void MOV_w_V(upd7810_state *cpustate) +void upd7810_device::MOV_w_V() { PAIR ea; ea.d = 0; @@ -5031,7 +5031,7 @@ static void MOV_w_V(upd7810_state *cpustate) } /* 70 79: 0111 0000 0111 1001 llll llll hhhh hhhh */ -static void MOV_w_A(upd7810_state *cpustate) +void upd7810_device::MOV_w_A() { PAIR ea; ea.d = 0; @@ -5042,7 +5042,7 @@ static void MOV_w_A(upd7810_state *cpustate) } /* 70 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */ -static void MOV_w_B(upd7810_state *cpustate) +void upd7810_device::MOV_w_B() { PAIR ea; ea.d = 0; @@ -5053,7 +5053,7 @@ static void MOV_w_B(upd7810_state *cpustate) } /* 70 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */ -static void MOV_w_C(upd7810_state *cpustate) +void upd7810_device::MOV_w_C() { PAIR ea; ea.d = 0; @@ -5064,7 +5064,7 @@ static void MOV_w_C(upd7810_state *cpustate) } /* 70 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */ -static void MOV_w_D(upd7810_state *cpustate) +void upd7810_device::MOV_w_D() { PAIR ea; ea.d = 0; @@ -5075,7 +5075,7 @@ static void MOV_w_D(upd7810_state *cpustate) } /* 70 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */ -static void MOV_w_E(upd7810_state *cpustate) +void upd7810_device::MOV_w_E() { PAIR ea; ea.d = 0; @@ -5086,7 +5086,7 @@ static void MOV_w_E(upd7810_state *cpustate) } /* 70 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */ -static void MOV_w_H(upd7810_state *cpustate) +void upd7810_device::MOV_w_H() { PAIR ea; ea.d = 0; @@ -5097,7 +5097,7 @@ static void MOV_w_H(upd7810_state *cpustate) } /* 70 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */ -static void MOV_w_L(upd7810_state *cpustate) +void upd7810_device::MOV_w_L() { PAIR ea; ea.d = 0; @@ -5108,28 +5108,28 @@ static void MOV_w_L(upd7810_state *cpustate) } /* 70 89: 0111 0000 1000 1001 */ -static void ANAX_B(upd7810_state *cpustate) +void upd7810_device::ANAX_B() { A &= RM( BC ); SET_Z(A); } /* 70 8a: 0111 0000 1000 1010 */ -static void ANAX_D(upd7810_state *cpustate) +void upd7810_device::ANAX_D() { A &= RM( DE ); SET_Z(A); } /* 70 8b: 0111 0000 1000 1011 */ -static void ANAX_H(upd7810_state *cpustate) +void upd7810_device::ANAX_H() { A &= RM( HL ); SET_Z(A); } /* 70 8c: 0111 0000 1000 1100 */ -static void ANAX_Dp(upd7810_state *cpustate) +void upd7810_device::ANAX_Dp() { A &= RM( DE ); DE++; @@ -5137,7 +5137,7 @@ static void ANAX_Dp(upd7810_state *cpustate) } /* 70 8d: 0111 0000 1000 1101 */ -static void ANAX_Hp(upd7810_state *cpustate) +void upd7810_device::ANAX_Hp() { A &= RM( HL ); HL++; @@ -5145,7 +5145,7 @@ static void ANAX_Hp(upd7810_state *cpustate) } /* 70 8e: 0111 0000 1000 1110 */ -static void ANAX_Dm(upd7810_state *cpustate) +void upd7810_device::ANAX_Dm() { A &= RM( DE ); DE--; @@ -5153,7 +5153,7 @@ static void ANAX_Dm(upd7810_state *cpustate) } /* 70 8f: 0111 0000 1000 1111 */ -static void ANAX_Hm(upd7810_state *cpustate) +void upd7810_device::ANAX_Hm() { A &= RM( HL ); HL--; @@ -5161,28 +5161,28 @@ static void ANAX_Hm(upd7810_state *cpustate) } /* 70 91: 0111 0000 1001 0001 */ -static void XRAX_B(upd7810_state *cpustate) +void upd7810_device::XRAX_B() { A ^= RM( BC ); SET_Z(A); } /* 70 92: 0111 0000 1001 0010 */ -static void XRAX_D(upd7810_state *cpustate) +void upd7810_device::XRAX_D() { A ^= RM( DE ); SET_Z(A); } /* 70 93: 0111 0000 1001 0011 */ -static void XRAX_H(upd7810_state *cpustate) +void upd7810_device::XRAX_H() { A ^= RM( HL ); SET_Z(A); } /* 70 94: 0111 0000 1001 0100 */ -static void XRAX_Dp(upd7810_state *cpustate) +void upd7810_device::XRAX_Dp() { A ^= RM( DE ); DE++; @@ -5190,7 +5190,7 @@ static void XRAX_Dp(upd7810_state *cpustate) } /* 70 95: 0111 0000 1001 0101 */ -static void XRAX_Hp(upd7810_state *cpustate) +void upd7810_device::XRAX_Hp() { A ^= RM( HL ); HL++; @@ -5198,7 +5198,7 @@ static void XRAX_Hp(upd7810_state *cpustate) } /* 70 96: 0111 0000 1001 0110 */ -static void XRAX_Dm(upd7810_state *cpustate) +void upd7810_device::XRAX_Dm() { A ^= RM( DE ); DE--; @@ -5206,7 +5206,7 @@ static void XRAX_Dm(upd7810_state *cpustate) } /* 70 97: 0111 0000 1001 0111 */ -static void XRAX_Hm(upd7810_state *cpustate) +void upd7810_device::XRAX_Hm() { A ^= RM( HL ); HL--; @@ -5214,28 +5214,28 @@ static void XRAX_Hm(upd7810_state *cpustate) } /* 70 99: 0111 0000 1001 1001 */ -static void ORAX_B(upd7810_state *cpustate) +void upd7810_device::ORAX_B() { A |= RM( BC ); SET_Z(A); } /* 70 9a: 0111 0000 1001 1010 */ -static void ORAX_D(upd7810_state *cpustate) +void upd7810_device::ORAX_D() { A |= RM( DE ); SET_Z(A); } /* 70 9b: 0111 0000 1001 1011 */ -static void ORAX_H(upd7810_state *cpustate) +void upd7810_device::ORAX_H() { A |= RM( HL ); SET_Z(A); } /* 70 9c: 0111 0000 1001 0100 */ -static void ORAX_Dp(upd7810_state *cpustate) +void upd7810_device::ORAX_Dp() { A |= RM( DE ); DE++; @@ -5243,7 +5243,7 @@ static void ORAX_Dp(upd7810_state *cpustate) } /* 70 9d: 0111 0000 1001 1101 */ -static void ORAX_Hp(upd7810_state *cpustate) +void upd7810_device::ORAX_Hp() { A |= RM( HL ); HL++; @@ -5251,7 +5251,7 @@ static void ORAX_Hp(upd7810_state *cpustate) } /* 70 9e: 0111 0000 1001 1110 */ -static void ORAX_Dm(upd7810_state *cpustate) +void upd7810_device::ORAX_Dm() { A |= RM( DE ); DE--; @@ -5259,7 +5259,7 @@ static void ORAX_Dm(upd7810_state *cpustate) } /* 70 9f: 0111 0000 1001 1111 */ -static void ORAX_Hm(upd7810_state *cpustate) +void upd7810_device::ORAX_Hm() { A |= RM( HL ); HL--; @@ -5267,7 +5267,7 @@ static void ORAX_Hm(upd7810_state *cpustate) } /* 70 a1: 0111 0000 1010 0001 */ -static void ADDNCX_B(upd7810_state *cpustate) +void upd7810_device::ADDNCX_B() { UINT8 tmp = A + RM( BC ); ZHC_ADD( tmp, A, 0 ); @@ -5276,7 +5276,7 @@ static void ADDNCX_B(upd7810_state *cpustate) } /* 70 a2: 0111 0000 1010 0010 */ -static void ADDNCX_D(upd7810_state *cpustate) +void upd7810_device::ADDNCX_D() { UINT8 tmp = A + RM( DE ); ZHC_ADD( tmp, A, 0 ); @@ -5285,7 +5285,7 @@ static void ADDNCX_D(upd7810_state *cpustate) } /* 70 a3: 0111 0000 1010 0011 */ -static void ADDNCX_H(upd7810_state *cpustate) +void upd7810_device::ADDNCX_H() { UINT8 tmp = A + RM( HL ); ZHC_ADD( tmp, A, 0 ); @@ -5294,7 +5294,7 @@ static void ADDNCX_H(upd7810_state *cpustate) } /* 70 a4: 0111 0000 1010 0100 */ -static void ADDNCX_Dp(upd7810_state *cpustate) +void upd7810_device::ADDNCX_Dp() { UINT8 tmp = A + RM( DE ); DE++; @@ -5304,7 +5304,7 @@ static void ADDNCX_Dp(upd7810_state *cpustate) } /* 70 a5: 0111 0000 1010 0101 */ -static void ADDNCX_Hp(upd7810_state *cpustate) +void upd7810_device::ADDNCX_Hp() { UINT8 tmp = A + RM( HL ); HL++; @@ -5314,7 +5314,7 @@ static void ADDNCX_Hp(upd7810_state *cpustate) } /* 70 a6: 0111 0000 1010 0110 */ -static void ADDNCX_Dm(upd7810_state *cpustate) +void upd7810_device::ADDNCX_Dm() { UINT8 tmp = A + RM( DE ); DE--; @@ -5324,7 +5324,7 @@ static void ADDNCX_Dm(upd7810_state *cpustate) } /* 70 a7: 0111 0000 1010 0111 */ -static void ADDNCX_Hm(upd7810_state *cpustate) +void upd7810_device::ADDNCX_Hm() { UINT8 tmp = A + RM( HL ); HL--; @@ -5334,7 +5334,7 @@ static void ADDNCX_Hm(upd7810_state *cpustate) } /* 70 a9: 0111 0000 1010 1001 */ -static void GTAX_B(upd7810_state *cpustate) +void upd7810_device::GTAX_B() { UINT16 tmp = A - RM( BC ) - 1; ZHC_SUB( tmp, A, 0 ); @@ -5342,7 +5342,7 @@ static void GTAX_B(upd7810_state *cpustate) } /* 70 aa: 0111 0000 1010 1010 */ -static void GTAX_D(upd7810_state *cpustate) +void upd7810_device::GTAX_D() { UINT16 tmp = A - RM( DE ) - 1; ZHC_SUB( tmp, A, 0 ); @@ -5350,7 +5350,7 @@ static void GTAX_D(upd7810_state *cpustate) } /* 70 ab: 0111 0000 1010 1011 */ -static void GTAX_H(upd7810_state *cpustate) +void upd7810_device::GTAX_H() { UINT16 tmp = A - RM( HL ) - 1; ZHC_SUB( tmp, A, 0 ); @@ -5358,7 +5358,7 @@ static void GTAX_H(upd7810_state *cpustate) } /* 70 ac: 0111 0000 1010 1100 */ -static void GTAX_Dp(upd7810_state *cpustate) +void upd7810_device::GTAX_Dp() { UINT16 tmp = A - RM( DE ) - 1; DE++; @@ -5367,7 +5367,7 @@ static void GTAX_Dp(upd7810_state *cpustate) } /* 70 ad: 0111 0000 1010 1101 */ -static void GTAX_Hp(upd7810_state *cpustate) +void upd7810_device::GTAX_Hp() { UINT16 tmp = A - RM( HL ) - 1; HL++; @@ -5376,7 +5376,7 @@ static void GTAX_Hp(upd7810_state *cpustate) } /* 70 ae: 0111 0000 1010 1110 */ -static void GTAX_Dm(upd7810_state *cpustate) +void upd7810_device::GTAX_Dm() { UINT16 tmp = A - RM( DE ) - 1; DE--; @@ -5385,7 +5385,7 @@ static void GTAX_Dm(upd7810_state *cpustate) } /* 70 af: 0111 0000 1010 1111 */ -static void GTAX_Hm(upd7810_state *cpustate) +void upd7810_device::GTAX_Hm() { UINT16 tmp = A - RM( HL ) - 1; HL--; @@ -5394,7 +5394,7 @@ static void GTAX_Hm(upd7810_state *cpustate) } /* 70 b1: 0111 0000 1011 0001 */ -static void SUBNBX_B(upd7810_state *cpustate) +void upd7810_device::SUBNBX_B() { UINT8 tmp = A - RM( BC ); ZHC_SUB( tmp, A, 0 ); @@ -5403,7 +5403,7 @@ static void SUBNBX_B(upd7810_state *cpustate) } /* 70 b2: 0111 0000 1011 0010 */ -static void SUBNBX_D(upd7810_state *cpustate) +void upd7810_device::SUBNBX_D() { UINT8 tmp = A - RM( DE ); ZHC_SUB( tmp, A, 0 ); @@ -5412,7 +5412,7 @@ static void SUBNBX_D(upd7810_state *cpustate) } /* 70 b3: 0111 0000 1011 0011 */ -static void SUBNBX_H(upd7810_state *cpustate) +void upd7810_device::SUBNBX_H() { UINT8 tmp = A - RM( HL ); ZHC_SUB( tmp, A, 0 ); @@ -5421,7 +5421,7 @@ static void SUBNBX_H(upd7810_state *cpustate) } /* 70 b4: 0111 0000 1011 0100 */ -static void SUBNBX_Dp(upd7810_state *cpustate) +void upd7810_device::SUBNBX_Dp() { UINT8 tmp = A - RM( DE ); DE++; @@ -5431,7 +5431,7 @@ static void SUBNBX_Dp(upd7810_state *cpustate) } /* 70 b5: 0111 0000 1011 0101 */ -static void SUBNBX_Hp(upd7810_state *cpustate) +void upd7810_device::SUBNBX_Hp() { UINT8 tmp = A - RM( HL ); HL++; @@ -5441,7 +5441,7 @@ static void SUBNBX_Hp(upd7810_state *cpustate) } /* 70 b6: 0111 0000 1011 0110 */ -static void SUBNBX_Dm(upd7810_state *cpustate) +void upd7810_device::SUBNBX_Dm() { UINT8 tmp = A - RM( DE ); DE--; @@ -5451,7 +5451,7 @@ static void SUBNBX_Dm(upd7810_state *cpustate) } /* 70 b7: 0111 0000 1011 0111 */ -static void SUBNBX_Hm(upd7810_state *cpustate) +void upd7810_device::SUBNBX_Hm() { UINT8 tmp = A - RM( HL ); HL--; @@ -5461,7 +5461,7 @@ static void SUBNBX_Hm(upd7810_state *cpustate) } /* 70 b9: 0111 0000 1011 1001 */ -static void LTAX_B(upd7810_state *cpustate) +void upd7810_device::LTAX_B() { UINT8 tmp = A - RM( BC ); ZHC_SUB( tmp, A, 0 ); @@ -5469,7 +5469,7 @@ static void LTAX_B(upd7810_state *cpustate) } /* 70 ba: 0111 0000 1011 1010 */ -static void LTAX_D(upd7810_state *cpustate) +void upd7810_device::LTAX_D() { UINT8 tmp = A - RM( DE ); ZHC_SUB( tmp, A, 0 ); @@ -5477,7 +5477,7 @@ static void LTAX_D(upd7810_state *cpustate) } /* 70 bb: 0111 0000 1011 1011 */ -static void LTAX_H(upd7810_state *cpustate) +void upd7810_device::LTAX_H() { UINT8 tmp = A - RM( HL ); ZHC_SUB( tmp, A, 0 ); @@ -5485,7 +5485,7 @@ static void LTAX_H(upd7810_state *cpustate) } /* 70 bc: 0111 0000 1011 1100 */ -static void LTAX_Dp(upd7810_state *cpustate) +void upd7810_device::LTAX_Dp() { UINT8 tmp = A - RM( DE ); DE++; @@ -5494,7 +5494,7 @@ static void LTAX_Dp(upd7810_state *cpustate) } /* 70 bd: 0111 0000 1011 1101 */ -static void LTAX_Hp(upd7810_state *cpustate) +void upd7810_device::LTAX_Hp() { UINT8 tmp = A - RM( HL ); HL++; @@ -5503,7 +5503,7 @@ static void LTAX_Hp(upd7810_state *cpustate) } /* 70 be: 0111 0000 1011 1110 */ -static void LTAX_Dm(upd7810_state *cpustate) +void upd7810_device::LTAX_Dm() { UINT8 tmp = A - RM( DE ); DE--; @@ -5512,7 +5512,7 @@ static void LTAX_Dm(upd7810_state *cpustate) } /* 70 bf: 0111 0000 1011 1111 */ -static void LTAX_Hm(upd7810_state *cpustate) +void upd7810_device::LTAX_Hm() { UINT8 tmp = A - RM( HL ); HL--; @@ -5521,7 +5521,7 @@ static void LTAX_Hm(upd7810_state *cpustate) } /* 70 c1: 0111 0000 1100 0001 */ -static void ADDX_B(upd7810_state *cpustate) +void upd7810_device::ADDX_B() { UINT8 tmp = A + RM( BC ); ZHC_ADD( tmp, A, 0 ); @@ -5529,7 +5529,7 @@ static void ADDX_B(upd7810_state *cpustate) } /* 70 c2: 0111 0000 1100 0010 */ -static void ADDX_D(upd7810_state *cpustate) +void upd7810_device::ADDX_D() { UINT8 tmp = A + RM( DE ); ZHC_ADD( tmp, A, 0 ); @@ -5537,7 +5537,7 @@ static void ADDX_D(upd7810_state *cpustate) } /* 70 c3: 0111 0000 1100 0011 */ -static void ADDX_H(upd7810_state *cpustate) +void upd7810_device::ADDX_H() { UINT8 tmp = A + RM( HL ); ZHC_ADD( tmp, A, 0 ); @@ -5545,7 +5545,7 @@ static void ADDX_H(upd7810_state *cpustate) } /* 70 c4: 0111 0000 1100 0100 */ -static void ADDX_Dp(upd7810_state *cpustate) +void upd7810_device::ADDX_Dp() { UINT8 tmp = A + RM( DE ); DE++; @@ -5554,7 +5554,7 @@ static void ADDX_Dp(upd7810_state *cpustate) } /* 70 c5: 0111 0000 1100 0101 */ -static void ADDX_Hp(upd7810_state *cpustate) +void upd7810_device::ADDX_Hp() { UINT8 tmp = A + RM( HL ); HL++; @@ -5563,7 +5563,7 @@ static void ADDX_Hp(upd7810_state *cpustate) } /* 70 c6: 0111 0000 1100 0110 */ -static void ADDX_Dm(upd7810_state *cpustate) +void upd7810_device::ADDX_Dm() { UINT8 tmp = A + RM( DE ); DE--; @@ -5572,7 +5572,7 @@ static void ADDX_Dm(upd7810_state *cpustate) } /* 70 c7: 0111 0000 1100 0111 */ -static void ADDX_Hm(upd7810_state *cpustate) +void upd7810_device::ADDX_Hm() { UINT8 tmp = A + RM( HL ); HL--; @@ -5581,7 +5581,7 @@ static void ADDX_Hm(upd7810_state *cpustate) } /* 70 c9: 0111 0000 1100 1001 */ -static void ONAX_B(upd7810_state *cpustate) +void upd7810_device::ONAX_B() { if (A & RM( BC )) PSW = (PSW & ~Z) | SK; @@ -5590,7 +5590,7 @@ static void ONAX_B(upd7810_state *cpustate) } /* 70 ca: 0111 0000 1100 1010 */ -static void ONAX_D(upd7810_state *cpustate) +void upd7810_device::ONAX_D() { if (A & RM( DE )) PSW = (PSW & ~Z) | SK; @@ -5599,7 +5599,7 @@ static void ONAX_D(upd7810_state *cpustate) } /* 70 cb: 0111 0000 1100 1011 */ -static void ONAX_H(upd7810_state *cpustate) +void upd7810_device::ONAX_H() { if (A & RM( HL )) PSW = (PSW & ~Z) | SK; @@ -5608,7 +5608,7 @@ static void ONAX_H(upd7810_state *cpustate) } /* 70 cc: 0111 0000 1100 1100 */ -static void ONAX_Dp(upd7810_state *cpustate) +void upd7810_device::ONAX_Dp() { if (A & RM( DE )) PSW = (PSW & ~Z) | SK; @@ -5618,7 +5618,7 @@ static void ONAX_Dp(upd7810_state *cpustate) } /* 70 cd: 0111 0000 1100 1101 */ -static void ONAX_Hp(upd7810_state *cpustate) +void upd7810_device::ONAX_Hp() { if (A & RM( HL )) PSW = (PSW & ~Z) | SK; @@ -5628,7 +5628,7 @@ static void ONAX_Hp(upd7810_state *cpustate) } /* 70 ce: 0111 0000 1100 1110 */ -static void ONAX_Dm(upd7810_state *cpustate) +void upd7810_device::ONAX_Dm() { if (A & RM( DE )) PSW = (PSW & ~Z) | SK; @@ -5638,7 +5638,7 @@ static void ONAX_Dm(upd7810_state *cpustate) } /* 70 cf: 0111 0000 1100 1111 */ -static void ONAX_Hm(upd7810_state *cpustate) +void upd7810_device::ONAX_Hm() { if (A & RM( HL )) PSW = (PSW & ~Z) | SK; @@ -5648,7 +5648,7 @@ static void ONAX_Hm(upd7810_state *cpustate) } /* 70 d1: 0111 0000 1101 0001 */ -static void ADCX_B(upd7810_state *cpustate) +void upd7810_device::ADCX_B() { UINT8 tmp = A + RM( BC ) + (PSW & CY); ZHC_ADD( tmp, A, 0 ); @@ -5656,7 +5656,7 @@ static void ADCX_B(upd7810_state *cpustate) } /* 70 d2: 0111 0000 1101 0010 */ -static void ADCX_D(upd7810_state *cpustate) +void upd7810_device::ADCX_D() { UINT8 tmp = A + RM( DE ) + (PSW & CY); ZHC_ADD( tmp, A, 0 ); @@ -5664,7 +5664,7 @@ static void ADCX_D(upd7810_state *cpustate) } /* 70 d3: 0111 0000 1101 0011 */ -static void ADCX_H(upd7810_state *cpustate) +void upd7810_device::ADCX_H() { UINT8 tmp = A + RM( HL ) + (PSW & CY); ZHC_ADD( tmp, A, 0 ); @@ -5672,7 +5672,7 @@ static void ADCX_H(upd7810_state *cpustate) } /* 70 d4: 0111 0000 1101 0100 */ -static void ADCX_Dp(upd7810_state *cpustate) +void upd7810_device::ADCX_Dp() { UINT8 tmp = A + RM( DE ) + (PSW & CY); DE++; @@ -5681,7 +5681,7 @@ static void ADCX_Dp(upd7810_state *cpustate) } /* 70 d5: 0111 0000 1101 0101 */ -static void ADCX_Hp(upd7810_state *cpustate) +void upd7810_device::ADCX_Hp() { UINT8 tmp = A + RM( HL ) + (PSW & CY); HL++; @@ -5690,7 +5690,7 @@ static void ADCX_Hp(upd7810_state *cpustate) } /* 70 d6: 0111 0000 1101 0110 */ -static void ADCX_Dm(upd7810_state *cpustate) +void upd7810_device::ADCX_Dm() { UINT8 tmp = A + RM( DE ) + (PSW & CY); DE--; @@ -5699,7 +5699,7 @@ static void ADCX_Dm(upd7810_state *cpustate) } /* 70 d7: 0111 0000 1101 0111 */ -static void ADCX_Hm(upd7810_state *cpustate) +void upd7810_device::ADCX_Hm() { UINT8 tmp = A + RM( HL ) + (PSW & CY); HL--; @@ -5708,7 +5708,7 @@ static void ADCX_Hm(upd7810_state *cpustate) } /* 70 d9: 0111 0000 1101 1001 */ -static void OFFAX_B(upd7810_state *cpustate) +void upd7810_device::OFFAX_B() { if ( A & RM( BC ) ) PSW &= ~Z; @@ -5717,7 +5717,7 @@ static void OFFAX_B(upd7810_state *cpustate) } /* 70 da: 0111 0000 1101 1010 */ -static void OFFAX_D(upd7810_state *cpustate) +void upd7810_device::OFFAX_D() { if ( A & RM( DE ) ) PSW &= ~Z; @@ -5726,7 +5726,7 @@ static void OFFAX_D(upd7810_state *cpustate) } /* 70 db: 0111 0000 1101 1011 */ -static void OFFAX_H(upd7810_state *cpustate) +void upd7810_device::OFFAX_H() { if ( A & RM( HL ) ) PSW &= ~Z; @@ -5735,7 +5735,7 @@ static void OFFAX_H(upd7810_state *cpustate) } /* 70 dc: 0111 0000 1101 1100 */ -static void OFFAX_Dp(upd7810_state *cpustate) +void upd7810_device::OFFAX_Dp() { if ( A & RM( DE ) ) PSW &= ~Z; @@ -5745,7 +5745,7 @@ static void OFFAX_Dp(upd7810_state *cpustate) } /* 70 dd: 0111 0000 1101 1101 */ -static void OFFAX_Hp(upd7810_state *cpustate) +void upd7810_device::OFFAX_Hp() { if ( A & RM( HL ) ) PSW &= ~Z; @@ -5755,7 +5755,7 @@ static void OFFAX_Hp(upd7810_state *cpustate) } /* 70 de: 0111 0000 1101 1110 */ -static void OFFAX_Dm(upd7810_state *cpustate) +void upd7810_device::OFFAX_Dm() { if ( A & RM( DE ) ) PSW &= ~Z; @@ -5765,7 +5765,7 @@ static void OFFAX_Dm(upd7810_state *cpustate) } /* 70 df: 0111 0000 1101 1111 */ -static void OFFAX_Hm(upd7810_state *cpustate) +void upd7810_device::OFFAX_Hm() { if ( A & RM( HL ) ) PSW &= ~Z; @@ -5775,7 +5775,7 @@ static void OFFAX_Hm(upd7810_state *cpustate) } /* 70 e1: 0111 0000 1110 0001 */ -static void SUBX_B(upd7810_state *cpustate) +void upd7810_device::SUBX_B() { UINT8 tmp = A - RM( BC ); ZHC_SUB( tmp, A, 0 ); @@ -5783,7 +5783,7 @@ static void SUBX_B(upd7810_state *cpustate) } /* 70 e2: 0111 0000 1110 0010 */ -static void SUBX_D(upd7810_state *cpustate) +void upd7810_device::SUBX_D() { UINT8 tmp = A - RM( DE ); ZHC_SUB( tmp, A, 0 ); @@ -5791,7 +5791,7 @@ static void SUBX_D(upd7810_state *cpustate) } /* 70 e3: 0111 0000 1110 0011 */ -static void SUBX_H(upd7810_state *cpustate) +void upd7810_device::SUBX_H() { UINT8 tmp = A - RM( HL ); ZHC_SUB( tmp, A, 0 ); @@ -5799,7 +5799,7 @@ static void SUBX_H(upd7810_state *cpustate) } /* 70 e4: 0111 0000 1110 0100 */ -static void SUBX_Dp(upd7810_state *cpustate) +void upd7810_device::SUBX_Dp() { UINT8 tmp = A - RM( DE ); ZHC_SUB( tmp, A, 0 ); @@ -5808,7 +5808,7 @@ static void SUBX_Dp(upd7810_state *cpustate) } /* 70 e5: 0111 0000 1110 0101 */ -static void SUBX_Hp(upd7810_state *cpustate) +void upd7810_device::SUBX_Hp() { UINT8 tmp = A - RM( HL ); ZHC_SUB( tmp, A, 0 ); @@ -5817,7 +5817,7 @@ static void SUBX_Hp(upd7810_state *cpustate) } /* 70 e6: 0111 0000 1110 0110 */ -static void SUBX_Dm(upd7810_state *cpustate) +void upd7810_device::SUBX_Dm() { UINT8 tmp = A - RM( DE ); ZHC_SUB( tmp, A, 0 ); @@ -5826,7 +5826,7 @@ static void SUBX_Dm(upd7810_state *cpustate) } /* 70 e7: 0111 0000 1110 0111 */ -static void SUBX_Hm(upd7810_state *cpustate) +void upd7810_device::SUBX_Hm() { UINT8 tmp = A - RM( HL ); ZHC_SUB( tmp, A, 0 ); @@ -5835,7 +5835,7 @@ static void SUBX_Hm(upd7810_state *cpustate) } /* 70 e9: 0111 0000 1110 1001 */ -static void NEAX_B(upd7810_state *cpustate) +void upd7810_device::NEAX_B() { UINT8 tmp = A - RM( BC ); ZHC_SUB( tmp, A, 0 ); @@ -5843,7 +5843,7 @@ static void NEAX_B(upd7810_state *cpustate) } /* 70 ea: 0111 0000 1110 1010 */ -static void NEAX_D(upd7810_state *cpustate) +void upd7810_device::NEAX_D() { UINT8 tmp = A - RM( DE ); ZHC_SUB( tmp, A, 0 ); @@ -5851,7 +5851,7 @@ static void NEAX_D(upd7810_state *cpustate) } /* 70 eb: 0111 0000 1110 1011 */ -static void NEAX_H(upd7810_state *cpustate) +void upd7810_device::NEAX_H() { UINT8 tmp = A - RM( HL ); ZHC_SUB( tmp, A, 0 ); @@ -5859,7 +5859,7 @@ static void NEAX_H(upd7810_state *cpustate) } /* 70 ec: 0111 0000 1110 1100 */ -static void NEAX_Dp(upd7810_state *cpustate) +void upd7810_device::NEAX_Dp() { UINT8 tmp = A - RM( DE ); DE++; @@ -5868,7 +5868,7 @@ static void NEAX_Dp(upd7810_state *cpustate) } /* 70 ed: 0111 0000 1110 1101 */ -static void NEAX_Hp(upd7810_state *cpustate) +void upd7810_device::NEAX_Hp() { UINT8 tmp = A - RM( HL ); HL++; @@ -5877,7 +5877,7 @@ static void NEAX_Hp(upd7810_state *cpustate) } /* 70 ee: 0111 0000 1110 1110 */ -static void NEAX_Dm(upd7810_state *cpustate) +void upd7810_device::NEAX_Dm() { UINT8 tmp = A - RM( DE ); DE--; @@ -5886,7 +5886,7 @@ static void NEAX_Dm(upd7810_state *cpustate) } /* 70 ef: 0111 0000 1110 1111 */ -static void NEAX_Hm(upd7810_state *cpustate) +void upd7810_device::NEAX_Hm() { UINT8 tmp = A - RM( HL ); HL--; @@ -5895,7 +5895,7 @@ static void NEAX_Hm(upd7810_state *cpustate) } /* 70 f1: 0111 0000 1111 0001 */ -static void SBBX_B(upd7810_state *cpustate) +void upd7810_device::SBBX_B() { UINT8 tmp = A - RM( BC ) - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -5903,7 +5903,7 @@ static void SBBX_B(upd7810_state *cpustate) } /* 70 f2: 0111 0000 1111 0010 */ -static void SBBX_D(upd7810_state *cpustate) +void upd7810_device::SBBX_D() { UINT8 tmp = A - RM( DE ) - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -5911,7 +5911,7 @@ static void SBBX_D(upd7810_state *cpustate) } /* 70 f3: 0111 0000 1111 0011 */ -static void SBBX_H(upd7810_state *cpustate) +void upd7810_device::SBBX_H() { UINT8 tmp = A - RM( HL ) - (PSW & CY); ZHC_SUB( tmp, A, (PSW & CY) ); @@ -5919,7 +5919,7 @@ static void SBBX_H(upd7810_state *cpustate) } /* 70 f4: 0111 0000 1111 0100 */ -static void SBBX_Dp(upd7810_state *cpustate) +void upd7810_device::SBBX_Dp() { UINT8 tmp = A - RM( DE ) - (PSW & CY); DE++; @@ -5928,7 +5928,7 @@ static void SBBX_Dp(upd7810_state *cpustate) } /* 70 f5: 0111 0000 1111 0101 */ -static void SBBX_Hp(upd7810_state *cpustate) +void upd7810_device::SBBX_Hp() { UINT8 tmp = A - RM( HL ) - (PSW & CY); HL++; @@ -5937,7 +5937,7 @@ static void SBBX_Hp(upd7810_state *cpustate) } /* 70 f6: 0111 0000 1111 0110 */ -static void SBBX_Dm(upd7810_state *cpustate) +void upd7810_device::SBBX_Dm() { UINT8 tmp = A - RM( DE ) - (PSW & CY); DE--; @@ -5946,7 +5946,7 @@ static void SBBX_Dm(upd7810_state *cpustate) } /* 70 f7: 0111 0000 1111 0111 */ -static void SBBX_Hm(upd7810_state *cpustate) +void upd7810_device::SBBX_Hm() { UINT8 tmp = A - RM( HL ) - (PSW & CY); HL--; @@ -5955,7 +5955,7 @@ static void SBBX_Hm(upd7810_state *cpustate) } /* 70 f9: 0111 0000 1111 1001 */ -static void EQAX_B(upd7810_state *cpustate) +void upd7810_device::EQAX_B() { UINT8 tmp = A - RM( BC ); ZHC_SUB( tmp, A, 0 ); @@ -5963,7 +5963,7 @@ static void EQAX_B(upd7810_state *cpustate) } /* 70 fa: 0111 0000 1111 1010 */ -static void EQAX_D(upd7810_state *cpustate) +void upd7810_device::EQAX_D() { UINT8 tmp = A - RM( DE ); ZHC_SUB( tmp, A, 0 ); @@ -5971,7 +5971,7 @@ static void EQAX_D(upd7810_state *cpustate) } /* 70 fb: 0111 0000 1111 1011 */ -static void EQAX_H(upd7810_state *cpustate) +void upd7810_device::EQAX_H() { UINT8 tmp = A - RM( HL ); ZHC_SUB( tmp, A, 0 ); @@ -5979,7 +5979,7 @@ static void EQAX_H(upd7810_state *cpustate) } /* 70 fc: 0111 0000 1111 1100 */ -static void EQAX_Dp(upd7810_state *cpustate) +void upd7810_device::EQAX_Dp() { UINT8 tmp = A - RM( DE ); DE++; @@ -5988,7 +5988,7 @@ static void EQAX_Dp(upd7810_state *cpustate) } /* 70 fd: 0111 0000 1111 1101 */ -static void EQAX_Hp(upd7810_state *cpustate) +void upd7810_device::EQAX_Hp() { UINT8 tmp = A - RM( HL ); HL++; @@ -5997,7 +5997,7 @@ static void EQAX_Hp(upd7810_state *cpustate) } /* 70 fe: 0111 0000 1111 1110 */ -static void EQAX_Dm(upd7810_state *cpustate) +void upd7810_device::EQAX_Dm() { UINT8 tmp = A - RM( DE ); DE--; @@ -6006,7 +6006,7 @@ static void EQAX_Dm(upd7810_state *cpustate) } /* 70 ff: 0111 0000 1111 1111 */ -static void EQAX_Hm(upd7810_state *cpustate) +void upd7810_device::EQAX_Hm() { UINT8 tmp = A - RM( HL ); HL--; @@ -6016,7 +6016,7 @@ static void EQAX_Hm(upd7810_state *cpustate) /* prefix 74 */ /* 74 08: 0111 0100 0000 1000 xxxx xxxx */ -static void ANI_V_xx(upd7810_state *cpustate) +void upd7810_device::ANI_V_xx() { UINT8 imm; RDOPARG( imm ); @@ -6025,7 +6025,7 @@ static void ANI_V_xx(upd7810_state *cpustate) } /* 74 09: 0111 0100 0000 1001 xxxx xxxx */ -static void ANI_A_xx(upd7810_state *cpustate) +void upd7810_device::ANI_A_xx() { UINT8 imm; RDOPARG( imm ); @@ -6034,7 +6034,7 @@ static void ANI_A_xx(upd7810_state *cpustate) } /* 74 0a: 0111 0100 0000 1010 xxxx xxxx */ -static void ANI_B_xx(upd7810_state *cpustate) +void upd7810_device::ANI_B_xx() { UINT8 imm; RDOPARG( imm ); @@ -6043,7 +6043,7 @@ static void ANI_B_xx(upd7810_state *cpustate) } /* 74 0b: 0111 0100 0000 1011 xxxx xxxx */ -static void ANI_C_xx(upd7810_state *cpustate) +void upd7810_device::ANI_C_xx() { UINT8 imm; RDOPARG( imm ); @@ -6052,7 +6052,7 @@ static void ANI_C_xx(upd7810_state *cpustate) } /* 74 0c: 0111 0100 0000 1100 xxxx xxxx */ -static void ANI_D_xx(upd7810_state *cpustate) +void upd7810_device::ANI_D_xx() { UINT8 imm; RDOPARG( imm ); @@ -6061,7 +6061,7 @@ static void ANI_D_xx(upd7810_state *cpustate) } /* 74 0d: 0111 0100 0000 1101 xxxx xxxx */ -static void ANI_E_xx(upd7810_state *cpustate) +void upd7810_device::ANI_E_xx() { UINT8 imm; RDOPARG( imm ); @@ -6070,7 +6070,7 @@ static void ANI_E_xx(upd7810_state *cpustate) } /* 74 0e: 0111 0100 0000 1110 xxxx xxxx */ -static void ANI_H_xx(upd7810_state *cpustate) +void upd7810_device::ANI_H_xx() { UINT8 imm; RDOPARG( imm ); @@ -6079,7 +6079,7 @@ static void ANI_H_xx(upd7810_state *cpustate) } /* 74 0f: 0111 0100 0000 1111 xxxx xxxx */ -static void ANI_L_xx(upd7810_state *cpustate) +void upd7810_device::ANI_L_xx() { UINT8 imm; RDOPARG( imm ); @@ -6088,7 +6088,7 @@ static void ANI_L_xx(upd7810_state *cpustate) } /* 74 10: 0111 0100 0001 0000 xxxx xxxx */ -static void XRI_V_xx(upd7810_state *cpustate) +void upd7810_device::XRI_V_xx() { UINT8 imm; RDOPARG( imm ); @@ -6097,7 +6097,7 @@ static void XRI_V_xx(upd7810_state *cpustate) } /* 74 11: 0111 0100 0001 0001 xxxx xxxx */ -static void XRI_A_xx(upd7810_state *cpustate) +void upd7810_device::XRI_A_xx() { UINT8 imm; RDOPARG( imm ); @@ -6106,7 +6106,7 @@ static void XRI_A_xx(upd7810_state *cpustate) } /* 74 12: 0111 0100 0001 0010 xxxx xxxx */ -static void XRI_B_xx(upd7810_state *cpustate) +void upd7810_device::XRI_B_xx() { UINT8 imm; RDOPARG( imm ); @@ -6115,7 +6115,7 @@ static void XRI_B_xx(upd7810_state *cpustate) } /* 74 13: 0111 0100 0001 0011 xxxx xxxx */ -static void XRI_C_xx(upd7810_state *cpustate) +void upd7810_device::XRI_C_xx() { UINT8 imm; RDOPARG( imm ); @@ -6124,7 +6124,7 @@ static void XRI_C_xx(upd7810_state *cpustate) } /* 74 14: 0111 0100 0001 0100 xxxx xxxx */ -static void XRI_D_xx(upd7810_state *cpustate) +void upd7810_device::XRI_D_xx() { UINT8 imm; RDOPARG( imm ); @@ -6133,7 +6133,7 @@ static void XRI_D_xx(upd7810_state *cpustate) } /* 74 15: 0111 0100 0001 0101 xxxx xxxx */ -static void XRI_E_xx(upd7810_state *cpustate) +void upd7810_device::XRI_E_xx() { UINT8 imm; RDOPARG( imm ); @@ -6142,7 +6142,7 @@ static void XRI_E_xx(upd7810_state *cpustate) } /* 74 16: 0111 0100 0001 0110 xxxx xxxx */ -static void XRI_H_xx(upd7810_state *cpustate) +void upd7810_device::XRI_H_xx() { UINT8 imm; RDOPARG( imm ); @@ -6151,7 +6151,7 @@ static void XRI_H_xx(upd7810_state *cpustate) } /* 74 17: 0111 0100 0001 0111 xxxx xxxx */ -static void XRI_L_xx(upd7810_state *cpustate) +void upd7810_device::XRI_L_xx() { UINT8 imm; RDOPARG( imm ); @@ -6160,7 +6160,7 @@ static void XRI_L_xx(upd7810_state *cpustate) } /* 74 18: 0111 0100 0001 1000 xxxx xxxx */ -static void ORI_V_xx(upd7810_state *cpustate) +void upd7810_device::ORI_V_xx() { UINT8 imm; RDOPARG( imm ); @@ -6169,7 +6169,7 @@ static void ORI_V_xx(upd7810_state *cpustate) } /* 74 19: 0111 0100 0001 1001 xxxx xxxx */ -static void ORI_A_xx(upd7810_state *cpustate) +void upd7810_device::ORI_A_xx() { UINT8 imm; RDOPARG( imm ); @@ -6178,7 +6178,7 @@ static void ORI_A_xx(upd7810_state *cpustate) } /* 74 1a: 0111 0100 0001 1010 xxxx xxxx */ -static void ORI_B_xx(upd7810_state *cpustate) +void upd7810_device::ORI_B_xx() { UINT8 imm; RDOPARG( imm ); @@ -6187,7 +6187,7 @@ static void ORI_B_xx(upd7810_state *cpustate) } /* 74 1b: 0111 0100 0001 1011 xxxx xxxx */ -static void ORI_C_xx(upd7810_state *cpustate) +void upd7810_device::ORI_C_xx() { UINT8 imm; RDOPARG( imm ); @@ -6196,7 +6196,7 @@ static void ORI_C_xx(upd7810_state *cpustate) } /* 74 1c: 0111 0100 0001 1100 xxxx xxxx */ -static void ORI_D_xx(upd7810_state *cpustate) +void upd7810_device::ORI_D_xx() { UINT8 imm; RDOPARG( imm ); @@ -6205,7 +6205,7 @@ static void ORI_D_xx(upd7810_state *cpustate) } /* 74 1d: 0111 0100 0001 1101 xxxx xxxx */ -static void ORI_E_xx(upd7810_state *cpustate) +void upd7810_device::ORI_E_xx() { UINT8 imm; RDOPARG( imm ); @@ -6214,7 +6214,7 @@ static void ORI_E_xx(upd7810_state *cpustate) } /* 74 1e: 0111 0100 0001 1110 xxxx xxxx */ -static void ORI_H_xx(upd7810_state *cpustate) +void upd7810_device::ORI_H_xx() { UINT8 imm; RDOPARG( imm ); @@ -6223,7 +6223,7 @@ static void ORI_H_xx(upd7810_state *cpustate) } /* 74 1f: 0111 0100 0001 1111 xxxx xxxx */ -static void ORI_L_xx(upd7810_state *cpustate) +void upd7810_device::ORI_L_xx() { UINT8 imm; RDOPARG( imm ); @@ -6232,7 +6232,7 @@ static void ORI_L_xx(upd7810_state *cpustate) } /* 74 20: 0111 0100 0010 0000 xxxx xxxx */ -static void ADINC_V_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_V_xx() { UINT8 tmp, imm; @@ -6245,7 +6245,7 @@ static void ADINC_V_xx(upd7810_state *cpustate) } /* 74 21: 0111 0100 0010 0001 xxxx xxxx */ -static void ADINC_A_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_A_xx() { UINT8 tmp, imm; @@ -6258,7 +6258,7 @@ static void ADINC_A_xx(upd7810_state *cpustate) } /* 74 22: 0111 0100 0010 0010 xxxx xxxx */ -static void ADINC_B_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_B_xx() { UINT8 tmp, imm; @@ -6271,7 +6271,7 @@ static void ADINC_B_xx(upd7810_state *cpustate) } /* 74 23: 0111 0100 0010 0011 xxxx xxxx */ -static void ADINC_C_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_C_xx() { UINT8 tmp, imm; @@ -6284,7 +6284,7 @@ static void ADINC_C_xx(upd7810_state *cpustate) } /* 74 24: 0111 0100 0010 0100 xxxx xxxx */ -static void ADINC_D_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_D_xx() { UINT8 tmp, imm; @@ -6297,7 +6297,7 @@ static void ADINC_D_xx(upd7810_state *cpustate) } /* 74 25: 0111 0100 0010 0101 xxxx xxxx */ -static void ADINC_E_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_E_xx() { UINT8 tmp, imm; @@ -6310,7 +6310,7 @@ static void ADINC_E_xx(upd7810_state *cpustate) } /* 74 26: 0111 0100 0010 0110 xxxx xxxx */ -static void ADINC_H_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_H_xx() { UINT8 tmp, imm; @@ -6323,7 +6323,7 @@ static void ADINC_H_xx(upd7810_state *cpustate) } /* 74 27: 0111 0100 0010 0111 xxxx xxxx */ -static void ADINC_L_xx(upd7810_state *cpustate) +void upd7810_device::ADINC_L_xx() { UINT8 tmp, imm; @@ -6336,7 +6336,7 @@ static void ADINC_L_xx(upd7810_state *cpustate) } /* 74 28: 0111 0100 0010 1000 xxxx xxxx */ -static void GTI_V_xx(upd7810_state *cpustate) +void upd7810_device::GTI_V_xx() { UINT8 imm; UINT16 tmp; @@ -6349,7 +6349,7 @@ static void GTI_V_xx(upd7810_state *cpustate) } /* 74 29: 0111 0100 0010 1001 xxxx xxxx */ -static void GTI_A_xx(upd7810_state *cpustate) +void upd7810_device::GTI_A_xx() { UINT8 imm; UINT16 tmp; @@ -6362,7 +6362,7 @@ static void GTI_A_xx(upd7810_state *cpustate) } /* 74 2a: 0111 0100 0010 1010 xxxx xxxx */ -static void GTI_B_xx(upd7810_state *cpustate) +void upd7810_device::GTI_B_xx() { UINT8 imm; UINT16 tmp; @@ -6375,7 +6375,7 @@ static void GTI_B_xx(upd7810_state *cpustate) } /* 74 2b: 0111 0100 0010 1011 xxxx xxxx */ -static void GTI_C_xx(upd7810_state *cpustate) +void upd7810_device::GTI_C_xx() { UINT8 imm; UINT16 tmp; @@ -6388,7 +6388,7 @@ static void GTI_C_xx(upd7810_state *cpustate) } /* 74 2c: 0111 0100 0010 1100 xxxx xxxx */ -static void GTI_D_xx(upd7810_state *cpustate) +void upd7810_device::GTI_D_xx() { UINT8 imm; UINT16 tmp; @@ -6401,7 +6401,7 @@ static void GTI_D_xx(upd7810_state *cpustate) } /* 74 2d: 0111 0100 0010 1101 xxxx xxxx */ -static void GTI_E_xx(upd7810_state *cpustate) +void upd7810_device::GTI_E_xx() { UINT8 imm; UINT16 tmp; @@ -6414,7 +6414,7 @@ static void GTI_E_xx(upd7810_state *cpustate) } /* 74 2e: 0111 0100 0010 1110 xxxx xxxx */ -static void GTI_H_xx(upd7810_state *cpustate) +void upd7810_device::GTI_H_xx() { UINT8 imm; UINT16 tmp; @@ -6427,7 +6427,7 @@ static void GTI_H_xx(upd7810_state *cpustate) } /* 74 2f: 0111 0100 0010 1111 xxxx xxxx */ -static void GTI_L_xx(upd7810_state *cpustate) +void upd7810_device::GTI_L_xx() { UINT8 imm; UINT16 tmp; @@ -6440,7 +6440,7 @@ static void GTI_L_xx(upd7810_state *cpustate) } /* 74 30: 0111 0100 0011 0000 xxxx xxxx */ -static void SUINB_V_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_V_xx() { UINT8 tmp, imm; @@ -6452,7 +6452,7 @@ static void SUINB_V_xx(upd7810_state *cpustate) } /* 74 31: 0111 0100 0011 0001 xxxx xxxx */ -static void SUINB_A_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_A_xx() { UINT8 tmp, imm; @@ -6464,7 +6464,7 @@ static void SUINB_A_xx(upd7810_state *cpustate) } /* 74 32: 0111 0100 0011 0010 xxxx xxxx */ -static void SUINB_B_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_B_xx() { UINT8 tmp, imm; @@ -6476,7 +6476,7 @@ static void SUINB_B_xx(upd7810_state *cpustate) } /* 74 33: 0111 0100 0011 0011 xxxx xxxx */ -static void SUINB_C_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_C_xx() { UINT8 tmp, imm; @@ -6488,7 +6488,7 @@ static void SUINB_C_xx(upd7810_state *cpustate) } /* 74 34: 0111 0100 0011 0100 xxxx xxxx */ -static void SUINB_D_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_D_xx() { UINT8 tmp, imm; @@ -6500,7 +6500,7 @@ static void SUINB_D_xx(upd7810_state *cpustate) } /* 74 35: 0111 0100 0011 0101 xxxx xxxx */ -static void SUINB_E_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_E_xx() { UINT8 tmp, imm; @@ -6512,7 +6512,7 @@ static void SUINB_E_xx(upd7810_state *cpustate) } /* 74 36: 0111 0100 0011 0110 xxxx xxxx */ -static void SUINB_H_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_H_xx() { UINT8 tmp, imm; @@ -6524,7 +6524,7 @@ static void SUINB_H_xx(upd7810_state *cpustate) } /* 74 37: 0111 0100 0011 0111 xxxx xxxx */ -static void SUINB_L_xx(upd7810_state *cpustate) +void upd7810_device::SUINB_L_xx() { UINT8 tmp, imm; @@ -6536,7 +6536,7 @@ static void SUINB_L_xx(upd7810_state *cpustate) } /* 74 38: 0111 0100 0011 1000 xxxx xxxx */ -static void LTI_V_xx(upd7810_state *cpustate) +void upd7810_device::LTI_V_xx() { UINT8 tmp, imm; @@ -6547,7 +6547,7 @@ static void LTI_V_xx(upd7810_state *cpustate) } /* 74 39: 0111 0100 0011 1001 xxxx xxxx */ -static void LTI_A_xx(upd7810_state *cpustate) +void upd7810_device::LTI_A_xx() { UINT8 tmp, imm; @@ -6558,7 +6558,7 @@ static void LTI_A_xx(upd7810_state *cpustate) } /* 74 3a: 0111 0100 0011 1010 xxxx xxxx */ -static void LTI_B_xx(upd7810_state *cpustate) +void upd7810_device::LTI_B_xx() { UINT8 tmp, imm; @@ -6569,7 +6569,7 @@ static void LTI_B_xx(upd7810_state *cpustate) } /* 74 3b: 0111 0100 0011 1011 xxxx xxxx */ -static void LTI_C_xx(upd7810_state *cpustate) +void upd7810_device::LTI_C_xx() { UINT8 tmp, imm; @@ -6580,7 +6580,7 @@ static void LTI_C_xx(upd7810_state *cpustate) } /* 74 3c: 0111 0100 0011 1100 xxxx xxxx */ -static void LTI_D_xx(upd7810_state *cpustate) +void upd7810_device::LTI_D_xx() { UINT8 tmp, imm; @@ -6591,7 +6591,7 @@ static void LTI_D_xx(upd7810_state *cpustate) } /* 74 3d: 0111 0100 0011 1101 xxxx xxxx */ -static void LTI_E_xx(upd7810_state *cpustate) +void upd7810_device::LTI_E_xx() { UINT8 tmp, imm; @@ -6602,7 +6602,7 @@ static void LTI_E_xx(upd7810_state *cpustate) } /* 74 3e: 0111 0100 0011 1110 xxxx xxxx */ -static void LTI_H_xx(upd7810_state *cpustate) +void upd7810_device::LTI_H_xx() { UINT8 tmp, imm; @@ -6613,7 +6613,7 @@ static void LTI_H_xx(upd7810_state *cpustate) } /* 74 3f: 0111 0100 0011 1111 xxxx xxxx */ -static void LTI_L_xx(upd7810_state *cpustate) +void upd7810_device::LTI_L_xx() { UINT8 tmp, imm; @@ -6624,7 +6624,7 @@ static void LTI_L_xx(upd7810_state *cpustate) } /* 74 40: 0111 0100 0100 0000 xxxx xxxx */ -static void ADI_V_xx(upd7810_state *cpustate) +void upd7810_device::ADI_V_xx() { UINT8 tmp, imm; @@ -6636,7 +6636,7 @@ static void ADI_V_xx(upd7810_state *cpustate) } /* 74 41: 0111 0100 0100 0001 xxxx xxxx */ -static void ADI_A_xx(upd7810_state *cpustate) +void upd7810_device::ADI_A_xx() { UINT8 tmp, imm; @@ -6648,7 +6648,7 @@ static void ADI_A_xx(upd7810_state *cpustate) } /* 74 42: 0111 0100 0100 0010 xxxx xxxx */ -static void ADI_B_xx(upd7810_state *cpustate) +void upd7810_device::ADI_B_xx() { UINT8 tmp, imm; @@ -6660,7 +6660,7 @@ static void ADI_B_xx(upd7810_state *cpustate) } /* 74 43: 0111 0100 0100 0011 xxxx xxxx */ -static void ADI_C_xx(upd7810_state *cpustate) +void upd7810_device::ADI_C_xx() { UINT8 tmp, imm; @@ -6672,7 +6672,7 @@ static void ADI_C_xx(upd7810_state *cpustate) } /* 74 44: 0111 0100 0100 0100 xxxx xxxx */ -static void ADI_D_xx(upd7810_state *cpustate) +void upd7810_device::ADI_D_xx() { UINT8 tmp, imm; @@ -6684,7 +6684,7 @@ static void ADI_D_xx(upd7810_state *cpustate) } /* 74 45: 0111 0100 0100 0101 xxxx xxxx */ -static void ADI_E_xx(upd7810_state *cpustate) +void upd7810_device::ADI_E_xx() { UINT8 tmp, imm; @@ -6696,7 +6696,7 @@ static void ADI_E_xx(upd7810_state *cpustate) } /* 74 46: 0111 0100 0100 0110 xxxx xxxx */ -static void ADI_H_xx(upd7810_state *cpustate) +void upd7810_device::ADI_H_xx() { UINT8 tmp, imm; @@ -6708,7 +6708,7 @@ static void ADI_H_xx(upd7810_state *cpustate) } /* 74 47: 0111 0100 0100 0111 xxxx xxxx */ -static void ADI_L_xx(upd7810_state *cpustate) +void upd7810_device::ADI_L_xx() { UINT8 tmp, imm; @@ -6720,7 +6720,7 @@ static void ADI_L_xx(upd7810_state *cpustate) } /* 74 48: 0111 0100 0100 1000 xxxx xxxx */ -static void ONI_V_xx(upd7810_state *cpustate) +void upd7810_device::ONI_V_xx() { UINT8 imm; @@ -6730,7 +6730,7 @@ static void ONI_V_xx(upd7810_state *cpustate) } /* 74 49: 0111 0100 0100 1001 xxxx xxxx */ -static void ONI_A_xx(upd7810_state *cpustate) +void upd7810_device::ONI_A_xx() { UINT8 imm; @@ -6740,7 +6740,7 @@ static void ONI_A_xx(upd7810_state *cpustate) } /* 74 4a: 0111 0100 0100 1010 xxxx xxxx */ -static void ONI_B_xx(upd7810_state *cpustate) +void upd7810_device::ONI_B_xx() { UINT8 imm; @@ -6750,7 +6750,7 @@ static void ONI_B_xx(upd7810_state *cpustate) } /* 74 4b: 0111 0100 0100 1011 xxxx xxxx */ -static void ONI_C_xx(upd7810_state *cpustate) +void upd7810_device::ONI_C_xx() { UINT8 imm; @@ -6760,7 +6760,7 @@ static void ONI_C_xx(upd7810_state *cpustate) } /* 74 4c: 0111 0100 0100 1100 xxxx xxxx */ -static void ONI_D_xx(upd7810_state *cpustate) +void upd7810_device::ONI_D_xx() { UINT8 imm; @@ -6770,7 +6770,7 @@ static void ONI_D_xx(upd7810_state *cpustate) } /* 74 4d: 0111 0100 0100 1101 xxxx xxxx */ -static void ONI_E_xx(upd7810_state *cpustate) +void upd7810_device::ONI_E_xx() { UINT8 imm; @@ -6780,7 +6780,7 @@ static void ONI_E_xx(upd7810_state *cpustate) } /* 74 4e: 0111 0100 0100 1110 xxxx xxxx */ -static void ONI_H_xx(upd7810_state *cpustate) +void upd7810_device::ONI_H_xx() { UINT8 imm; @@ -6790,7 +6790,7 @@ static void ONI_H_xx(upd7810_state *cpustate) } /* 74 4f: 0111 0100 0100 1111 xxxx xxxx */ -static void ONI_L_xx(upd7810_state *cpustate) +void upd7810_device::ONI_L_xx() { UINT8 imm; @@ -6800,7 +6800,7 @@ static void ONI_L_xx(upd7810_state *cpustate) } /* 74 50: 0111 0100 0101 0000 xxxx xxxx */ -static void ACI_V_xx(upd7810_state *cpustate) +void upd7810_device::ACI_V_xx() { UINT8 tmp, imm; @@ -6811,7 +6811,7 @@ static void ACI_V_xx(upd7810_state *cpustate) } /* 74 51: 0111 0100 0101 0001 xxxx xxxx */ -static void ACI_A_xx(upd7810_state *cpustate) +void upd7810_device::ACI_A_xx() { UINT8 tmp, imm; @@ -6822,7 +6822,7 @@ static void ACI_A_xx(upd7810_state *cpustate) } /* 74 52: 0111 0100 0101 0010 xxxx xxxx */ -static void ACI_B_xx(upd7810_state *cpustate) +void upd7810_device::ACI_B_xx() { UINT8 tmp, imm; @@ -6833,7 +6833,7 @@ static void ACI_B_xx(upd7810_state *cpustate) } /* 74 53: 0111 0100 0101 0011 xxxx xxxx */ -static void ACI_C_xx(upd7810_state *cpustate) +void upd7810_device::ACI_C_xx() { UINT8 tmp, imm; @@ -6844,7 +6844,7 @@ static void ACI_C_xx(upd7810_state *cpustate) } /* 74 54: 0111 0100 0101 0100 xxxx xxxx */ -static void ACI_D_xx(upd7810_state *cpustate) +void upd7810_device::ACI_D_xx() { UINT8 tmp, imm; @@ -6855,7 +6855,7 @@ static void ACI_D_xx(upd7810_state *cpustate) } /* 74 55: 0111 0100 0101 0101 xxxx xxxx */ -static void ACI_E_xx(upd7810_state *cpustate) +void upd7810_device::ACI_E_xx() { UINT8 tmp, imm; @@ -6866,7 +6866,7 @@ static void ACI_E_xx(upd7810_state *cpustate) } /* 74 56: 0111 0100 0101 0110 xxxx xxxx */ -static void ACI_H_xx(upd7810_state *cpustate) +void upd7810_device::ACI_H_xx() { UINT8 tmp, imm; @@ -6877,7 +6877,7 @@ static void ACI_H_xx(upd7810_state *cpustate) } /* 74 57: 0111 0100 0101 0111 xxxx xxxx */ -static void ACI_L_xx(upd7810_state *cpustate) +void upd7810_device::ACI_L_xx() { UINT8 tmp, imm; @@ -6888,7 +6888,7 @@ static void ACI_L_xx(upd7810_state *cpustate) } /* 74 58: 0111 0100 0101 1000 xxxx xxxx */ -static void OFFI_V_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_V_xx() { UINT8 imm; @@ -6898,7 +6898,7 @@ static void OFFI_V_xx(upd7810_state *cpustate) } /* 74 59: 0111 0100 0101 1001 xxxx xxxx */ -static void OFFI_A_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_A_xx() { UINT8 imm; @@ -6908,7 +6908,7 @@ static void OFFI_A_xx(upd7810_state *cpustate) } /* 74 5a: 0111 0100 0101 1010 xxxx xxxx */ -static void OFFI_B_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_B_xx() { UINT8 imm; @@ -6918,7 +6918,7 @@ static void OFFI_B_xx(upd7810_state *cpustate) } /* 74 5b: 0111 0100 0101 1011 xxxx xxxx */ -static void OFFI_C_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_C_xx() { UINT8 imm; @@ -6928,7 +6928,7 @@ static void OFFI_C_xx(upd7810_state *cpustate) } /* 74 5c: 0111 0100 0101 1100 xxxx xxxx */ -static void OFFI_D_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_D_xx() { UINT8 imm; @@ -6938,7 +6938,7 @@ static void OFFI_D_xx(upd7810_state *cpustate) } /* 74 5d: 0111 0100 0101 1101 xxxx xxxx */ -static void OFFI_E_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_E_xx() { UINT8 imm; @@ -6948,7 +6948,7 @@ static void OFFI_E_xx(upd7810_state *cpustate) } /* 74 5e: 0111 0100 0101 1110 xxxx xxxx */ -static void OFFI_H_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_H_xx() { UINT8 imm; @@ -6958,7 +6958,7 @@ static void OFFI_H_xx(upd7810_state *cpustate) } /* 74 5f: 0111 0100 0101 1111 xxxx xxxx */ -static void OFFI_L_xx(upd7810_state *cpustate) +void upd7810_device::OFFI_L_xx() { UINT8 imm; @@ -6968,7 +6968,7 @@ static void OFFI_L_xx(upd7810_state *cpustate) } /* 74 60: 0111 0100 0110 0000 xxxx xxxx */ -static void SUI_V_xx(upd7810_state *cpustate) +void upd7810_device::SUI_V_xx() { UINT8 tmp, imm; @@ -6979,7 +6979,7 @@ static void SUI_V_xx(upd7810_state *cpustate) } /* 74 61: 0111 0100 0110 0001 xxxx xxxx */ -static void SUI_A_xx(upd7810_state *cpustate) +void upd7810_device::SUI_A_xx() { UINT8 tmp, imm; @@ -6990,7 +6990,7 @@ static void SUI_A_xx(upd7810_state *cpustate) } /* 74 62: 0111 0100 0110 0010 xxxx xxxx */ -static void SUI_B_xx(upd7810_state *cpustate) +void upd7810_device::SUI_B_xx() { UINT8 tmp, imm; @@ -7001,7 +7001,7 @@ static void SUI_B_xx(upd7810_state *cpustate) } /* 74 63: 0111 0100 0110 0011 xxxx xxxx */ -static void SUI_C_xx(upd7810_state *cpustate) +void upd7810_device::SUI_C_xx() { UINT8 tmp, imm; @@ -7012,7 +7012,7 @@ static void SUI_C_xx(upd7810_state *cpustate) } /* 74 64: 0111 0100 0110 0100 xxxx xxxx */ -static void SUI_D_xx(upd7810_state *cpustate) +void upd7810_device::SUI_D_xx() { UINT8 tmp, imm; @@ -7023,7 +7023,7 @@ static void SUI_D_xx(upd7810_state *cpustate) } /* 74 65: 0111 0100 0110 0101 xxxx xxxx */ -static void SUI_E_xx(upd7810_state *cpustate) +void upd7810_device::SUI_E_xx() { UINT8 tmp, imm; @@ -7034,7 +7034,7 @@ static void SUI_E_xx(upd7810_state *cpustate) } /* 74 66: 0111 0100 0110 0110 xxxx xxxx */ -static void SUI_H_xx(upd7810_state *cpustate) +void upd7810_device::SUI_H_xx() { UINT8 tmp, imm; @@ -7045,7 +7045,7 @@ static void SUI_H_xx(upd7810_state *cpustate) } /* 74 67: 0111 0100 0110 0111 xxxx xxxx */ -static void SUI_L_xx(upd7810_state *cpustate) +void upd7810_device::SUI_L_xx() { UINT8 tmp, imm; @@ -7056,7 +7056,7 @@ static void SUI_L_xx(upd7810_state *cpustate) } /* 74 68: 0111 0100 0110 1000 xxxx xxxx */ -static void NEI_V_xx(upd7810_state *cpustate) +void upd7810_device::NEI_V_xx() { UINT8 tmp, imm; @@ -7067,7 +7067,7 @@ static void NEI_V_xx(upd7810_state *cpustate) } /* 74 69: 0111 0100 0110 1001 xxxx xxxx */ -static void NEI_A_xx(upd7810_state *cpustate) +void upd7810_device::NEI_A_xx() { UINT8 tmp, imm; @@ -7078,7 +7078,7 @@ static void NEI_A_xx(upd7810_state *cpustate) } /* 74 6a: 0111 0100 0110 1010 xxxx xxxx */ -static void NEI_B_xx(upd7810_state *cpustate) +void upd7810_device::NEI_B_xx() { UINT8 tmp, imm; @@ -7089,7 +7089,7 @@ static void NEI_B_xx(upd7810_state *cpustate) } /* 74 6b: 0111 0100 0110 1011 xxxx xxxx */ -static void NEI_C_xx(upd7810_state *cpustate) +void upd7810_device::NEI_C_xx() { UINT8 tmp, imm; @@ -7100,7 +7100,7 @@ static void NEI_C_xx(upd7810_state *cpustate) } /* 74 6c: 0111 0100 0110 1100 xxxx xxxx */ -static void NEI_D_xx(upd7810_state *cpustate) +void upd7810_device::NEI_D_xx() { UINT8 tmp, imm; @@ -7111,7 +7111,7 @@ static void NEI_D_xx(upd7810_state *cpustate) } /* 74 6d: 0111 0100 0110 1101 xxxx xxxx */ -static void NEI_E_xx(upd7810_state *cpustate) +void upd7810_device::NEI_E_xx() { UINT8 tmp, imm; @@ -7122,7 +7122,7 @@ static void NEI_E_xx(upd7810_state *cpustate) } /* 74 6e: 0111 0100 0110 1110 xxxx xxxx */ -static void NEI_H_xx(upd7810_state *cpustate) +void upd7810_device::NEI_H_xx() { UINT8 tmp, imm; @@ -7133,7 +7133,7 @@ static void NEI_H_xx(upd7810_state *cpustate) } /* 74 6f: 0111 0100 0110 1111 xxxx xxxx */ -static void NEI_L_xx(upd7810_state *cpustate) +void upd7810_device::NEI_L_xx() { UINT8 tmp, imm; @@ -7144,7 +7144,7 @@ static void NEI_L_xx(upd7810_state *cpustate) } /* 74 70: 0111 0100 0111 0000 xxxx xxxx */ -static void SBI_V_xx(upd7810_state *cpustate) +void upd7810_device::SBI_V_xx() { UINT8 tmp, imm; @@ -7155,7 +7155,7 @@ static void SBI_V_xx(upd7810_state *cpustate) } /* 74 71: 0111 0100 0111 0001 xxxx xxxx */ -static void SBI_A_xx(upd7810_state *cpustate) +void upd7810_device::SBI_A_xx() { UINT8 tmp, imm; @@ -7166,7 +7166,7 @@ static void SBI_A_xx(upd7810_state *cpustate) } /* 74 72: 0111 0100 0111 0010 xxxx xxxx */ -static void SBI_B_xx(upd7810_state *cpustate) +void upd7810_device::SBI_B_xx() { UINT8 tmp, imm; @@ -7177,7 +7177,7 @@ static void SBI_B_xx(upd7810_state *cpustate) } /* 74 73: 0111 0100 0111 0011 xxxx xxxx */ -static void SBI_C_xx(upd7810_state *cpustate) +void upd7810_device::SBI_C_xx() { UINT8 tmp, imm; @@ -7188,7 +7188,7 @@ static void SBI_C_xx(upd7810_state *cpustate) } /* 74 74: 0111 0100 0111 0100 xxxx xxxx */ -static void SBI_D_xx(upd7810_state *cpustate) +void upd7810_device::SBI_D_xx() { UINT8 tmp, imm; @@ -7199,7 +7199,7 @@ static void SBI_D_xx(upd7810_state *cpustate) } /* 74 75: 0111 0100 0111 0101 xxxx xxxx */ -static void SBI_E_xx(upd7810_state *cpustate) +void upd7810_device::SBI_E_xx() { UINT8 tmp, imm; @@ -7210,7 +7210,7 @@ static void SBI_E_xx(upd7810_state *cpustate) } /* 74 76: 0111 0100 0111 0110 xxxx xxxx */ -static void SBI_H_xx(upd7810_state *cpustate) +void upd7810_device::SBI_H_xx() { UINT8 tmp, imm; @@ -7221,7 +7221,7 @@ static void SBI_H_xx(upd7810_state *cpustate) } /* 74 77: 0111 0100 0111 0111 xxxx xxxx */ -static void SBI_L_xx(upd7810_state *cpustate) +void upd7810_device::SBI_L_xx() { UINT8 tmp, imm; @@ -7232,7 +7232,7 @@ static void SBI_L_xx(upd7810_state *cpustate) } /* 74 78: 0111 0100 0111 1000 xxxx xxxx */ -static void EQI_V_xx(upd7810_state *cpustate) +void upd7810_device::EQI_V_xx() { UINT8 tmp, imm; @@ -7243,7 +7243,7 @@ static void EQI_V_xx(upd7810_state *cpustate) } /* 74 79: 0111 0100 0111 1001 xxxx xxxx */ -static void EQI_A_xx(upd7810_state *cpustate) +void upd7810_device::EQI_A_xx() { UINT8 tmp, imm; @@ -7254,7 +7254,7 @@ static void EQI_A_xx(upd7810_state *cpustate) } /* 74 7a: 0111 0100 0111 1010 xxxx xxxx */ -static void EQI_B_xx(upd7810_state *cpustate) +void upd7810_device::EQI_B_xx() { UINT8 tmp, imm; @@ -7265,7 +7265,7 @@ static void EQI_B_xx(upd7810_state *cpustate) } /* 74 7b: 0111 0100 0111 1011 xxxx xxxx */ -static void EQI_C_xx(upd7810_state *cpustate) +void upd7810_device::EQI_C_xx() { UINT8 tmp, imm; @@ -7276,7 +7276,7 @@ static void EQI_C_xx(upd7810_state *cpustate) } /* 74 7c: 0111 0100 0111 1100 xxxx xxxx */ -static void EQI_D_xx(upd7810_state *cpustate) +void upd7810_device::EQI_D_xx() { UINT8 tmp, imm; @@ -7287,7 +7287,7 @@ static void EQI_D_xx(upd7810_state *cpustate) } /* 74 7d: 0111 0100 0111 1101 xxxx xxxx */ -static void EQI_E_xx(upd7810_state *cpustate) +void upd7810_device::EQI_E_xx() { UINT8 tmp, imm; @@ -7298,7 +7298,7 @@ static void EQI_E_xx(upd7810_state *cpustate) } /* 74 7e: 0111 0100 0111 1110 xxxx xxxx */ -static void EQI_H_xx(upd7810_state *cpustate) +void upd7810_device::EQI_H_xx() { UINT8 tmp, imm; @@ -7309,7 +7309,7 @@ static void EQI_H_xx(upd7810_state *cpustate) } /* 74 7f: 0111 0100 0111 1111 xxxx xxxx */ -static void EQI_L_xx(upd7810_state *cpustate) +void upd7810_device::EQI_L_xx() { UINT8 tmp, imm; @@ -7320,9 +7320,9 @@ static void EQI_L_xx(upd7810_state *cpustate) } /* 74 88: 0111 0100 1000 1000 oooo oooo */ -static void ANAW_wa(upd7810_state *cpustate) +void upd7810_device::ANAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); A &= RM( ea.d ); @@ -7330,30 +7330,30 @@ static void ANAW_wa(upd7810_state *cpustate) } /* 74 8d: 0111 0100 1000 1101 */ -static void DAN_EA_BC(upd7810_state *cpustate) +void upd7810_device::DAN_EA_BC() { EA &= BC; SET_Z(EA); } /* 74 8e: 0111 0100 1000 1110 */ -static void DAN_EA_DE(upd7810_state *cpustate) +void upd7810_device::DAN_EA_DE() { EA &= DE; SET_Z(EA); } /* 74 8f: 0111 0100 1000 1111 */ -static void DAN_EA_HL(upd7810_state *cpustate) +void upd7810_device::DAN_EA_HL() { EA &= HL; SET_Z(EA); } /* 74 90: 0111 0100 1001 0000 oooo oooo */ -static void XRAW_wa(upd7810_state *cpustate) +void upd7810_device::XRAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); A ^= RM( ea.d ); @@ -7361,30 +7361,30 @@ static void XRAW_wa(upd7810_state *cpustate) } /* 74 95: 0111 0100 1001 0101 */ -static void DXR_EA_BC(upd7810_state *cpustate) +void upd7810_device::DXR_EA_BC() { EA ^= BC; SET_Z(EA); } /* 74 96: 0111 0100 1001 0110 */ -static void DXR_EA_DE(upd7810_state *cpustate) +void upd7810_device::DXR_EA_DE() { EA ^= DE; SET_Z(EA); } /* 74 97: 0111 0100 1001 0111 */ -static void DXR_EA_HL(upd7810_state *cpustate) +void upd7810_device::DXR_EA_HL() { EA ^= HL; SET_Z(EA); } /* 74 98: 0111 0100 1001 1000 oooo oooo */ -static void ORAW_wa(upd7810_state *cpustate) +void upd7810_device::ORAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); A |= RM( ea.d ); @@ -7392,30 +7392,30 @@ static void ORAW_wa(upd7810_state *cpustate) } /* 74 9d: 0111 0100 1001 1101 */ -static void DOR_EA_BC(upd7810_state *cpustate) +void upd7810_device::DOR_EA_BC() { EA |= BC; SET_Z(EA); } /* 74 9e: 0111 0100 1001 1110 */ -static void DOR_EA_DE(upd7810_state *cpustate) +void upd7810_device::DOR_EA_DE() { EA |= DE; SET_Z(EA); } /* 74 9f: 0111 0100 1001 1111 */ -static void DOR_EA_HL(upd7810_state *cpustate) +void upd7810_device::DOR_EA_HL() { EA |= HL; SET_Z(EA); } /* 74 a0: 0111 0100 1010 0000 oooo oooo */ -static void ADDNCW_wa(upd7810_state *cpustate) +void upd7810_device::ADDNCW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); @@ -7427,7 +7427,7 @@ static void ADDNCW_wa(upd7810_state *cpustate) } /* 74 a5: 0111 0100 1010 0101 */ -static void DADDNC_EA_BC(upd7810_state *cpustate) +void upd7810_device::DADDNC_EA_BC() { UINT16 tmp = EA + BC; @@ -7437,7 +7437,7 @@ static void DADDNC_EA_BC(upd7810_state *cpustate) } /* 74 a6: 0111 0100 1010 0110 */ -static void DADDNC_EA_DE(upd7810_state *cpustate) +void upd7810_device::DADDNC_EA_DE() { UINT16 tmp = EA + DE; @@ -7447,7 +7447,7 @@ static void DADDNC_EA_DE(upd7810_state *cpustate) } /* 74 a7: 0111 0100 1010 0111 */ -static void DADDNC_EA_HL(upd7810_state *cpustate) +void upd7810_device::DADDNC_EA_HL() { UINT16 tmp = EA + HL; @@ -7457,9 +7457,9 @@ static void DADDNC_EA_HL(upd7810_state *cpustate) } /* 74 a8: 0111 0100 1010 1000 oooo oooo */ -static void GTAW_wa(upd7810_state *cpustate) +void upd7810_device::GTAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT16 tmp; RDOPARG( ea.b.l ); @@ -7469,7 +7469,7 @@ static void GTAW_wa(upd7810_state *cpustate) } /* 74 ad: 0111 0100 1010 1101 */ -static void DGT_EA_BC(upd7810_state *cpustate) +void upd7810_device::DGT_EA_BC() { UINT32 tmp = EA - BC - 1; ZHC_SUB( tmp, EA, 0 ); @@ -7477,7 +7477,7 @@ static void DGT_EA_BC(upd7810_state *cpustate) } /* 74 ae: 0111 0100 1010 1110 */ -static void DGT_EA_DE(upd7810_state *cpustate) +void upd7810_device::DGT_EA_DE() { UINT32 tmp = EA - DE - 1; ZHC_SUB( tmp, EA, 0 ); @@ -7485,7 +7485,7 @@ static void DGT_EA_DE(upd7810_state *cpustate) } /* 74 af: 0111 0100 1010 1111 */ -static void DGT_EA_HL(upd7810_state *cpustate) +void upd7810_device::DGT_EA_HL() { UINT32 tmp = EA - HL - 1; ZHC_SUB( tmp, EA, 0 ); @@ -7493,9 +7493,9 @@ static void DGT_EA_HL(upd7810_state *cpustate) } /* 74 b0: 0111 0100 1011 0000 oooo oooo */ -static void SUBNBW_wa(upd7810_state *cpustate) +void upd7810_device::SUBNBW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); @@ -7506,7 +7506,7 @@ static void SUBNBW_wa(upd7810_state *cpustate) } /* 74 b5: 0111 0100 1011 0101 */ -static void DSUBNB_EA_BC(upd7810_state *cpustate) +void upd7810_device::DSUBNB_EA_BC() { UINT16 tmp = EA - BC; ZHC_SUB( tmp, EA, 0 ); @@ -7515,7 +7515,7 @@ static void DSUBNB_EA_BC(upd7810_state *cpustate) } /* 74 b6: 0111 0100 1011 0110 */ -static void DSUBNB_EA_DE(upd7810_state *cpustate) +void upd7810_device::DSUBNB_EA_DE() { UINT16 tmp = EA - DE; ZHC_SUB( tmp, EA, 0 ); @@ -7524,7 +7524,7 @@ static void DSUBNB_EA_DE(upd7810_state *cpustate) } /* 74 b7: 0111 0100 1011 0111 */ -static void DSUBNB_EA_HL(upd7810_state *cpustate) +void upd7810_device::DSUBNB_EA_HL() { UINT16 tmp; @@ -7535,9 +7535,9 @@ static void DSUBNB_EA_HL(upd7810_state *cpustate) } /* 74 b8: 0111 0100 1011 1000 oooo oooo */ -static void LTAW_wa(upd7810_state *cpustate) +void upd7810_device::LTAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); @@ -7547,7 +7547,7 @@ static void LTAW_wa(upd7810_state *cpustate) } /* 74 bd: 0111 0100 1011 1101 */ -static void DLT_EA_BC(upd7810_state *cpustate) +void upd7810_device::DLT_EA_BC() { UINT16 tmp = EA - BC; ZHC_SUB( tmp, EA, 0 ); @@ -7555,7 +7555,7 @@ static void DLT_EA_BC(upd7810_state *cpustate) } /* 74 be: 0111 0100 1011 1110 */ -static void DLT_EA_DE(upd7810_state *cpustate) +void upd7810_device::DLT_EA_DE() { UINT16 tmp = EA - DE; ZHC_SUB( tmp, EA, 0 ); @@ -7563,7 +7563,7 @@ static void DLT_EA_DE(upd7810_state *cpustate) } /* 74 bf: 0111 0100 1011 1111 */ -static void DLT_EA_HL(upd7810_state *cpustate) +void upd7810_device::DLT_EA_HL() { UINT16 tmp = EA - HL; ZHC_SUB( tmp, EA, 0 ); @@ -7571,9 +7571,9 @@ static void DLT_EA_HL(upd7810_state *cpustate) } /* 74 c0: 0111 0100 1100 0000 oooo oooo */ -static void ADDW_wa(upd7810_state *cpustate) +void upd7810_device::ADDW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); tmp = A + RM( ea.d ); @@ -7582,7 +7582,7 @@ static void ADDW_wa(upd7810_state *cpustate) } /* 74 c5: 0111 0100 1100 0101 */ -static void DADD_EA_BC(upd7810_state *cpustate) +void upd7810_device::DADD_EA_BC() { UINT16 tmp = EA + BC; ZHC_ADD( tmp, EA, 0 ); @@ -7590,7 +7590,7 @@ static void DADD_EA_BC(upd7810_state *cpustate) } /* 74 c6: 0111 0100 1100 0110 */ -static void DADD_EA_DE(upd7810_state *cpustate) +void upd7810_device::DADD_EA_DE() { UINT16 tmp = EA + DE; ZHC_ADD( tmp, EA, 0 ); @@ -7598,7 +7598,7 @@ static void DADD_EA_DE(upd7810_state *cpustate) } /* 74 c7: 0111 0100 1100 0111 */ -static void DADD_EA_HL(upd7810_state *cpustate) +void upd7810_device::DADD_EA_HL() { UINT16 tmp = EA + HL; ZHC_ADD( tmp, EA, 0 ); @@ -7606,9 +7606,9 @@ static void DADD_EA_HL(upd7810_state *cpustate) } /* 74 c8: 0111 0100 1100 1000 oooo oooo */ -static void ONAW_wa(upd7810_state *cpustate) +void upd7810_device::ONAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); if (A & RM( ea.d )) @@ -7618,7 +7618,7 @@ static void ONAW_wa(upd7810_state *cpustate) } /* 74 cd: 0111 0100 1100 1101 */ -static void DON_EA_BC(upd7810_state *cpustate) +void upd7810_device::DON_EA_BC() { if (EA & BC) PSW = (PSW & ~Z) | SK; @@ -7627,7 +7627,7 @@ static void DON_EA_BC(upd7810_state *cpustate) } /* 74 ce: 0111 0100 1100 1110 */ -static void DON_EA_DE(upd7810_state *cpustate) +void upd7810_device::DON_EA_DE() { if (EA & DE) PSW = (PSW & ~Z) | SK; @@ -7636,7 +7636,7 @@ static void DON_EA_DE(upd7810_state *cpustate) } /* 74 cf: 0111 0100 1100 1111 */ -static void DON_EA_HL(upd7810_state *cpustate) +void upd7810_device::DON_EA_HL() { if (EA & HL) PSW = (PSW & ~Z) | SK; @@ -7645,9 +7645,9 @@ static void DON_EA_HL(upd7810_state *cpustate) } /* 74 d0: 0111 0100 1101 0000 oooo oooo */ -static void ADCW_wa(upd7810_state *cpustate) +void upd7810_device::ADCW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); @@ -7657,7 +7657,7 @@ static void ADCW_wa(upd7810_state *cpustate) } /* 74 d5: 0111 0100 1101 0101 */ -static void DADC_EA_BC(upd7810_state *cpustate) +void upd7810_device::DADC_EA_BC() { UINT16 tmp = EA + BC + (PSW & CY); ZHC_ADD( tmp, EA, (PSW & CY) ); @@ -7665,7 +7665,7 @@ static void DADC_EA_BC(upd7810_state *cpustate) } /* 74 d6: 0111 0100 1101 0110 */ -static void DADC_EA_DE(upd7810_state *cpustate) +void upd7810_device::DADC_EA_DE() { UINT16 tmp = EA + DE + (PSW & CY); ZHC_ADD( tmp, EA, (PSW & CY) ); @@ -7673,7 +7673,7 @@ static void DADC_EA_DE(upd7810_state *cpustate) } /* 74 d7: 0111 0100 1101 0111 */ -static void DADC_EA_HL(upd7810_state *cpustate) +void upd7810_device::DADC_EA_HL() { UINT16 tmp = EA + HL + (PSW & CY); ZHC_ADD( tmp, EA, (PSW & CY) ); @@ -7681,9 +7681,9 @@ static void DADC_EA_HL(upd7810_state *cpustate) } /* 74 d8: 0111 0100 1101 1000 oooo oooo */ -static void OFFAW_wa(upd7810_state *cpustate) +void upd7810_device::OFFAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); if ( A & RM( ea.d ) ) @@ -7693,7 +7693,7 @@ static void OFFAW_wa(upd7810_state *cpustate) } /* 74 dd: 0111 0100 1101 1101 */ -static void DOFF_EA_BC(upd7810_state *cpustate) +void upd7810_device::DOFF_EA_BC() { if ( EA & BC ) PSW &= ~Z; @@ -7702,7 +7702,7 @@ static void DOFF_EA_BC(upd7810_state *cpustate) } /* 74 de: 0111 0100 1101 1110 */ -static void DOFF_EA_DE(upd7810_state *cpustate) +void upd7810_device::DOFF_EA_DE() { if ( EA & DE ) PSW &= ~Z; @@ -7711,7 +7711,7 @@ static void DOFF_EA_DE(upd7810_state *cpustate) } /* 74 df: 0111 0100 1101 1111 */ -static void DOFF_EA_HL(upd7810_state *cpustate) +void upd7810_device::DOFF_EA_HL() { if ( EA & HL ) PSW &= ~Z; @@ -7720,9 +7720,9 @@ static void DOFF_EA_HL(upd7810_state *cpustate) } /* 74 e0: 0111 0100 1110 0000 oooo oooo */ -static void SUBW_wa(upd7810_state *cpustate) +void upd7810_device::SUBW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); @@ -7732,7 +7732,7 @@ static void SUBW_wa(upd7810_state *cpustate) } /* 74 e5: 0111 0100 1110 0101 */ -static void DSUB_EA_BC(upd7810_state *cpustate) +void upd7810_device::DSUB_EA_BC() { UINT16 tmp = EA - BC; ZHC_SUB( tmp, EA, 0 ); @@ -7740,7 +7740,7 @@ static void DSUB_EA_BC(upd7810_state *cpustate) } /* 74 e6: 0111 0100 1110 0110 */ -static void DSUB_EA_DE(upd7810_state *cpustate) +void upd7810_device::DSUB_EA_DE() { UINT16 tmp = EA - DE; ZHC_SUB( tmp, EA, 0 ); @@ -7748,7 +7748,7 @@ static void DSUB_EA_DE(upd7810_state *cpustate) } /* 74 e7: 0111 0100 1110 0111 */ -static void DSUB_EA_HL(upd7810_state *cpustate) +void upd7810_device::DSUB_EA_HL() { UINT16 tmp = EA - HL; ZHC_SUB( tmp, EA, 0 ); @@ -7756,9 +7756,9 @@ static void DSUB_EA_HL(upd7810_state *cpustate) } /* 74 e8: 0111 0100 1110 1000 oooo oooo */ -static void NEAW_wa(upd7810_state *cpustate) +void upd7810_device::NEAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); @@ -7768,7 +7768,7 @@ static void NEAW_wa(upd7810_state *cpustate) } /* 74 ed: 0111 0100 1110 1101 */ -static void DNE_EA_BC(upd7810_state *cpustate) +void upd7810_device::DNE_EA_BC() { UINT16 tmp; @@ -7778,7 +7778,7 @@ static void DNE_EA_BC(upd7810_state *cpustate) } /* 74 ee: 0111 0100 1110 1110 */ -static void DNE_EA_DE(upd7810_state *cpustate) +void upd7810_device::DNE_EA_DE() { UINT16 tmp; @@ -7788,7 +7788,7 @@ static void DNE_EA_DE(upd7810_state *cpustate) } /* 74 ef: 0111 0100 1110 1111 */ -static void DNE_EA_HL(upd7810_state *cpustate) +void upd7810_device::DNE_EA_HL() { UINT16 tmp; @@ -7798,9 +7798,9 @@ static void DNE_EA_HL(upd7810_state *cpustate) } /* 74 f0: 0111 0100 1111 0000 oooo oooo */ -static void SBBW_wa(upd7810_state *cpustate) +void upd7810_device::SBBW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); @@ -7810,7 +7810,7 @@ static void SBBW_wa(upd7810_state *cpustate) } /* 74 f5: 0111 0100 1111 0101 */ -static void DSBB_EA_BC(upd7810_state *cpustate) +void upd7810_device::DSBB_EA_BC() { UINT16 tmp = EA - BC - (PSW & CY); ZHC_SUB( tmp, EA, (PSW & CY) ); @@ -7818,7 +7818,7 @@ static void DSBB_EA_BC(upd7810_state *cpustate) } /* 74 f6: 0111 0100 1111 0110 */ -static void DSBB_EA_DE(upd7810_state *cpustate) +void upd7810_device::DSBB_EA_DE() { UINT16 tmp = EA - DE - (PSW & CY); ZHC_SUB( tmp, EA, (PSW & CY) ); @@ -7826,7 +7826,7 @@ static void DSBB_EA_DE(upd7810_state *cpustate) } /* 74 f7: 0111 0100 1111 0111 */ -static void DSBB_EA_HL(upd7810_state *cpustate) +void upd7810_device::DSBB_EA_HL() { UINT16 tmp = EA - HL - (PSW & CY); ZHC_SUB( tmp, EA, (PSW & CY) ); @@ -7834,9 +7834,9 @@ static void DSBB_EA_HL(upd7810_state *cpustate) } /* 74 f8: 0111 0100 1111 1000 oooo oooo */ -static void EQAW_wa(upd7810_state *cpustate) +void upd7810_device::EQAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp; RDOPARG( ea.b.l ); @@ -7846,7 +7846,7 @@ static void EQAW_wa(upd7810_state *cpustate) } /* 74 fd: 0111 0100 1111 1101 */ -static void DEQ_EA_BC(upd7810_state *cpustate) +void upd7810_device::DEQ_EA_BC() { UINT16 tmp; @@ -7856,7 +7856,7 @@ static void DEQ_EA_BC(upd7810_state *cpustate) } /* 74 fe: 0111 0100 1111 1110 */ -static void DEQ_EA_DE(upd7810_state *cpustate) +void upd7810_device::DEQ_EA_DE() { UINT16 tmp; @@ -7866,7 +7866,7 @@ static void DEQ_EA_DE(upd7810_state *cpustate) } /* 74 ff: 0111 0100 1111 1111 */ -static void DEQ_EA_HL(upd7810_state *cpustate) +void upd7810_device::DEQ_EA_HL() { UINT16 tmp; @@ -7880,14 +7880,14 @@ static void DEQ_EA_HL(upd7810_state *cpustate) ************************************************/ /* 00: 0000 0000 */ -static void NOP(upd7810_state *cpustate) +void upd7810_device::NOP() { } /* 01: 0000 0001 oooo oooo */ -static void LDAW_wa(upd7810_state *cpustate) +void upd7810_device::LDAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -7895,28 +7895,28 @@ static void LDAW_wa(upd7810_state *cpustate) } /* 02: 0000 0010 */ -static void INX_SP(upd7810_state *cpustate) +void upd7810_device::INX_SP() { SP++; } /* 03: 0000 0011 */ -static void DCX_SP(upd7810_state *cpustate) +void upd7810_device::DCX_SP() { SP--; } /* 04: 0000 0100 llll llll hhhh hhhh */ -static void LXI_S_w(upd7810_state *cpustate) +void upd7810_device::LXI_S_w() { RDOPARG( SPL ); RDOPARG( SPH ); } /* 05: 0000 0101 oooo oooo xxxx xxxx */ -static void ANIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::ANIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 m, imm; RDOPARG( ea.b.l ); @@ -7931,55 +7931,55 @@ static void ANIW_wa_xx(upd7810_state *cpustate) /* ANI_A_xx already defined (long form) */ /* 08: 0000 1000 */ -static void MOV_A_EAH(upd7810_state *cpustate) +void upd7810_device::MOV_A_EAH() { A = EAH; } /* 09: 0000 1001 */ -static void MOV_A_EAL(upd7810_state *cpustate) +void upd7810_device::MOV_A_EAL() { A = EAL; } /* 0a: 0000 1010 */ -static void MOV_A_B(upd7810_state *cpustate) +void upd7810_device::MOV_A_B() { A = B; } /* 0b: 0000 1011 */ -static void MOV_A_C(upd7810_state *cpustate) +void upd7810_device::MOV_A_C() { A = C; } /* 0c: 0000 1100 */ -static void MOV_A_D(upd7810_state *cpustate) +void upd7810_device::MOV_A_D() { A = D; } /* 0d: 0000 1101 */ -static void MOV_A_E(upd7810_state *cpustate) +void upd7810_device::MOV_A_E() { A = E; } /* 0e: 0000 1110 */ -static void MOV_A_H(upd7810_state *cpustate) +void upd7810_device::MOV_A_H() { A = H; } /* 0f: 0000 1111 */ -static void MOV_A_L(upd7810_state *cpustate) +void upd7810_device::MOV_A_L() { A = L; } /* 10: 0001 0000 */ -static void EXA(upd7810_state *cpustate) +void upd7810_device::EXA() { UINT16 tmp; tmp = EA; EA = EA2; EA2 = tmp; @@ -7987,7 +7987,7 @@ static void EXA(upd7810_state *cpustate) } /* 11: 0001 0001 */ -static void EXX(upd7810_state *cpustate) +void upd7810_device::EXX() { UINT16 tmp; tmp = BC; BC = BC2; BC2 = tmp; @@ -7996,7 +7996,7 @@ static void EXX(upd7810_state *cpustate) } /* 48 AD (7807 only) */ -static void EXR(upd7810_state *cpustate) +void upd7810_device::EXR() { UINT16 tmp; tmp = BC; BC = BC2; BC2 = tmp; @@ -8007,28 +8007,28 @@ static void EXR(upd7810_state *cpustate) } /* 12: 0001 0010 */ -static void INX_BC(upd7810_state *cpustate) +void upd7810_device::INX_BC() { BC++; } /* 13: 0001 0011 */ -static void DCX_BC(upd7810_state *cpustate) +void upd7810_device::DCX_BC() { BC--; } /* 14: 0001 0100 llll llll hhhh hhhh */ -static void LXI_B_w(upd7810_state *cpustate) +void upd7810_device::LXI_B_w() { RDOPARG( C ); RDOPARG( B ); } /* 15: 0001 0101 oooo oooo xxxx xxxx */ -static void ORIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::ORIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 m, imm; RDOPARG( ea.b.l ); @@ -8046,57 +8046,57 @@ static void ORIW_wa_xx(upd7810_state *cpustate) /* ORI_A_xx already defined (long form) */ /* 18: 0001 1000 */ -static void MOV_EAH_A(upd7810_state *cpustate) +void upd7810_device::MOV_EAH_A() { EAH = A; } /* 19: 0001 1001 */ -static void MOV_EAL_A(upd7810_state *cpustate) +void upd7810_device::MOV_EAL_A() { EAL = A; } /* 1a: 0001 1010 */ -static void MOV_B_A(upd7810_state *cpustate) +void upd7810_device::MOV_B_A() { B = A; } /* 1b: 0001 1011 */ -static void MOV_C_A(upd7810_state *cpustate) +void upd7810_device::MOV_C_A() { C = A; } /* 1c: 0001 1100 */ -static void MOV_D_A(upd7810_state *cpustate) +void upd7810_device::MOV_D_A() { D = A; } /* 1d: 0001 1101 */ -static void MOV_E_A(upd7810_state *cpustate) +void upd7810_device::MOV_E_A() { E = A; } /* 1e: 0001 1110 */ -static void MOV_H_A(upd7810_state *cpustate) +void upd7810_device::MOV_H_A() { H = A; } /* 1f: 0001 1111 */ -static void MOV_L_A(upd7810_state *cpustate) +void upd7810_device::MOV_L_A() { L = A; } /* 20: 0010 0000 oooo oooo */ -static void INRW_wa(upd7810_state *cpustate) +void upd7810_device::INRW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp, m; RDOPARG( ea.b.l ); @@ -8108,34 +8108,34 @@ static void INRW_wa(upd7810_state *cpustate) } /* 21: 0010 0001 */ -static void JB(upd7810_state *cpustate) +void upd7810_device::JB() { PC = BC; } /* 22: 0010 0010 */ -static void INX_DE(upd7810_state *cpustate) +void upd7810_device::INX_DE() { DE++; } /* 23: 0010 0011 */ -static void DCX_DE(upd7810_state *cpustate) +void upd7810_device::DCX_DE() { DE--; } /* 24: 0010 0100 llll llll hhhh hhhh */ -static void LXI_D_w(upd7810_state *cpustate) +void upd7810_device::LXI_D_w() { RDOPARG( E ); RDOPARG( D ); } /* 25: 0010 0101 oooo oooo xxxx xxxx */ -static void GTIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::GTIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 m, imm; UINT16 tmp; @@ -8154,55 +8154,55 @@ static void GTIW_wa_xx(upd7810_state *cpustate) /* GTI_A_xx already defined (long form) */ /* 29: 0010 1001 */ -static void LDAX_B(upd7810_state *cpustate) +void upd7810_device::LDAX_B() { A = RM( BC ); } /* 2a: 0010 1010 */ -static void LDAX_D(upd7810_state *cpustate) +void upd7810_device::LDAX_D() { A = RM( DE ); } /* 2b: 0010 1011 */ -static void LDAX_H(upd7810_state *cpustate) +void upd7810_device::LDAX_H() { A = RM( HL ); } /* 2c: 0010 1100 */ -static void LDAX_Dp(upd7810_state *cpustate) +void upd7810_device::LDAX_Dp() { A = RM( DE ); DE++; } /* 2d: 0010 1101 dddd dddd */ -static void LDAX_Hp(upd7810_state *cpustate) +void upd7810_device::LDAX_Hp() { A = RM( HL ); HL++; } /* 2e: 0010 1110 dddd dddd */ -static void LDAX_Dm(upd7810_state *cpustate) +void upd7810_device::LDAX_Dm() { A = RM( DE ); DE--; } /* 2f: 0010 1111 dddd dddd */ -static void LDAX_Hm(upd7810_state *cpustate) +void upd7810_device::LDAX_Hm() { A = RM( HL ); HL--; } /* 30: 0011 0000 oooo oooo */ -static void DCRW_wa(upd7810_state *cpustate) +void upd7810_device::DCRW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp, m; RDOPARG( ea.b.l ); @@ -8214,7 +8214,7 @@ static void DCRW_wa(upd7810_state *cpustate) } /* 31: 0011 0001 */ -static void BLOCK(upd7810_state *cpustate) +void upd7810_device::BLOCK() { WM( DE, RM( HL ) ); DE++; @@ -8230,19 +8230,19 @@ static void BLOCK(upd7810_state *cpustate) } /* 32: 0011 0010 */ -static void INX_HL(upd7810_state *cpustate) +void upd7810_device::INX_HL() { HL++; } /* 33: 0011 0011 */ -static void DCX_HL(upd7810_state *cpustate) +void upd7810_device::DCX_HL() { HL--; } /* 34: 0011 0100 llll llll hhhh hhhh */ -static void LXI_H_w(upd7810_state *cpustate) +void upd7810_device::LXI_H_w() { if (PSW & L0) { /* overlay active? */ PC+=2; @@ -8254,9 +8254,9 @@ static void LXI_H_w(upd7810_state *cpustate) } /* 35: 0011 0101 oooo oooo xxxx xxxx */ -static void LTIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::LTIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp, m, imm; RDOPARG( ea.b.l ); @@ -8274,53 +8274,53 @@ static void LTIW_wa_xx(upd7810_state *cpustate) /* LTI_A_xx already defined (long form) */ /* 39: 0011 1001 */ -static void STAX_B(upd7810_state *cpustate) +void upd7810_device::STAX_B() { WM( BC, A ); } /* 3a: 0011 1010 */ -static void STAX_D(upd7810_state *cpustate) +void upd7810_device::STAX_D() { WM( DE, A ); } /* 3b: 0011 1011 */ -static void STAX_H(upd7810_state *cpustate) +void upd7810_device::STAX_H() { WM( HL, A ); } /* 3c: 0011 1100 */ -static void STAX_Dp(upd7810_state *cpustate) +void upd7810_device::STAX_Dp() { WM( DE, A ); DE++; } /* 3d: 0011 1101 */ -static void STAX_Hp(upd7810_state *cpustate) +void upd7810_device::STAX_Hp() { WM( HL, A ); HL++; } /* 3e: 0011 1110 */ -static void STAX_Dm(upd7810_state *cpustate) +void upd7810_device::STAX_Dm() { WM( DE, A ); DE--; } /* 3f: 0011 1111 */ -static void STAX_Hm(upd7810_state *cpustate) +void upd7810_device::STAX_Hm() { WM( HL, A ); HL--; } /* 40: 0100 0000 llll llll hhhh hhhh */ -static void CALL_w(upd7810_state *cpustate) +void upd7810_device::CALL_w() { PAIR w; w.d = 0; @@ -8337,7 +8337,7 @@ static void CALL_w(upd7810_state *cpustate) } /* 41: 0100 0001 */ -static void INR_A(upd7810_state *cpustate) +void upd7810_device::INR_A() { UINT8 tmp = A + 1; ZHC_ADD( tmp, A, 0 ); @@ -8346,7 +8346,7 @@ static void INR_A(upd7810_state *cpustate) } /* 42: 0100 0010 */ -static void INR_B(upd7810_state *cpustate) +void upd7810_device::INR_B() { UINT8 tmp = B + 1; ZHC_ADD( tmp, B, 0 ); @@ -8355,7 +8355,7 @@ static void INR_B(upd7810_state *cpustate) } /* 43: 0100 0011 */ -static void INR_C(upd7810_state *cpustate) +void upd7810_device::INR_C() { UINT8 tmp = C + 1; ZHC_ADD( tmp, C, 0 ); @@ -8364,16 +8364,16 @@ static void INR_C(upd7810_state *cpustate) } /* 44: 0100 0100 llll llll hhhh hhhh */ -static void LXI_EA_s(upd7810_state *cpustate) +void upd7810_device::LXI_EA_s() { RDOPARG( EAL ); RDOPARG( EAH ); } /* 45: 0100 0101 oooo oooo xxxx xxxx */ -static void ONIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::ONIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 imm; RDOPARG( ea.b.l ); @@ -8390,16 +8390,16 @@ static void ONIW_wa_xx(upd7810_state *cpustate) /* ONI_A_xx already defined (long form) */ /* 48: prefix */ -static void PRE_48(upd7810_state *cpustate) +void upd7810_device::PRE_48() { RDOP(OP2); - cpustate->icount -= cpustate->op48[OP2].cycles; - cpustate->handle_timers(cpustate, cpustate->op48[OP2].cycles); - (*cpustate->op48[OP2].opfunc)(cpustate); + m_icount -= m_op48[OP2].cycles; + handle_timers(m_op48[OP2].cycles); + (this->*m_op48[OP2].opfunc)(); } /* 49: 0100 1001 xxxx xxxx */ -static void MVIX_BC_xx(upd7810_state *cpustate) +void upd7810_device::MVIX_BC_xx() { UINT8 imm; RDOPARG( imm ); @@ -8407,7 +8407,7 @@ static void MVIX_BC_xx(upd7810_state *cpustate) } /* 4a: 0100 1010 xxxx xxxx */ -static void MVIX_DE_xx(upd7810_state *cpustate) +void upd7810_device::MVIX_DE_xx() { UINT8 imm; RDOPARG( imm ); @@ -8415,7 +8415,7 @@ static void MVIX_DE_xx(upd7810_state *cpustate) } /* 4b: 0100 1011 xxxx xxxx */ -static void MVIX_HL_xx(upd7810_state *cpustate) +void upd7810_device::MVIX_HL_xx() { UINT8 imm; RDOPARG( imm ); @@ -8423,25 +8423,25 @@ static void MVIX_HL_xx(upd7810_state *cpustate) } /* 4c: prefix */ -static void PRE_4C(upd7810_state *cpustate) +void upd7810_device::PRE_4C() { RDOP(OP2); - cpustate->icount -= cpustate->op4C[OP2].cycles; - cpustate->handle_timers(cpustate, cpustate->op4C[OP2].cycles); - (*cpustate->op4C[OP2].opfunc)(cpustate); + m_icount -= m_op4C[OP2].cycles; + handle_timers(m_op4C[OP2].cycles); + (this->*m_op4C[OP2].opfunc)(); } /* 4d: prefix */ -static void PRE_4D(upd7810_state *cpustate) +void upd7810_device::PRE_4D() { RDOP(OP2); - cpustate->icount -= cpustate->op4D[OP2].cycles; - cpustate->handle_timers(cpustate, cpustate->op4D[OP2].cycles); - (*cpustate->op4D[OP2].opfunc)(cpustate); + m_icount -= m_op4D[OP2].cycles; + handle_timers(m_op4D[OP2].cycles); + (this->*m_op4D[OP2].opfunc)(); } /* 4e: 0100 111d dddd dddd */ -static void JRE(upd7810_state *cpustate) +void upd7810_device::JRE() { UINT8 offs; RDOPARG( offs ); @@ -8452,14 +8452,14 @@ static void JRE(upd7810_state *cpustate) } /* 50: 0101 0000 */ -static void EXH(upd7810_state *cpustate) +void upd7810_device::EXH() { UINT16 tmp; tmp = HL; HL = HL2; HL2 = tmp; } /* 51: 0101 0001 */ -static void DCR_A(upd7810_state *cpustate) +void upd7810_device::DCR_A() { UINT8 tmp = A - 1; ZHC_SUB( tmp, A, 0 ); @@ -8468,7 +8468,7 @@ static void DCR_A(upd7810_state *cpustate) } /* 52: 0101 0010 */ -static void DCR_B(upd7810_state *cpustate) +void upd7810_device::DCR_B() { UINT8 tmp = B - 1; ZHC_SUB( tmp, B, 0 ); @@ -8477,7 +8477,7 @@ static void DCR_B(upd7810_state *cpustate) } /* 53: 0101 0011 */ -static void DCR_C(upd7810_state *cpustate) +void upd7810_device::DCR_C() { UINT8 tmp = C - 1; ZHC_SUB( tmp, C, 0 ); @@ -8486,7 +8486,7 @@ static void DCR_C(upd7810_state *cpustate) } /* 54: 0101 0100 llll llll hhhh hhhh */ -static void JMP_w(upd7810_state *cpustate) +void upd7810_device::JMP_w() { PAIR w; w.d = 0; @@ -8498,9 +8498,9 @@ static void JMP_w(upd7810_state *cpustate) } /* 55: 0101 0101 oooo oooo xxxx xxxx */ -static void OFFIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::OFFIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 imm; RDOPARG( ea.b.l ); @@ -8517,9 +8517,9 @@ static void OFFIW_wa_xx(upd7810_state *cpustate) /* OFFI_A_xx already defined (long form) */ /* 58: 0101 1000 oooo oooo (7810 only) */ -static void BIT_0_wa(upd7810_state *cpustate) +void upd7810_device::BIT_0_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8528,9 +8528,9 @@ static void BIT_0_wa(upd7810_state *cpustate) } /* 59: 0101 1001 oooo oooo (7810 only) */ -static void BIT_1_wa(upd7810_state *cpustate) +void upd7810_device::BIT_1_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8539,9 +8539,9 @@ static void BIT_1_wa(upd7810_state *cpustate) } /* 5a: 0101 1010 oooo oooo (7810 only) */ -static void BIT_2_wa(upd7810_state *cpustate) +void upd7810_device::BIT_2_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8550,9 +8550,9 @@ static void BIT_2_wa(upd7810_state *cpustate) } /* 5b: 0101 1011 oooo oooo (7810 only) */ -static void BIT_3_wa(upd7810_state *cpustate) +void upd7810_device::BIT_3_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8561,9 +8561,9 @@ static void BIT_3_wa(upd7810_state *cpustate) } /* 5c: 0101 1100 oooo oooo (7810 only) */ -static void BIT_4_wa(upd7810_state *cpustate) +void upd7810_device::BIT_4_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8572,9 +8572,9 @@ static void BIT_4_wa(upd7810_state *cpustate) } /* 5d: 0101 1101 oooo oooo (7810 only) */ -static void BIT_5_wa(upd7810_state *cpustate) +void upd7810_device::BIT_5_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8583,9 +8583,9 @@ static void BIT_5_wa(upd7810_state *cpustate) } /* 5e: 0101 1110 oooo oooo (7810 only) */ -static void BIT_6_wa(upd7810_state *cpustate) +void upd7810_device::BIT_6_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8594,9 +8594,9 @@ static void BIT_6_wa(upd7810_state *cpustate) } /* 5f: 0101 1111 oooo oooo (7810 only) */ -static void BIT_7_wa(upd7810_state *cpustate) +void upd7810_device::BIT_7_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8605,7 +8605,7 @@ static void BIT_7_wa(upd7810_state *cpustate) } /* 5d: 0101 1111 bbbb bbbb (7807 only) */ -static void SKN_bit(upd7810_state *cpustate) +void upd7810_device::SKN_bit() { UINT8 imm; int val; @@ -8615,19 +8615,19 @@ static void SKN_bit(upd7810_state *cpustate) switch( imm & 0x1f ) { case 0x10: /* PA */ - val = RP( cpustate, UPD7810_PORTA ); + val = RP( UPD7810_PORTA ); break; case 0x11: /* PB */ - val = RP( cpustate, UPD7810_PORTB ); + val = RP( UPD7810_PORTB ); break; case 0x12: /* PC */ - val = RP( cpustate, UPD7810_PORTC ); + val = RP( UPD7810_PORTC ); break; case 0x13: /* PD */ - val = RP( cpustate, UPD7810_PORTD ); + val = RP( UPD7810_PORTD ); break; case 0x15: /* PF */ - val = RP( cpustate, UPD7810_PORTF ); + val = RP( UPD7810_PORTF ); break; case 0x16: /* MKH */ val = MKH; @@ -8645,10 +8645,10 @@ static void SKN_bit(upd7810_state *cpustate) val = TMM; break; case 0x1e: /* PT */ - val = RP( cpustate, UPD7807_PORTT ); + val = RP( UPD7807_PORTT ); break; default: - logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", cpustate->device->tag(), OP, imm, PC); + logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC); val = 0; break; } @@ -8658,7 +8658,7 @@ static void SKN_bit(upd7810_state *cpustate) } /* 58: 0101 1000 bbbb bbbb (7807 only) */ -static void SETB(upd7810_state *cpustate) +void upd7810_device::SETB() { UINT8 imm; int bit; @@ -8669,19 +8669,19 @@ static void SETB(upd7810_state *cpustate) switch( imm & 0x1f ) { case 0x10: /* PA */ - WP( cpustate, UPD7810_PORTA, RP( cpustate, UPD7810_PORTA ) | (1 << bit)); + WP( UPD7810_PORTA, RP( UPD7810_PORTA ) | (1 << bit)); break; case 0x11: /* PB */ - WP( cpustate, UPD7810_PORTB, RP( cpustate, UPD7810_PORTB ) | (1 << bit)); + WP( UPD7810_PORTB, RP( UPD7810_PORTB ) | (1 << bit)); break; case 0x12: /* PC */ - WP( cpustate, UPD7810_PORTC, RP( cpustate, UPD7810_PORTC ) | (1 << bit)); + WP( UPD7810_PORTC, RP( UPD7810_PORTC ) | (1 << bit)); break; case 0x13: /* PD */ - WP( cpustate, UPD7810_PORTD, RP( cpustate, UPD7810_PORTD ) | (1 << bit)); + WP( UPD7810_PORTD, RP( UPD7810_PORTD ) | (1 << bit)); break; case 0x15: /* PF */ - WP( cpustate, UPD7810_PORTF, RP( cpustate, UPD7810_PORTF ) | (1 << bit)); + WP( UPD7810_PORTF, RP( UPD7810_PORTF ) | (1 << bit)); break; case 0x16: /* MKH */ MKH |= (1 << bit); @@ -8702,13 +8702,13 @@ static void SETB(upd7810_state *cpustate) // PT is input only // break; default: - logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", cpustate->device->tag(), OP, imm, PC); + logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC); break; } } /* 5b: 0101 1011 bbbb bbbb (7807 only) */ -static void CLR(upd7810_state *cpustate) +void upd7810_device::CLR() { UINT8 imm; int bit; @@ -8719,19 +8719,19 @@ static void CLR(upd7810_state *cpustate) switch( imm & 0x1f ) { case 0x10: /* PA */ - WP( cpustate, UPD7810_PORTA, RP( cpustate, UPD7810_PORTA ) & ~(1 << bit)); + WP( UPD7810_PORTA, RP( UPD7810_PORTA ) & ~(1 << bit)); break; case 0x11: /* PB */ - WP( cpustate, UPD7810_PORTB, RP( cpustate, UPD7810_PORTB ) & ~(1 << bit)); + WP( UPD7810_PORTB, RP( UPD7810_PORTB ) & ~(1 << bit)); break; case 0x12: /* PC */ - WP( cpustate, UPD7810_PORTC, RP( cpustate, UPD7810_PORTC ) & ~(1 << bit)); + WP( UPD7810_PORTC, RP( UPD7810_PORTC ) & ~(1 << bit)); break; case 0x13: /* PD */ - WP( cpustate, UPD7810_PORTD, RP( cpustate, UPD7810_PORTD ) & ~(1 << bit)); + WP( UPD7810_PORTD, RP( UPD7810_PORTD ) & ~(1 << bit)); break; case 0x15: /* PF */ - WP( cpustate, UPD7810_PORTF, RP( cpustate, UPD7810_PORTF ) & ~(1 << bit)); + WP( UPD7810_PORTF, RP( UPD7810_PORTF ) & ~(1 << bit)); break; case 0x16: /* MKH */ MKH &= ~(1 << bit); @@ -8752,13 +8752,13 @@ static void CLR(upd7810_state *cpustate) // PT is input only // break; default: - logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", cpustate->device->tag(), OP, imm, PC); + logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC); break; } } /* 5d: 0101 1111 bbbb bbbb (7807 only) */ -static void SK_bit(upd7810_state *cpustate) +void upd7810_device::SK_bit() { UINT8 imm; int val; @@ -8768,19 +8768,19 @@ static void SK_bit(upd7810_state *cpustate) switch( imm & 0x1f ) { case 0x10: /* PA */ - val = RP( cpustate, UPD7810_PORTA ); + val = RP( UPD7810_PORTA ); break; case 0x11: /* PB */ - val = RP( cpustate, UPD7810_PORTB ); + val = RP( UPD7810_PORTB ); break; case 0x12: /* PC */ - val = RP( cpustate, UPD7810_PORTC ); + val = RP( UPD7810_PORTC ); break; case 0x13: /* PD */ - val = RP( cpustate, UPD7810_PORTD ); + val = RP( UPD7810_PORTD ); break; case 0x15: /* PF */ - val = RP( cpustate, UPD7810_PORTF ); + val = RP( UPD7810_PORTF ); break; case 0x16: /* MKH */ val = MKH; @@ -8798,10 +8798,10 @@ static void SK_bit(upd7810_state *cpustate) val = TMM; break; case 0x1e: /* PT */ - val = RP( cpustate, UPD7807_PORTT ); + val = RP( UPD7807_PORTT ); break; default: - logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", cpustate->device->tag(), OP, imm, PC); + logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", tag(), OP, imm, PC); val = 0; break; } @@ -8811,16 +8811,16 @@ static void SK_bit(upd7810_state *cpustate) } /* 60:*/ -static void PRE_60(upd7810_state *cpustate) +void upd7810_device::PRE_60() { RDOP(OP2); - cpustate->icount -= cpustate->op60[OP2].cycles; - cpustate->handle_timers(cpustate, cpustate->op60[OP2].cycles); - (*cpustate->op60[OP2].opfunc)(cpustate); + m_icount -= m_op60[OP2].cycles; + handle_timers(m_op60[OP2].cycles); + (this->*m_op60[OP2].opfunc)(); } /* 61: 0110 0001 */ -static void DAA(upd7810_state *cpustate) +void upd7810_device::DAA() { UINT8 l = A & 0x0f, h = A >> 4, tmp, adj = 0x00, old_cy = PSW & CY; @@ -8854,7 +8854,7 @@ static void DAA(upd7810_state *cpustate) } /* 62: 0110 0010 */ -static void RETI(upd7810_state *cpustate) +void upd7810_device::RETI() { PCL = RM( SPD ); SP++; @@ -8865,9 +8865,9 @@ static void RETI(upd7810_state *cpustate) } /* 63: 0110 0011 oooo oooo */ -static void STAW_wa(upd7810_state *cpustate) +void upd7810_device::STAW_wa() { - PAIR ea = cpustate->va; + PAIR ea = m_va; RDOPARG( ea.b.l ); @@ -8875,18 +8875,18 @@ static void STAW_wa(upd7810_state *cpustate) } /* 64: prefix */ -static void PRE_64(upd7810_state *cpustate) +void upd7810_device::PRE_64() { RDOP(OP2); - cpustate->icount -= cpustate->op64[OP2].cycles; - cpustate->handle_timers(cpustate, cpustate->op64[OP2].cycles); - (*cpustate->op64[OP2].opfunc)(cpustate); + m_icount -= m_op64[OP2].cycles; + handle_timers(m_op64[OP2].cycles); + (this->*m_op64[OP2].opfunc)(); } /* 65: 0110 0101 oooo oooo xxxx xxxx */ -static void NEIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::NEIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp, m, imm; RDOPARG( ea.b.l ); @@ -8904,13 +8904,13 @@ static void NEIW_wa_xx(upd7810_state *cpustate) /* NEI_A_xx already defined (long form) */ /* 68: 0110 1000 xxxx xxxx */ -static void MVI_V_xx(upd7810_state *cpustate) +void upd7810_device::MVI_V_xx() { RDOPARG( V ); } /* 69: 0110 1001 xxxx xxxx */ -static void MVI_A_xx(upd7810_state *cpustate) +void upd7810_device::MVI_A_xx() { if (PSW & L1) { /* overlay active? */ PC++; @@ -8921,37 +8921,37 @@ static void MVI_A_xx(upd7810_state *cpustate) } /* 6a: 0110 1010 xxxx xxxx */ -static void MVI_B_xx(upd7810_state *cpustate) +void upd7810_device::MVI_B_xx() { RDOPARG( B ); } /* 6b: 0110 1011 xxxx xxxx */ -static void MVI_C_xx(upd7810_state *cpustate) +void upd7810_device::MVI_C_xx() { RDOPARG( C ); } /* 6c: 0110 1100 xxxx xxxx */ -static void MVI_D_xx(upd7810_state *cpustate) +void upd7810_device::MVI_D_xx() { RDOPARG( D ); } /* 6d: 0110 1101 xxxx xxxx */ -static void MVI_E_xx(upd7810_state *cpustate) +void upd7810_device::MVI_E_xx() { RDOPARG( E ); } /* 6e: 0110 1110 xxxx xxxx */ -static void MVI_H_xx(upd7810_state *cpustate) +void upd7810_device::MVI_H_xx() { RDOPARG( H ); } /* 6f: 0110 1111 xxxx xxxx */ -static void MVI_L_xx(upd7810_state *cpustate) +void upd7810_device::MVI_L_xx() { if (PSW & L0) { /* overlay active? */ PC++; @@ -8962,18 +8962,18 @@ static void MVI_L_xx(upd7810_state *cpustate) } /* 70: prefix */ -static void PRE_70(upd7810_state *cpustate) +void upd7810_device::PRE_70() { RDOP(OP2); - cpustate->icount -= cpustate->op70[OP2].cycles; - cpustate->handle_timers(cpustate, cpustate->op70[OP2].cycles); - (*cpustate->op70[OP2].opfunc)(cpustate); + m_icount -= m_op70[OP2].cycles; + handle_timers(m_op70[OP2].cycles); + (this->*m_op70[OP2].opfunc)(); } /* 71: 0111 0001 oooo oooo xxxx xxxx */ -static void MVIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::MVIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 imm; RDOPARG( ea.b.l ); @@ -8983,7 +8983,7 @@ static void MVIW_wa_xx(upd7810_state *cpustate) } /* 72: 0111 0010 */ -static void SOFTI(upd7810_state *cpustate) +void upd7810_device::SOFTI() { SP--; WM( SPD, PSW ); @@ -8996,18 +8996,18 @@ static void SOFTI(upd7810_state *cpustate) } /* 74: prefix */ -static void PRE_74(upd7810_state *cpustate) +void upd7810_device::PRE_74() { RDOP(OP2); - cpustate->icount -= cpustate->op74[OP2].cycles; - cpustate->handle_timers(cpustate, cpustate->op74[OP2].cycles); - (*cpustate->op74[OP2].opfunc)(cpustate); + m_icount -= m_op74[OP2].cycles; + handle_timers(m_op74[OP2].cycles); + (this->*m_op74[OP2].opfunc)(); } /* 75: 0111 0101 oooo oooo xxxx xxxx */ -static void EQIW_wa_xx(upd7810_state *cpustate) +void upd7810_device::EQIW_wa_xx() { - PAIR ea = cpustate->va; + PAIR ea = m_va; UINT8 tmp, m, imm; RDOPARG( ea.b.l ); @@ -9025,7 +9025,7 @@ static void EQIW_wa_xx(upd7810_state *cpustate) /* EQI_A_xx already defined (long form) */ /* 78: 0111 1ddd dddd dddd */ -static void CALF(upd7810_state *cpustate) +void upd7810_device::CALF() { PAIR w; w.d = 0; @@ -9042,7 +9042,7 @@ static void CALF(upd7810_state *cpustate) } /* 80: 100t tttt */ -static void CALT(upd7810_state *cpustate) +void upd7810_device::CALT() { PAIR w; w.d = 0; @@ -9059,7 +9059,7 @@ static void CALT(upd7810_state *cpustate) } /* a0: 1010 0000 */ -static void POP_VA(upd7810_state *cpustate) +void upd7810_device::POP_VA() { A = RM( SPD ); SP++; @@ -9068,7 +9068,7 @@ static void POP_VA(upd7810_state *cpustate) } /* a1: 1010 0001 */ -static void POP_BC(upd7810_state *cpustate) +void upd7810_device::POP_BC() { C = RM( SPD ); SP++; @@ -9077,7 +9077,7 @@ static void POP_BC(upd7810_state *cpustate) } /* a2: 1010 0010 */ -static void POP_DE(upd7810_state *cpustate) +void upd7810_device::POP_DE() { E = RM( SPD ); SP++; @@ -9086,7 +9086,7 @@ static void POP_DE(upd7810_state *cpustate) } /* a3: 1010 0011 */ -static void POP_HL(upd7810_state *cpustate) +void upd7810_device::POP_HL() { L = RM( SPD ); SP++; @@ -9095,7 +9095,7 @@ static void POP_HL(upd7810_state *cpustate) } /* a4: 1010 0100 */ -static void POP_EA(upd7810_state *cpustate) +void upd7810_device::POP_EA() { EAL = RM( SPD ); SP++; @@ -9104,43 +9104,43 @@ static void POP_EA(upd7810_state *cpustate) } /* a5: 1010 0101 */ -static void DMOV_EA_BC(upd7810_state *cpustate) +void upd7810_device::DMOV_EA_BC() { EA = BC; } /* a6: 1010 0110 */ -static void DMOV_EA_DE(upd7810_state *cpustate) +void upd7810_device::DMOV_EA_DE() { EA = DE; } /* a7: 1010 0111 */ -static void DMOV_EA_HL(upd7810_state *cpustate) +void upd7810_device::DMOV_EA_HL() { EA = HL; } /* a8: 1010 1000 */ -static void INX_EA(upd7810_state *cpustate) +void upd7810_device::INX_EA() { EA++; } /* a9: 1010 1001 */ -static void DCX_EA(upd7810_state *cpustate) +void upd7810_device::DCX_EA() { EA--; } /* aa: 1010 1010 */ -static void EI(upd7810_state *cpustate) +void upd7810_device::EI() { IFF = 1; } /* ab: 1010 1011 dddd dddd */ -static void LDAX_D_xx(upd7810_state *cpustate) +void upd7810_device::LDAX_D_xx() { UINT16 ea; RDOPARG( ea ); @@ -9149,7 +9149,7 @@ static void LDAX_D_xx(upd7810_state *cpustate) } /* ac: 1010 1100 */ -static void LDAX_H_A(upd7810_state *cpustate) +void upd7810_device::LDAX_H_A() { UINT16 ea; ea = HL + A; @@ -9157,7 +9157,7 @@ static void LDAX_H_A(upd7810_state *cpustate) } /* ad: 1010 1101 */ -static void LDAX_H_B(upd7810_state *cpustate) +void upd7810_device::LDAX_H_B() { UINT16 ea; ea = HL + B; @@ -9165,7 +9165,7 @@ static void LDAX_H_B(upd7810_state *cpustate) } /* ae: 1010 1110 */ -static void LDAX_H_EA(upd7810_state *cpustate) +void upd7810_device::LDAX_H_EA() { UINT16 ea; ea = HL + EA; @@ -9173,7 +9173,7 @@ static void LDAX_H_EA(upd7810_state *cpustate) } /* af: 1010 1111 dddd dddd */ -static void LDAX_H_xx(upd7810_state *cpustate) +void upd7810_device::LDAX_H_xx() { UINT16 ea; RDOPARG( ea ); @@ -9182,7 +9182,7 @@ static void LDAX_H_xx(upd7810_state *cpustate) } /* b0: 1011 0000 */ -static void PUSH_VA(upd7810_state *cpustate) +void upd7810_device::PUSH_VA() { SP--; WM( SPD, V ); @@ -9191,7 +9191,7 @@ static void PUSH_VA(upd7810_state *cpustate) } /* b1: 1011 0001 */ -static void PUSH_BC(upd7810_state *cpustate) +void upd7810_device::PUSH_BC() { SP--; WM( SPD, B ); @@ -9200,7 +9200,7 @@ static void PUSH_BC(upd7810_state *cpustate) } /* b2: 1011 0010 */ -static void PUSH_DE(upd7810_state *cpustate) +void upd7810_device::PUSH_DE() { SP--; WM( SPD, D ); @@ -9209,7 +9209,7 @@ static void PUSH_DE(upd7810_state *cpustate) } /* b3: 1011 0011 */ -static void PUSH_HL(upd7810_state *cpustate) +void upd7810_device::PUSH_HL() { SP--; WM( SPD, H ); @@ -9218,7 +9218,7 @@ static void PUSH_HL(upd7810_state *cpustate) } /* b4: 1011 0100 */ -static void PUSH_EA(upd7810_state *cpustate) +void upd7810_device::PUSH_EA() { SP--; WM( SPD, EAH ); @@ -9227,25 +9227,25 @@ static void PUSH_EA(upd7810_state *cpustate) } /* b5: 1011 0101 */ -static void DMOV_BC_EA(upd7810_state *cpustate) +void upd7810_device::DMOV_BC_EA() { BC = EA; } /* b6: 1011 0110 */ -static void DMOV_DE_EA(upd7810_state *cpustate) +void upd7810_device::DMOV_DE_EA() { DE = EA; } /* b7: 1011 0111 */ -static void DMOV_HL_EA(upd7810_state *cpustate) +void upd7810_device::DMOV_HL_EA() { HL = EA; } /* b8: 1011 1000 */ -static void RET(upd7810_state *cpustate) +void upd7810_device::RET() { PCL = RM( SPD ); SP++; @@ -9254,7 +9254,7 @@ static void RET(upd7810_state *cpustate) } /* b9: 1011 1001 */ -static void RETS(upd7810_state *cpustate) +void upd7810_device::RETS() { PCL = RM( SPD ); SP++; @@ -9264,13 +9264,13 @@ static void RETS(upd7810_state *cpustate) } /* ba: 1011 1010 */ -static void DI(upd7810_state *cpustate) +void upd7810_device::DI() { IFF = 0; } /* bb: 1011 1011 dddd dddd */ -static void STAX_D_xx(upd7810_state *cpustate) +void upd7810_device::STAX_D_xx() { UINT16 ea; RDOPARG(ea); @@ -9279,7 +9279,7 @@ static void STAX_D_xx(upd7810_state *cpustate) } /* bc: 1011 1100 */ -static void STAX_H_A(upd7810_state *cpustate) +void upd7810_device::STAX_H_A() { UINT16 ea = A; ea += HL; @@ -9287,7 +9287,7 @@ static void STAX_H_A(upd7810_state *cpustate) } /* bd: 1011 1101 */ -static void STAX_H_B(upd7810_state *cpustate) +void upd7810_device::STAX_H_B() { UINT16 ea = B; ea += HL; @@ -9295,7 +9295,7 @@ static void STAX_H_B(upd7810_state *cpustate) } /* be: 1011 1110 */ -static void STAX_H_EA(upd7810_state *cpustate) +void upd7810_device::STAX_H_EA() { UINT16 ea = EA; ea += HL; @@ -9303,7 +9303,7 @@ static void STAX_H_EA(upd7810_state *cpustate) } /* bf: 1011 1111 dddd dddd */ -static void STAX_H_xx(upd7810_state *cpustate) +void upd7810_device::STAX_H_xx() { UINT16 ea; RDOPARG( ea ); @@ -9312,7 +9312,7 @@ static void STAX_H_xx(upd7810_state *cpustate) } /* c0: 11dd dddd */ -static void JR(upd7810_state *cpustate) +void upd7810_device::JR() { INT8 offs = (INT8)(OP << 2) >> 2; PC += offs; @@ -9324,7 +9324,7 @@ static void JR(upd7810_state *cpustate) /* */ /*********************/ -static void CALT_7801(upd7810_state *cpustate) +void upd7810_device::CALT_7801() { PAIR w; w.d = 0; @@ -9341,131 +9341,130 @@ static void CALT_7801(upd7810_state *cpustate) } /* DCR(W) and INR(W) instructions do not modify the CY register on at least 78c05 and 78c06 */ -static void DCR_A_7801(upd7810_state *cpustate) +void upd7810_device::DCR_A_7801() { UINT32 old_CY = PSW & CY; - DCR_A(cpustate); + DCR_A(); PSW = ( PSW & ~CY ) | old_CY; } -static void DCR_B_7801(upd7810_state *cpustate) +void upd7810_device::DCR_B_7801() { UINT32 old_CY = PSW & CY; - DCR_B(cpustate); + DCR_B(); PSW = ( PSW & ~CY ) | old_CY; } -static void DCR_C_7801(upd7810_state *cpustate) +void upd7810_device::DCR_C_7801() { UINT32 old_CY = PSW & CY; - DCR_C(cpustate); + DCR_C(); PSW = ( PSW & ~CY ) | old_CY; } -static void DCRW_wa_7801(upd7810_state *cpustate) +void upd7810_device::DCRW_wa_7801() { UINT32 old_CY = PSW & CY; - DCRW_wa(cpustate); + DCRW_wa(); PSW = ( PSW & ~CY ) | old_CY; } -static void INR_A_7801(upd7810_state *cpustate) +void upd7810_device::INR_A_7801() { UINT32 old_CY = PSW & CY; - INR_A(cpustate); + INR_A(); PSW = ( PSW & ~CY ) | old_CY; } -static void INR_B_7801(upd7810_state *cpustate) +void upd7810_device::INR_B_7801() { UINT32 old_CY = PSW & CY; - INR_B(cpustate); + INR_B(); PSW = ( PSW & ~CY ) | old_CY; } -static void INR_C_7801(upd7810_state *cpustate) +void upd7810_device::INR_C_7801() { UINT32 old_CY = PSW & CY; - INR_C(cpustate); + INR_C(); PSW = ( PSW & ~CY ) | old_CY; } -static void INRW_wa_7801(upd7810_state *cpustate) +void upd7810_device::INRW_wa_7801() { UINT32 old_CY = PSW & CY; - INRW_wa(cpustate); + INRW_wa(); PSW = ( PSW & ~CY ) | old_CY; } -static void IN(upd7810_state *cpustate) +void upd7810_device::IN() { logerror("unimplemented instruction: IN\n"); } -static void OUT(upd7810_state *cpustate) +void upd7810_device::OUT() { logerror("unimplemented instruction: OUT\n"); } -static void MOV_A_S(upd7810_state *cpustate) +void upd7810_device::MOV_A_S() { logerror("unimplemented instruction: MOV_A_S\n"); } -static void MOV_S_A(upd7810_state *cpustate) +void upd7810_device::MOV_S_A() { logerror("unimplemented instruction: MOV_A_S\n"); } -static void PEN(upd7810_state *cpustate) +void upd7810_device::PEN() { logerror("unimplemented instruction: PEN\n"); } -static void PER(upd7810_state *cpustate) +void upd7810_device::PER() { logerror("unimplemented instruction: PER\n"); } -static void PEX(upd7810_state *cpustate) +void upd7810_device::PEX() { logerror("unimplemented instruction: PEX\n"); } -static void SIO(upd7810_state *cpustate) +void upd7810_device::SIO() { logerror("unimplemented instruction: SIO\n"); } -static void SKIT_F0(upd7810_state *cpustate) +void upd7810_device::SKIT_F0() { if (IRR & INTF0) PSW |= SK; IRR &= ~INTF0; } -static void SKNIT_F0(upd7810_state *cpustate) +void upd7810_device::SKNIT_F0() { logerror("unimplemented instruction: SKNIT_F0\n"); } -static void STM(upd7810_state *cpustate) +void upd7810_device::STM() { - cpustate->ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0; + m_ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0; } -static void STM_7801(upd7810_state *cpustate) +void upd7810_device::STM_7801() { /* Set the timer flip/fliop */ TO = 1; - if ( cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); /* Reload the timer */ - cpustate->ovc0 = 16 * ( TM0 + ( ( TM1 & 0x0f ) << 8 ) ); + m_ovc0 = 16 * ( TM0 + ( ( TM1 & 0x0f ) << 8 ) ); } -static void MOV_MC_A_7801(upd7810_state *cpustate) +void upd7810_device::MOV_MC_A_7801() { /* On the 7801 the mode C bits function as follows: */ /* Cn=1 Cn=0 */ diff --git a/src/emu/cpu/upd7810/7810tbl.c b/src/emu/cpu/upd7810/7810tbl.c index 9f3377dacab..a83ec07476e 100644 --- a/src/emu/cpu/upd7810/7810tbl.c +++ b/src/emu/cpu/upd7810/7810tbl.c @@ -7,3531 +7,2492 @@ * *****************************************************************************/ -static void illegal(upd7810_state *cpustate); -static void illegal2(upd7810_state *cpustate); - -static void ACI_ANM_xx(upd7810_state *cpustate); -static void ACI_A_xx(upd7810_state *cpustate); -static void ACI_B_xx(upd7810_state *cpustate); -static void ACI_C_xx(upd7810_state *cpustate); -static void ACI_D_xx(upd7810_state *cpustate); -static void ACI_EOM_xx(upd7810_state *cpustate); -static void ACI_E_xx(upd7810_state *cpustate); -static void ACI_H_xx(upd7810_state *cpustate); -static void ACI_L_xx(upd7810_state *cpustate); -static void ACI_MKH_xx(upd7810_state *cpustate); -static void ACI_MKL_xx(upd7810_state *cpustate); -static void ACI_PA_xx(upd7810_state *cpustate); -static void ACI_PB_xx(upd7810_state *cpustate); -static void ACI_PC_xx(upd7810_state *cpustate); -static void ACI_PD_xx(upd7810_state *cpustate); -static void ACI_PF_xx(upd7810_state *cpustate); -static void ACI_SMH_xx(upd7810_state *cpustate); -static void ACI_TMM_xx(upd7810_state *cpustate); -static void ACI_V_xx(upd7810_state *cpustate); -static void ADCW_wa(upd7810_state *cpustate); -static void ADCX_B(upd7810_state *cpustate); -static void ADCX_D(upd7810_state *cpustate); -static void ADCX_Dm(upd7810_state *cpustate); -static void ADCX_Dp(upd7810_state *cpustate); -static void ADCX_H(upd7810_state *cpustate); -static void ADCX_Hm(upd7810_state *cpustate); -static void ADCX_Hp(upd7810_state *cpustate); -static void ADC_A_A(upd7810_state *cpustate); -static void ADC_A_A(upd7810_state *cpustate); -static void ADC_A_B(upd7810_state *cpustate); -static void ADC_A_C(upd7810_state *cpustate); -static void ADC_A_D(upd7810_state *cpustate); -static void ADC_A_E(upd7810_state *cpustate); -static void ADC_A_H(upd7810_state *cpustate); -static void ADC_A_L(upd7810_state *cpustate); -static void ADC_A_V(upd7810_state *cpustate); -static void ADC_B_A(upd7810_state *cpustate); -static void ADC_C_A(upd7810_state *cpustate); -static void ADC_D_A(upd7810_state *cpustate); -static void ADC_E_A(upd7810_state *cpustate); -static void ADC_H_A(upd7810_state *cpustate); -static void ADC_L_A(upd7810_state *cpustate); -static void ADC_V_A(upd7810_state *cpustate); -static void ADDNCW_wa(upd7810_state *cpustate); -static void ADDNCX_B(upd7810_state *cpustate); -static void ADDNCX_D(upd7810_state *cpustate); -static void ADDNCX_Dm(upd7810_state *cpustate); -static void ADDNCX_Dp(upd7810_state *cpustate); -static void ADDNCX_H(upd7810_state *cpustate); -static void ADDNCX_Hm(upd7810_state *cpustate); -static void ADDNCX_Hp(upd7810_state *cpustate); -static void ADDNC_A_A(upd7810_state *cpustate); -static void ADDNC_A_A(upd7810_state *cpustate); -static void ADDNC_A_B(upd7810_state *cpustate); -static void ADDNC_A_C(upd7810_state *cpustate); -static void ADDNC_A_D(upd7810_state *cpustate); -static void ADDNC_A_E(upd7810_state *cpustate); -static void ADDNC_A_H(upd7810_state *cpustate); -static void ADDNC_A_L(upd7810_state *cpustate); -static void ADDNC_A_V(upd7810_state *cpustate); -static void ADDNC_B_A(upd7810_state *cpustate); -static void ADDNC_C_A(upd7810_state *cpustate); -static void ADDNC_D_A(upd7810_state *cpustate); -static void ADDNC_E_A(upd7810_state *cpustate); -static void ADDNC_H_A(upd7810_state *cpustate); -static void ADDNC_L_A(upd7810_state *cpustate); -static void ADDNC_V_A(upd7810_state *cpustate); -static void ADDW_wa(upd7810_state *cpustate); -static void ADDX_B(upd7810_state *cpustate); -static void ADDX_D(upd7810_state *cpustate); -static void ADDX_Dm(upd7810_state *cpustate); -static void ADDX_Dp(upd7810_state *cpustate); -static void ADDX_H(upd7810_state *cpustate); -static void ADDX_Hm(upd7810_state *cpustate); -static void ADDX_Hp(upd7810_state *cpustate); -static void ADD_A_A(upd7810_state *cpustate); -static void ADD_A_A(upd7810_state *cpustate); -static void ADD_A_B(upd7810_state *cpustate); -static void ADD_A_C(upd7810_state *cpustate); -static void ADD_A_D(upd7810_state *cpustate); -static void ADD_A_E(upd7810_state *cpustate); -static void ADD_A_H(upd7810_state *cpustate); -static void ADD_A_L(upd7810_state *cpustate); -static void ADD_A_V(upd7810_state *cpustate); -static void ADD_B_A(upd7810_state *cpustate); -static void ADD_C_A(upd7810_state *cpustate); -static void ADD_D_A(upd7810_state *cpustate); -static void ADD_E_A(upd7810_state *cpustate); -static void ADD_H_A(upd7810_state *cpustate); -static void ADD_L_A(upd7810_state *cpustate); -static void ADD_V_A(upd7810_state *cpustate); -static void ADINC_ANM_xx(upd7810_state *cpustate); -static void ADINC_A_xx(upd7810_state *cpustate); -static void ADINC_A_xx(upd7810_state *cpustate); -static void ADINC_B_xx(upd7810_state *cpustate); -static void ADINC_C_xx(upd7810_state *cpustate); -static void ADINC_D_xx(upd7810_state *cpustate); -static void ADINC_EOM_xx(upd7810_state *cpustate); -static void ADINC_E_xx(upd7810_state *cpustate); -static void ADINC_H_xx(upd7810_state *cpustate); -static void ADINC_L_xx(upd7810_state *cpustate); -static void ADINC_MKH_xx(upd7810_state *cpustate); -static void ADINC_MKL_xx(upd7810_state *cpustate); -static void ADINC_PA_xx(upd7810_state *cpustate); -static void ADINC_PB_xx(upd7810_state *cpustate); -static void ADINC_PC_xx(upd7810_state *cpustate); -static void ADINC_PD_xx(upd7810_state *cpustate); -static void ADINC_PF_xx(upd7810_state *cpustate); -static void ADINC_SMH_xx(upd7810_state *cpustate); -static void ADINC_TMM_xx(upd7810_state *cpustate); -static void ADINC_V_xx(upd7810_state *cpustate); -static void ADI_ANM_xx(upd7810_state *cpustate); -static void ADI_A_xx(upd7810_state *cpustate); -static void ADI_A_xx(upd7810_state *cpustate); -static void ADI_B_xx(upd7810_state *cpustate); -static void ADI_C_xx(upd7810_state *cpustate); -static void ADI_D_xx(upd7810_state *cpustate); -static void ADI_EOM_xx(upd7810_state *cpustate); -static void ADI_E_xx(upd7810_state *cpustate); -static void ADI_H_xx(upd7810_state *cpustate); -static void ADI_L_xx(upd7810_state *cpustate); -static void ADI_MKH_xx(upd7810_state *cpustate); -static void ADI_MKL_xx(upd7810_state *cpustate); -static void ADI_PA_xx(upd7810_state *cpustate); -static void ADI_PB_xx(upd7810_state *cpustate); -static void ADI_PC_xx(upd7810_state *cpustate); -static void ADI_PD_xx(upd7810_state *cpustate); -static void ADI_PF_xx(upd7810_state *cpustate); -static void ADI_SMH_xx(upd7810_state *cpustate); -static void ADI_TMM_xx(upd7810_state *cpustate); -static void ADI_V_xx(upd7810_state *cpustate); -static void ANAW_wa(upd7810_state *cpustate); -static void ANAX_B(upd7810_state *cpustate); -static void ANAX_D(upd7810_state *cpustate); -static void ANAX_Dm(upd7810_state *cpustate); -static void ANAX_Dp(upd7810_state *cpustate); -static void ANAX_H(upd7810_state *cpustate); -static void ANAX_Hm(upd7810_state *cpustate); -static void ANAX_Hp(upd7810_state *cpustate); -static void ANA_A_A(upd7810_state *cpustate); -static void ANA_A_A(upd7810_state *cpustate); -static void ANA_A_B(upd7810_state *cpustate); -static void ANA_A_C(upd7810_state *cpustate); -static void ANA_A_D(upd7810_state *cpustate); -static void ANA_A_E(upd7810_state *cpustate); -static void ANA_A_H(upd7810_state *cpustate); -static void ANA_A_L(upd7810_state *cpustate); -static void ANA_A_V(upd7810_state *cpustate); -static void ANA_B_A(upd7810_state *cpustate); -static void ANA_C_A(upd7810_state *cpustate); -static void ANA_D_A(upd7810_state *cpustate); -static void ANA_E_A(upd7810_state *cpustate); -static void ANA_H_A(upd7810_state *cpustate); -static void ANA_L_A(upd7810_state *cpustate); -static void ANA_V_A(upd7810_state *cpustate); -static void ANIW_wa_xx(upd7810_state *cpustate); -static void ANI_ANM_xx(upd7810_state *cpustate); -static void ANI_A_xx(upd7810_state *cpustate); -static void ANI_A_xx(upd7810_state *cpustate); -static void ANI_B_xx(upd7810_state *cpustate); -static void ANI_C_xx(upd7810_state *cpustate); -static void ANI_D_xx(upd7810_state *cpustate); -static void ANI_EOM_xx(upd7810_state *cpustate); -static void ANI_E_xx(upd7810_state *cpustate); -static void ANI_H_xx(upd7810_state *cpustate); -static void ANI_L_xx(upd7810_state *cpustate); -static void ANI_MKH_xx(upd7810_state *cpustate); -static void ANI_MKL_xx(upd7810_state *cpustate); -static void ANI_PA_xx(upd7810_state *cpustate); -static void ANI_PB_xx(upd7810_state *cpustate); -static void ANI_PC_xx(upd7810_state *cpustate); -static void ANI_PD_xx(upd7810_state *cpustate); -static void ANI_PF_xx(upd7810_state *cpustate); -static void ANI_SMH_xx(upd7810_state *cpustate); -static void ANI_TMM_xx(upd7810_state *cpustate); -static void ANI_V_xx(upd7810_state *cpustate); -static void BIT_0_wa(upd7810_state *cpustate); -static void BIT_1_wa(upd7810_state *cpustate); -static void BIT_2_wa(upd7810_state *cpustate); -static void BIT_3_wa(upd7810_state *cpustate); -static void BIT_4_wa(upd7810_state *cpustate); -static void BIT_5_wa(upd7810_state *cpustate); -static void BIT_6_wa(upd7810_state *cpustate); -static void BIT_7_wa(upd7810_state *cpustate); -static void BLOCK(upd7810_state *cpustate); -static void CALB(upd7810_state *cpustate); -static void CALF(upd7810_state *cpustate); -static void CALL_w(upd7810_state *cpustate); -static void CALT(upd7810_state *cpustate); -static void CLC(upd7810_state *cpustate); -static void CLR(upd7810_state *cpustate); -static void DAA(upd7810_state *cpustate); -static void DADC_EA_BC(upd7810_state *cpustate); -static void DADC_EA_DE(upd7810_state *cpustate); -static void DADC_EA_HL(upd7810_state *cpustate); -static void DADDNC_EA_BC(upd7810_state *cpustate); -static void DADDNC_EA_DE(upd7810_state *cpustate); -static void DADDNC_EA_HL(upd7810_state *cpustate); -static void DADD_EA_BC(upd7810_state *cpustate); -static void DADD_EA_DE(upd7810_state *cpustate); -static void DADD_EA_HL(upd7810_state *cpustate); -static void DAN_EA_BC(upd7810_state *cpustate); -static void DAN_EA_DE(upd7810_state *cpustate); -static void DAN_EA_HL(upd7810_state *cpustate); -static void DCRW_wa(upd7810_state *cpustate); -static void DCR_A(upd7810_state *cpustate); -static void DCR_B(upd7810_state *cpustate); -static void DCR_C(upd7810_state *cpustate); -static void DCX_BC(upd7810_state *cpustate); -static void DCX_DE(upd7810_state *cpustate); -static void DCX_EA(upd7810_state *cpustate); -static void DCX_HL(upd7810_state *cpustate); -static void DCX_SP(upd7810_state *cpustate); -static void DEQ_EA_BC(upd7810_state *cpustate); -static void DEQ_EA_DE(upd7810_state *cpustate); -static void DEQ_EA_HL(upd7810_state *cpustate); -static void DGT_EA_BC(upd7810_state *cpustate); -static void DGT_EA_DE(upd7810_state *cpustate); -static void DGT_EA_HL(upd7810_state *cpustate); -static void DI(upd7810_state *cpustate); -static void DIV_A(upd7810_state *cpustate); -static void DIV_B(upd7810_state *cpustate); -static void DIV_C(upd7810_state *cpustate); -static void DLT_EA_BC(upd7810_state *cpustate); -static void DLT_EA_DE(upd7810_state *cpustate); -static void DLT_EA_HL(upd7810_state *cpustate); -static void DMOV_BC_EA(upd7810_state *cpustate); -static void DMOV_DE_EA(upd7810_state *cpustate); -static void DMOV_EA_BC(upd7810_state *cpustate); -static void DMOV_EA_DE(upd7810_state *cpustate); -static void DMOV_EA_ECNT(upd7810_state *cpustate); -static void DMOV_EA_ECPT(upd7810_state *cpustate); -static void DMOV_EA_HL(upd7810_state *cpustate); -static void DMOV_ETM0_EA(upd7810_state *cpustate); -static void DMOV_ETM1_EA(upd7810_state *cpustate); -static void DMOV_HL_EA(upd7810_state *cpustate); -static void DNE_EA_BC(upd7810_state *cpustate); -static void DNE_EA_DE(upd7810_state *cpustate); -static void DNE_EA_HL(upd7810_state *cpustate); -static void DOFF_EA_BC(upd7810_state *cpustate); -static void DOFF_EA_DE(upd7810_state *cpustate); -static void DOFF_EA_HL(upd7810_state *cpustate); -static void DON_EA_BC(upd7810_state *cpustate); -static void DON_EA_DE(upd7810_state *cpustate); -static void DON_EA_HL(upd7810_state *cpustate); -static void DOR_EA_BC(upd7810_state *cpustate); -static void DOR_EA_DE(upd7810_state *cpustate); -static void DOR_EA_HL(upd7810_state *cpustate); -static void DRLL_EA(upd7810_state *cpustate); -static void DRLR_EA(upd7810_state *cpustate); -static void DSBB_EA_BC(upd7810_state *cpustate); -static void DSBB_EA_DE(upd7810_state *cpustate); -static void DSBB_EA_HL(upd7810_state *cpustate); -static void DSLL_EA(upd7810_state *cpustate); -static void DSLR_EA(upd7810_state *cpustate); -static void DSUBNB_EA_BC(upd7810_state *cpustate); -static void DSUBNB_EA_DE(upd7810_state *cpustate); -static void DSUBNB_EA_HL(upd7810_state *cpustate); -static void DSUB_EA_BC(upd7810_state *cpustate); -static void DSUB_EA_DE(upd7810_state *cpustate); -static void DSUB_EA_HL(upd7810_state *cpustate); -static void DXR_EA_BC(upd7810_state *cpustate); -static void DXR_EA_DE(upd7810_state *cpustate); -static void DXR_EA_HL(upd7810_state *cpustate); -static void EADD_EA_A(upd7810_state *cpustate); -static void EADD_EA_B(upd7810_state *cpustate); -static void EADD_EA_C(upd7810_state *cpustate); -static void EI(upd7810_state *cpustate); -static void EQAW_wa(upd7810_state *cpustate); -static void EQAX_B(upd7810_state *cpustate); -static void EQAX_D(upd7810_state *cpustate); -static void EQAX_Dm(upd7810_state *cpustate); -static void EQAX_Dp(upd7810_state *cpustate); -static void EQAX_H(upd7810_state *cpustate); -static void EQAX_Hm(upd7810_state *cpustate); -static void EQAX_Hp(upd7810_state *cpustate); -static void EQA_A_A(upd7810_state *cpustate); -static void EQA_A_A(upd7810_state *cpustate); -static void EQA_A_B(upd7810_state *cpustate); -static void EQA_A_C(upd7810_state *cpustate); -static void EQA_A_D(upd7810_state *cpustate); -static void EQA_A_E(upd7810_state *cpustate); -static void EQA_A_H(upd7810_state *cpustate); -static void EQA_A_L(upd7810_state *cpustate); -static void EQA_A_V(upd7810_state *cpustate); -static void EQA_B_A(upd7810_state *cpustate); -static void EQA_C_A(upd7810_state *cpustate); -static void EQA_D_A(upd7810_state *cpustate); -static void EQA_E_A(upd7810_state *cpustate); -static void EQA_H_A(upd7810_state *cpustate); -static void EQA_L_A(upd7810_state *cpustate); -static void EQA_V_A(upd7810_state *cpustate); -static void EQIW_wa_xx(upd7810_state *cpustate); -static void EQI_ANM_xx(upd7810_state *cpustate); -static void EQI_A_xx(upd7810_state *cpustate); -static void EQI_A_xx(upd7810_state *cpustate); -static void EQI_B_xx(upd7810_state *cpustate); -static void EQI_C_xx(upd7810_state *cpustate); -static void EQI_D_xx(upd7810_state *cpustate); -static void EQI_EOM_xx(upd7810_state *cpustate); -static void EQI_E_xx(upd7810_state *cpustate); -static void EQI_H_xx(upd7810_state *cpustate); -static void EQI_L_xx(upd7810_state *cpustate); -static void EQI_MKH_xx(upd7810_state *cpustate); -static void EQI_MKL_xx(upd7810_state *cpustate); -static void EQI_PA_xx(upd7810_state *cpustate); -static void EQI_PB_xx(upd7810_state *cpustate); -static void EQI_PC_xx(upd7810_state *cpustate); -static void EQI_PD_xx(upd7810_state *cpustate); -static void EQI_PF_xx(upd7810_state *cpustate); -static void EQI_SMH_xx(upd7810_state *cpustate); -static void EQI_TMM_xx(upd7810_state *cpustate); -static void EQI_V_xx(upd7810_state *cpustate); -static void ESUB_EA_A(upd7810_state *cpustate); -static void ESUB_EA_B(upd7810_state *cpustate); -static void ESUB_EA_C(upd7810_state *cpustate); -static void EXA(upd7810_state *cpustate); -static void EXH(upd7810_state *cpustate); -static void EXX(upd7810_state *cpustate); -static void EXR(upd7810_state *cpustate); -static void GTAW_wa(upd7810_state *cpustate); -static void GTAX_B(upd7810_state *cpustate); -static void GTAX_D(upd7810_state *cpustate); -static void GTAX_Dm(upd7810_state *cpustate); -static void GTAX_Dp(upd7810_state *cpustate); -static void GTAX_H(upd7810_state *cpustate); -static void GTAX_Hm(upd7810_state *cpustate); -static void GTAX_Hp(upd7810_state *cpustate); -static void GTA_A_A(upd7810_state *cpustate); -static void GTA_A_A(upd7810_state *cpustate); -static void GTA_A_B(upd7810_state *cpustate); -static void GTA_A_C(upd7810_state *cpustate); -static void GTA_A_D(upd7810_state *cpustate); -static void GTA_A_E(upd7810_state *cpustate); -static void GTA_A_H(upd7810_state *cpustate); -static void GTA_A_L(upd7810_state *cpustate); -static void GTA_A_V(upd7810_state *cpustate); -static void GTA_B_A(upd7810_state *cpustate); -static void GTA_C_A(upd7810_state *cpustate); -static void GTA_D_A(upd7810_state *cpustate); -static void GTA_E_A(upd7810_state *cpustate); -static void GTA_H_A(upd7810_state *cpustate); -static void GTA_L_A(upd7810_state *cpustate); -static void GTA_V_A(upd7810_state *cpustate); -static void GTIW_wa_xx(upd7810_state *cpustate); -static void GTI_ANM_xx(upd7810_state *cpustate); -static void GTI_A_xx(upd7810_state *cpustate); -static void GTI_A_xx(upd7810_state *cpustate); -static void GTI_B_xx(upd7810_state *cpustate); -static void GTI_C_xx(upd7810_state *cpustate); -static void GTI_D_xx(upd7810_state *cpustate); -static void GTI_EOM_xx(upd7810_state *cpustate); -static void GTI_E_xx(upd7810_state *cpustate); -static void GTI_H_xx(upd7810_state *cpustate); -static void GTI_L_xx(upd7810_state *cpustate); -static void GTI_MKH_xx(upd7810_state *cpustate); -static void GTI_MKL_xx(upd7810_state *cpustate); -static void GTI_PA_xx(upd7810_state *cpustate); -static void GTI_PB_xx(upd7810_state *cpustate); -static void GTI_PC_xx(upd7810_state *cpustate); -static void GTI_PD_xx(upd7810_state *cpustate); -static void GTI_PF_xx(upd7810_state *cpustate); -static void GTI_SMH_xx(upd7810_state *cpustate); -static void GTI_TMM_xx(upd7810_state *cpustate); -static void GTI_V_xx(upd7810_state *cpustate); -static void HALT(upd7810_state *cpustate); -static void IN(upd7810_state *cpustate); -static void INRW_wa(upd7810_state *cpustate); -static void INR_A(upd7810_state *cpustate); -static void INR_B(upd7810_state *cpustate); -static void INR_C(upd7810_state *cpustate); -static void INX_BC(upd7810_state *cpustate); -static void INX_DE(upd7810_state *cpustate); -static void INX_EA(upd7810_state *cpustate); -static void INX_HL(upd7810_state *cpustate); -static void INX_SP(upd7810_state *cpustate); -static void JB(upd7810_state *cpustate); -static void JEA(upd7810_state *cpustate); -static void JMP_w(upd7810_state *cpustate); -static void JR(upd7810_state *cpustate); -static void JRE(upd7810_state *cpustate); -static void LBCD_w(upd7810_state *cpustate); -static void LDAW_wa(upd7810_state *cpustate); -static void LDAX_B(upd7810_state *cpustate); -static void LDAX_D(upd7810_state *cpustate); -static void LDAX_D_xx(upd7810_state *cpustate); -static void LDAX_Dm(upd7810_state *cpustate); -static void LDAX_Dp(upd7810_state *cpustate); -static void LDAX_H(upd7810_state *cpustate); -static void LDAX_H_A(upd7810_state *cpustate); -static void LDAX_H_B(upd7810_state *cpustate); -static void LDAX_H_EA(upd7810_state *cpustate); -static void LDAX_H_xx(upd7810_state *cpustate); -static void LDAX_Hm(upd7810_state *cpustate); -static void LDAX_Hp(upd7810_state *cpustate); -static void LDEAX_D(upd7810_state *cpustate); -static void LDEAX_D_xx(upd7810_state *cpustate); -static void LDEAX_Dp(upd7810_state *cpustate); -static void LDEAX_H(upd7810_state *cpustate); -static void LDEAX_H_A(upd7810_state *cpustate); -static void LDEAX_H_B(upd7810_state *cpustate); -static void LDEAX_H_EA(upd7810_state *cpustate); -static void LDEAX_H_xx(upd7810_state *cpustate); -static void LDEAX_Hp(upd7810_state *cpustate); -static void LDED_w(upd7810_state *cpustate); -static void LHLD_w(upd7810_state *cpustate); -static void LSPD_w(upd7810_state *cpustate); -static void LTAW_wa(upd7810_state *cpustate); -static void LTAX_B(upd7810_state *cpustate); -static void LTAX_D(upd7810_state *cpustate); -static void LTAX_Dm(upd7810_state *cpustate); -static void LTAX_Dp(upd7810_state *cpustate); -static void LTAX_H(upd7810_state *cpustate); -static void LTAX_Hm(upd7810_state *cpustate); -static void LTAX_Hp(upd7810_state *cpustate); -static void LTA_A_A(upd7810_state *cpustate); -static void LTA_A_A(upd7810_state *cpustate); -static void LTA_A_B(upd7810_state *cpustate); -static void LTA_A_C(upd7810_state *cpustate); -static void LTA_A_D(upd7810_state *cpustate); -static void LTA_A_E(upd7810_state *cpustate); -static void LTA_A_H(upd7810_state *cpustate); -static void LTA_A_L(upd7810_state *cpustate); -static void LTA_A_V(upd7810_state *cpustate); -static void LTA_B_A(upd7810_state *cpustate); -static void LTA_C_A(upd7810_state *cpustate); -static void LTA_D_A(upd7810_state *cpustate); -static void LTA_E_A(upd7810_state *cpustate); -static void LTA_H_A(upd7810_state *cpustate); -static void LTA_L_A(upd7810_state *cpustate); -static void LTA_V_A(upd7810_state *cpustate); -static void LTIW_wa_xx(upd7810_state *cpustate); -static void LTI_ANM_xx(upd7810_state *cpustate); -static void LTI_A_xx(upd7810_state *cpustate); -static void LTI_A_xx(upd7810_state *cpustate); -static void LTI_B_xx(upd7810_state *cpustate); -static void LTI_C_xx(upd7810_state *cpustate); -static void LTI_D_xx(upd7810_state *cpustate); -static void LTI_EOM_xx(upd7810_state *cpustate); -static void LTI_E_xx(upd7810_state *cpustate); -static void LTI_H_xx(upd7810_state *cpustate); -static void LTI_L_xx(upd7810_state *cpustate); -static void LTI_MKH_xx(upd7810_state *cpustate); -static void LTI_MKL_xx(upd7810_state *cpustate); -static void LTI_PA_xx(upd7810_state *cpustate); -static void LTI_PB_xx(upd7810_state *cpustate); -static void LTI_PC_xx(upd7810_state *cpustate); -static void LTI_PD_xx(upd7810_state *cpustate); -static void LTI_PF_xx(upd7810_state *cpustate); -static void LTI_SMH_xx(upd7810_state *cpustate); -static void LTI_TMM_xx(upd7810_state *cpustate); -static void LTI_V_xx(upd7810_state *cpustate); -static void LXI_B_w(upd7810_state *cpustate); -static void LXI_D_w(upd7810_state *cpustate); -static void LXI_EA_s(upd7810_state *cpustate); -static void LXI_H_w(upd7810_state *cpustate); -static void LXI_S_w(upd7810_state *cpustate); -static void MOV_ANM_A(upd7810_state *cpustate); -static void MOV_A_ANM(upd7810_state *cpustate); -static void MOV_A_B(upd7810_state *cpustate); -static void MOV_A_C(upd7810_state *cpustate); -static void MOV_A_CR0(upd7810_state *cpustate); -static void MOV_A_CR1(upd7810_state *cpustate); -static void MOV_A_CR2(upd7810_state *cpustate); -static void MOV_A_CR3(upd7810_state *cpustate); -static void MOV_A_D(upd7810_state *cpustate); -static void MOV_A_E(upd7810_state *cpustate); -static void MOV_A_EAH(upd7810_state *cpustate); -static void MOV_A_EAL(upd7810_state *cpustate); -static void MOV_A_EOM(upd7810_state *cpustate); -static void MOV_A_H(upd7810_state *cpustate); -static void MOV_A_L(upd7810_state *cpustate); -static void MOV_A_MKH(upd7810_state *cpustate); -static void MOV_A_MKL(upd7810_state *cpustate); -static void MOV_A_PA(upd7810_state *cpustate); -static void MOV_A_PB(upd7810_state *cpustate); -static void MOV_A_PC(upd7810_state *cpustate); -static void MOV_A_PD(upd7810_state *cpustate); -static void MOV_A_PF(upd7810_state *cpustate); -static void MOV_A_RXB(upd7810_state *cpustate); -static void MOV_A_S(upd7810_state *cpustate); -static void MOV_A_SMH(upd7810_state *cpustate); -static void MOV_A_TMM(upd7810_state *cpustate); -static void MOV_A_PT(upd7810_state *cpustate); -static void MOV_A_w(upd7810_state *cpustate); -static void MOV_B_A(upd7810_state *cpustate); -static void MOV_B_w(upd7810_state *cpustate); -static void MOV_C_A(upd7810_state *cpustate); -static void MOV_C_w(upd7810_state *cpustate); -static void MOV_D_A(upd7810_state *cpustate); -static void MOV_D_w(upd7810_state *cpustate); -static void MOV_EAH_A(upd7810_state *cpustate); -static void MOV_EAL_A(upd7810_state *cpustate); -static void MOV_EOM_A(upd7810_state *cpustate); -static void MOV_ETMM_A(upd7810_state *cpustate); -static void MOV_E_A(upd7810_state *cpustate); -static void MOV_E_w(upd7810_state *cpustate); -static void MOV_H_A(upd7810_state *cpustate); -static void MOV_H_w(upd7810_state *cpustate); -static void MOV_L_A(upd7810_state *cpustate); -static void MOV_L_w(upd7810_state *cpustate); -static void MOV_MA_A(upd7810_state *cpustate); -static void MOV_MB_A(upd7810_state *cpustate); -static void MOV_MCC_A(upd7810_state *cpustate); -static void MOV_MC_A(upd7810_state *cpustate); -static void MOV_MF_A(upd7810_state *cpustate); -static void MOV_MKH_A(upd7810_state *cpustate); -static void MOV_MKL_A(upd7810_state *cpustate); -static void MOV_MM_A(upd7810_state *cpustate); -static void MOV_PA_A(upd7810_state *cpustate); -static void MOV_PB_A(upd7810_state *cpustate); -static void MOV_PC_A(upd7810_state *cpustate); -static void MOV_PD_A(upd7810_state *cpustate); -static void MOV_PF_A(upd7810_state *cpustate); -static void MOV_S_A(upd7810_state *cpustate); -static void MOV_SMH_A(upd7810_state *cpustate); -static void MOV_SML_A(upd7810_state *cpustate); -static void MOV_TM0_A(upd7810_state *cpustate); -static void MOV_TM1_A(upd7810_state *cpustate); -static void MOV_TMM_A(upd7810_state *cpustate); -static void MOV_TXB_A(upd7810_state *cpustate); -static void MOV_V_w(upd7810_state *cpustate); -static void MOV_ZCM_A(upd7810_state *cpustate); -static void MOV_w_A(upd7810_state *cpustate); -static void MOV_w_B(upd7810_state *cpustate); -static void MOV_w_C(upd7810_state *cpustate); -static void MOV_w_D(upd7810_state *cpustate); -static void MOV_w_E(upd7810_state *cpustate); -static void MOV_w_H(upd7810_state *cpustate); -static void MOV_w_L(upd7810_state *cpustate); -static void MOV_w_V(upd7810_state *cpustate); -static void MUL_A(upd7810_state *cpustate); -static void MUL_B(upd7810_state *cpustate); -static void MUL_C(upd7810_state *cpustate); -static void MVIW_wa_xx(upd7810_state *cpustate); -static void MVIX_BC_xx(upd7810_state *cpustate); -static void MVIX_DE_xx(upd7810_state *cpustate); -static void MVIX_HL_xx(upd7810_state *cpustate); -static void MVI_ANM_xx(upd7810_state *cpustate); -static void MVI_A_xx(upd7810_state *cpustate); -static void MVI_B_xx(upd7810_state *cpustate); -static void MVI_C_xx(upd7810_state *cpustate); -static void MVI_D_xx(upd7810_state *cpustate); -static void MVI_EOM_xx(upd7810_state *cpustate); -static void MVI_E_xx(upd7810_state *cpustate); -static void MVI_H_xx(upd7810_state *cpustate); -static void MVI_L_xx(upd7810_state *cpustate); -static void MVI_MKH_xx(upd7810_state *cpustate); -static void MVI_MKL_xx(upd7810_state *cpustate); -static void MVI_PA_xx(upd7810_state *cpustate); -static void MVI_PB_xx(upd7810_state *cpustate); -static void MVI_PC_xx(upd7810_state *cpustate); -static void MVI_PD_xx(upd7810_state *cpustate); -static void MVI_PF_xx(upd7810_state *cpustate); -static void MVI_SMH_xx(upd7810_state *cpustate); -static void MVI_TMM_xx(upd7810_state *cpustate); -static void MVI_V_xx(upd7810_state *cpustate); -static void NEAW_wa(upd7810_state *cpustate); -static void NEAX_B(upd7810_state *cpustate); -static void NEAX_D(upd7810_state *cpustate); -static void NEAX_Dm(upd7810_state *cpustate); -static void NEAX_Dp(upd7810_state *cpustate); -static void NEAX_H(upd7810_state *cpustate); -static void NEAX_Hm(upd7810_state *cpustate); -static void NEAX_Hp(upd7810_state *cpustate); -static void NEA_A_A(upd7810_state *cpustate); -static void NEA_A_A(upd7810_state *cpustate); -static void NEA_A_B(upd7810_state *cpustate); -static void NEA_A_C(upd7810_state *cpustate); -static void NEA_A_D(upd7810_state *cpustate); -static void NEA_A_E(upd7810_state *cpustate); -static void NEA_A_H(upd7810_state *cpustate); -static void NEA_A_L(upd7810_state *cpustate); -static void NEA_A_V(upd7810_state *cpustate); -static void NEA_B_A(upd7810_state *cpustate); -static void NEA_C_A(upd7810_state *cpustate); -static void NEA_D_A(upd7810_state *cpustate); -static void NEA_E_A(upd7810_state *cpustate); -static void NEA_H_A(upd7810_state *cpustate); -static void NEA_L_A(upd7810_state *cpustate); -static void NEA_V_A(upd7810_state *cpustate); -static void NEGA(upd7810_state *cpustate); -static void NEIW_wa_xx(upd7810_state *cpustate); -static void NEI_ANM_xx(upd7810_state *cpustate); -static void NEI_A_xx(upd7810_state *cpustate); -static void NEI_A_xx(upd7810_state *cpustate); -static void NEI_B_xx(upd7810_state *cpustate); -static void NEI_C_xx(upd7810_state *cpustate); -static void NEI_D_xx(upd7810_state *cpustate); -static void NEI_EOM_xx(upd7810_state *cpustate); -static void NEI_E_xx(upd7810_state *cpustate); -static void NEI_H_xx(upd7810_state *cpustate); -static void NEI_L_xx(upd7810_state *cpustate); -static void NEI_MKH_xx(upd7810_state *cpustate); -static void NEI_MKL_xx(upd7810_state *cpustate); -static void NEI_PA_xx(upd7810_state *cpustate); -static void NEI_PB_xx(upd7810_state *cpustate); -static void NEI_PC_xx(upd7810_state *cpustate); -static void NEI_PD_xx(upd7810_state *cpustate); -static void NEI_PF_xx(upd7810_state *cpustate); -static void NEI_SMH_xx(upd7810_state *cpustate); -static void NEI_TMM_xx(upd7810_state *cpustate); -static void NEI_V_xx(upd7810_state *cpustate); -static void NOP(upd7810_state *cpustate); -static void OFFAW_wa(upd7810_state *cpustate); -static void OFFAX_B(upd7810_state *cpustate); -static void OFFAX_D(upd7810_state *cpustate); -static void OFFAX_Dm(upd7810_state *cpustate); -static void OFFAX_Dp(upd7810_state *cpustate); -static void OFFAX_H(upd7810_state *cpustate); -static void OFFAX_Hm(upd7810_state *cpustate); -static void OFFAX_Hp(upd7810_state *cpustate); -static void OFFA_A_A(upd7810_state *cpustate); -static void OFFA_A_B(upd7810_state *cpustate); -static void OFFA_A_C(upd7810_state *cpustate); -static void OFFA_A_D(upd7810_state *cpustate); -static void OFFA_A_E(upd7810_state *cpustate); -static void OFFA_A_H(upd7810_state *cpustate); -static void OFFA_A_L(upd7810_state *cpustate); -static void OFFA_A_V(upd7810_state *cpustate); -static void OFFIW_wa_xx(upd7810_state *cpustate); -static void OFFI_ANM_xx(upd7810_state *cpustate); -static void OFFI_A_xx(upd7810_state *cpustate); -static void OFFI_A_xx(upd7810_state *cpustate); -static void OFFI_B_xx(upd7810_state *cpustate); -static void OFFI_C_xx(upd7810_state *cpustate); -static void OFFI_D_xx(upd7810_state *cpustate); -static void OFFI_EOM_xx(upd7810_state *cpustate); -static void OFFI_E_xx(upd7810_state *cpustate); -static void OFFI_H_xx(upd7810_state *cpustate); -static void OFFI_L_xx(upd7810_state *cpustate); -static void OFFI_MKH_xx(upd7810_state *cpustate); -static void OFFI_MKL_xx(upd7810_state *cpustate); -static void OFFI_PA_xx(upd7810_state *cpustate); -static void OFFI_PB_xx(upd7810_state *cpustate); -static void OFFI_PC_xx(upd7810_state *cpustate); -static void OFFI_PD_xx(upd7810_state *cpustate); -static void OFFI_PF_xx(upd7810_state *cpustate); -static void OFFI_SMH_xx(upd7810_state *cpustate); -static void OFFI_TMM_xx(upd7810_state *cpustate); -static void OFFI_V_xx(upd7810_state *cpustate); -static void ONAW_wa(upd7810_state *cpustate); -static void ONAX_B(upd7810_state *cpustate); -static void ONAX_D(upd7810_state *cpustate); -static void ONAX_Dm(upd7810_state *cpustate); -static void ONAX_Dp(upd7810_state *cpustate); -static void ONAX_H(upd7810_state *cpustate); -static void ONAX_Hm(upd7810_state *cpustate); -static void ONAX_Hp(upd7810_state *cpustate); -static void ONA_A_A(upd7810_state *cpustate); -static void ONA_A_B(upd7810_state *cpustate); -static void ONA_A_C(upd7810_state *cpustate); -static void ONA_A_D(upd7810_state *cpustate); -static void ONA_A_E(upd7810_state *cpustate); -static void ONA_A_H(upd7810_state *cpustate); -static void ONA_A_L(upd7810_state *cpustate); -static void ONA_A_V(upd7810_state *cpustate); -static void ONIW_wa_xx(upd7810_state *cpustate); -static void ONI_ANM_xx(upd7810_state *cpustate); -static void ONI_A_xx(upd7810_state *cpustate); -static void ONI_A_xx(upd7810_state *cpustate); -static void ONI_B_xx(upd7810_state *cpustate); -static void ONI_C_xx(upd7810_state *cpustate); -static void ONI_D_xx(upd7810_state *cpustate); -static void ONI_EOM_xx(upd7810_state *cpustate); -static void ONI_E_xx(upd7810_state *cpustate); -static void ONI_H_xx(upd7810_state *cpustate); -static void ONI_L_xx(upd7810_state *cpustate); -static void ONI_MKH_xx(upd7810_state *cpustate); -static void ONI_MKL_xx(upd7810_state *cpustate); -static void ONI_PA_xx(upd7810_state *cpustate); -static void ONI_PB_xx(upd7810_state *cpustate); -static void ONI_PC_xx(upd7810_state *cpustate); -static void ONI_PD_xx(upd7810_state *cpustate); -static void ONI_PF_xx(upd7810_state *cpustate); -static void ONI_SMH_xx(upd7810_state *cpustate); -static void ONI_TMM_xx(upd7810_state *cpustate); -static void ONI_V_xx(upd7810_state *cpustate); -static void ORAW_wa(upd7810_state *cpustate); -static void ORAX_B(upd7810_state *cpustate); -static void ORAX_D(upd7810_state *cpustate); -static void ORAX_Dm(upd7810_state *cpustate); -static void ORAX_Dp(upd7810_state *cpustate); -static void ORAX_H(upd7810_state *cpustate); -static void ORAX_Hm(upd7810_state *cpustate); -static void ORAX_Hp(upd7810_state *cpustate); -static void ORA_A_A(upd7810_state *cpustate); -static void ORA_A_A(upd7810_state *cpustate); -static void ORA_A_B(upd7810_state *cpustate); -static void ORA_A_C(upd7810_state *cpustate); -static void ORA_A_D(upd7810_state *cpustate); -static void ORA_A_E(upd7810_state *cpustate); -static void ORA_A_H(upd7810_state *cpustate); -static void ORA_A_L(upd7810_state *cpustate); -static void ORA_A_V(upd7810_state *cpustate); -static void ORA_B_A(upd7810_state *cpustate); -static void ORA_C_A(upd7810_state *cpustate); -static void ORA_D_A(upd7810_state *cpustate); -static void ORA_E_A(upd7810_state *cpustate); -static void ORA_H_A(upd7810_state *cpustate); -static void ORA_L_A(upd7810_state *cpustate); -static void ORA_V_A(upd7810_state *cpustate); -static void ORIW_wa_xx(upd7810_state *cpustate); -static void ORI_ANM_xx(upd7810_state *cpustate); -static void ORI_A_xx(upd7810_state *cpustate); -static void ORI_A_xx(upd7810_state *cpustate); -static void ORI_B_xx(upd7810_state *cpustate); -static void ORI_C_xx(upd7810_state *cpustate); -static void ORI_D_xx(upd7810_state *cpustate); -static void ORI_EOM_xx(upd7810_state *cpustate); -static void ORI_E_xx(upd7810_state *cpustate); -static void ORI_H_xx(upd7810_state *cpustate); -static void ORI_L_xx(upd7810_state *cpustate); -static void ORI_MKH_xx(upd7810_state *cpustate); -static void ORI_MKL_xx(upd7810_state *cpustate); -static void ORI_PA_xx(upd7810_state *cpustate); -static void ORI_PB_xx(upd7810_state *cpustate); -static void ORI_PC_xx(upd7810_state *cpustate); -static void ORI_PD_xx(upd7810_state *cpustate); -static void ORI_PF_xx(upd7810_state *cpustate); -static void ORI_SMH_xx(upd7810_state *cpustate); -static void ORI_TMM_xx(upd7810_state *cpustate); -static void ORI_V_xx(upd7810_state *cpustate); -static void OUT(upd7810_state *cpustate); -static void PEN(upd7810_state *cpustate); -static void PER(upd7810_state *cpustate); -static void PEX(upd7810_state *cpustate); -static void POP_BC(upd7810_state *cpustate); -static void POP_DE(upd7810_state *cpustate); -static void POP_EA(upd7810_state *cpustate); -static void POP_HL(upd7810_state *cpustate); -static void POP_VA(upd7810_state *cpustate); -static void PRE_48(upd7810_state *cpustate); -static void PRE_4C(upd7810_state *cpustate); -static void PRE_4D(upd7810_state *cpustate); -static void PRE_60(upd7810_state *cpustate); -static void PRE_64(upd7810_state *cpustate); -static void PRE_70(upd7810_state *cpustate); -static void PRE_74(upd7810_state *cpustate); -static void PUSH_BC(upd7810_state *cpustate); -static void PUSH_DE(upd7810_state *cpustate); -static void PUSH_EA(upd7810_state *cpustate); -static void PUSH_HL(upd7810_state *cpustate); -static void PUSH_VA(upd7810_state *cpustate); -static void RET(upd7810_state *cpustate); -static void RETI(upd7810_state *cpustate); -static void RETS(upd7810_state *cpustate); -static void RLD(upd7810_state *cpustate); -static void RLL_A(upd7810_state *cpustate); -static void RLL_B(upd7810_state *cpustate); -static void RLL_C(upd7810_state *cpustate); -static void RLR_A(upd7810_state *cpustate); -static void RLR_B(upd7810_state *cpustate); -static void RLR_C(upd7810_state *cpustate); -static void RRD(upd7810_state *cpustate); -static void SBBW_wa(upd7810_state *cpustate); -static void SBBX_B(upd7810_state *cpustate); -static void SBBX_D(upd7810_state *cpustate); -static void SBBX_Dm(upd7810_state *cpustate); -static void SBBX_Dp(upd7810_state *cpustate); -static void SBBX_H(upd7810_state *cpustate); -static void SBBX_Hm(upd7810_state *cpustate); -static void SBBX_Hp(upd7810_state *cpustate); -static void SBB_A_A(upd7810_state *cpustate); -static void SBB_A_A(upd7810_state *cpustate); -static void SBB_A_B(upd7810_state *cpustate); -static void SBB_A_C(upd7810_state *cpustate); -static void SBB_A_D(upd7810_state *cpustate); -static void SBB_A_E(upd7810_state *cpustate); -static void SBB_A_H(upd7810_state *cpustate); -static void SBB_A_L(upd7810_state *cpustate); -static void SBB_A_V(upd7810_state *cpustate); -static void SBB_B_A(upd7810_state *cpustate); -static void SBB_C_A(upd7810_state *cpustate); -static void SBB_D_A(upd7810_state *cpustate); -static void SBB_E_A(upd7810_state *cpustate); -static void SBB_H_A(upd7810_state *cpustate); -static void SBB_L_A(upd7810_state *cpustate); -static void SBB_V_A(upd7810_state *cpustate); -static void SBCD_w(upd7810_state *cpustate); -static void SBI_ANM_xx(upd7810_state *cpustate); -static void SBI_A_xx(upd7810_state *cpustate); -static void SBI_A_xx(upd7810_state *cpustate); -static void SBI_B_xx(upd7810_state *cpustate); -static void SBI_C_xx(upd7810_state *cpustate); -static void SBI_D_xx(upd7810_state *cpustate); -static void SBI_EOM_xx(upd7810_state *cpustate); -static void SBI_E_xx(upd7810_state *cpustate); -static void SBI_H_xx(upd7810_state *cpustate); -static void SBI_L_xx(upd7810_state *cpustate); -static void SBI_MKH_xx(upd7810_state *cpustate); -static void SBI_MKL_xx(upd7810_state *cpustate); -static void SBI_PA_xx(upd7810_state *cpustate); -static void SBI_PB_xx(upd7810_state *cpustate); -static void SBI_PC_xx(upd7810_state *cpustate); -static void SBI_PD_xx(upd7810_state *cpustate); -static void SBI_PF_xx(upd7810_state *cpustate); -static void SBI_SMH_xx(upd7810_state *cpustate); -static void SBI_TMM_xx(upd7810_state *cpustate); -static void SBI_V_xx(upd7810_state *cpustate); -static void SDED_w(upd7810_state *cpustate); -static void SETB(upd7810_state *cpustate); -static void SHLD_w(upd7810_state *cpustate); -static void SIO(upd7810_state *cpustate); -static void SK_bit(upd7810_state *cpustate); -static void SKN_bit(upd7810_state *cpustate); -static void SKIT_AN4(upd7810_state *cpustate); -static void SKIT_AN5(upd7810_state *cpustate); -static void SKIT_AN6(upd7810_state *cpustate); -static void SKIT_AN7(upd7810_state *cpustate); -static void SKIT_ER(upd7810_state *cpustate); -static void SKIT_F0(upd7810_state *cpustate); -static void SKIT_F1(upd7810_state *cpustate); -static void SKIT_F2(upd7810_state *cpustate); -static void SKIT_FAD(upd7810_state *cpustate); -static void SKIT_FE0(upd7810_state *cpustate); -static void SKIT_FE1(upd7810_state *cpustate); -static void SKIT_FEIN(upd7810_state *cpustate); -static void SKIT_FSR(upd7810_state *cpustate); -static void SKIT_FST(upd7810_state *cpustate); -static void SKIT_FT0(upd7810_state *cpustate); -static void SKIT_FT1(upd7810_state *cpustate); -static void SKIT_NMI(upd7810_state *cpustate); -static void SKIT_OV(upd7810_state *cpustate); -static void SKIT_SB(upd7810_state *cpustate); -static void SKNIT_AN4(upd7810_state *cpustate); -static void SKNIT_AN5(upd7810_state *cpustate); -static void SKNIT_AN6(upd7810_state *cpustate); -static void SKNIT_AN7(upd7810_state *cpustate); -static void SKNIT_ER(upd7810_state *cpustate); -static void SKNIT_F0(upd7810_state *cpustate); -static void SKNIT_F1(upd7810_state *cpustate); -static void SKNIT_F2(upd7810_state *cpustate); -static void SKNIT_FAD(upd7810_state *cpustate); -static void SKNIT_FE0(upd7810_state *cpustate); -static void SKNIT_FE1(upd7810_state *cpustate); -static void SKNIT_FEIN(upd7810_state *cpustate); -static void SKNIT_FSR(upd7810_state *cpustate); -static void SKNIT_FST(upd7810_state *cpustate); -static void SKNIT_FT0(upd7810_state *cpustate); -static void SKNIT_FT1(upd7810_state *cpustate); -static void SKNIT_NMI(upd7810_state *cpustate); -static void SKNIT_OV(upd7810_state *cpustate); -static void SKNIT_SB(upd7810_state *cpustate); -static void SKN_CY(upd7810_state *cpustate); -static void SKN_HC(upd7810_state *cpustate); -static void SKN_NV(upd7810_state *cpustate); -static void SKN_Z(upd7810_state *cpustate); -static void SK_CY(upd7810_state *cpustate); -static void SK_HC(upd7810_state *cpustate); -static void SK_NV(upd7810_state *cpustate); -static void SK_Z(upd7810_state *cpustate); -static void SLLC_A(upd7810_state *cpustate); -static void SLLC_B(upd7810_state *cpustate); -static void SLLC_C(upd7810_state *cpustate); -static void SLL_A(upd7810_state *cpustate); -static void SLL_B(upd7810_state *cpustate); -static void SLL_C(upd7810_state *cpustate); -static void SLRC_A(upd7810_state *cpustate); -static void SLRC_B(upd7810_state *cpustate); -static void SLRC_C(upd7810_state *cpustate); -static void SLR_A(upd7810_state *cpustate); -static void SLR_B(upd7810_state *cpustate); -static void SLR_C(upd7810_state *cpustate); -static void SOFTI(upd7810_state *cpustate); -static void SSPD_w(upd7810_state *cpustate); -static void STAW_wa(upd7810_state *cpustate); -static void STAX_B(upd7810_state *cpustate); -static void STAX_D(upd7810_state *cpustate); -static void STAX_D_xx(upd7810_state *cpustate); -static void STAX_Dm(upd7810_state *cpustate); -static void STAX_Dp(upd7810_state *cpustate); -static void STAX_H(upd7810_state *cpustate); -static void STAX_H_A(upd7810_state *cpustate); -static void STAX_H_B(upd7810_state *cpustate); -static void STAX_H_EA(upd7810_state *cpustate); -static void STAX_H_xx(upd7810_state *cpustate); -static void STAX_Hm(upd7810_state *cpustate); -static void STAX_Hp(upd7810_state *cpustate); -static void STC(upd7810_state *cpustate); -static void STEAX_D(upd7810_state *cpustate); -static void STEAX_D_xx(upd7810_state *cpustate); -static void STEAX_Dp(upd7810_state *cpustate); -static void STEAX_H(upd7810_state *cpustate); -static void STEAX_H_A(upd7810_state *cpustate); -static void STEAX_H_B(upd7810_state *cpustate); -static void STEAX_H_EA(upd7810_state *cpustate); -static void STEAX_H_xx(upd7810_state *cpustate); -static void STEAX_Hp(upd7810_state *cpustate); -static void STM(upd7810_state *cpustate); -static void STOP(upd7810_state *cpustate); -static void SUBNBW_wa(upd7810_state *cpustate); -static void SUBNBX_B(upd7810_state *cpustate); -static void SUBNBX_D(upd7810_state *cpustate); -static void SUBNBX_Dm(upd7810_state *cpustate); -static void SUBNBX_Dp(upd7810_state *cpustate); -static void SUBNBX_H(upd7810_state *cpustate); -static void SUBNBX_Hm(upd7810_state *cpustate); -static void SUBNBX_Hp(upd7810_state *cpustate); -static void SUBNB_A_A(upd7810_state *cpustate); -static void SUBNB_A_A(upd7810_state *cpustate); -static void SUBNB_A_B(upd7810_state *cpustate); -static void SUBNB_A_C(upd7810_state *cpustate); -static void SUBNB_A_D(upd7810_state *cpustate); -static void SUBNB_A_E(upd7810_state *cpustate); -static void SUBNB_A_H(upd7810_state *cpustate); -static void SUBNB_A_L(upd7810_state *cpustate); -static void SUBNB_A_V(upd7810_state *cpustate); -static void SUBNB_B_A(upd7810_state *cpustate); -static void SUBNB_C_A(upd7810_state *cpustate); -static void SUBNB_D_A(upd7810_state *cpustate); -static void SUBNB_E_A(upd7810_state *cpustate); -static void SUBNB_H_A(upd7810_state *cpustate); -static void SUBNB_L_A(upd7810_state *cpustate); -static void SUBNB_V_A(upd7810_state *cpustate); -static void SUBW_wa(upd7810_state *cpustate); -static void SUBX_B(upd7810_state *cpustate); -static void SUBX_D(upd7810_state *cpustate); -static void SUBX_Dm(upd7810_state *cpustate); -static void SUBX_Dp(upd7810_state *cpustate); -static void SUBX_H(upd7810_state *cpustate); -static void SUBX_Hm(upd7810_state *cpustate); -static void SUBX_Hp(upd7810_state *cpustate); -static void SUB_A_A(upd7810_state *cpustate); -static void SUB_A_A(upd7810_state *cpustate); -static void SUB_A_B(upd7810_state *cpustate); -static void SUB_A_C(upd7810_state *cpustate); -static void SUB_A_D(upd7810_state *cpustate); -static void SUB_A_E(upd7810_state *cpustate); -static void SUB_A_H(upd7810_state *cpustate); -static void SUB_A_L(upd7810_state *cpustate); -static void SUB_A_V(upd7810_state *cpustate); -static void SUB_B_A(upd7810_state *cpustate); -static void SUB_C_A(upd7810_state *cpustate); -static void SUB_D_A(upd7810_state *cpustate); -static void SUB_E_A(upd7810_state *cpustate); -static void SUB_H_A(upd7810_state *cpustate); -static void SUB_L_A(upd7810_state *cpustate); -static void SUB_V_A(upd7810_state *cpustate); -static void SUINB_ANM_xx(upd7810_state *cpustate); -static void SUINB_A_xx(upd7810_state *cpustate); -static void SUINB_A_xx(upd7810_state *cpustate); -static void SUINB_B_xx(upd7810_state *cpustate); -static void SUINB_C_xx(upd7810_state *cpustate); -static void SUINB_D_xx(upd7810_state *cpustate); -static void SUINB_EOM_xx(upd7810_state *cpustate); -static void SUINB_E_xx(upd7810_state *cpustate); -static void SUINB_H_xx(upd7810_state *cpustate); -static void SUINB_L_xx(upd7810_state *cpustate); -static void SUINB_MKH_xx(upd7810_state *cpustate); -static void SUINB_MKL_xx(upd7810_state *cpustate); -static void SUINB_PA_xx(upd7810_state *cpustate); -static void SUINB_PB_xx(upd7810_state *cpustate); -static void SUINB_PC_xx(upd7810_state *cpustate); -static void SUINB_PD_xx(upd7810_state *cpustate); -static void SUINB_PF_xx(upd7810_state *cpustate); -static void SUINB_SMH_xx(upd7810_state *cpustate); -static void SUINB_TMM_xx(upd7810_state *cpustate); -static void SUINB_V_xx(upd7810_state *cpustate); -static void SUI_ANM_xx(upd7810_state *cpustate); -static void SUI_A_xx(upd7810_state *cpustate); -static void SUI_A_xx(upd7810_state *cpustate); -static void SUI_B_xx(upd7810_state *cpustate); -static void SUI_C_xx(upd7810_state *cpustate); -static void SUI_D_xx(upd7810_state *cpustate); -static void SUI_EOM_xx(upd7810_state *cpustate); -static void SUI_E_xx(upd7810_state *cpustate); -static void SUI_H_xx(upd7810_state *cpustate); -static void SUI_L_xx(upd7810_state *cpustate); -static void SUI_MKH_xx(upd7810_state *cpustate); -static void SUI_MKL_xx(upd7810_state *cpustate); -static void SUI_PA_xx(upd7810_state *cpustate); -static void SUI_PB_xx(upd7810_state *cpustate); -static void SUI_PC_xx(upd7810_state *cpustate); -static void SUI_PD_xx(upd7810_state *cpustate); -static void SUI_PF_xx(upd7810_state *cpustate); -static void SUI_SMH_xx(upd7810_state *cpustate); -static void SUI_TMM_xx(upd7810_state *cpustate); -static void SUI_V_xx(upd7810_state *cpustate); -static void TABLE(upd7810_state *cpustate); -static void XRAW_wa(upd7810_state *cpustate); -static void XRAX_B(upd7810_state *cpustate); -static void XRAX_D(upd7810_state *cpustate); -static void XRAX_Dm(upd7810_state *cpustate); -static void XRAX_Dp(upd7810_state *cpustate); -static void XRAX_H(upd7810_state *cpustate); -static void XRAX_Hm(upd7810_state *cpustate); -static void XRAX_Hp(upd7810_state *cpustate); -static void XRA_A_A(upd7810_state *cpustate); -static void XRA_A_A(upd7810_state *cpustate); -static void XRA_A_B(upd7810_state *cpustate); -static void XRA_A_C(upd7810_state *cpustate); -static void XRA_A_D(upd7810_state *cpustate); -static void XRA_A_E(upd7810_state *cpustate); -static void XRA_A_H(upd7810_state *cpustate); -static void XRA_A_L(upd7810_state *cpustate); -static void XRA_A_V(upd7810_state *cpustate); -static void XRA_B_A(upd7810_state *cpustate); -static void XRA_C_A(upd7810_state *cpustate); -static void XRA_D_A(upd7810_state *cpustate); -static void XRA_E_A(upd7810_state *cpustate); -static void XRA_H_A(upd7810_state *cpustate); -static void XRA_L_A(upd7810_state *cpustate); -static void XRA_V_A(upd7810_state *cpustate); -static void XRI_ANM_xx(upd7810_state *cpustate); -static void XRI_A_xx(upd7810_state *cpustate); -static void XRI_A_xx(upd7810_state *cpustate); -static void XRI_B_xx(upd7810_state *cpustate); -static void XRI_C_xx(upd7810_state *cpustate); -static void XRI_D_xx(upd7810_state *cpustate); -static void XRI_EOM_xx(upd7810_state *cpustate); -static void XRI_E_xx(upd7810_state *cpustate); -static void XRI_H_xx(upd7810_state *cpustate); -static void XRI_L_xx(upd7810_state *cpustate); -static void XRI_MKH_xx(upd7810_state *cpustate); -static void XRI_MKL_xx(upd7810_state *cpustate); -static void XRI_PA_xx(upd7810_state *cpustate); -static void XRI_PB_xx(upd7810_state *cpustate); -static void XRI_PC_xx(upd7810_state *cpustate); -static void XRI_PD_xx(upd7810_state *cpustate); -static void XRI_PF_xx(upd7810_state *cpustate); -static void XRI_SMH_xx(upd7810_state *cpustate); -static void XRI_TMM_xx(upd7810_state *cpustate); -static void XRI_V_xx(upd7810_state *cpustate); -static void CALT_7801(upd7810_state *cpustate); -static void DCR_A_7801(upd7810_state *cpustate); -static void DCR_B_7801(upd7810_state *cpustate); -static void DCR_C_7801(upd7810_state *cpustate); -static void DCRW_wa_7801(upd7810_state *cpustate); -static void INR_A_7801(upd7810_state *cpustate); -static void INR_B_7801(upd7810_state *cpustate); -static void INR_C_7801(upd7810_state *cpustate); -static void INRW_wa_7801(upd7810_state *cpustate); -static void STM_7801(upd7810_state *cpustate); -static void MOV_MC_A_7801(upd7810_state *cpustate); - - -static const struct opcode_s op48[256] = + +const struct upd7810_device::opcode_s upd7810_device::s_op48[256] = { - {illegal, 2, 8, 8,L0|L1}, /* 00: 0100 1000 0000 0000 */ - {SLRC_A, 2, 8, 8,L0|L1}, /* 01: 0100 1000 0000 0001 */ - {SLRC_B, 2, 8, 8,L0|L1}, /* 02: 0100 1000 0000 0010 */ - {SLRC_C, 2, 8, 8,L0|L1}, /* 03: 0100 1000 0000 0011 */ - {illegal, 2, 8, 8,L0|L1}, /* 04: 0100 1000 0000 0100 */ - {SLLC_A, 2, 8, 8,L0|L1}, /* 05: 0100 1000 0000 0101 */ - {SLLC_B, 2, 8, 8,L0|L1}, /* 06: 0100 1000 0000 0110 */ - {SLLC_C, 2, 8, 8,L0|L1}, /* 07: 0100 1000 0000 0111 */ - {SK_NV, 2, 8, 8,L0|L1}, /* 08: 0100 1000 0000 1000 */ - {illegal, 2, 8, 8,L0|L1}, /* 09: 0100 1000 0000 1001 */ - {SK_CY, 2, 8, 8,L0|L1}, /* 0a: 0100 1000 0000 1010 */ - {SK_HC, 2, 8, 8,L0|L1}, /* 0b: 0100 1000 0000 1011 */ - {SK_Z, 2, 8, 8,L0|L1}, /* 0c: 0100 1000 0000 1100 */ - {illegal, 2, 8, 8,L0|L1}, /* 0d: 0100 1000 0000 1101 */ - {illegal, 2, 8, 8,L0|L1}, /* 0e: 0100 1000 0000 1110 */ - {illegal, 2, 8, 8,L0|L1}, /* 0f: 0100 1000 0000 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 10: 0100 1000 0001 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 11: 0100 1000 0001 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 12: 0100 1000 0001 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 13: 0100 1000 0001 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 14: 0100 1000 0001 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 15: 0100 1000 0001 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 16: 0100 1000 0001 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 17: 0100 1000 0001 0111 */ - {SKN_NV, 2, 8, 8,L0|L1}, /* 18: 0100 1000 0001 1000 */ - {illegal, 2, 8, 8,L0|L1}, /* 19: 0100 1000 0001 1001 */ - {SKN_CY, 2, 8, 8,L0|L1}, /* 1a: 0100 1000 0001 1010 */ - {SKN_HC, 2, 8, 8,L0|L1}, /* 1b: 0100 1000 0001 1011 */ - {SKN_Z, 2, 8, 8,L0|L1}, /* 1c: 0100 1000 0001 1100 */ - {illegal, 2, 8, 8,L0|L1}, /* 1d: 0100 1000 0001 1101 */ - {illegal, 2, 8, 8,L0|L1}, /* 1e: 0100 1000 0001 1110 */ - {illegal, 2, 8, 8,L0|L1}, /* 1f: 0100 1000 0001 1111 */ - - {illegal, 2, 8, 8,L0|L1}, /* 20: 0100 1000 0010 0000 */ - {SLR_A, 2, 8, 8,L0|L1}, /* 21: 0100 1000 0010 0001 */ - {SLR_B, 2, 8, 8,L0|L1}, /* 22: 0100 1000 0010 0010 */ - {SLR_C, 2, 8, 8,L0|L1}, /* 23: 0100 1000 0010 0011 */ - {illegal, 2, 8, 8,L0|L1}, /* 24: 0100 1000 0010 0100 */ - {SLL_A, 2, 8, 8,L0|L1}, /* 25: 0100 1000 0010 0101 */ - {SLL_B, 2, 8, 8,L0|L1}, /* 26: 0100 1000 0010 0110 */ - {SLL_C, 2, 8, 8,L0|L1}, /* 27: 0100 1000 0010 0111 */ - {JEA, 2, 8, 8,L0|L1}, /* 28: 0100 1000 0010 1000 */ - {CALB, 2,17,17,L0|L1}, /* 29: 0100 1000 0010 1001 */ - {CLC, 2, 8, 8,L0|L1}, /* 2a: 0100 1000 0010 1010 */ - {STC, 2, 8, 8,L0|L1}, /* 2b: 0100 1000 0010 1011 */ - {illegal, 2,32,32,L0|L1}, /* 2c: 0100 1000 0010 1100 */ - {MUL_A, 2,32,32,L0|L1}, /* 2d: 0100 1000 0010 1101 */ - {MUL_B, 2,32,32,L0|L1}, /* 2e: 0100 1000 0010 1110 */ - {MUL_C, 2,32,32,L0|L1}, /* 2f: 0100 1000 0010 1111 */ - - {illegal, 2, 8, 8,L0|L1}, /* 30: 0100 1000 0011 0000 */ - {RLR_A, 2, 8, 8,L0|L1}, /* 31: 0100 1000 0011 0001 */ - {RLR_B, 2, 8, 8,L0|L1}, /* 32: 0100 1000 0011 0010 */ - {RLR_C, 2, 8, 8,L0|L1}, /* 33: 0100 1000 0011 0011 */ - {illegal, 2, 8, 8,L0|L1}, /* 34: 0100 1000 0011 0100 */ - {RLL_A, 2, 8, 8,L0|L1}, /* 35: 0100 1000 0011 0101 */ - {RLL_B, 2, 8, 8,L0|L1}, /* 36: 0100 1000 0011 0110 */ - {RLL_C, 2, 8, 8,L0|L1}, /* 37: 0100 1000 0011 0111 */ - {RLD, 2,17,17,L0|L1}, /* 38: 0100 1000 0011 1000 */ - {RRD, 2,17,17,L0|L1}, /* 39: 0100 1000 0011 1001 */ - {NEGA, 2, 8, 8,L0|L1}, /* 3a: 0100 1000 0011 1010 */ - {HALT, 2,12,12,L0|L1}, /* 3b: 0100 1000 0011 1011 */ - {illegal, 2, 8, 8,L0|L1}, /* 3c: 0100 1000 0011 1100 */ - {DIV_A, 2,59,59,L0|L1}, /* 3d: 0100 1000 0011 1101 */ - {DIV_B, 2,59,59,L0|L1}, /* 3e: 0100 1000 0011 1110 */ - {DIV_C, 2,59,59,L0|L1}, /* 3f: 0100 1000 0011 1111 */ - - {SKIT_NMI, 2, 8, 8,L0|L1}, /* 40: 0100 1000 0100 0000 */ - {SKIT_FT0, 2, 8, 8,L0|L1}, /* 41: 0100 1000 0100 0001 */ - {SKIT_FT1, 2, 8, 8,L0|L1}, /* 42: 0100 1000 0100 0010 */ - {SKIT_F1, 2, 8, 8,L0|L1}, /* 43: 0100 1000 0100 0011 */ - {SKIT_F2, 2, 8, 8,L0|L1}, /* 44: 0100 1000 0100 0100 */ - {SKIT_FE0, 2, 8, 8,L0|L1}, /* 45: 0100 1000 0100 0101 */ - {SKIT_FE1, 2, 8, 8,L0|L1}, /* 46: 0100 1000 0100 0110 */ - {SKIT_FEIN, 2, 8, 8,L0|L1}, /* 47: 0100 1000 0100 0111 */ - {SKIT_FAD, 2, 8, 8,L0|L1}, /* 48: 0100 1000 0100 1000 */ - {SKIT_FSR, 2, 8, 8,L0|L1}, /* 49: 0100 1000 0100 1001 */ - {SKIT_FST, 2, 8, 8,L0|L1}, /* 4a: 0100 1000 0100 1010 */ - {SKIT_ER, 2, 8, 8,L0|L1}, /* 4b: 0100 1000 0100 1011 */ - {SKIT_OV, 2, 8, 8,L0|L1}, /* 4c: 0100 1000 0100 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4d: 0100 1000 0100 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4e: 0100 1000 0100 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4f: 0100 1000 0100 1111 */ - - {SKIT_AN4, 2, 8, 8,L0|L1}, /* 50: 0100 1000 0101 0000 */ - {SKIT_AN5, 2, 8, 8,L0|L1}, /* 51: 0100 1000 0101 0001 */ - {SKIT_AN6, 2, 8, 8,L0|L1}, /* 52: 0100 1000 0101 0010 */ - {SKIT_AN7, 2, 8, 8,L0|L1}, /* 53: 0100 1000 0101 0011 */ - {SKIT_SB, 2, 8, 8,L0|L1}, /* 54: 0100 1000 0101 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 55: 0100 1000 0101 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 56: 0100 1000 0101 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 57: 0100 1000 0101 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 58: 0100 1000 0101 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 59: 0100 1000 0101 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5a: 0100 1000 0101 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5b: 0100 1000 0101 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5c: 0100 1000 0101 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5d: 0100 1000 0101 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5e: 0100 1000 0101 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5f: 0100 1000 0101 1111 */ - - {SKNIT_NMI, 2, 8, 8,L0|L1}, /* 60: 0100 1000 0110 0000 */ - {SKNIT_FT0, 2, 8, 8,L0|L1}, /* 61: 0100 1000 0110 0001 */ - {SKNIT_FT1, 2, 8, 8,L0|L1}, /* 62: 0100 1000 0110 0010 */ - {SKNIT_F1, 2, 8, 8,L0|L1}, /* 63: 0100 1000 0110 0011 */ - {SKNIT_F2, 2, 8, 8,L0|L1}, /* 64: 0100 1000 0110 0100 */ - {SKNIT_FE0, 2, 8, 8,L0|L1}, /* 65: 0100 1000 0110 0101 */ - {SKNIT_FE1, 2, 8, 8,L0|L1}, /* 66: 0100 1000 0110 0110 */ - {SKNIT_FEIN, 2, 8, 8,L0|L1}, /* 67: 0100 1000 0110 0111 */ - {SKNIT_FAD, 2, 8, 8,L0|L1}, /* 68: 0100 1000 0110 1000 */ - {SKNIT_FSR, 2, 8, 8,L0|L1}, /* 69: 0100 1000 0110 1001 */ - {SKNIT_FST, 2, 8, 8,L0|L1}, /* 6a: 0100 1000 0110 1010 */ - {SKNIT_ER, 2, 8, 8,L0|L1}, /* 6b: 0100 1000 0110 1011 */ - {SKNIT_OV, 2, 8, 8,L0|L1}, /* 6c: 0100 1000 0110 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6d: 0100 1000 0110 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6e: 0100 1000 0110 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6f: 0100 1000 0110 1111 */ - - {SKNIT_AN4, 2, 8, 8,L0|L1}, /* 70: 0100 1000 0111 0000 */ - {SKNIT_AN5, 2, 8, 8,L0|L1}, /* 71: 0100 1000 0111 0001 */ - {SKNIT_AN6, 2, 8, 8,L0|L1}, /* 72: 0100 1000 0111 0010 */ - {SKNIT_AN7, 2, 8, 8,L0|L1}, /* 73: 0100 1000 0111 0011 */ - {SKNIT_SB, 2, 8, 8,L0|L1}, /* 74: 0100 1000 0111 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 75: 0100 1000 0111 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 76: 0100 1000 0111 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 77: 0100 1000 0111 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 78: 0100 1000 0111 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 79: 0100 1000 0111 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7a: 0100 1000 0111 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7b: 0100 1000 0111 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7c: 0100 1000 0111 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7d: 0100 1000 0111 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7e: 0100 1000 0111 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7f: 0100 1000 0111 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 80: 0100 1000 1000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 81: 0100 1000 1000 0001 */ - {LDEAX_D, 2,14,11,L0|L1}, /* 82: 0100 1000 1000 0010 */ - {LDEAX_H, 2,14,11,L0|L1}, /* 83: 0100 1000 1000 0011 */ - {LDEAX_Dp, 2,14,11,L0|L1}, /* 84: 0100 1000 1000 0100 */ - {LDEAX_Hp, 2,14,11,L0|L1}, /* 85: 0100 1000 1000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 86: 0100 1000 1000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 87: 0100 1000 1000 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 88: 0100 1000 1000 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 89: 0100 1000 1000 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8a: 0100 1000 1000 1010 */ - {LDEAX_D_xx, 3,20,20,L0|L1}, /* 8b: 0100 1000 1000 1011 xxxx xxxx */ - {LDEAX_H_A, 2,20,20,L0|L1}, /* 8c: 0100 1000 1000 1100 */ - {LDEAX_H_B, 2,20,20,L0|L1}, /* 8d: 0100 1000 1000 1101 */ - {LDEAX_H_EA, 2,20,20,L0|L1}, /* 8e: 0100 1000 1000 1110 */ - {LDEAX_H_xx, 3,20,20,L0|L1}, /* 8f: 0100 1000 1000 1111 xxxx xxxx */ - - {illegal2, 2, 8, 8,L0|L1}, /* 90: 0100 1000 1000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 91: 0100 1000 1000 0001 */ - {STEAX_D, 2,14,11,L0|L1}, /* 92: 0100 1000 1000 0010 */ - {STEAX_H, 2,14,11,L0|L1}, /* 93: 0100 1000 1000 0011 */ - {STEAX_Dp, 2,14,11,L0|L1}, /* 94: 0100 1000 1000 0100 */ - {STEAX_Hp, 2,14,11,L0|L1}, /* 95: 0100 1000 1000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 96: 0100 1000 1000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 97: 0100 1000 1000 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 98: 0100 1000 1000 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 99: 0100 1000 1000 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9a: 0100 1000 1000 1010 */ - {STEAX_D_xx, 3,20,20,L0|L1}, /* 9b: 0100 1000 1000 1011 xxxx xxxx */ - {STEAX_H_A, 2,20,20,L0|L1}, /* 9c: 0100 1000 1000 1100 */ - {STEAX_H_B, 2,20,20,L0|L1}, /* 9d: 0100 1000 1000 1101 */ - {STEAX_H_EA, 2,20,20,L0|L1}, /* 9e: 0100 1000 1000 1110 */ - {STEAX_H_xx, 3,20,20,L0|L1}, /* 9f: 0100 1000 1000 1111 xxxx xxxx */ - - {DSLR_EA, 2, 8, 8,L0|L1}, /* a0: 0100 1000 1010 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* a1: 0100 1000 1010 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* a2: 0100 1000 1010 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* a3: 0100 1000 1010 0011 */ - {DSLL_EA, 2, 8, 8,L0|L1}, /* a4: 0100 1000 1010 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* a5: 0100 1000 1010 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* a6: 0100 1000 1010 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* a7: 0100 1000 1010 0111 */ - {TABLE, 2,17,17,L0|L1}, /* a8: 0100 1000 1010 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* a9: 0100 1000 1010 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* aa: 0100 1000 1010 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* ab: 0100 1000 1010 1011 */ -// {illegal2, 2, 8, 8,L0|L1}, /* ac: 0100 1000 1010 1100 */ -// {illegal2, 2, 8, 8,L0|L1}, /* ad: 0100 1000 1010 1101 */ -// {illegal2, 2, 8, 8,L0|L1}, /* ae: 0100 1000 1010 1110 */ -// {illegal2, 2, 8, 8,L0|L1}, /* af: 0100 1000 1010 1111 */ - {EXA, 2, 8, 8,L0|L1}, /* ac: 0100 1000 1010 1100 */ /* 7807 */ - {EXR, 2, 8, 8,L0|L1}, /* ad: 0100 1000 1010 1101 */ /* 7807 */ - {EXH, 2, 8, 8,L0|L1}, /* ae: 0100 1000 1010 1110 */ /* 7807 */ - {EXX, 2, 8, 8,L0|L1}, /* af: 0100 1000 1010 1111 */ /* 7807 */ - {DRLR_EA, 2, 8, 8,L0|L1}, /* b0: 0100 1000 1011 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* b1: 0100 1000 1011 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* b2: 0100 1000 1011 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* b3: 0100 1000 1011 0011 */ - {DRLL_EA, 2, 8, 8,L0|L1}, /* b4: 0100 1000 1011 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* b5: 0100 1000 1011 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* b6: 0100 1000 1011 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* b7: 0100 1000 1011 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* b8: 0100 1000 1011 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* b9: 0100 1000 1011 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* ba: 0100 1000 1011 1010 */ - {STOP, 2,12,12,L0|L1}, /* bb: 0100 1000 1011 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* bc: 0100 1000 1011 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* bd: 0100 1000 1011 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* be: 0100 1000 1011 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* bf: 0100 1000 1011 1111 */ - - {DMOV_EA_ECNT, 2,14,11,L0|L1}, /* c0: 0100 1000 1100 0000 */ - {DMOV_EA_ECPT, 2,14,11,L0|L1}, /* c1: 0100 1000 1100 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* c2: 0100 1000 1100 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* c3: 0100 1000 1100 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* c4: 0100 1000 1100 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* c5: 0100 1000 1100 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* c6: 0100 1000 1100 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* c7: 0100 1000 1100 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* c8: 0100 1000 1100 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* c9: 0100 1000 1100 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* ca: 0100 1000 1100 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* cb: 0100 1000 1100 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* cc: 0100 1000 1100 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* cd: 0100 1000 1100 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* ce: 0100 1000 1100 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* cf: 0100 1000 1100 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* d0: 0100 1000 1101 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* d1: 0100 1000 1101 0001 */ - {DMOV_ETM0_EA, 2,14,11,L0|L1}, /* d2: 0100 1000 1101 0010 */ - {DMOV_ETM1_EA, 2,14,11,L0|L1}, /* d3: 0100 1000 1101 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* d4: 0100 1000 1101 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* d5: 0100 1000 1101 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* d6: 0100 1000 1101 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* d7: 0100 1000 1101 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* d8: 0100 1000 1101 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* d9: 0100 1000 1101 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* da: 0100 1000 1101 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* db: 0100 1000 1101 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* dc: 0100 1000 1101 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* dd: 0100 1000 1101 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* de: 0100 1000 1101 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* df: 0100 1000 1101 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* e0: 0100 1000 1110 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* e1: 0100 1000 1110 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* e2: 0100 1000 1110 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* e3: 0100 1000 1110 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* e4: 0100 1000 1110 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* e5: 0100 1000 1110 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* e6: 0100 1000 1110 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* e7: 0100 1000 1110 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* e8: 0100 1000 1110 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* e9: 0100 1000 1110 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* ea: 0100 1000 1110 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* eb: 0100 1000 1110 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* ec: 0100 1000 1110 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* ed: 0100 1000 1110 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* ee: 0100 1000 1110 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* ef: 0100 1000 1110 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* f0: 0100 1000 1111 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* f1: 0100 1000 1111 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* f2: 0100 1000 1111 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* f3: 0100 1000 1111 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* f4: 0100 1000 1111 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* f5: 0100 1000 1111 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* f6: 0100 1000 1111 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* f7: 0100 1000 1111 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* f8: 0100 1000 1111 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* f9: 0100 1000 1111 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* fa: 0100 1000 1111 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* fb: 0100 1000 1111 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* fc: 0100 1000 1111 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* fd: 0100 1000 1111 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* fe: 0100 1000 1111 1110 */ - {illegal2, 2, 8, 8,L0|L1} /* ff: 0100 1000 1111 1111 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 00: 0100 1000 0000 0000 */ + {&upd7810_device::SLRC_A, 2, 8, 8,L0|L1}, /* 01: 0100 1000 0000 0001 */ + {&upd7810_device::SLRC_B, 2, 8, 8,L0|L1}, /* 02: 0100 1000 0000 0010 */ + {&upd7810_device::SLRC_C, 2, 8, 8,L0|L1}, /* 03: 0100 1000 0000 0011 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 04: 0100 1000 0000 0100 */ + {&upd7810_device::SLLC_A, 2, 8, 8,L0|L1}, /* 05: 0100 1000 0000 0101 */ + {&upd7810_device::SLLC_B, 2, 8, 8,L0|L1}, /* 06: 0100 1000 0000 0110 */ + {&upd7810_device::SLLC_C, 2, 8, 8,L0|L1}, /* 07: 0100 1000 0000 0111 */ + {&upd7810_device::SK_NV, 2, 8, 8,L0|L1}, /* 08: 0100 1000 0000 1000 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 09: 0100 1000 0000 1001 */ + {&upd7810_device::SK_CY, 2, 8, 8,L0|L1}, /* 0a: 0100 1000 0000 1010 */ + {&upd7810_device::SK_HC, 2, 8, 8,L0|L1}, /* 0b: 0100 1000 0000 1011 */ + {&upd7810_device::SK_Z, 2, 8, 8,L0|L1}, /* 0c: 0100 1000 0000 1100 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 0d: 0100 1000 0000 1101 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 0e: 0100 1000 0000 1110 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 0f: 0100 1000 0000 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 10: 0100 1000 0001 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 11: 0100 1000 0001 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 12: 0100 1000 0001 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 13: 0100 1000 0001 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 14: 0100 1000 0001 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 15: 0100 1000 0001 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 16: 0100 1000 0001 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 17: 0100 1000 0001 0111 */ + {&upd7810_device::SKN_NV, 2, 8, 8,L0|L1}, /* 18: 0100 1000 0001 1000 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 19: 0100 1000 0001 1001 */ + {&upd7810_device::SKN_CY, 2, 8, 8,L0|L1}, /* 1a: 0100 1000 0001 1010 */ + {&upd7810_device::SKN_HC, 2, 8, 8,L0|L1}, /* 1b: 0100 1000 0001 1011 */ + {&upd7810_device::SKN_Z, 2, 8, 8,L0|L1}, /* 1c: 0100 1000 0001 1100 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 1d: 0100 1000 0001 1101 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 1e: 0100 1000 0001 1110 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 1f: 0100 1000 0001 1111 */ + + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 20: 0100 1000 0010 0000 */ + {&upd7810_device::SLR_A, 2, 8, 8,L0|L1}, /* 21: 0100 1000 0010 0001 */ + {&upd7810_device::SLR_B, 2, 8, 8,L0|L1}, /* 22: 0100 1000 0010 0010 */ + {&upd7810_device::SLR_C, 2, 8, 8,L0|L1}, /* 23: 0100 1000 0010 0011 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 24: 0100 1000 0010 0100 */ + {&upd7810_device::SLL_A, 2, 8, 8,L0|L1}, /* 25: 0100 1000 0010 0101 */ + {&upd7810_device::SLL_B, 2, 8, 8,L0|L1}, /* 26: 0100 1000 0010 0110 */ + {&upd7810_device::SLL_C, 2, 8, 8,L0|L1}, /* 27: 0100 1000 0010 0111 */ + {&upd7810_device::JEA, 2, 8, 8,L0|L1}, /* 28: 0100 1000 0010 1000 */ + {&upd7810_device::CALB, 2,17,17,L0|L1}, /* 29: 0100 1000 0010 1001 */ + {&upd7810_device::CLC, 2, 8, 8,L0|L1}, /* 2a: 0100 1000 0010 1010 */ + {&upd7810_device::STC, 2, 8, 8,L0|L1}, /* 2b: 0100 1000 0010 1011 */ + {&upd7810_device::illegal, 2,32,32,L0|L1}, /* 2c: 0100 1000 0010 1100 */ + {&upd7810_device::MUL_A, 2,32,32,L0|L1}, /* 2d: 0100 1000 0010 1101 */ + {&upd7810_device::MUL_B, 2,32,32,L0|L1}, /* 2e: 0100 1000 0010 1110 */ + {&upd7810_device::MUL_C, 2,32,32,L0|L1}, /* 2f: 0100 1000 0010 1111 */ + + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 30: 0100 1000 0011 0000 */ + {&upd7810_device::RLR_A, 2, 8, 8,L0|L1}, /* 31: 0100 1000 0011 0001 */ + {&upd7810_device::RLR_B, 2, 8, 8,L0|L1}, /* 32: 0100 1000 0011 0010 */ + {&upd7810_device::RLR_C, 2, 8, 8,L0|L1}, /* 33: 0100 1000 0011 0011 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 34: 0100 1000 0011 0100 */ + {&upd7810_device::RLL_A, 2, 8, 8,L0|L1}, /* 35: 0100 1000 0011 0101 */ + {&upd7810_device::RLL_B, 2, 8, 8,L0|L1}, /* 36: 0100 1000 0011 0110 */ + {&upd7810_device::RLL_C, 2, 8, 8,L0|L1}, /* 37: 0100 1000 0011 0111 */ + {&upd7810_device::RLD, 2,17,17,L0|L1}, /* 38: 0100 1000 0011 1000 */ + {&upd7810_device::RRD, 2,17,17,L0|L1}, /* 39: 0100 1000 0011 1001 */ + {&upd7810_device::NEGA, 2, 8, 8,L0|L1}, /* 3a: 0100 1000 0011 1010 */ + {&upd7810_device::HALT, 2,12,12,L0|L1}, /* 3b: 0100 1000 0011 1011 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 3c: 0100 1000 0011 1100 */ + {&upd7810_device::DIV_A, 2,59,59,L0|L1}, /* 3d: 0100 1000 0011 1101 */ + {&upd7810_device::DIV_B, 2,59,59,L0|L1}, /* 3e: 0100 1000 0011 1110 */ + {&upd7810_device::DIV_C, 2,59,59,L0|L1}, /* 3f: 0100 1000 0011 1111 */ + + {&upd7810_device::SKIT_NMI, 2, 8, 8,L0|L1}, /* 40: 0100 1000 0100 0000 */ + {&upd7810_device::SKIT_FT0, 2, 8, 8,L0|L1}, /* 41: 0100 1000 0100 0001 */ + {&upd7810_device::SKIT_FT1, 2, 8, 8,L0|L1}, /* 42: 0100 1000 0100 0010 */ + {&upd7810_device::SKIT_F1, 2, 8, 8,L0|L1}, /* 43: 0100 1000 0100 0011 */ + {&upd7810_device::SKIT_F2, 2, 8, 8,L0|L1}, /* 44: 0100 1000 0100 0100 */ + {&upd7810_device::SKIT_FE0, 2, 8, 8,L0|L1}, /* 45: 0100 1000 0100 0101 */ + {&upd7810_device::SKIT_FE1, 2, 8, 8,L0|L1}, /* 46: 0100 1000 0100 0110 */ + {&upd7810_device::SKIT_FEIN, 2, 8, 8,L0|L1}, /* 47: 0100 1000 0100 0111 */ + {&upd7810_device::SKIT_FAD, 2, 8, 8,L0|L1}, /* 48: 0100 1000 0100 1000 */ + {&upd7810_device::SKIT_FSR, 2, 8, 8,L0|L1}, /* 49: 0100 1000 0100 1001 */ + {&upd7810_device::SKIT_FST, 2, 8, 8,L0|L1}, /* 4a: 0100 1000 0100 1010 */ + {&upd7810_device::SKIT_ER, 2, 8, 8,L0|L1}, /* 4b: 0100 1000 0100 1011 */ + {&upd7810_device::SKIT_OV, 2, 8, 8,L0|L1}, /* 4c: 0100 1000 0100 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4d: 0100 1000 0100 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4e: 0100 1000 0100 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4f: 0100 1000 0100 1111 */ + + {&upd7810_device::SKIT_AN4, 2, 8, 8,L0|L1}, /* 50: 0100 1000 0101 0000 */ + {&upd7810_device::SKIT_AN5, 2, 8, 8,L0|L1}, /* 51: 0100 1000 0101 0001 */ + {&upd7810_device::SKIT_AN6, 2, 8, 8,L0|L1}, /* 52: 0100 1000 0101 0010 */ + {&upd7810_device::SKIT_AN7, 2, 8, 8,L0|L1}, /* 53: 0100 1000 0101 0011 */ + {&upd7810_device::SKIT_SB, 2, 8, 8,L0|L1}, /* 54: 0100 1000 0101 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 55: 0100 1000 0101 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 56: 0100 1000 0101 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 57: 0100 1000 0101 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 58: 0100 1000 0101 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 59: 0100 1000 0101 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5a: 0100 1000 0101 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5b: 0100 1000 0101 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5c: 0100 1000 0101 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5d: 0100 1000 0101 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5e: 0100 1000 0101 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5f: 0100 1000 0101 1111 */ + + {&upd7810_device::SKNIT_NMI, 2, 8, 8,L0|L1}, /* 60: 0100 1000 0110 0000 */ + {&upd7810_device::SKNIT_FT0, 2, 8, 8,L0|L1}, /* 61: 0100 1000 0110 0001 */ + {&upd7810_device::SKNIT_FT1, 2, 8, 8,L0|L1}, /* 62: 0100 1000 0110 0010 */ + {&upd7810_device::SKNIT_F1, 2, 8, 8,L0|L1}, /* 63: 0100 1000 0110 0011 */ + {&upd7810_device::SKNIT_F2, 2, 8, 8,L0|L1}, /* 64: 0100 1000 0110 0100 */ + {&upd7810_device::SKNIT_FE0, 2, 8, 8,L0|L1}, /* 65: 0100 1000 0110 0101 */ + {&upd7810_device::SKNIT_FE1, 2, 8, 8,L0|L1}, /* 66: 0100 1000 0110 0110 */ + {&upd7810_device::SKNIT_FEIN, 2, 8, 8,L0|L1}, /* 67: 0100 1000 0110 0111 */ + {&upd7810_device::SKNIT_FAD, 2, 8, 8,L0|L1}, /* 68: 0100 1000 0110 1000 */ + {&upd7810_device::SKNIT_FSR, 2, 8, 8,L0|L1}, /* 69: 0100 1000 0110 1001 */ + {&upd7810_device::SKNIT_FST, 2, 8, 8,L0|L1}, /* 6a: 0100 1000 0110 1010 */ + {&upd7810_device::SKNIT_ER, 2, 8, 8,L0|L1}, /* 6b: 0100 1000 0110 1011 */ + {&upd7810_device::SKNIT_OV, 2, 8, 8,L0|L1}, /* 6c: 0100 1000 0110 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6d: 0100 1000 0110 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6e: 0100 1000 0110 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6f: 0100 1000 0110 1111 */ + + {&upd7810_device::SKNIT_AN4, 2, 8, 8,L0|L1}, /* 70: 0100 1000 0111 0000 */ + {&upd7810_device::SKNIT_AN5, 2, 8, 8,L0|L1}, /* 71: 0100 1000 0111 0001 */ + {&upd7810_device::SKNIT_AN6, 2, 8, 8,L0|L1}, /* 72: 0100 1000 0111 0010 */ + {&upd7810_device::SKNIT_AN7, 2, 8, 8,L0|L1}, /* 73: 0100 1000 0111 0011 */ + {&upd7810_device::SKNIT_SB, 2, 8, 8,L0|L1}, /* 74: 0100 1000 0111 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 75: 0100 1000 0111 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 76: 0100 1000 0111 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 77: 0100 1000 0111 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 78: 0100 1000 0111 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 79: 0100 1000 0111 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7a: 0100 1000 0111 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7b: 0100 1000 0111 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7c: 0100 1000 0111 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7d: 0100 1000 0111 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7e: 0100 1000 0111 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7f: 0100 1000 0111 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 80: 0100 1000 1000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 81: 0100 1000 1000 0001 */ + {&upd7810_device::LDEAX_D, 2,14,11,L0|L1}, /* 82: 0100 1000 1000 0010 */ + {&upd7810_device::LDEAX_H, 2,14,11,L0|L1}, /* 83: 0100 1000 1000 0011 */ + {&upd7810_device::LDEAX_Dp, 2,14,11,L0|L1}, /* 84: 0100 1000 1000 0100 */ + {&upd7810_device::LDEAX_Hp, 2,14,11,L0|L1}, /* 85: 0100 1000 1000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 86: 0100 1000 1000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 87: 0100 1000 1000 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 88: 0100 1000 1000 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 89: 0100 1000 1000 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8a: 0100 1000 1000 1010 */ + {&upd7810_device::LDEAX_D_xx, 3,20,20,L0|L1}, /* 8b: 0100 1000 1000 1011 xxxx xxxx */ + {&upd7810_device::LDEAX_H_A, 2,20,20,L0|L1}, /* 8c: 0100 1000 1000 1100 */ + {&upd7810_device::LDEAX_H_B, 2,20,20,L0|L1}, /* 8d: 0100 1000 1000 1101 */ + {&upd7810_device::LDEAX_H_EA, 2,20,20,L0|L1}, /* 8e: 0100 1000 1000 1110 */ + {&upd7810_device::LDEAX_H_xx, 3,20,20,L0|L1}, /* 8f: 0100 1000 1000 1111 xxxx xxxx */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 90: 0100 1000 1000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 91: 0100 1000 1000 0001 */ + {&upd7810_device::STEAX_D, 2,14,11,L0|L1}, /* 92: 0100 1000 1000 0010 */ + {&upd7810_device::STEAX_H, 2,14,11,L0|L1}, /* 93: 0100 1000 1000 0011 */ + {&upd7810_device::STEAX_Dp, 2,14,11,L0|L1}, /* 94: 0100 1000 1000 0100 */ + {&upd7810_device::STEAX_Hp, 2,14,11,L0|L1}, /* 95: 0100 1000 1000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 96: 0100 1000 1000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 97: 0100 1000 1000 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 98: 0100 1000 1000 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 99: 0100 1000 1000 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9a: 0100 1000 1000 1010 */ + {&upd7810_device::STEAX_D_xx, 3,20,20,L0|L1}, /* 9b: 0100 1000 1000 1011 xxxx xxxx */ + {&upd7810_device::STEAX_H_A, 2,20,20,L0|L1}, /* 9c: 0100 1000 1000 1100 */ + {&upd7810_device::STEAX_H_B, 2,20,20,L0|L1}, /* 9d: 0100 1000 1000 1101 */ + {&upd7810_device::STEAX_H_EA, 2,20,20,L0|L1}, /* 9e: 0100 1000 1000 1110 */ + {&upd7810_device::STEAX_H_xx, 3,20,20,L0|L1}, /* 9f: 0100 1000 1000 1111 xxxx xxxx */ + + {&upd7810_device::DSLR_EA, 2, 8, 8,L0|L1}, /* a0: 0100 1000 1010 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a1: 0100 1000 1010 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a2: 0100 1000 1010 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a3: 0100 1000 1010 0011 */ + {&upd7810_device::DSLL_EA, 2, 8, 8,L0|L1}, /* a4: 0100 1000 1010 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a5: 0100 1000 1010 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a6: 0100 1000 1010 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a7: 0100 1000 1010 0111 */ + {&upd7810_device::TABLE, 2,17,17,L0|L1}, /* a8: 0100 1000 1010 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a9: 0100 1000 1010 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* aa: 0100 1000 1010 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ab: 0100 1000 1010 1011 */ +// {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ac: 0100 1000 1010 1100 */ +// {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ad: 0100 1000 1010 1101 */ +// {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ae: 0100 1000 1010 1110 */ +// {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* af: 0100 1000 1010 1111 */ + {&upd7810_device::EXA, 2, 8, 8,L0|L1}, /* ac: 0100 1000 1010 1100 */ /* 7807 */ + {&upd7810_device::EXR, 2, 8, 8,L0|L1}, /* ad: 0100 1000 1010 1101 */ /* 7807 */ + {&upd7810_device::EXH, 2, 8, 8,L0|L1}, /* ae: 0100 1000 1010 1110 */ /* 7807 */ + {&upd7810_device::EXX, 2, 8, 8,L0|L1}, /* af: 0100 1000 1010 1111 */ /* 7807 */ + {&upd7810_device::DRLR_EA, 2, 8, 8,L0|L1}, /* b0: 0100 1000 1011 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b1: 0100 1000 1011 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b2: 0100 1000 1011 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b3: 0100 1000 1011 0011 */ + {&upd7810_device::DRLL_EA, 2, 8, 8,L0|L1}, /* b4: 0100 1000 1011 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b5: 0100 1000 1011 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b6: 0100 1000 1011 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b7: 0100 1000 1011 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b8: 0100 1000 1011 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b9: 0100 1000 1011 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ba: 0100 1000 1011 1010 */ + {&upd7810_device::STOP, 2,12,12,L0|L1}, /* bb: 0100 1000 1011 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bc: 0100 1000 1011 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bd: 0100 1000 1011 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* be: 0100 1000 1011 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bf: 0100 1000 1011 1111 */ + + {&upd7810_device::DMOV_EA_ECNT, 2,14,11,L0|L1}, /* c0: 0100 1000 1100 0000 */ + {&upd7810_device::DMOV_EA_ECPT, 2,14,11,L0|L1}, /* c1: 0100 1000 1100 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c2: 0100 1000 1100 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c3: 0100 1000 1100 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c4: 0100 1000 1100 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c5: 0100 1000 1100 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c6: 0100 1000 1100 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c7: 0100 1000 1100 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c8: 0100 1000 1100 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c9: 0100 1000 1100 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ca: 0100 1000 1100 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* cb: 0100 1000 1100 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* cc: 0100 1000 1100 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* cd: 0100 1000 1100 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ce: 0100 1000 1100 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* cf: 0100 1000 1100 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d0: 0100 1000 1101 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d1: 0100 1000 1101 0001 */ + {&upd7810_device::DMOV_ETM0_EA, 2,14,11,L0|L1}, /* d2: 0100 1000 1101 0010 */ + {&upd7810_device::DMOV_ETM1_EA, 2,14,11,L0|L1}, /* d3: 0100 1000 1101 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d4: 0100 1000 1101 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d5: 0100 1000 1101 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d6: 0100 1000 1101 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d7: 0100 1000 1101 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d8: 0100 1000 1101 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d9: 0100 1000 1101 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* da: 0100 1000 1101 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* db: 0100 1000 1101 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* dc: 0100 1000 1101 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* dd: 0100 1000 1101 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* de: 0100 1000 1101 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* df: 0100 1000 1101 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e0: 0100 1000 1110 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e1: 0100 1000 1110 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e2: 0100 1000 1110 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e3: 0100 1000 1110 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e4: 0100 1000 1110 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e5: 0100 1000 1110 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e6: 0100 1000 1110 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e7: 0100 1000 1110 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e8: 0100 1000 1110 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e9: 0100 1000 1110 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ea: 0100 1000 1110 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* eb: 0100 1000 1110 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ec: 0100 1000 1110 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ed: 0100 1000 1110 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ee: 0100 1000 1110 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ef: 0100 1000 1110 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f0: 0100 1000 1111 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f1: 0100 1000 1111 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f2: 0100 1000 1111 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f3: 0100 1000 1111 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f4: 0100 1000 1111 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f5: 0100 1000 1111 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f6: 0100 1000 1111 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f7: 0100 1000 1111 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f8: 0100 1000 1111 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f9: 0100 1000 1111 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* fa: 0100 1000 1111 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* fb: 0100 1000 1111 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* fc: 0100 1000 1111 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* fd: 0100 1000 1111 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* fe: 0100 1000 1111 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1} /* ff: 0100 1000 1111 1111 */ }; /* prefix 4C */ -static const struct opcode_s op4C[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op4C[256] = { - {illegal2, 2, 8, 8,L0|L1}, /* 00: 0100 1100 0000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 01: 0100 1100 0000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 02: 0100 1100 0000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 03: 0100 1100 0000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 04: 0100 1100 0000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 05: 0100 1100 0000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 06: 0100 1100 0000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 07: 0100 1100 0000 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 08: 0100 1100 0000 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 09: 0100 1100 0000 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0a: 0100 1100 0000 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0b: 0100 1100 0000 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0c: 0100 1100 0000 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0d: 0100 1100 0000 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0e: 0100 1100 0000 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0f: 0100 1100 0000 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 10: 0100 1100 0001 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 11: 0100 1100 0001 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 12: 0100 1100 0001 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 13: 0100 1100 0001 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 14: 0100 1100 0001 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 15: 0100 1100 0001 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 16: 0100 1100 0001 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 17: 0100 1100 0001 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 18: 0100 1100 0001 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 19: 0100 1100 0001 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1a: 0100 1100 0001 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1b: 0100 1100 0001 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1c: 0100 1100 0001 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1d: 0100 1100 0001 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1e: 0100 1100 0001 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1f: 0100 1100 0001 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 20: 0100 1100 0010 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 21: 0100 1100 0010 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 22: 0100 1100 0010 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 23: 0100 1100 0010 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 24: 0100 1100 0010 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 25: 0100 1100 0010 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 26: 0100 1100 0010 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 27: 0100 1100 0010 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 28: 0100 1100 0010 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 29: 0100 1100 0010 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2a: 0100 1100 0010 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2b: 0100 1100 0010 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2c: 0100 1100 0010 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2d: 0100 1100 0010 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2e: 0100 1100 0010 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2f: 0100 1100 0010 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 30: 0100 1100 0011 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 31: 0100 1100 0011 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 32: 0100 1100 0011 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 33: 0100 1100 0011 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 34: 0100 1100 0011 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 35: 0100 1100 0011 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 36: 0100 1100 0011 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 37: 0100 1100 0011 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 38: 0100 1100 0011 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 39: 0100 1100 0011 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3a: 0100 1100 0011 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3b: 0100 1100 0011 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3c: 0100 1100 0011 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3d: 0100 1100 0011 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3e: 0100 1100 0011 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3f: 0100 1100 0011 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 40: 0100 1100 0100 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 41: 0100 1100 0100 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 42: 0100 1100 0100 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 43: 0100 1100 0100 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 44: 0100 1100 0100 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 45: 0100 1100 0100 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 46: 0100 1100 0100 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 47: 0100 1100 0100 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 48: 0100 1100 0100 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 49: 0100 1100 0100 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4a: 0100 1100 0100 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4b: 0100 1100 0100 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4c: 0100 1100 0100 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4d: 0100 1100 0100 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4e: 0100 1100 0100 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4f: 0100 1100 0100 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 50: 0100 1100 0101 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 51: 0100 1100 0101 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 52: 0100 1100 0101 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 53: 0100 1100 0101 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 54: 0100 1100 0101 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 55: 0100 1100 0101 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 56: 0100 1100 0101 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 57: 0100 1100 0101 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 58: 0100 1100 0101 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 59: 0100 1100 0101 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5a: 0100 1100 0101 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5b: 0100 1100 0101 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5c: 0100 1100 0101 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5d: 0100 1100 0101 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5e: 0100 1100 0101 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5f: 0100 1100 0101 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 60: 0100 1100 0110 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 61: 0100 1100 0110 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 62: 0100 1100 0110 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 63: 0100 1100 0110 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 64: 0100 1100 0110 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 65: 0100 1100 0110 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 66: 0100 1100 0110 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 67: 0100 1100 0110 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 68: 0100 1100 0110 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 69: 0100 1100 0110 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6a: 0100 1100 0110 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6b: 0100 1100 0110 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6c: 0100 1100 0110 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6d: 0100 1100 0110 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6e: 0100 1100 0110 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6f: 0100 1100 0110 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 70: 0100 1100 0111 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 71: 0100 1100 0111 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 72: 0100 1100 0111 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 73: 0100 1100 0111 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 74: 0100 1100 0111 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 75: 0100 1100 0111 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 76: 0100 1100 0111 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 77: 0100 1100 0111 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 78: 0100 1100 0111 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 79: 0100 1100 0111 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7a: 0100 1100 0111 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7b: 0100 1100 0111 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7c: 0100 1100 0111 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7d: 0100 1100 0111 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7e: 0100 1100 0111 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7f: 0100 1100 0111 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 80: 0100 1100 1000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 81: 0100 1100 1000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 82: 0100 1100 1000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 83: 0100 1100 1000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 84: 0100 1100 1000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 85: 0100 1100 1000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 86: 0100 1100 1000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 87: 0100 1100 1000 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 88: 0100 1100 1000 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 89: 0100 1100 1000 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8a: 0100 1100 1000 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8b: 0100 1100 1000 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8c: 0100 1100 1000 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8d: 0100 1100 1000 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8e: 0100 1100 1000 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8f: 0100 1100 1000 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 90: 0100 1100 1001 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 91: 0100 1100 1001 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 92: 0100 1100 1001 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 93: 0100 1100 1001 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 94: 0100 1100 1001 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 95: 0100 1100 1001 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 96: 0100 1100 1001 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 97: 0100 1100 1001 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 98: 0100 1100 1001 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 99: 0100 1100 1001 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9a: 0100 1100 1001 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9b: 0100 1100 1001 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9c: 0100 1100 1001 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9d: 0100 1100 1001 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9e: 0100 1100 1001 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9f: 0100 1100 1001 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* a0: 0100 1100 1010 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* a1: 0100 1100 1010 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* a2: 0100 1100 1010 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* a3: 0100 1100 1010 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* a4: 0100 1100 1010 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* a5: 0100 1100 1010 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* a6: 0100 1100 1010 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* a7: 0100 1100 1010 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* a8: 0100 1100 1010 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* a9: 0100 1100 1010 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* aa: 0100 1100 1010 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* ab: 0100 1100 1010 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* ac: 0100 1100 1010 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* ad: 0100 1100 1010 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* ae: 0100 1100 1010 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* af: 0100 1100 1010 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* b0: 0100 1100 1011 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* b1: 0100 1100 1011 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* b2: 0100 1100 1011 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* b3: 0100 1100 1011 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* b4: 0100 1100 1011 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* b5: 0100 1100 1011 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* b6: 0100 1100 1011 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* b7: 0100 1100 1011 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* b8: 0100 1100 1011 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* b9: 0100 1100 1011 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* ba: 0100 1100 1011 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* bb: 0100 1100 1011 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* bc: 0100 1100 1011 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* bd: 0100 1100 1011 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* be: 0100 1100 1011 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* bf: 0100 1100 1011 1111 */ - - {MOV_A_PA, 2,10,10,L0|L1}, /* c0: 0100 1100 1100 0000 */ - {MOV_A_PB, 2,10,10,L0|L1}, /* c1: 0100 1100 1100 0001 */ - {MOV_A_PC, 2,10,10,L0|L1}, /* c2: 0100 1100 1100 0010 */ - {MOV_A_PD, 2,10,10,L0|L1}, /* c3: 0100 1100 1100 0011 */ - {illegal2, 2,10,10,L0|L1}, /* c4: 0100 1100 1100 0100 */ - {MOV_A_PF, 2,10,10,L0|L1}, /* c5: 0100 1100 1100 0101 */ - {MOV_A_MKH, 2,10,10,L0|L1}, /* c6: 0100 1100 1100 0110 */ - {MOV_A_MKL, 2,10,10,L0|L1}, /* c7: 0100 1100 1100 0111 */ - {MOV_A_ANM, 2,10,10,L0|L1}, /* c8: 0100 1100 1100 1000 */ - {MOV_A_SMH, 2,10,10,L0|L1}, /* c9: 0100 1100 1100 1001 */ - {illegal2, 2,10,10,L0|L1}, /* ca: 0100 1100 1100 1010 */ - {MOV_A_EOM, 2,10,10,L0|L1}, /* cb: 0100 1100 1100 1011 */ - {illegal2, 2,10,10,L0|L1}, /* cc: 0100 1100 1100 1100 */ - {MOV_A_TMM, 2,10,10,L0|L1}, /* cd: 0100 1100 1100 1101 */ -// {illegal2, 2,10,10,L0|L1}, /* ce: 0100 1100 1100 1110 */ - {MOV_A_PT, 2,10,10,L0|L1}, /* ce: 0100 1100 1100 1110 */ /* 7807 */ - {illegal2, 2,10,10,L0|L1}, /* cf: 0100 1100 1100 1111 */ - - {illegal2, 2,10,10,L0|L1}, /* d0: 0100 1100 1101 0000 */ - {illegal2, 2,10,10,L0|L1}, /* d1: 0100 1100 1101 0001 */ - {illegal2, 2,10,10,L0|L1}, /* d2: 0100 1100 1101 0010 */ - {illegal2, 2,10,10,L0|L1}, /* d3: 0100 1100 1101 0011 */ - {illegal2, 2,10,10,L0|L1}, /* d4: 0100 1100 1101 0100 */ - {illegal2, 2,10,10,L0|L1}, /* d5: 0100 1100 1101 0101 */ - {illegal2, 2,10,10,L0|L1}, /* d6: 0100 1100 1101 0110 */ - {illegal2, 2,10,10,L0|L1}, /* d7: 0100 1100 1101 0111 */ - {illegal2, 2,10,10,L0|L1}, /* d8: 0100 1100 1101 1000 */ - {MOV_A_RXB, 2,10,10,L0|L1}, /* d9: 0100 1100 1101 1001 */ - {illegal2, 2,10,10,L0|L1}, /* da: 0100 1100 1101 1010 */ - {illegal2, 2,10,10,L0|L1}, /* db: 0100 1100 1101 1011 */ - {illegal2, 2,10,10,L0|L1}, /* dc: 0100 1100 1101 1100 */ - {illegal2, 2,10,10,L0|L1}, /* dd: 0100 1100 1101 1101 */ - {illegal2, 2,10,10,L0|L1}, /* de: 0100 1100 1101 1110 */ - {illegal2, 2,10,10,L0|L1}, /* df: 0100 1100 1101 1111 */ - - {MOV_A_CR0, 2,10,10,L0|L1}, /* e0: 0100 1100 1110 0000 */ - {MOV_A_CR1, 2,10,10,L0|L1}, /* e1: 0100 1100 1110 0001 */ - {MOV_A_CR2, 2,10,10,L0|L1}, /* e2: 0100 1100 1110 0010 */ - {MOV_A_CR3, 2,10,10,L0|L1}, /* e3: 0100 1100 1110 0011 */ - {illegal2, 2,10,10,L0|L1}, /* e4: 0100 1100 1110 0100 */ - {illegal2, 2,10,10,L0|L1}, /* e5: 0100 1100 1110 0101 */ - {illegal2, 2,10,10,L0|L1}, /* e6: 0100 1100 1110 0110 */ - {illegal2, 2,10,10,L0|L1}, /* e7: 0100 1100 1110 0111 */ - {illegal2, 2,10,10,L0|L1}, /* e8: 0100 1100 1110 1000 */ - {illegal2, 2,10,10,L0|L1}, /* e9: 0100 1100 1110 1001 */ - {illegal2, 2,10,10,L0|L1}, /* ea: 0100 1100 1110 1010 */ - {illegal2, 2,10,10,L0|L1}, /* eb: 0100 1100 1110 1011 */ - {illegal2, 2,10,10,L0|L1}, /* ec: 0100 1100 1110 1100 */ - {illegal2, 2,10,10,L0|L1}, /* ed: 0100 1100 1110 1101 */ - {illegal2, 2,10,10,L0|L1}, /* ee: 0100 1100 1110 1110 */ - {illegal2, 2,10,10,L0|L1}, /* ef: 0100 1100 1110 1111 */ - - {illegal2, 2,10,10,L0|L1}, /* f0: 0100 1100 1111 0000 */ - {illegal2, 2,10,10,L0|L1}, /* f1: 0100 1100 1111 0001 */ - {illegal2, 2,10,10,L0|L1}, /* f2: 0100 1100 1111 0010 */ - {illegal2, 2,10,10,L0|L1}, /* f3: 0100 1100 1111 0011 */ - {illegal2, 2,10,10,L0|L1}, /* f4: 0100 1100 1111 0100 */ - {illegal2, 2,10,10,L0|L1}, /* f5: 0100 1100 1111 0101 */ - {illegal2, 2,10,10,L0|L1}, /* f6: 0100 1100 1111 0110 */ - {illegal2, 2,10,10,L0|L1}, /* f7: 0100 1100 1111 0111 */ - {illegal2, 2,10,10,L0|L1}, /* f8: 0100 1100 1111 1000 */ - {illegal2, 2,10,10,L0|L1}, /* f9: 0100 1100 1111 1001 */ - {illegal2, 2,10,10,L0|L1}, /* fa: 0100 1100 1111 1010 */ - {illegal2, 2,10,10,L0|L1}, /* fb: 0100 1100 1111 1011 */ - {illegal2, 2,10,10,L0|L1}, /* fc: 0100 1100 1111 1100 */ - {illegal2, 2,10,10,L0|L1}, /* fd: 0100 1100 1111 1101 */ - {illegal2, 2,10,10,L0|L1}, /* fe: 0100 1100 1111 1110 */ - {illegal2, 2,10,10,L0|L1}, /* ff: 0100 1100 1111 1111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 00: 0100 1100 0000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 01: 0100 1100 0000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 02: 0100 1100 0000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 03: 0100 1100 0000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 04: 0100 1100 0000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 05: 0100 1100 0000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 06: 0100 1100 0000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 07: 0100 1100 0000 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 08: 0100 1100 0000 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 09: 0100 1100 0000 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0a: 0100 1100 0000 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0b: 0100 1100 0000 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0c: 0100 1100 0000 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0d: 0100 1100 0000 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0e: 0100 1100 0000 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0f: 0100 1100 0000 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 10: 0100 1100 0001 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 11: 0100 1100 0001 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 12: 0100 1100 0001 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 13: 0100 1100 0001 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 14: 0100 1100 0001 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 15: 0100 1100 0001 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 16: 0100 1100 0001 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 17: 0100 1100 0001 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 18: 0100 1100 0001 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 19: 0100 1100 0001 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1a: 0100 1100 0001 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1b: 0100 1100 0001 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1c: 0100 1100 0001 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1d: 0100 1100 0001 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1e: 0100 1100 0001 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1f: 0100 1100 0001 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 20: 0100 1100 0010 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 21: 0100 1100 0010 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 22: 0100 1100 0010 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 23: 0100 1100 0010 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 24: 0100 1100 0010 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 25: 0100 1100 0010 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 26: 0100 1100 0010 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 27: 0100 1100 0010 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 28: 0100 1100 0010 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 29: 0100 1100 0010 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2a: 0100 1100 0010 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2b: 0100 1100 0010 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2c: 0100 1100 0010 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2d: 0100 1100 0010 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2e: 0100 1100 0010 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2f: 0100 1100 0010 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 30: 0100 1100 0011 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 31: 0100 1100 0011 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 32: 0100 1100 0011 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 33: 0100 1100 0011 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 34: 0100 1100 0011 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 35: 0100 1100 0011 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 36: 0100 1100 0011 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 37: 0100 1100 0011 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 38: 0100 1100 0011 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 39: 0100 1100 0011 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3a: 0100 1100 0011 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3b: 0100 1100 0011 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3c: 0100 1100 0011 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3d: 0100 1100 0011 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3e: 0100 1100 0011 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3f: 0100 1100 0011 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 40: 0100 1100 0100 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 41: 0100 1100 0100 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 42: 0100 1100 0100 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 43: 0100 1100 0100 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 44: 0100 1100 0100 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 45: 0100 1100 0100 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 46: 0100 1100 0100 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 47: 0100 1100 0100 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 48: 0100 1100 0100 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 49: 0100 1100 0100 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4a: 0100 1100 0100 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4b: 0100 1100 0100 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4c: 0100 1100 0100 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4d: 0100 1100 0100 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4e: 0100 1100 0100 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4f: 0100 1100 0100 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 50: 0100 1100 0101 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 51: 0100 1100 0101 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 52: 0100 1100 0101 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 53: 0100 1100 0101 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 54: 0100 1100 0101 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 55: 0100 1100 0101 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 56: 0100 1100 0101 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 57: 0100 1100 0101 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 58: 0100 1100 0101 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 59: 0100 1100 0101 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5a: 0100 1100 0101 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5b: 0100 1100 0101 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5c: 0100 1100 0101 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5d: 0100 1100 0101 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5e: 0100 1100 0101 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5f: 0100 1100 0101 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 60: 0100 1100 0110 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 61: 0100 1100 0110 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 62: 0100 1100 0110 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 63: 0100 1100 0110 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 64: 0100 1100 0110 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 65: 0100 1100 0110 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 66: 0100 1100 0110 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 67: 0100 1100 0110 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 68: 0100 1100 0110 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 69: 0100 1100 0110 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6a: 0100 1100 0110 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6b: 0100 1100 0110 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6c: 0100 1100 0110 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6d: 0100 1100 0110 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6e: 0100 1100 0110 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6f: 0100 1100 0110 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 70: 0100 1100 0111 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 71: 0100 1100 0111 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 72: 0100 1100 0111 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 73: 0100 1100 0111 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 74: 0100 1100 0111 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 75: 0100 1100 0111 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 76: 0100 1100 0111 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 77: 0100 1100 0111 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 78: 0100 1100 0111 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 79: 0100 1100 0111 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7a: 0100 1100 0111 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7b: 0100 1100 0111 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7c: 0100 1100 0111 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7d: 0100 1100 0111 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7e: 0100 1100 0111 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7f: 0100 1100 0111 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 80: 0100 1100 1000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 81: 0100 1100 1000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 82: 0100 1100 1000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 83: 0100 1100 1000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 84: 0100 1100 1000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 85: 0100 1100 1000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 86: 0100 1100 1000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 87: 0100 1100 1000 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 88: 0100 1100 1000 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 89: 0100 1100 1000 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8a: 0100 1100 1000 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8b: 0100 1100 1000 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8c: 0100 1100 1000 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8d: 0100 1100 1000 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8e: 0100 1100 1000 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8f: 0100 1100 1000 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 90: 0100 1100 1001 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 91: 0100 1100 1001 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 92: 0100 1100 1001 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 93: 0100 1100 1001 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 94: 0100 1100 1001 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 95: 0100 1100 1001 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 96: 0100 1100 1001 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 97: 0100 1100 1001 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 98: 0100 1100 1001 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 99: 0100 1100 1001 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9a: 0100 1100 1001 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9b: 0100 1100 1001 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9c: 0100 1100 1001 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9d: 0100 1100 1001 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9e: 0100 1100 1001 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9f: 0100 1100 1001 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a0: 0100 1100 1010 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a1: 0100 1100 1010 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a2: 0100 1100 1010 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a3: 0100 1100 1010 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a4: 0100 1100 1010 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a5: 0100 1100 1010 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a6: 0100 1100 1010 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a7: 0100 1100 1010 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a8: 0100 1100 1010 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a9: 0100 1100 1010 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* aa: 0100 1100 1010 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ab: 0100 1100 1010 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ac: 0100 1100 1010 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ad: 0100 1100 1010 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ae: 0100 1100 1010 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* af: 0100 1100 1010 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b0: 0100 1100 1011 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b1: 0100 1100 1011 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b2: 0100 1100 1011 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b3: 0100 1100 1011 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b4: 0100 1100 1011 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b5: 0100 1100 1011 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b6: 0100 1100 1011 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b7: 0100 1100 1011 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b8: 0100 1100 1011 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b9: 0100 1100 1011 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ba: 0100 1100 1011 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bb: 0100 1100 1011 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bc: 0100 1100 1011 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bd: 0100 1100 1011 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* be: 0100 1100 1011 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bf: 0100 1100 1011 1111 */ + + {&upd7810_device::MOV_A_PA, 2,10,10,L0|L1}, /* c0: 0100 1100 1100 0000 */ + {&upd7810_device::MOV_A_PB, 2,10,10,L0|L1}, /* c1: 0100 1100 1100 0001 */ + {&upd7810_device::MOV_A_PC, 2,10,10,L0|L1}, /* c2: 0100 1100 1100 0010 */ + {&upd7810_device::MOV_A_PD, 2,10,10,L0|L1}, /* c3: 0100 1100 1100 0011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* c4: 0100 1100 1100 0100 */ + {&upd7810_device::MOV_A_PF, 2,10,10,L0|L1}, /* c5: 0100 1100 1100 0101 */ + {&upd7810_device::MOV_A_MKH, 2,10,10,L0|L1}, /* c6: 0100 1100 1100 0110 */ + {&upd7810_device::MOV_A_MKL, 2,10,10,L0|L1}, /* c7: 0100 1100 1100 0111 */ + {&upd7810_device::MOV_A_ANM, 2,10,10,L0|L1}, /* c8: 0100 1100 1100 1000 */ + {&upd7810_device::MOV_A_SMH, 2,10,10,L0|L1}, /* c9: 0100 1100 1100 1001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ca: 0100 1100 1100 1010 */ + {&upd7810_device::MOV_A_EOM, 2,10,10,L0|L1}, /* cb: 0100 1100 1100 1011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* cc: 0100 1100 1100 1100 */ + {&upd7810_device::MOV_A_TMM, 2,10,10,L0|L1}, /* cd: 0100 1100 1100 1101 */ +// {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ce: 0100 1100 1100 1110 */ + {&upd7810_device::MOV_A_PT, 2,10,10,L0|L1}, /* ce: 0100 1100 1100 1110 */ /* 7807 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* cf: 0100 1100 1100 1111 */ + + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d0: 0100 1100 1101 0000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d1: 0100 1100 1101 0001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d2: 0100 1100 1101 0010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d3: 0100 1100 1101 0011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d4: 0100 1100 1101 0100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d5: 0100 1100 1101 0101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d6: 0100 1100 1101 0110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d7: 0100 1100 1101 0111 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d8: 0100 1100 1101 1000 */ + {&upd7810_device::MOV_A_RXB, 2,10,10,L0|L1}, /* d9: 0100 1100 1101 1001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* da: 0100 1100 1101 1010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* db: 0100 1100 1101 1011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* dc: 0100 1100 1101 1100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* dd: 0100 1100 1101 1101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* de: 0100 1100 1101 1110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* df: 0100 1100 1101 1111 */ + + {&upd7810_device::MOV_A_CR0, 2,10,10,L0|L1}, /* e0: 0100 1100 1110 0000 */ + {&upd7810_device::MOV_A_CR1, 2,10,10,L0|L1}, /* e1: 0100 1100 1110 0001 */ + {&upd7810_device::MOV_A_CR2, 2,10,10,L0|L1}, /* e2: 0100 1100 1110 0010 */ + {&upd7810_device::MOV_A_CR3, 2,10,10,L0|L1}, /* e3: 0100 1100 1110 0011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e4: 0100 1100 1110 0100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e5: 0100 1100 1110 0101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e6: 0100 1100 1110 0110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e7: 0100 1100 1110 0111 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e8: 0100 1100 1110 1000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e9: 0100 1100 1110 1001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ea: 0100 1100 1110 1010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* eb: 0100 1100 1110 1011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ec: 0100 1100 1110 1100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ed: 0100 1100 1110 1101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ee: 0100 1100 1110 1110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ef: 0100 1100 1110 1111 */ + + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f0: 0100 1100 1111 0000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f1: 0100 1100 1111 0001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f2: 0100 1100 1111 0010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f3: 0100 1100 1111 0011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f4: 0100 1100 1111 0100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f5: 0100 1100 1111 0101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f6: 0100 1100 1111 0110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f7: 0100 1100 1111 0111 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f8: 0100 1100 1111 1000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f9: 0100 1100 1111 1001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fa: 0100 1100 1111 1010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fb: 0100 1100 1111 1011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fc: 0100 1100 1111 1100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fd: 0100 1100 1111 1101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fe: 0100 1100 1111 1110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ff: 0100 1100 1111 1111 */ }; /* prefix 4D */ -static const struct opcode_s op4D[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op4D[256] = { - {illegal2, 2, 8, 8,L0|L1}, /* 00: 0100 1101 0000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 01: 0100 1101 0000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 02: 0100 1101 0000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 03: 0100 1101 0000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 04: 0100 1101 0000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 05: 0100 1101 0000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 06: 0100 1101 0000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 07: 0100 1101 0000 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 08: 0100 1101 0000 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 09: 0100 1101 0000 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0a: 0100 1101 0000 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0b: 0100 1101 0000 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0c: 0100 1101 0000 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0d: 0100 1101 0000 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0e: 0100 1101 0000 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0f: 0100 1101 0000 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 10: 0100 1101 0001 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 11: 0100 1101 0001 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 12: 0100 1101 0001 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 13: 0100 1101 0001 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 14: 0100 1101 0001 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 15: 0100 1101 0001 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 16: 0100 1101 0001 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 17: 0100 1101 0001 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 18: 0100 1101 0001 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 19: 0100 1101 0001 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1a: 0100 1101 0001 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1b: 0100 1101 0001 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1c: 0100 1101 0001 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1d: 0100 1101 0001 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1e: 0100 1101 0001 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1f: 0100 1101 0001 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 20: 0100 1101 0010 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 21: 0100 1101 0010 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 22: 0100 1101 0010 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 23: 0100 1101 0010 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 24: 0100 1101 0010 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 25: 0100 1101 0010 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 26: 0100 1101 0010 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 27: 0100 1101 0010 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 28: 0100 1101 0010 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 29: 0100 1101 0010 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2a: 0100 1101 0010 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2b: 0100 1101 0010 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2c: 0100 1101 0010 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2d: 0100 1101 0010 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2e: 0100 1101 0010 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2f: 0100 1101 0010 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 30: 0100 1101 0011 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 31: 0100 1101 0011 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 32: 0100 1101 0011 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 33: 0100 1101 0011 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 34: 0100 1101 0011 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 35: 0100 1101 0011 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 36: 0100 1101 0011 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 37: 0100 1101 0011 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 38: 0100 1101 0011 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 39: 0100 1101 0011 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3a: 0100 1101 0011 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3b: 0100 1101 0011 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3c: 0100 1101 0011 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3d: 0100 1101 0011 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3e: 0100 1101 0011 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3f: 0100 1101 0011 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 40: 0100 1101 0100 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 41: 0100 1101 0100 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 42: 0100 1101 0100 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 43: 0100 1101 0100 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 44: 0100 1101 0100 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 45: 0100 1101 0100 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 46: 0100 1101 0100 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 47: 0100 1101 0100 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 48: 0100 1101 0100 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 49: 0100 1101 0100 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4a: 0100 1101 0100 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4b: 0100 1101 0100 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4c: 0100 1101 0100 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4d: 0100 1101 0100 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4e: 0100 1101 0100 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4f: 0100 1101 0100 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 50: 0100 1101 0101 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 51: 0100 1101 0101 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 52: 0100 1101 0101 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 53: 0100 1101 0101 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 54: 0100 1101 0101 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 55: 0100 1101 0101 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 56: 0100 1101 0101 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 57: 0100 1101 0101 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 58: 0100 1101 0101 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 59: 0100 1101 0101 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5a: 0100 1101 0101 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5b: 0100 1101 0101 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5c: 0100 1101 0101 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5d: 0100 1101 0101 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5e: 0100 1101 0101 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5f: 0100 1101 0101 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 60: 0100 1101 0110 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 61: 0100 1101 0110 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 62: 0100 1101 0110 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 63: 0100 1101 0110 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 64: 0100 1101 0110 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 65: 0100 1101 0110 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 66: 0100 1101 0110 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 67: 0100 1101 0110 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 68: 0100 1101 0110 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 69: 0100 1101 0110 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6a: 0100 1101 0110 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6b: 0100 1101 0110 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6c: 0100 1101 0110 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6d: 0100 1101 0110 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6e: 0100 1101 0110 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 6f: 0100 1101 0110 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 70: 0100 1101 0111 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 71: 0100 1101 0111 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 72: 0100 1101 0111 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 73: 0100 1101 0111 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 74: 0100 1101 0111 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 75: 0100 1101 0111 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 76: 0100 1101 0111 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 77: 0100 1101 0111 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 78: 0100 1101 0111 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 79: 0100 1101 0111 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7a: 0100 1101 0111 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7b: 0100 1101 0111 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7c: 0100 1101 0111 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7d: 0100 1101 0111 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7e: 0100 1101 0111 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 7f: 0100 1101 0111 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 80: 0100 1101 1000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 81: 0100 1101 1000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 82: 0100 1101 1000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 83: 0100 1101 1000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 84: 0100 1101 1000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 85: 0100 1101 1000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 86: 0100 1101 1000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 87: 0100 1101 1000 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 88: 0100 1101 1000 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 89: 0100 1101 1000 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8a: 0100 1101 1000 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8b: 0100 1101 1000 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8c: 0100 1101 1000 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8d: 0100 1101 1000 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8e: 0100 1101 1000 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8f: 0100 1101 1000 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 90: 0100 1101 1001 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 91: 0100 1101 1001 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 92: 0100 1101 1001 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 93: 0100 1101 1001 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 94: 0100 1101 1001 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 95: 0100 1101 1001 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 96: 0100 1101 1001 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 97: 0100 1101 1001 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 98: 0100 1101 1001 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 99: 0100 1101 1001 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9a: 0100 1101 1001 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9b: 0100 1101 1001 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9c: 0100 1101 1001 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9d: 0100 1101 1001 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9e: 0100 1101 1001 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9f: 0100 1101 1001 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* a0: 0100 1101 1010 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* a1: 0100 1101 1010 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* a2: 0100 1101 1010 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* a3: 0100 1101 1010 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* a4: 0100 1101 1010 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* a5: 0100 1101 1010 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* a6: 0100 1101 1010 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* a7: 0100 1101 1010 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* a8: 0100 1101 1010 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* a9: 0100 1101 1010 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* aa: 0100 1101 1010 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* ab: 0100 1101 1010 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* ac: 0100 1101 1010 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* ad: 0100 1101 1010 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* ae: 0100 1101 1010 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* af: 0100 1101 1010 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* b0: 0100 1101 1011 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* b1: 0100 1101 1011 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* b2: 0100 1101 1011 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* b3: 0100 1101 1011 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* b4: 0100 1101 1011 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* b5: 0100 1101 1011 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* b6: 0100 1101 1011 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* b7: 0100 1101 1011 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* b8: 0100 1101 1011 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* b9: 0100 1101 1011 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* ba: 0100 1101 1011 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* bb: 0100 1101 1011 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* bc: 0100 1101 1011 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* bd: 0100 1101 1011 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* be: 0100 1101 1011 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* bf: 0100 1101 1011 1111 */ - - {MOV_PA_A, 2,10,10,L0|L1}, /* c0: 0100 1101 1100 0000 */ - {MOV_PB_A, 2,10,10,L0|L1}, /* c1: 0100 1101 1100 0001 */ - {MOV_PC_A, 2,10,10,L0|L1}, /* c2: 0100 1101 1100 0010 */ - {MOV_PD_A, 2,10,10,L0|L1}, /* c3: 0100 1101 1100 0011 */ - {illegal2, 2,10,10,L0|L1}, /* c4: 0100 1101 1100 0100 */ - {MOV_PF_A, 2,10,10,L0|L1}, /* c5: 0100 1101 1100 0101 */ - {MOV_MKH_A, 2,10,10,L0|L1}, /* c6: 0100 1101 1100 0110 */ - {MOV_MKL_A, 2,10,10,L0|L1}, /* c7: 0100 1101 1100 0111 */ - {MOV_ANM_A, 2,10,10,L0|L1}, /* c8: 0100 1101 1100 1000 */ - {MOV_SMH_A, 2,10,10,L0|L1}, /* c9: 0100 1101 1100 1001 */ - {MOV_SML_A, 2,10,10,L0|L1}, /* ca: 0100 1101 1100 1010 */ - {MOV_EOM_A, 2,10,10,L0|L1}, /* cb: 0100 1101 1100 1011 */ - {MOV_ETMM_A, 2,10,10,L0|L1}, /* cc: 0100 1101 1100 1100 */ - {MOV_TMM_A, 2,10,10,L0|L1}, /* cd: 0100 1101 1100 1101 */ - {illegal2, 2,10,10,L0|L1}, /* ce: 0100 1101 1100 1110 */ - {illegal2, 2,10,10,L0|L1}, /* cf: 0100 1101 1100 1111 */ - - {MOV_MM_A, 2,10,10,L0|L1}, /* d0: 0100 1101 1101 0000 */ - {MOV_MCC_A, 2,10,10,L0|L1}, /* d1: 0100 1101 1101 0001 */ - {MOV_MA_A, 2,10,10,L0|L1}, /* d2: 0100 1101 1101 0010 */ - {MOV_MB_A, 2,10,10,L0|L1}, /* d3: 0100 1101 1101 0011 */ - {MOV_MC_A, 2,10,10,L0|L1}, /* d4: 0100 1101 1101 0100 */ - {illegal2, 2,10,10,L0|L1}, /* d5: 0100 1101 1101 0101 */ - {illegal2, 2,10,10,L0|L1}, /* d6: 0100 1101 1101 0110 */ - {MOV_MF_A, 2,10,10,L0|L1}, /* d7: 0100 1101 1101 0111 */ - {MOV_TXB_A, 2,10,10,L0|L1}, /* d8: 0100 1101 1101 1000 */ - {illegal2, 2,10,10,L0|L1}, /* d9: 0100 1101 1101 1001 */ - {MOV_TM0_A, 2,10,10,L0|L1}, /* da: 0100 1101 1101 1010 */ - {MOV_TM1_A, 2,10,10,L0|L1}, /* db: 0100 1101 1101 1011 */ - {illegal2, 2,10,10,L0|L1}, /* dc: 0100 1101 1101 1100 */ - {illegal2, 2,10,10,L0|L1}, /* dd: 0100 1101 1101 1101 */ - {illegal2, 2,10,10,L0|L1}, /* de: 0100 1101 1101 1110 */ - {illegal2, 2,10,10,L0|L1}, /* df: 0100 1101 1101 1111 */ - - {illegal2, 2,10,10,L0|L1}, /* e0: 0100 1101 1110 0000 */ - {illegal2, 2,10,10,L0|L1}, /* e1: 0100 1101 1110 0001 */ - {illegal2, 2,10,10,L0|L1}, /* e2: 0100 1101 1110 0010 */ - {illegal2, 2,10,10,L0|L1}, /* e3: 0100 1101 1110 0011 */ - {illegal2, 2,10,10,L0|L1}, /* e4: 0100 1101 1110 0100 */ - {illegal2, 2,10,10,L0|L1}, /* e5: 0100 1101 1110 0101 */ - {illegal2, 2,10,10,L0|L1}, /* e6: 0100 1101 1110 0110 */ - {illegal2, 2,10,10,L0|L1}, /* e7: 0100 1101 1110 0111 */ - {MOV_ZCM_A, 2,10,10,L0|L1}, /* e8: 0100 1101 1110 1000 */ - {illegal2, 2,10,10,L0|L1}, /* e9: 0100 1101 1110 1001 */ - {illegal2, 2,10,10,L0|L1}, /* ea: 0100 1101 1110 1010 */ - {illegal2, 2,10,10,L0|L1}, /* eb: 0100 1101 1110 1011 */ - {illegal2, 2,10,10,L0|L1}, /* ec: 0100 1101 1110 1100 */ - {illegal2, 2,10,10,L0|L1}, /* ed: 0100 1101 1110 1101 */ - {illegal2, 2,10,10,L0|L1}, /* ee: 0100 1101 1110 1110 */ - {illegal2, 2,10,10,L0|L1}, /* ef: 0100 1101 1110 1111 */ - - {illegal2, 2,10,10,L0|L1}, /* f0: 0100 1101 1111 0000 */ - {illegal2, 2,10,10,L0|L1}, /* f1: 0100 1101 1111 0001 */ - {illegal2, 2,10,10,L0|L1}, /* f2: 0100 1101 1111 0010 */ - {illegal2, 2,10,10,L0|L1}, /* f3: 0100 1101 1111 0011 */ - {illegal2, 2,10,10,L0|L1}, /* f4: 0100 1101 1111 0100 */ - {illegal2, 2,10,10,L0|L1}, /* f5: 0100 1101 1111 0101 */ - {illegal2, 2,10,10,L0|L1}, /* f6: 0100 1101 1111 0110 */ - {illegal2, 2,10,10,L0|L1}, /* f7: 0100 1101 1111 0111 */ - {illegal2, 2,10,10,L0|L1}, /* f8: 0100 1101 1111 1000 */ - {illegal2, 2,10,10,L0|L1}, /* f9: 0100 1101 1111 1001 */ - {illegal2, 2,10,10,L0|L1}, /* fa: 0100 1101 1111 1010 */ - {illegal2, 2,10,10,L0|L1}, /* fb: 0100 1101 1111 1011 */ - {illegal2, 2,10,10,L0|L1}, /* fc: 0100 1101 1111 1100 */ - {illegal2, 2,10,10,L0|L1}, /* fd: 0100 1101 1111 1101 */ - {illegal2, 2,10,10,L0|L1}, /* fe: 0100 1101 1111 1110 */ - {illegal2, 2,10,10,L0|L1} /* ff: 0100 1101 1111 1111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 00: 0100 1101 0000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 01: 0100 1101 0000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 02: 0100 1101 0000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 03: 0100 1101 0000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 04: 0100 1101 0000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 05: 0100 1101 0000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 06: 0100 1101 0000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 07: 0100 1101 0000 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 08: 0100 1101 0000 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 09: 0100 1101 0000 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0a: 0100 1101 0000 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0b: 0100 1101 0000 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0c: 0100 1101 0000 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0d: 0100 1101 0000 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0e: 0100 1101 0000 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0f: 0100 1101 0000 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 10: 0100 1101 0001 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 11: 0100 1101 0001 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 12: 0100 1101 0001 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 13: 0100 1101 0001 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 14: 0100 1101 0001 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 15: 0100 1101 0001 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 16: 0100 1101 0001 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 17: 0100 1101 0001 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 18: 0100 1101 0001 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 19: 0100 1101 0001 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1a: 0100 1101 0001 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1b: 0100 1101 0001 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1c: 0100 1101 0001 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1d: 0100 1101 0001 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1e: 0100 1101 0001 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1f: 0100 1101 0001 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 20: 0100 1101 0010 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 21: 0100 1101 0010 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 22: 0100 1101 0010 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 23: 0100 1101 0010 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 24: 0100 1101 0010 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 25: 0100 1101 0010 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 26: 0100 1101 0010 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 27: 0100 1101 0010 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 28: 0100 1101 0010 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 29: 0100 1101 0010 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2a: 0100 1101 0010 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2b: 0100 1101 0010 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2c: 0100 1101 0010 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2d: 0100 1101 0010 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2e: 0100 1101 0010 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2f: 0100 1101 0010 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 30: 0100 1101 0011 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 31: 0100 1101 0011 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 32: 0100 1101 0011 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 33: 0100 1101 0011 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 34: 0100 1101 0011 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 35: 0100 1101 0011 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 36: 0100 1101 0011 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 37: 0100 1101 0011 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 38: 0100 1101 0011 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 39: 0100 1101 0011 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3a: 0100 1101 0011 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3b: 0100 1101 0011 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3c: 0100 1101 0011 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3d: 0100 1101 0011 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3e: 0100 1101 0011 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3f: 0100 1101 0011 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 40: 0100 1101 0100 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 41: 0100 1101 0100 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 42: 0100 1101 0100 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 43: 0100 1101 0100 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 44: 0100 1101 0100 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 45: 0100 1101 0100 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 46: 0100 1101 0100 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 47: 0100 1101 0100 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 48: 0100 1101 0100 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 49: 0100 1101 0100 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4a: 0100 1101 0100 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4b: 0100 1101 0100 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4c: 0100 1101 0100 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4d: 0100 1101 0100 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4e: 0100 1101 0100 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4f: 0100 1101 0100 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 50: 0100 1101 0101 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 51: 0100 1101 0101 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 52: 0100 1101 0101 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 53: 0100 1101 0101 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 54: 0100 1101 0101 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 55: 0100 1101 0101 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 56: 0100 1101 0101 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 57: 0100 1101 0101 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 58: 0100 1101 0101 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 59: 0100 1101 0101 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5a: 0100 1101 0101 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5b: 0100 1101 0101 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5c: 0100 1101 0101 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5d: 0100 1101 0101 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5e: 0100 1101 0101 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5f: 0100 1101 0101 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 60: 0100 1101 0110 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 61: 0100 1101 0110 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 62: 0100 1101 0110 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 63: 0100 1101 0110 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 64: 0100 1101 0110 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 65: 0100 1101 0110 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 66: 0100 1101 0110 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 67: 0100 1101 0110 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 68: 0100 1101 0110 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 69: 0100 1101 0110 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6a: 0100 1101 0110 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6b: 0100 1101 0110 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6c: 0100 1101 0110 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6d: 0100 1101 0110 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6e: 0100 1101 0110 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 6f: 0100 1101 0110 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 70: 0100 1101 0111 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 71: 0100 1101 0111 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 72: 0100 1101 0111 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 73: 0100 1101 0111 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 74: 0100 1101 0111 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 75: 0100 1101 0111 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 76: 0100 1101 0111 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 77: 0100 1101 0111 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 78: 0100 1101 0111 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 79: 0100 1101 0111 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7a: 0100 1101 0111 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7b: 0100 1101 0111 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7c: 0100 1101 0111 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7d: 0100 1101 0111 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7e: 0100 1101 0111 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 7f: 0100 1101 0111 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 80: 0100 1101 1000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 81: 0100 1101 1000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 82: 0100 1101 1000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 83: 0100 1101 1000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 84: 0100 1101 1000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 85: 0100 1101 1000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 86: 0100 1101 1000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 87: 0100 1101 1000 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 88: 0100 1101 1000 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 89: 0100 1101 1000 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8a: 0100 1101 1000 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8b: 0100 1101 1000 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8c: 0100 1101 1000 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8d: 0100 1101 1000 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8e: 0100 1101 1000 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8f: 0100 1101 1000 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 90: 0100 1101 1001 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 91: 0100 1101 1001 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 92: 0100 1101 1001 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 93: 0100 1101 1001 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 94: 0100 1101 1001 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 95: 0100 1101 1001 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 96: 0100 1101 1001 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 97: 0100 1101 1001 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 98: 0100 1101 1001 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 99: 0100 1101 1001 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9a: 0100 1101 1001 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9b: 0100 1101 1001 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9c: 0100 1101 1001 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9d: 0100 1101 1001 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9e: 0100 1101 1001 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9f: 0100 1101 1001 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a0: 0100 1101 1010 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a1: 0100 1101 1010 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a2: 0100 1101 1010 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a3: 0100 1101 1010 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a4: 0100 1101 1010 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a5: 0100 1101 1010 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a6: 0100 1101 1010 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a7: 0100 1101 1010 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a8: 0100 1101 1010 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a9: 0100 1101 1010 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* aa: 0100 1101 1010 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ab: 0100 1101 1010 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ac: 0100 1101 1010 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ad: 0100 1101 1010 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ae: 0100 1101 1010 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* af: 0100 1101 1010 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b0: 0100 1101 1011 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b1: 0100 1101 1011 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b2: 0100 1101 1011 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b3: 0100 1101 1011 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b4: 0100 1101 1011 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b5: 0100 1101 1011 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b6: 0100 1101 1011 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b7: 0100 1101 1011 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b8: 0100 1101 1011 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b9: 0100 1101 1011 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ba: 0100 1101 1011 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bb: 0100 1101 1011 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bc: 0100 1101 1011 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bd: 0100 1101 1011 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* be: 0100 1101 1011 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bf: 0100 1101 1011 1111 */ + + {&upd7810_device::MOV_PA_A, 2,10,10,L0|L1}, /* c0: 0100 1101 1100 0000 */ + {&upd7810_device::MOV_PB_A, 2,10,10,L0|L1}, /* c1: 0100 1101 1100 0001 */ + {&upd7810_device::MOV_PC_A, 2,10,10,L0|L1}, /* c2: 0100 1101 1100 0010 */ + {&upd7810_device::MOV_PD_A, 2,10,10,L0|L1}, /* c3: 0100 1101 1100 0011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* c4: 0100 1101 1100 0100 */ + {&upd7810_device::MOV_PF_A, 2,10,10,L0|L1}, /* c5: 0100 1101 1100 0101 */ + {&upd7810_device::MOV_MKH_A, 2,10,10,L0|L1}, /* c6: 0100 1101 1100 0110 */ + {&upd7810_device::MOV_MKL_A, 2,10,10,L0|L1}, /* c7: 0100 1101 1100 0111 */ + {&upd7810_device::MOV_ANM_A, 2,10,10,L0|L1}, /* c8: 0100 1101 1100 1000 */ + {&upd7810_device::MOV_SMH_A, 2,10,10,L0|L1}, /* c9: 0100 1101 1100 1001 */ + {&upd7810_device::MOV_SML_A, 2,10,10,L0|L1}, /* ca: 0100 1101 1100 1010 */ + {&upd7810_device::MOV_EOM_A, 2,10,10,L0|L1}, /* cb: 0100 1101 1100 1011 */ + {&upd7810_device::MOV_ETMM_A, 2,10,10,L0|L1}, /* cc: 0100 1101 1100 1100 */ + {&upd7810_device::MOV_TMM_A, 2,10,10,L0|L1}, /* cd: 0100 1101 1100 1101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ce: 0100 1101 1100 1110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* cf: 0100 1101 1100 1111 */ + + {&upd7810_device::MOV_MM_A, 2,10,10,L0|L1}, /* d0: 0100 1101 1101 0000 */ + {&upd7810_device::MOV_MCC_A, 2,10,10,L0|L1}, /* d1: 0100 1101 1101 0001 */ + {&upd7810_device::MOV_MA_A, 2,10,10,L0|L1}, /* d2: 0100 1101 1101 0010 */ + {&upd7810_device::MOV_MB_A, 2,10,10,L0|L1}, /* d3: 0100 1101 1101 0011 */ + {&upd7810_device::MOV_MC_A, 2,10,10,L0|L1}, /* d4: 0100 1101 1101 0100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d5: 0100 1101 1101 0101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d6: 0100 1101 1101 0110 */ + {&upd7810_device::MOV_MF_A, 2,10,10,L0|L1}, /* d7: 0100 1101 1101 0111 */ + {&upd7810_device::MOV_TXB_A, 2,10,10,L0|L1}, /* d8: 0100 1101 1101 1000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* d9: 0100 1101 1101 1001 */ + {&upd7810_device::MOV_TM0_A, 2,10,10,L0|L1}, /* da: 0100 1101 1101 1010 */ + {&upd7810_device::MOV_TM1_A, 2,10,10,L0|L1}, /* db: 0100 1101 1101 1011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* dc: 0100 1101 1101 1100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* dd: 0100 1101 1101 1101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* de: 0100 1101 1101 1110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* df: 0100 1101 1101 1111 */ + + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e0: 0100 1101 1110 0000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e1: 0100 1101 1110 0001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e2: 0100 1101 1110 0010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e3: 0100 1101 1110 0011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e4: 0100 1101 1110 0100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e5: 0100 1101 1110 0101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e6: 0100 1101 1110 0110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e7: 0100 1101 1110 0111 */ + {&upd7810_device::MOV_ZCM_A, 2,10,10,L0|L1}, /* e8: 0100 1101 1110 1000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* e9: 0100 1101 1110 1001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ea: 0100 1101 1110 1010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* eb: 0100 1101 1110 1011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ec: 0100 1101 1110 1100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ed: 0100 1101 1110 1101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ee: 0100 1101 1110 1110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* ef: 0100 1101 1110 1111 */ + + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f0: 0100 1101 1111 0000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f1: 0100 1101 1111 0001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f2: 0100 1101 1111 0010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f3: 0100 1101 1111 0011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f4: 0100 1101 1111 0100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f5: 0100 1101 1111 0101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f6: 0100 1101 1111 0110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f7: 0100 1101 1111 0111 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f8: 0100 1101 1111 1000 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* f9: 0100 1101 1111 1001 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fa: 0100 1101 1111 1010 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fb: 0100 1101 1111 1011 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fc: 0100 1101 1111 1100 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fd: 0100 1101 1111 1101 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1}, /* fe: 0100 1101 1111 1110 */ + {&upd7810_device::illegal2, 2,10,10,L0|L1} /* ff: 0100 1101 1111 1111 */ }; /* prefix 60 */ -static const struct opcode_s op60[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op60[256] = { - {illegal2, 2, 8, 8,L0|L1}, /* 00: 0110 0000 0000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 01: 0110 0000 0000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 02: 0110 0000 0000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 03: 0110 0000 0000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 04: 0110 0000 0000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 05: 0110 0000 0000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 06: 0110 0000 0000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 07: 0110 0000 0000 0111 */ - {ANA_V_A, 2, 8, 8,L0|L1}, /* 08: 0110 0000 0000 1000 */ - {ANA_A_A, 2, 8, 8,L0|L1}, /* 09: 0110 0000 0000 1001 */ - {ANA_B_A, 2, 8, 8,L0|L1}, /* 0a: 0110 0000 0000 1010 */ - {ANA_C_A, 2, 8, 8,L0|L1}, /* 0b: 0110 0000 0000 1011 */ - {ANA_D_A, 2, 8, 8,L0|L1}, /* 0c: 0110 0000 0000 1100 */ - {ANA_E_A, 2, 8, 8,L0|L1}, /* 0d: 0110 0000 0000 1101 */ - {ANA_H_A, 2, 8, 8,L0|L1}, /* 0e: 0110 0000 0000 1110 */ - {ANA_L_A, 2, 8, 8,L0|L1}, /* 0f: 0110 0000 0000 1111 */ - - {XRA_V_A, 2, 8, 8,L0|L1}, /* 10: 0110 0000 0001 0000 */ - {XRA_A_A, 2, 8, 8,L0|L1}, /* 11: 0110 0000 0001 0001 */ - {XRA_B_A, 2, 8, 8,L0|L1}, /* 12: 0110 0000 0001 0010 */ - {XRA_C_A, 2, 8, 8,L0|L1}, /* 13: 0110 0000 0001 0011 */ - {XRA_D_A, 2, 8, 8,L0|L1}, /* 14: 0110 0000 0001 0100 */ - {XRA_E_A, 2, 8, 8,L0|L1}, /* 15: 0110 0000 0001 0101 */ - {XRA_H_A, 2, 8, 8,L0|L1}, /* 16: 0110 0000 0001 0110 */ - {XRA_L_A, 2, 8, 8,L0|L1}, /* 17: 0110 0000 0001 0111 */ - {ORA_V_A, 2, 8, 8,L0|L1}, /* 18: 0110 0000 0001 1000 */ - {ORA_A_A, 2, 8, 8,L0|L1}, /* 19: 0110 0000 0001 1001 */ - {ORA_B_A, 2, 8, 8,L0|L1}, /* 1a: 0110 0000 0001 1010 */ - {ORA_C_A, 2, 8, 8,L0|L1}, /* 1b: 0110 0000 0001 1011 */ - {ORA_D_A, 2, 8, 8,L0|L1}, /* 1c: 0110 0000 0001 1100 */ - {ORA_E_A, 2, 8, 8,L0|L1}, /* 1d: 0110 0000 0001 1101 */ - {ORA_H_A, 2, 8, 8,L0|L1}, /* 1e: 0110 0000 0001 1110 */ - {ORA_L_A, 2, 8, 8,L0|L1}, /* 1f: 0110 0000 0001 1111 */ - - {ADDNC_V_A, 2, 8, 8,L0|L1}, /* 20: 0110 0000 0010 0000 */ - {ADDNC_A_A, 2, 8, 8,L0|L1}, /* 21: 0110 0000 0010 0001 */ - {ADDNC_B_A, 2, 8, 8,L0|L1}, /* 22: 0110 0000 0010 0010 */ - {ADDNC_C_A, 2, 8, 8,L0|L1}, /* 23: 0110 0000 0010 0011 */ - {ADDNC_D_A, 2, 8, 8,L0|L1}, /* 24: 0110 0000 0010 0100 */ - {ADDNC_E_A, 2, 8, 8,L0|L1}, /* 25: 0110 0000 0010 0101 */ - {ADDNC_H_A, 2, 8, 8,L0|L1}, /* 26: 0110 0000 0010 0110 */ - {ADDNC_L_A, 2, 8, 8,L0|L1}, /* 27: 0110 0000 0010 0111 */ - {GTA_V_A, 2, 8, 8,L0|L1}, /* 28: 0110 0000 0010 1000 */ - {GTA_A_A, 2, 8, 8,L0|L1}, /* 29: 0110 0000 0010 1001 */ - {GTA_B_A, 2, 8, 8,L0|L1}, /* 2a: 0110 0000 0010 1010 */ - {GTA_C_A, 2, 8, 8,L0|L1}, /* 2b: 0110 0000 0010 1011 */ - {GTA_D_A, 2, 8, 8,L0|L1}, /* 2c: 0110 0000 0010 1100 */ - {GTA_E_A, 2, 8, 8,L0|L1}, /* 2d: 0110 0000 0010 1101 */ - {GTA_H_A, 2, 8, 8,L0|L1}, /* 2e: 0110 0000 0010 1110 */ - {GTA_L_A, 2, 8, 8,L0|L1}, /* 2f: 0110 0000 0010 1111 */ - - {SUBNB_V_A, 2, 8, 8,L0|L1}, /* 30: 0110 0000 0011 0000 */ - {SUBNB_A_A, 2, 8, 8,L0|L1}, /* 31: 0110 0000 0011 0001 */ - {SUBNB_B_A, 2, 8, 8,L0|L1}, /* 32: 0110 0000 0011 0010 */ - {SUBNB_C_A, 2, 8, 8,L0|L1}, /* 33: 0110 0000 0011 0011 */ - {SUBNB_D_A, 2, 8, 8,L0|L1}, /* 34: 0110 0000 0011 0100 */ - {SUBNB_E_A, 2, 8, 8,L0|L1}, /* 35: 0110 0000 0011 0101 */ - {SUBNB_H_A, 2, 8, 8,L0|L1}, /* 36: 0110 0000 0011 0110 */ - {SUBNB_L_A, 2, 8, 8,L0|L1}, /* 37: 0110 0000 0011 0111 */ - {LTA_V_A, 2, 8, 8,L0|L1}, /* 38: 0110 0000 0011 1000 */ - {LTA_A_A, 2, 8, 8,L0|L1}, /* 39: 0110 0000 0011 1001 */ - {LTA_B_A, 2, 8, 8,L0|L1}, /* 3a: 0110 0000 0011 1010 */ - {LTA_C_A, 2, 8, 8,L0|L1}, /* 3b: 0110 0000 0011 1011 */ - {LTA_D_A, 2, 8, 8,L0|L1}, /* 3c: 0110 0000 0011 1100 */ - {LTA_E_A, 2, 8, 8,L0|L1}, /* 3d: 0110 0000 0011 1101 */ - {LTA_H_A, 2, 8, 8,L0|L1}, /* 3e: 0110 0000 0011 1110 */ - {LTA_L_A, 2, 8, 8,L0|L1}, /* 3f: 0110 0000 0011 1111 */ - - {ADD_V_A, 2, 8, 8,L0|L1}, /* 40: 0110 0000 0100 0000 */ - {ADD_A_A, 2, 8, 8,L0|L1}, /* 41: 0110 0000 0100 0001 */ - {ADD_B_A, 2, 8, 8,L0|L1}, /* 42: 0110 0000 0100 0010 */ - {ADD_C_A, 2, 8, 8,L0|L1}, /* 43: 0110 0000 0100 0011 */ - {ADD_D_A, 2, 8, 8,L0|L1}, /* 44: 0110 0000 0100 0100 */ - {ADD_E_A, 2, 8, 8,L0|L1}, /* 45: 0110 0000 0100 0101 */ - {ADD_H_A, 2, 8, 8,L0|L1}, /* 46: 0110 0000 0100 0110 */ - {ADD_L_A, 2, 8, 8,L0|L1}, /* 47: 0110 0000 0100 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 48: 0110 0000 0100 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 49: 0110 0000 0100 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4a: 0110 0000 0100 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4b: 0110 0000 0100 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4c: 0110 0000 0100 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4d: 0110 0000 0100 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4e: 0110 0000 0100 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4f: 0110 0000 0100 1111 */ - - {ADC_V_A, 2, 8, 8,L0|L1}, /* 50: 0110 0000 0101 0000 */ - {ADC_A_A, 2, 8, 8,L0|L1}, /* 51: 0110 0000 0101 0001 */ - {ADC_B_A, 2, 8, 8,L0|L1}, /* 52: 0110 0000 0101 0010 */ - {ADC_C_A, 2, 8, 8,L0|L1}, /* 53: 0110 0000 0101 0011 */ - {ADC_D_A, 2, 8, 8,L0|L1}, /* 54: 0110 0000 0101 0100 */ - {ADC_E_A, 2, 8, 8,L0|L1}, /* 55: 0110 0000 0101 0101 */ - {ADC_H_A, 2, 8, 8,L0|L1}, /* 56: 0110 0000 0101 0110 */ - {ADC_L_A, 2, 8, 8,L0|L1}, /* 57: 0110 0000 0101 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 58: 0110 0000 0101 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 59: 0110 0000 0101 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5a: 0110 0000 0101 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5b: 0110 0000 0101 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5c: 0110 0000 0101 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5d: 0110 0000 0101 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5e: 0110 0000 0101 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5f: 0110 0000 0101 1111 */ - - {SUB_V_A, 2, 8, 8,L0|L1}, /* 60: 0110 0000 0110 0000 */ - {SUB_A_A, 2, 8, 8,L0|L1}, /* 61: 0110 0000 0110 0001 */ - {SUB_B_A, 2, 8, 8,L0|L1}, /* 62: 0110 0000 0110 0010 */ - {SUB_C_A, 2, 8, 8,L0|L1}, /* 63: 0110 0000 0110 0011 */ - {SUB_D_A, 2, 8, 8,L0|L1}, /* 64: 0110 0000 0110 0100 */ - {SUB_E_A, 2, 8, 8,L0|L1}, /* 65: 0110 0000 0110 0101 */ - {SUB_H_A, 2, 8, 8,L0|L1}, /* 66: 0110 0000 0110 0110 */ - {SUB_L_A, 2, 8, 8,L0|L1}, /* 67: 0110 0000 0110 0111 */ - {NEA_V_A, 2, 8, 8,L0|L1}, /* 68: 0110 0000 0110 1000 */ - {NEA_A_A, 2, 8, 8,L0|L1}, /* 69: 0110 0000 0110 1001 */ - {NEA_B_A, 2, 8, 8,L0|L1}, /* 6a: 0110 0000 0110 1010 */ - {NEA_C_A, 2, 8, 8,L0|L1}, /* 6b: 0110 0000 0110 1011 */ - {NEA_D_A, 2, 8, 8,L0|L1}, /* 6c: 0110 0000 0110 1100 */ - {NEA_E_A, 2, 8, 8,L0|L1}, /* 6d: 0110 0000 0110 1101 */ - {NEA_H_A, 2, 8, 8,L0|L1}, /* 6e: 0110 0000 0110 1110 */ - {NEA_L_A, 2, 8, 8,L0|L1}, /* 6f: 0110 0000 0110 1111 */ - - {SBB_V_A, 2, 8, 8,L0|L1}, /* 70: 0110 0000 0111 0000 */ - {SBB_A_A, 2, 8, 8,L0|L1}, /* 71: 0110 0000 0111 0001 */ - {SBB_B_A, 2, 8, 8,L0|L1}, /* 72: 0110 0000 0111 0010 */ - {SBB_C_A, 2, 8, 8,L0|L1}, /* 73: 0110 0000 0111 0011 */ - {SBB_D_A, 2, 8, 8,L0|L1}, /* 74: 0110 0000 0111 0100 */ - {SBB_E_A, 2, 8, 8,L0|L1}, /* 75: 0110 0000 0111 0101 */ - {SBB_H_A, 2, 8, 8,L0|L1}, /* 76: 0110 0000 0111 0110 */ - {SBB_L_A, 2, 8, 8,L0|L1}, /* 77: 0110 0000 0111 0111 */ - {EQA_V_A, 2, 8, 8,L0|L1}, /* 78: 0110 0000 0111 1000 */ - {EQA_A_A, 2, 8, 8,L0|L1}, /* 79: 0110 0000 0111 1001 */ - {EQA_B_A, 2, 8, 8,L0|L1}, /* 7a: 0110 0000 0111 1010 */ - {EQA_C_A, 2, 8, 8,L0|L1}, /* 7b: 0110 0000 0111 1011 */ - {EQA_D_A, 2, 8, 8,L0|L1}, /* 7c: 0110 0000 0111 1100 */ - {EQA_E_A, 2, 8, 8,L0|L1}, /* 7d: 0110 0000 0111 1101 */ - {EQA_H_A, 2, 8, 8,L0|L1}, /* 7e: 0110 0000 0111 1110 */ - {EQA_L_A, 2, 8, 8,L0|L1}, /* 7f: 0110 0000 0111 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 80: 0110 0000 1000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 81: 0110 0000 1000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 82: 0110 0000 1000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 83: 0110 0000 1000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 84: 0110 0000 1000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 85: 0110 0000 1000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 86: 0110 0000 1000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 87: 0110 0000 1000 0111 */ - {ANA_A_V, 2, 8, 8,L0|L1}, /* 88: 0110 0000 1000 1000 */ - {ANA_A_A, 2, 8, 8,L0|L1}, /* 89: 0110 0000 1000 1001 */ - {ANA_A_B, 2, 8, 8,L0|L1}, /* 8a: 0110 0000 1000 1010 */ - {ANA_A_C, 2, 8, 8,L0|L1}, /* 8b: 0110 0000 1000 1011 */ - {ANA_A_D, 2, 8, 8,L0|L1}, /* 8c: 0110 0000 1000 1100 */ - {ANA_A_E, 2, 8, 8,L0|L1}, /* 8d: 0110 0000 1000 1101 */ - {ANA_A_H, 2, 8, 8,L0|L1}, /* 8e: 0110 0000 1000 1110 */ - {ANA_A_L, 2, 8, 8,L0|L1}, /* 8f: 0110 0000 1000 1111 */ - - {XRA_A_V, 2, 8, 8,L0|L1}, /* 90: 0110 0000 1001 0000 */ - {XRA_A_A, 2, 8, 8,L0|L1}, /* 91: 0110 0000 1001 0001 */ - {XRA_A_B, 2, 8, 8,L0|L1}, /* 92: 0110 0000 1001 0010 */ - {XRA_A_C, 2, 8, 8,L0|L1}, /* 93: 0110 0000 1001 0011 */ - {XRA_A_D, 2, 8, 8,L0|L1}, /* 94: 0110 0000 1001 0100 */ - {XRA_A_E, 2, 8, 8,L0|L1}, /* 95: 0110 0000 1001 0101 */ - {XRA_A_H, 2, 8, 8,L0|L1}, /* 96: 0110 0000 1001 0110 */ - {XRA_A_L, 2, 8, 8,L0|L1}, /* 97: 0110 0000 1001 0111 */ - {ORA_A_V, 2, 8, 8,L0|L1}, /* 98: 0110 0000 1001 1000 */ - {ORA_A_A, 2, 8, 8,L0|L1}, /* 99: 0110 0000 1001 1001 */ - {ORA_A_B, 2, 8, 8,L0|L1}, /* 9a: 0110 0000 1001 1010 */ - {ORA_A_C, 2, 8, 8,L0|L1}, /* 9b: 0110 0000 1001 1011 */ - {ORA_A_D, 2, 8, 8,L0|L1}, /* 9c: 0110 0000 1001 1100 */ - {ORA_A_E, 2, 8, 8,L0|L1}, /* 9d: 0110 0000 1001 1101 */ - {ORA_A_H, 2, 8, 8,L0|L1}, /* 9e: 0110 0000 1001 1110 */ - {ORA_A_L, 2, 8, 8,L0|L1}, /* 9f: 0110 0000 1001 1111 */ - - {ADDNC_A_V, 2, 8, 8,L0|L1}, /* a0: 0110 0000 1010 0000 */ - {ADDNC_A_A, 2, 8, 8,L0|L1}, /* a1: 0110 0000 1010 0001 */ - {ADDNC_A_B, 2, 8, 8,L0|L1}, /* a2: 0110 0000 1010 0010 */ - {ADDNC_A_C, 2, 8, 8,L0|L1}, /* a3: 0110 0000 1010 0011 */ - {ADDNC_A_D, 2, 8, 8,L0|L1}, /* a4: 0110 0000 1010 0100 */ - {ADDNC_A_E, 2, 8, 8,L0|L1}, /* a5: 0110 0000 1010 0101 */ - {ADDNC_A_H, 2, 8, 8,L0|L1}, /* a6: 0110 0000 1010 0110 */ - {ADDNC_A_L, 2, 8, 8,L0|L1}, /* a7: 0110 0000 1010 0111 */ - {GTA_A_V, 2, 8, 8,L0|L1}, /* a8: 0110 0000 1010 1000 */ - {GTA_A_A, 2, 8, 8,L0|L1}, /* a9: 0110 0000 1010 1001 */ - {GTA_A_B, 2, 8, 8,L0|L1}, /* aa: 0110 0000 1010 1010 */ - {GTA_A_C, 2, 8, 8,L0|L1}, /* ab: 0110 0000 1010 1011 */ - {GTA_A_D, 2, 8, 8,L0|L1}, /* ac: 0110 0000 1010 1100 */ - {GTA_A_E, 2, 8, 8,L0|L1}, /* ad: 0110 0000 1010 1101 */ - {GTA_A_H, 2, 8, 8,L0|L1}, /* ae: 0110 0000 1010 1110 */ - {GTA_A_L, 2, 8, 8,L0|L1}, /* af: 0110 0000 1010 1111 */ - - {SUBNB_A_V, 2, 8, 8,L0|L1}, /* b0: 0110 0000 1011 0000 */ - {SUBNB_A_A, 2, 8, 8,L0|L1}, /* b1: 0110 0000 1011 0001 */ - {SUBNB_A_B, 2, 8, 8,L0|L1}, /* b2: 0110 0000 1011 0010 */ - {SUBNB_A_C, 2, 8, 8,L0|L1}, /* b3: 0110 0000 1011 0011 */ - {SUBNB_A_D, 2, 8, 8,L0|L1}, /* b4: 0110 0000 1011 0100 */ - {SUBNB_A_E, 2, 8, 8,L0|L1}, /* b5: 0110 0000 1011 0101 */ - {SUBNB_A_H, 2, 8, 8,L0|L1}, /* b6: 0110 0000 1011 0110 */ - {SUBNB_A_L, 2, 8, 8,L0|L1}, /* b7: 0110 0000 1011 0111 */ - {LTA_A_V, 2, 8, 8,L0|L1}, /* b8: 0110 0000 1011 1000 */ - {LTA_A_A, 2, 8, 8,L0|L1}, /* b9: 0110 0000 1011 1001 */ - {LTA_A_B, 2, 8, 8,L0|L1}, /* ba: 0110 0000 1011 1010 */ - {LTA_A_C, 2, 8, 8,L0|L1}, /* bb: 0110 0000 1011 1011 */ - {LTA_A_D, 2, 8, 8,L0|L1}, /* bc: 0110 0000 1011 1100 */ - {LTA_A_E, 2, 8, 8,L0|L1}, /* bd: 0110 0000 1011 1101 */ - {LTA_A_H, 2, 8, 8,L0|L1}, /* be: 0110 0000 1011 1110 */ - {LTA_A_L, 2, 8, 8,L0|L1}, /* bf: 0110 0000 1011 1111 */ - - {ADD_A_V, 2, 8, 8,L0|L1}, /* c0: 0110 0000 1100 0000 */ - {ADD_A_A, 2, 8, 8,L0|L1}, /* c1: 0110 0000 1100 0001 */ - {ADD_A_B, 2, 8, 8,L0|L1}, /* c2: 0110 0000 1100 0010 */ - {ADD_A_C, 2, 8, 8,L0|L1}, /* c3: 0110 0000 1100 0011 */ - {ADD_A_D, 2, 8, 8,L0|L1}, /* c4: 0110 0000 1100 0100 */ - {ADD_A_E, 2, 8, 8,L0|L1}, /* c5: 0110 0000 1100 0101 */ - {ADD_A_H, 2, 8, 8,L0|L1}, /* c6: 0110 0000 1100 0110 */ - {ADD_A_L, 2, 8, 8,L0|L1}, /* c7: 0110 0000 1100 0111 */ - {ONA_A_V, 2, 8, 8,L0|L1}, /* c8: 0110 0000 1100 1000 */ - {ONA_A_A, 2, 8, 8,L0|L1}, /* c9: 0110 0000 1100 1001 */ - {ONA_A_B, 2, 8, 8,L0|L1}, /* ca: 0110 0000 1100 1010 */ - {ONA_A_C, 2, 8, 8,L0|L1}, /* cb: 0110 0000 1100 1011 */ - {ONA_A_D, 2, 8, 8,L0|L1}, /* cc: 0110 0000 1100 1100 */ - {ONA_A_E, 2, 8, 8,L0|L1}, /* cd: 0110 0000 1100 1101 */ - {ONA_A_H, 2, 8, 8,L0|L1}, /* ce: 0110 0000 1100 1110 */ - {ONA_A_L, 2, 8, 8,L0|L1}, /* cf: 0110 0000 1100 1111 */ - - {ADC_A_V, 2, 8, 8,L0|L1}, /* d0: 0110 0000 1101 0000 */ - {ADC_A_A, 2, 8, 8,L0|L1}, /* d1: 0110 0000 1101 0001 */ - {ADC_A_B, 2, 8, 8,L0|L1}, /* d2: 0110 0000 1101 0010 */ - {ADC_A_C, 2, 8, 8,L0|L1}, /* d3: 0110 0000 1101 0011 */ - {ADC_A_D, 2, 8, 8,L0|L1}, /* d4: 0110 0000 1101 0100 */ - {ADC_A_E, 2, 8, 8,L0|L1}, /* d5: 0110 0000 1101 0101 */ - {ADC_A_H, 2, 8, 8,L0|L1}, /* d6: 0110 0000 1101 0110 */ - {ADC_A_L, 2, 8, 8,L0|L1}, /* d7: 0110 0000 1101 0111 */ - {OFFA_A_V, 2, 8, 8,L0|L1}, /* d8: 0110 0000 1101 1000 */ - {OFFA_A_A, 2, 8, 8,L0|L1}, /* d9: 0110 0000 1101 1001 */ - {OFFA_A_B, 2, 8, 8,L0|L1}, /* da: 0110 0000 1101 1010 */ - {OFFA_A_C, 2, 8, 8,L0|L1}, /* db: 0110 0000 1101 1011 */ - {OFFA_A_D, 2, 8, 8,L0|L1}, /* dc: 0110 0000 1101 1100 */ - {OFFA_A_E, 2, 8, 8,L0|L1}, /* dd: 0110 0000 1101 1101 */ - {OFFA_A_H, 2, 8, 8,L0|L1}, /* de: 0110 0000 1101 1110 */ - {OFFA_A_L, 2, 8, 8,L0|L1}, /* df: 0110 0000 1101 1111 */ - - {SUB_A_V, 2, 8, 8,L0|L1}, /* e0: 0110 0000 1110 0000 */ - {SUB_A_A, 2, 8, 8,L0|L1}, /* e1: 0110 0000 1110 0001 */ - {SUB_A_B, 2, 8, 8,L0|L1}, /* e2: 0110 0000 1110 0010 */ - {SUB_A_C, 2, 8, 8,L0|L1}, /* e3: 0110 0000 1110 0011 */ - {SUB_A_D, 2, 8, 8,L0|L1}, /* e4: 0110 0000 1110 0100 */ - {SUB_A_E, 2, 8, 8,L0|L1}, /* e5: 0110 0000 1110 0101 */ - {SUB_A_H, 2, 8, 8,L0|L1}, /* e6: 0110 0000 1110 0110 */ - {SUB_A_L, 2, 8, 8,L0|L1}, /* e7: 0110 0000 1110 0111 */ - {NEA_A_V, 2, 8, 8,L0|L1}, /* e8: 0110 0000 1110 1000 */ - {NEA_A_A, 2, 8, 8,L0|L1}, /* e9: 0110 0000 1110 1001 */ - {NEA_A_B, 2, 8, 8,L0|L1}, /* ea: 0110 0000 1110 1010 */ - {NEA_A_C, 2, 8, 8,L0|L1}, /* eb: 0110 0000 1110 1011 */ - {NEA_A_D, 2, 8, 8,L0|L1}, /* ec: 0110 0000 1110 1100 */ - {NEA_A_E, 2, 8, 8,L0|L1}, /* ed: 0110 0000 1110 1101 */ - {NEA_A_H, 2, 8, 8,L0|L1}, /* ee: 0110 0000 1110 1110 */ - {NEA_A_L, 2, 8, 8,L0|L1}, /* ef: 0110 0000 1110 1111 */ - - {SBB_A_V, 2, 8, 8,L0|L1}, /* f0: 0110 0000 1111 0000 */ - {SBB_A_A, 2, 8, 8,L0|L1}, /* f1: 0110 0000 1111 0001 */ - {SBB_A_B, 2, 8, 8,L0|L1}, /* f2: 0110 0000 1111 0010 */ - {SBB_A_C, 2, 8, 8,L0|L1}, /* f3: 0110 0000 1111 0011 */ - {SBB_A_D, 2, 8, 8,L0|L1}, /* f4: 0110 0000 1111 0100 */ - {SBB_A_E, 2, 8, 8,L0|L1}, /* f5: 0110 0000 1111 0101 */ - {SBB_A_H, 2, 8, 8,L0|L1}, /* f6: 0110 0000 1111 0110 */ - {SBB_A_L, 2, 8, 8,L0|L1}, /* f7: 0110 0000 1111 0111 */ - {EQA_A_V, 2, 8, 8,L0|L1}, /* f8: 0110 0000 1111 1000 */ - {EQA_A_A, 2, 8, 8,L0|L1}, /* f9: 0110 0000 1111 1001 */ - {EQA_A_B, 2, 8, 8,L0|L1}, /* fa: 0110 0000 1111 1010 */ - {EQA_A_C, 2, 8, 8,L0|L1}, /* fb: 0110 0000 1111 1011 */ - {EQA_A_D, 2, 8, 8,L0|L1}, /* fc: 0110 0000 1111 1100 */ - {EQA_A_E, 2, 8, 8,L0|L1}, /* fd: 0110 0000 1111 1101 */ - {EQA_A_H, 2, 8, 8,L0|L1}, /* fe: 0110 0000 1111 1110 */ - {EQA_A_L, 2, 8, 8,L0|L1} /* ff: 0110 0000 1111 1111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 00: 0110 0000 0000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 01: 0110 0000 0000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 02: 0110 0000 0000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 03: 0110 0000 0000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 04: 0110 0000 0000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 05: 0110 0000 0000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 06: 0110 0000 0000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 07: 0110 0000 0000 0111 */ + {&upd7810_device::ANA_V_A, 2, 8, 8,L0|L1}, /* 08: 0110 0000 0000 1000 */ + {&upd7810_device::ANA_A_A, 2, 8, 8,L0|L1}, /* 09: 0110 0000 0000 1001 */ + {&upd7810_device::ANA_B_A, 2, 8, 8,L0|L1}, /* 0a: 0110 0000 0000 1010 */ + {&upd7810_device::ANA_C_A, 2, 8, 8,L0|L1}, /* 0b: 0110 0000 0000 1011 */ + {&upd7810_device::ANA_D_A, 2, 8, 8,L0|L1}, /* 0c: 0110 0000 0000 1100 */ + {&upd7810_device::ANA_E_A, 2, 8, 8,L0|L1}, /* 0d: 0110 0000 0000 1101 */ + {&upd7810_device::ANA_H_A, 2, 8, 8,L0|L1}, /* 0e: 0110 0000 0000 1110 */ + {&upd7810_device::ANA_L_A, 2, 8, 8,L0|L1}, /* 0f: 0110 0000 0000 1111 */ + + {&upd7810_device::XRA_V_A, 2, 8, 8,L0|L1}, /* 10: 0110 0000 0001 0000 */ + {&upd7810_device::XRA_A_A, 2, 8, 8,L0|L1}, /* 11: 0110 0000 0001 0001 */ + {&upd7810_device::XRA_B_A, 2, 8, 8,L0|L1}, /* 12: 0110 0000 0001 0010 */ + {&upd7810_device::XRA_C_A, 2, 8, 8,L0|L1}, /* 13: 0110 0000 0001 0011 */ + {&upd7810_device::XRA_D_A, 2, 8, 8,L0|L1}, /* 14: 0110 0000 0001 0100 */ + {&upd7810_device::XRA_E_A, 2, 8, 8,L0|L1}, /* 15: 0110 0000 0001 0101 */ + {&upd7810_device::XRA_H_A, 2, 8, 8,L0|L1}, /* 16: 0110 0000 0001 0110 */ + {&upd7810_device::XRA_L_A, 2, 8, 8,L0|L1}, /* 17: 0110 0000 0001 0111 */ + {&upd7810_device::ORA_V_A, 2, 8, 8,L0|L1}, /* 18: 0110 0000 0001 1000 */ + {&upd7810_device::ORA_A_A, 2, 8, 8,L0|L1}, /* 19: 0110 0000 0001 1001 */ + {&upd7810_device::ORA_B_A, 2, 8, 8,L0|L1}, /* 1a: 0110 0000 0001 1010 */ + {&upd7810_device::ORA_C_A, 2, 8, 8,L0|L1}, /* 1b: 0110 0000 0001 1011 */ + {&upd7810_device::ORA_D_A, 2, 8, 8,L0|L1}, /* 1c: 0110 0000 0001 1100 */ + {&upd7810_device::ORA_E_A, 2, 8, 8,L0|L1}, /* 1d: 0110 0000 0001 1101 */ + {&upd7810_device::ORA_H_A, 2, 8, 8,L0|L1}, /* 1e: 0110 0000 0001 1110 */ + {&upd7810_device::ORA_L_A, 2, 8, 8,L0|L1}, /* 1f: 0110 0000 0001 1111 */ + + {&upd7810_device::ADDNC_V_A, 2, 8, 8,L0|L1}, /* 20: 0110 0000 0010 0000 */ + {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0|L1}, /* 21: 0110 0000 0010 0001 */ + {&upd7810_device::ADDNC_B_A, 2, 8, 8,L0|L1}, /* 22: 0110 0000 0010 0010 */ + {&upd7810_device::ADDNC_C_A, 2, 8, 8,L0|L1}, /* 23: 0110 0000 0010 0011 */ + {&upd7810_device::ADDNC_D_A, 2, 8, 8,L0|L1}, /* 24: 0110 0000 0010 0100 */ + {&upd7810_device::ADDNC_E_A, 2, 8, 8,L0|L1}, /* 25: 0110 0000 0010 0101 */ + {&upd7810_device::ADDNC_H_A, 2, 8, 8,L0|L1}, /* 26: 0110 0000 0010 0110 */ + {&upd7810_device::ADDNC_L_A, 2, 8, 8,L0|L1}, /* 27: 0110 0000 0010 0111 */ + {&upd7810_device::GTA_V_A, 2, 8, 8,L0|L1}, /* 28: 0110 0000 0010 1000 */ + {&upd7810_device::GTA_A_A, 2, 8, 8,L0|L1}, /* 29: 0110 0000 0010 1001 */ + {&upd7810_device::GTA_B_A, 2, 8, 8,L0|L1}, /* 2a: 0110 0000 0010 1010 */ + {&upd7810_device::GTA_C_A, 2, 8, 8,L0|L1}, /* 2b: 0110 0000 0010 1011 */ + {&upd7810_device::GTA_D_A, 2, 8, 8,L0|L1}, /* 2c: 0110 0000 0010 1100 */ + {&upd7810_device::GTA_E_A, 2, 8, 8,L0|L1}, /* 2d: 0110 0000 0010 1101 */ + {&upd7810_device::GTA_H_A, 2, 8, 8,L0|L1}, /* 2e: 0110 0000 0010 1110 */ + {&upd7810_device::GTA_L_A, 2, 8, 8,L0|L1}, /* 2f: 0110 0000 0010 1111 */ + + {&upd7810_device::SUBNB_V_A, 2, 8, 8,L0|L1}, /* 30: 0110 0000 0011 0000 */ + {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0|L1}, /* 31: 0110 0000 0011 0001 */ + {&upd7810_device::SUBNB_B_A, 2, 8, 8,L0|L1}, /* 32: 0110 0000 0011 0010 */ + {&upd7810_device::SUBNB_C_A, 2, 8, 8,L0|L1}, /* 33: 0110 0000 0011 0011 */ + {&upd7810_device::SUBNB_D_A, 2, 8, 8,L0|L1}, /* 34: 0110 0000 0011 0100 */ + {&upd7810_device::SUBNB_E_A, 2, 8, 8,L0|L1}, /* 35: 0110 0000 0011 0101 */ + {&upd7810_device::SUBNB_H_A, 2, 8, 8,L0|L1}, /* 36: 0110 0000 0011 0110 */ + {&upd7810_device::SUBNB_L_A, 2, 8, 8,L0|L1}, /* 37: 0110 0000 0011 0111 */ + {&upd7810_device::LTA_V_A, 2, 8, 8,L0|L1}, /* 38: 0110 0000 0011 1000 */ + {&upd7810_device::LTA_A_A, 2, 8, 8,L0|L1}, /* 39: 0110 0000 0011 1001 */ + {&upd7810_device::LTA_B_A, 2, 8, 8,L0|L1}, /* 3a: 0110 0000 0011 1010 */ + {&upd7810_device::LTA_C_A, 2, 8, 8,L0|L1}, /* 3b: 0110 0000 0011 1011 */ + {&upd7810_device::LTA_D_A, 2, 8, 8,L0|L1}, /* 3c: 0110 0000 0011 1100 */ + {&upd7810_device::LTA_E_A, 2, 8, 8,L0|L1}, /* 3d: 0110 0000 0011 1101 */ + {&upd7810_device::LTA_H_A, 2, 8, 8,L0|L1}, /* 3e: 0110 0000 0011 1110 */ + {&upd7810_device::LTA_L_A, 2, 8, 8,L0|L1}, /* 3f: 0110 0000 0011 1111 */ + + {&upd7810_device::ADD_V_A, 2, 8, 8,L0|L1}, /* 40: 0110 0000 0100 0000 */ + {&upd7810_device::ADD_A_A, 2, 8, 8,L0|L1}, /* 41: 0110 0000 0100 0001 */ + {&upd7810_device::ADD_B_A, 2, 8, 8,L0|L1}, /* 42: 0110 0000 0100 0010 */ + {&upd7810_device::ADD_C_A, 2, 8, 8,L0|L1}, /* 43: 0110 0000 0100 0011 */ + {&upd7810_device::ADD_D_A, 2, 8, 8,L0|L1}, /* 44: 0110 0000 0100 0100 */ + {&upd7810_device::ADD_E_A, 2, 8, 8,L0|L1}, /* 45: 0110 0000 0100 0101 */ + {&upd7810_device::ADD_H_A, 2, 8, 8,L0|L1}, /* 46: 0110 0000 0100 0110 */ + {&upd7810_device::ADD_L_A, 2, 8, 8,L0|L1}, /* 47: 0110 0000 0100 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 48: 0110 0000 0100 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 49: 0110 0000 0100 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4a: 0110 0000 0100 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4b: 0110 0000 0100 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4c: 0110 0000 0100 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4d: 0110 0000 0100 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4e: 0110 0000 0100 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4f: 0110 0000 0100 1111 */ + + {&upd7810_device::ADC_V_A, 2, 8, 8,L0|L1}, /* 50: 0110 0000 0101 0000 */ + {&upd7810_device::ADC_A_A, 2, 8, 8,L0|L1}, /* 51: 0110 0000 0101 0001 */ + {&upd7810_device::ADC_B_A, 2, 8, 8,L0|L1}, /* 52: 0110 0000 0101 0010 */ + {&upd7810_device::ADC_C_A, 2, 8, 8,L0|L1}, /* 53: 0110 0000 0101 0011 */ + {&upd7810_device::ADC_D_A, 2, 8, 8,L0|L1}, /* 54: 0110 0000 0101 0100 */ + {&upd7810_device::ADC_E_A, 2, 8, 8,L0|L1}, /* 55: 0110 0000 0101 0101 */ + {&upd7810_device::ADC_H_A, 2, 8, 8,L0|L1}, /* 56: 0110 0000 0101 0110 */ + {&upd7810_device::ADC_L_A, 2, 8, 8,L0|L1}, /* 57: 0110 0000 0101 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 58: 0110 0000 0101 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 59: 0110 0000 0101 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5a: 0110 0000 0101 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5b: 0110 0000 0101 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5c: 0110 0000 0101 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5d: 0110 0000 0101 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5e: 0110 0000 0101 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5f: 0110 0000 0101 1111 */ + + {&upd7810_device::SUB_V_A, 2, 8, 8,L0|L1}, /* 60: 0110 0000 0110 0000 */ + {&upd7810_device::SUB_A_A, 2, 8, 8,L0|L1}, /* 61: 0110 0000 0110 0001 */ + {&upd7810_device::SUB_B_A, 2, 8, 8,L0|L1}, /* 62: 0110 0000 0110 0010 */ + {&upd7810_device::SUB_C_A, 2, 8, 8,L0|L1}, /* 63: 0110 0000 0110 0011 */ + {&upd7810_device::SUB_D_A, 2, 8, 8,L0|L1}, /* 64: 0110 0000 0110 0100 */ + {&upd7810_device::SUB_E_A, 2, 8, 8,L0|L1}, /* 65: 0110 0000 0110 0101 */ + {&upd7810_device::SUB_H_A, 2, 8, 8,L0|L1}, /* 66: 0110 0000 0110 0110 */ + {&upd7810_device::SUB_L_A, 2, 8, 8,L0|L1}, /* 67: 0110 0000 0110 0111 */ + {&upd7810_device::NEA_V_A, 2, 8, 8,L0|L1}, /* 68: 0110 0000 0110 1000 */ + {&upd7810_device::NEA_A_A, 2, 8, 8,L0|L1}, /* 69: 0110 0000 0110 1001 */ + {&upd7810_device::NEA_B_A, 2, 8, 8,L0|L1}, /* 6a: 0110 0000 0110 1010 */ + {&upd7810_device::NEA_C_A, 2, 8, 8,L0|L1}, /* 6b: 0110 0000 0110 1011 */ + {&upd7810_device::NEA_D_A, 2, 8, 8,L0|L1}, /* 6c: 0110 0000 0110 1100 */ + {&upd7810_device::NEA_E_A, 2, 8, 8,L0|L1}, /* 6d: 0110 0000 0110 1101 */ + {&upd7810_device::NEA_H_A, 2, 8, 8,L0|L1}, /* 6e: 0110 0000 0110 1110 */ + {&upd7810_device::NEA_L_A, 2, 8, 8,L0|L1}, /* 6f: 0110 0000 0110 1111 */ + + {&upd7810_device::SBB_V_A, 2, 8, 8,L0|L1}, /* 70: 0110 0000 0111 0000 */ + {&upd7810_device::SBB_A_A, 2, 8, 8,L0|L1}, /* 71: 0110 0000 0111 0001 */ + {&upd7810_device::SBB_B_A, 2, 8, 8,L0|L1}, /* 72: 0110 0000 0111 0010 */ + {&upd7810_device::SBB_C_A, 2, 8, 8,L0|L1}, /* 73: 0110 0000 0111 0011 */ + {&upd7810_device::SBB_D_A, 2, 8, 8,L0|L1}, /* 74: 0110 0000 0111 0100 */ + {&upd7810_device::SBB_E_A, 2, 8, 8,L0|L1}, /* 75: 0110 0000 0111 0101 */ + {&upd7810_device::SBB_H_A, 2, 8, 8,L0|L1}, /* 76: 0110 0000 0111 0110 */ + {&upd7810_device::SBB_L_A, 2, 8, 8,L0|L1}, /* 77: 0110 0000 0111 0111 */ + {&upd7810_device::EQA_V_A, 2, 8, 8,L0|L1}, /* 78: 0110 0000 0111 1000 */ + {&upd7810_device::EQA_A_A, 2, 8, 8,L0|L1}, /* 79: 0110 0000 0111 1001 */ + {&upd7810_device::EQA_B_A, 2, 8, 8,L0|L1}, /* 7a: 0110 0000 0111 1010 */ + {&upd7810_device::EQA_C_A, 2, 8, 8,L0|L1}, /* 7b: 0110 0000 0111 1011 */ + {&upd7810_device::EQA_D_A, 2, 8, 8,L0|L1}, /* 7c: 0110 0000 0111 1100 */ + {&upd7810_device::EQA_E_A, 2, 8, 8,L0|L1}, /* 7d: 0110 0000 0111 1101 */ + {&upd7810_device::EQA_H_A, 2, 8, 8,L0|L1}, /* 7e: 0110 0000 0111 1110 */ + {&upd7810_device::EQA_L_A, 2, 8, 8,L0|L1}, /* 7f: 0110 0000 0111 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 80: 0110 0000 1000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 81: 0110 0000 1000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 82: 0110 0000 1000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 83: 0110 0000 1000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 84: 0110 0000 1000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 85: 0110 0000 1000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 86: 0110 0000 1000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 87: 0110 0000 1000 0111 */ + {&upd7810_device::ANA_A_V, 2, 8, 8,L0|L1}, /* 88: 0110 0000 1000 1000 */ + {&upd7810_device::ANA_A_A, 2, 8, 8,L0|L1}, /* 89: 0110 0000 1000 1001 */ + {&upd7810_device::ANA_A_B, 2, 8, 8,L0|L1}, /* 8a: 0110 0000 1000 1010 */ + {&upd7810_device::ANA_A_C, 2, 8, 8,L0|L1}, /* 8b: 0110 0000 1000 1011 */ + {&upd7810_device::ANA_A_D, 2, 8, 8,L0|L1}, /* 8c: 0110 0000 1000 1100 */ + {&upd7810_device::ANA_A_E, 2, 8, 8,L0|L1}, /* 8d: 0110 0000 1000 1101 */ + {&upd7810_device::ANA_A_H, 2, 8, 8,L0|L1}, /* 8e: 0110 0000 1000 1110 */ + {&upd7810_device::ANA_A_L, 2, 8, 8,L0|L1}, /* 8f: 0110 0000 1000 1111 */ + + {&upd7810_device::XRA_A_V, 2, 8, 8,L0|L1}, /* 90: 0110 0000 1001 0000 */ + {&upd7810_device::XRA_A_A, 2, 8, 8,L0|L1}, /* 91: 0110 0000 1001 0001 */ + {&upd7810_device::XRA_A_B, 2, 8, 8,L0|L1}, /* 92: 0110 0000 1001 0010 */ + {&upd7810_device::XRA_A_C, 2, 8, 8,L0|L1}, /* 93: 0110 0000 1001 0011 */ + {&upd7810_device::XRA_A_D, 2, 8, 8,L0|L1}, /* 94: 0110 0000 1001 0100 */ + {&upd7810_device::XRA_A_E, 2, 8, 8,L0|L1}, /* 95: 0110 0000 1001 0101 */ + {&upd7810_device::XRA_A_H, 2, 8, 8,L0|L1}, /* 96: 0110 0000 1001 0110 */ + {&upd7810_device::XRA_A_L, 2, 8, 8,L0|L1}, /* 97: 0110 0000 1001 0111 */ + {&upd7810_device::ORA_A_V, 2, 8, 8,L0|L1}, /* 98: 0110 0000 1001 1000 */ + {&upd7810_device::ORA_A_A, 2, 8, 8,L0|L1}, /* 99: 0110 0000 1001 1001 */ + {&upd7810_device::ORA_A_B, 2, 8, 8,L0|L1}, /* 9a: 0110 0000 1001 1010 */ + {&upd7810_device::ORA_A_C, 2, 8, 8,L0|L1}, /* 9b: 0110 0000 1001 1011 */ + {&upd7810_device::ORA_A_D, 2, 8, 8,L0|L1}, /* 9c: 0110 0000 1001 1100 */ + {&upd7810_device::ORA_A_E, 2, 8, 8,L0|L1}, /* 9d: 0110 0000 1001 1101 */ + {&upd7810_device::ORA_A_H, 2, 8, 8,L0|L1}, /* 9e: 0110 0000 1001 1110 */ + {&upd7810_device::ORA_A_L, 2, 8, 8,L0|L1}, /* 9f: 0110 0000 1001 1111 */ + + {&upd7810_device::ADDNC_A_V, 2, 8, 8,L0|L1}, /* a0: 0110 0000 1010 0000 */ + {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0|L1}, /* a1: 0110 0000 1010 0001 */ + {&upd7810_device::ADDNC_A_B, 2, 8, 8,L0|L1}, /* a2: 0110 0000 1010 0010 */ + {&upd7810_device::ADDNC_A_C, 2, 8, 8,L0|L1}, /* a3: 0110 0000 1010 0011 */ + {&upd7810_device::ADDNC_A_D, 2, 8, 8,L0|L1}, /* a4: 0110 0000 1010 0100 */ + {&upd7810_device::ADDNC_A_E, 2, 8, 8,L0|L1}, /* a5: 0110 0000 1010 0101 */ + {&upd7810_device::ADDNC_A_H, 2, 8, 8,L0|L1}, /* a6: 0110 0000 1010 0110 */ + {&upd7810_device::ADDNC_A_L, 2, 8, 8,L0|L1}, /* a7: 0110 0000 1010 0111 */ + {&upd7810_device::GTA_A_V, 2, 8, 8,L0|L1}, /* a8: 0110 0000 1010 1000 */ + {&upd7810_device::GTA_A_A, 2, 8, 8,L0|L1}, /* a9: 0110 0000 1010 1001 */ + {&upd7810_device::GTA_A_B, 2, 8, 8,L0|L1}, /* aa: 0110 0000 1010 1010 */ + {&upd7810_device::GTA_A_C, 2, 8, 8,L0|L1}, /* ab: 0110 0000 1010 1011 */ + {&upd7810_device::GTA_A_D, 2, 8, 8,L0|L1}, /* ac: 0110 0000 1010 1100 */ + {&upd7810_device::GTA_A_E, 2, 8, 8,L0|L1}, /* ad: 0110 0000 1010 1101 */ + {&upd7810_device::GTA_A_H, 2, 8, 8,L0|L1}, /* ae: 0110 0000 1010 1110 */ + {&upd7810_device::GTA_A_L, 2, 8, 8,L0|L1}, /* af: 0110 0000 1010 1111 */ + + {&upd7810_device::SUBNB_A_V, 2, 8, 8,L0|L1}, /* b0: 0110 0000 1011 0000 */ + {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0|L1}, /* b1: 0110 0000 1011 0001 */ + {&upd7810_device::SUBNB_A_B, 2, 8, 8,L0|L1}, /* b2: 0110 0000 1011 0010 */ + {&upd7810_device::SUBNB_A_C, 2, 8, 8,L0|L1}, /* b3: 0110 0000 1011 0011 */ + {&upd7810_device::SUBNB_A_D, 2, 8, 8,L0|L1}, /* b4: 0110 0000 1011 0100 */ + {&upd7810_device::SUBNB_A_E, 2, 8, 8,L0|L1}, /* b5: 0110 0000 1011 0101 */ + {&upd7810_device::SUBNB_A_H, 2, 8, 8,L0|L1}, /* b6: 0110 0000 1011 0110 */ + {&upd7810_device::SUBNB_A_L, 2, 8, 8,L0|L1}, /* b7: 0110 0000 1011 0111 */ + {&upd7810_device::LTA_A_V, 2, 8, 8,L0|L1}, /* b8: 0110 0000 1011 1000 */ + {&upd7810_device::LTA_A_A, 2, 8, 8,L0|L1}, /* b9: 0110 0000 1011 1001 */ + {&upd7810_device::LTA_A_B, 2, 8, 8,L0|L1}, /* ba: 0110 0000 1011 1010 */ + {&upd7810_device::LTA_A_C, 2, 8, 8,L0|L1}, /* bb: 0110 0000 1011 1011 */ + {&upd7810_device::LTA_A_D, 2, 8, 8,L0|L1}, /* bc: 0110 0000 1011 1100 */ + {&upd7810_device::LTA_A_E, 2, 8, 8,L0|L1}, /* bd: 0110 0000 1011 1101 */ + {&upd7810_device::LTA_A_H, 2, 8, 8,L0|L1}, /* be: 0110 0000 1011 1110 */ + {&upd7810_device::LTA_A_L, 2, 8, 8,L0|L1}, /* bf: 0110 0000 1011 1111 */ + + {&upd7810_device::ADD_A_V, 2, 8, 8,L0|L1}, /* c0: 0110 0000 1100 0000 */ + {&upd7810_device::ADD_A_A, 2, 8, 8,L0|L1}, /* c1: 0110 0000 1100 0001 */ + {&upd7810_device::ADD_A_B, 2, 8, 8,L0|L1}, /* c2: 0110 0000 1100 0010 */ + {&upd7810_device::ADD_A_C, 2, 8, 8,L0|L1}, /* c3: 0110 0000 1100 0011 */ + {&upd7810_device::ADD_A_D, 2, 8, 8,L0|L1}, /* c4: 0110 0000 1100 0100 */ + {&upd7810_device::ADD_A_E, 2, 8, 8,L0|L1}, /* c5: 0110 0000 1100 0101 */ + {&upd7810_device::ADD_A_H, 2, 8, 8,L0|L1}, /* c6: 0110 0000 1100 0110 */ + {&upd7810_device::ADD_A_L, 2, 8, 8,L0|L1}, /* c7: 0110 0000 1100 0111 */ + {&upd7810_device::ONA_A_V, 2, 8, 8,L0|L1}, /* c8: 0110 0000 1100 1000 */ + {&upd7810_device::ONA_A_A, 2, 8, 8,L0|L1}, /* c9: 0110 0000 1100 1001 */ + {&upd7810_device::ONA_A_B, 2, 8, 8,L0|L1}, /* ca: 0110 0000 1100 1010 */ + {&upd7810_device::ONA_A_C, 2, 8, 8,L0|L1}, /* cb: 0110 0000 1100 1011 */ + {&upd7810_device::ONA_A_D, 2, 8, 8,L0|L1}, /* cc: 0110 0000 1100 1100 */ + {&upd7810_device::ONA_A_E, 2, 8, 8,L0|L1}, /* cd: 0110 0000 1100 1101 */ + {&upd7810_device::ONA_A_H, 2, 8, 8,L0|L1}, /* ce: 0110 0000 1100 1110 */ + {&upd7810_device::ONA_A_L, 2, 8, 8,L0|L1}, /* cf: 0110 0000 1100 1111 */ + + {&upd7810_device::ADC_A_V, 2, 8, 8,L0|L1}, /* d0: 0110 0000 1101 0000 */ + {&upd7810_device::ADC_A_A, 2, 8, 8,L0|L1}, /* d1: 0110 0000 1101 0001 */ + {&upd7810_device::ADC_A_B, 2, 8, 8,L0|L1}, /* d2: 0110 0000 1101 0010 */ + {&upd7810_device::ADC_A_C, 2, 8, 8,L0|L1}, /* d3: 0110 0000 1101 0011 */ + {&upd7810_device::ADC_A_D, 2, 8, 8,L0|L1}, /* d4: 0110 0000 1101 0100 */ + {&upd7810_device::ADC_A_E, 2, 8, 8,L0|L1}, /* d5: 0110 0000 1101 0101 */ + {&upd7810_device::ADC_A_H, 2, 8, 8,L0|L1}, /* d6: 0110 0000 1101 0110 */ + {&upd7810_device::ADC_A_L, 2, 8, 8,L0|L1}, /* d7: 0110 0000 1101 0111 */ + {&upd7810_device::OFFA_A_V, 2, 8, 8,L0|L1}, /* d8: 0110 0000 1101 1000 */ + {&upd7810_device::OFFA_A_A, 2, 8, 8,L0|L1}, /* d9: 0110 0000 1101 1001 */ + {&upd7810_device::OFFA_A_B, 2, 8, 8,L0|L1}, /* da: 0110 0000 1101 1010 */ + {&upd7810_device::OFFA_A_C, 2, 8, 8,L0|L1}, /* db: 0110 0000 1101 1011 */ + {&upd7810_device::OFFA_A_D, 2, 8, 8,L0|L1}, /* dc: 0110 0000 1101 1100 */ + {&upd7810_device::OFFA_A_E, 2, 8, 8,L0|L1}, /* dd: 0110 0000 1101 1101 */ + {&upd7810_device::OFFA_A_H, 2, 8, 8,L0|L1}, /* de: 0110 0000 1101 1110 */ + {&upd7810_device::OFFA_A_L, 2, 8, 8,L0|L1}, /* df: 0110 0000 1101 1111 */ + + {&upd7810_device::SUB_A_V, 2, 8, 8,L0|L1}, /* e0: 0110 0000 1110 0000 */ + {&upd7810_device::SUB_A_A, 2, 8, 8,L0|L1}, /* e1: 0110 0000 1110 0001 */ + {&upd7810_device::SUB_A_B, 2, 8, 8,L0|L1}, /* e2: 0110 0000 1110 0010 */ + {&upd7810_device::SUB_A_C, 2, 8, 8,L0|L1}, /* e3: 0110 0000 1110 0011 */ + {&upd7810_device::SUB_A_D, 2, 8, 8,L0|L1}, /* e4: 0110 0000 1110 0100 */ + {&upd7810_device::SUB_A_E, 2, 8, 8,L0|L1}, /* e5: 0110 0000 1110 0101 */ + {&upd7810_device::SUB_A_H, 2, 8, 8,L0|L1}, /* e6: 0110 0000 1110 0110 */ + {&upd7810_device::SUB_A_L, 2, 8, 8,L0|L1}, /* e7: 0110 0000 1110 0111 */ + {&upd7810_device::NEA_A_V, 2, 8, 8,L0|L1}, /* e8: 0110 0000 1110 1000 */ + {&upd7810_device::NEA_A_A, 2, 8, 8,L0|L1}, /* e9: 0110 0000 1110 1001 */ + {&upd7810_device::NEA_A_B, 2, 8, 8,L0|L1}, /* ea: 0110 0000 1110 1010 */ + {&upd7810_device::NEA_A_C, 2, 8, 8,L0|L1}, /* eb: 0110 0000 1110 1011 */ + {&upd7810_device::NEA_A_D, 2, 8, 8,L0|L1}, /* ec: 0110 0000 1110 1100 */ + {&upd7810_device::NEA_A_E, 2, 8, 8,L0|L1}, /* ed: 0110 0000 1110 1101 */ + {&upd7810_device::NEA_A_H, 2, 8, 8,L0|L1}, /* ee: 0110 0000 1110 1110 */ + {&upd7810_device::NEA_A_L, 2, 8, 8,L0|L1}, /* ef: 0110 0000 1110 1111 */ + + {&upd7810_device::SBB_A_V, 2, 8, 8,L0|L1}, /* f0: 0110 0000 1111 0000 */ + {&upd7810_device::SBB_A_A, 2, 8, 8,L0|L1}, /* f1: 0110 0000 1111 0001 */ + {&upd7810_device::SBB_A_B, 2, 8, 8,L0|L1}, /* f2: 0110 0000 1111 0010 */ + {&upd7810_device::SBB_A_C, 2, 8, 8,L0|L1}, /* f3: 0110 0000 1111 0011 */ + {&upd7810_device::SBB_A_D, 2, 8, 8,L0|L1}, /* f4: 0110 0000 1111 0100 */ + {&upd7810_device::SBB_A_E, 2, 8, 8,L0|L1}, /* f5: 0110 0000 1111 0101 */ + {&upd7810_device::SBB_A_H, 2, 8, 8,L0|L1}, /* f6: 0110 0000 1111 0110 */ + {&upd7810_device::SBB_A_L, 2, 8, 8,L0|L1}, /* f7: 0110 0000 1111 0111 */ + {&upd7810_device::EQA_A_V, 2, 8, 8,L0|L1}, /* f8: 0110 0000 1111 1000 */ + {&upd7810_device::EQA_A_A, 2, 8, 8,L0|L1}, /* f9: 0110 0000 1111 1001 */ + {&upd7810_device::EQA_A_B, 2, 8, 8,L0|L1}, /* fa: 0110 0000 1111 1010 */ + {&upd7810_device::EQA_A_C, 2, 8, 8,L0|L1}, /* fb: 0110 0000 1111 1011 */ + {&upd7810_device::EQA_A_D, 2, 8, 8,L0|L1}, /* fc: 0110 0000 1111 1100 */ + {&upd7810_device::EQA_A_E, 2, 8, 8,L0|L1}, /* fd: 0110 0000 1111 1101 */ + {&upd7810_device::EQA_A_H, 2, 8, 8,L0|L1}, /* fe: 0110 0000 1111 1110 */ + {&upd7810_device::EQA_A_L, 2, 8, 8,L0|L1} /* ff: 0110 0000 1111 1111 */ }; /* prefix 64 */ -static const struct opcode_s op64[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op64[256] = { - {MVI_PA_xx, 3,14,11,L0|L1}, /* 00: 0110 0100 0000 0000 xxxx xxxx */ - {MVI_PB_xx, 3,14,11,L0|L1}, /* 01: 0110 0100 0000 0001 xxxx xxxx */ - {MVI_PC_xx, 3,14,11,L0|L1}, /* 02: 0110 0100 0000 0010 xxxx xxxx */ - {MVI_PD_xx, 3,14,11,L0|L1}, /* 03: 0110 0100 0000 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 04: 0110 0100 0000 0100 xxxx xxxx */ - {MVI_PF_xx, 3,14,11,L0|L1}, /* 05: 0110 0100 0000 0101 xxxx xxxx */ - {MVI_MKH_xx, 3,14,11,L0|L1}, /* 06: 0110 0100 0000 0110 xxxx xxxx */ - {MVI_MKL_xx, 3,14,11,L0|L1}, /* 07: 0110 0100 0000 0111 xxxx xxxx */ - {ANI_PA_xx, 3,20,11,L0|L1}, /* 08: 0110 0100 0000 1000 xxxx xxxx */ - {ANI_PB_xx, 3,20,11,L0|L1}, /* 09: 0110 0100 0000 1001 xxxx xxxx */ - {ANI_PC_xx, 3,20,11,L0|L1}, /* 0a: 0110 0100 0000 1010 xxxx xxxx */ - {ANI_PD_xx, 3,20,11,L0|L1}, /* 0b: 0110 0100 0000 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 0c: 0110 0100 0000 1100 xxxx xxxx */ - {ANI_PF_xx, 3,20,11,L0|L1}, /* 0d: 0110 0100 0000 1101 xxxx xxxx */ - {ANI_MKH_xx, 3,20,11,L0|L1}, /* 0e: 0110 0100 0000 1110 xxxx xxxx */ - {ANI_MKL_xx, 3,20,11,L0|L1}, /* 0f: 0110 0100 0000 1111 xxxx xxxx */ - - {XRI_PA_xx, 3,20,11,L0|L1}, /* 10: 0110 0100 0001 0000 xxxx xxxx */ - {XRI_PB_xx, 3,20,11,L0|L1}, /* 11: 0110 0100 0001 0001 xxxx xxxx */ - {XRI_PC_xx, 3,20,11,L0|L1}, /* 12: 0110 0100 0001 0010 xxxx xxxx */ - {XRI_PD_xx, 3,20,11,L0|L1}, /* 13: 0110 0100 0001 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 14: 0110 0100 0001 0100 xxxx xxxx */ - {XRI_PF_xx, 3,20,11,L0|L1}, /* 15: 0110 0100 0001 0101 xxxx xxxx */ - {XRI_MKH_xx, 3,20,11,L0|L1}, /* 16: 0110 0100 0001 0110 xxxx xxxx */ - {XRI_MKL_xx, 3,20,11,L0|L1}, /* 17: 0110 0100 0001 0111 xxxx xxxx */ - {ORI_PA_xx, 3,20,11,L0|L1}, /* 18: 0110 0100 0001 1000 xxxx xxxx */ - {ORI_PB_xx, 3,20,11,L0|L1}, /* 19: 0110 0100 0001 1001 xxxx xxxx */ - {ORI_PC_xx, 3,20,11,L0|L1}, /* 1a: 0110 0100 0001 1010 xxxx xxxx */ - {ORI_PD_xx, 3,20,11,L0|L1}, /* 1b: 0110 0100 0001 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 1c: 0110 0100 0001 1100 xxxx xxxx */ - {ORI_PF_xx, 3,20,11,L0|L1}, /* 1d: 0110 0100 0001 1101 xxxx xxxx */ - {ORI_MKH_xx, 3,20,11,L0|L1}, /* 1e: 0110 0100 0001 1110 xxxx xxxx */ - {ORI_MKL_xx, 3,20,11,L0|L1}, /* 1f: 0110 0100 0001 1111 xxxx xxxx */ - - {ADINC_PA_xx, 3,20,11,L0|L1}, /* 20: 0110 0100 0010 0000 xxxx xxxx */ - {ADINC_PB_xx, 3,20,11,L0|L1}, /* 21: 0110 0100 0010 0001 xxxx xxxx */ - {ADINC_PC_xx, 3,20,11,L0|L1}, /* 22: 0110 0100 0010 0010 xxxx xxxx */ - {ADINC_PD_xx, 3,20,11,L0|L1}, /* 23: 0110 0100 0010 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 24: 0110 0100 0010 0100 xxxx xxxx */ - {ADINC_PF_xx, 3,20,11,L0|L1}, /* 25: 0110 0100 0010 0101 xxxx xxxx */ - {ADINC_MKH_xx, 3,20,11,L0|L1}, /* 26: 0110 0100 0010 0110 xxxx xxxx */ - {ADINC_MKL_xx, 3,20,11,L0|L1}, /* 27: 0110 0100 0010 0111 xxxx xxxx */ - {GTI_PA_xx, 3,20,11,L0|L1}, /* 28: 0110 0100 0010 1000 xxxx xxxx */ - {GTI_PB_xx, 3,20,11,L0|L1}, /* 29: 0110 0100 0010 1001 xxxx xxxx */ - {GTI_PC_xx, 3,20,11,L0|L1}, /* 2a: 0110 0100 0010 1010 xxxx xxxx */ - {GTI_PD_xx, 3,20,11,L0|L1}, /* 2b: 0110 0100 0010 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 2c: 0110 0100 0010 1100 xxxx xxxx */ - {GTI_PF_xx, 3,20,11,L0|L1}, /* 2d: 0110 0100 0010 1101 xxxx xxxx */ - {GTI_MKH_xx, 3,20,11,L0|L1}, /* 2e: 0110 0100 0010 1110 xxxx xxxx */ - {GTI_MKL_xx, 3,20,11,L0|L1}, /* 2f: 0110 0100 0010 1111 xxxx xxxx */ - - {SUINB_PA_xx, 3,20,11,L0|L1}, /* 30: 0110 0100 0011 0000 xxxx xxxx */ - {SUINB_PB_xx, 3,20,11,L0|L1}, /* 31: 0110 0100 0011 0001 xxxx xxxx */ - {SUINB_PC_xx, 3,20,11,L0|L1}, /* 32: 0110 0100 0011 0010 xxxx xxxx */ - {SUINB_PD_xx, 3,20,11,L0|L1}, /* 33: 0110 0100 0011 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 34: 0110 0100 0011 0100 xxxx xxxx */ - {SUINB_PF_xx, 3,20,11,L0|L1}, /* 35: 0110 0100 0011 0101 xxxx xxxx */ - {SUINB_MKH_xx, 3,20,11,L0|L1}, /* 36: 0110 0100 0011 0110 xxxx xxxx */ - {SUINB_MKL_xx, 3,20,11,L0|L1}, /* 37: 0110 0100 0011 0111 xxxx xxxx */ - {LTI_PA_xx, 3,20,11,L0|L1}, /* 38: 0110 0100 0011 1000 xxxx xxxx */ - {LTI_PB_xx, 3,20,11,L0|L1}, /* 39: 0110 0100 0011 1001 xxxx xxxx */ - {LTI_PC_xx, 3,20,11,L0|L1}, /* 3a: 0110 0100 0011 1010 xxxx xxxx */ - {LTI_PD_xx, 3,20,11,L0|L1}, /* 3b: 0110 0100 0011 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 3c: 0110 0100 0011 1100 xxxx xxxx */ - {LTI_PF_xx, 3,20,11,L0|L1}, /* 3d: 0110 0100 0011 1101 xxxx xxxx */ - {LTI_MKH_xx, 3,20,11,L0|L1}, /* 3e: 0110 0100 0011 1110 xxxx xxxx */ - {LTI_MKL_xx, 3,20,11,L0|L1}, /* 3f: 0110 0100 0011 1111 xxxx xxxx */ - - {ADI_PA_xx, 3,20,11,L0|L1}, /* 40: 0110 0100 0100 0000 xxxx xxxx */ - {ADI_PB_xx, 3,20,11,L0|L1}, /* 41: 0110 0100 0100 0001 xxxx xxxx */ - {ADI_PC_xx, 3,20,11,L0|L1}, /* 42: 0110 0100 0100 0010 xxxx xxxx */ - {ADI_PD_xx, 3,20,11,L0|L1}, /* 43: 0110 0100 0100 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 44: 0110 0100 0100 0100 xxxx xxxx */ - {ADI_PF_xx, 3,20,11,L0|L1}, /* 45: 0110 0100 0100 0101 xxxx xxxx */ - {ADI_MKH_xx, 3,20,11,L0|L1}, /* 46: 0110 0100 0100 0110 xxxx xxxx */ - {ADI_MKL_xx, 3,20,11,L0|L1}, /* 47: 0110 0100 0100 0111 xxxx xxxx */ - {ONI_PA_xx, 3,20,11,L0|L1}, /* 48: 0110 0100 0100 1000 xxxx xxxx */ - {ONI_PB_xx, 3,20,11,L0|L1}, /* 49: 0110 0100 0100 1001 xxxx xxxx */ - {ONI_PC_xx, 3,20,11,L0|L1}, /* 4a: 0110 0100 0100 1010 xxxx xxxx */ - {ONI_PD_xx, 3,20,11,L0|L1}, /* 4b: 0110 0100 0100 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 4c: 0110 0100 0100 1100 xxxx xxxx */ - {ONI_PF_xx, 3,20,11,L0|L1}, /* 4d: 0110 0100 0100 1101 xxxx xxxx */ - {ONI_MKH_xx, 3,20,11,L0|L1}, /* 4e: 0110 0100 0100 1110 xxxx xxxx */ - {ONI_MKL_xx, 3,20,11,L0|L1}, /* 4f: 0110 0100 0100 1111 xxxx xxxx */ - - {ACI_PA_xx, 3,20,11,L0|L1}, /* 50: 0110 0100 0101 0000 xxxx xxxx */ - {ACI_PB_xx, 3,20,11,L0|L1}, /* 51: 0110 0100 0101 0001 xxxx xxxx */ - {ACI_PC_xx, 3,20,11,L0|L1}, /* 52: 0110 0100 0101 0010 xxxx xxxx */ - {ACI_PD_xx, 3,20,11,L0|L1}, /* 53: 0110 0100 0101 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 54: 0110 0100 0101 0100 xxxx xxxx */ - {ACI_PF_xx, 3,20,11,L0|L1}, /* 55: 0110 0100 0101 0101 xxxx xxxx */ - {ACI_MKH_xx, 3,20,11,L0|L1}, /* 56: 0110 0100 0101 0110 xxxx xxxx */ - {ACI_MKL_xx, 3,20,11,L0|L1}, /* 57: 0110 0100 0101 0111 xxxx xxxx */ - {OFFI_PA_xx, 3,20,11,L0|L1}, /* 58: 0110 0100 0101 1000 xxxx xxxx */ - {OFFI_PB_xx, 3,20,11,L0|L1}, /* 59: 0110 0100 0101 1001 xxxx xxxx */ - {OFFI_PC_xx, 3,20,11,L0|L1}, /* 5a: 0110 0100 0101 1010 xxxx xxxx */ - {OFFI_PD_xx, 3,20,11,L0|L1}, /* 5b: 0110 0100 0101 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 5c: 0110 0100 0101 1100 xxxx xxxx */ - {OFFI_PF_xx, 3,20,11,L0|L1}, /* 5d: 0110 0100 0101 1101 xxxx xxxx */ - {OFFI_MKH_xx, 3,20,11,L0|L1}, /* 5e: 0110 0100 0101 1110 xxxx xxxx */ - {OFFI_MKL_xx, 3,20,11,L0|L1}, /* 5f: 0110 0100 0101 1111 xxxx xxxx */ - - {SUI_PA_xx, 3,20,11,L0|L1}, /* 60: 0110 0100 0110 0000 xxxx xxxx */ - {SUI_PB_xx, 3,20,11,L0|L1}, /* 61: 0110 0100 0110 0001 xxxx xxxx */ - {SUI_PC_xx, 3,20,11,L0|L1}, /* 62: 0110 0100 0110 0010 xxxx xxxx */ - {SUI_PD_xx, 3,20,11,L0|L1}, /* 63: 0110 0100 0110 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 64: 0110 0100 0110 0100 xxxx xxxx */ - {SUI_PF_xx, 3,20,11,L0|L1}, /* 65: 0110 0100 0110 0101 xxxx xxxx */ - {SUI_MKH_xx, 3,20,11,L0|L1}, /* 66: 0110 0100 0110 0110 xxxx xxxx */ - {SUI_MKL_xx, 3,20,11,L0|L1}, /* 67: 0110 0100 0110 0111 xxxx xxxx */ - {NEI_PA_xx, 3,20,11,L0|L1}, /* 68: 0110 0100 0110 1000 xxxx xxxx */ - {NEI_PB_xx, 3,20,11,L0|L1}, /* 69: 0110 0100 0110 1001 xxxx xxxx */ - {NEI_PC_xx, 3,20,11,L0|L1}, /* 6a: 0110 0100 0110 1010 xxxx xxxx */ - {NEI_PD_xx, 3,20,11,L0|L1}, /* 6b: 0110 0100 0110 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 6c: 0110 0100 0110 1100 xxxx xxxx */ - {NEI_PF_xx, 3,20,11,L0|L1}, /* 6d: 0110 0100 0110 1101 xxxx xxxx */ - {NEI_MKH_xx, 3,20,11,L0|L1}, /* 6e: 0110 0100 0110 1110 xxxx xxxx */ - {NEI_MKL_xx, 3,20,11,L0|L1}, /* 6f: 0110 0100 0110 1111 xxxx xxxx */ - - {SBI_PA_xx, 3,20,11,L0|L1}, /* 70: 0110 0100 0111 0000 xxxx xxxx */ - {SBI_PB_xx, 3,20,11,L0|L1}, /* 71: 0110 0100 0111 0001 xxxx xxxx */ - {SBI_PC_xx, 3,20,11,L0|L1}, /* 72: 0110 0100 0111 0010 xxxx xxxx */ - {SBI_PD_xx, 3,20,11,L0|L1}, /* 73: 0110 0100 0111 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 74: 0110 0100 0111 0100 xxxx xxxx */ - {SBI_PF_xx, 3,20,11,L0|L1}, /* 75: 0110 0100 0111 0101 xxxx xxxx */ - {SBI_MKH_xx, 3,20,11,L0|L1}, /* 76: 0110 0100 0111 0110 xxxx xxxx */ - {SBI_MKL_xx, 3,20,11,L0|L1}, /* 77: 0110 0100 0111 0111 xxxx xxxx */ - {EQI_PA_xx, 3,20,11,L0|L1}, /* 78: 0110 0100 0111 1000 xxxx xxxx */ - {EQI_PB_xx, 3,20,11,L0|L1}, /* 79: 0110 0100 0111 1001 xxxx xxxx */ - {EQI_PC_xx, 3,20,11,L0|L1}, /* 7a: 0110 0100 0111 1010 xxxx xxxx */ - {EQI_PD_xx, 3,20,11,L0|L1}, /* 7b: 0110 0100 0111 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 7c: 0110 0100 0111 1100 xxxx xxxx */ - {EQI_PF_xx, 3,20,11,L0|L1}, /* 7d: 0110 0100 0111 1101 xxxx xxxx */ - {EQI_MKH_xx, 3,20,11,L0|L1}, /* 7e: 0110 0100 0111 1110 xxxx xxxx */ - {EQI_MKL_xx, 3,20,11,L0|L1}, /* 7f: 0110 0100 0111 1111 xxxx xxxx */ - - {MVI_ANM_xx, 3,14,11,L0|L1}, /* 80: 0110 0100 1000 0000 xxxx xxxx */ - {MVI_SMH_xx, 3,14,11,L0|L1}, /* 81: 0110 0100 1000 0001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 82: 0110 0100 1000 0010 xxxx xxxx */ - {MVI_EOM_xx, 3,14,11,L0|L1}, /* 83: 0110 0100 1000 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 84: 0110 0100 1000 0100 xxxx xxxx */ - {MVI_TMM_xx, 3,14,11,L0|L1}, /* 85: 0110 0100 1000 0101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 86: 0110 0100 1000 0110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 87: 0110 0100 1000 0111 xxxx xxxx */ - {ANI_ANM_xx, 3,20,11,L0|L1}, /* 88: 0110 0100 1000 1000 xxxx xxxx */ - {ANI_SMH_xx, 3,20,11,L0|L1}, /* 89: 0110 0100 1000 1001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 8a: 0110 0100 1000 1010 xxxx xxxx */ - {ANI_EOM_xx, 3,20,11,L0|L1}, /* 8b: 0110 0100 1000 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 8c: 0110 0100 1000 1100 xxxx xxxx */ - {ANI_TMM_xx, 3,20,11,L0|L1}, /* 8d: 0110 0100 1000 1101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 8e: 0110 0100 1000 1110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 8f: 0110 0100 1000 1111 xxxx xxxx */ - - {XRI_ANM_xx, 3,20,11,L0|L1}, /* 90: 0110 0100 1001 0000 xxxx xxxx */ - {XRI_SMH_xx, 3,20,11,L0|L1}, /* 91: 0110 0100 1001 0001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 92: 0110 0100 1001 0010 xxxx xxxx */ - {XRI_EOM_xx, 3,20,11,L0|L1}, /* 93: 0110 0100 1001 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 94: 0110 0100 1001 0100 xxxx xxxx */ - {XRI_TMM_xx, 3,20,11,L0|L1}, /* 95: 0110 0100 1001 0101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 96: 0110 0100 1001 0110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 97: 0110 0100 1001 0111 xxxx xxxx */ - {ORI_ANM_xx, 3,20,11,L0|L1}, /* 98: 0110 0100 1001 1000 xxxx xxxx */ - {ORI_SMH_xx, 3,20,11,L0|L1}, /* 99: 0110 0100 1001 1001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 9a: 0110 0100 1001 1010 xxxx xxxx */ - {ORI_EOM_xx, 3,20,11,L0|L1}, /* 9b: 0110 0100 1001 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 9c: 0110 0100 1001 1100 xxxx xxxx */ - {ORI_TMM_xx, 3,20,11,L0|L1}, /* 9d: 0110 0100 1001 1101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 9e: 0110 0100 1001 1110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* 9f: 0110 0100 1001 1111 xxxx xxxx */ - - {ADINC_ANM_xx, 3,20,11,L0|L1}, /* a0: 0110 0100 1010 0000 xxxx xxxx */ - {ADINC_SMH_xx, 3,20,11,L0|L1}, /* a1: 0110 0100 1010 0001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* a2: 0110 0100 1010 0010 xxxx xxxx */ - {ADINC_EOM_xx, 3,20,11,L0|L1}, /* a3: 0110 0100 1010 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* a4: 0110 0100 1010 0100 xxxx xxxx */ - {ADINC_TMM_xx, 3,20,11,L0|L1}, /* a5: 0110 0100 1010 0101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* a6: 0110 0100 1010 0110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* a7: 0110 0100 1010 0111 xxxx xxxx */ - {GTI_ANM_xx, 3,20,11,L0|L1}, /* a8: 0110 0100 1010 1000 xxxx xxxx */ - {GTI_SMH_xx, 3,20,11,L0|L1}, /* a9: 0110 0100 1010 1001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* aa: 0110 0100 1010 1010 xxxx xxxx */ - {GTI_EOM_xx, 3,20,11,L0|L1}, /* ab: 0110 0100 1010 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ac: 0110 0100 1010 1100 xxxx xxxx */ - {GTI_TMM_xx, 3,20,11,L0|L1}, /* ad: 0110 0100 1010 1101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ae: 0110 0100 1010 1110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* af: 0110 0100 1010 1111 xxxx xxxx */ - - {SUINB_ANM_xx, 3,20,11,L0|L1}, /* b0: 0110 0100 1011 0000 xxxx xxxx */ - {SUINB_SMH_xx, 3,20,11,L0|L1}, /* b1: 0110 0100 1011 0001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* b2: 0110 0100 1011 0010 xxxx xxxx */ - {SUINB_EOM_xx, 3,20,11,L0|L1}, /* b3: 0110 0100 1011 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* b4: 0110 0100 1011 0100 xxxx xxxx */ - {SUINB_TMM_xx, 3,20,11,L0|L1}, /* b5: 0110 0100 1011 0101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* b6: 0110 0100 1011 0110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* b7: 0110 0100 1011 0111 xxxx xxxx */ - {LTI_ANM_xx, 3,20,11,L0|L1}, /* b8: 0110 0100 1011 1000 xxxx xxxx */ - {LTI_SMH_xx, 3,20,11,L0|L1}, /* b9: 0110 0100 1011 1001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ba: 0110 0100 1011 1010 xxxx xxxx */ - {LTI_EOM_xx, 3,20,11,L0|L1}, /* bb: 0110 0100 1011 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* bc: 0110 0100 1011 1100 xxxx xxxx */ - {LTI_TMM_xx, 3,20,11,L0|L1}, /* bd: 0110 0100 1011 1101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* be: 0110 0100 1011 1110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* bf: 0110 0100 1011 1111 xxxx xxxx */ - - {ADI_ANM_xx, 3,20,11,L0|L1}, /* c0: 0110 0100 1100 0000 xxxx xxxx */ - {ADI_SMH_xx, 3,20,11,L0|L1}, /* c1: 0110 0100 1100 0001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* c2: 0110 0100 1100 0010 xxxx xxxx */ - {ADI_EOM_xx, 3,20,11,L0|L1}, /* c3: 0110 0100 1100 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* c4: 0110 0100 1100 0100 xxxx xxxx */ - {ADI_TMM_xx, 3,20,11,L0|L1}, /* c5: 0110 0100 1100 0101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* c6: 0110 0100 1100 0110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* c7: 0110 0100 1100 0111 xxxx xxxx */ - {ONI_ANM_xx, 3,20,11,L0|L1}, /* c8: 0110 0100 1100 1000 xxxx xxxx */ - {ONI_SMH_xx, 3,20,11,L0|L1}, /* c9: 0110 0100 1100 1001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ca: 0110 0100 1100 1010 xxxx xxxx */ - {ONI_EOM_xx, 3,20,11,L0|L1}, /* cb: 0110 0100 1100 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* cc: 0110 0100 1100 1100 xxxx xxxx */ - {ONI_TMM_xx, 3,20,11,L0|L1}, /* cd: 0110 0100 1100 1101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ce: 0110 0100 1100 1110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* cf: 0110 0100 1100 1111 xxxx xxxx */ - - {ACI_ANM_xx, 3,20,11,L0|L1}, /* d0: 0110 0100 1101 0000 xxxx xxxx */ - {ACI_SMH_xx, 3,20,11,L0|L1}, /* d1: 0110 0100 1101 0001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* d2: 0110 0100 1101 0010 xxxx xxxx */ - {ACI_EOM_xx, 3,20,11,L0|L1}, /* d3: 0110 0100 1101 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* d4: 0110 0100 1101 0100 xxxx xxxx */ - {ACI_TMM_xx, 3,20,11,L0|L1}, /* d5: 0110 0100 1101 0101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* d6: 0110 0100 1101 0110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* d7: 0110 0100 1101 0111 xxxx xxxx */ - {OFFI_ANM_xx, 3,20,11,L0|L1}, /* d8: 0110 0100 1101 1000 xxxx xxxx */ - {OFFI_SMH_xx, 3,20,11,L0|L1}, /* d9: 0110 0100 1101 1001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* da: 0110 0100 1101 1010 xxxx xxxx */ - {OFFI_EOM_xx, 3,20,11,L0|L1}, /* db: 0110 0100 1101 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* dc: 0110 0100 1101 1100 xxxx xxxx */ - {OFFI_TMM_xx, 3,20,11,L0|L1}, /* dd: 0110 0100 1101 1101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* de: 0110 0100 1101 1110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* df: 0110 0100 1101 1111 xxxx xxxx */ - - {SUI_ANM_xx, 3,20,11,L0|L1}, /* e0: 0110 0100 1110 0000 xxxx xxxx */ - {SUI_SMH_xx, 3,20,11,L0|L1}, /* e1: 0110 0100 1110 0001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* e2: 0110 0100 1110 0010 xxxx xxxx */ - {SUI_EOM_xx, 3,20,11,L0|L1}, /* e3: 0110 0100 1110 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* e4: 0110 0100 1110 0100 xxxx xxxx */ - {SUI_TMM_xx, 3,20,11,L0|L1}, /* e5: 0110 0100 1110 0101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* e6: 0110 0100 1110 0110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* e7: 0110 0100 1110 0111 xxxx xxxx */ - {NEI_ANM_xx, 3,20,11,L0|L1}, /* e8: 0110 0100 1110 1000 xxxx xxxx */ - {NEI_SMH_xx, 3,20,11,L0|L1}, /* e9: 0110 0100 1110 1001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ea: 0110 0100 1110 1010 xxxx xxxx */ - {NEI_EOM_xx, 3,20,11,L0|L1}, /* eb: 0110 0100 1110 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ec: 0110 0100 1110 1100 xxxx xxxx */ - {NEI_TMM_xx, 3,20,11,L0|L1}, /* ed: 0110 0100 1110 1101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ee: 0110 0100 1110 1110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* ef: 0110 0100 1110 1111 xxxx xxxx */ - - {SBI_ANM_xx, 3,20,11,L0|L1}, /* f0: 0110 0100 1111 0000 xxxx xxxx */ - {SBI_SMH_xx, 3,20,11,L0|L1}, /* f1: 0110 0100 1111 0001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* f2: 0110 0100 1111 0010 xxxx xxxx */ - {SBI_EOM_xx, 3,20,11,L0|L1}, /* f3: 0110 0100 1111 0011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* f4: 0110 0100 1111 0100 xxxx xxxx */ - {SBI_TMM_xx, 3,20,11,L0|L1}, /* f5: 0110 0100 1111 0101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* f6: 0110 0100 1111 0110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* f7: 0110 0100 1111 0111 xxxx xxxx */ - {EQI_ANM_xx, 3,20,11,L0|L1}, /* f8: 0110 0100 1111 1000 xxxx xxxx */ - {EQI_SMH_xx, 3,20,11,L0|L1}, /* f9: 0110 0100 1111 1001 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* fa: 0110 0100 1111 1010 xxxx xxxx */ - {EQI_EOM_xx, 3,20,11,L0|L1}, /* fb: 0110 0100 1111 1011 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* fc: 0110 0100 1111 1100 xxxx xxxx */ - {EQI_TMM_xx, 3,20,11,L0|L1}, /* fd: 0110 0100 1111 1101 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1}, /* fe: 0110 0100 1111 1110 xxxx xxxx */ - {illegal2, 3,11,11,L0|L1} /* ff: 0110 0100 1111 1111 xxxx xxxx */ + {&upd7810_device::MVI_PA_xx, 3,14,11,L0|L1}, /* 00: 0110 0100 0000 0000 xxxx xxxx */ + {&upd7810_device::MVI_PB_xx, 3,14,11,L0|L1}, /* 01: 0110 0100 0000 0001 xxxx xxxx */ + {&upd7810_device::MVI_PC_xx, 3,14,11,L0|L1}, /* 02: 0110 0100 0000 0010 xxxx xxxx */ + {&upd7810_device::MVI_PD_xx, 3,14,11,L0|L1}, /* 03: 0110 0100 0000 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 04: 0110 0100 0000 0100 xxxx xxxx */ + {&upd7810_device::MVI_PF_xx, 3,14,11,L0|L1}, /* 05: 0110 0100 0000 0101 xxxx xxxx */ + {&upd7810_device::MVI_MKH_xx, 3,14,11,L0|L1}, /* 06: 0110 0100 0000 0110 xxxx xxxx */ + {&upd7810_device::MVI_MKL_xx, 3,14,11,L0|L1}, /* 07: 0110 0100 0000 0111 xxxx xxxx */ + {&upd7810_device::ANI_PA_xx, 3,20,11,L0|L1}, /* 08: 0110 0100 0000 1000 xxxx xxxx */ + {&upd7810_device::ANI_PB_xx, 3,20,11,L0|L1}, /* 09: 0110 0100 0000 1001 xxxx xxxx */ + {&upd7810_device::ANI_PC_xx, 3,20,11,L0|L1}, /* 0a: 0110 0100 0000 1010 xxxx xxxx */ + {&upd7810_device::ANI_PD_xx, 3,20,11,L0|L1}, /* 0b: 0110 0100 0000 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 0c: 0110 0100 0000 1100 xxxx xxxx */ + {&upd7810_device::ANI_PF_xx, 3,20,11,L0|L1}, /* 0d: 0110 0100 0000 1101 xxxx xxxx */ + {&upd7810_device::ANI_MKH_xx, 3,20,11,L0|L1}, /* 0e: 0110 0100 0000 1110 xxxx xxxx */ + {&upd7810_device::ANI_MKL_xx, 3,20,11,L0|L1}, /* 0f: 0110 0100 0000 1111 xxxx xxxx */ + + {&upd7810_device::XRI_PA_xx, 3,20,11,L0|L1}, /* 10: 0110 0100 0001 0000 xxxx xxxx */ + {&upd7810_device::XRI_PB_xx, 3,20,11,L0|L1}, /* 11: 0110 0100 0001 0001 xxxx xxxx */ + {&upd7810_device::XRI_PC_xx, 3,20,11,L0|L1}, /* 12: 0110 0100 0001 0010 xxxx xxxx */ + {&upd7810_device::XRI_PD_xx, 3,20,11,L0|L1}, /* 13: 0110 0100 0001 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 14: 0110 0100 0001 0100 xxxx xxxx */ + {&upd7810_device::XRI_PF_xx, 3,20,11,L0|L1}, /* 15: 0110 0100 0001 0101 xxxx xxxx */ + {&upd7810_device::XRI_MKH_xx, 3,20,11,L0|L1}, /* 16: 0110 0100 0001 0110 xxxx xxxx */ + {&upd7810_device::XRI_MKL_xx, 3,20,11,L0|L1}, /* 17: 0110 0100 0001 0111 xxxx xxxx */ + {&upd7810_device::ORI_PA_xx, 3,20,11,L0|L1}, /* 18: 0110 0100 0001 1000 xxxx xxxx */ + {&upd7810_device::ORI_PB_xx, 3,20,11,L0|L1}, /* 19: 0110 0100 0001 1001 xxxx xxxx */ + {&upd7810_device::ORI_PC_xx, 3,20,11,L0|L1}, /* 1a: 0110 0100 0001 1010 xxxx xxxx */ + {&upd7810_device::ORI_PD_xx, 3,20,11,L0|L1}, /* 1b: 0110 0100 0001 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 1c: 0110 0100 0001 1100 xxxx xxxx */ + {&upd7810_device::ORI_PF_xx, 3,20,11,L0|L1}, /* 1d: 0110 0100 0001 1101 xxxx xxxx */ + {&upd7810_device::ORI_MKH_xx, 3,20,11,L0|L1}, /* 1e: 0110 0100 0001 1110 xxxx xxxx */ + {&upd7810_device::ORI_MKL_xx, 3,20,11,L0|L1}, /* 1f: 0110 0100 0001 1111 xxxx xxxx */ + + {&upd7810_device::ADINC_PA_xx, 3,20,11,L0|L1}, /* 20: 0110 0100 0010 0000 xxxx xxxx */ + {&upd7810_device::ADINC_PB_xx, 3,20,11,L0|L1}, /* 21: 0110 0100 0010 0001 xxxx xxxx */ + {&upd7810_device::ADINC_PC_xx, 3,20,11,L0|L1}, /* 22: 0110 0100 0010 0010 xxxx xxxx */ + {&upd7810_device::ADINC_PD_xx, 3,20,11,L0|L1}, /* 23: 0110 0100 0010 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 24: 0110 0100 0010 0100 xxxx xxxx */ + {&upd7810_device::ADINC_PF_xx, 3,20,11,L0|L1}, /* 25: 0110 0100 0010 0101 xxxx xxxx */ + {&upd7810_device::ADINC_MKH_xx, 3,20,11,L0|L1}, /* 26: 0110 0100 0010 0110 xxxx xxxx */ + {&upd7810_device::ADINC_MKL_xx, 3,20,11,L0|L1}, /* 27: 0110 0100 0010 0111 xxxx xxxx */ + {&upd7810_device::GTI_PA_xx, 3,20,11,L0|L1}, /* 28: 0110 0100 0010 1000 xxxx xxxx */ + {&upd7810_device::GTI_PB_xx, 3,20,11,L0|L1}, /* 29: 0110 0100 0010 1001 xxxx xxxx */ + {&upd7810_device::GTI_PC_xx, 3,20,11,L0|L1}, /* 2a: 0110 0100 0010 1010 xxxx xxxx */ + {&upd7810_device::GTI_PD_xx, 3,20,11,L0|L1}, /* 2b: 0110 0100 0010 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 2c: 0110 0100 0010 1100 xxxx xxxx */ + {&upd7810_device::GTI_PF_xx, 3,20,11,L0|L1}, /* 2d: 0110 0100 0010 1101 xxxx xxxx */ + {&upd7810_device::GTI_MKH_xx, 3,20,11,L0|L1}, /* 2e: 0110 0100 0010 1110 xxxx xxxx */ + {&upd7810_device::GTI_MKL_xx, 3,20,11,L0|L1}, /* 2f: 0110 0100 0010 1111 xxxx xxxx */ + + {&upd7810_device::SUINB_PA_xx, 3,20,11,L0|L1}, /* 30: 0110 0100 0011 0000 xxxx xxxx */ + {&upd7810_device::SUINB_PB_xx, 3,20,11,L0|L1}, /* 31: 0110 0100 0011 0001 xxxx xxxx */ + {&upd7810_device::SUINB_PC_xx, 3,20,11,L0|L1}, /* 32: 0110 0100 0011 0010 xxxx xxxx */ + {&upd7810_device::SUINB_PD_xx, 3,20,11,L0|L1}, /* 33: 0110 0100 0011 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 34: 0110 0100 0011 0100 xxxx xxxx */ + {&upd7810_device::SUINB_PF_xx, 3,20,11,L0|L1}, /* 35: 0110 0100 0011 0101 xxxx xxxx */ + {&upd7810_device::SUINB_MKH_xx, 3,20,11,L0|L1}, /* 36: 0110 0100 0011 0110 xxxx xxxx */ + {&upd7810_device::SUINB_MKL_xx, 3,20,11,L0|L1}, /* 37: 0110 0100 0011 0111 xxxx xxxx */ + {&upd7810_device::LTI_PA_xx, 3,20,11,L0|L1}, /* 38: 0110 0100 0011 1000 xxxx xxxx */ + {&upd7810_device::LTI_PB_xx, 3,20,11,L0|L1}, /* 39: 0110 0100 0011 1001 xxxx xxxx */ + {&upd7810_device::LTI_PC_xx, 3,20,11,L0|L1}, /* 3a: 0110 0100 0011 1010 xxxx xxxx */ + {&upd7810_device::LTI_PD_xx, 3,20,11,L0|L1}, /* 3b: 0110 0100 0011 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 3c: 0110 0100 0011 1100 xxxx xxxx */ + {&upd7810_device::LTI_PF_xx, 3,20,11,L0|L1}, /* 3d: 0110 0100 0011 1101 xxxx xxxx */ + {&upd7810_device::LTI_MKH_xx, 3,20,11,L0|L1}, /* 3e: 0110 0100 0011 1110 xxxx xxxx */ + {&upd7810_device::LTI_MKL_xx, 3,20,11,L0|L1}, /* 3f: 0110 0100 0011 1111 xxxx xxxx */ + + {&upd7810_device::ADI_PA_xx, 3,20,11,L0|L1}, /* 40: 0110 0100 0100 0000 xxxx xxxx */ + {&upd7810_device::ADI_PB_xx, 3,20,11,L0|L1}, /* 41: 0110 0100 0100 0001 xxxx xxxx */ + {&upd7810_device::ADI_PC_xx, 3,20,11,L0|L1}, /* 42: 0110 0100 0100 0010 xxxx xxxx */ + {&upd7810_device::ADI_PD_xx, 3,20,11,L0|L1}, /* 43: 0110 0100 0100 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 44: 0110 0100 0100 0100 xxxx xxxx */ + {&upd7810_device::ADI_PF_xx, 3,20,11,L0|L1}, /* 45: 0110 0100 0100 0101 xxxx xxxx */ + {&upd7810_device::ADI_MKH_xx, 3,20,11,L0|L1}, /* 46: 0110 0100 0100 0110 xxxx xxxx */ + {&upd7810_device::ADI_MKL_xx, 3,20,11,L0|L1}, /* 47: 0110 0100 0100 0111 xxxx xxxx */ + {&upd7810_device::ONI_PA_xx, 3,20,11,L0|L1}, /* 48: 0110 0100 0100 1000 xxxx xxxx */ + {&upd7810_device::ONI_PB_xx, 3,20,11,L0|L1}, /* 49: 0110 0100 0100 1001 xxxx xxxx */ + {&upd7810_device::ONI_PC_xx, 3,20,11,L0|L1}, /* 4a: 0110 0100 0100 1010 xxxx xxxx */ + {&upd7810_device::ONI_PD_xx, 3,20,11,L0|L1}, /* 4b: 0110 0100 0100 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 4c: 0110 0100 0100 1100 xxxx xxxx */ + {&upd7810_device::ONI_PF_xx, 3,20,11,L0|L1}, /* 4d: 0110 0100 0100 1101 xxxx xxxx */ + {&upd7810_device::ONI_MKH_xx, 3,20,11,L0|L1}, /* 4e: 0110 0100 0100 1110 xxxx xxxx */ + {&upd7810_device::ONI_MKL_xx, 3,20,11,L0|L1}, /* 4f: 0110 0100 0100 1111 xxxx xxxx */ + + {&upd7810_device::ACI_PA_xx, 3,20,11,L0|L1}, /* 50: 0110 0100 0101 0000 xxxx xxxx */ + {&upd7810_device::ACI_PB_xx, 3,20,11,L0|L1}, /* 51: 0110 0100 0101 0001 xxxx xxxx */ + {&upd7810_device::ACI_PC_xx, 3,20,11,L0|L1}, /* 52: 0110 0100 0101 0010 xxxx xxxx */ + {&upd7810_device::ACI_PD_xx, 3,20,11,L0|L1}, /* 53: 0110 0100 0101 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 54: 0110 0100 0101 0100 xxxx xxxx */ + {&upd7810_device::ACI_PF_xx, 3,20,11,L0|L1}, /* 55: 0110 0100 0101 0101 xxxx xxxx */ + {&upd7810_device::ACI_MKH_xx, 3,20,11,L0|L1}, /* 56: 0110 0100 0101 0110 xxxx xxxx */ + {&upd7810_device::ACI_MKL_xx, 3,20,11,L0|L1}, /* 57: 0110 0100 0101 0111 xxxx xxxx */ + {&upd7810_device::OFFI_PA_xx, 3,20,11,L0|L1}, /* 58: 0110 0100 0101 1000 xxxx xxxx */ + {&upd7810_device::OFFI_PB_xx, 3,20,11,L0|L1}, /* 59: 0110 0100 0101 1001 xxxx xxxx */ + {&upd7810_device::OFFI_PC_xx, 3,20,11,L0|L1}, /* 5a: 0110 0100 0101 1010 xxxx xxxx */ + {&upd7810_device::OFFI_PD_xx, 3,20,11,L0|L1}, /* 5b: 0110 0100 0101 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 5c: 0110 0100 0101 1100 xxxx xxxx */ + {&upd7810_device::OFFI_PF_xx, 3,20,11,L0|L1}, /* 5d: 0110 0100 0101 1101 xxxx xxxx */ + {&upd7810_device::OFFI_MKH_xx, 3,20,11,L0|L1}, /* 5e: 0110 0100 0101 1110 xxxx xxxx */ + {&upd7810_device::OFFI_MKL_xx, 3,20,11,L0|L1}, /* 5f: 0110 0100 0101 1111 xxxx xxxx */ + + {&upd7810_device::SUI_PA_xx, 3,20,11,L0|L1}, /* 60: 0110 0100 0110 0000 xxxx xxxx */ + {&upd7810_device::SUI_PB_xx, 3,20,11,L0|L1}, /* 61: 0110 0100 0110 0001 xxxx xxxx */ + {&upd7810_device::SUI_PC_xx, 3,20,11,L0|L1}, /* 62: 0110 0100 0110 0010 xxxx xxxx */ + {&upd7810_device::SUI_PD_xx, 3,20,11,L0|L1}, /* 63: 0110 0100 0110 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 64: 0110 0100 0110 0100 xxxx xxxx */ + {&upd7810_device::SUI_PF_xx, 3,20,11,L0|L1}, /* 65: 0110 0100 0110 0101 xxxx xxxx */ + {&upd7810_device::SUI_MKH_xx, 3,20,11,L0|L1}, /* 66: 0110 0100 0110 0110 xxxx xxxx */ + {&upd7810_device::SUI_MKL_xx, 3,20,11,L0|L1}, /* 67: 0110 0100 0110 0111 xxxx xxxx */ + {&upd7810_device::NEI_PA_xx, 3,20,11,L0|L1}, /* 68: 0110 0100 0110 1000 xxxx xxxx */ + {&upd7810_device::NEI_PB_xx, 3,20,11,L0|L1}, /* 69: 0110 0100 0110 1001 xxxx xxxx */ + {&upd7810_device::NEI_PC_xx, 3,20,11,L0|L1}, /* 6a: 0110 0100 0110 1010 xxxx xxxx */ + {&upd7810_device::NEI_PD_xx, 3,20,11,L0|L1}, /* 6b: 0110 0100 0110 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 6c: 0110 0100 0110 1100 xxxx xxxx */ + {&upd7810_device::NEI_PF_xx, 3,20,11,L0|L1}, /* 6d: 0110 0100 0110 1101 xxxx xxxx */ + {&upd7810_device::NEI_MKH_xx, 3,20,11,L0|L1}, /* 6e: 0110 0100 0110 1110 xxxx xxxx */ + {&upd7810_device::NEI_MKL_xx, 3,20,11,L0|L1}, /* 6f: 0110 0100 0110 1111 xxxx xxxx */ + + {&upd7810_device::SBI_PA_xx, 3,20,11,L0|L1}, /* 70: 0110 0100 0111 0000 xxxx xxxx */ + {&upd7810_device::SBI_PB_xx, 3,20,11,L0|L1}, /* 71: 0110 0100 0111 0001 xxxx xxxx */ + {&upd7810_device::SBI_PC_xx, 3,20,11,L0|L1}, /* 72: 0110 0100 0111 0010 xxxx xxxx */ + {&upd7810_device::SBI_PD_xx, 3,20,11,L0|L1}, /* 73: 0110 0100 0111 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 74: 0110 0100 0111 0100 xxxx xxxx */ + {&upd7810_device::SBI_PF_xx, 3,20,11,L0|L1}, /* 75: 0110 0100 0111 0101 xxxx xxxx */ + {&upd7810_device::SBI_MKH_xx, 3,20,11,L0|L1}, /* 76: 0110 0100 0111 0110 xxxx xxxx */ + {&upd7810_device::SBI_MKL_xx, 3,20,11,L0|L1}, /* 77: 0110 0100 0111 0111 xxxx xxxx */ + {&upd7810_device::EQI_PA_xx, 3,20,11,L0|L1}, /* 78: 0110 0100 0111 1000 xxxx xxxx */ + {&upd7810_device::EQI_PB_xx, 3,20,11,L0|L1}, /* 79: 0110 0100 0111 1001 xxxx xxxx */ + {&upd7810_device::EQI_PC_xx, 3,20,11,L0|L1}, /* 7a: 0110 0100 0111 1010 xxxx xxxx */ + {&upd7810_device::EQI_PD_xx, 3,20,11,L0|L1}, /* 7b: 0110 0100 0111 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 7c: 0110 0100 0111 1100 xxxx xxxx */ + {&upd7810_device::EQI_PF_xx, 3,20,11,L0|L1}, /* 7d: 0110 0100 0111 1101 xxxx xxxx */ + {&upd7810_device::EQI_MKH_xx, 3,20,11,L0|L1}, /* 7e: 0110 0100 0111 1110 xxxx xxxx */ + {&upd7810_device::EQI_MKL_xx, 3,20,11,L0|L1}, /* 7f: 0110 0100 0111 1111 xxxx xxxx */ + + {&upd7810_device::MVI_ANM_xx, 3,14,11,L0|L1}, /* 80: 0110 0100 1000 0000 xxxx xxxx */ + {&upd7810_device::MVI_SMH_xx, 3,14,11,L0|L1}, /* 81: 0110 0100 1000 0001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 82: 0110 0100 1000 0010 xxxx xxxx */ + {&upd7810_device::MVI_EOM_xx, 3,14,11,L0|L1}, /* 83: 0110 0100 1000 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 84: 0110 0100 1000 0100 xxxx xxxx */ + {&upd7810_device::MVI_TMM_xx, 3,14,11,L0|L1}, /* 85: 0110 0100 1000 0101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 86: 0110 0100 1000 0110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 87: 0110 0100 1000 0111 xxxx xxxx */ + {&upd7810_device::ANI_ANM_xx, 3,20,11,L0|L1}, /* 88: 0110 0100 1000 1000 xxxx xxxx */ + {&upd7810_device::ANI_SMH_xx, 3,20,11,L0|L1}, /* 89: 0110 0100 1000 1001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 8a: 0110 0100 1000 1010 xxxx xxxx */ + {&upd7810_device::ANI_EOM_xx, 3,20,11,L0|L1}, /* 8b: 0110 0100 1000 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 8c: 0110 0100 1000 1100 xxxx xxxx */ + {&upd7810_device::ANI_TMM_xx, 3,20,11,L0|L1}, /* 8d: 0110 0100 1000 1101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 8e: 0110 0100 1000 1110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 8f: 0110 0100 1000 1111 xxxx xxxx */ + + {&upd7810_device::XRI_ANM_xx, 3,20,11,L0|L1}, /* 90: 0110 0100 1001 0000 xxxx xxxx */ + {&upd7810_device::XRI_SMH_xx, 3,20,11,L0|L1}, /* 91: 0110 0100 1001 0001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 92: 0110 0100 1001 0010 xxxx xxxx */ + {&upd7810_device::XRI_EOM_xx, 3,20,11,L0|L1}, /* 93: 0110 0100 1001 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 94: 0110 0100 1001 0100 xxxx xxxx */ + {&upd7810_device::XRI_TMM_xx, 3,20,11,L0|L1}, /* 95: 0110 0100 1001 0101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 96: 0110 0100 1001 0110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 97: 0110 0100 1001 0111 xxxx xxxx */ + {&upd7810_device::ORI_ANM_xx, 3,20,11,L0|L1}, /* 98: 0110 0100 1001 1000 xxxx xxxx */ + {&upd7810_device::ORI_SMH_xx, 3,20,11,L0|L1}, /* 99: 0110 0100 1001 1001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 9a: 0110 0100 1001 1010 xxxx xxxx */ + {&upd7810_device::ORI_EOM_xx, 3,20,11,L0|L1}, /* 9b: 0110 0100 1001 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 9c: 0110 0100 1001 1100 xxxx xxxx */ + {&upd7810_device::ORI_TMM_xx, 3,20,11,L0|L1}, /* 9d: 0110 0100 1001 1101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 9e: 0110 0100 1001 1110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* 9f: 0110 0100 1001 1111 xxxx xxxx */ + + {&upd7810_device::ADINC_ANM_xx, 3,20,11,L0|L1}, /* a0: 0110 0100 1010 0000 xxxx xxxx */ + {&upd7810_device::ADINC_SMH_xx, 3,20,11,L0|L1}, /* a1: 0110 0100 1010 0001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* a2: 0110 0100 1010 0010 xxxx xxxx */ + {&upd7810_device::ADINC_EOM_xx, 3,20,11,L0|L1}, /* a3: 0110 0100 1010 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* a4: 0110 0100 1010 0100 xxxx xxxx */ + {&upd7810_device::ADINC_TMM_xx, 3,20,11,L0|L1}, /* a5: 0110 0100 1010 0101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* a6: 0110 0100 1010 0110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* a7: 0110 0100 1010 0111 xxxx xxxx */ + {&upd7810_device::GTI_ANM_xx, 3,20,11,L0|L1}, /* a8: 0110 0100 1010 1000 xxxx xxxx */ + {&upd7810_device::GTI_SMH_xx, 3,20,11,L0|L1}, /* a9: 0110 0100 1010 1001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* aa: 0110 0100 1010 1010 xxxx xxxx */ + {&upd7810_device::GTI_EOM_xx, 3,20,11,L0|L1}, /* ab: 0110 0100 1010 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ac: 0110 0100 1010 1100 xxxx xxxx */ + {&upd7810_device::GTI_TMM_xx, 3,20,11,L0|L1}, /* ad: 0110 0100 1010 1101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ae: 0110 0100 1010 1110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* af: 0110 0100 1010 1111 xxxx xxxx */ + + {&upd7810_device::SUINB_ANM_xx, 3,20,11,L0|L1}, /* b0: 0110 0100 1011 0000 xxxx xxxx */ + {&upd7810_device::SUINB_SMH_xx, 3,20,11,L0|L1}, /* b1: 0110 0100 1011 0001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* b2: 0110 0100 1011 0010 xxxx xxxx */ + {&upd7810_device::SUINB_EOM_xx, 3,20,11,L0|L1}, /* b3: 0110 0100 1011 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* b4: 0110 0100 1011 0100 xxxx xxxx */ + {&upd7810_device::SUINB_TMM_xx, 3,20,11,L0|L1}, /* b5: 0110 0100 1011 0101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* b6: 0110 0100 1011 0110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* b7: 0110 0100 1011 0111 xxxx xxxx */ + {&upd7810_device::LTI_ANM_xx, 3,20,11,L0|L1}, /* b8: 0110 0100 1011 1000 xxxx xxxx */ + {&upd7810_device::LTI_SMH_xx, 3,20,11,L0|L1}, /* b9: 0110 0100 1011 1001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ba: 0110 0100 1011 1010 xxxx xxxx */ + {&upd7810_device::LTI_EOM_xx, 3,20,11,L0|L1}, /* bb: 0110 0100 1011 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* bc: 0110 0100 1011 1100 xxxx xxxx */ + {&upd7810_device::LTI_TMM_xx, 3,20,11,L0|L1}, /* bd: 0110 0100 1011 1101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* be: 0110 0100 1011 1110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* bf: 0110 0100 1011 1111 xxxx xxxx */ + + {&upd7810_device::ADI_ANM_xx, 3,20,11,L0|L1}, /* c0: 0110 0100 1100 0000 xxxx xxxx */ + {&upd7810_device::ADI_SMH_xx, 3,20,11,L0|L1}, /* c1: 0110 0100 1100 0001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* c2: 0110 0100 1100 0010 xxxx xxxx */ + {&upd7810_device::ADI_EOM_xx, 3,20,11,L0|L1}, /* c3: 0110 0100 1100 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* c4: 0110 0100 1100 0100 xxxx xxxx */ + {&upd7810_device::ADI_TMM_xx, 3,20,11,L0|L1}, /* c5: 0110 0100 1100 0101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* c6: 0110 0100 1100 0110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* c7: 0110 0100 1100 0111 xxxx xxxx */ + {&upd7810_device::ONI_ANM_xx, 3,20,11,L0|L1}, /* c8: 0110 0100 1100 1000 xxxx xxxx */ + {&upd7810_device::ONI_SMH_xx, 3,20,11,L0|L1}, /* c9: 0110 0100 1100 1001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ca: 0110 0100 1100 1010 xxxx xxxx */ + {&upd7810_device::ONI_EOM_xx, 3,20,11,L0|L1}, /* cb: 0110 0100 1100 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* cc: 0110 0100 1100 1100 xxxx xxxx */ + {&upd7810_device::ONI_TMM_xx, 3,20,11,L0|L1}, /* cd: 0110 0100 1100 1101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ce: 0110 0100 1100 1110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* cf: 0110 0100 1100 1111 xxxx xxxx */ + + {&upd7810_device::ACI_ANM_xx, 3,20,11,L0|L1}, /* d0: 0110 0100 1101 0000 xxxx xxxx */ + {&upd7810_device::ACI_SMH_xx, 3,20,11,L0|L1}, /* d1: 0110 0100 1101 0001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* d2: 0110 0100 1101 0010 xxxx xxxx */ + {&upd7810_device::ACI_EOM_xx, 3,20,11,L0|L1}, /* d3: 0110 0100 1101 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* d4: 0110 0100 1101 0100 xxxx xxxx */ + {&upd7810_device::ACI_TMM_xx, 3,20,11,L0|L1}, /* d5: 0110 0100 1101 0101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* d6: 0110 0100 1101 0110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* d7: 0110 0100 1101 0111 xxxx xxxx */ + {&upd7810_device::OFFI_ANM_xx, 3,20,11,L0|L1}, /* d8: 0110 0100 1101 1000 xxxx xxxx */ + {&upd7810_device::OFFI_SMH_xx, 3,20,11,L0|L1}, /* d9: 0110 0100 1101 1001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* da: 0110 0100 1101 1010 xxxx xxxx */ + {&upd7810_device::OFFI_EOM_xx, 3,20,11,L0|L1}, /* db: 0110 0100 1101 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* dc: 0110 0100 1101 1100 xxxx xxxx */ + {&upd7810_device::OFFI_TMM_xx, 3,20,11,L0|L1}, /* dd: 0110 0100 1101 1101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* de: 0110 0100 1101 1110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* df: 0110 0100 1101 1111 xxxx xxxx */ + + {&upd7810_device::SUI_ANM_xx, 3,20,11,L0|L1}, /* e0: 0110 0100 1110 0000 xxxx xxxx */ + {&upd7810_device::SUI_SMH_xx, 3,20,11,L0|L1}, /* e1: 0110 0100 1110 0001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* e2: 0110 0100 1110 0010 xxxx xxxx */ + {&upd7810_device::SUI_EOM_xx, 3,20,11,L0|L1}, /* e3: 0110 0100 1110 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* e4: 0110 0100 1110 0100 xxxx xxxx */ + {&upd7810_device::SUI_TMM_xx, 3,20,11,L0|L1}, /* e5: 0110 0100 1110 0101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* e6: 0110 0100 1110 0110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* e7: 0110 0100 1110 0111 xxxx xxxx */ + {&upd7810_device::NEI_ANM_xx, 3,20,11,L0|L1}, /* e8: 0110 0100 1110 1000 xxxx xxxx */ + {&upd7810_device::NEI_SMH_xx, 3,20,11,L0|L1}, /* e9: 0110 0100 1110 1001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ea: 0110 0100 1110 1010 xxxx xxxx */ + {&upd7810_device::NEI_EOM_xx, 3,20,11,L0|L1}, /* eb: 0110 0100 1110 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ec: 0110 0100 1110 1100 xxxx xxxx */ + {&upd7810_device::NEI_TMM_xx, 3,20,11,L0|L1}, /* ed: 0110 0100 1110 1101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ee: 0110 0100 1110 1110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* ef: 0110 0100 1110 1111 xxxx xxxx */ + + {&upd7810_device::SBI_ANM_xx, 3,20,11,L0|L1}, /* f0: 0110 0100 1111 0000 xxxx xxxx */ + {&upd7810_device::SBI_SMH_xx, 3,20,11,L0|L1}, /* f1: 0110 0100 1111 0001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* f2: 0110 0100 1111 0010 xxxx xxxx */ + {&upd7810_device::SBI_EOM_xx, 3,20,11,L0|L1}, /* f3: 0110 0100 1111 0011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* f4: 0110 0100 1111 0100 xxxx xxxx */ + {&upd7810_device::SBI_TMM_xx, 3,20,11,L0|L1}, /* f5: 0110 0100 1111 0101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* f6: 0110 0100 1111 0110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* f7: 0110 0100 1111 0111 xxxx xxxx */ + {&upd7810_device::EQI_ANM_xx, 3,20,11,L0|L1}, /* f8: 0110 0100 1111 1000 xxxx xxxx */ + {&upd7810_device::EQI_SMH_xx, 3,20,11,L0|L1}, /* f9: 0110 0100 1111 1001 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* fa: 0110 0100 1111 1010 xxxx xxxx */ + {&upd7810_device::EQI_EOM_xx, 3,20,11,L0|L1}, /* fb: 0110 0100 1111 1011 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* fc: 0110 0100 1111 1100 xxxx xxxx */ + {&upd7810_device::EQI_TMM_xx, 3,20,11,L0|L1}, /* fd: 0110 0100 1111 1101 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1}, /* fe: 0110 0100 1111 1110 xxxx xxxx */ + {&upd7810_device::illegal2, 3,11,11,L0|L1} /* ff: 0110 0100 1111 1111 xxxx xxxx */ }; /* prefix 70 */ -static const struct opcode_s op70[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op70[256] = { - {illegal2, 2, 8, 8,L0|L1}, /* 00: 0111 0000 0000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 01: 0111 0000 0000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 02: 0111 0000 0000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 03: 0111 0000 0000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 04: 0111 0000 0000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 05: 0111 0000 0000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 06: 0111 0000 0000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 07: 0111 0000 0000 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 08: 0111 0000 0000 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 09: 0111 0000 0000 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0a: 0111 0000 0000 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0b: 0111 0000 0000 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0c: 0111 0000 0000 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 0d: 0111 0000 0000 1101 */ - {SSPD_w, 4,20,20,L0|L1}, /* 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */ - {LSPD_w, 4,20,20,L0|L1}, /* 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */ - - {illegal2, 2, 8, 8,L0|L1}, /* 10: 0111 0000 0001 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 11: 0111 0000 0001 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 12: 0111 0000 0001 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 13: 0111 0000 0001 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 14: 0111 0000 0001 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 15: 0111 0000 0001 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 16: 0111 0000 0001 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 17: 0111 0000 0001 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 18: 0111 0000 0001 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 19: 0111 0000 0001 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1a: 0111 0000 0001 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1b: 0111 0000 0001 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1c: 0111 0000 0001 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 1d: 0111 0000 0001 1101 */ - {SBCD_w, 4,20,20,L0|L1}, /* 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */ - {LBCD_w, 4,20,20,L0|L1}, /* 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */ - - {illegal2, 2, 8, 8,L0|L1}, /* 20: 0111 0000 0010 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 21: 0111 0000 0010 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 22: 0111 0000 0010 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 23: 0111 0000 0010 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 24: 0111 0000 0010 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 25: 0111 0000 0010 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 26: 0111 0000 0010 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 27: 0111 0000 0010 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 28: 0111 0000 0010 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 29: 0111 0000 0010 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2a: 0111 0000 0010 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2b: 0111 0000 0010 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2c: 0111 0000 0010 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 2d: 0111 0000 0010 1101 */ - {SDED_w, 4,20,20,L0|L1}, /* 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */ - {LDED_w, 4,20,20,L0|L1}, /* 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */ - - {illegal2, 2, 8, 8,L0|L1}, /* 30: 0111 0000 0011 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 31: 0111 0000 0011 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 32: 0111 0000 0011 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 33: 0111 0000 0011 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 34: 0111 0000 0011 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 35: 0111 0000 0011 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 36: 0111 0000 0011 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 37: 0111 0000 0011 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 38: 0111 0000 0011 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 39: 0111 0000 0011 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3a: 0111 0000 0011 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3b: 0111 0000 0011 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3c: 0111 0000 0011 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 3d: 0111 0000 0011 1101 */ - {SHLD_w, 4,20,20,L0|L1}, /* 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */ - {LHLD_w, 4,20,20,L0|L1}, /* 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */ - - {illegal2, 2, 8, 8,L0|L1}, /* 40: 0111 0000 0100 0000 */ - {EADD_EA_A, 2,11,11,L0|L1}, /* 41: 0111 0000 0100 0001 */ - {EADD_EA_B, 2,11,11,L0|L1}, /* 42: 0111 0000 0100 0010 */ - {EADD_EA_C, 2,11,11,L0|L1}, /* 43: 0111 0000 0100 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 44: 0111 0000 0100 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 45: 0111 0000 0100 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 46: 0111 0000 0100 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 47: 0111 0000 0100 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 48: 0111 0000 0100 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 49: 0111 0000 0100 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4a: 0111 0000 0100 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4b: 0111 0000 0100 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4c: 0111 0000 0100 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4d: 0111 0000 0100 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4e: 0111 0000 0100 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 4f: 0111 0000 0100 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 50: 0111 0000 0101 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 51: 0111 0000 0101 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 52: 0111 0000 0101 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 53: 0111 0000 0101 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 54: 0111 0000 0101 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 55: 0111 0000 0101 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 56: 0111 0000 0101 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 57: 0111 0000 0101 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 58: 0111 0000 0101 1000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 59: 0111 0000 0101 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5a: 0111 0000 0101 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5b: 0111 0000 0101 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5c: 0111 0000 0101 1100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5d: 0111 0000 0101 1101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5e: 0111 0000 0101 1110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 5f: 0111 0000 0101 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 60: 0111 0000 0110 0000 */ - {ESUB_EA_A, 2,11,11,L0|L1}, /* 61: 0111 0000 0110 0001 */ - {ESUB_EA_B, 2,11,11,L0|L1}, /* 62: 0111 0000 0110 0010 */ - {ESUB_EA_C, 2,11,11,L0|L1}, /* 63: 0111 0000 0110 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 64: 0111 0000 0110 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 65: 0111 0000 0110 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 66: 0111 0000 0110 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 67: 0111 0000 0110 0111 */ - {MOV_V_w, 4,17,17,L0|L1}, /* 68: 0111 0000 0110 1000 llll llll hhhh hhhh */ - {MOV_A_w, 4,17,17,L0|L1}, /* 69: 0111 0000 0110 1001 llll llll hhhh hhhh */ - {MOV_B_w, 4,17,17,L0|L1}, /* 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */ - {MOV_C_w, 4,17,17,L0|L1}, /* 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */ - {MOV_D_w, 4,17,17,L0|L1}, /* 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */ - {MOV_E_w, 4,17,17,L0|L1}, /* 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */ - {MOV_H_w, 4,17,17,L0|L1}, /* 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */ - {MOV_L_w, 4,17,17,L0|L1}, /* 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */ - - {illegal2, 2, 8, 8,L0|L1}, /* 70: 0111 0000 0111 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 71: 0111 0000 0111 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 72: 0111 0000 0111 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 73: 0111 0000 0111 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 74: 0111 0000 0111 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 75: 0111 0000 0111 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 76: 0111 0000 0111 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 77: 0111 0000 0111 0111 */ - {MOV_w_V, 4,17,17,L0|L1}, /* 78: 0111 0000 0111 1000 llll llll hhhh hhhh */ - {MOV_w_A, 4,17,17,L0|L1}, /* 79: 0111 0000 0111 1001 llll llll hhhh hhhh */ - {MOV_w_B, 4,17,17,L0|L1}, /* 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */ - {MOV_w_C, 4,17,17,L0|L1}, /* 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */ - {MOV_w_D, 4,17,17,L0|L1}, /* 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */ - {MOV_w_E, 4,17,17,L0|L1}, /* 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */ - {MOV_w_H, 4,17,17,L0|L1}, /* 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */ - {MOV_w_L, 4,17,17,L0|L1}, /* 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */ - - {illegal2, 2, 8, 8,L0|L1}, /* 80: 0111 0000 1000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 81: 0111 0000 1000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 82: 0111 0000 1000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 83: 0111 0000 1000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 84: 0111 0000 1000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 85: 0111 0000 1000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 86: 0111 0000 1000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 87: 0111 0000 1000 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 88: 0111 0000 1000 1000 */ - {ANAX_B, 2,11,11,L0|L1}, /* 89: 0111 0000 1000 1001 */ - {ANAX_D, 2,11,11,L0|L1}, /* 8a: 0111 0000 1000 1010 */ - {ANAX_H, 2,11,11,L0|L1}, /* 8b: 0111 0000 1000 1011 */ - {ANAX_Dp, 2,11,11,L0|L1}, /* 8c: 0111 0000 1000 1100 */ - {ANAX_Hp, 2,11,11,L0|L1}, /* 8d: 0111 0000 1000 1101 */ - {ANAX_Dm, 2,11,11,L0|L1}, /* 8e: 0111 0000 1000 1110 */ - {ANAX_Hm, 2,11,11,L0|L1}, /* 8f: 0111 0000 1000 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* 90: 0111 0000 1001 0000 */ - {XRAX_B, 2,11,11,L0|L1}, /* 91: 0111 0000 1001 0001 */ - {XRAX_D, 2,11,11,L0|L1}, /* 92: 0111 0000 1001 0010 */ - {XRAX_H, 2,11,11,L0|L1}, /* 93: 0111 0000 1001 0011 */ - {XRAX_Dp, 2,11,11,L0|L1}, /* 94: 0111 0000 1001 0100 */ - {XRAX_Hp, 2,11,11,L0|L1}, /* 95: 0111 0000 1001 0101 */ - {XRAX_Dm, 2,11,11,L0|L1}, /* 96: 0111 0000 1001 0110 */ - {XRAX_Hm, 2,11,11,L0|L1}, /* 97: 0111 0000 1001 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* 98: 0111 0000 1001 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 00: 0111 0000 0000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 01: 0111 0000 0000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 02: 0111 0000 0000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 03: 0111 0000 0000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 04: 0111 0000 0000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 05: 0111 0000 0000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 06: 0111 0000 0000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 07: 0111 0000 0000 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 08: 0111 0000 0000 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 09: 0111 0000 0000 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0a: 0111 0000 0000 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0b: 0111 0000 0000 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0c: 0111 0000 0000 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0d: 0111 0000 0000 1101 */ + {&upd7810_device::SSPD_w, 4,20,20,L0|L1}, /* 0e: 0111 0000 0000 1110 llll llll hhhh hhhh */ + {&upd7810_device::LSPD_w, 4,20,20,L0|L1}, /* 0f: 0111 0000 0000 1111 llll llll hhhh hhhh */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 10: 0111 0000 0001 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 11: 0111 0000 0001 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 12: 0111 0000 0001 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 13: 0111 0000 0001 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 14: 0111 0000 0001 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 15: 0111 0000 0001 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 16: 0111 0000 0001 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 17: 0111 0000 0001 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 18: 0111 0000 0001 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 19: 0111 0000 0001 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1a: 0111 0000 0001 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1b: 0111 0000 0001 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1c: 0111 0000 0001 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 1d: 0111 0000 0001 1101 */ + {&upd7810_device::SBCD_w, 4,20,20,L0|L1}, /* 1e: 0111 0000 0001 1110 llll llll hhhh hhhh */ + {&upd7810_device::LBCD_w, 4,20,20,L0|L1}, /* 1f: 0111 0000 0001 1111 llll llll hhhh hhhh */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 20: 0111 0000 0010 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 21: 0111 0000 0010 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 22: 0111 0000 0010 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 23: 0111 0000 0010 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 24: 0111 0000 0010 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 25: 0111 0000 0010 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 26: 0111 0000 0010 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 27: 0111 0000 0010 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 28: 0111 0000 0010 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 29: 0111 0000 0010 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2a: 0111 0000 0010 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2b: 0111 0000 0010 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2c: 0111 0000 0010 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 2d: 0111 0000 0010 1101 */ + {&upd7810_device::SDED_w, 4,20,20,L0|L1}, /* 2e: 0111 0000 0010 1110 llll llll hhhh hhhh */ + {&upd7810_device::LDED_w, 4,20,20,L0|L1}, /* 2f: 0111 0000 0010 1111 llll llll hhhh hhhh */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 30: 0111 0000 0011 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 31: 0111 0000 0011 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 32: 0111 0000 0011 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 33: 0111 0000 0011 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 34: 0111 0000 0011 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 35: 0111 0000 0011 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 36: 0111 0000 0011 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 37: 0111 0000 0011 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 38: 0111 0000 0011 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 39: 0111 0000 0011 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3a: 0111 0000 0011 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3b: 0111 0000 0011 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3c: 0111 0000 0011 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 3d: 0111 0000 0011 1101 */ + {&upd7810_device::SHLD_w, 4,20,20,L0|L1}, /* 3e: 0111 0000 0011 1110 llll llll hhhh hhhh */ + {&upd7810_device::LHLD_w, 4,20,20,L0|L1}, /* 3f: 0111 0000 0011 1111 llll llll hhhh hhhh */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 40: 0111 0000 0100 0000 */ + {&upd7810_device::EADD_EA_A, 2,11,11,L0|L1}, /* 41: 0111 0000 0100 0001 */ + {&upd7810_device::EADD_EA_B, 2,11,11,L0|L1}, /* 42: 0111 0000 0100 0010 */ + {&upd7810_device::EADD_EA_C, 2,11,11,L0|L1}, /* 43: 0111 0000 0100 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 44: 0111 0000 0100 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 45: 0111 0000 0100 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 46: 0111 0000 0100 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 47: 0111 0000 0100 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 48: 0111 0000 0100 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 49: 0111 0000 0100 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4a: 0111 0000 0100 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4b: 0111 0000 0100 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4c: 0111 0000 0100 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4d: 0111 0000 0100 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4e: 0111 0000 0100 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 4f: 0111 0000 0100 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 50: 0111 0000 0101 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 51: 0111 0000 0101 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 52: 0111 0000 0101 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 53: 0111 0000 0101 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 54: 0111 0000 0101 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 55: 0111 0000 0101 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 56: 0111 0000 0101 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 57: 0111 0000 0101 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 58: 0111 0000 0101 1000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 59: 0111 0000 0101 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5a: 0111 0000 0101 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5b: 0111 0000 0101 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5c: 0111 0000 0101 1100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5d: 0111 0000 0101 1101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5e: 0111 0000 0101 1110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 5f: 0111 0000 0101 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 60: 0111 0000 0110 0000 */ + {&upd7810_device::ESUB_EA_A, 2,11,11,L0|L1}, /* 61: 0111 0000 0110 0001 */ + {&upd7810_device::ESUB_EA_B, 2,11,11,L0|L1}, /* 62: 0111 0000 0110 0010 */ + {&upd7810_device::ESUB_EA_C, 2,11,11,L0|L1}, /* 63: 0111 0000 0110 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 64: 0111 0000 0110 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 65: 0111 0000 0110 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 66: 0111 0000 0110 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 67: 0111 0000 0110 0111 */ + {&upd7810_device::MOV_V_w, 4,17,17,L0|L1}, /* 68: 0111 0000 0110 1000 llll llll hhhh hhhh */ + {&upd7810_device::MOV_A_w, 4,17,17,L0|L1}, /* 69: 0111 0000 0110 1001 llll llll hhhh hhhh */ + {&upd7810_device::MOV_B_w, 4,17,17,L0|L1}, /* 6a: 0111 0000 0110 1010 llll llll hhhh hhhh */ + {&upd7810_device::MOV_C_w, 4,17,17,L0|L1}, /* 6b: 0111 0000 0110 1011 llll llll hhhh hhhh */ + {&upd7810_device::MOV_D_w, 4,17,17,L0|L1}, /* 6c: 0111 0000 0110 1100 llll llll hhhh hhhh */ + {&upd7810_device::MOV_E_w, 4,17,17,L0|L1}, /* 6d: 0111 0000 0110 1101 llll llll hhhh hhhh */ + {&upd7810_device::MOV_H_w, 4,17,17,L0|L1}, /* 6e: 0111 0000 0110 1110 llll llll hhhh hhhh */ + {&upd7810_device::MOV_L_w, 4,17,17,L0|L1}, /* 6f: 0111 0000 0110 1111 llll llll hhhh hhhh */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 70: 0111 0000 0111 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 71: 0111 0000 0111 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 72: 0111 0000 0111 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 73: 0111 0000 0111 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 74: 0111 0000 0111 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 75: 0111 0000 0111 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 76: 0111 0000 0111 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 77: 0111 0000 0111 0111 */ + {&upd7810_device::MOV_w_V, 4,17,17,L0|L1}, /* 78: 0111 0000 0111 1000 llll llll hhhh hhhh */ + {&upd7810_device::MOV_w_A, 4,17,17,L0|L1}, /* 79: 0111 0000 0111 1001 llll llll hhhh hhhh */ + {&upd7810_device::MOV_w_B, 4,17,17,L0|L1}, /* 7a: 0111 0000 0111 1010 llll llll hhhh hhhh */ + {&upd7810_device::MOV_w_C, 4,17,17,L0|L1}, /* 7b: 0111 0000 0111 1011 llll llll hhhh hhhh */ + {&upd7810_device::MOV_w_D, 4,17,17,L0|L1}, /* 7c: 0111 0000 0111 1100 llll llll hhhh hhhh */ + {&upd7810_device::MOV_w_E, 4,17,17,L0|L1}, /* 7d: 0111 0000 0111 1101 llll llll hhhh hhhh */ + {&upd7810_device::MOV_w_H, 4,17,17,L0|L1}, /* 7e: 0111 0000 0111 1110 llll llll hhhh hhhh */ + {&upd7810_device::MOV_w_L, 4,17,17,L0|L1}, /* 7f: 0111 0000 0111 1111 llll llll hhhh hhhh */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 80: 0111 0000 1000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 81: 0111 0000 1000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 82: 0111 0000 1000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 83: 0111 0000 1000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 84: 0111 0000 1000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 85: 0111 0000 1000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 86: 0111 0000 1000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 87: 0111 0000 1000 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 88: 0111 0000 1000 1000 */ + {&upd7810_device::ANAX_B, 2,11,11,L0|L1}, /* 89: 0111 0000 1000 1001 */ + {&upd7810_device::ANAX_D, 2,11,11,L0|L1}, /* 8a: 0111 0000 1000 1010 */ + {&upd7810_device::ANAX_H, 2,11,11,L0|L1}, /* 8b: 0111 0000 1000 1011 */ + {&upd7810_device::ANAX_Dp, 2,11,11,L0|L1}, /* 8c: 0111 0000 1000 1100 */ + {&upd7810_device::ANAX_Hp, 2,11,11,L0|L1}, /* 8d: 0111 0000 1000 1101 */ + {&upd7810_device::ANAX_Dm, 2,11,11,L0|L1}, /* 8e: 0111 0000 1000 1110 */ + {&upd7810_device::ANAX_Hm, 2,11,11,L0|L1}, /* 8f: 0111 0000 1000 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 90: 0111 0000 1001 0000 */ + {&upd7810_device::XRAX_B, 2,11,11,L0|L1}, /* 91: 0111 0000 1001 0001 */ + {&upd7810_device::XRAX_D, 2,11,11,L0|L1}, /* 92: 0111 0000 1001 0010 */ + {&upd7810_device::XRAX_H, 2,11,11,L0|L1}, /* 93: 0111 0000 1001 0011 */ + {&upd7810_device::XRAX_Dp, 2,11,11,L0|L1}, /* 94: 0111 0000 1001 0100 */ + {&upd7810_device::XRAX_Hp, 2,11,11,L0|L1}, /* 95: 0111 0000 1001 0101 */ + {&upd7810_device::XRAX_Dm, 2,11,11,L0|L1}, /* 96: 0111 0000 1001 0110 */ + {&upd7810_device::XRAX_Hm, 2,11,11,L0|L1}, /* 97: 0111 0000 1001 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 98: 0111 0000 1001 1000 */ // orax added, timings not verified - {ORAX_B, 2,11, 8,L0|L1}, /* 99: 0111 0000 1001 1001 */ - {ORAX_D, 2,11, 8,L0|L1}, /* 9a: 0111 0000 1001 1010 */ - {ORAX_H, 2,11, 8,L0|L1}, /* 9b: 0111 0000 1001 1011 */ - {ORAX_Dp, 2,11, 8,L0|L1}, /* 9c: 0111 0000 1001 1100 */ - {ORAX_Hp, 2,11, 8,L0|L1}, /* 9d: 0111 0000 1001 1101 */ - {ORAX_Dm, 2,11, 8,L0|L1}, /* 9e: 0111 0000 1001 1110 */ - {ORAX_Hm, 2,11, 8,L0|L1}, /* 9f: 0111 0000 1001 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* a0: 0111 0000 1010 0000 */ - {ADDNCX_B, 2,11, 8,L0|L1}, /* a1: 0111 0000 1010 0001 */ - {ADDNCX_D, 2,11, 8,L0|L1}, /* a2: 0111 0000 1010 0010 */ - {ADDNCX_H, 2,11, 8,L0|L1}, /* a3: 0111 0000 1010 0011 */ - {ADDNCX_Dp, 2,11, 8,L0|L1}, /* a4: 0111 0000 1010 0100 */ - {ADDNCX_Hp, 2,11, 8,L0|L1}, /* a5: 0111 0000 1010 0101 */ - {ADDNCX_Dm, 2,11, 8,L0|L1}, /* a6: 0111 0000 1010 0110 */ - {ADDNCX_Hm, 2,11, 8,L0|L1}, /* a7: 0111 0000 1010 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* a8: 0111 0000 1010 1000 */ - {GTAX_B, 2,11,11,L0|L1}, /* a9: 0111 0000 1010 1001 */ - {GTAX_D, 2,11,11,L0|L1}, /* aa: 0111 0000 1010 1010 */ - {GTAX_H, 2,11,11,L0|L1}, /* ab: 0111 0000 1010 1011 */ - {GTAX_Dp, 2,11,11,L0|L1}, /* ac: 0111 0000 1010 1100 */ - {GTAX_Hp, 2,11,11,L0|L1}, /* ad: 0111 0000 1010 1101 */ - {GTAX_Dm, 2,11,11,L0|L1}, /* ae: 0111 0000 1010 1110 */ - {GTAX_Hm, 2,11,11,L0|L1}, /* af: 0111 0000 1010 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* b0: 0111 0000 1011 0000 */ - {SUBNBX_B, 2,11,11,L0|L1}, /* b1: 0111 0000 1011 0001 */ - {SUBNBX_D, 2,11,11,L0|L1}, /* b2: 0111 0000 1011 0010 */ - {SUBNBX_H, 2,11,11,L0|L1}, /* b3: 0111 0000 1011 0011 */ - {SUBNBX_Dp, 2,11,11,L0|L1}, /* b4: 0111 0000 1011 0100 */ - {SUBNBX_Hp, 2,11,11,L0|L1}, /* b5: 0111 0000 1011 0101 */ - {SUBNBX_Dm, 2,11,11,L0|L1}, /* b6: 0111 0000 1011 0110 */ - {SUBNBX_Hm, 2,11,11,L0|L1}, /* b7: 0111 0000 1011 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* b8: 0111 0000 1011 1000 */ - {LTAX_B, 2,11,11,L0|L1}, /* b9: 0111 0000 1011 1001 */ - {LTAX_D, 2,11,11,L0|L1}, /* ba: 0111 0000 1011 1010 */ - {LTAX_H, 2,11,11,L0|L1}, /* bb: 0111 0000 1011 1011 */ - {LTAX_Dp, 2,11,11,L0|L1}, /* bc: 0111 0000 1011 1100 */ - {LTAX_Hp, 2,11,11,L0|L1}, /* bd: 0111 0000 1011 1101 */ - {LTAX_Dm, 2,11,11,L0|L1}, /* be: 0111 0000 1011 1110 */ - {LTAX_Hm, 2,11,11,L0|L1}, /* bf: 0111 0000 1011 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* c0: 0111 0000 1100 0000 */ - {ADDX_B, 2,11, 8,L0|L1}, /* c1: 0111 0000 1100 0001 */ - {ADDX_D, 2,11, 8,L0|L1}, /* c2: 0111 0000 1100 0010 */ - {ADDX_H, 2,11, 8,L0|L1}, /* c3: 0111 0000 1100 0011 */ - {ADDX_Dp, 2,11, 8,L0|L1}, /* c4: 0111 0000 1100 0100 */ - {ADDX_Hp, 2,11, 8,L0|L1}, /* c5: 0111 0000 1100 0101 */ - {ADDX_Dm, 2,11, 8,L0|L1}, /* c6: 0111 0000 1100 0110 */ - {ADDX_Hm, 2,11, 8,L0|L1}, /* c7: 0111 0000 1100 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* c8: 0111 0000 1100 1000 */ - {ONAX_B, 2,11, 8,L0|L1}, /* c9: 0111 0000 1100 1001 */ - {ONAX_D, 2,11, 8,L0|L1}, /* ca: 0111 0000 1100 1010 */ - {ONAX_H, 2,11, 8,L0|L1}, /* cb: 0111 0000 1100 1011 */ - {ONAX_Dp, 2,11, 8,L0|L1}, /* cc: 0111 0000 1100 1100 */ - {ONAX_Hp, 2,11, 8,L0|L1}, /* cd: 0111 0000 1100 1101 */ - {ONAX_Dm, 2,11, 8,L0|L1}, /* ce: 0111 0000 1100 1110 */ - {ONAX_Hm, 2,11, 8,L0|L1}, /* cf: 0111 0000 1100 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* d0: 0111 0000 1101 0000 */ - {ADCX_B, 2,11, 8,L0|L1}, /* d1: 0111 0000 1101 0001 */ - {ADCX_D, 2,11, 8,L0|L1}, /* d2: 0111 0000 1101 0010 */ - {ADCX_H, 2,11, 8,L0|L1}, /* d3: 0111 0000 1101 0011 */ - {ADCX_Dp, 2,11, 8,L0|L1}, /* d4: 0111 0000 1101 0100 */ - {ADCX_Hp, 2,11, 8,L0|L1}, /* d5: 0111 0000 1101 0101 */ - {ADCX_Dm, 2,11, 8,L0|L1}, /* d6: 0111 0000 1101 0110 */ - {ADCX_Hm, 2,11, 8,L0|L1}, /* d7: 0111 0000 1101 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* d8: 0111 0000 1101 1000 */ - {OFFAX_B, 2,11, 8,L0|L1}, /* d9: 0111 0000 1101 1001 */ - {OFFAX_D, 2,11, 8,L0|L1}, /* da: 0111 0000 1101 1010 */ - {OFFAX_H, 2,11, 8,L0|L1}, /* db: 0111 0000 1101 1011 */ - {OFFAX_Dp, 2,11, 8,L0|L1}, /* dc: 0111 0000 1101 1100 */ - {OFFAX_Hp, 2,11, 8,L0|L1}, /* dd: 0111 0000 1101 1101 */ - {OFFAX_Dm, 2,11, 8,L0|L1}, /* de: 0111 0000 1101 1110 */ - {OFFAX_Hm, 2,11, 8,L0|L1}, /* df: 0111 0000 1101 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* e0: 0111 0000 1110 0000 */ - {SUBX_B, 2,11,11,L0|L1}, /* e1: 0111 0000 1110 0001 */ - {SUBX_D, 2,11,11,L0|L1}, /* e2: 0111 0000 1110 0010 */ - {SUBX_H, 2,11,11,L0|L1}, /* e3: 0111 0000 1110 0011 */ - {SUBX_Dp, 2,11,11,L0|L1}, /* e4: 0111 0000 1110 0100 */ - {SUBX_Hp, 2,11,11,L0|L1}, /* e5: 0111 0000 1110 0101 */ - {SUBX_Dm, 2,11,11,L0|L1}, /* e6: 0111 0000 1110 0110 */ - {SUBX_Hm, 2,11,11,L0|L1}, /* e7: 0111 0000 1110 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* e8: 0111 0000 1110 1000 */ - {NEAX_B, 2,11,11,L0|L1}, /* e9: 0111 0000 1110 1001 */ - {NEAX_D, 2,11,11,L0|L1}, /* ea: 0111 0000 1110 1010 */ - {NEAX_H, 2,11,11,L0|L1}, /* eb: 0111 0000 1110 1011 */ - {NEAX_Dp, 2,11,11,L0|L1}, /* ec: 0111 0000 1110 1100 */ - {NEAX_Hp, 2,11,11,L0|L1}, /* ed: 0111 0000 1110 1101 */ - {NEAX_Dm, 2,11,11,L0|L1}, /* ee: 0111 0000 1110 1110 */ - {NEAX_Hm, 2,11,11,L0|L1}, /* ef: 0111 0000 1110 1111 */ - - {illegal2, 2, 8, 8,L0|L1}, /* f0: 0111 0000 1111 0000 */ - {SBBX_B, 2,11,11,L0|L1}, /* f1: 0111 0000 1111 0001 */ - {SBBX_D, 2,11,11,L0|L1}, /* f2: 0111 0000 1111 0010 */ - {SBBX_H, 2,11,11,L0|L1}, /* f3: 0111 0000 1111 0011 */ - {SBBX_Dp, 2,11,11,L0|L1}, /* f4: 0111 0000 1111 0100 */ - {SBBX_Hp, 2,11,11,L0|L1}, /* f5: 0111 0000 1111 0101 */ - {SBBX_Dm, 2,11,11,L0|L1}, /* f6: 0111 0000 1111 0110 */ - {SBBX_Hm, 2,11,11,L0|L1}, /* f7: 0111 0000 1111 0111 */ - {illegal2, 2, 8, 8,L0|L1}, /* f8: 0111 0000 1111 1000 */ - {EQAX_B, 2,11,11,L0|L1}, /* f9: 0111 0000 1111 1001 */ - {EQAX_D, 2,11,11,L0|L1}, /* fa: 0111 0000 1111 1010 */ - {EQAX_H, 2,11,11,L0|L1}, /* fb: 0111 0000 1111 1011 */ - {EQAX_Dp, 2,11,11,L0|L1}, /* fc: 0111 0000 1111 1100 */ - {EQAX_Hp, 2,11,11,L0|L1}, /* fd: 0111 0000 1111 1101 */ - {EQAX_Dm, 2,11,11,L0|L1}, /* fe: 0111 0000 1111 1110 */ - {EQAX_Hm, 2,11,11,L0|L1} /* ff: 0111 0000 1111 1111 */ + {&upd7810_device::ORAX_B, 2,11, 8,L0|L1}, /* 99: 0111 0000 1001 1001 */ + {&upd7810_device::ORAX_D, 2,11, 8,L0|L1}, /* 9a: 0111 0000 1001 1010 */ + {&upd7810_device::ORAX_H, 2,11, 8,L0|L1}, /* 9b: 0111 0000 1001 1011 */ + {&upd7810_device::ORAX_Dp, 2,11, 8,L0|L1}, /* 9c: 0111 0000 1001 1100 */ + {&upd7810_device::ORAX_Hp, 2,11, 8,L0|L1}, /* 9d: 0111 0000 1001 1101 */ + {&upd7810_device::ORAX_Dm, 2,11, 8,L0|L1}, /* 9e: 0111 0000 1001 1110 */ + {&upd7810_device::ORAX_Hm, 2,11, 8,L0|L1}, /* 9f: 0111 0000 1001 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a0: 0111 0000 1010 0000 */ + {&upd7810_device::ADDNCX_B, 2,11, 8,L0|L1}, /* a1: 0111 0000 1010 0001 */ + {&upd7810_device::ADDNCX_D, 2,11, 8,L0|L1}, /* a2: 0111 0000 1010 0010 */ + {&upd7810_device::ADDNCX_H, 2,11, 8,L0|L1}, /* a3: 0111 0000 1010 0011 */ + {&upd7810_device::ADDNCX_Dp, 2,11, 8,L0|L1}, /* a4: 0111 0000 1010 0100 */ + {&upd7810_device::ADDNCX_Hp, 2,11, 8,L0|L1}, /* a5: 0111 0000 1010 0101 */ + {&upd7810_device::ADDNCX_Dm, 2,11, 8,L0|L1}, /* a6: 0111 0000 1010 0110 */ + {&upd7810_device::ADDNCX_Hm, 2,11, 8,L0|L1}, /* a7: 0111 0000 1010 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a8: 0111 0000 1010 1000 */ + {&upd7810_device::GTAX_B, 2,11,11,L0|L1}, /* a9: 0111 0000 1010 1001 */ + {&upd7810_device::GTAX_D, 2,11,11,L0|L1}, /* aa: 0111 0000 1010 1010 */ + {&upd7810_device::GTAX_H, 2,11,11,L0|L1}, /* ab: 0111 0000 1010 1011 */ + {&upd7810_device::GTAX_Dp, 2,11,11,L0|L1}, /* ac: 0111 0000 1010 1100 */ + {&upd7810_device::GTAX_Hp, 2,11,11,L0|L1}, /* ad: 0111 0000 1010 1101 */ + {&upd7810_device::GTAX_Dm, 2,11,11,L0|L1}, /* ae: 0111 0000 1010 1110 */ + {&upd7810_device::GTAX_Hm, 2,11,11,L0|L1}, /* af: 0111 0000 1010 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b0: 0111 0000 1011 0000 */ + {&upd7810_device::SUBNBX_B, 2,11,11,L0|L1}, /* b1: 0111 0000 1011 0001 */ + {&upd7810_device::SUBNBX_D, 2,11,11,L0|L1}, /* b2: 0111 0000 1011 0010 */ + {&upd7810_device::SUBNBX_H, 2,11,11,L0|L1}, /* b3: 0111 0000 1011 0011 */ + {&upd7810_device::SUBNBX_Dp, 2,11,11,L0|L1}, /* b4: 0111 0000 1011 0100 */ + {&upd7810_device::SUBNBX_Hp, 2,11,11,L0|L1}, /* b5: 0111 0000 1011 0101 */ + {&upd7810_device::SUBNBX_Dm, 2,11,11,L0|L1}, /* b6: 0111 0000 1011 0110 */ + {&upd7810_device::SUBNBX_Hm, 2,11,11,L0|L1}, /* b7: 0111 0000 1011 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b8: 0111 0000 1011 1000 */ + {&upd7810_device::LTAX_B, 2,11,11,L0|L1}, /* b9: 0111 0000 1011 1001 */ + {&upd7810_device::LTAX_D, 2,11,11,L0|L1}, /* ba: 0111 0000 1011 1010 */ + {&upd7810_device::LTAX_H, 2,11,11,L0|L1}, /* bb: 0111 0000 1011 1011 */ + {&upd7810_device::LTAX_Dp, 2,11,11,L0|L1}, /* bc: 0111 0000 1011 1100 */ + {&upd7810_device::LTAX_Hp, 2,11,11,L0|L1}, /* bd: 0111 0000 1011 1101 */ + {&upd7810_device::LTAX_Dm, 2,11,11,L0|L1}, /* be: 0111 0000 1011 1110 */ + {&upd7810_device::LTAX_Hm, 2,11,11,L0|L1}, /* bf: 0111 0000 1011 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c0: 0111 0000 1100 0000 */ + {&upd7810_device::ADDX_B, 2,11, 8,L0|L1}, /* c1: 0111 0000 1100 0001 */ + {&upd7810_device::ADDX_D, 2,11, 8,L0|L1}, /* c2: 0111 0000 1100 0010 */ + {&upd7810_device::ADDX_H, 2,11, 8,L0|L1}, /* c3: 0111 0000 1100 0011 */ + {&upd7810_device::ADDX_Dp, 2,11, 8,L0|L1}, /* c4: 0111 0000 1100 0100 */ + {&upd7810_device::ADDX_Hp, 2,11, 8,L0|L1}, /* c5: 0111 0000 1100 0101 */ + {&upd7810_device::ADDX_Dm, 2,11, 8,L0|L1}, /* c6: 0111 0000 1100 0110 */ + {&upd7810_device::ADDX_Hm, 2,11, 8,L0|L1}, /* c7: 0111 0000 1100 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c8: 0111 0000 1100 1000 */ + {&upd7810_device::ONAX_B, 2,11, 8,L0|L1}, /* c9: 0111 0000 1100 1001 */ + {&upd7810_device::ONAX_D, 2,11, 8,L0|L1}, /* ca: 0111 0000 1100 1010 */ + {&upd7810_device::ONAX_H, 2,11, 8,L0|L1}, /* cb: 0111 0000 1100 1011 */ + {&upd7810_device::ONAX_Dp, 2,11, 8,L0|L1}, /* cc: 0111 0000 1100 1100 */ + {&upd7810_device::ONAX_Hp, 2,11, 8,L0|L1}, /* cd: 0111 0000 1100 1101 */ + {&upd7810_device::ONAX_Dm, 2,11, 8,L0|L1}, /* ce: 0111 0000 1100 1110 */ + {&upd7810_device::ONAX_Hm, 2,11, 8,L0|L1}, /* cf: 0111 0000 1100 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d0: 0111 0000 1101 0000 */ + {&upd7810_device::ADCX_B, 2,11, 8,L0|L1}, /* d1: 0111 0000 1101 0001 */ + {&upd7810_device::ADCX_D, 2,11, 8,L0|L1}, /* d2: 0111 0000 1101 0010 */ + {&upd7810_device::ADCX_H, 2,11, 8,L0|L1}, /* d3: 0111 0000 1101 0011 */ + {&upd7810_device::ADCX_Dp, 2,11, 8,L0|L1}, /* d4: 0111 0000 1101 0100 */ + {&upd7810_device::ADCX_Hp, 2,11, 8,L0|L1}, /* d5: 0111 0000 1101 0101 */ + {&upd7810_device::ADCX_Dm, 2,11, 8,L0|L1}, /* d6: 0111 0000 1101 0110 */ + {&upd7810_device::ADCX_Hm, 2,11, 8,L0|L1}, /* d7: 0111 0000 1101 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d8: 0111 0000 1101 1000 */ + {&upd7810_device::OFFAX_B, 2,11, 8,L0|L1}, /* d9: 0111 0000 1101 1001 */ + {&upd7810_device::OFFAX_D, 2,11, 8,L0|L1}, /* da: 0111 0000 1101 1010 */ + {&upd7810_device::OFFAX_H, 2,11, 8,L0|L1}, /* db: 0111 0000 1101 1011 */ + {&upd7810_device::OFFAX_Dp, 2,11, 8,L0|L1}, /* dc: 0111 0000 1101 1100 */ + {&upd7810_device::OFFAX_Hp, 2,11, 8,L0|L1}, /* dd: 0111 0000 1101 1101 */ + {&upd7810_device::OFFAX_Dm, 2,11, 8,L0|L1}, /* de: 0111 0000 1101 1110 */ + {&upd7810_device::OFFAX_Hm, 2,11, 8,L0|L1}, /* df: 0111 0000 1101 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e0: 0111 0000 1110 0000 */ + {&upd7810_device::SUBX_B, 2,11,11,L0|L1}, /* e1: 0111 0000 1110 0001 */ + {&upd7810_device::SUBX_D, 2,11,11,L0|L1}, /* e2: 0111 0000 1110 0010 */ + {&upd7810_device::SUBX_H, 2,11,11,L0|L1}, /* e3: 0111 0000 1110 0011 */ + {&upd7810_device::SUBX_Dp, 2,11,11,L0|L1}, /* e4: 0111 0000 1110 0100 */ + {&upd7810_device::SUBX_Hp, 2,11,11,L0|L1}, /* e5: 0111 0000 1110 0101 */ + {&upd7810_device::SUBX_Dm, 2,11,11,L0|L1}, /* e6: 0111 0000 1110 0110 */ + {&upd7810_device::SUBX_Hm, 2,11,11,L0|L1}, /* e7: 0111 0000 1110 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e8: 0111 0000 1110 1000 */ + {&upd7810_device::NEAX_B, 2,11,11,L0|L1}, /* e9: 0111 0000 1110 1001 */ + {&upd7810_device::NEAX_D, 2,11,11,L0|L1}, /* ea: 0111 0000 1110 1010 */ + {&upd7810_device::NEAX_H, 2,11,11,L0|L1}, /* eb: 0111 0000 1110 1011 */ + {&upd7810_device::NEAX_Dp, 2,11,11,L0|L1}, /* ec: 0111 0000 1110 1100 */ + {&upd7810_device::NEAX_Hp, 2,11,11,L0|L1}, /* ed: 0111 0000 1110 1101 */ + {&upd7810_device::NEAX_Dm, 2,11,11,L0|L1}, /* ee: 0111 0000 1110 1110 */ + {&upd7810_device::NEAX_Hm, 2,11,11,L0|L1}, /* ef: 0111 0000 1110 1111 */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f0: 0111 0000 1111 0000 */ + {&upd7810_device::SBBX_B, 2,11,11,L0|L1}, /* f1: 0111 0000 1111 0001 */ + {&upd7810_device::SBBX_D, 2,11,11,L0|L1}, /* f2: 0111 0000 1111 0010 */ + {&upd7810_device::SBBX_H, 2,11,11,L0|L1}, /* f3: 0111 0000 1111 0011 */ + {&upd7810_device::SBBX_Dp, 2,11,11,L0|L1}, /* f4: 0111 0000 1111 0100 */ + {&upd7810_device::SBBX_Hp, 2,11,11,L0|L1}, /* f5: 0111 0000 1111 0101 */ + {&upd7810_device::SBBX_Dm, 2,11,11,L0|L1}, /* f6: 0111 0000 1111 0110 */ + {&upd7810_device::SBBX_Hm, 2,11,11,L0|L1}, /* f7: 0111 0000 1111 0111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f8: 0111 0000 1111 1000 */ + {&upd7810_device::EQAX_B, 2,11,11,L0|L1}, /* f9: 0111 0000 1111 1001 */ + {&upd7810_device::EQAX_D, 2,11,11,L0|L1}, /* fa: 0111 0000 1111 1010 */ + {&upd7810_device::EQAX_H, 2,11,11,L0|L1}, /* fb: 0111 0000 1111 1011 */ + {&upd7810_device::EQAX_Dp, 2,11,11,L0|L1}, /* fc: 0111 0000 1111 1100 */ + {&upd7810_device::EQAX_Hp, 2,11,11,L0|L1}, /* fd: 0111 0000 1111 1101 */ + {&upd7810_device::EQAX_Dm, 2,11,11,L0|L1}, /* fe: 0111 0000 1111 1110 */ + {&upd7810_device::EQAX_Hm, 2,11,11,L0|L1} /* ff: 0111 0000 1111 1111 */ }; /* prefix 74 */ -static const struct opcode_s op74[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op74[256] = { - {illegal2, 2, 8, 8,L0|L1}, /* 00: 0111 0100 0000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 01: 0111 0100 0000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 02: 0111 0100 0000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 03: 0111 0100 0000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 04: 0111 0100 0000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 05: 0111 0100 0000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 06: 0111 0100 0000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 07: 0111 0100 0000 0111 */ - {ANI_V_xx, 3,11,11,L0|L1}, /* 08: 0111 0100 0000 1000 xxxx xxxx */ - {ANI_A_xx, 3,11,11,L0|L1}, /* 09: 0111 0100 0000 1001 xxxx xxxx */ - {ANI_B_xx, 3,11,11,L0|L1}, /* 0a: 0111 0100 0000 1010 xxxx xxxx */ - {ANI_C_xx, 3,11,11,L0|L1}, /* 0b: 0111 0100 0000 1011 xxxx xxxx */ - {ANI_D_xx, 3,11,11,L0|L1}, /* 0c: 0111 0100 0000 1100 xxxx xxxx */ - {ANI_E_xx, 3,11,11,L0|L1}, /* 0d: 0111 0100 0000 1101 xxxx xxxx */ - {ANI_H_xx, 3,11,11,L0|L1}, /* 0e: 0111 0100 0000 1110 xxxx xxxx */ - {ANI_L_xx, 3,11,11,L0|L1}, /* 0f: 0111 0100 0000 1111 xxxx xxxx */ - - {XRI_V_xx, 3,11,11,L0|L1}, /* 10: 0111 0100 0001 0000 xxxx xxxx */ - {XRI_A_xx, 3,11,11,L0|L1}, /* 11: 0111 0100 0001 0001 xxxx xxxx */ - {XRI_B_xx, 3,11,11,L0|L1}, /* 12: 0111 0100 0001 0010 xxxx xxxx */ - {XRI_C_xx, 3,11,11,L0|L1}, /* 13: 0111 0100 0001 0011 xxxx xxxx */ - {XRI_D_xx, 3,11,11,L0|L1}, /* 14: 0111 0100 0001 0100 xxxx xxxx */ - {XRI_E_xx, 3,11,11,L0|L1}, /* 15: 0111 0100 0001 0101 xxxx xxxx */ - {XRI_H_xx, 3,11,11,L0|L1}, /* 16: 0111 0100 0001 0110 xxxx xxxx */ - {XRI_L_xx, 3,11,11,L0|L1}, /* 17: 0111 0100 0001 0111 xxxx xxxx */ - {ORI_V_xx, 3,11,11,L0|L1}, /* 18: 0111 0100 0001 1000 xxxx xxxx */ - {ORI_A_xx, 3,11,11,L0|L1}, /* 19: 0111 0100 0001 1001 xxxx xxxx */ - {ORI_B_xx, 3,11,11,L0|L1}, /* 1a: 0111 0100 0001 1010 xxxx xxxx */ - {ORI_C_xx, 3,11,11,L0|L1}, /* 1b: 0111 0100 0001 1011 xxxx xxxx */ - {ORI_D_xx, 3,11,11,L0|L1}, /* 1c: 0111 0100 0001 1100 xxxx xxxx */ - {ORI_E_xx, 3,11,11,L0|L1}, /* 1d: 0111 0100 0001 1101 xxxx xxxx */ - {ORI_H_xx, 3,11,11,L0|L1}, /* 1e: 0111 0100 0001 1110 xxxx xxxx */ - {ORI_L_xx, 3,11,11,L0|L1}, /* 1f: 0111 0100 0001 1111 xxxx xxxx */ - - {ADINC_V_xx, 3,11,11,L0|L1}, /* 20: 0111 0100 0010 0000 xxxx xxxx */ - {ADINC_A_xx, 3,11,11,L0|L1}, /* 21: 0111 0100 0010 0001 xxxx xxxx */ - {ADINC_B_xx, 3,11,11,L0|L1}, /* 22: 0111 0100 0010 0010 xxxx xxxx */ - {ADINC_C_xx, 3,11,11,L0|L1}, /* 23: 0111 0100 0010 0011 xxxx xxxx */ - {ADINC_D_xx, 3,11,11,L0|L1}, /* 24: 0111 0100 0010 0100 xxxx xxxx */ - {ADINC_E_xx, 3,11,11,L0|L1}, /* 25: 0111 0100 0010 0101 xxxx xxxx */ - {ADINC_H_xx, 3,11,11,L0|L1}, /* 26: 0111 0100 0010 0110 xxxx xxxx */ - {ADINC_L_xx, 3,11,11,L0|L1}, /* 27: 0111 0100 0010 0111 xxxx xxxx */ - {GTI_V_xx, 3,11,11,L0|L1}, /* 28: 0111 0100 0010 1000 xxxx xxxx */ - {GTI_A_xx, 3,11,11,L0|L1}, /* 29: 0111 0100 0010 1001 xxxx xxxx */ - {GTI_B_xx, 3,11,11,L0|L1}, /* 2a: 0111 0100 0010 1010 xxxx xxxx */ - {GTI_C_xx, 3,11,11,L0|L1}, /* 2b: 0111 0100 0010 1011 xxxx xxxx */ - {GTI_D_xx, 3,11,11,L0|L1}, /* 2c: 0111 0100 0010 1100 xxxx xxxx */ - {GTI_E_xx, 3,11,11,L0|L1}, /* 2d: 0111 0100 0010 1101 xxxx xxxx */ - {GTI_H_xx, 3,11,11,L0|L1}, /* 2e: 0111 0100 0010 1110 xxxx xxxx */ - {GTI_L_xx, 3,11,11,L0|L1}, /* 2f: 0111 0100 0010 1111 xxxx xxxx */ - - {SUINB_V_xx, 3,11,11,L0|L1}, /* 30: 0111 0100 0011 0000 xxxx xxxx */ - {SUINB_A_xx, 3,11,11,L0|L1}, /* 31: 0111 0100 0011 0001 xxxx xxxx */ - {SUINB_B_xx, 3,11,11,L0|L1}, /* 32: 0111 0100 0011 0010 xxxx xxxx */ - {SUINB_C_xx, 3,11,11,L0|L1}, /* 33: 0111 0100 0011 0011 xxxx xxxx */ - {SUINB_D_xx, 3,11,11,L0|L1}, /* 34: 0111 0100 0011 0100 xxxx xxxx */ - {SUINB_E_xx, 3,11,11,L0|L1}, /* 35: 0111 0100 0011 0101 xxxx xxxx */ - {SUINB_H_xx, 3,11,11,L0|L1}, /* 36: 0111 0100 0011 0110 xxxx xxxx */ - {SUINB_L_xx, 3,11,11,L0|L1}, /* 37: 0111 0100 0011 0111 xxxx xxxx */ - {LTI_V_xx, 3,11,11,L0|L1}, /* 38: 0111 0100 0011 1000 xxxx xxxx */ - {LTI_A_xx, 3,11,11,L0|L1}, /* 39: 0111 0100 0011 1001 xxxx xxxx */ - {LTI_B_xx, 3,11,11,L0|L1}, /* 3a: 0111 0100 0011 1010 xxxx xxxx */ - {LTI_C_xx, 3,11,11,L0|L1}, /* 3b: 0111 0100 0011 1011 xxxx xxxx */ - {LTI_D_xx, 3,11,11,L0|L1}, /* 3c: 0111 0100 0011 1100 xxxx xxxx */ - {LTI_E_xx, 3,11,11,L0|L1}, /* 3d: 0111 0100 0011 1101 xxxx xxxx */ - {LTI_H_xx, 3,11,11,L0|L1}, /* 3e: 0111 0100 0011 1110 xxxx xxxx */ - {LTI_L_xx, 3,11,11,L0|L1}, /* 3f: 0111 0100 0011 1111 xxxx xxxx */ - - {ADI_V_xx, 3,11,11,L0|L1}, /* 40: 0111 0100 0100 0000 xxxx xxxx */ - {ADI_A_xx, 3,11,11,L0|L1}, /* 41: 0111 0100 0100 0001 xxxx xxxx */ - {ADI_B_xx, 3,11,11,L0|L1}, /* 42: 0111 0100 0100 0010 xxxx xxxx */ - {ADI_C_xx, 3,11,11,L0|L1}, /* 43: 0111 0100 0100 0011 xxxx xxxx */ - {ADI_D_xx, 3,11,11,L0|L1}, /* 44: 0111 0100 0100 0100 xxxx xxxx */ - {ADI_E_xx, 3,11,11,L0|L1}, /* 45: 0111 0100 0100 0101 xxxx xxxx */ - {ADI_H_xx, 3,11,11,L0|L1}, /* 46: 0111 0100 0100 0110 xxxx xxxx */ - {ADI_L_xx, 3,11,11,L0|L1}, /* 47: 0111 0100 0100 0111 xxxx xxxx */ - {ONI_V_xx, 3,11,11,L0|L1}, /* 48: 0111 0100 0100 1000 xxxx xxxx */ - {ONI_A_xx, 3,11,11,L0|L1}, /* 49: 0111 0100 0100 1001 xxxx xxxx */ - {ONI_B_xx, 3,11,11,L0|L1}, /* 4a: 0111 0100 0100 1010 xxxx xxxx */ - {ONI_C_xx, 3,11,11,L0|L1}, /* 4b: 0111 0100 0100 1011 xxxx xxxx */ - {ONI_D_xx, 3,11,11,L0|L1}, /* 4c: 0111 0100 0100 1100 xxxx xxxx */ - {ONI_E_xx, 3,11,11,L0|L1}, /* 4d: 0111 0100 0100 1101 xxxx xxxx */ - {ONI_H_xx, 3,11,11,L0|L1}, /* 4e: 0111 0100 0100 1110 xxxx xxxx */ - {ONI_L_xx, 3,11,11,L0|L1}, /* 4f: 0111 0100 0100 1111 xxxx xxxx */ - - {ACI_V_xx, 3,11,11,L0|L1}, /* 50: 0111 0100 0101 0000 xxxx xxxx */ - {ACI_A_xx, 3,11,11,L0|L1}, /* 51: 0111 0100 0101 0001 xxxx xxxx */ - {ACI_B_xx, 3,11,11,L0|L1}, /* 52: 0111 0100 0101 0010 xxxx xxxx */ - {ACI_C_xx, 3,11,11,L0|L1}, /* 53: 0111 0100 0101 0011 xxxx xxxx */ - {ACI_D_xx, 3,11,11,L0|L1}, /* 54: 0111 0100 0101 0100 xxxx xxxx */ - {ACI_E_xx, 3,11,11,L0|L1}, /* 55: 0111 0100 0101 0101 xxxx xxxx */ - {ACI_H_xx, 3,11,11,L0|L1}, /* 56: 0111 0100 0101 0110 xxxx xxxx */ - {ACI_L_xx, 3,11,11,L0|L1}, /* 57: 0111 0100 0101 0111 xxxx xxxx */ - {OFFI_V_xx, 3,11,11,L0|L1}, /* 58: 0111 0100 0101 1000 xxxx xxxx */ - {OFFI_A_xx, 3,11,11,L0|L1}, /* 59: 0111 0100 0101 1001 xxxx xxxx */ - {OFFI_B_xx, 3,11,11,L0|L1}, /* 5a: 0111 0100 0101 1010 xxxx xxxx */ - {OFFI_C_xx, 3,11,11,L0|L1}, /* 5b: 0111 0100 0101 1011 xxxx xxxx */ - {OFFI_D_xx, 3,11,11,L0|L1}, /* 5c: 0111 0100 0101 1100 xxxx xxxx */ - {OFFI_E_xx, 3,11,11,L0|L1}, /* 5d: 0111 0100 0101 1101 xxxx xxxx */ - {OFFI_H_xx, 3,11,11,L0|L1}, /* 5e: 0111 0100 0101 1110 xxxx xxxx */ - {OFFI_L_xx, 3,11,11,L0|L1}, /* 5f: 0111 0100 0101 1111 xxxx xxxx */ - - {SUI_V_xx, 3,11,11,L0|L1}, /* 60: 0111 0100 0110 0000 xxxx xxxx */ - {SUI_A_xx, 3,11,11,L0|L1}, /* 61: 0111 0100 0110 0001 xxxx xxxx */ - {SUI_B_xx, 3,11,11,L0|L1}, /* 62: 0111 0100 0110 0010 xxxx xxxx */ - {SUI_C_xx, 3,11,11,L0|L1}, /* 63: 0111 0100 0110 0011 xxxx xxxx */ - {SUI_D_xx, 3,11,11,L0|L1}, /* 64: 0111 0100 0110 0100 xxxx xxxx */ - {SUI_E_xx, 3,11,11,L0|L1}, /* 65: 0111 0100 0110 0101 xxxx xxxx */ - {SUI_H_xx, 3,11,11,L0|L1}, /* 66: 0111 0100 0110 0110 xxxx xxxx */ - {SUI_L_xx, 3,11,11,L0|L1}, /* 67: 0111 0100 0110 0111 xxxx xxxx */ - {NEI_V_xx, 3,11,11,L0|L1}, /* 68: 0111 0100 0110 1000 xxxx xxxx */ - {NEI_A_xx, 3,11,11,L0|L1}, /* 69: 0111 0100 0110 1001 xxxx xxxx */ - {NEI_B_xx, 3,11,11,L0|L1}, /* 6a: 0111 0100 0110 1010 xxxx xxxx */ - {NEI_C_xx, 3,11,11,L0|L1}, /* 6b: 0111 0100 0110 1011 xxxx xxxx */ - {NEI_D_xx, 3,11,11,L0|L1}, /* 6c: 0111 0100 0110 1100 xxxx xxxx */ - {NEI_E_xx, 3,11,11,L0|L1}, /* 6d: 0111 0100 0110 1101 xxxx xxxx */ - {NEI_H_xx, 3,11,11,L0|L1}, /* 6e: 0111 0100 0110 1110 xxxx xxxx */ - {NEI_L_xx, 3,11,11,L0|L1}, /* 6f: 0111 0100 0110 1111 xxxx xxxx */ - - {SBI_V_xx, 3,11,11,L0|L1}, /* 70: 0111 0100 0111 0000 xxxx xxxx */ - {SBI_A_xx, 3,11,11,L0|L1}, /* 71: 0111 0100 0111 0001 xxxx xxxx */ - {SBI_B_xx, 3,11,11,L0|L1}, /* 72: 0111 0100 0111 0010 xxxx xxxx */ - {SBI_C_xx, 3,11,11,L0|L1}, /* 73: 0111 0100 0111 0011 xxxx xxxx */ - {SBI_D_xx, 3,11,11,L0|L1}, /* 74: 0111 0100 0111 0100 xxxx xxxx */ - {SBI_E_xx, 3,11,11,L0|L1}, /* 75: 0111 0100 0111 0101 xxxx xxxx */ - {SBI_H_xx, 3,11,11,L0|L1}, /* 76: 0111 0100 0111 0110 xxxx xxxx */ - {SBI_L_xx, 3,11,11,L0|L1}, /* 77: 0111 0100 0111 0111 xxxx xxxx */ - {EQI_V_xx, 3,11,11,L0|L1}, /* 78: 0111 0100 0111 1000 xxxx xxxx */ - {EQI_A_xx, 3,11,11,L0|L1}, /* 79: 0111 0100 0111 1001 xxxx xxxx */ - {EQI_B_xx, 3,11,11,L0|L1}, /* 7a: 0111 0100 0111 1010 xxxx xxxx */ - {EQI_C_xx, 3,11,11,L0|L1}, /* 7b: 0111 0100 0111 1011 xxxx xxxx */ - {EQI_D_xx, 3,11,11,L0|L1}, /* 7c: 0111 0100 0111 1100 xxxx xxxx */ - {EQI_E_xx, 3,11,11,L0|L1}, /* 7d: 0111 0100 0111 1101 xxxx xxxx */ - {EQI_H_xx, 3,11,11,L0|L1}, /* 7e: 0111 0100 0111 1110 xxxx xxxx */ - {EQI_L_xx, 3,11,11,L0|L1}, /* 7f: 0111 0100 0111 1111 xxxx xxxx */ - - {illegal2, 2, 8, 8,L0|L1}, /* 80: 0111 0100 1000 0000 */ - {illegal2, 2, 8, 8,L0|L1}, /* 81: 0111 0100 1000 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 82: 0111 0100 1000 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 83: 0111 0100 1000 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 84: 0111 0100 1000 0100 */ - {illegal2, 2, 8, 8,L0|L1}, /* 85: 0111 0100 1000 0101 */ - {illegal2, 2, 8, 8,L0|L1}, /* 86: 0111 0100 1000 0110 */ - {illegal2, 2, 8, 8,L0|L1}, /* 87: 0111 0100 1000 0111 */ - {ANAW_wa, 3,14,11,L0|L1}, /* 88: 0111 0100 1000 1000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* 89: 0111 0100 1000 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8a: 0111 0100 1000 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8b: 0111 0100 1000 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 8c: 0111 0100 1000 1100 */ - {DAN_EA_BC, 2,11,11,L0|L1}, /* 8d: 0111 0100 1000 1101 */ - {DAN_EA_DE, 2,11,11,L0|L1}, /* 8e: 0111 0100 1000 1110 */ - {DAN_EA_HL, 2,11,11,L0|L1}, /* 8f: 0111 0100 1000 1111 */ - - {XRAW_wa, 3,14,11,L0|L1}, /* 90: 0111 0100 1001 0000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* 91: 0111 0100 1001 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 92: 0111 0100 1001 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 93: 0111 0100 1001 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 94: 0111 0100 1001 0100 */ - {DXR_EA_BC, 2,11,11,L0|L1}, /* 95: 0111 0100 1001 0101 */ - {DXR_EA_DE, 2,11,11,L0|L1}, /* 96: 0111 0100 1001 0110 */ - {DXR_EA_HL, 2,11,11,L0|L1}, /* 97: 0111 0100 1001 0111 */ - {ORAW_wa, 3,14,11,L0|L1}, /* 98: 0111 0100 1001 1000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* 99: 0111 0100 1001 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9a: 0111 0100 1001 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9b: 0111 0100 1001 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* 9c: 0111 0100 1001 1100 */ - {DOR_EA_BC, 2,11,11,L0|L1}, /* 9d: 0111 0100 1001 1101 */ - {DOR_EA_DE, 2,11,11,L0|L1}, /* 9e: 0111 0100 1001 1110 */ - {DOR_EA_HL, 2,11,11,L0|L1}, /* 9f: 0111 0100 1001 1111 */ - - {ADDNCW_wa, 3,14,11,L0|L1}, /* a0: 0111 0100 1010 0000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* a1: 0111 0100 1010 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* a2: 0111 0100 1010 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* a3: 0111 0100 1010 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* a4: 0111 0100 1010 0100 */ - {DADDNC_EA_BC, 2,11,11,L0|L1}, /* a5: 0111 0100 1010 0101 */ - {DADDNC_EA_DE, 2,11,11,L0|L1}, /* a6: 0111 0100 1010 0110 */ - {DADDNC_EA_HL, 2,11,11,L0|L1}, /* a7: 0111 0100 1010 0111 */ - {GTAW_wa, 3,14,11,L0|L1}, /* a8: 0111 0100 1010 1000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* a9: 0111 0100 1010 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* aa: 0111 0100 1010 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* ab: 0111 0100 1010 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* ac: 0111 0100 1010 1100 */ - {DGT_EA_BC, 2,11,11,L0|L1}, /* ad: 0111 0100 1010 1101 */ - {DGT_EA_DE, 2,11,11,L0|L1}, /* ae: 0111 0100 1010 1110 */ - {DGT_EA_HL, 2,11,11,L0|L1}, /* af: 0111 0100 1010 1111 */ - - {SUBNBW_wa, 3,14,11,L0|L1}, /* b0: 0111 0100 1011 0000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* b1: 0111 0100 1011 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* b2: 0111 0100 1011 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* b3: 0111 0100 1011 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* b4: 0111 0100 1011 0100 */ - {DSUBNB_EA_BC, 2,11,11,L0|L1}, /* b5: 0111 0100 1011 0101 */ - {DSUBNB_EA_DE, 2,11,11,L0|L1}, /* b6: 0111 0100 1011 0110 */ - {DSUBNB_EA_HL, 2,11,11,L0|L1}, /* b7: 0111 0100 1011 0111 */ - {LTAW_wa, 3,14,11,L0|L1}, /* b8: 0111 0100 1011 1000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* b9: 0111 0100 1011 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* ba: 0111 0100 1011 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* bb: 0111 0100 1011 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* bc: 0111 0100 1011 1100 */ - {DLT_EA_BC, 2,11,11,L0|L1}, /* bd: 0111 0100 1011 1101 */ - {DLT_EA_DE, 2,11,11,L0|L1}, /* be: 0111 0100 1011 1110 */ - {DLT_EA_HL, 2,11,11,L0|L1}, /* bf: 0111 0100 1011 1111 */ - - {ADDW_wa, 3,14,11,L0|L1}, /* c0: 0111 0100 1100 0000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* c1: 0111 0100 1100 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* c2: 0111 0100 1100 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* c3: 0111 0100 1100 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* c4: 0111 0100 1100 0100 */ - {DADD_EA_BC, 2,11,11,L0|L1}, /* c5: 0111 0100 1100 0101 */ - {DADD_EA_DE, 2,11,11,L0|L1}, /* c6: 0111 0100 1100 0110 */ - {DADD_EA_HL, 2,11,11,L0|L1}, /* c7: 0111 0100 1100 0111 */ - {ONAW_wa, 3,14,11,L0|L1}, /* c8: 0111 0100 1100 1000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* c9: 0111 0100 1100 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* ca: 0111 0100 1100 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* cb: 0111 0100 1100 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* cc: 0111 0100 1100 1100 */ - {DON_EA_BC, 2,11,11,L0|L1}, /* cd: 0111 0100 1100 1101 */ - {DON_EA_DE, 2,11,11,L0|L1}, /* ce: 0111 0100 1100 1110 */ - {DON_EA_HL, 2,11,11,L0|L1}, /* cf: 0111 0100 1100 1111 */ - - {ADCW_wa, 3,14,11,L0|L1}, /* d0: 0111 0100 1101 0000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* d1: 0111 0100 1101 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* d2: 0111 0100 1101 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* d3: 0111 0100 1101 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* d4: 0111 0100 1101 0100 */ - {DADC_EA_BC, 2,11,11,L0|L1}, /* d5: 0111 0100 1101 0101 */ - {DADC_EA_DE, 2,11,11,L0|L1}, /* d6: 0111 0100 1101 0110 */ - {DADC_EA_HL, 2,11,11,L0|L1}, /* d7: 0111 0100 1101 0111 */ - {OFFAW_wa, 3,14,11,L0|L1}, /* d8: 0111 0100 1101 1000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* d9: 0111 0100 1101 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* da: 0111 0100 1101 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* db: 0111 0100 1101 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* dc: 0111 0100 1101 1100 */ - {DOFF_EA_BC, 2,11,11,L0|L1}, /* dd: 0111 0100 1101 1101 */ - {DOFF_EA_DE, 2,11,11,L0|L1}, /* de: 0111 0100 1101 1110 */ - {DOFF_EA_HL, 2,11,11,L0|L1}, /* df: 0111 0100 1101 1111 */ - - {SUBW_wa, 3,14,11,L0|L1}, /* e0: 0111 0100 1110 0000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* e1: 0111 0100 1110 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* e2: 0111 0100 1110 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* e3: 0111 0100 1110 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* e4: 0111 0100 1110 0100 */ - {DSUB_EA_BC, 2,11,11,L0|L1}, /* e5: 0111 0100 1110 0101 */ - {DSUB_EA_DE, 2,11,11,L0|L1}, /* e6: 0111 0100 1110 0110 */ - {DSUB_EA_HL, 2,11,11,L0|L1}, /* e7: 0111 0100 1110 0111 */ - {NEAW_wa, 3,14,11,L0|L1}, /* e8: 0111 0100 1110 1000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* e9: 0111 0100 1110 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* ea: 0111 0100 1110 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* eb: 0111 0100 1110 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* ec: 0111 0100 1110 1100 */ - {DNE_EA_BC, 2,11,11,L0|L1}, /* ed: 0111 0100 1110 1101 */ - {DNE_EA_DE, 2,11,11,L0|L1}, /* ee: 0111 0100 1110 1110 */ - {DNE_EA_HL, 2,11,11,L0|L1}, /* ef: 0111 0100 1110 1111 */ - - {SBBW_wa, 3,14,11,L0|L1}, /* f0: 0111 0100 1111 0000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* f1: 0111 0100 1111 0001 */ - {illegal2, 2, 8, 8,L0|L1}, /* f2: 0111 0100 1111 0010 */ - {illegal2, 2, 8, 8,L0|L1}, /* f3: 0111 0100 1111 0011 */ - {illegal2, 2, 8, 8,L0|L1}, /* f4: 0111 0100 1111 0100 */ - {DSBB_EA_BC, 2,11,11,L0|L1}, /* f5: 0111 0100 1111 0101 */ - {DSBB_EA_DE, 2,11,11,L0|L1}, /* f6: 0111 0100 1111 0110 */ - {DSBB_EA_HL, 2,11,11,L0|L1}, /* f7: 0111 0100 1111 0111 */ - {EQAW_wa, 3,14,11,L0|L1}, /* f8: 0111 0100 1111 1000 oooo oooo */ - {illegal2, 2, 8, 8,L0|L1}, /* f9: 0111 0100 1111 1001 */ - {illegal2, 2, 8, 8,L0|L1}, /* fa: 0111 0100 1111 1010 */ - {illegal2, 2, 8, 8,L0|L1}, /* fb: 0111 0100 1111 1011 */ - {illegal2, 2, 8, 8,L0|L1}, /* fc: 0111 0100 1111 1100 */ - {DEQ_EA_BC, 2,11,11,L0|L1}, /* fd: 0111 0100 1111 1101 */ - {DEQ_EA_DE, 2,11,11,L0|L1}, /* fe: 0111 0100 1111 1110 */ - {DEQ_EA_HL, 2,11,11,L0|L1} /* ff: 0111 0100 1111 1111 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 00: 0111 0100 0000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 01: 0111 0100 0000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 02: 0111 0100 0000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 03: 0111 0100 0000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 04: 0111 0100 0000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 05: 0111 0100 0000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 06: 0111 0100 0000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 07: 0111 0100 0000 0111 */ + {&upd7810_device::ANI_V_xx, 3,11,11,L0|L1}, /* 08: 0111 0100 0000 1000 xxxx xxxx */ + {&upd7810_device::ANI_A_xx, 3,11,11,L0|L1}, /* 09: 0111 0100 0000 1001 xxxx xxxx */ + {&upd7810_device::ANI_B_xx, 3,11,11,L0|L1}, /* 0a: 0111 0100 0000 1010 xxxx xxxx */ + {&upd7810_device::ANI_C_xx, 3,11,11,L0|L1}, /* 0b: 0111 0100 0000 1011 xxxx xxxx */ + {&upd7810_device::ANI_D_xx, 3,11,11,L0|L1}, /* 0c: 0111 0100 0000 1100 xxxx xxxx */ + {&upd7810_device::ANI_E_xx, 3,11,11,L0|L1}, /* 0d: 0111 0100 0000 1101 xxxx xxxx */ + {&upd7810_device::ANI_H_xx, 3,11,11,L0|L1}, /* 0e: 0111 0100 0000 1110 xxxx xxxx */ + {&upd7810_device::ANI_L_xx, 3,11,11,L0|L1}, /* 0f: 0111 0100 0000 1111 xxxx xxxx */ + + {&upd7810_device::XRI_V_xx, 3,11,11,L0|L1}, /* 10: 0111 0100 0001 0000 xxxx xxxx */ + {&upd7810_device::XRI_A_xx, 3,11,11,L0|L1}, /* 11: 0111 0100 0001 0001 xxxx xxxx */ + {&upd7810_device::XRI_B_xx, 3,11,11,L0|L1}, /* 12: 0111 0100 0001 0010 xxxx xxxx */ + {&upd7810_device::XRI_C_xx, 3,11,11,L0|L1}, /* 13: 0111 0100 0001 0011 xxxx xxxx */ + {&upd7810_device::XRI_D_xx, 3,11,11,L0|L1}, /* 14: 0111 0100 0001 0100 xxxx xxxx */ + {&upd7810_device::XRI_E_xx, 3,11,11,L0|L1}, /* 15: 0111 0100 0001 0101 xxxx xxxx */ + {&upd7810_device::XRI_H_xx, 3,11,11,L0|L1}, /* 16: 0111 0100 0001 0110 xxxx xxxx */ + {&upd7810_device::XRI_L_xx, 3,11,11,L0|L1}, /* 17: 0111 0100 0001 0111 xxxx xxxx */ + {&upd7810_device::ORI_V_xx, 3,11,11,L0|L1}, /* 18: 0111 0100 0001 1000 xxxx xxxx */ + {&upd7810_device::ORI_A_xx, 3,11,11,L0|L1}, /* 19: 0111 0100 0001 1001 xxxx xxxx */ + {&upd7810_device::ORI_B_xx, 3,11,11,L0|L1}, /* 1a: 0111 0100 0001 1010 xxxx xxxx */ + {&upd7810_device::ORI_C_xx, 3,11,11,L0|L1}, /* 1b: 0111 0100 0001 1011 xxxx xxxx */ + {&upd7810_device::ORI_D_xx, 3,11,11,L0|L1}, /* 1c: 0111 0100 0001 1100 xxxx xxxx */ + {&upd7810_device::ORI_E_xx, 3,11,11,L0|L1}, /* 1d: 0111 0100 0001 1101 xxxx xxxx */ + {&upd7810_device::ORI_H_xx, 3,11,11,L0|L1}, /* 1e: 0111 0100 0001 1110 xxxx xxxx */ + {&upd7810_device::ORI_L_xx, 3,11,11,L0|L1}, /* 1f: 0111 0100 0001 1111 xxxx xxxx */ + + {&upd7810_device::ADINC_V_xx, 3,11,11,L0|L1}, /* 20: 0111 0100 0010 0000 xxxx xxxx */ + {&upd7810_device::ADINC_A_xx, 3,11,11,L0|L1}, /* 21: 0111 0100 0010 0001 xxxx xxxx */ + {&upd7810_device::ADINC_B_xx, 3,11,11,L0|L1}, /* 22: 0111 0100 0010 0010 xxxx xxxx */ + {&upd7810_device::ADINC_C_xx, 3,11,11,L0|L1}, /* 23: 0111 0100 0010 0011 xxxx xxxx */ + {&upd7810_device::ADINC_D_xx, 3,11,11,L0|L1}, /* 24: 0111 0100 0010 0100 xxxx xxxx */ + {&upd7810_device::ADINC_E_xx, 3,11,11,L0|L1}, /* 25: 0111 0100 0010 0101 xxxx xxxx */ + {&upd7810_device::ADINC_H_xx, 3,11,11,L0|L1}, /* 26: 0111 0100 0010 0110 xxxx xxxx */ + {&upd7810_device::ADINC_L_xx, 3,11,11,L0|L1}, /* 27: 0111 0100 0010 0111 xxxx xxxx */ + {&upd7810_device::GTI_V_xx, 3,11,11,L0|L1}, /* 28: 0111 0100 0010 1000 xxxx xxxx */ + {&upd7810_device::GTI_A_xx, 3,11,11,L0|L1}, /* 29: 0111 0100 0010 1001 xxxx xxxx */ + {&upd7810_device::GTI_B_xx, 3,11,11,L0|L1}, /* 2a: 0111 0100 0010 1010 xxxx xxxx */ + {&upd7810_device::GTI_C_xx, 3,11,11,L0|L1}, /* 2b: 0111 0100 0010 1011 xxxx xxxx */ + {&upd7810_device::GTI_D_xx, 3,11,11,L0|L1}, /* 2c: 0111 0100 0010 1100 xxxx xxxx */ + {&upd7810_device::GTI_E_xx, 3,11,11,L0|L1}, /* 2d: 0111 0100 0010 1101 xxxx xxxx */ + {&upd7810_device::GTI_H_xx, 3,11,11,L0|L1}, /* 2e: 0111 0100 0010 1110 xxxx xxxx */ + {&upd7810_device::GTI_L_xx, 3,11,11,L0|L1}, /* 2f: 0111 0100 0010 1111 xxxx xxxx */ + + {&upd7810_device::SUINB_V_xx, 3,11,11,L0|L1}, /* 30: 0111 0100 0011 0000 xxxx xxxx */ + {&upd7810_device::SUINB_A_xx, 3,11,11,L0|L1}, /* 31: 0111 0100 0011 0001 xxxx xxxx */ + {&upd7810_device::SUINB_B_xx, 3,11,11,L0|L1}, /* 32: 0111 0100 0011 0010 xxxx xxxx */ + {&upd7810_device::SUINB_C_xx, 3,11,11,L0|L1}, /* 33: 0111 0100 0011 0011 xxxx xxxx */ + {&upd7810_device::SUINB_D_xx, 3,11,11,L0|L1}, /* 34: 0111 0100 0011 0100 xxxx xxxx */ + {&upd7810_device::SUINB_E_xx, 3,11,11,L0|L1}, /* 35: 0111 0100 0011 0101 xxxx xxxx */ + {&upd7810_device::SUINB_H_xx, 3,11,11,L0|L1}, /* 36: 0111 0100 0011 0110 xxxx xxxx */ + {&upd7810_device::SUINB_L_xx, 3,11,11,L0|L1}, /* 37: 0111 0100 0011 0111 xxxx xxxx */ + {&upd7810_device::LTI_V_xx, 3,11,11,L0|L1}, /* 38: 0111 0100 0011 1000 xxxx xxxx */ + {&upd7810_device::LTI_A_xx, 3,11,11,L0|L1}, /* 39: 0111 0100 0011 1001 xxxx xxxx */ + {&upd7810_device::LTI_B_xx, 3,11,11,L0|L1}, /* 3a: 0111 0100 0011 1010 xxxx xxxx */ + {&upd7810_device::LTI_C_xx, 3,11,11,L0|L1}, /* 3b: 0111 0100 0011 1011 xxxx xxxx */ + {&upd7810_device::LTI_D_xx, 3,11,11,L0|L1}, /* 3c: 0111 0100 0011 1100 xxxx xxxx */ + {&upd7810_device::LTI_E_xx, 3,11,11,L0|L1}, /* 3d: 0111 0100 0011 1101 xxxx xxxx */ + {&upd7810_device::LTI_H_xx, 3,11,11,L0|L1}, /* 3e: 0111 0100 0011 1110 xxxx xxxx */ + {&upd7810_device::LTI_L_xx, 3,11,11,L0|L1}, /* 3f: 0111 0100 0011 1111 xxxx xxxx */ + + {&upd7810_device::ADI_V_xx, 3,11,11,L0|L1}, /* 40: 0111 0100 0100 0000 xxxx xxxx */ + {&upd7810_device::ADI_A_xx, 3,11,11,L0|L1}, /* 41: 0111 0100 0100 0001 xxxx xxxx */ + {&upd7810_device::ADI_B_xx, 3,11,11,L0|L1}, /* 42: 0111 0100 0100 0010 xxxx xxxx */ + {&upd7810_device::ADI_C_xx, 3,11,11,L0|L1}, /* 43: 0111 0100 0100 0011 xxxx xxxx */ + {&upd7810_device::ADI_D_xx, 3,11,11,L0|L1}, /* 44: 0111 0100 0100 0100 xxxx xxxx */ + {&upd7810_device::ADI_E_xx, 3,11,11,L0|L1}, /* 45: 0111 0100 0100 0101 xxxx xxxx */ + {&upd7810_device::ADI_H_xx, 3,11,11,L0|L1}, /* 46: 0111 0100 0100 0110 xxxx xxxx */ + {&upd7810_device::ADI_L_xx, 3,11,11,L0|L1}, /* 47: 0111 0100 0100 0111 xxxx xxxx */ + {&upd7810_device::ONI_V_xx, 3,11,11,L0|L1}, /* 48: 0111 0100 0100 1000 xxxx xxxx */ + {&upd7810_device::ONI_A_xx, 3,11,11,L0|L1}, /* 49: 0111 0100 0100 1001 xxxx xxxx */ + {&upd7810_device::ONI_B_xx, 3,11,11,L0|L1}, /* 4a: 0111 0100 0100 1010 xxxx xxxx */ + {&upd7810_device::ONI_C_xx, 3,11,11,L0|L1}, /* 4b: 0111 0100 0100 1011 xxxx xxxx */ + {&upd7810_device::ONI_D_xx, 3,11,11,L0|L1}, /* 4c: 0111 0100 0100 1100 xxxx xxxx */ + {&upd7810_device::ONI_E_xx, 3,11,11,L0|L1}, /* 4d: 0111 0100 0100 1101 xxxx xxxx */ + {&upd7810_device::ONI_H_xx, 3,11,11,L0|L1}, /* 4e: 0111 0100 0100 1110 xxxx xxxx */ + {&upd7810_device::ONI_L_xx, 3,11,11,L0|L1}, /* 4f: 0111 0100 0100 1111 xxxx xxxx */ + + {&upd7810_device::ACI_V_xx, 3,11,11,L0|L1}, /* 50: 0111 0100 0101 0000 xxxx xxxx */ + {&upd7810_device::ACI_A_xx, 3,11,11,L0|L1}, /* 51: 0111 0100 0101 0001 xxxx xxxx */ + {&upd7810_device::ACI_B_xx, 3,11,11,L0|L1}, /* 52: 0111 0100 0101 0010 xxxx xxxx */ + {&upd7810_device::ACI_C_xx, 3,11,11,L0|L1}, /* 53: 0111 0100 0101 0011 xxxx xxxx */ + {&upd7810_device::ACI_D_xx, 3,11,11,L0|L1}, /* 54: 0111 0100 0101 0100 xxxx xxxx */ + {&upd7810_device::ACI_E_xx, 3,11,11,L0|L1}, /* 55: 0111 0100 0101 0101 xxxx xxxx */ + {&upd7810_device::ACI_H_xx, 3,11,11,L0|L1}, /* 56: 0111 0100 0101 0110 xxxx xxxx */ + {&upd7810_device::ACI_L_xx, 3,11,11,L0|L1}, /* 57: 0111 0100 0101 0111 xxxx xxxx */ + {&upd7810_device::OFFI_V_xx, 3,11,11,L0|L1}, /* 58: 0111 0100 0101 1000 xxxx xxxx */ + {&upd7810_device::OFFI_A_xx, 3,11,11,L0|L1}, /* 59: 0111 0100 0101 1001 xxxx xxxx */ + {&upd7810_device::OFFI_B_xx, 3,11,11,L0|L1}, /* 5a: 0111 0100 0101 1010 xxxx xxxx */ + {&upd7810_device::OFFI_C_xx, 3,11,11,L0|L1}, /* 5b: 0111 0100 0101 1011 xxxx xxxx */ + {&upd7810_device::OFFI_D_xx, 3,11,11,L0|L1}, /* 5c: 0111 0100 0101 1100 xxxx xxxx */ + {&upd7810_device::OFFI_E_xx, 3,11,11,L0|L1}, /* 5d: 0111 0100 0101 1101 xxxx xxxx */ + {&upd7810_device::OFFI_H_xx, 3,11,11,L0|L1}, /* 5e: 0111 0100 0101 1110 xxxx xxxx */ + {&upd7810_device::OFFI_L_xx, 3,11,11,L0|L1}, /* 5f: 0111 0100 0101 1111 xxxx xxxx */ + + {&upd7810_device::SUI_V_xx, 3,11,11,L0|L1}, /* 60: 0111 0100 0110 0000 xxxx xxxx */ + {&upd7810_device::SUI_A_xx, 3,11,11,L0|L1}, /* 61: 0111 0100 0110 0001 xxxx xxxx */ + {&upd7810_device::SUI_B_xx, 3,11,11,L0|L1}, /* 62: 0111 0100 0110 0010 xxxx xxxx */ + {&upd7810_device::SUI_C_xx, 3,11,11,L0|L1}, /* 63: 0111 0100 0110 0011 xxxx xxxx */ + {&upd7810_device::SUI_D_xx, 3,11,11,L0|L1}, /* 64: 0111 0100 0110 0100 xxxx xxxx */ + {&upd7810_device::SUI_E_xx, 3,11,11,L0|L1}, /* 65: 0111 0100 0110 0101 xxxx xxxx */ + {&upd7810_device::SUI_H_xx, 3,11,11,L0|L1}, /* 66: 0111 0100 0110 0110 xxxx xxxx */ + {&upd7810_device::SUI_L_xx, 3,11,11,L0|L1}, /* 67: 0111 0100 0110 0111 xxxx xxxx */ + {&upd7810_device::NEI_V_xx, 3,11,11,L0|L1}, /* 68: 0111 0100 0110 1000 xxxx xxxx */ + {&upd7810_device::NEI_A_xx, 3,11,11,L0|L1}, /* 69: 0111 0100 0110 1001 xxxx xxxx */ + {&upd7810_device::NEI_B_xx, 3,11,11,L0|L1}, /* 6a: 0111 0100 0110 1010 xxxx xxxx */ + {&upd7810_device::NEI_C_xx, 3,11,11,L0|L1}, /* 6b: 0111 0100 0110 1011 xxxx xxxx */ + {&upd7810_device::NEI_D_xx, 3,11,11,L0|L1}, /* 6c: 0111 0100 0110 1100 xxxx xxxx */ + {&upd7810_device::NEI_E_xx, 3,11,11,L0|L1}, /* 6d: 0111 0100 0110 1101 xxxx xxxx */ + {&upd7810_device::NEI_H_xx, 3,11,11,L0|L1}, /* 6e: 0111 0100 0110 1110 xxxx xxxx */ + {&upd7810_device::NEI_L_xx, 3,11,11,L0|L1}, /* 6f: 0111 0100 0110 1111 xxxx xxxx */ + + {&upd7810_device::SBI_V_xx, 3,11,11,L0|L1}, /* 70: 0111 0100 0111 0000 xxxx xxxx */ + {&upd7810_device::SBI_A_xx, 3,11,11,L0|L1}, /* 71: 0111 0100 0111 0001 xxxx xxxx */ + {&upd7810_device::SBI_B_xx, 3,11,11,L0|L1}, /* 72: 0111 0100 0111 0010 xxxx xxxx */ + {&upd7810_device::SBI_C_xx, 3,11,11,L0|L1}, /* 73: 0111 0100 0111 0011 xxxx xxxx */ + {&upd7810_device::SBI_D_xx, 3,11,11,L0|L1}, /* 74: 0111 0100 0111 0100 xxxx xxxx */ + {&upd7810_device::SBI_E_xx, 3,11,11,L0|L1}, /* 75: 0111 0100 0111 0101 xxxx xxxx */ + {&upd7810_device::SBI_H_xx, 3,11,11,L0|L1}, /* 76: 0111 0100 0111 0110 xxxx xxxx */ + {&upd7810_device::SBI_L_xx, 3,11,11,L0|L1}, /* 77: 0111 0100 0111 0111 xxxx xxxx */ + {&upd7810_device::EQI_V_xx, 3,11,11,L0|L1}, /* 78: 0111 0100 0111 1000 xxxx xxxx */ + {&upd7810_device::EQI_A_xx, 3,11,11,L0|L1}, /* 79: 0111 0100 0111 1001 xxxx xxxx */ + {&upd7810_device::EQI_B_xx, 3,11,11,L0|L1}, /* 7a: 0111 0100 0111 1010 xxxx xxxx */ + {&upd7810_device::EQI_C_xx, 3,11,11,L0|L1}, /* 7b: 0111 0100 0111 1011 xxxx xxxx */ + {&upd7810_device::EQI_D_xx, 3,11,11,L0|L1}, /* 7c: 0111 0100 0111 1100 xxxx xxxx */ + {&upd7810_device::EQI_E_xx, 3,11,11,L0|L1}, /* 7d: 0111 0100 0111 1101 xxxx xxxx */ + {&upd7810_device::EQI_H_xx, 3,11,11,L0|L1}, /* 7e: 0111 0100 0111 1110 xxxx xxxx */ + {&upd7810_device::EQI_L_xx, 3,11,11,L0|L1}, /* 7f: 0111 0100 0111 1111 xxxx xxxx */ + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 80: 0111 0100 1000 0000 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 81: 0111 0100 1000 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 82: 0111 0100 1000 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 83: 0111 0100 1000 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 84: 0111 0100 1000 0100 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 85: 0111 0100 1000 0101 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 86: 0111 0100 1000 0110 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 87: 0111 0100 1000 0111 */ + {&upd7810_device::ANAW_wa, 3,14,11,L0|L1}, /* 88: 0111 0100 1000 1000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 89: 0111 0100 1000 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8a: 0111 0100 1000 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8b: 0111 0100 1000 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 8c: 0111 0100 1000 1100 */ + {&upd7810_device::DAN_EA_BC, 2,11,11,L0|L1}, /* 8d: 0111 0100 1000 1101 */ + {&upd7810_device::DAN_EA_DE, 2,11,11,L0|L1}, /* 8e: 0111 0100 1000 1110 */ + {&upd7810_device::DAN_EA_HL, 2,11,11,L0|L1}, /* 8f: 0111 0100 1000 1111 */ + + {&upd7810_device::XRAW_wa, 3,14,11,L0|L1}, /* 90: 0111 0100 1001 0000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 91: 0111 0100 1001 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 92: 0111 0100 1001 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 93: 0111 0100 1001 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 94: 0111 0100 1001 0100 */ + {&upd7810_device::DXR_EA_BC, 2,11,11,L0|L1}, /* 95: 0111 0100 1001 0101 */ + {&upd7810_device::DXR_EA_DE, 2,11,11,L0|L1}, /* 96: 0111 0100 1001 0110 */ + {&upd7810_device::DXR_EA_HL, 2,11,11,L0|L1}, /* 97: 0111 0100 1001 0111 */ + {&upd7810_device::ORAW_wa, 3,14,11,L0|L1}, /* 98: 0111 0100 1001 1000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 99: 0111 0100 1001 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9a: 0111 0100 1001 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9b: 0111 0100 1001 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 9c: 0111 0100 1001 1100 */ + {&upd7810_device::DOR_EA_BC, 2,11,11,L0|L1}, /* 9d: 0111 0100 1001 1101 */ + {&upd7810_device::DOR_EA_DE, 2,11,11,L0|L1}, /* 9e: 0111 0100 1001 1110 */ + {&upd7810_device::DOR_EA_HL, 2,11,11,L0|L1}, /* 9f: 0111 0100 1001 1111 */ + + {&upd7810_device::ADDNCW_wa, 3,14,11,L0|L1}, /* a0: 0111 0100 1010 0000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a1: 0111 0100 1010 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a2: 0111 0100 1010 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a3: 0111 0100 1010 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a4: 0111 0100 1010 0100 */ + {&upd7810_device::DADDNC_EA_BC, 2,11,11,L0|L1}, /* a5: 0111 0100 1010 0101 */ + {&upd7810_device::DADDNC_EA_DE, 2,11,11,L0|L1}, /* a6: 0111 0100 1010 0110 */ + {&upd7810_device::DADDNC_EA_HL, 2,11,11,L0|L1}, /* a7: 0111 0100 1010 0111 */ + {&upd7810_device::GTAW_wa, 3,14,11,L0|L1}, /* a8: 0111 0100 1010 1000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* a9: 0111 0100 1010 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* aa: 0111 0100 1010 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ab: 0111 0100 1010 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ac: 0111 0100 1010 1100 */ + {&upd7810_device::DGT_EA_BC, 2,11,11,L0|L1}, /* ad: 0111 0100 1010 1101 */ + {&upd7810_device::DGT_EA_DE, 2,11,11,L0|L1}, /* ae: 0111 0100 1010 1110 */ + {&upd7810_device::DGT_EA_HL, 2,11,11,L0|L1}, /* af: 0111 0100 1010 1111 */ + + {&upd7810_device::SUBNBW_wa, 3,14,11,L0|L1}, /* b0: 0111 0100 1011 0000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b1: 0111 0100 1011 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b2: 0111 0100 1011 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b3: 0111 0100 1011 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b4: 0111 0100 1011 0100 */ + {&upd7810_device::DSUBNB_EA_BC, 2,11,11,L0|L1}, /* b5: 0111 0100 1011 0101 */ + {&upd7810_device::DSUBNB_EA_DE, 2,11,11,L0|L1}, /* b6: 0111 0100 1011 0110 */ + {&upd7810_device::DSUBNB_EA_HL, 2,11,11,L0|L1}, /* b7: 0111 0100 1011 0111 */ + {&upd7810_device::LTAW_wa, 3,14,11,L0|L1}, /* b8: 0111 0100 1011 1000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* b9: 0111 0100 1011 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ba: 0111 0100 1011 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bb: 0111 0100 1011 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* bc: 0111 0100 1011 1100 */ + {&upd7810_device::DLT_EA_BC, 2,11,11,L0|L1}, /* bd: 0111 0100 1011 1101 */ + {&upd7810_device::DLT_EA_DE, 2,11,11,L0|L1}, /* be: 0111 0100 1011 1110 */ + {&upd7810_device::DLT_EA_HL, 2,11,11,L0|L1}, /* bf: 0111 0100 1011 1111 */ + + {&upd7810_device::ADDW_wa, 3,14,11,L0|L1}, /* c0: 0111 0100 1100 0000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c1: 0111 0100 1100 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c2: 0111 0100 1100 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c3: 0111 0100 1100 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c4: 0111 0100 1100 0100 */ + {&upd7810_device::DADD_EA_BC, 2,11,11,L0|L1}, /* c5: 0111 0100 1100 0101 */ + {&upd7810_device::DADD_EA_DE, 2,11,11,L0|L1}, /* c6: 0111 0100 1100 0110 */ + {&upd7810_device::DADD_EA_HL, 2,11,11,L0|L1}, /* c7: 0111 0100 1100 0111 */ + {&upd7810_device::ONAW_wa, 3,14,11,L0|L1}, /* c8: 0111 0100 1100 1000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* c9: 0111 0100 1100 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ca: 0111 0100 1100 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* cb: 0111 0100 1100 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* cc: 0111 0100 1100 1100 */ + {&upd7810_device::DON_EA_BC, 2,11,11,L0|L1}, /* cd: 0111 0100 1100 1101 */ + {&upd7810_device::DON_EA_DE, 2,11,11,L0|L1}, /* ce: 0111 0100 1100 1110 */ + {&upd7810_device::DON_EA_HL, 2,11,11,L0|L1}, /* cf: 0111 0100 1100 1111 */ + + {&upd7810_device::ADCW_wa, 3,14,11,L0|L1}, /* d0: 0111 0100 1101 0000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d1: 0111 0100 1101 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d2: 0111 0100 1101 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d3: 0111 0100 1101 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d4: 0111 0100 1101 0100 */ + {&upd7810_device::DADC_EA_BC, 2,11,11,L0|L1}, /* d5: 0111 0100 1101 0101 */ + {&upd7810_device::DADC_EA_DE, 2,11,11,L0|L1}, /* d6: 0111 0100 1101 0110 */ + {&upd7810_device::DADC_EA_HL, 2,11,11,L0|L1}, /* d7: 0111 0100 1101 0111 */ + {&upd7810_device::OFFAW_wa, 3,14,11,L0|L1}, /* d8: 0111 0100 1101 1000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* d9: 0111 0100 1101 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* da: 0111 0100 1101 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* db: 0111 0100 1101 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* dc: 0111 0100 1101 1100 */ + {&upd7810_device::DOFF_EA_BC, 2,11,11,L0|L1}, /* dd: 0111 0100 1101 1101 */ + {&upd7810_device::DOFF_EA_DE, 2,11,11,L0|L1}, /* de: 0111 0100 1101 1110 */ + {&upd7810_device::DOFF_EA_HL, 2,11,11,L0|L1}, /* df: 0111 0100 1101 1111 */ + + {&upd7810_device::SUBW_wa, 3,14,11,L0|L1}, /* e0: 0111 0100 1110 0000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e1: 0111 0100 1110 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e2: 0111 0100 1110 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e3: 0111 0100 1110 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e4: 0111 0100 1110 0100 */ + {&upd7810_device::DSUB_EA_BC, 2,11,11,L0|L1}, /* e5: 0111 0100 1110 0101 */ + {&upd7810_device::DSUB_EA_DE, 2,11,11,L0|L1}, /* e6: 0111 0100 1110 0110 */ + {&upd7810_device::DSUB_EA_HL, 2,11,11,L0|L1}, /* e7: 0111 0100 1110 0111 */ + {&upd7810_device::NEAW_wa, 3,14,11,L0|L1}, /* e8: 0111 0100 1110 1000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* e9: 0111 0100 1110 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ea: 0111 0100 1110 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* eb: 0111 0100 1110 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* ec: 0111 0100 1110 1100 */ + {&upd7810_device::DNE_EA_BC, 2,11,11,L0|L1}, /* ed: 0111 0100 1110 1101 */ + {&upd7810_device::DNE_EA_DE, 2,11,11,L0|L1}, /* ee: 0111 0100 1110 1110 */ + {&upd7810_device::DNE_EA_HL, 2,11,11,L0|L1}, /* ef: 0111 0100 1110 1111 */ + + {&upd7810_device::SBBW_wa, 3,14,11,L0|L1}, /* f0: 0111 0100 1111 0000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f1: 0111 0100 1111 0001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f2: 0111 0100 1111 0010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f3: 0111 0100 1111 0011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f4: 0111 0100 1111 0100 */ + {&upd7810_device::DSBB_EA_BC, 2,11,11,L0|L1}, /* f5: 0111 0100 1111 0101 */ + {&upd7810_device::DSBB_EA_DE, 2,11,11,L0|L1}, /* f6: 0111 0100 1111 0110 */ + {&upd7810_device::DSBB_EA_HL, 2,11,11,L0|L1}, /* f7: 0111 0100 1111 0111 */ + {&upd7810_device::EQAW_wa, 3,14,11,L0|L1}, /* f8: 0111 0100 1111 1000 oooo oooo */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* f9: 0111 0100 1111 1001 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* fa: 0111 0100 1111 1010 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* fb: 0111 0100 1111 1011 */ + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* fc: 0111 0100 1111 1100 */ + {&upd7810_device::DEQ_EA_BC, 2,11,11,L0|L1}, /* fd: 0111 0100 1111 1101 */ + {&upd7810_device::DEQ_EA_DE, 2,11,11,L0|L1}, /* fe: 0111 0100 1111 1110 */ + {&upd7810_device::DEQ_EA_HL, 2,11,11,L0|L1} /* ff: 0111 0100 1111 1111 */ }; /* main opcodes */ -static const struct opcode_s opXX_7810[256] = +const struct upd7810_device::opcode_s upd7810_device::s_opXX_7810[256] = { - {NOP, 1, 4, 4,L0|L1}, /* 00: 0000 0000 */ - {LDAW_wa, 2,10,10,L0|L1}, /* 01: 0000 0001 oooo oooo */ - {INX_SP, 1, 7, 7,L0|L1}, /* 02: 0000 0010 */ - {DCX_SP, 1, 7, 7,L0|L1}, /* 03: 0000 0011 */ - {LXI_S_w, 3,10,10,L0|L1}, /* 04: 0000 0100 llll llll hhhh hhhh */ - {ANIW_wa_xx, 3,19,19,L0|L1}, /* 05: 0000 0101 oooo oooo xxxx xxxx */ - {illegal, 1, 4, 4,L0|L1}, /* 06: */ - {ANI_A_xx, 2, 7, 7,L0|L1}, /* 07: 0000 0111 xxxx xxxx */ - {MOV_A_EAH, 1, 4, 4,L0|L1}, /* 08: 0000 1000 */ - {MOV_A_EAL, 1, 4, 4,L0|L1}, /* 09: 0000 1001 */ - {MOV_A_B, 1, 4, 4,L0|L1}, /* 0a: 0000 1010 */ - {MOV_A_C, 1, 4, 4,L0|L1}, /* 0b: 0000 1011 */ - {MOV_A_D, 1, 4, 4,L0|L1}, /* 0c: 0000 1100 */ - {MOV_A_E, 1, 4, 4,L0|L1}, /* 0d: 0000 1101 */ - {MOV_A_H, 1, 4, 4,L0|L1}, /* 0e: 0000 1110 */ - {MOV_A_L, 1, 4, 4,L0|L1}, /* 0f: 0000 1111 */ - - {EXA, 1, 4, 4,L0|L1}, /* 10: 0001 0000 */ - {EXX, 1, 4, 4,L0|L1}, /* 11: 0001 0001 */ - {INX_BC, 1, 7, 7,L0|L1}, /* 12: 0001 0010 */ - {DCX_BC, 1, 7, 7,L0|L1}, /* 13: 0001 0011 */ - {LXI_B_w, 3,10,10,L0|L1}, /* 14: 0001 0100 llll llll hhhh hhhh */ - {ORIW_wa_xx, 3,19,19,L0|L1}, /* 15: 0001 0101 oooo oooo xxxx xxxx */ - {XRI_A_xx, 2, 7, 7,L0|L1}, /* 16: 0001 0110 xxxx xxxx */ - {ORI_A_xx, 2, 7, 7,L0|L1}, /* 17: 0001 0111 xxxx xxxx */ - {MOV_EAH_A, 1, 4, 4,L0|L1}, /* 18: 0001 1000 */ - {MOV_EAL_A, 1, 4, 4,L0|L1}, /* 19: 0001 1001 */ - {MOV_B_A, 1, 4, 4,L0|L1}, /* 1a: 0001 1010 */ - {MOV_C_A, 1, 4, 4,L0|L1}, /* 1b: 0001 1011 */ - {MOV_D_A, 1, 4, 4,L0|L1}, /* 1c: 0001 1100 */ - {MOV_E_A, 1, 4, 4,L0|L1}, /* 1d: 0001 1101 */ - {MOV_H_A, 1, 4, 4,L0|L1}, /* 1e: 0001 1110 */ - {MOV_L_A, 1, 4, 4,L0|L1}, /* 1f: 0001 1111 */ - - {INRW_wa, 2,16,16,L0|L1}, /* 20: 0010 0000 oooo oooo */ - {JB, 1, 4, 4,L0|L1}, /* 21: 0010 0001 */ - {INX_DE, 1, 7, 7,L0|L1}, /* 22: 0010 0010 */ - {DCX_DE, 1, 7, 7,L0|L1}, /* 23: 0010 0011 */ - {LXI_D_w, 3,10,10,L0|L1}, /* 24: 0010 0100 llll llll hhhh hhhh */ - {GTIW_wa_xx, 3,19,19,L0|L1}, /* 25: 0010 0101 oooo oooo xxxx xxxx */ - {ADINC_A_xx, 2, 7, 7,L0|L1}, /* 26: 0010 0110 xxxx xxxx */ - {GTI_A_xx, 2, 7, 7,L0|L1}, /* 27: 0010 0111 xxxx xxxx */ - {illegal, 1, 4, 4,L0|L1}, /* 28: */ - {LDAX_B, 2, 7, 7,L0|L1}, /* 29: 0010 1001 dddd dddd */ - {LDAX_D, 2, 7, 7,L0|L1}, /* 2a: 0010 1010 dddd dddd */ - {LDAX_H, 2, 7, 7,L0|L1}, /* 2b: 0010 1011 dddd dddd */ - {LDAX_Dp, 2, 7, 7,L0|L1}, /* 2c: 0010 1100 dddd dddd */ - {LDAX_Hp, 2, 7, 7,L0|L1}, /* 2d: 0010 1101 dddd dddd */ - {LDAX_Dm, 2, 7, 7,L0|L1}, /* 2e: 0010 1110 dddd dddd */ - {LDAX_Hm, 2, 7, 7,L0|L1}, /* 2f: 0010 1111 dddd dddd */ - - {DCRW_wa, 2,16,16,L0|L1}, /* 30: 0011 0000 oooo oooo */ - {BLOCK, 1,13,13,L0|L1}, /* 31: 0011 0001 */ /* 7810 */ - {INX_HL, 1, 7, 7,L0|L1}, /* 32: 0011 0010 */ - {DCX_HL, 1, 7, 7,L0|L1}, /* 33: 0011 0011 */ - {LXI_H_w, 3,10,10, L1}, /* 34: 0011 0100 llll llll hhhh hhhh */ - {LTIW_wa_xx, 3,19,19,L0|L1}, /* 35: 0011 0101 oooo oooo xxxx xxxx */ - {SUINB_A_xx, 2, 7, 7,L0|L1}, /* 36: 0011 0110 xxxx xxxx */ - {LTI_A_xx, 2, 7, 7,L0|L1}, /* 37: 0011 0111 xxxx xxxx */ - {illegal, 1, 4, 4,L0|L1}, /* 38: */ - {STAX_B, 2, 7, 7,L0|L1}, /* 39: 0011 1001 dddd dddd */ - {STAX_D, 2, 7, 7,L0|L1}, /* 3a: 0011 1010 dddd dddd */ - {STAX_H, 2, 7, 7,L0|L1}, /* 3b: 0011 1011 dddd dddd */ - {STAX_Dp, 2, 7, 7,L0|L1}, /* 3c: 0011 1100 dddd dddd */ - {STAX_Hp, 2, 7, 7,L0|L1}, /* 3d: 0011 1101 dddd dddd */ - {STAX_Dm, 2, 7, 7,L0|L1}, /* 3e: 0011 1110 dddd dddd */ - {STAX_Hm, 2, 7, 7,L0|L1}, /* 3f: 0011 1111 dddd dddd */ - - {CALL_w, 3,16,16,L0|L1}, /* 40: 0100 0000 llll llll hhhh hhhh */ - {INR_A, 1, 4, 4,L0|L1}, /* 41: 0100 0001 */ - {INR_B, 1, 4, 4,L0|L1}, /* 42: 0100 0010 */ - {INR_C, 1, 4, 4,L0|L1}, /* 43: 0100 0011 */ - {LXI_EA_s, 3,10,10,L0|L1}, /* 44: 0100 0100 llll llll hhhh hhhh */ - {ONIW_wa_xx, 3,19,19,L0|L1}, /* 45: 0100 0101 oooo oooo xxxx xxxx */ - {ADI_A_xx, 2, 7, 7,L0|L1}, /* 46: 0100 0110 xxxx xxxx */ - {ONI_A_xx, 2, 7, 7,L0|L1}, /* 47: 0100 0111 xxxx xxxx */ - {PRE_48, 1, 0, 0,L0|L1}, /* 48: prefix */ - {MVIX_BC_xx, 2,10,10,L0|L1}, /* 49: 0100 1001 xxxx xxxx */ - {MVIX_DE_xx, 2,10,10,L0|L1}, /* 4a: 0100 1010 xxxx xxxx */ - {MVIX_HL_xx, 2,10,10,L0|L1}, /* 4b: 0100 1011 xxxx xxxx */ - {PRE_4C, 1, 0, 0,L0|L1}, /* 4c: prefix */ - {PRE_4D, 1, 4, 4,L0|L1}, /* 4d: prefix */ - {JRE, 2,10,10,L0|L1}, /* 4e: 0100 111d dddd dddd */ - {JRE, 2,10,10,L0|L1}, /* 4f: 0100 111d dddd dddd */ - - {EXH, 1, 4, 4,L0|L1}, /* 50: 0101 0000 */ /* 7810 */ - {DCR_A, 1, 4, 4,L0|L1}, /* 51: 0101 0001 */ - {DCR_B, 1, 4, 4,L0|L1}, /* 52: 0101 0010 */ - {DCR_C, 1, 4, 4,L0|L1}, /* 53: 0101 0011 */ - {JMP_w, 3,10,10,L0|L1}, /* 54: 0101 0100 llll llll hhhh hhhh */ - {OFFIW_wa_xx, 3,19,19,L0|L1}, /* 55: 0101 0101 oooo oooo xxxx xxxx */ - {ACI_A_xx, 2, 7, 7,L0|L1}, /* 56: 0101 0110 xxxx xxxx */ - {OFFI_A_xx, 2, 7, 7,L0|L1}, /* 57: 0101 0111 xxxx xxxx */ - {BIT_0_wa, 2,10,10,L0|L1}, /* 58: 0101 1000 oooo oooo */ /* 7810 */ - {BIT_1_wa, 2,10,10,L0|L1}, /* 59: 0101 1001 oooo oooo */ /* 7810 */ - {BIT_2_wa, 2,10,10,L0|L1}, /* 5a: 0101 1010 oooo oooo */ /* 7810 */ - {BIT_3_wa, 2,10,10,L0|L1}, /* 5b: 0101 1011 oooo oooo */ /* 7810 */ - {BIT_4_wa, 2,10,10,L0|L1}, /* 5c: 0101 1100 oooo oooo */ /* 7810 */ - {BIT_5_wa, 2,10,10,L0|L1}, /* 5d: 0101 1101 oooo oooo */ /* 7810 */ - {BIT_6_wa, 2,10,10,L0|L1}, /* 5e: 0101 1110 oooo oooo */ /* 7810 */ - {BIT_7_wa, 2,10,10,L0|L1}, /* 5f: 0101 1111 oooo oooo */ /* 7810 */ - - {PRE_60, 1, 0, 0,L0|L1}, /* 60: */ - {DAA, 1, 4, 4,L0|L1}, /* 61: 0110 0001 */ - {RETI, 1,13,13,L0|L1}, /* 62: 0110 0010 */ - {STAW_wa, 2,10,10,L0|L1}, /* 63: 0110 0011 oooo oooo */ - {PRE_64, 1, 0, 0,L0|L1}, /* 64: */ - {NEIW_wa_xx, 3,19,19,L0|L1}, /* 65: 0110 0101 oooo oooo xxxx xxxx */ - {SUI_A_xx, 2, 7, 7,L0|L1}, /* 66: 0110 0110 xxxx xxxx */ - {NEI_A_xx, 2, 7, 7,L0|L1}, /* 67: 0110 0111 xxxx xxxx */ - {MVI_V_xx, 2, 7, 7,L0|L1}, /* 68: 0110 1000 xxxx xxxx */ - {MVI_A_xx, 2, 7, 7,L0 }, /* 69: 0110 1001 xxxx xxxx */ - {MVI_B_xx, 2, 7, 7,L0|L1}, /* 6a: 0110 1010 xxxx xxxx */ - {MVI_C_xx, 2, 7, 7,L0|L1}, /* 6b: 0110 1011 xxxx xxxx */ - {MVI_D_xx, 2, 7, 7,L0|L1}, /* 6c: 0110 1100 xxxx xxxx */ - {MVI_E_xx, 2, 7, 7,L0|L1}, /* 6d: 0110 1101 xxxx xxxx */ - {MVI_H_xx, 2, 7, 7,L0|L1}, /* 6e: 0110 1110 xxxx xxxx */ - {MVI_L_xx, 2, 7, 7, L1}, /* 6f: 0110 1111 xxxx xxxx */ - - {PRE_70, 1, 0, 0,L0|L1}, /* 70: */ - {MVIW_wa_xx, 3,13,13,L0|L1}, /* 71: 0111 0001 oooo oooo xxxx xxxx */ - {SOFTI, 1,16,16,L0|L1}, /* 72: 0111 0010 */ - {illegal, 1, 0, 0,L0|L1}, /* 73: */ - {PRE_74, 1, 0, 0,L0|L1}, /* 74: prefix */ - {EQIW_wa_xx, 3,19,19,L0|L1}, /* 75: 0111 0101 oooo oooo xxxx xxxx */ - {SBI_A_xx, 2, 7, 7,L0|L1}, /* 76: 0111 0110 xxxx xxxx */ - {EQI_A_xx, 2, 7, 7,L0|L1}, /* 77: 0111 0111 xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 78: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 79: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7a: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7b: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7c: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7d: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7e: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7f: 0111 1xxx xxxx xxxx */ - - {CALT, 1,16,16,L0|L1}, /* 80: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 81: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 82: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 83: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 84: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 85: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 86: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 87: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 88: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 89: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8a: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8b: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8c: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8d: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8e: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8f: 100x xxxx */ - - {CALT, 1,16,16,L0|L1}, /* 90: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 91: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 92: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 93: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 94: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 95: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 96: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 97: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 98: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 99: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9a: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9b: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9c: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9d: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9e: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9f: 100x xxxx */ - - {POP_VA, 1,10,10,L0|L1}, /* a0: 1010 0000 */ - {POP_BC, 1,10,10,L0|L1}, /* a1: 1010 0001 */ - {POP_DE, 1,10,10,L0|L1}, /* a2: 1010 0010 */ - {POP_HL, 1,10,10,L0|L1}, /* a3: 1010 0011 */ - {POP_EA, 1,10,10,L0|L1}, /* a4: 1010 0100 */ - {DMOV_EA_BC, 1, 4, 4,L0|L1}, /* a5: 1010 0101 */ - {DMOV_EA_DE, 1, 4, 4,L0|L1}, /* a6: 1010 0110 */ - {DMOV_EA_HL, 1, 4, 4,L0|L1}, /* a7: 1010 0111 */ - {INX_EA, 1, 7, 7,L0|L1}, /* a8: 1010 1000 */ - {DCX_EA, 1, 7, 7,L0|L1}, /* a9: 1010 1001 */ - {EI, 1, 4, 4,L0|L1}, /* aa: 1010 1010 */ - {LDAX_D_xx, 2, 7, 7,L0|L1}, /* ab: 1010 1011 dddd dddd */ - {LDAX_H_A, 1, 7, 7,L0|L1}, /* ac: 1010 1100 */ - {LDAX_H_B, 1, 7, 7,L0|L1}, /* ad: 1010 1101 */ - {LDAX_H_EA, 1, 7, 7,L0|L1}, /* ae: 1010 1110 */ - {LDAX_H_xx, 2, 7, 7,L0|L1}, /* af: 1010 1111 dddd dddd */ - - {PUSH_VA, 1,13,13,L0|L1}, /* b0: 1011 0000 */ - {PUSH_BC, 1,13,13,L0|L1}, /* b1: 1011 0001 */ - {PUSH_DE, 1,13,13,L0|L1}, /* b2: 1011 0010 */ - {PUSH_HL, 1,13,13,L0|L1}, /* b3: 1011 0011 */ - {PUSH_EA, 1,13,13,L0|L1}, /* b4: 1011 0100 */ - {DMOV_BC_EA, 1, 4, 4,L0|L1}, /* b5: 1011 0101 */ - {DMOV_DE_EA, 1, 4, 4,L0|L1}, /* b6: 1011 0110 */ - {DMOV_HL_EA, 1, 4, 4,L0|L1}, /* b7: 1011 0111 */ - {RET, 1,10,10,L0|L1}, /* b8: 1011 1000 */ - {RETS, 1,10,10,L0|L1}, /* b9: 1011 1001 */ - {DI, 1, 4, 4,L0|L1}, /* ba: 1011 1010 */ - {STAX_D_xx, 2, 7, 7,L0|L1}, /* bb: 1011 1011 dddd dddd */ - {STAX_H_A, 1, 7, 7,L0|L1}, /* bc: 1011 1100 */ - {STAX_H_B, 1, 7, 7,L0|L1}, /* bd: 1011 1101 */ - {STAX_H_EA, 1, 7, 7,L0|L1}, /* be: 1011 1110 */ - {STAX_H_xx, 2, 7, 7,L0|L1}, /* bf: 1011 1111 dddd dddd */ - - {JR, 1,10,10,L0|L1}, /* c0: 1100 0000 */ - {JR, 1,10,10,L0|L1}, /* c1: 1100 0001 */ - {JR, 1,10,10,L0|L1}, /* c2: 1100 0010 */ - {JR, 1,10,10,L0|L1}, /* c3: 1100 0011 */ - {JR, 1,10,10,L0|L1}, /* c4: 1100 0100 */ - {JR, 1,10,10,L0|L1}, /* c5: 1100 0101 */ - {JR, 1,10,10,L0|L1}, /* c6: 1100 0110 */ - {JR, 1,10,10,L0|L1}, /* c7: 1100 0111 */ - {JR, 1,10,10,L0|L1}, /* c8: 1100 1000 */ - {JR, 1,10,10,L0|L1}, /* c9: 1100 1001 */ - {JR, 1,10,10,L0|L1}, /* ca: 1100 1010 */ - {JR, 1,10,10,L0|L1}, /* cb: 1100 1011 */ - {JR, 1,10,10,L0|L1}, /* cc: 1100 1100 */ - {JR, 1,10,10,L0|L1}, /* cd: 1100 1101 */ - {JR, 1,10,10,L0|L1}, /* ce: 1100 1110 */ - {JR, 1,10,10,L0|L1}, /* cf: 1100 1111 */ - - {JR, 1,10,10,L0|L1}, /* d0: 1101 0000 */ - {JR, 1,10,10,L0|L1}, /* d1: 1101 0001 */ - {JR, 1,10,10,L0|L1}, /* d2: 1101 0010 */ - {JR, 1,10,10,L0|L1}, /* d3: 1101 0011 */ - {JR, 1,10,10,L0|L1}, /* d4: 1101 0100 */ - {JR, 1,10,10,L0|L1}, /* d5: 1101 0101 */ - {JR, 1,10,10,L0|L1}, /* d6: 1101 0110 */ - {JR, 1,10,10,L0|L1}, /* d7: 1101 0111 */ - {JR, 1,10,10,L0|L1}, /* d8: 1101 1000 */ - {JR, 1,10,10,L0|L1}, /* d9: 1101 1001 */ - {JR, 1,10,10,L0|L1}, /* da: 1101 1010 */ - {JR, 1,10,10,L0|L1}, /* db: 1101 1011 */ - {JR, 1,10,10,L0|L1}, /* dc: 1101 1100 */ - {JR, 1,10,10,L0|L1}, /* dd: 1101 1101 */ - {JR, 1,10,10,L0|L1}, /* de: 1101 1110 */ - {JR, 1,10,10,L0|L1}, /* df: 1101 1111 */ - - {JR, 1,10,10,L0|L1}, /* e0: 1110 0000 */ - {JR, 1,10,10,L0|L1}, /* e1: 1110 0001 */ - {JR, 1,10,10,L0|L1}, /* e2: 1110 0010 */ - {JR, 1,10,10,L0|L1}, /* e3: 1110 0011 */ - {JR, 1,10,10,L0|L1}, /* e4: 1110 0100 */ - {JR, 1,10,10,L0|L1}, /* e5: 1110 0101 */ - {JR, 1,10,10,L0|L1}, /* e6: 1110 0110 */ - {JR, 1,10,10,L0|L1}, /* e7: 1110 0111 */ - {JR, 1,10,10,L0|L1}, /* e8: 1110 1000 */ - {JR, 1,10,10,L0|L1}, /* e9: 1110 1001 */ - {JR, 1,10,10,L0|L1}, /* ea: 1110 1010 */ - {JR, 1,10,10,L0|L1}, /* eb: 1110 1011 */ - {JR, 1,10,10,L0|L1}, /* ec: 1110 1100 */ - {JR, 1,10,10,L0|L1}, /* ed: 1110 1101 */ - {JR, 1,10,10,L0|L1}, /* ee: 1110 1110 */ - {JR, 1,10,10,L0|L1}, /* ef: 1110 1111 */ - - {JR, 1,10,10,L0|L1}, /* f0: 1111 0000 */ - {JR, 1,10,10,L0|L1}, /* f1: 1111 0001 */ - {JR, 1,10,10,L0|L1}, /* f2: 1111 0010 */ - {JR, 1,10,10,L0|L1}, /* f3: 1111 0011 */ - {JR, 1,10,10,L0|L1}, /* f4: 1111 0100 */ - {JR, 1,10,10,L0|L1}, /* f5: 1111 0101 */ - {JR, 1,10,10,L0|L1}, /* f6: 1111 0110 */ - {JR, 1,10,10,L0|L1}, /* f7: 1111 0111 */ - {JR, 1,10,10,L0|L1}, /* f8: 1111 1000 */ - {JR, 1,10,10,L0|L1}, /* f9: 1111 1001 */ - {JR, 1,10,10,L0|L1}, /* fa: 1111 1010 */ - {JR, 1,10,10,L0|L1}, /* fb: 1111 1011 */ - {JR, 1,10,10,L0|L1}, /* fc: 1111 1100 */ - {JR, 1,10,10,L0|L1}, /* fd: 1111 1101 */ - {JR, 1,10,10,L0|L1}, /* fe: 1111 1110 */ - {JR, 1,10,10,L0|L1} /* ff: 1111 1111 */ + {&upd7810_device::NOP, 1, 4, 4,L0|L1}, /* 00: 0000 0000 */ + {&upd7810_device::LDAW_wa, 2,10,10,L0|L1}, /* 01: 0000 0001 oooo oooo */ + {&upd7810_device::INX_SP, 1, 7, 7,L0|L1}, /* 02: 0000 0010 */ + {&upd7810_device::DCX_SP, 1, 7, 7,L0|L1}, /* 03: 0000 0011 */ + {&upd7810_device::LXI_S_w, 3,10,10,L0|L1}, /* 04: 0000 0100 llll llll hhhh hhhh */ + {&upd7810_device::ANIW_wa_xx, 3,19,19,L0|L1}, /* 05: 0000 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, /* 06: */ + {&upd7810_device::ANI_A_xx, 2, 7, 7,L0|L1}, /* 07: 0000 0111 xxxx xxxx */ + {&upd7810_device::MOV_A_EAH, 1, 4, 4,L0|L1}, /* 08: 0000 1000 */ + {&upd7810_device::MOV_A_EAL, 1, 4, 4,L0|L1}, /* 09: 0000 1001 */ + {&upd7810_device::MOV_A_B, 1, 4, 4,L0|L1}, /* 0a: 0000 1010 */ + {&upd7810_device::MOV_A_C, 1, 4, 4,L0|L1}, /* 0b: 0000 1011 */ + {&upd7810_device::MOV_A_D, 1, 4, 4,L0|L1}, /* 0c: 0000 1100 */ + {&upd7810_device::MOV_A_E, 1, 4, 4,L0|L1}, /* 0d: 0000 1101 */ + {&upd7810_device::MOV_A_H, 1, 4, 4,L0|L1}, /* 0e: 0000 1110 */ + {&upd7810_device::MOV_A_L, 1, 4, 4,L0|L1}, /* 0f: 0000 1111 */ + + {&upd7810_device::EXA, 1, 4, 4,L0|L1}, /* 10: 0001 0000 */ + {&upd7810_device::EXX, 1, 4, 4,L0|L1}, /* 11: 0001 0001 */ + {&upd7810_device::INX_BC, 1, 7, 7,L0|L1}, /* 12: 0001 0010 */ + {&upd7810_device::DCX_BC, 1, 7, 7,L0|L1}, /* 13: 0001 0011 */ + {&upd7810_device::LXI_B_w, 3,10,10,L0|L1}, /* 14: 0001 0100 llll llll hhhh hhhh */ + {&upd7810_device::ORIW_wa_xx, 3,19,19,L0|L1}, /* 15: 0001 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::XRI_A_xx, 2, 7, 7,L0|L1}, /* 16: 0001 0110 xxxx xxxx */ + {&upd7810_device::ORI_A_xx, 2, 7, 7,L0|L1}, /* 17: 0001 0111 xxxx xxxx */ + {&upd7810_device::MOV_EAH_A, 1, 4, 4,L0|L1}, /* 18: 0001 1000 */ + {&upd7810_device::MOV_EAL_A, 1, 4, 4,L0|L1}, /* 19: 0001 1001 */ + {&upd7810_device::MOV_B_A, 1, 4, 4,L0|L1}, /* 1a: 0001 1010 */ + {&upd7810_device::MOV_C_A, 1, 4, 4,L0|L1}, /* 1b: 0001 1011 */ + {&upd7810_device::MOV_D_A, 1, 4, 4,L0|L1}, /* 1c: 0001 1100 */ + {&upd7810_device::MOV_E_A, 1, 4, 4,L0|L1}, /* 1d: 0001 1101 */ + {&upd7810_device::MOV_H_A, 1, 4, 4,L0|L1}, /* 1e: 0001 1110 */ + {&upd7810_device::MOV_L_A, 1, 4, 4,L0|L1}, /* 1f: 0001 1111 */ + + {&upd7810_device::INRW_wa, 2,16,16,L0|L1}, /* 20: 0010 0000 oooo oooo */ + {&upd7810_device::JB, 1, 4, 4,L0|L1}, /* 21: 0010 0001 */ + {&upd7810_device::INX_DE, 1, 7, 7,L0|L1}, /* 22: 0010 0010 */ + {&upd7810_device::DCX_DE, 1, 7, 7,L0|L1}, /* 23: 0010 0011 */ + {&upd7810_device::LXI_D_w, 3,10,10,L0|L1}, /* 24: 0010 0100 llll llll hhhh hhhh */ + {&upd7810_device::GTIW_wa_xx, 3,19,19,L0|L1}, /* 25: 0010 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::ADINC_A_xx, 2, 7, 7,L0|L1}, /* 26: 0010 0110 xxxx xxxx */ + {&upd7810_device::GTI_A_xx, 2, 7, 7,L0|L1}, /* 27: 0010 0111 xxxx xxxx */ + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, /* 28: */ + {&upd7810_device::LDAX_B, 2, 7, 7,L0|L1}, /* 29: 0010 1001 dddd dddd */ + {&upd7810_device::LDAX_D, 2, 7, 7,L0|L1}, /* 2a: 0010 1010 dddd dddd */ + {&upd7810_device::LDAX_H, 2, 7, 7,L0|L1}, /* 2b: 0010 1011 dddd dddd */ + {&upd7810_device::LDAX_Dp, 2, 7, 7,L0|L1}, /* 2c: 0010 1100 dddd dddd */ + {&upd7810_device::LDAX_Hp, 2, 7, 7,L0|L1}, /* 2d: 0010 1101 dddd dddd */ + {&upd7810_device::LDAX_Dm, 2, 7, 7,L0|L1}, /* 2e: 0010 1110 dddd dddd */ + {&upd7810_device::LDAX_Hm, 2, 7, 7,L0|L1}, /* 2f: 0010 1111 dddd dddd */ + + {&upd7810_device::DCRW_wa, 2,16,16,L0|L1}, /* 30: 0011 0000 oooo oooo */ + {&upd7810_device::BLOCK, 1,13,13,L0|L1}, /* 31: 0011 0001 */ /* 7810 */ + {&upd7810_device::INX_HL, 1, 7, 7,L0|L1}, /* 32: 0011 0010 */ + {&upd7810_device::DCX_HL, 1, 7, 7,L0|L1}, /* 33: 0011 0011 */ + {&upd7810_device::LXI_H_w, 3,10,10, L1}, /* 34: 0011 0100 llll llll hhhh hhhh */ + {&upd7810_device::LTIW_wa_xx, 3,19,19,L0|L1}, /* 35: 0011 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::SUINB_A_xx, 2, 7, 7,L0|L1}, /* 36: 0011 0110 xxxx xxxx */ + {&upd7810_device::LTI_A_xx, 2, 7, 7,L0|L1}, /* 37: 0011 0111 xxxx xxxx */ + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, /* 38: */ + {&upd7810_device::STAX_B, 2, 7, 7,L0|L1}, /* 39: 0011 1001 dddd dddd */ + {&upd7810_device::STAX_D, 2, 7, 7,L0|L1}, /* 3a: 0011 1010 dddd dddd */ + {&upd7810_device::STAX_H, 2, 7, 7,L0|L1}, /* 3b: 0011 1011 dddd dddd */ + {&upd7810_device::STAX_Dp, 2, 7, 7,L0|L1}, /* 3c: 0011 1100 dddd dddd */ + {&upd7810_device::STAX_Hp, 2, 7, 7,L0|L1}, /* 3d: 0011 1101 dddd dddd */ + {&upd7810_device::STAX_Dm, 2, 7, 7,L0|L1}, /* 3e: 0011 1110 dddd dddd */ + {&upd7810_device::STAX_Hm, 2, 7, 7,L0|L1}, /* 3f: 0011 1111 dddd dddd */ + + {&upd7810_device::CALL_w, 3,16,16,L0|L1}, /* 40: 0100 0000 llll llll hhhh hhhh */ + {&upd7810_device::INR_A, 1, 4, 4,L0|L1}, /* 41: 0100 0001 */ + {&upd7810_device::INR_B, 1, 4, 4,L0|L1}, /* 42: 0100 0010 */ + {&upd7810_device::INR_C, 1, 4, 4,L0|L1}, /* 43: 0100 0011 */ + {&upd7810_device::LXI_EA_s, 3,10,10,L0|L1}, /* 44: 0100 0100 llll llll hhhh hhhh */ + {&upd7810_device::ONIW_wa_xx, 3,19,19,L0|L1}, /* 45: 0100 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::ADI_A_xx, 2, 7, 7,L0|L1}, /* 46: 0100 0110 xxxx xxxx */ + {&upd7810_device::ONI_A_xx, 2, 7, 7,L0|L1}, /* 47: 0100 0111 xxxx xxxx */ + {&upd7810_device::PRE_48, 1, 0, 0,L0|L1}, /* 48: prefix */ + {&upd7810_device::MVIX_BC_xx, 2,10,10,L0|L1}, /* 49: 0100 1001 xxxx xxxx */ + {&upd7810_device::MVIX_DE_xx, 2,10,10,L0|L1}, /* 4a: 0100 1010 xxxx xxxx */ + {&upd7810_device::MVIX_HL_xx, 2,10,10,L0|L1}, /* 4b: 0100 1011 xxxx xxxx */ + {&upd7810_device::PRE_4C, 1, 0, 0,L0|L1}, /* 4c: prefix */ + {&upd7810_device::PRE_4D, 1, 4, 4,L0|L1}, /* 4d: prefix */ + {&upd7810_device::JRE, 2,10,10,L0|L1}, /* 4e: 0100 111d dddd dddd */ + {&upd7810_device::JRE, 2,10,10,L0|L1}, /* 4f: 0100 111d dddd dddd */ + + {&upd7810_device::EXH, 1, 4, 4,L0|L1}, /* 50: 0101 0000 */ /* 7810 */ + {&upd7810_device::DCR_A, 1, 4, 4,L0|L1}, /* 51: 0101 0001 */ + {&upd7810_device::DCR_B, 1, 4, 4,L0|L1}, /* 52: 0101 0010 */ + {&upd7810_device::DCR_C, 1, 4, 4,L0|L1}, /* 53: 0101 0011 */ + {&upd7810_device::JMP_w, 3,10,10,L0|L1}, /* 54: 0101 0100 llll llll hhhh hhhh */ + {&upd7810_device::OFFIW_wa_xx, 3,19,19,L0|L1}, /* 55: 0101 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::ACI_A_xx, 2, 7, 7,L0|L1}, /* 56: 0101 0110 xxxx xxxx */ + {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0|L1}, /* 57: 0101 0111 xxxx xxxx */ + {&upd7810_device::BIT_0_wa, 2,10,10,L0|L1}, /* 58: 0101 1000 oooo oooo */ /* 7810 */ + {&upd7810_device::BIT_1_wa, 2,10,10,L0|L1}, /* 59: 0101 1001 oooo oooo */ /* 7810 */ + {&upd7810_device::BIT_2_wa, 2,10,10,L0|L1}, /* 5a: 0101 1010 oooo oooo */ /* 7810 */ + {&upd7810_device::BIT_3_wa, 2,10,10,L0|L1}, /* 5b: 0101 1011 oooo oooo */ /* 7810 */ + {&upd7810_device::BIT_4_wa, 2,10,10,L0|L1}, /* 5c: 0101 1100 oooo oooo */ /* 7810 */ + {&upd7810_device::BIT_5_wa, 2,10,10,L0|L1}, /* 5d: 0101 1101 oooo oooo */ /* 7810 */ + {&upd7810_device::BIT_6_wa, 2,10,10,L0|L1}, /* 5e: 0101 1110 oooo oooo */ /* 7810 */ + {&upd7810_device::BIT_7_wa, 2,10,10,L0|L1}, /* 5f: 0101 1111 oooo oooo */ /* 7810 */ + + {&upd7810_device::PRE_60, 1, 0, 0,L0|L1}, /* 60: */ + {&upd7810_device::DAA, 1, 4, 4,L0|L1}, /* 61: 0110 0001 */ + {&upd7810_device::RETI, 1,13,13,L0|L1}, /* 62: 0110 0010 */ + {&upd7810_device::STAW_wa, 2,10,10,L0|L1}, /* 63: 0110 0011 oooo oooo */ + {&upd7810_device::PRE_64, 1, 0, 0,L0|L1}, /* 64: */ + {&upd7810_device::NEIW_wa_xx, 3,19,19,L0|L1}, /* 65: 0110 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::SUI_A_xx, 2, 7, 7,L0|L1}, /* 66: 0110 0110 xxxx xxxx */ + {&upd7810_device::NEI_A_xx, 2, 7, 7,L0|L1}, /* 67: 0110 0111 xxxx xxxx */ + {&upd7810_device::MVI_V_xx, 2, 7, 7,L0|L1}, /* 68: 0110 1000 xxxx xxxx */ + {&upd7810_device::MVI_A_xx, 2, 7, 7,L0 }, /* 69: 0110 1001 xxxx xxxx */ + {&upd7810_device::MVI_B_xx, 2, 7, 7,L0|L1}, /* 6a: 0110 1010 xxxx xxxx */ + {&upd7810_device::MVI_C_xx, 2, 7, 7,L0|L1}, /* 6b: 0110 1011 xxxx xxxx */ + {&upd7810_device::MVI_D_xx, 2, 7, 7,L0|L1}, /* 6c: 0110 1100 xxxx xxxx */ + {&upd7810_device::MVI_E_xx, 2, 7, 7,L0|L1}, /* 6d: 0110 1101 xxxx xxxx */ + {&upd7810_device::MVI_H_xx, 2, 7, 7,L0|L1}, /* 6e: 0110 1110 xxxx xxxx */ + {&upd7810_device::MVI_L_xx, 2, 7, 7, L1}, /* 6f: 0110 1111 xxxx xxxx */ + + {&upd7810_device::PRE_70, 1, 0, 0,L0|L1}, /* 70: */ + {&upd7810_device::MVIW_wa_xx, 3,13,13,L0|L1}, /* 71: 0111 0001 oooo oooo xxxx xxxx */ + {&upd7810_device::SOFTI, 1,16,16,L0|L1}, /* 72: 0111 0010 */ + {&upd7810_device::illegal, 1, 0, 0,L0|L1}, /* 73: */ + {&upd7810_device::PRE_74, 1, 0, 0,L0|L1}, /* 74: prefix */ + {&upd7810_device::EQIW_wa_xx, 3,19,19,L0|L1}, /* 75: 0111 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::SBI_A_xx, 2, 7, 7,L0|L1}, /* 76: 0111 0110 xxxx xxxx */ + {&upd7810_device::EQI_A_xx, 2, 7, 7,L0|L1}, /* 77: 0111 0111 xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 78: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 79: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7a: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7b: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7c: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7d: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7e: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7f: 0111 1xxx xxxx xxxx */ + + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 80: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 81: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 82: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 83: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 84: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 85: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 86: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 87: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 88: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 89: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8a: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8b: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8c: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8d: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8e: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8f: 100x xxxx */ + + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 90: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 91: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 92: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 93: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 94: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 95: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 96: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 97: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 98: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 99: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9a: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9b: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9c: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9d: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9e: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9f: 100x xxxx */ + + {&upd7810_device::POP_VA, 1,10,10,L0|L1}, /* a0: 1010 0000 */ + {&upd7810_device::POP_BC, 1,10,10,L0|L1}, /* a1: 1010 0001 */ + {&upd7810_device::POP_DE, 1,10,10,L0|L1}, /* a2: 1010 0010 */ + {&upd7810_device::POP_HL, 1,10,10,L0|L1}, /* a3: 1010 0011 */ + {&upd7810_device::POP_EA, 1,10,10,L0|L1}, /* a4: 1010 0100 */ + {&upd7810_device::DMOV_EA_BC, 1, 4, 4,L0|L1}, /* a5: 1010 0101 */ + {&upd7810_device::DMOV_EA_DE, 1, 4, 4,L0|L1}, /* a6: 1010 0110 */ + {&upd7810_device::DMOV_EA_HL, 1, 4, 4,L0|L1}, /* a7: 1010 0111 */ + {&upd7810_device::INX_EA, 1, 7, 7,L0|L1}, /* a8: 1010 1000 */ + {&upd7810_device::DCX_EA, 1, 7, 7,L0|L1}, /* a9: 1010 1001 */ + {&upd7810_device::EI, 1, 4, 4,L0|L1}, /* aa: 1010 1010 */ + {&upd7810_device::LDAX_D_xx, 2, 7, 7,L0|L1}, /* ab: 1010 1011 dddd dddd */ + {&upd7810_device::LDAX_H_A, 1, 7, 7,L0|L1}, /* ac: 1010 1100 */ + {&upd7810_device::LDAX_H_B, 1, 7, 7,L0|L1}, /* ad: 1010 1101 */ + {&upd7810_device::LDAX_H_EA, 1, 7, 7,L0|L1}, /* ae: 1010 1110 */ + {&upd7810_device::LDAX_H_xx, 2, 7, 7,L0|L1}, /* af: 1010 1111 dddd dddd */ + + {&upd7810_device::PUSH_VA, 1,13,13,L0|L1}, /* b0: 1011 0000 */ + {&upd7810_device::PUSH_BC, 1,13,13,L0|L1}, /* b1: 1011 0001 */ + {&upd7810_device::PUSH_DE, 1,13,13,L0|L1}, /* b2: 1011 0010 */ + {&upd7810_device::PUSH_HL, 1,13,13,L0|L1}, /* b3: 1011 0011 */ + {&upd7810_device::PUSH_EA, 1,13,13,L0|L1}, /* b4: 1011 0100 */ + {&upd7810_device::DMOV_BC_EA, 1, 4, 4,L0|L1}, /* b5: 1011 0101 */ + {&upd7810_device::DMOV_DE_EA, 1, 4, 4,L0|L1}, /* b6: 1011 0110 */ + {&upd7810_device::DMOV_HL_EA, 1, 4, 4,L0|L1}, /* b7: 1011 0111 */ + {&upd7810_device::RET, 1,10,10,L0|L1}, /* b8: 1011 1000 */ + {&upd7810_device::RETS, 1,10,10,L0|L1}, /* b9: 1011 1001 */ + {&upd7810_device::DI, 1, 4, 4,L0|L1}, /* ba: 1011 1010 */ + {&upd7810_device::STAX_D_xx, 2, 7, 7,L0|L1}, /* bb: 1011 1011 dddd dddd */ + {&upd7810_device::STAX_H_A, 1, 7, 7,L0|L1}, /* bc: 1011 1100 */ + {&upd7810_device::STAX_H_B, 1, 7, 7,L0|L1}, /* bd: 1011 1101 */ + {&upd7810_device::STAX_H_EA, 1, 7, 7,L0|L1}, /* be: 1011 1110 */ + {&upd7810_device::STAX_H_xx, 2, 7, 7,L0|L1}, /* bf: 1011 1111 dddd dddd */ + + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c0: 1100 0000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c1: 1100 0001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c2: 1100 0010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c3: 1100 0011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c4: 1100 0100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c5: 1100 0101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c6: 1100 0110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c7: 1100 0111 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c8: 1100 1000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c9: 1100 1001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ca: 1100 1010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* cb: 1100 1011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* cc: 1100 1100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* cd: 1100 1101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ce: 1100 1110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* cf: 1100 1111 */ + + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d0: 1101 0000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d1: 1101 0001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d2: 1101 0010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d3: 1101 0011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d4: 1101 0100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d5: 1101 0101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d6: 1101 0110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d7: 1101 0111 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d8: 1101 1000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d9: 1101 1001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* da: 1101 1010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* db: 1101 1011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* dc: 1101 1100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* dd: 1101 1101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* de: 1101 1110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* df: 1101 1111 */ + + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e0: 1110 0000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e1: 1110 0001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e2: 1110 0010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e3: 1110 0011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e4: 1110 0100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e5: 1110 0101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e6: 1110 0110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e7: 1110 0111 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e8: 1110 1000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e9: 1110 1001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ea: 1110 1010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* eb: 1110 1011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ec: 1110 1100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ed: 1110 1101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ee: 1110 1110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ef: 1110 1111 */ + + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f0: 1111 0000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f1: 1111 0001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f2: 1111 0010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f3: 1111 0011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f4: 1111 0100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f5: 1111 0101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f6: 1111 0110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f7: 1111 0111 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f8: 1111 1000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f9: 1111 1001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fa: 1111 1010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fb: 1111 1011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fc: 1111 1100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fd: 1111 1101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fe: 1111 1110 */ + {&upd7810_device::JR, 1,10,10,L0|L1} /* ff: 1111 1111 */ }; -static const struct opcode_s opXX_7807[256] = +const struct upd7810_device::opcode_s upd7810_device::s_opXX_7807[256] = { - {NOP, 1, 4, 4,L0|L1}, /* 00: 0000 0000 */ - {LDAW_wa, 2,10,10,L0|L1}, /* 01: 0000 0001 oooo oooo */ - {INX_SP, 1, 7, 7,L0|L1}, /* 02: 0000 0010 */ - {DCX_SP, 1, 7, 7,L0|L1}, /* 03: 0000 0011 */ - {LXI_S_w, 3,10,10,L0|L1}, /* 04: 0000 0100 llll llll hhhh hhhh */ - {ANIW_wa_xx, 3,19,19,L0|L1}, /* 05: 0000 0101 oooo oooo xxxx xxxx */ - {illegal, 1, 4, 4,L0|L1}, /* 06: */ - {ANI_A_xx, 2, 7, 7,L0|L1}, /* 07: 0000 0111 xxxx xxxx */ - {MOV_A_EAH, 1, 4, 4,L0|L1}, /* 08: 0000 1000 */ - {MOV_A_EAL, 1, 4, 4,L0|L1}, /* 09: 0000 1001 */ - {MOV_A_B, 1, 4, 4,L0|L1}, /* 0a: 0000 1010 */ - {MOV_A_C, 1, 4, 4,L0|L1}, /* 0b: 0000 1011 */ - {MOV_A_D, 1, 4, 4,L0|L1}, /* 0c: 0000 1100 */ - {MOV_A_E, 1, 4, 4,L0|L1}, /* 0d: 0000 1101 */ - {MOV_A_H, 1, 4, 4,L0|L1}, /* 0e: 0000 1110 */ - {MOV_A_L, 1, 4, 4,L0|L1}, /* 0f: 0000 1111 */ - - {illegal, 1,13, 4,L0|L1}, /* 10: 0001 0000 */ /* 7807 */ - {illegal, 1,13, 4,L0|L1}, /* 11: 0001 0001 */ /* 7807 */ - {INX_BC, 1, 7, 7,L0|L1}, /* 12: 0001 0010 */ - {DCX_BC, 1, 7, 7,L0|L1}, /* 13: 0001 0011 */ - {LXI_B_w, 3,10,10,L0|L1}, /* 14: 0001 0100 llll llll hhhh hhhh */ - {ORIW_wa_xx, 3,19,19,L0|L1}, /* 15: 0001 0101 oooo oooo xxxx xxxx */ - {XRI_A_xx, 2, 7, 7,L0|L1}, /* 16: 0001 0110 xxxx xxxx */ - {ORI_A_xx, 2, 7, 7,L0|L1}, /* 17: 0001 0111 xxxx xxxx */ - {MOV_EAH_A, 1, 4, 4,L0|L1}, /* 18: 0001 1000 */ - {MOV_EAL_A, 1, 4, 4,L0|L1}, /* 19: 0001 1001 */ - {MOV_B_A, 1, 4, 4,L0|L1}, /* 1a: 0001 1010 */ - {MOV_C_A, 1, 4, 4,L0|L1}, /* 1b: 0001 1011 */ - {MOV_D_A, 1, 4, 4,L0|L1}, /* 1c: 0001 1100 */ - {MOV_E_A, 1, 4, 4,L0|L1}, /* 1d: 0001 1101 */ - {MOV_H_A, 1, 4, 4,L0|L1}, /* 1e: 0001 1110 */ - {MOV_L_A, 1, 4, 4,L0|L1}, /* 1f: 0001 1111 */ - - {INRW_wa, 2,16,16,L0|L1}, /* 20: 0010 0000 oooo oooo */ - {JB, 1, 4, 4,L0|L1}, /* 21: 0010 0001 */ - {INX_DE, 1, 7, 7,L0|L1}, /* 22: 0010 0010 */ - {DCX_DE, 1, 7, 7,L0|L1}, /* 23: 0010 0011 */ - {LXI_D_w, 3,10,10,L0|L1}, /* 24: 0010 0100 llll llll hhhh hhhh */ - {GTIW_wa_xx, 3,19,19,L0|L1}, /* 25: 0010 0101 oooo oooo xxxx xxxx */ - {ADINC_A_xx, 2, 7, 7,L0|L1}, /* 26: 0010 0110 xxxx xxxx */ - {GTI_A_xx, 2, 7, 7,L0|L1}, /* 27: 0010 0111 xxxx xxxx */ - {illegal, 1, 4, 4,L0|L1}, /* 28: */ - {LDAX_B, 2, 7, 7,L0|L1}, /* 29: 0010 1001 dddd dddd */ - {LDAX_D, 2, 7, 7,L0|L1}, /* 2a: 0010 1010 dddd dddd */ - {LDAX_H, 2, 7, 7,L0|L1}, /* 2b: 0010 1011 dddd dddd */ - {LDAX_Dp, 2, 7, 7,L0|L1}, /* 2c: 0010 1100 dddd dddd */ - {LDAX_Hp, 2, 7, 7,L0|L1}, /* 2d: 0010 1101 dddd dddd */ - {LDAX_Dm, 2, 7, 7,L0|L1}, /* 2e: 0010 1110 dddd dddd */ - {LDAX_Hm, 2, 7, 7,L0|L1}, /* 2f: 0010 1111 dddd dddd */ - - {DCRW_wa, 2,16,16,L0|L1}, /* 30: 0011 0000 oooo oooo */ - {illegal, 2, 8, 8,L0|L1}, /* 31: 0011 0001 bbbb bbbb */ /* 7807 */ - {INX_HL, 1, 7, 7,L0|L1}, /* 32: 0011 0010 */ - {DCX_HL, 1, 7, 7,L0|L1}, /* 33: 0011 0011 */ - {LXI_H_w, 3,10,10, L1}, /* 34: 0011 0100 llll llll hhhh hhhh */ - {LTIW_wa_xx, 3,19,19,L0|L1}, /* 35: 0011 0101 oooo oooo xxxx xxxx */ - {SUINB_A_xx, 2, 7, 7,L0|L1}, /* 36: 0011 0110 xxxx xxxx */ - {LTI_A_xx, 2, 7, 7,L0|L1}, /* 37: 0011 0111 xxxx xxxx */ - {illegal, 1, 4, 4,L0|L1}, /* 38: */ - {STAX_B, 2, 7, 7,L0|L1}, /* 39: 0011 1001 dddd dddd */ - {STAX_D, 2, 7, 7,L0|L1}, /* 3a: 0011 1010 dddd dddd */ - {STAX_H, 2, 7, 7,L0|L1}, /* 3b: 0011 1011 dddd dddd */ - {STAX_Dp, 2, 7, 7,L0|L1}, /* 3c: 0011 1100 dddd dddd */ - {STAX_Hp, 2, 7, 7,L0|L1}, /* 3d: 0011 1101 dddd dddd */ - {STAX_Dm, 2, 7, 7,L0|L1}, /* 3e: 0011 1110 dddd dddd */ - {STAX_Hm, 2, 7, 7,L0|L1}, /* 3f: 0011 1111 dddd dddd */ - - {CALL_w, 3,16,16,L0|L1}, /* 40: 0100 0000 llll llll hhhh hhhh */ - {INR_A, 1, 4, 4,L0|L1}, /* 41: 0100 0001 */ - {INR_B, 1, 4, 4,L0|L1}, /* 42: 0100 0010 */ - {INR_C, 1, 4, 4,L0|L1}, /* 43: 0100 0011 */ - {LXI_EA_s, 3,10,10,L0|L1}, /* 44: 0100 0100 llll llll hhhh hhhh */ - {ONIW_wa_xx, 3,19,19,L0|L1}, /* 45: 0100 0101 oooo oooo xxxx xxxx */ - {ADI_A_xx, 2, 7, 7,L0|L1}, /* 46: 0100 0110 xxxx xxxx */ - {ONI_A_xx, 2, 7, 7,L0|L1}, /* 47: 0100 0111 xxxx xxxx */ - {PRE_48, 1, 0, 0,L0|L1}, /* 48: prefix */ - {MVIX_BC_xx, 2,10,10,L0|L1}, /* 49: 0100 1001 xxxx xxxx */ - {MVIX_DE_xx, 2,10,10,L0|L1}, /* 4a: 0100 1010 xxxx xxxx */ - {MVIX_HL_xx, 2,10,10,L0|L1}, /* 4b: 0100 1011 xxxx xxxx */ - {PRE_4C, 1, 0, 0,L0|L1}, /* 4c: prefix */ - {PRE_4D, 1, 4, 4,L0|L1}, /* 4d: prefix */ - {JRE, 2,10,10,L0|L1}, /* 4e: 0100 111d dddd dddd */ - {JRE, 2,10,10,L0|L1}, /* 4f: 0100 111d dddd dddd */ - - {SKN_bit, 2,13,13,L0|L1}, /* 50: 0101 0000 bbbb bbbb */ /* 7807 */ - {DCR_A, 1, 4, 4,L0|L1}, /* 51: 0101 0001 */ - {DCR_B, 1, 4, 4,L0|L1}, /* 52: 0101 0010 */ - {DCR_C, 1, 4, 4,L0|L1}, /* 53: 0101 0011 */ - {JMP_w, 3,10,10,L0|L1}, /* 54: 0101 0100 llll llll hhhh hhhh */ - {OFFIW_wa_xx, 3,19,19,L0|L1}, /* 55: 0101 0101 oooo oooo xxxx xxxx */ - {ACI_A_xx, 2, 7, 7,L0|L1}, /* 56: 0101 0110 xxxx xxxx */ - {OFFI_A_xx, 2, 7, 7,L0|L1}, /* 57: 0101 0111 xxxx xxxx */ - {SETB, 2,13,13,L0|L1}, /* 58: 0101 1000 bbbb bbbb */ /* 7807 */ - {illegal, 2, 8, 8,L0|L1}, /* 59: 0101 1001 bbbb bbbb */ /* 7807 */ - {illegal, 2, 8, 8,L0|L1}, /* 5a: 0101 1010 bbbb bbbb */ /* 7807 */ - {CLR, 2,13,13,L0|L1}, /* 5b: 0101 1011 bbbb bbbb */ /* 7807 */ - {illegal, 2, 8, 8,L0|L1}, /* 5c: 0101 1100 bbbb bbbb */ /* 7807 */ - {SK_bit, 2,10,10,L0|L1}, /* 5d: 0101 1101 bbbb bbbb */ /* 7807 */ - {illegal, 2, 8, 8,L0|L1}, /* 5e: 0101 1110 bbbb bbbb */ /* 7807 */ - {illegal, 2, 8, 8,L0|L1}, /* 5f: 0101 1111 bbbb bbbb */ /* 7807 */ - - {PRE_60, 1, 0, 0,L0|L1}, /* 60: */ - {DAA, 1, 4, 4,L0|L1}, /* 61: 0110 0001 */ - {RETI, 1,13,13,L0|L1}, /* 62: 0110 0010 */ - {STAW_wa, 2,10,10,L0|L1}, /* 63: 0110 0011 oooo oooo */ - {PRE_64, 1, 0, 0,L0|L1}, /* 64: */ - {NEIW_wa_xx, 3,19,19,L0|L1}, /* 65: 0110 0101 oooo oooo xxxx xxxx */ - {SUI_A_xx, 2, 7, 7,L0|L1}, /* 66: 0110 0110 xxxx xxxx */ - {NEI_A_xx, 2, 7, 7,L0|L1}, /* 67: 0110 0111 xxxx xxxx */ - {MVI_V_xx, 2, 7, 7,L0|L1}, /* 68: 0110 1000 xxxx xxxx */ - {MVI_A_xx, 2, 7, 7,L0 }, /* 69: 0110 1001 xxxx xxxx */ - {MVI_B_xx, 2, 7, 7,L0|L1}, /* 6a: 0110 1010 xxxx xxxx */ - {MVI_C_xx, 2, 7, 7,L0|L1}, /* 6b: 0110 1011 xxxx xxxx */ - {MVI_D_xx, 2, 7, 7,L0|L1}, /* 6c: 0110 1100 xxxx xxxx */ - {MVI_E_xx, 2, 7, 7,L0|L1}, /* 6d: 0110 1101 xxxx xxxx */ - {MVI_H_xx, 2, 7, 7,L0|L1}, /* 6e: 0110 1110 xxxx xxxx */ - {MVI_L_xx, 2, 7, 7, L1}, /* 6f: 0110 1111 xxxx xxxx */ - - {PRE_70, 1, 0, 0,L0|L1}, /* 70: */ - {MVIW_wa_xx, 3,13,13,L0|L1}, /* 71: 0111 0001 oooo oooo xxxx xxxx */ - {SOFTI, 1,16,16,L0|L1}, /* 72: 0111 0010 */ - {illegal, 1, 0, 0,L0|L1}, /* 73: */ - {PRE_74, 1, 0, 0,L0|L1}, /* 74: prefix */ - {EQIW_wa_xx, 3,19,19,L0|L1}, /* 75: 0111 0101 oooo oooo xxxx xxxx */ - {SBI_A_xx, 2, 7, 7,L0|L1}, /* 76: 0111 0110 xxxx xxxx */ - {EQI_A_xx, 2, 7, 7,L0|L1}, /* 77: 0111 0111 xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 78: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 79: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7a: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7b: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7c: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7d: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7e: 0111 1xxx xxxx xxxx */ - {CALF, 2,13,13,L0|L1}, /* 7f: 0111 1xxx xxxx xxxx */ - - {CALT, 1,16,16,L0|L1}, /* 80: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 81: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 82: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 83: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 84: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 85: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 86: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 87: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 88: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 89: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8a: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8b: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8c: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8d: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8e: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 8f: 100x xxxx */ - - {CALT, 1,16,16,L0|L1}, /* 90: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 91: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 92: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 93: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 94: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 95: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 96: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 97: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 98: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 99: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9a: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9b: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9c: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9d: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9e: 100x xxxx */ - {CALT, 1,16,16,L0|L1}, /* 9f: 100x xxxx */ - - {POP_VA, 1,10,10,L0|L1}, /* a0: 1010 0000 */ - {POP_BC, 1,10,10,L0|L1}, /* a1: 1010 0001 */ - {POP_DE, 1,10,10,L0|L1}, /* a2: 1010 0010 */ - {POP_HL, 1,10,10,L0|L1}, /* a3: 1010 0011 */ - {POP_EA, 1,10,10,L0|L1}, /* a4: 1010 0100 */ - {DMOV_EA_BC, 1, 4, 4,L0|L1}, /* a5: 1010 0101 */ - {DMOV_EA_DE, 1, 4, 4,L0|L1}, /* a6: 1010 0110 */ - {DMOV_EA_HL, 1, 4, 4,L0|L1}, /* a7: 1010 0111 */ - {INX_EA, 1, 7, 7,L0|L1}, /* a8: 1010 1000 */ - {DCX_EA, 1, 7, 7,L0|L1}, /* a9: 1010 1001 */ - {EI, 1, 4, 4,L0|L1}, /* aa: 1010 1010 */ - {LDAX_D_xx, 2, 7, 7,L0|L1}, /* ab: 1010 1011 dddd dddd */ - {LDAX_H_A, 1, 7, 7,L0|L1}, /* ac: 1010 1100 */ - {LDAX_H_B, 1, 7, 7,L0|L1}, /* ad: 1010 1101 */ - {LDAX_H_EA, 1, 7, 7,L0|L1}, /* ae: 1010 1110 */ - {LDAX_H_xx, 2, 7, 7,L0|L1}, /* af: 1010 1111 dddd dddd */ - - {PUSH_VA, 1,13,13,L0|L1}, /* b0: 1011 0000 */ - {PUSH_BC, 1,13,13,L0|L1}, /* b1: 1011 0001 */ - {PUSH_DE, 1,13,13,L0|L1}, /* b2: 1011 0010 */ - {PUSH_HL, 1,13,13,L0|L1}, /* b3: 1011 0011 */ - {PUSH_EA, 1,13,13,L0|L1}, /* b4: 1011 0100 */ - {DMOV_BC_EA, 1, 4, 4,L0|L1}, /* b5: 1011 0101 */ - {DMOV_DE_EA, 1, 4, 4,L0|L1}, /* b6: 1011 0110 */ - {DMOV_HL_EA, 1, 4, 4,L0|L1}, /* b7: 1011 0111 */ - {RET, 1,10,10,L0|L1}, /* b8: 1011 1000 */ - {RETS, 1,10,10,L0|L1}, /* b9: 1011 1001 */ - {DI, 1, 4, 4,L0|L1}, /* ba: 1011 1010 */ - {STAX_D_xx, 2, 7, 7,L0|L1}, /* bb: 1011 1011 dddd dddd */ - {STAX_H_A, 1, 7, 7,L0|L1}, /* bc: 1011 1100 */ - {STAX_H_B, 1, 7, 7,L0|L1}, /* bd: 1011 1101 */ - {STAX_H_EA, 1, 7, 7,L0|L1}, /* be: 1011 1110 */ - {STAX_H_xx, 2, 7, 7,L0|L1}, /* bf: 1011 1111 dddd dddd */ - - {JR, 1,10,10,L0|L1}, /* c0: 1100 0000 */ - {JR, 1,10,10,L0|L1}, /* c1: 1100 0001 */ - {JR, 1,10,10,L0|L1}, /* c2: 1100 0010 */ - {JR, 1,10,10,L0|L1}, /* c3: 1100 0011 */ - {JR, 1,10,10,L0|L1}, /* c4: 1100 0100 */ - {JR, 1,10,10,L0|L1}, /* c5: 1100 0101 */ - {JR, 1,10,10,L0|L1}, /* c6: 1100 0110 */ - {JR, 1,10,10,L0|L1}, /* c7: 1100 0111 */ - {JR, 1,10,10,L0|L1}, /* c8: 1100 1000 */ - {JR, 1,10,10,L0|L1}, /* c9: 1100 1001 */ - {JR, 1,10,10,L0|L1}, /* ca: 1100 1010 */ - {JR, 1,10,10,L0|L1}, /* cb: 1100 1011 */ - {JR, 1,10,10,L0|L1}, /* cc: 1100 1100 */ - {JR, 1,10,10,L0|L1}, /* cd: 1100 1101 */ - {JR, 1,10,10,L0|L1}, /* ce: 1100 1110 */ - {JR, 1,10,10,L0|L1}, /* cf: 1100 1111 */ - - {JR, 1,10,10,L0|L1}, /* d0: 1101 0000 */ - {JR, 1,10,10,L0|L1}, /* d1: 1101 0001 */ - {JR, 1,10,10,L0|L1}, /* d2: 1101 0010 */ - {JR, 1,10,10,L0|L1}, /* d3: 1101 0011 */ - {JR, 1,10,10,L0|L1}, /* d4: 1101 0100 */ - {JR, 1,10,10,L0|L1}, /* d5: 1101 0101 */ - {JR, 1,10,10,L0|L1}, /* d6: 1101 0110 */ - {JR, 1,10,10,L0|L1}, /* d7: 1101 0111 */ - {JR, 1,10,10,L0|L1}, /* d8: 1101 1000 */ - {JR, 1,10,10,L0|L1}, /* d9: 1101 1001 */ - {JR, 1,10,10,L0|L1}, /* da: 1101 1010 */ - {JR, 1,10,10,L0|L1}, /* db: 1101 1011 */ - {JR, 1,10,10,L0|L1}, /* dc: 1101 1100 */ - {JR, 1,10,10,L0|L1}, /* dd: 1101 1101 */ - {JR, 1,10,10,L0|L1}, /* de: 1101 1110 */ - {JR, 1,10,10,L0|L1}, /* df: 1101 1111 */ - - {JR, 1,10,10,L0|L1}, /* e0: 1110 0000 */ - {JR, 1,10,10,L0|L1}, /* e1: 1110 0001 */ - {JR, 1,10,10,L0|L1}, /* e2: 1110 0010 */ - {JR, 1,10,10,L0|L1}, /* e3: 1110 0011 */ - {JR, 1,10,10,L0|L1}, /* e4: 1110 0100 */ - {JR, 1,10,10,L0|L1}, /* e5: 1110 0101 */ - {JR, 1,10,10,L0|L1}, /* e6: 1110 0110 */ - {JR, 1,10,10,L0|L1}, /* e7: 1110 0111 */ - {JR, 1,10,10,L0|L1}, /* e8: 1110 1000 */ - {JR, 1,10,10,L0|L1}, /* e9: 1110 1001 */ - {JR, 1,10,10,L0|L1}, /* ea: 1110 1010 */ - {JR, 1,10,10,L0|L1}, /* eb: 1110 1011 */ - {JR, 1,10,10,L0|L1}, /* ec: 1110 1100 */ - {JR, 1,10,10,L0|L1}, /* ed: 1110 1101 */ - {JR, 1,10,10,L0|L1}, /* ee: 1110 1110 */ - {JR, 1,10,10,L0|L1}, /* ef: 1110 1111 */ - - {JR, 1,10,10,L0|L1}, /* f0: 1111 0000 */ - {JR, 1,10,10,L0|L1}, /* f1: 1111 0001 */ - {JR, 1,10,10,L0|L1}, /* f2: 1111 0010 */ - {JR, 1,10,10,L0|L1}, /* f3: 1111 0011 */ - {JR, 1,10,10,L0|L1}, /* f4: 1111 0100 */ - {JR, 1,10,10,L0|L1}, /* f5: 1111 0101 */ - {JR, 1,10,10,L0|L1}, /* f6: 1111 0110 */ - {JR, 1,10,10,L0|L1}, /* f7: 1111 0111 */ - {JR, 1,10,10,L0|L1}, /* f8: 1111 1000 */ - {JR, 1,10,10,L0|L1}, /* f9: 1111 1001 */ - {JR, 1,10,10,L0|L1}, /* fa: 1111 1010 */ - {JR, 1,10,10,L0|L1}, /* fb: 1111 1011 */ - {JR, 1,10,10,L0|L1}, /* fc: 1111 1100 */ - {JR, 1,10,10,L0|L1}, /* fd: 1111 1101 */ - {JR, 1,10,10,L0|L1}, /* fe: 1111 1110 */ - {JR, 1,10,10,L0|L1} /* ff: 1111 1111 */ + {&upd7810_device::NOP, 1, 4, 4,L0|L1}, /* 00: 0000 0000 */ + {&upd7810_device::LDAW_wa, 2,10,10,L0|L1}, /* 01: 0000 0001 oooo oooo */ + {&upd7810_device::INX_SP, 1, 7, 7,L0|L1}, /* 02: 0000 0010 */ + {&upd7810_device::DCX_SP, 1, 7, 7,L0|L1}, /* 03: 0000 0011 */ + {&upd7810_device::LXI_S_w, 3,10,10,L0|L1}, /* 04: 0000 0100 llll llll hhhh hhhh */ + {&upd7810_device::ANIW_wa_xx, 3,19,19,L0|L1}, /* 05: 0000 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, /* 06: */ + {&upd7810_device::ANI_A_xx, 2, 7, 7,L0|L1}, /* 07: 0000 0111 xxxx xxxx */ + {&upd7810_device::MOV_A_EAH, 1, 4, 4,L0|L1}, /* 08: 0000 1000 */ + {&upd7810_device::MOV_A_EAL, 1, 4, 4,L0|L1}, /* 09: 0000 1001 */ + {&upd7810_device::MOV_A_B, 1, 4, 4,L0|L1}, /* 0a: 0000 1010 */ + {&upd7810_device::MOV_A_C, 1, 4, 4,L0|L1}, /* 0b: 0000 1011 */ + {&upd7810_device::MOV_A_D, 1, 4, 4,L0|L1}, /* 0c: 0000 1100 */ + {&upd7810_device::MOV_A_E, 1, 4, 4,L0|L1}, /* 0d: 0000 1101 */ + {&upd7810_device::MOV_A_H, 1, 4, 4,L0|L1}, /* 0e: 0000 1110 */ + {&upd7810_device::MOV_A_L, 1, 4, 4,L0|L1}, /* 0f: 0000 1111 */ + + {&upd7810_device::illegal, 1,13, 4,L0|L1}, /* 10: 0001 0000 */ /* 7807 */ + {&upd7810_device::illegal, 1,13, 4,L0|L1}, /* 11: 0001 0001 */ /* 7807 */ + {&upd7810_device::INX_BC, 1, 7, 7,L0|L1}, /* 12: 0001 0010 */ + {&upd7810_device::DCX_BC, 1, 7, 7,L0|L1}, /* 13: 0001 0011 */ + {&upd7810_device::LXI_B_w, 3,10,10,L0|L1}, /* 14: 0001 0100 llll llll hhhh hhhh */ + {&upd7810_device::ORIW_wa_xx, 3,19,19,L0|L1}, /* 15: 0001 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::XRI_A_xx, 2, 7, 7,L0|L1}, /* 16: 0001 0110 xxxx xxxx */ + {&upd7810_device::ORI_A_xx, 2, 7, 7,L0|L1}, /* 17: 0001 0111 xxxx xxxx */ + {&upd7810_device::MOV_EAH_A, 1, 4, 4,L0|L1}, /* 18: 0001 1000 */ + {&upd7810_device::MOV_EAL_A, 1, 4, 4,L0|L1}, /* 19: 0001 1001 */ + {&upd7810_device::MOV_B_A, 1, 4, 4,L0|L1}, /* 1a: 0001 1010 */ + {&upd7810_device::MOV_C_A, 1, 4, 4,L0|L1}, /* 1b: 0001 1011 */ + {&upd7810_device::MOV_D_A, 1, 4, 4,L0|L1}, /* 1c: 0001 1100 */ + {&upd7810_device::MOV_E_A, 1, 4, 4,L0|L1}, /* 1d: 0001 1101 */ + {&upd7810_device::MOV_H_A, 1, 4, 4,L0|L1}, /* 1e: 0001 1110 */ + {&upd7810_device::MOV_L_A, 1, 4, 4,L0|L1}, /* 1f: 0001 1111 */ + + {&upd7810_device::INRW_wa, 2,16,16,L0|L1}, /* 20: 0010 0000 oooo oooo */ + {&upd7810_device::JB, 1, 4, 4,L0|L1}, /* 21: 0010 0001 */ + {&upd7810_device::INX_DE, 1, 7, 7,L0|L1}, /* 22: 0010 0010 */ + {&upd7810_device::DCX_DE, 1, 7, 7,L0|L1}, /* 23: 0010 0011 */ + {&upd7810_device::LXI_D_w, 3,10,10,L0|L1}, /* 24: 0010 0100 llll llll hhhh hhhh */ + {&upd7810_device::GTIW_wa_xx, 3,19,19,L0|L1}, /* 25: 0010 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::ADINC_A_xx, 2, 7, 7,L0|L1}, /* 26: 0010 0110 xxxx xxxx */ + {&upd7810_device::GTI_A_xx, 2, 7, 7,L0|L1}, /* 27: 0010 0111 xxxx xxxx */ + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, /* 28: */ + {&upd7810_device::LDAX_B, 2, 7, 7,L0|L1}, /* 29: 0010 1001 dddd dddd */ + {&upd7810_device::LDAX_D, 2, 7, 7,L0|L1}, /* 2a: 0010 1010 dddd dddd */ + {&upd7810_device::LDAX_H, 2, 7, 7,L0|L1}, /* 2b: 0010 1011 dddd dddd */ + {&upd7810_device::LDAX_Dp, 2, 7, 7,L0|L1}, /* 2c: 0010 1100 dddd dddd */ + {&upd7810_device::LDAX_Hp, 2, 7, 7,L0|L1}, /* 2d: 0010 1101 dddd dddd */ + {&upd7810_device::LDAX_Dm, 2, 7, 7,L0|L1}, /* 2e: 0010 1110 dddd dddd */ + {&upd7810_device::LDAX_Hm, 2, 7, 7,L0|L1}, /* 2f: 0010 1111 dddd dddd */ + + {&upd7810_device::DCRW_wa, 2,16,16,L0|L1}, /* 30: 0011 0000 oooo oooo */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 31: 0011 0001 bbbb bbbb */ /* 7807 */ + {&upd7810_device::INX_HL, 1, 7, 7,L0|L1}, /* 32: 0011 0010 */ + {&upd7810_device::DCX_HL, 1, 7, 7,L0|L1}, /* 33: 0011 0011 */ + {&upd7810_device::LXI_H_w, 3,10,10, L1}, /* 34: 0011 0100 llll llll hhhh hhhh */ + {&upd7810_device::LTIW_wa_xx, 3,19,19,L0|L1}, /* 35: 0011 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::SUINB_A_xx, 2, 7, 7,L0|L1}, /* 36: 0011 0110 xxxx xxxx */ + {&upd7810_device::LTI_A_xx, 2, 7, 7,L0|L1}, /* 37: 0011 0111 xxxx xxxx */ + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, /* 38: */ + {&upd7810_device::STAX_B, 2, 7, 7,L0|L1}, /* 39: 0011 1001 dddd dddd */ + {&upd7810_device::STAX_D, 2, 7, 7,L0|L1}, /* 3a: 0011 1010 dddd dddd */ + {&upd7810_device::STAX_H, 2, 7, 7,L0|L1}, /* 3b: 0011 1011 dddd dddd */ + {&upd7810_device::STAX_Dp, 2, 7, 7,L0|L1}, /* 3c: 0011 1100 dddd dddd */ + {&upd7810_device::STAX_Hp, 2, 7, 7,L0|L1}, /* 3d: 0011 1101 dddd dddd */ + {&upd7810_device::STAX_Dm, 2, 7, 7,L0|L1}, /* 3e: 0011 1110 dddd dddd */ + {&upd7810_device::STAX_Hm, 2, 7, 7,L0|L1}, /* 3f: 0011 1111 dddd dddd */ + + {&upd7810_device::CALL_w, 3,16,16,L0|L1}, /* 40: 0100 0000 llll llll hhhh hhhh */ + {&upd7810_device::INR_A, 1, 4, 4,L0|L1}, /* 41: 0100 0001 */ + {&upd7810_device::INR_B, 1, 4, 4,L0|L1}, /* 42: 0100 0010 */ + {&upd7810_device::INR_C, 1, 4, 4,L0|L1}, /* 43: 0100 0011 */ + {&upd7810_device::LXI_EA_s, 3,10,10,L0|L1}, /* 44: 0100 0100 llll llll hhhh hhhh */ + {&upd7810_device::ONIW_wa_xx, 3,19,19,L0|L1}, /* 45: 0100 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::ADI_A_xx, 2, 7, 7,L0|L1}, /* 46: 0100 0110 xxxx xxxx */ + {&upd7810_device::ONI_A_xx, 2, 7, 7,L0|L1}, /* 47: 0100 0111 xxxx xxxx */ + {&upd7810_device::PRE_48, 1, 0, 0,L0|L1}, /* 48: prefix */ + {&upd7810_device::MVIX_BC_xx, 2,10,10,L0|L1}, /* 49: 0100 1001 xxxx xxxx */ + {&upd7810_device::MVIX_DE_xx, 2,10,10,L0|L1}, /* 4a: 0100 1010 xxxx xxxx */ + {&upd7810_device::MVIX_HL_xx, 2,10,10,L0|L1}, /* 4b: 0100 1011 xxxx xxxx */ + {&upd7810_device::PRE_4C, 1, 0, 0,L0|L1}, /* 4c: prefix */ + {&upd7810_device::PRE_4D, 1, 4, 4,L0|L1}, /* 4d: prefix */ + {&upd7810_device::JRE, 2,10,10,L0|L1}, /* 4e: 0100 111d dddd dddd */ + {&upd7810_device::JRE, 2,10,10,L0|L1}, /* 4f: 0100 111d dddd dddd */ + + {&upd7810_device::SKN_bit, 2,13,13,L0|L1}, /* 50: 0101 0000 bbbb bbbb */ /* 7807 */ + {&upd7810_device::DCR_A, 1, 4, 4,L0|L1}, /* 51: 0101 0001 */ + {&upd7810_device::DCR_B, 1, 4, 4,L0|L1}, /* 52: 0101 0010 */ + {&upd7810_device::DCR_C, 1, 4, 4,L0|L1}, /* 53: 0101 0011 */ + {&upd7810_device::JMP_w, 3,10,10,L0|L1}, /* 54: 0101 0100 llll llll hhhh hhhh */ + {&upd7810_device::OFFIW_wa_xx, 3,19,19,L0|L1}, /* 55: 0101 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::ACI_A_xx, 2, 7, 7,L0|L1}, /* 56: 0101 0110 xxxx xxxx */ + {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0|L1}, /* 57: 0101 0111 xxxx xxxx */ + {&upd7810_device::SETB, 2,13,13,L0|L1}, /* 58: 0101 1000 bbbb bbbb */ /* 7807 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 59: 0101 1001 bbbb bbbb */ /* 7807 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 5a: 0101 1010 bbbb bbbb */ /* 7807 */ + {&upd7810_device::CLR, 2,13,13,L0|L1}, /* 5b: 0101 1011 bbbb bbbb */ /* 7807 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 5c: 0101 1100 bbbb bbbb */ /* 7807 */ + {&upd7810_device::SK_bit, 2,10,10,L0|L1}, /* 5d: 0101 1101 bbbb bbbb */ /* 7807 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 5e: 0101 1110 bbbb bbbb */ /* 7807 */ + {&upd7810_device::illegal, 2, 8, 8,L0|L1}, /* 5f: 0101 1111 bbbb bbbb */ /* 7807 */ + + {&upd7810_device::PRE_60, 1, 0, 0,L0|L1}, /* 60: */ + {&upd7810_device::DAA, 1, 4, 4,L0|L1}, /* 61: 0110 0001 */ + {&upd7810_device::RETI, 1,13,13,L0|L1}, /* 62: 0110 0010 */ + {&upd7810_device::STAW_wa, 2,10,10,L0|L1}, /* 63: 0110 0011 oooo oooo */ + {&upd7810_device::PRE_64, 1, 0, 0,L0|L1}, /* 64: */ + {&upd7810_device::NEIW_wa_xx, 3,19,19,L0|L1}, /* 65: 0110 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::SUI_A_xx, 2, 7, 7,L0|L1}, /* 66: 0110 0110 xxxx xxxx */ + {&upd7810_device::NEI_A_xx, 2, 7, 7,L0|L1}, /* 67: 0110 0111 xxxx xxxx */ + {&upd7810_device::MVI_V_xx, 2, 7, 7,L0|L1}, /* 68: 0110 1000 xxxx xxxx */ + {&upd7810_device::MVI_A_xx, 2, 7, 7,L0 }, /* 69: 0110 1001 xxxx xxxx */ + {&upd7810_device::MVI_B_xx, 2, 7, 7,L0|L1}, /* 6a: 0110 1010 xxxx xxxx */ + {&upd7810_device::MVI_C_xx, 2, 7, 7,L0|L1}, /* 6b: 0110 1011 xxxx xxxx */ + {&upd7810_device::MVI_D_xx, 2, 7, 7,L0|L1}, /* 6c: 0110 1100 xxxx xxxx */ + {&upd7810_device::MVI_E_xx, 2, 7, 7,L0|L1}, /* 6d: 0110 1101 xxxx xxxx */ + {&upd7810_device::MVI_H_xx, 2, 7, 7,L0|L1}, /* 6e: 0110 1110 xxxx xxxx */ + {&upd7810_device::MVI_L_xx, 2, 7, 7, L1}, /* 6f: 0110 1111 xxxx xxxx */ + + {&upd7810_device::PRE_70, 1, 0, 0,L0|L1}, /* 70: */ + {&upd7810_device::MVIW_wa_xx, 3,13,13,L0|L1}, /* 71: 0111 0001 oooo oooo xxxx xxxx */ + {&upd7810_device::SOFTI, 1,16,16,L0|L1}, /* 72: 0111 0010 */ + {&upd7810_device::illegal, 1, 0, 0,L0|L1}, /* 73: */ + {&upd7810_device::PRE_74, 1, 0, 0,L0|L1}, /* 74: prefix */ + {&upd7810_device::EQIW_wa_xx, 3,19,19,L0|L1}, /* 75: 0111 0101 oooo oooo xxxx xxxx */ + {&upd7810_device::SBI_A_xx, 2, 7, 7,L0|L1}, /* 76: 0111 0110 xxxx xxxx */ + {&upd7810_device::EQI_A_xx, 2, 7, 7,L0|L1}, /* 77: 0111 0111 xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 78: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 79: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7a: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7b: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7c: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7d: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7e: 0111 1xxx xxxx xxxx */ + {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 7f: 0111 1xxx xxxx xxxx */ + + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 80: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 81: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 82: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 83: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 84: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 85: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 86: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 87: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 88: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 89: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8a: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8b: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8c: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8d: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8e: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 8f: 100x xxxx */ + + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 90: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 91: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 92: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 93: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 94: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 95: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 96: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 97: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 98: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 99: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9a: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9b: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9c: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9d: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9e: 100x xxxx */ + {&upd7810_device::CALT, 1,16,16,L0|L1}, /* 9f: 100x xxxx */ + + {&upd7810_device::POP_VA, 1,10,10,L0|L1}, /* a0: 1010 0000 */ + {&upd7810_device::POP_BC, 1,10,10,L0|L1}, /* a1: 1010 0001 */ + {&upd7810_device::POP_DE, 1,10,10,L0|L1}, /* a2: 1010 0010 */ + {&upd7810_device::POP_HL, 1,10,10,L0|L1}, /* a3: 1010 0011 */ + {&upd7810_device::POP_EA, 1,10,10,L0|L1}, /* a4: 1010 0100 */ + {&upd7810_device::DMOV_EA_BC, 1, 4, 4,L0|L1}, /* a5: 1010 0101 */ + {&upd7810_device::DMOV_EA_DE, 1, 4, 4,L0|L1}, /* a6: 1010 0110 */ + {&upd7810_device::DMOV_EA_HL, 1, 4, 4,L0|L1}, /* a7: 1010 0111 */ + {&upd7810_device::INX_EA, 1, 7, 7,L0|L1}, /* a8: 1010 1000 */ + {&upd7810_device::DCX_EA, 1, 7, 7,L0|L1}, /* a9: 1010 1001 */ + {&upd7810_device::EI, 1, 4, 4,L0|L1}, /* aa: 1010 1010 */ + {&upd7810_device::LDAX_D_xx, 2, 7, 7,L0|L1}, /* ab: 1010 1011 dddd dddd */ + {&upd7810_device::LDAX_H_A, 1, 7, 7,L0|L1}, /* ac: 1010 1100 */ + {&upd7810_device::LDAX_H_B, 1, 7, 7,L0|L1}, /* ad: 1010 1101 */ + {&upd7810_device::LDAX_H_EA, 1, 7, 7,L0|L1}, /* ae: 1010 1110 */ + {&upd7810_device::LDAX_H_xx, 2, 7, 7,L0|L1}, /* af: 1010 1111 dddd dddd */ + + {&upd7810_device::PUSH_VA, 1,13,13,L0|L1}, /* b0: 1011 0000 */ + {&upd7810_device::PUSH_BC, 1,13,13,L0|L1}, /* b1: 1011 0001 */ + {&upd7810_device::PUSH_DE, 1,13,13,L0|L1}, /* b2: 1011 0010 */ + {&upd7810_device::PUSH_HL, 1,13,13,L0|L1}, /* b3: 1011 0011 */ + {&upd7810_device::PUSH_EA, 1,13,13,L0|L1}, /* b4: 1011 0100 */ + {&upd7810_device::DMOV_BC_EA, 1, 4, 4,L0|L1}, /* b5: 1011 0101 */ + {&upd7810_device::DMOV_DE_EA, 1, 4, 4,L0|L1}, /* b6: 1011 0110 */ + {&upd7810_device::DMOV_HL_EA, 1, 4, 4,L0|L1}, /* b7: 1011 0111 */ + {&upd7810_device::RET, 1,10,10,L0|L1}, /* b8: 1011 1000 */ + {&upd7810_device::RETS, 1,10,10,L0|L1}, /* b9: 1011 1001 */ + {&upd7810_device::DI, 1, 4, 4,L0|L1}, /* ba: 1011 1010 */ + {&upd7810_device::STAX_D_xx, 2, 7, 7,L0|L1}, /* bb: 1011 1011 dddd dddd */ + {&upd7810_device::STAX_H_A, 1, 7, 7,L0|L1}, /* bc: 1011 1100 */ + {&upd7810_device::STAX_H_B, 1, 7, 7,L0|L1}, /* bd: 1011 1101 */ + {&upd7810_device::STAX_H_EA, 1, 7, 7,L0|L1}, /* be: 1011 1110 */ + {&upd7810_device::STAX_H_xx, 2, 7, 7,L0|L1}, /* bf: 1011 1111 dddd dddd */ + + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c0: 1100 0000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c1: 1100 0001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c2: 1100 0010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c3: 1100 0011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c4: 1100 0100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c5: 1100 0101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c6: 1100 0110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c7: 1100 0111 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c8: 1100 1000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* c9: 1100 1001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ca: 1100 1010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* cb: 1100 1011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* cc: 1100 1100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* cd: 1100 1101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ce: 1100 1110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* cf: 1100 1111 */ + + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d0: 1101 0000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d1: 1101 0001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d2: 1101 0010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d3: 1101 0011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d4: 1101 0100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d5: 1101 0101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d6: 1101 0110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d7: 1101 0111 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d8: 1101 1000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* d9: 1101 1001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* da: 1101 1010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* db: 1101 1011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* dc: 1101 1100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* dd: 1101 1101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* de: 1101 1110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* df: 1101 1111 */ + + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e0: 1110 0000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e1: 1110 0001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e2: 1110 0010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e3: 1110 0011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e4: 1110 0100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e5: 1110 0101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e6: 1110 0110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e7: 1110 0111 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e8: 1110 1000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* e9: 1110 1001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ea: 1110 1010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* eb: 1110 1011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ec: 1110 1100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ed: 1110 1101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ee: 1110 1110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* ef: 1110 1111 */ + + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f0: 1111 0000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f1: 1111 0001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f2: 1111 0010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f3: 1111 0011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f4: 1111 0100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f5: 1111 0101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f6: 1111 0110 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f7: 1111 0111 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f8: 1111 1000 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* f9: 1111 1001 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fa: 1111 1010 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fb: 1111 1011 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fc: 1111 1100 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fd: 1111 1101 */ + {&upd7810_device::JR, 1,10,10,L0|L1}, /* fe: 1111 1110 */ + {&upd7810_device::JR, 1,10,10,L0|L1} /* ff: 1111 1111 */ }; @@ -3541,1249 +2502,1249 @@ static const struct opcode_s opXX_7807[256] = * **********************************************************************/ -static const struct opcode_s op48_7801[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op48_7801[256] = { /* 0x00 - 0x1F */ - {SKIT_F0, 2, 8, 8,L0|L1}, {SKIT_FT0, 2, 8, 8,L0|L1}, - {SKIT_F1, 2, 8, 8,L0|L1}, {SKIT_F2, 2, 8, 8,L0|L1}, - {SKIT_FST, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SK_CY, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SK_Z, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {PUSH_VA, 2,17,17,L0|L1}, {POP_VA, 2,15,15,L0|L1}, - - {SKNIT_F0, 2, 8, 8,L0|L1}, {SKNIT_FT0, 2, 8, 8,L0|L1}, - {SKNIT_F1, 2, 8, 8,L0|L1}, {SKNIT_F2, 2, 8, 8,L0|L1}, - {SKNIT_FST, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal, 2, 8, 8,L0|L1}, - {SKN_CY, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SKN_Z, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {PUSH_BC, 2,17,17,L0|L1}, {POP_BC, 2,15,15,L0|L1}, + {&upd7810_device::SKIT_F0, 2, 8, 8,L0|L1}, {&upd7810_device::SKIT_FT0, 2, 8, 8,L0|L1}, + {&upd7810_device::SKIT_F1, 2, 8, 8,L0|L1}, {&upd7810_device::SKIT_F2, 2, 8, 8,L0|L1}, + {&upd7810_device::SKIT_FST, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SK_CY, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SK_Z, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::PUSH_VA, 2,17,17,L0|L1}, {&upd7810_device::POP_VA, 2,15,15,L0|L1}, + + {&upd7810_device::SKNIT_F0, 2, 8, 8,L0|L1}, {&upd7810_device::SKNIT_FT0, 2, 8, 8,L0|L1}, + {&upd7810_device::SKNIT_F1, 2, 8, 8,L0|L1}, {&upd7810_device::SKNIT_F2, 2, 8, 8,L0|L1}, + {&upd7810_device::SKNIT_FST, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal, 2, 8, 8,L0|L1}, + {&upd7810_device::SKN_CY, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SKN_Z, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::PUSH_BC, 2,17,17,L0|L1}, {&upd7810_device::POP_BC, 2,15,15,L0|L1}, /* 0x20 - 0x3F */ - {EI, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {DI, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {CLC, 2, 8, 8,L0|L1}, {STC, 2, 8, 8,L0|L1}, - {PEN, 2,11,11,L0|L1}, {PEX, 2,11,11,L0|L1}, - {PUSH_DE, 2,17,17,L0|L1}, {POP_DE, 2,15,15,L0|L1}, - - {RLL_A, 2, 8, 8,L0|L1}, {RLR_A, 2, 8, 8,L0|L1}, - {RLL_C, 2, 8, 8,L0|L1}, {RLR_C, 2, 8, 8,L0|L1}, - {SLL_A, 2, 8, 8,L0|L1}, {SLR_A, 2, 8, 8,L0|L1}, - {SLL_C, 2, 8, 8,L0|L1}, {SLR_C, 2, 8, 8,L0|L1}, - {RLD, 2,17,17,L0|L1}, {RRD, 2,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {PER, 2,11,11,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {PUSH_HL, 2,17,17,L0|L1}, {POP_HL, 2,15,15,L0|L1}, + {&upd7810_device::EI, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::DI, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::CLC, 2, 8, 8,L0|L1}, {&upd7810_device::STC, 2, 8, 8,L0|L1}, + {&upd7810_device::PEN, 2,11,11,L0|L1}, {&upd7810_device::PEX, 2,11,11,L0|L1}, + {&upd7810_device::PUSH_DE, 2,17,17,L0|L1}, {&upd7810_device::POP_DE, 2,15,15,L0|L1}, + + {&upd7810_device::RLL_A, 2, 8, 8,L0|L1}, {&upd7810_device::RLR_A, 2, 8, 8,L0|L1}, + {&upd7810_device::RLL_C, 2, 8, 8,L0|L1}, {&upd7810_device::RLR_C, 2, 8, 8,L0|L1}, + {&upd7810_device::SLL_A, 2, 8, 8,L0|L1}, {&upd7810_device::SLR_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SLL_C, 2, 8, 8,L0|L1}, {&upd7810_device::SLR_C, 2, 8, 8,L0|L1}, + {&upd7810_device::RLD, 2,17,17,L0|L1}, {&upd7810_device::RRD, 2,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::PER, 2,11,11,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::PUSH_HL, 2,17,17,L0|L1}, {&upd7810_device::POP_HL, 2,15,15,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; -static const struct opcode_s op4C_7801[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op4C_7801[256] = { /* 0x00 - 0x1F */ - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, /* 0x20 - 0x3F */ - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, /* 0x40 - 0x5F */ - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, /* 0x60 - 0x7F */ - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, /* 0x80 - 0x9F */ - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, /* 0xA0 - 0xBF */ - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, - {IN, 2,10,10,L0|L1}, {IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, + {&upd7810_device::IN, 2,10,10,L0|L1}, {&upd7810_device::IN, 2,10,10,L0|L1}, /* 0xC0 - 0xDF */ - {MOV_A_PA, 2,10,10,L0|L1}, {MOV_A_PB, 2,10,10,L0|L1}, - {MOV_A_PC, 2,10,10,L0|L1}, {MOV_A_MKL, 2,10,10,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {MOV_A_S, 2,10,10,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::MOV_A_PA, 2,10,10,L0|L1}, {&upd7810_device::MOV_A_PB, 2,10,10,L0|L1}, + {&upd7810_device::MOV_A_PC, 2,10,10,L0|L1}, {&upd7810_device::MOV_A_MKL, 2,10,10,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::MOV_A_S, 2,10,10,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; /* prefix 4D */ -static const struct opcode_s op4D_7801[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op4D_7801[256] = { /* 0x00 - 0x1F */ - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, /* 0x20 - 0x3F */ - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, /* 0x40 - 0x5F */ - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, /* 0x60 - 0x7F */ - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, /* 0x80 - 0x9F */ - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, /* 0xA0 - 0xBF */ - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, - {OUT, 2,10,10,L0|L1}, {OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, + {&upd7810_device::OUT, 2,10,10,L0|L1}, {&upd7810_device::OUT, 2,10,10,L0|L1}, /* 0xC0 - 0xDF */ - {MOV_PA_A, 2,10,10,L0|L1}, {MOV_PB_A, 2,10,10,L0|L1}, - {MOV_PC_A, 2,10,10,L0|L1}, {MOV_MKL_A, 2,10,10,L0|L1}, - {MOV_MB_A, 2,10,10,L0|L1}, {MOV_MC_A_7801, 2,10,10,L0|L1}, - {MOV_TM0_A, 2,10,10,L0|L1}, {MOV_TM1_A, 2,10,10,L0|L1}, - {MOV_S_A, 2,10,10,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::MOV_PA_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_PB_A, 2,10,10,L0|L1}, + {&upd7810_device::MOV_PC_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_MKL_A, 2,10,10,L0|L1}, + {&upd7810_device::MOV_MB_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_MC_A_7801, 2,10,10,L0|L1}, + {&upd7810_device::MOV_TM0_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_TM1_A, 2,10,10,L0|L1}, + {&upd7810_device::MOV_S_A, 2,10,10,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; /* prefix 60 */ -static const struct opcode_s op60_7801[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op60_7801[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ANA_V_A, 2, 8, 8,L0|L1}, {ANA_A_A, 2, 8, 8,L0|L1}, - {ANA_B_A, 2, 8, 8,L0|L1}, {ANA_C_A, 2, 8, 8,L0|L1}, - {ANA_D_A, 2, 8, 8,L0|L1}, {ANA_E_A, 2, 8, 8,L0|L1}, - {ANA_H_A, 2, 8, 8,L0|L1}, {ANA_L_A, 2, 8, 8,L0|L1}, - - {XRA_V_A, 2, 8, 8,L0|L1}, {XRA_A_A, 2, 8, 8,L0|L1}, - {XRA_B_A, 2, 8, 8,L0|L1}, {XRA_C_A, 2, 8, 8,L0|L1}, - {XRA_D_A, 2, 8, 8,L0|L1}, {XRA_E_A, 2, 8, 8,L0|L1}, - {XRA_H_A, 2, 8, 8,L0|L1}, {XRA_L_A, 2, 8, 8,L0|L1}, - {ORA_V_A, 2, 8, 8,L0|L1}, {ORA_A_A, 2, 8, 8,L0|L1}, - {ORA_B_A, 2, 8, 8,L0|L1}, {ORA_C_A, 2, 8, 8,L0|L1}, - {ORA_D_A, 2, 8, 8,L0|L1}, {ORA_E_A, 2, 8, 8,L0|L1}, - {ORA_H_A, 2, 8, 8,L0|L1}, {ORA_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_L_A, 2, 8, 8,L0|L1}, + + {&upd7810_device::XRA_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_L_A, 2, 8, 8,L0|L1}, /* 0x20 - 0x3F */ - {ADDNC_V_A, 2, 8, 8,L0|L1}, {ADDNC_A_A, 2, 8, 8,L0|L1}, - {ADDNC_B_A, 2, 8, 8,L0|L1}, {ADDNC_C_A, 2, 8, 8,L0|L1}, - {ADDNC_D_A, 2, 8, 8,L0|L1}, {ADDNC_E_A, 2, 8, 8,L0|L1}, - {ADDNC_H_A, 2, 8, 8,L0|L1}, {ADDNC_L_A, 2, 8, 8,L0|L1}, - {GTA_V_A, 2, 8, 8,L0|L1}, {GTA_A_A, 2, 8, 8,L0|L1}, - {GTA_B_A, 2, 8, 8,L0|L1}, {GTA_C_A, 2, 8, 8,L0|L1}, - {GTA_D_A, 2, 8, 8,L0|L1}, {GTA_E_A, 2, 8, 8,L0|L1}, - {GTA_H_A, 2, 8, 8,L0|L1}, {GTA_L_A, 2, 8, 8,L0|L1}, - - {SUBNB_V_A, 2, 8, 8,L0|L1}, {SUBNB_A_A, 2, 8, 8,L0|L1}, - {SUBNB_B_A, 2, 8, 8,L0|L1}, {SUBNB_C_A, 2, 8, 8,L0|L1}, - {SUBNB_D_A, 2, 8, 8,L0|L1}, {SUBNB_E_A, 2, 8, 8,L0|L1}, - {SUBNB_H_A, 2, 8, 8,L0|L1}, {SUBNB_L_A, 2, 8, 8,L0|L1}, - {LTA_V_A, 2, 8, 8,L0|L1}, {LTA_A_A, 2, 8, 8,L0|L1}, - {LTA_B_A, 2, 8, 8,L0|L1}, {LTA_C_A, 2, 8, 8,L0|L1}, - {LTA_D_A, 2, 8, 8,L0|L1}, {LTA_E_A, 2, 8, 8,L0|L1}, - {LTA_H_A, 2, 8, 8,L0|L1}, {LTA_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_L_A, 2, 8, 8,L0|L1}, + + {&upd7810_device::SUBNB_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_L_A, 2, 8, 8,L0|L1}, /* 0x40 - 0x5F */ - {ADD_V_A, 2, 8, 8,L0|L1}, {ADD_A_A, 2, 8, 8,L0|L1}, - {ADD_B_A, 2, 8, 8,L0|L1}, {ADD_C_A, 2, 8, 8,L0|L1}, - {ADD_D_A, 2, 8, 8,L0|L1}, {ADD_E_A, 2, 8, 8,L0|L1}, - {ADD_H_A, 2, 8, 8,L0|L1}, {ADD_L_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {ADC_V_A, 2, 8, 8,L0|L1}, {ADC_A_A, 2, 8, 8,L0|L1}, - {ADC_B_A, 2, 8, 8,L0|L1}, {ADC_C_A, 2, 8, 8,L0|L1}, - {ADC_D_A, 2, 8, 8,L0|L1}, {ADC_E_A, 2, 8, 8,L0|L1}, - {ADC_H_A, 2, 8, 8,L0|L1}, {ADC_L_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::ADC_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {SUB_V_A, 2, 8, 8,L0|L1}, {SUB_A_A, 2, 8, 8,L0|L1}, - {SUB_B_A, 2, 8, 8,L0|L1}, {SUB_C_A, 2, 8, 8,L0|L1}, - {SUB_D_A, 2, 8, 8,L0|L1}, {SUB_E_A, 2, 8, 8,L0|L1}, - {SUB_H_A, 2, 8, 8,L0|L1}, {SUB_L_A, 2, 8, 8,L0|L1}, - {NEA_V_A, 2, 8, 8,L0|L1}, {NEA_A_A, 2, 8, 8,L0|L1}, - {NEA_B_A, 2, 8, 8,L0|L1}, {NEA_C_A, 2, 8, 8,L0|L1}, - {NEA_D_A, 2, 8, 8,L0|L1}, {NEA_E_A, 2, 8, 8,L0|L1}, - {NEA_H_A, 2, 8, 8,L0|L1}, {NEA_L_A, 2, 8, 8,L0|L1}, - - {SBB_V_A, 2, 8, 8,L0|L1}, {SBB_A_A, 2, 8, 8,L0|L1}, - {SBB_B_A, 2, 8, 8,L0|L1}, {SBB_C_A, 2, 8, 8,L0|L1}, - {SBB_D_A, 2, 8, 8,L0|L1}, {SBB_E_A, 2, 8, 8,L0|L1}, - {SBB_H_A, 2, 8, 8,L0|L1}, {SBB_L_A, 2, 8, 8,L0|L1}, - {EQA_V_A, 2, 8, 8,L0|L1}, {EQA_A_A, 2, 8, 8,L0|L1}, - {EQA_B_A, 2, 8, 8,L0|L1}, {EQA_C_A, 2, 8, 8,L0|L1}, - {EQA_D_A, 2, 8, 8,L0|L1}, {EQA_E_A, 2, 8, 8,L0|L1}, - {EQA_H_A, 2, 8, 8,L0|L1}, {EQA_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_L_A, 2, 8, 8,L0|L1}, + + {&upd7810_device::SBB_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_L_A, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_V_A, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_B_A, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_C_A, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_D_A, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_E_A, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_H_A, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_L_A, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ANA_A_V, 2, 8, 8,L0|L1}, {ANA_A_A, 2, 8, 8,L0|L1}, - {ANA_A_B, 2, 8, 8,L0|L1}, {ANA_A_C, 2, 8, 8,L0|L1}, - {ANA_A_D, 2, 8, 8,L0|L1}, {ANA_A_E, 2, 8, 8,L0|L1}, - {ANA_A_H, 2, 8, 8,L0|L1}, {ANA_A_L, 2, 8, 8,L0|L1}, - - {XRA_A_V, 2, 8, 8,L0|L1}, {XRA_A_A, 2, 8, 8,L0|L1}, - {XRA_A_B, 2, 8, 8,L0|L1}, {XRA_A_C, 2, 8, 8,L0|L1}, - {XRA_A_D, 2, 8, 8,L0|L1}, {XRA_A_E, 2, 8, 8,L0|L1}, - {XRA_A_H, 2, 8, 8,L0|L1}, {XRA_A_L, 2, 8, 8,L0|L1}, - {ORA_A_V, 2, 8, 8,L0|L1}, {ORA_A_A, 2, 8, 8,L0|L1}, - {ORA_A_B, 2, 8, 8,L0|L1}, {ORA_A_C, 2, 8, 8,L0|L1}, - {ORA_A_D, 2, 8, 8,L0|L1}, {ORA_A_E, 2, 8, 8,L0|L1}, - {ORA_A_H, 2, 8, 8,L0|L1}, {ORA_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_L, 2, 8, 8,L0|L1}, + + {&upd7810_device::XRA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_L, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {ADDNC_A_V, 2, 8, 8,L0|L1}, {ADDNC_A_A, 2, 8, 8,L0|L1}, - {ADDNC_A_B, 2, 8, 8,L0|L1}, {ADDNC_A_C, 2, 8, 8,L0|L1}, - {ADDNC_A_D, 2, 8, 8,L0|L1}, {ADDNC_A_E, 2, 8, 8,L0|L1}, - {ADDNC_A_H, 2, 8, 8,L0|L1}, {ADDNC_A_L, 2, 8, 8,L0|L1}, - {GTA_A_V, 2, 8, 8,L0|L1}, {GTA_A_A, 2, 8, 8,L0|L1}, - {GTA_A_B, 2, 8, 8,L0|L1}, {GTA_A_C, 2, 8, 8,L0|L1}, - {GTA_A_D, 2, 8, 8,L0|L1}, {GTA_A_E, 2, 8, 8,L0|L1}, - {GTA_A_H, 2, 8, 8,L0|L1}, {GTA_A_L, 2, 8, 8,L0|L1}, - - {SUBNB_A_V, 2, 8, 8,L0|L1}, {SUBNB_A_A, 2, 8, 8,L0|L1}, - {SUBNB_A_B, 2, 8, 8,L0|L1}, {SUBNB_A_C, 2, 8, 8,L0|L1}, - {SUBNB_A_D, 2, 8, 8,L0|L1}, {SUBNB_A_E, 2, 8, 8,L0|L1}, - {SUBNB_A_H, 2, 8, 8,L0|L1}, {SUBNB_A_L, 2, 8, 8,L0|L1}, - {LTA_A_V, 2, 8, 8,L0|L1}, {LTA_A_A, 2, 8, 8,L0|L1}, - {LTA_A_B, 2, 8, 8,L0|L1}, {LTA_A_C, 2, 8, 8,L0|L1}, - {LTA_A_D, 2, 8, 8,L0|L1}, {LTA_A_E, 2, 8, 8,L0|L1}, - {LTA_A_H, 2, 8, 8,L0|L1}, {LTA_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_L, 2, 8, 8,L0|L1}, + + {&upd7810_device::SUBNB_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_L, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {ADD_A_V, 2, 8, 8,L0|L1}, {ADD_A_A, 2, 8, 8,L0|L1}, - {ADD_A_B, 2, 8, 8,L0|L1}, {ADD_A_C, 2, 8, 8,L0|L1}, - {ADD_A_D, 2, 8, 8,L0|L1}, {ADD_A_E, 2, 8, 8,L0|L1}, - {ADD_A_H, 2, 8, 8,L0|L1}, {ADD_A_L, 2, 8, 8,L0|L1}, - {ONA_A_V, 2, 8, 8,L0|L1}, {ONA_A_A, 2, 8, 8,L0|L1}, - {ONA_A_B, 2, 8, 8,L0|L1}, {ONA_A_C, 2, 8, 8,L0|L1}, - {ONA_A_D, 2, 8, 8,L0|L1}, {ONA_A_E, 2, 8, 8,L0|L1}, - {ONA_A_H, 2, 8, 8,L0|L1}, {ONA_A_L, 2, 8, 8,L0|L1}, - - {ADC_A_V, 2, 8, 8,L0|L1}, {ADC_A_A, 2, 8, 8,L0|L1}, - {ADC_A_B, 2, 8, 8,L0|L1}, {ADC_A_C, 2, 8, 8,L0|L1}, - {ADC_A_D, 2, 8, 8,L0|L1}, {ADC_A_E, 2, 8, 8,L0|L1}, - {ADC_A_H, 2, 8, 8,L0|L1}, {ADC_A_L, 2, 8, 8,L0|L1}, - {OFFA_A_V, 2, 8, 8,L0|L1}, {OFFA_A_A, 2, 8, 8,L0|L1}, - {OFFA_A_B, 2, 8, 8,L0|L1}, {OFFA_A_C, 2, 8, 8,L0|L1}, - {OFFA_A_D, 2, 8, 8,L0|L1}, {OFFA_A_E, 2, 8, 8,L0|L1}, - {OFFA_A_H, 2, 8, 8,L0|L1}, {OFFA_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::ONA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::ONA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ONA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ONA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ONA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ONA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ONA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ONA_A_L, 2, 8, 8,L0|L1}, + + {&upd7810_device::ADC_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::OFFA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::OFFA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::OFFA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::OFFA_A_L, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {SUB_A_V, 2, 8, 8,L0|L1}, {SUB_A_A, 2, 8, 8,L0|L1}, - {SUB_A_B, 2, 8, 8,L0|L1}, {SUB_A_C, 2, 8, 8,L0|L1}, - {SUB_A_D, 2, 8, 8,L0|L1}, {SUB_A_E, 2, 8, 8,L0|L1}, - {SUB_A_H, 2, 8, 8,L0|L1}, {SUB_A_L, 2, 8, 8,L0|L1}, - {NEA_A_V, 2, 8, 8,L0|L1}, {NEA_A_A, 2, 8, 8,L0|L1}, - {NEA_A_B, 2, 8, 8,L0|L1}, {NEA_A_C, 2, 8, 8,L0|L1}, - {NEA_A_D, 2, 8, 8,L0|L1}, {NEA_A_E, 2, 8, 8,L0|L1}, - {NEA_A_H, 2, 8, 8,L0|L1}, {NEA_A_L, 2, 8, 8,L0|L1}, - - {SBB_A_V, 2, 8, 8,L0|L1}, {SBB_A_A, 2, 8, 8,L0|L1}, - {SBB_A_B, 2, 8, 8,L0|L1}, {SBB_A_C, 2, 8, 8,L0|L1}, - {SBB_A_D, 2, 8, 8,L0|L1}, {SBB_A_E, 2, 8, 8,L0|L1}, - {SBB_A_H, 2, 8, 8,L0|L1}, {SBB_A_L, 2, 8, 8,L0|L1}, - {EQA_A_V, 2, 8, 8,L0|L1}, {EQA_A_A, 2, 8, 8,L0|L1}, - {EQA_A_B, 2, 8, 8,L0|L1}, {EQA_A_C, 2, 8, 8,L0|L1}, - {EQA_A_D, 2, 8, 8,L0|L1}, {EQA_A_E, 2, 8, 8,L0|L1}, - {EQA_A_H, 2, 8, 8,L0|L1}, {EQA_A_L, 2, 8, 8,L0|L1} + {&upd7810_device::SUB_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_L, 2, 8, 8,L0|L1}, + + {&upd7810_device::SBB_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_A_V, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_L, 2, 8, 8,L0|L1} }; /* prefix 64 */ -static const struct opcode_s op64_7801[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op64_7801[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ANI_V_xx, 3,11,11,L0|L1}, {ANI_A_xx, 3,11,11,L0|L1}, - {ANI_B_xx, 3,11,11,L0|L1}, {ANI_C_xx, 3,11,11,L0|L1}, - {ANI_D_xx, 3,11,11,L0|L1}, {ANI_E_xx, 3,11,11,L0|L1}, - {ANI_H_xx, 3,11,11,L0|L1}, {ANI_L_xx, 3,11,11,L0|L1}, - - {XRI_V_xx, 3,11,11,L0|L1}, {XRI_A_xx, 3,11,11,L0|L1}, - {XRI_B_xx, 3,11,11,L0|L1}, {XRI_C_xx, 3,11,11,L0|L1}, - {XRI_D_xx, 3,11,11,L0|L1}, {XRI_E_xx, 3,11,11,L0|L1}, - {XRI_H_xx, 3,11,11,L0|L1}, {XRI_L_xx, 3,11,11,L0|L1}, - {ORI_V_xx, 3,11,11,L0|L1}, {ORI_A_xx, 3,11,11,L0|L1}, - {ORI_B_xx, 3,11,11,L0|L1}, {ORI_C_xx, 3,11,11,L0|L1}, - {ORI_D_xx, 3,11,11,L0|L1}, {ORI_E_xx, 3,11,11,L0|L1}, - {ORI_H_xx, 3,11,11,L0|L1}, {ORI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ANI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::ANI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::ANI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::ANI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::ANI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::ANI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::ANI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::ANI_L_xx, 3,11,11,L0|L1}, + + {&upd7810_device::XRI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::XRI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::XRI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::XRI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::XRI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::XRI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::XRI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::XRI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::ORI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::ORI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::ORI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::ORI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::ORI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::ORI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::ORI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::ORI_L_xx, 3,11,11,L0|L1}, /* 0x20 - 0x3F */ - {ADINC_V_xx, 3,11,11,L0|L1}, {ADINC_A_xx, 3,11,11,L0|L1}, - {ADINC_B_xx, 3,11,11,L0|L1}, {ADINC_C_xx, 3,11,11,L0|L1}, - {ADINC_D_xx, 3,11,11,L0|L1}, {ADINC_E_xx, 3,11,11,L0|L1}, - {ADINC_H_xx, 3,11,11,L0|L1}, {ADINC_L_xx, 3,11,11,L0|L1}, - {GTI_V_xx, 3,11,11,L0|L1}, {GTI_A_xx, 3,11,11,L0|L1}, - {GTI_B_xx, 3,11,11,L0|L1}, {GTI_C_xx, 3,11,11,L0|L1}, - {GTI_D_xx, 3,11,11,L0|L1}, {GTI_E_xx, 3,11,11,L0|L1}, - {GTI_H_xx, 3,11,11,L0|L1}, {GTI_L_xx, 3,11,11,L0|L1}, - - {SUINB_V_xx, 3,11,11,L0|L1}, {SUINB_A_xx, 3,11,11,L0|L1}, - {SUINB_B_xx, 3,11,11,L0|L1}, {SUINB_C_xx, 3,11,11,L0|L1}, - {SUINB_D_xx, 3,11,11,L0|L1}, {SUINB_E_xx, 3,11,11,L0|L1}, - {SUINB_H_xx, 3,11,11,L0|L1}, {SUINB_L_xx, 3,11,11,L0|L1}, - {LTI_V_xx, 3,11,11,L0|L1}, {LTI_A_xx, 3,11,11,L0|L1}, - {LTI_B_xx, 3,11,11,L0|L1}, {LTI_C_xx, 3,11,11,L0|L1}, - {LTI_D_xx, 3,11,11,L0|L1}, {LTI_E_xx, 3,11,11,L0|L1}, - {LTI_H_xx, 3,11,11,L0|L1}, {LTI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::ADINC_V_xx, 3,11,11,L0|L1}, {&upd7810_device::ADINC_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::ADINC_B_xx, 3,11,11,L0|L1}, {&upd7810_device::ADINC_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::ADINC_D_xx, 3,11,11,L0|L1}, {&upd7810_device::ADINC_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::ADINC_H_xx, 3,11,11,L0|L1}, {&upd7810_device::ADINC_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::GTI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::GTI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::GTI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::GTI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::GTI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::GTI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::GTI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::GTI_L_xx, 3,11,11,L0|L1}, + + {&upd7810_device::SUINB_V_xx, 3,11,11,L0|L1}, {&upd7810_device::SUINB_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::SUINB_B_xx, 3,11,11,L0|L1}, {&upd7810_device::SUINB_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::SUINB_D_xx, 3,11,11,L0|L1}, {&upd7810_device::SUINB_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::SUINB_H_xx, 3,11,11,L0|L1}, {&upd7810_device::SUINB_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::LTI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::LTI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::LTI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::LTI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::LTI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::LTI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::LTI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::LTI_L_xx, 3,11,11,L0|L1}, /* 0x40 - 0x5F */ - {ADI_V_xx, 3,11,11,L0|L1}, {ADI_A_xx, 3,11,11,L0|L1}, - {ADI_B_xx, 3,11,11,L0|L1}, {ADI_C_xx, 3,11,11,L0|L1}, - {ADI_D_xx, 3,11,11,L0|L1}, {ADI_E_xx, 3,11,11,L0|L1}, - {ADI_H_xx, 3,11,11,L0|L1}, {ADI_L_xx, 3,11,11,L0|L1}, - {ONI_V_xx, 3,11,11,L0|L1}, {ONI_A_xx, 3,11,11,L0|L1}, - {ONI_B_xx, 3,11,11,L0|L1}, {ONI_C_xx, 3,11,11,L0|L1}, - {ONI_D_xx, 3,11,11,L0|L1}, {ONI_E_xx, 3,11,11,L0|L1}, - {ONI_H_xx, 3,11,11,L0|L1}, {ONI_L_xx, 3,11,11,L0|L1}, - - {ACI_V_xx, 3,11,11,L0|L1}, {ACI_A_xx, 3,11,11,L0|L1}, - {ACI_B_xx, 3,11,11,L0|L1}, {ACI_C_xx, 3,11,11,L0|L1}, - {ACI_D_xx, 3,11,11,L0|L1}, {ACI_E_xx, 3,11,11,L0|L1}, - {ACI_H_xx, 3,11,11,L0|L1}, {ACI_L_xx, 3,11,11,L0|L1}, - {OFFI_V_xx, 3,11,11,L0|L1}, {OFFI_A_xx, 3,11,11,L0|L1}, - {OFFI_B_xx, 3,11,11,L0|L1}, {OFFI_C_xx, 3,11,11,L0|L1}, - {OFFI_D_xx, 3,11,11,L0|L1}, {OFFI_E_xx, 3,11,11,L0|L1}, - {OFFI_H_xx, 3,11,11,L0|L1}, {OFFI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::ADI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::ADI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::ADI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::ADI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::ADI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::ADI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::ADI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::ADI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::ONI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::ONI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::ONI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::ONI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::ONI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::ONI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::ONI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::ONI_L_xx, 3,11,11,L0|L1}, + + {&upd7810_device::ACI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::ACI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::ACI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::ACI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::ACI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::ACI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::ACI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::ACI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::OFFI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::OFFI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::OFFI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::OFFI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::OFFI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::OFFI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::OFFI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::OFFI_L_xx, 3,11,11,L0|L1}, /* 0x60 - 0x7F */ - {SUI_V_xx, 3,11,11,L0|L1}, {SUI_A_xx, 3,11,11,L0|L1}, - {SUI_B_xx, 3,11,11,L0|L1}, {SUI_C_xx, 3,11,11,L0|L1}, - {SUI_D_xx, 3,11,11,L0|L1}, {SUI_E_xx, 3,11,11,L0|L1}, - {SUI_H_xx, 3,11,11,L0|L1}, {SUI_L_xx, 3,11,11,L0|L1}, - {NEI_V_xx, 3,11,11,L0|L1}, {NEI_A_xx, 3,11,11,L0|L1}, - {NEI_B_xx, 3,11,11,L0|L1}, {NEI_C_xx, 3,11,11,L0|L1}, - {NEI_D_xx, 3,11,11,L0|L1}, {NEI_E_xx, 3,11,11,L0|L1}, - {NEI_H_xx, 3,11,11,L0|L1}, {NEI_L_xx, 3,11,11,L0|L1}, - - {SBI_V_xx, 3,11,11,L0|L1}, {SBI_A_xx, 3,11,11,L0|L1}, - {SBI_B_xx, 3,11,11,L0|L1}, {SBI_C_xx, 3,11,11,L0|L1}, - {SBI_D_xx, 3,11,11,L0|L1}, {SBI_E_xx, 3,11,11,L0|L1}, - {SBI_H_xx, 3,11,11,L0|L1}, {SBI_L_xx, 3,11,11,L0|L1}, - {EQI_V_xx, 3,11,11,L0|L1}, {EQI_A_xx, 3,11,11,L0|L1}, - {EQI_B_xx, 3,11,11,L0|L1}, {EQI_C_xx, 3,11,11,L0|L1}, - {EQI_D_xx, 3,11,11,L0|L1}, {EQI_E_xx, 3,11,11,L0|L1}, - {EQI_H_xx, 3,11,11,L0|L1}, {EQI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::SUI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::SUI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::SUI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::SUI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::SUI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::SUI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::SUI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::SUI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::NEI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::NEI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::NEI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::NEI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::NEI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::NEI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::NEI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::NEI_L_xx, 3,11,11,L0|L1}, + + {&upd7810_device::SBI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::SBI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::SBI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::SBI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::SBI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::SBI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::SBI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::SBI_L_xx, 3,11,11,L0|L1}, + {&upd7810_device::EQI_V_xx, 3,11,11,L0|L1}, {&upd7810_device::EQI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::EQI_B_xx, 3,11,11,L0|L1}, {&upd7810_device::EQI_C_xx, 3,11,11,L0|L1}, + {&upd7810_device::EQI_D_xx, 3,11,11,L0|L1}, {&upd7810_device::EQI_E_xx, 3,11,11,L0|L1}, + {&upd7810_device::EQI_H_xx, 3,11,11,L0|L1}, {&upd7810_device::EQI_L_xx, 3,11,11,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ANI_PA_xx, 3,17,17,L0|L1}, {ANI_PB_xx, 3,17,17,L0|L1}, - {ANI_PC_xx, 3,17,17,L0|L1}, {ANI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {XRI_PA_xx, 3,17,17,L0|L1}, {XRI_PB_xx, 3,17,17,L0|L1}, - {XRI_PC_xx, 3,17,17,L0|L1}, {XRI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ORI_PA_xx, 3,17,17,L0|L1}, {ORI_PB_xx, 3,17,17,L0|L1}, - {ORI_PC_xx, 3,17,17,L0|L1}, {ORI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ANI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ANI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ANI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ANI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::XRI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::XRI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::XRI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::XRI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ORI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ORI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ORI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ORI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {ADINC_PA_xx, 3,17,17,L0|L1}, {ADINC_PB_xx, 3,17,17,L0|L1}, - {ADINC_PC_xx, 3,17,17,L0|L1}, {ADINC_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {GTI_PA_xx, 3,14,14,L0|L1}, {GTI_PB_xx, 3,14,14,L0|L1}, - {GTI_PC_xx, 3,14,14,L0|L1}, {GTI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {SUINB_PA_xx, 3,17,17,L0|L1}, {SUINB_PB_xx, 3,17,17,L0|L1}, - {SUINB_PC_xx, 3,17,17,L0|L1}, {SUINB_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {LTI_PA_xx, 3,14,14,L0|L1}, {LTI_PB_xx, 3,14,14,L0|L1}, - {LTI_PC_xx, 3,14,14,L0|L1}, {LTI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADINC_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ADINC_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ADINC_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ADINC_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::GTI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::GTI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::GTI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::GTI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::SUINB_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::SUINB_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::SUINB_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::SUINB_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::LTI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::LTI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::LTI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::LTI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {ADI_PA_xx, 3,17,17,L0|L1}, {ADI_PB_xx, 3,17,17,L0|L1}, - {ADI_PC_xx, 3,17,17,L0|L1}, {ADI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ONI_PA_xx, 3,14,14,L0|L1}, {ONI_PB_xx, 3,14,14,L0|L1}, - {ONI_PC_xx, 3,14,14,L0|L1}, {ONI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {ACI_PA_xx, 3,17,17,L0|L1}, {ACI_PB_xx, 3,17,17,L0|L1}, - {ACI_PC_xx, 3,17,17,L0|L1}, {ACI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {OFFI_PA_xx, 3,14,14,L0|L1}, {OFFI_PB_xx, 3,14,14,L0|L1}, - {OFFI_PC_xx, 3,14,14,L0|L1}, {OFFI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ADI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ADI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ADI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ONI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::ONI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::ONI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::ONI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::ACI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ACI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ACI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ACI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::OFFI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::OFFI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::OFFI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {SUI_PA_xx, 3,17,17,L0|L1}, {SUI_PB_xx, 3,17,17,L0|L1}, - {SUI_PC_xx, 3,17,17,L0|L1}, {SUI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {NEI_PA_xx, 3,14,14,L0|L1}, {NEI_PB_xx, 3,14,14,L0|L1}, - {NEI_PC_xx, 3,14,14,L0|L1}, {NEI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {SBI_PA_xx, 3,17,17,L0|L1}, {SBI_PB_xx, 3,17,17,L0|L1}, - {SBI_PC_xx, 3,17,17,L0|L1}, {SBI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {EQI_PA_xx, 3,14,14,L0|L1}, {EQI_PB_xx, 3,14,14,L0|L1}, - {EQI_PC_xx, 3,14,14,L0|L1}, {EQI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::SUI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::SUI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::SUI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::SUI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::NEI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::NEI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::NEI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::NEI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::SBI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::SBI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::SBI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::SBI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::EQI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::EQI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::EQI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::EQI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; /* prefix 70 */ -static const struct opcode_s op70_7801[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op70_7801[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SSPD_w, 4,20,20,L0|L1}, {LSPD_w, 4,20,20,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SBCD_w, 4,20,20,L0|L1}, {LBCD_w, 4,20,20,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SSPD_w, 4,20,20,L0|L1}, {&upd7810_device::LSPD_w, 4,20,20,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SBCD_w, 4,20,20,L0|L1}, {&upd7810_device::LBCD_w, 4,20,20,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SDED_w, 4,20,20,L0|L1}, {LDED_w, 4,20,20,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SHLD_w, 4,20,20,L0|L1}, {LHLD_w, 4,20,20,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SDED_w, 4,20,20,L0|L1}, {&upd7810_device::LDED_w, 4,20,20,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SHLD_w, 4,20,20,L0|L1}, {&upd7810_device::LHLD_w, 4,20,20,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {MOV_V_w, 4,17,17,L0|L1}, {MOV_A_w, 4,17,17,L0|L1}, - {MOV_B_w, 4,17,17,L0|L1}, {MOV_C_w, 4,17,17,L0|L1}, - {MOV_D_w, 4,17,17,L0|L1}, {MOV_E_w, 4,17,17,L0|L1}, - {MOV_H_w, 4,17,17,L0|L1}, {MOV_L_w, 4,17,17,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {MOV_w_V, 4,17,17,L0|L1}, {MOV_w_A, 4,17,17,L0|L1}, - {MOV_w_B, 4,17,17,L0|L1}, {MOV_w_C, 4,17,17,L0|L1}, - {MOV_w_D, 4,17,17,L0|L1}, {MOV_w_E, 4,17,17,L0|L1}, - {MOV_w_H, 4,17,17,L0|L1}, {MOV_w_L, 4,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::MOV_V_w, 4,17,17,L0|L1}, {&upd7810_device::MOV_A_w, 4,17,17,L0|L1}, + {&upd7810_device::MOV_B_w, 4,17,17,L0|L1}, {&upd7810_device::MOV_C_w, 4,17,17,L0|L1}, + {&upd7810_device::MOV_D_w, 4,17,17,L0|L1}, {&upd7810_device::MOV_E_w, 4,17,17,L0|L1}, + {&upd7810_device::MOV_H_w, 4,17,17,L0|L1}, {&upd7810_device::MOV_L_w, 4,17,17,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::MOV_w_V, 4,17,17,L0|L1}, {&upd7810_device::MOV_w_A, 4,17,17,L0|L1}, + {&upd7810_device::MOV_w_B, 4,17,17,L0|L1}, {&upd7810_device::MOV_w_C, 4,17,17,L0|L1}, + {&upd7810_device::MOV_w_D, 4,17,17,L0|L1}, {&upd7810_device::MOV_w_E, 4,17,17,L0|L1}, + {&upd7810_device::MOV_w_H, 4,17,17,L0|L1}, {&upd7810_device::MOV_w_L, 4,17,17,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ANAX_B, 2,11,11,L0|L1}, - {ANAX_D, 2,11,11,L0|L1}, {ANAX_H, 2,11,11,L0|L1}, - {ANAX_Dp, 2,11,11,L0|L1}, {ANAX_Hp, 2,11,11,L0|L1}, - {ANAX_Dm, 2,11,11,L0|L1}, {ANAX_Hm, 2,11,11,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {XRAX_B, 2,11,11,L0|L1}, - {XRAX_D, 2,11,11,L0|L1}, {XRAX_H, 2,11,11,L0|L1}, - {XRAX_Dp, 2,11,11,L0|L1}, {XRAX_Hp, 2,11,11,L0|L1}, - {XRAX_Dm, 2,11,11,L0|L1}, {XRAX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ORAX_B, 2,11,11,L0|L1}, - {ORAX_D, 2,11,11,L0|L1}, {ORAX_H, 2,11,11,L0|L1}, - {ORAX_Dp, 2,11,11,L0|L1}, {ORAX_Hp, 2,11,11,L0|L1}, - {ORAX_Dm, 2,11,11,L0|L1}, {ORAX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ANAX_B, 2,11,11,L0|L1}, + {&upd7810_device::ANAX_D, 2,11,11,L0|L1}, {&upd7810_device::ANAX_H, 2,11,11,L0|L1}, + {&upd7810_device::ANAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ANAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ANAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ANAX_Hm, 2,11,11,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::XRAX_B, 2,11,11,L0|L1}, + {&upd7810_device::XRAX_D, 2,11,11,L0|L1}, {&upd7810_device::XRAX_H, 2,11,11,L0|L1}, + {&upd7810_device::XRAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::XRAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::XRAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::XRAX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ORAX_B, 2,11,11,L0|L1}, + {&upd7810_device::ORAX_D, 2,11,11,L0|L1}, {&upd7810_device::ORAX_H, 2,11,11,L0|L1}, + {&upd7810_device::ORAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ORAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ORAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ORAX_Hm, 2,11,11,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2, 8, 8,L0|L1}, {ADDNCX_B, 2,11,11,L0|L1}, - {ADDNCX_D, 2,11,11,L0|L1}, {ADDNCX_H, 2,11,11,L0|L1}, - {ADDNCX_Dp, 2,11,11,L0|L1}, {ADDNCX_Hp, 2,11,11,L0|L1}, - {ADDNCX_Dm, 2,11,11,L0|L1}, {ADDNCX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {GTAX_B, 2,11,11,L0|L1}, - {GTAX_D, 2,11,11,L0|L1}, {GTAX_H, 2,11,11,L0|L1}, - {GTAX_Dp, 2,11,11,L0|L1}, {GTAX_Hp, 2,11,11,L0|L1}, - {GTAX_Dm, 2,11,11,L0|L1}, {GTAX_Hm, 2,11,11,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SUBNBX_B, 2,11,11,L0|L1}, - {SUBNBX_D, 2,11,11,L0|L1}, {SUBNBX_H, 2,11,11,L0|L1}, - {SUBNBX_Dp, 2,11,11,L0|L1}, {SUBNBX_Hp, 2,11,11,L0|L1}, - {SUBNBX_Dm, 2,11,11,L0|L1}, {SUBNBX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {LTAX_B, 2,11,11,L0|L1}, - {LTAX_D, 2,11,11,L0|L1}, {LTAX_H, 2,11,11,L0|L1}, - {LTAX_Dp, 2,11,11,L0|L1}, {LTAX_Hp, 2,11,11,L0|L1}, - {LTAX_Dm, 2,11,11,L0|L1}, {LTAX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNCX_B, 2,11,11,L0|L1}, + {&upd7810_device::ADDNCX_D, 2,11,11,L0|L1}, {&upd7810_device::ADDNCX_H, 2,11,11,L0|L1}, + {&upd7810_device::ADDNCX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ADDNCX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ADDNCX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ADDNCX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::GTAX_B, 2,11,11,L0|L1}, + {&upd7810_device::GTAX_D, 2,11,11,L0|L1}, {&upd7810_device::GTAX_H, 2,11,11,L0|L1}, + {&upd7810_device::GTAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::GTAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::GTAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::GTAX_Hm, 2,11,11,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNBX_B, 2,11,11,L0|L1}, + {&upd7810_device::SUBNBX_D, 2,11,11,L0|L1}, {&upd7810_device::SUBNBX_H, 2,11,11,L0|L1}, + {&upd7810_device::SUBNBX_Dp, 2,11,11,L0|L1}, {&upd7810_device::SUBNBX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::SUBNBX_Dm, 2,11,11,L0|L1}, {&upd7810_device::SUBNBX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::LTAX_B, 2,11,11,L0|L1}, + {&upd7810_device::LTAX_D, 2,11,11,L0|L1}, {&upd7810_device::LTAX_H, 2,11,11,L0|L1}, + {&upd7810_device::LTAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::LTAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::LTAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::LTAX_Hm, 2,11,11,L0|L1}, /* 0xC0 - 0xDF */ - {illegal2, 2, 8, 8,L0|L1}, {ADDX_B, 2,11,11,L0|L1}, - {ADDX_D, 2,11,11,L0|L1}, {ADDX_H, 2,11,11,L0|L1}, - {ADDX_Dp, 2,11,11,L0|L1}, {ADDX_Hp, 2,11,11,L0|L1}, - {ADDX_Dm, 2,11,11,L0|L1}, {ADDX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ONAX_B, 2,11,11,L0|L1}, - {ONAX_D, 2,11,11,L0|L1}, {ONAX_H, 2,11,11,L0|L1}, - {ONAX_Dp, 2,11,11,L0|L1}, {ONAX_Hp, 2,11,11,L0|L1}, - {ONAX_Dm, 2,11,11,L0|L1}, {ONAX_Hm, 2,11,11,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {ADCX_B, 2,11,11,L0|L1}, - {ADCX_D, 2,11,11,L0|L1}, {ADCX_H, 2,11,11,L0|L1}, - {ADCX_Dp, 2,11,11,L0|L1}, {ADCX_Hp, 2,11,11,L0|L1}, - {ADCX_Dm, 2,11,11,L0|L1}, {ADCX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {OFFAX_B, 2,11,11,L0|L1}, - {OFFAX_D, 2,11,11,L0|L1}, {OFFAX_H, 2,11,11,L0|L1}, - {OFFAX_Dp, 2,11,11,L0|L1}, {OFFAX_Hp, 2,11,11,L0|L1}, - {OFFAX_Dm, 2,11,11,L0|L1}, {OFFAX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADDX_B, 2,11,11,L0|L1}, + {&upd7810_device::ADDX_D, 2,11,11,L0|L1}, {&upd7810_device::ADDX_H, 2,11,11,L0|L1}, + {&upd7810_device::ADDX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ADDX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ADDX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ADDX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ONAX_B, 2,11,11,L0|L1}, + {&upd7810_device::ONAX_D, 2,11,11,L0|L1}, {&upd7810_device::ONAX_H, 2,11,11,L0|L1}, + {&upd7810_device::ONAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ONAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ONAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ONAX_Hm, 2,11,11,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADCX_B, 2,11,11,L0|L1}, + {&upd7810_device::ADCX_D, 2,11,11,L0|L1}, {&upd7810_device::ADCX_H, 2,11,11,L0|L1}, + {&upd7810_device::ADCX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ADCX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ADCX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ADCX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::OFFAX_B, 2,11,11,L0|L1}, + {&upd7810_device::OFFAX_D, 2,11,11,L0|L1}, {&upd7810_device::OFFAX_H, 2,11,11,L0|L1}, + {&upd7810_device::OFFAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::OFFAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::OFFAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::OFFAX_Hm, 2,11,11,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {SUBX_B, 2,11,11,L0|L1}, - {SUBX_D, 2,11,11,L0|L1}, {SUBX_H, 2,11,11,L0|L1}, - {SUBX_Dp, 2,11,11,L0|L1}, {SUBX_Hp, 2,11,11,L0|L1}, - {SUBX_Dm, 2,11,11,L0|L1}, {SUBX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {NEAX_B, 2,11,11,L0|L1}, - {NEAX_D, 2,11,11,L0|L1}, {NEAX_H, 2,11,11,L0|L1}, - {NEAX_Dp, 2,11,11,L0|L1}, {NEAX_Hp, 2,11,11,L0|L1}, - {NEAX_Dm, 2,11,11,L0|L1}, {NEAX_Hm, 2,11,11,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SBBX_B, 2,11,11,L0|L1}, - {SBBX_D, 2,11,11,L0|L1}, {SBBX_H, 2,11,11,L0|L1}, - {SBBX_Dp, 2,11,11,L0|L1}, {SBBX_Hp, 2,11,11,L0|L1}, - {SBBX_Dm, 2,11,11,L0|L1}, {SBBX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {EQAX_B, 2,11,11,L0|L1}, - {EQAX_D, 2,11,11,L0|L1}, {EQAX_H, 2,11,11,L0|L1}, - {EQAX_Dp, 2,11,11,L0|L1}, {EQAX_Hp, 2,11,11,L0|L1}, - {EQAX_Dm, 2,11,11,L0|L1}, {EQAX_Hm, 2,11,11,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUBX_B, 2,11,11,L0|L1}, + {&upd7810_device::SUBX_D, 2,11,11,L0|L1}, {&upd7810_device::SUBX_H, 2,11,11,L0|L1}, + {&upd7810_device::SUBX_Dp, 2,11,11,L0|L1}, {&upd7810_device::SUBX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::SUBX_Dm, 2,11,11,L0|L1}, {&upd7810_device::SUBX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::NEAX_B, 2,11,11,L0|L1}, + {&upd7810_device::NEAX_D, 2,11,11,L0|L1}, {&upd7810_device::NEAX_H, 2,11,11,L0|L1}, + {&upd7810_device::NEAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::NEAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::NEAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::NEAX_Hm, 2,11,11,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SBBX_B, 2,11,11,L0|L1}, + {&upd7810_device::SBBX_D, 2,11,11,L0|L1}, {&upd7810_device::SBBX_H, 2,11,11,L0|L1}, + {&upd7810_device::SBBX_Dp, 2,11,11,L0|L1}, {&upd7810_device::SBBX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::SBBX_Dm, 2,11,11,L0|L1}, {&upd7810_device::SBBX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::EQAX_B, 2,11,11,L0|L1}, + {&upd7810_device::EQAX_D, 2,11,11,L0|L1}, {&upd7810_device::EQAX_H, 2,11,11,L0|L1}, + {&upd7810_device::EQAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::EQAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::EQAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::EQAX_Hm, 2,11,11,L0|L1} }; /* prefix 74 */ -static const struct opcode_s op74_7801[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op74_7801[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ANAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {XRAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ORAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ANAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::XRAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ORAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {ADDNCW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {GTAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {SUBNBW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {LTAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNCW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::GTAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::SUBNBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::LTAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {ADDW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ONAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {ADCW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {OFFAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ONAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::ADCW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {SUBW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {NEAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {SBBW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {EQAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::SUBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::NEAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::SBBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::EQAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; -static const struct opcode_s opXX_7801[256] = +const struct upd7810_device::opcode_s upd7810_device::s_opXX_7801[256] = { /* 0x00 - 0x1F */ - {NOP, 1, 4, 4,L0|L1}, {HALT, 1, 6, 6,L0|L1}, - {INX_SP, 1, 7, 7,L0|L1}, {DCX_SP, 1, 7, 7,L0|L1}, - {LXI_S_w, 3,10,10,L0|L1}, {ANIW_wa_xx, 3,16,16,L0|L1}, - {illegal, 1, 4, 4,L0|L1}, {ANI_A_xx, 2, 7, 7,L0|L1}, - {RET, 1,11,11,L0|L1}, {SIO, 1, 4, 4,L0|L1}, - {MOV_A_B, 1, 4, 4,L0|L1}, {MOV_A_C, 1, 4, 4,L0|L1}, - {MOV_A_D, 1, 4, 4,L0|L1}, {MOV_A_E, 1, 4, 4,L0|L1}, - {MOV_A_H, 1, 4, 4,L0|L1}, {MOV_A_L, 1, 4, 4,L0|L1}, - - {EXA, 1, 4, 4,L0|L1}, {EXX, 1, 4, 4,L0|L1}, - {INX_BC, 1, 7, 7,L0|L1}, {DCX_BC, 1, 7, 7,L0|L1}, - {LXI_B_w, 3,10,10,L0|L1}, {ORIW_wa_xx, 3,16,16,L0|L1}, - {XRI_A_xx, 2, 7, 7,L0|L1}, {ORI_A_xx, 2, 7, 7,L0|L1}, - {RETS, 1,11,11,L0|L1}, {STM_7801, 1, 4, 4,L0|L1}, - {MOV_B_A, 1, 4, 4,L0|L1}, {MOV_C_A, 1, 4, 4,L0|L1}, - {MOV_D_A, 1, 4, 4,L0|L1}, {MOV_E_A, 1, 4, 4,L0|L1}, - {MOV_H_A, 1, 4, 4,L0|L1}, {MOV_L_A, 1, 4, 4,L0|L1}, + {&upd7810_device::NOP, 1, 4, 4,L0|L1}, {&upd7810_device::HALT, 1, 6, 6,L0|L1}, + {&upd7810_device::INX_SP, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_SP, 1, 7, 7,L0|L1}, + {&upd7810_device::LXI_S_w, 3,10,10,L0|L1}, {&upd7810_device::ANIW_wa_xx, 3,16,16,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::ANI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::RET, 1,11,11,L0|L1}, {&upd7810_device::SIO, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_A_B, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_A_C, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_A_D, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_A_E, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_A_H, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_A_L, 1, 4, 4,L0|L1}, + + {&upd7810_device::EXA, 1, 4, 4,L0|L1}, {&upd7810_device::EXX, 1, 4, 4,L0|L1}, + {&upd7810_device::INX_BC, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_BC, 1, 7, 7,L0|L1}, + {&upd7810_device::LXI_B_w, 3,10,10,L0|L1}, {&upd7810_device::ORIW_wa_xx, 3,16,16,L0|L1}, + {&upd7810_device::XRI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::ORI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::RETS, 1,11,11,L0|L1}, {&upd7810_device::STM_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_B_A, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_C_A, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_D_A, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_E_A, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_H_A, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_L_A, 1, 4, 4,L0|L1}, /* 0x20 - 0x3F */ - {INRW_wa_7801, 2,13,13,L0|L1}, {TABLE, 1,19,19,L0|L1}, - {INX_DE, 1, 7, 7,L0|L1}, {DCX_DE, 1, 7, 7,L0|L1}, - {LXI_D_w, 3,10,10,L0|L1}, {GTIW_wa_xx, 3,13,13,L0|L1}, - {ADINC_A_xx, 2, 7, 7,L0|L1}, {GTI_A_xx, 2, 7, 7,L0|L1}, - {LDAW_wa, 2,10,10,L0|L1}, {LDAX_B, 1, 7, 7,L0|L1}, - {LDAX_D, 1, 7, 7,L0|L1}, {LDAX_H, 1, 7, 7,L0|L1}, - {LDAX_Dp, 1, 7, 7,L0|L1}, {LDAX_Hp, 1, 7, 7,L0|L1}, - {LDAX_Dm, 1, 7, 7,L0|L1}, {LDAX_Hm, 1, 7, 7,L0|L1}, - - {DCRW_wa_7801, 2,13,13,L0|L1}, {BLOCK, 1,13,13,L0|L1}, - {INX_HL, 1, 7, 7,L0|L1}, {DCX_HL, 1, 7, 7,L0|L1}, - {LXI_H_w, 3,10,10, L1}, {LTIW_wa_xx, 3,13,13,L0|L1}, - {SUINB_A_xx, 2, 7, 7,L0|L1}, {LTI_A_xx, 2, 7, 7,L0|L1}, - {STAW_wa, 2,10,10,L0|L1}, {STAX_B, 1, 7, 7,L0|L1}, - {STAX_D, 1, 7, 7,L0|L1}, {STAX_H, 1, 7, 7,L0|L1}, - {STAX_Dp, 1, 7, 7,L0|L1}, {STAX_Hp, 1, 7, 7,L0|L1}, - {STAX_Dm, 1, 7, 7,L0|L1}, {STAX_Hm, 1, 7, 7,L0|L1}, + {&upd7810_device::INRW_wa_7801, 2,13,13,L0|L1}, {&upd7810_device::TABLE, 1,19,19,L0|L1}, + {&upd7810_device::INX_DE, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_DE, 1, 7, 7,L0|L1}, + {&upd7810_device::LXI_D_w, 3,10,10,L0|L1}, {&upd7810_device::GTIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::ADINC_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::GTI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::LDAW_wa, 2,10,10,L0|L1}, {&upd7810_device::LDAX_B, 1, 7, 7,L0|L1}, + {&upd7810_device::LDAX_D, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_H, 1, 7, 7,L0|L1}, + {&upd7810_device::LDAX_Dp, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_Hp, 1, 7, 7,L0|L1}, + {&upd7810_device::LDAX_Dm, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_Hm, 1, 7, 7,L0|L1}, + + {&upd7810_device::DCRW_wa_7801, 2,13,13,L0|L1}, {&upd7810_device::BLOCK, 1,13,13,L0|L1}, + {&upd7810_device::INX_HL, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_HL, 1, 7, 7,L0|L1}, + {&upd7810_device::LXI_H_w, 3,10,10, L1}, {&upd7810_device::LTIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SUINB_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::LTI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::STAW_wa, 2,10,10,L0|L1}, {&upd7810_device::STAX_B, 1, 7, 7,L0|L1}, + {&upd7810_device::STAX_D, 1, 7, 7,L0|L1}, {&upd7810_device::STAX_H, 1, 7, 7,L0|L1}, + {&upd7810_device::STAX_Dp, 1, 7, 7,L0|L1}, {&upd7810_device::STAX_Hp, 1, 7, 7,L0|L1}, + {&upd7810_device::STAX_Dm, 1, 7, 7,L0|L1}, {&upd7810_device::STAX_Hm, 1, 7, 7,L0|L1}, /* 0x40 - 0x5F */ - {illegal, 1, 4, 4,L0|L1}, {INR_A_7801, 1, 4, 4,L0|L1}, - {INR_B_7801, 1, 4, 4,L0|L1}, {INR_C_7801, 1, 4, 4,L0|L1}, - {CALL_w, 3,16,16,L0|L1}, {ONIW_wa_xx, 3,13,13,L0|L1}, - {ADI_A_xx, 2, 7, 7,L0|L1}, {ONI_A_xx, 2, 7, 7,L0|L1}, - {PRE_48, 1, 0, 0,L0|L1}, {MVIX_BC_xx, 2,10,10,L0|L1}, - {MVIX_DE_xx, 2,10,10,L0|L1}, {MVIX_HL_xx, 2,10,10,L0|L1}, - {PRE_4C, 1, 0, 0,L0|L1}, {PRE_4D, 1, 0, 0,L0|L1}, - {JRE, 2,17,17,L0|L1}, {JRE, 2,17,17,L0|L1}, - - {illegal, 1, 4, 4,L0|L1}, {DCR_A_7801, 1, 4, 4,L0|L1}, - {DCR_B_7801, 1, 4, 4,L0|L1}, {DCR_C_7801, 1, 4, 4,L0|L1}, - {JMP_w, 3,10,10,L0|L1}, {OFFIW_wa_xx, 3,13,13,L0|L1}, - {ACI_A_xx, 2, 7, 7,L0|L1}, {OFFI_A_xx, 2, 7, 7,L0|L1}, - {BIT_0_wa, 2,10,10,L0|L1}, {BIT_1_wa, 2,10,10,L0|L1}, - {BIT_2_wa, 2,10,10,L0|L1}, {BIT_3_wa, 2,10,10,L0|L1}, - {BIT_4_wa, 2,10,10,L0|L1}, {BIT_5_wa, 2,10,10,L0|L1}, - {BIT_6_wa, 2,10,10,L0|L1}, {BIT_7_wa, 2,10,10,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::INR_A_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::INR_B_7801, 1, 4, 4,L0|L1}, {&upd7810_device::INR_C_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::CALL_w, 3,16,16,L0|L1}, {&upd7810_device::ONIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::ADI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::ONI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::PRE_48, 1, 0, 0,L0|L1}, {&upd7810_device::MVIX_BC_xx, 2,10,10,L0|L1}, + {&upd7810_device::MVIX_DE_xx, 2,10,10,L0|L1}, {&upd7810_device::MVIX_HL_xx, 2,10,10,L0|L1}, + {&upd7810_device::PRE_4C, 1, 0, 0,L0|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0|L1}, + {&upd7810_device::JRE, 2,17,17,L0|L1}, {&upd7810_device::JRE, 2,17,17,L0|L1}, + + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_A_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::DCR_B_7801, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_C_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::JMP_w, 3,10,10,L0|L1}, {&upd7810_device::OFFIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::ACI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::BIT_0_wa, 2,10,10,L0|L1}, {&upd7810_device::BIT_1_wa, 2,10,10,L0|L1}, + {&upd7810_device::BIT_2_wa, 2,10,10,L0|L1}, {&upd7810_device::BIT_3_wa, 2,10,10,L0|L1}, + {&upd7810_device::BIT_4_wa, 2,10,10,L0|L1}, {&upd7810_device::BIT_5_wa, 2,10,10,L0|L1}, + {&upd7810_device::BIT_6_wa, 2,10,10,L0|L1}, {&upd7810_device::BIT_7_wa, 2,10,10,L0|L1}, /* 0x60 - 0x7F */ - {PRE_60, 1, 0, 0,L0|L1}, {DAA, 1, 4, 4,L0|L1}, - {RETI, 1,15,15,L0|L1}, {CALB, 2,13,13,L0|L1}, - {PRE_64, 1, 0, 0,L0|L1}, {NEIW_wa_xx, 3,13,13,L0|L1}, - {SUI_A_xx, 2, 7, 7,L0|L1}, {NEI_A_xx, 2, 7, 7,L0|L1}, - {MVI_V_xx, 2, 7, 7,L0|L1}, {MVI_A_xx, 2, 7, 7,L0 }, - {MVI_B_xx, 2, 7, 7,L0|L1}, {MVI_C_xx, 2, 7, 7,L0|L1}, - {MVI_D_xx, 2, 7, 7,L0|L1}, {MVI_E_xx, 2, 7, 7,L0|L1}, - {MVI_H_xx, 2, 7, 7,L0|L1}, {MVI_L_xx, 2, 7, 7, L1}, - - {PRE_70, 1, 0, 0,L0|L1}, {MVIW_wa_xx, 3,13,13,L0|L1}, - {SOFTI, 1,19,19,L0|L1}, {JB, 1, 4, 4,L0|L1}, - {PRE_74, 1, 0, 0,L0|L1}, {EQIW_wa_xx, 3,13,13,L0|L1}, - {SBI_A_xx, 2, 7, 7,L0|L1}, {EQI_A_xx, 2, 7, 7,L0|L1}, - {CALF, 2,16,16,L0|L1}, {CALF, 2,16,16,L0|L1}, - {CALF, 2,16,16,L0|L1}, {CALF, 2,16,16,L0|L1}, - {CALF, 2,16,16,L0|L1}, {CALF, 2,16,16,L0|L1}, - {CALF, 2,16,16,L0|L1}, {CALF, 2,16,16,L0|L1}, + {&upd7810_device::PRE_60, 1, 0, 0,L0|L1}, {&upd7810_device::DAA, 1, 4, 4,L0|L1}, + {&upd7810_device::RETI, 1,15,15,L0|L1}, {&upd7810_device::CALB, 2,13,13,L0|L1}, + {&upd7810_device::PRE_64, 1, 0, 0,L0|L1}, {&upd7810_device::NEIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SUI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::NEI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::MVI_V_xx, 2, 7, 7,L0|L1}, {&upd7810_device::MVI_A_xx, 2, 7, 7,L0 }, + {&upd7810_device::MVI_B_xx, 2, 7, 7,L0|L1}, {&upd7810_device::MVI_C_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::MVI_D_xx, 2, 7, 7,L0|L1}, {&upd7810_device::MVI_E_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::MVI_H_xx, 2, 7, 7,L0|L1}, {&upd7810_device::MVI_L_xx, 2, 7, 7, L1}, + + {&upd7810_device::PRE_70, 1, 0, 0,L0|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SOFTI, 1,19,19,L0|L1}, {&upd7810_device::JB, 1, 4, 4,L0|L1}, + {&upd7810_device::PRE_74, 1, 0, 0,L0|L1}, {&upd7810_device::EQIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SBI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::EQI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::CALF, 2,16,16,L0|L1}, {&upd7810_device::CALF, 2,16,16,L0|L1}, + {&upd7810_device::CALF, 2,16,16,L0|L1}, {&upd7810_device::CALF, 2,16,16,L0|L1}, + {&upd7810_device::CALF, 2,16,16,L0|L1}, {&upd7810_device::CALF, 2,16,16,L0|L1}, + {&upd7810_device::CALF, 2,16,16,L0|L1}, {&upd7810_device::CALF, 2,16,16,L0|L1}, /* 0x80 - 0x9F */ - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, /* 0xA0 - 0xBF */ - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, /* 0xC0 - 0xDF */ - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, /* 0xE0 - 0xFF */ - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1}, - {JR, 1,13,13,L0|L1}, {JR, 1,13,13,L0|L1} + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1}, + {&upd7810_device::JR, 1,13,13,L0|L1}, {&upd7810_device::JR, 1,13,13,L0|L1} }; /*********************************************************************** @@ -4792,1248 +3753,1248 @@ static const struct opcode_s opXX_7801[256] = * **********************************************************************/ -static const struct opcode_s op48_78c05[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op48_78c05[256] = { /* 0x00 - 0x1F */ - {SKIT_F0, 2, 8, 8,L0|L1}, {SKIT_FT0, 2, 8, 8,L0|L1}, - {SKIT_F1, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SKIT_FST, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SK_CY, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SK_Z, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {PUSH_VA, 2,17,17,L0|L1}, {POP_VA, 2,14,14,L0|L1}, - - {SKNIT_F0, 2, 8, 8,L0|L1}, {SKNIT_FT0, 2, 8, 8,L0|L1}, - {SKNIT_F1, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SKNIT_FST, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SKN_CY, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SKN_Z, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {PUSH_BC, 2,17,17,L0|L1}, {POP_BC, 2,14,14,L0|L1}, + {&upd7810_device::SKIT_F0, 2, 8, 8,L0|L1}, {&upd7810_device::SKIT_FT0, 2, 8, 8,L0|L1}, + {&upd7810_device::SKIT_F1, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SKIT_FST, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SK_CY, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SK_Z, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::PUSH_VA, 2,17,17,L0|L1}, {&upd7810_device::POP_VA, 2,14,14,L0|L1}, + + {&upd7810_device::SKNIT_F0, 2, 8, 8,L0|L1}, {&upd7810_device::SKNIT_FT0, 2, 8, 8,L0|L1}, + {&upd7810_device::SKNIT_F1, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SKNIT_FST, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SKN_CY, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SKN_Z, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::PUSH_BC, 2,17,17,L0|L1}, {&upd7810_device::POP_BC, 2,14,14,L0|L1}, /* 0x20 - 0x3F */ - {EI, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {DI, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {CLC, 2, 8, 8,L0|L1}, {STC, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {PEX, 2,11,11,L0|L1}, - {PUSH_DE, 2,17,17,L0|L1}, {POP_DE, 2,14,14,L0|L1}, - - {RLL_A, 2, 8, 8,L0|L1}, {RLR_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {RLD, 2,17,17,L0|L1}, {RRD, 2,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {PER, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {PUSH_HL, 2,17,17,L0|L1}, {POP_HL, 2,14,14,L0|L1}, + {&upd7810_device::EI, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::DI, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::CLC, 2, 8, 8,L0|L1}, {&upd7810_device::STC, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::PEX, 2,11,11,L0|L1}, + {&upd7810_device::PUSH_DE, 2,17,17,L0|L1}, {&upd7810_device::POP_DE, 2,14,14,L0|L1}, + + {&upd7810_device::RLL_A, 2, 8, 8,L0|L1}, {&upd7810_device::RLR_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::RLD, 2,17,17,L0|L1}, {&upd7810_device::RRD, 2,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::PER, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::PUSH_HL, 2,17,17,L0|L1}, {&upd7810_device::POP_HL, 2,14,14,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; -static const struct opcode_s op4C_78c05[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op4C_78c05[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {MOV_A_PA, 2,10,10,L0|L1}, {MOV_A_PB, 2,10,10,L0|L1}, - {MOV_A_PC, 2,10,10,L0|L1}, {MOV_A_MKL, 2,10,10,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {MOV_A_S, 2,10,10,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::MOV_A_PA, 2,10,10,L0|L1}, {&upd7810_device::MOV_A_PB, 2,10,10,L0|L1}, + {&upd7810_device::MOV_A_PC, 2,10,10,L0|L1}, {&upd7810_device::MOV_A_MKL, 2,10,10,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::MOV_A_S, 2,10,10,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; /* prefix 4D */ -static const struct opcode_s op4D_78c05[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op4D_78c05[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {MOV_PA_A, 2,10,10,L0|L1}, {MOV_PB_A, 2,10,10,L0|L1}, - {MOV_PC_A, 2,10,10,L0|L1}, {MOV_MKL_A, 2,10,10,L0|L1}, - {MOV_MB_A, 2,10,10,L0|L1}, {MOV_MC_A, 2,10,10,L0|L1}, - {MOV_TM0_A, 2,10,10,L0|L1}, {MOV_TM1_A, 2,10,10,L0|L1}, - {MOV_S_A, 2,10,10,L0|L1}, {MOV_TMM_A, 2,10,10,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::MOV_PA_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_PB_A, 2,10,10,L0|L1}, + {&upd7810_device::MOV_PC_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_MKL_A, 2,10,10,L0|L1}, + {&upd7810_device::MOV_MB_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_MC_A, 2,10,10,L0|L1}, + {&upd7810_device::MOV_TM0_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_TM1_A, 2,10,10,L0|L1}, + {&upd7810_device::MOV_S_A, 2,10,10,L0|L1}, {&upd7810_device::MOV_TMM_A, 2,10,10,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; /* prefix 60 */ -static const struct opcode_s op60_78c05[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op60_78c05[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ANA_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {XRA_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ORA_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2, 8, 8,L0|L1}, {ADDNC_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {GTA_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SUBNB_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {LTA_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {ADD_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {ADC_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {SUB_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {NEA_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SBB_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {EQA_A_A, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ANA_A_A, 2, 8, 8,L0|L1}, - {ANA_A_B, 2, 8, 8,L0|L1}, {ANA_A_C, 2, 8, 8,L0|L1}, - {ANA_A_D, 2, 8, 8,L0|L1}, {ANA_A_E, 2, 8, 8,L0|L1}, - {ANA_A_H, 2, 8, 8,L0|L1}, {ANA_A_L, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {XRA_A_A, 2, 8, 8,L0|L1}, - {XRA_A_B, 2, 8, 8,L0|L1}, {XRA_A_C, 2, 8, 8,L0|L1}, - {XRA_A_D, 2, 8, 8,L0|L1}, {XRA_A_E, 2, 8, 8,L0|L1}, - {XRA_A_H, 2, 8, 8,L0|L1}, {XRA_A_L, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ORA_A_A, 2, 8, 8,L0|L1}, - {ORA_A_B, 2, 8, 8,L0|L1}, {ORA_A_C, 2, 8, 8,L0|L1}, - {ORA_A_D, 2, 8, 8,L0|L1}, {ORA_A_E, 2, 8, 8,L0|L1}, - {ORA_A_H, 2, 8, 8,L0|L1}, {ORA_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ANA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ANA_A_L, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::XRA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::XRA_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ORA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ORA_A_L, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2, 8, 8,L0|L1}, {ADDNC_A_A, 2, 8, 8,L0|L1}, - {ADDNC_A_B, 2, 8, 8,L0|L1}, {ADDNC_A_C, 2, 8, 8,L0|L1}, - {ADDNC_A_D, 2, 8, 8,L0|L1}, {ADDNC_A_E, 2, 8, 8,L0|L1}, - {ADDNC_A_H, 2, 8, 8,L0|L1}, {ADDNC_A_L, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {GTA_A_A, 2, 8, 8,L0|L1}, - {GTA_A_B, 2, 8, 8,L0|L1}, {GTA_A_C, 2, 8, 8,L0|L1}, - {GTA_A_D, 2, 8, 8,L0|L1}, {GTA_A_E, 2, 8, 8,L0|L1}, - {GTA_A_H, 2, 8, 8,L0|L1}, {GTA_A_L, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SUBNB_A_A, 2, 8, 8,L0|L1}, - {SUBNB_A_B, 2, 8, 8,L0|L1}, {SUBNB_A_C, 2, 8, 8,L0|L1}, - {SUBNB_A_D, 2, 8, 8,L0|L1}, {SUBNB_A_E, 2, 8, 8,L0|L1}, - {SUBNB_A_H, 2, 8, 8,L0|L1}, {SUBNB_A_L, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {LTA_A_A, 2, 8, 8,L0|L1}, - {LTA_A_B, 2, 8, 8,L0|L1}, {LTA_A_C, 2, 8, 8,L0|L1}, - {LTA_A_D, 2, 8, 8,L0|L1}, {LTA_A_E, 2, 8, 8,L0|L1}, - {LTA_A_H, 2, 8, 8,L0|L1}, {LTA_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNC_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNC_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::GTA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::GTA_A_L, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::SUBNB_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNB_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::LTA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::LTA_A_L, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {illegal2, 2, 8, 8,L0|L1}, {ADD_A_A, 2, 8, 8,L0|L1}, - {ADD_A_B, 2, 8, 8,L0|L1}, {ADD_A_C, 2, 8, 8,L0|L1}, - {ADD_A_D, 2, 8, 8,L0|L1}, {ADD_A_E, 2, 8, 8,L0|L1}, - {ADD_A_H, 2, 8, 8,L0|L1}, {ADD_A_L, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ONA_A_A, 2, 8, 8,L0|L1}, - {ONA_A_B, 2, 8, 8,L0|L1}, {ONA_A_C, 2, 8, 8,L0|L1}, - {ONA_A_D, 2, 8, 8,L0|L1}, {ONA_A_E, 2, 8, 8,L0|L1}, - {ONA_A_H, 2, 8, 8,L0|L1}, {ONA_A_L, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {ADC_A_A, 2, 8, 8,L0|L1}, - {ADC_A_B, 2, 8, 8,L0|L1}, {ADC_A_C, 2, 8, 8,L0|L1}, - {ADC_A_D, 2, 8, 8,L0|L1}, {ADC_A_E, 2, 8, 8,L0|L1}, - {ADC_A_H, 2, 8, 8,L0|L1}, {ADC_A_L, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {OFFA_A_A, 2, 8, 8,L0|L1}, - {OFFA_A_B, 2, 8, 8,L0|L1}, {OFFA_A_C, 2, 8, 8,L0|L1}, - {OFFA_A_D, 2, 8, 8,L0|L1}, {OFFA_A_E, 2, 8, 8,L0|L1}, - {OFFA_A_H, 2, 8, 8,L0|L1}, {OFFA_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ADD_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ADD_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ONA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ONA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ONA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ONA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ONA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ONA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ONA_A_L, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::ADC_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::ADC_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::OFFA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::OFFA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::OFFA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::OFFA_A_L, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {SUB_A_A, 2, 8, 8,L0|L1}, - {SUB_A_B, 2, 8, 8,L0|L1}, {SUB_A_C, 2, 8, 8,L0|L1}, - {SUB_A_D, 2, 8, 8,L0|L1}, {SUB_A_E, 2, 8, 8,L0|L1}, - {SUB_A_H, 2, 8, 8,L0|L1}, {SUB_A_L, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {NEA_A_A, 2, 8, 8,L0|L1}, - {NEA_A_B, 2, 8, 8,L0|L1}, {NEA_A_C, 2, 8, 8,L0|L1}, - {NEA_A_D, 2, 8, 8,L0|L1}, {NEA_A_E, 2, 8, 8,L0|L1}, - {NEA_A_H, 2, 8, 8,L0|L1}, {NEA_A_L, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SBB_A_A, 2, 8, 8,L0|L1}, - {SBB_A_B, 2, 8, 8,L0|L1}, {SBB_A_C, 2, 8, 8,L0|L1}, - {SBB_A_D, 2, 8, 8,L0|L1}, {SBB_A_E, 2, 8, 8,L0|L1}, - {SBB_A_H, 2, 8, 8,L0|L1}, {SBB_A_L, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {EQA_A_A, 2, 8, 8,L0|L1}, - {EQA_A_B, 2, 8, 8,L0|L1}, {EQA_A_C, 2, 8, 8,L0|L1}, - {EQA_A_D, 2, 8, 8,L0|L1}, {EQA_A_E, 2, 8, 8,L0|L1}, - {EQA_A_H, 2, 8, 8,L0|L1}, {EQA_A_L, 2, 8, 8,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::SUB_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::NEA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::NEA_A_L, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::SBB_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::SBB_A_L, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_A, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_A_B, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_C, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_A_D, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_E, 2, 8, 8,L0|L1}, + {&upd7810_device::EQA_A_H, 2, 8, 8,L0|L1}, {&upd7810_device::EQA_A_L, 2, 8, 8,L0|L1} }; /* prefix 64 */ -static const struct opcode_s op64_78c05[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op64_78c05[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ANI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {XRI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ORI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ANI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::XRI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ORI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2, 8, 8,L0|L1}, {ADINC_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {GTI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SUINB_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 3, 8, 8,L0|L1}, {LTI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADINC_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::GTI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUINB_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 3, 8, 8,L0|L1}, {&upd7810_device::LTI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {ADI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ONI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 3, 8, 8,L0|L1}, {ACI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 3, 8, 8,L0|L1}, {OFFI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ONI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 3, 8, 8,L0|L1}, {&upd7810_device::ACI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 3, 8, 8,L0|L1}, {&upd7810_device::OFFI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {SUI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {NEI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SBI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {EQI_A_xx, 3,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::NEI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SBI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::EQI_A_xx, 3,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ANI_PA_xx, 3,17,17,L0|L1}, {ANI_PB_xx, 3,17,17,L0|L1}, - {ANI_PC_xx, 3,17,17,L0|L1}, {ANI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {XRI_PA_xx, 3,17,17,L0|L1}, {XRI_PB_xx, 3,17,17,L0|L1}, - {XRI_PC_xx, 3,17,17,L0|L1}, {XRI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ORI_PA_xx, 3,17,17,L0|L1}, {ORI_PB_xx, 3,17,17,L0|L1}, - {ORI_PC_xx, 3,17,17,L0|L1}, {ORI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ANI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ANI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ANI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ANI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::XRI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::XRI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::XRI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::XRI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ORI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ORI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ORI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ORI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {ADINC_PA_xx, 3,17,17,L0|L1}, {ADINC_PB_xx, 3,17,17,L0|L1}, - {ADINC_PC_xx, 3,17,17,L0|L1}, {ADINC_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {GTI_PA_xx, 3,14,14,L0|L1}, {GTI_PB_xx, 3,14,14,L0|L1}, - {GTI_PC_xx, 3,14,14,L0|L1}, {GTI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {SUINB_PA_xx, 3,17,17,L0|L1}, {SUINB_PB_xx, 3,17,17,L0|L1}, - {SUINB_PC_xx, 3,17,17,L0|L1}, {SUINB_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {LTI_PA_xx, 3,14,14,L0|L1}, {LTI_PB_xx, 3,14,14,L0|L1}, - {LTI_PC_xx, 3,14,14,L0|L1}, {LTI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADINC_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ADINC_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ADINC_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ADINC_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::GTI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::GTI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::GTI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::GTI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::SUINB_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::SUINB_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::SUINB_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::SUINB_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::LTI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::LTI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::LTI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::LTI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {ADI_PA_xx, 3,17,17,L0|L1}, {ADI_PB_xx, 3,17,17,L0|L1}, - {ADI_PC_xx, 3,17,17,L0|L1}, {ADI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ONI_PA_xx, 3,14,14,L0|L1}, {ONI_PB_xx, 3,14,14,L0|L1}, - {ONI_PC_xx, 3,14,14,L0|L1}, {ONI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {ACI_PA_xx, 3,17,17,L0|L1}, {ACI_PB_xx, 3,17,17,L0|L1}, - {ACI_PC_xx, 3,17,17,L0|L1}, {ACI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {OFFI_PA_xx, 3,14,14,L0|L1}, {OFFI_PB_xx, 3,14,14,L0|L1}, - {OFFI_PC_xx, 3,14,14,L0|L1}, {OFFI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ADI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ADI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ADI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ONI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::ONI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::ONI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::ONI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::ACI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::ACI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::ACI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::ACI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::OFFI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::OFFI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::OFFI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {SUI_PA_xx, 3,17,17,L0|L1}, {SUI_PB_xx, 3,17,17,L0|L1}, - {SUI_PC_xx, 3,17,17,L0|L1}, {SUI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {NEI_PA_xx, 3,14,14,L0|L1}, {NEI_PB_xx, 3,14,14,L0|L1}, - {NEI_PC_xx, 3,14,14,L0|L1}, {NEI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {SBI_PA_xx, 3,17,17,L0|L1}, {SBI_PB_xx, 3,17,17,L0|L1}, - {SBI_PC_xx, 3,17,17,L0|L1}, {SBI_MKL_xx, 3,17,17,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {EQI_PA_xx, 3,14,14,L0|L1}, {EQI_PB_xx, 3,14,14,L0|L1}, - {EQI_PC_xx, 3,14,14,L0|L1}, {EQI_MKL_xx, 3,14,14,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::SUI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::SUI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::SUI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::SUI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::NEI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::NEI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::NEI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::NEI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::SBI_PA_xx, 3,17,17,L0|L1}, {&upd7810_device::SBI_PB_xx, 3,17,17,L0|L1}, + {&upd7810_device::SBI_PC_xx, 3,17,17,L0|L1}, {&upd7810_device::SBI_MKL_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::EQI_PA_xx, 3,14,14,L0|L1}, {&upd7810_device::EQI_PB_xx, 3,14,14,L0|L1}, + {&upd7810_device::EQI_PC_xx, 3,14,14,L0|L1}, {&upd7810_device::EQI_MKL_xx, 3,14,14,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; /* prefix 70 */ -static const struct opcode_s op70_78c05[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op70_78c05[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SSPD_w, 4,20,20,L0|L1}, {LSPD_w, 4,20,20,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SBCD_w, 4,20,20,L0|L1}, {LBCD_w, 4,20,20,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SSPD_w, 4,20,20,L0|L1}, {&upd7810_device::LSPD_w, 4,20,20,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SBCD_w, 4,20,20,L0|L1}, {&upd7810_device::LBCD_w, 4,20,20,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SDED_w, 4,20,20,L0|L1}, {LDED_w, 4,20,20,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {SHLD_w, 4,20,20,L0|L1}, {LHLD_w, 4,20,20,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SDED_w, 4,20,20,L0|L1}, {&upd7810_device::LDED_w, 4,20,20,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::SHLD_w, 4,20,20,L0|L1}, {&upd7810_device::LHLD_w, 4,20,20,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {MOV_A_w, 4,17,17,L0|L1}, - {MOV_B_w, 4,17,17,L0|L1}, {MOV_C_w, 4,17,17,L0|L1}, - {MOV_D_w, 4,17,17,L0|L1}, {MOV_E_w, 4,17,17,L0|L1}, - {MOV_H_w, 4,17,17,L0|L1}, {MOV_L_w, 4,17,17,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {MOV_w_A, 4,17,17,L0|L1}, - {MOV_w_B, 4,17,17,L0|L1}, {MOV_w_C, 4,17,17,L0|L1}, - {MOV_w_D, 4,17,17,L0|L1}, {MOV_w_E, 4,17,17,L0|L1}, - {MOV_w_H, 4,17,17,L0|L1}, {MOV_w_L, 4,17,17,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::MOV_A_w, 4,17,17,L0|L1}, + {&upd7810_device::MOV_B_w, 4,17,17,L0|L1}, {&upd7810_device::MOV_C_w, 4,17,17,L0|L1}, + {&upd7810_device::MOV_D_w, 4,17,17,L0|L1}, {&upd7810_device::MOV_E_w, 4,17,17,L0|L1}, + {&upd7810_device::MOV_H_w, 4,17,17,L0|L1}, {&upd7810_device::MOV_L_w, 4,17,17,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::MOV_w_A, 4,17,17,L0|L1}, + {&upd7810_device::MOV_w_B, 4,17,17,L0|L1}, {&upd7810_device::MOV_w_C, 4,17,17,L0|L1}, + {&upd7810_device::MOV_w_D, 4,17,17,L0|L1}, {&upd7810_device::MOV_w_E, 4,17,17,L0|L1}, + {&upd7810_device::MOV_w_H, 4,17,17,L0|L1}, {&upd7810_device::MOV_w_L, 4,17,17,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ANAX_B, 2,11,11,L0|L1}, - {ANAX_D, 2,11,11,L0|L1}, {ANAX_H, 2,11,11,L0|L1}, - {ANAX_Dp, 2,11,11,L0|L1}, {ANAX_Hp, 2,11,11,L0|L1}, - {ANAX_Dm, 2,11,11,L0|L1}, {ANAX_Hm, 2,11,11,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {XRAX_B, 2,11,11,L0|L1}, - {XRAX_D, 2,11,11,L0|L1}, {XRAX_H, 2,11,11,L0|L1}, - {XRAX_Dp, 2,11,11,L0|L1}, {XRAX_Hp, 2,11,11,L0|L1}, - {XRAX_Dm, 2,11,11,L0|L1}, {XRAX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ORAX_B, 2,11,11,L0|L1}, - {ORAX_D, 2,11,11,L0|L1}, {ORAX_H, 2,11,11,L0|L1}, - {ORAX_Dp, 2,11,11,L0|L1}, {ORAX_Hp, 2,11,11,L0|L1}, - {ORAX_Dm, 2,11,11,L0|L1}, {ORAX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ANAX_B, 2,11,11,L0|L1}, + {&upd7810_device::ANAX_D, 2,11,11,L0|L1}, {&upd7810_device::ANAX_H, 2,11,11,L0|L1}, + {&upd7810_device::ANAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ANAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ANAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ANAX_Hm, 2,11,11,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::XRAX_B, 2,11,11,L0|L1}, + {&upd7810_device::XRAX_D, 2,11,11,L0|L1}, {&upd7810_device::XRAX_H, 2,11,11,L0|L1}, + {&upd7810_device::XRAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::XRAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::XRAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::XRAX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ORAX_B, 2,11,11,L0|L1}, + {&upd7810_device::ORAX_D, 2,11,11,L0|L1}, {&upd7810_device::ORAX_H, 2,11,11,L0|L1}, + {&upd7810_device::ORAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ORAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ORAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ORAX_Hm, 2,11,11,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2, 8, 8,L0|L1}, {ADDNCX_B, 2,11,11,L0|L1}, - {ADDNCX_D, 2,11,11,L0|L1}, {ADDNCX_H, 2,11,11,L0|L1}, - {ADDNCX_Dp, 2,11,11,L0|L1}, {ADDNCX_Hp, 2,11,11,L0|L1}, - {ADDNCX_Dm, 2,11,11,L0|L1}, {ADDNCX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {GTAX_B, 2,11,11,L0|L1}, - {GTAX_D, 2,11,11,L0|L1}, {GTAX_H, 2,11,11,L0|L1}, - {GTAX_Dp, 2,11,11,L0|L1}, {GTAX_Hp, 2,11,11,L0|L1}, - {GTAX_Dm, 2,11,11,L0|L1}, {GTAX_Hm, 2,11,11,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SUBNBX_B, 2,11,11,L0|L1}, - {SUBNBX_D, 2,11,11,L0|L1}, {SUBNBX_H, 2,11,11,L0|L1}, - {SUBNBX_Dp, 2,11,11,L0|L1}, {SUBNBX_Hp, 2,11,11,L0|L1}, - {SUBNBX_Dm, 2,11,11,L0|L1}, {SUBNBX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {LTAX_B, 2,11,11,L0|L1}, - {LTAX_D, 2,11,11,L0|L1}, {LTAX_H, 2,11,11,L0|L1}, - {LTAX_Dp, 2,11,11,L0|L1}, {LTAX_Hp, 2,11,11,L0|L1}, - {LTAX_Dm, 2,11,11,L0|L1}, {LTAX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADDNCX_B, 2,11,11,L0|L1}, + {&upd7810_device::ADDNCX_D, 2,11,11,L0|L1}, {&upd7810_device::ADDNCX_H, 2,11,11,L0|L1}, + {&upd7810_device::ADDNCX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ADDNCX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ADDNCX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ADDNCX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::GTAX_B, 2,11,11,L0|L1}, + {&upd7810_device::GTAX_D, 2,11,11,L0|L1}, {&upd7810_device::GTAX_H, 2,11,11,L0|L1}, + {&upd7810_device::GTAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::GTAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::GTAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::GTAX_Hm, 2,11,11,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUBNBX_B, 2,11,11,L0|L1}, + {&upd7810_device::SUBNBX_D, 2,11,11,L0|L1}, {&upd7810_device::SUBNBX_H, 2,11,11,L0|L1}, + {&upd7810_device::SUBNBX_Dp, 2,11,11,L0|L1}, {&upd7810_device::SUBNBX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::SUBNBX_Dm, 2,11,11,L0|L1}, {&upd7810_device::SUBNBX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::LTAX_B, 2,11,11,L0|L1}, + {&upd7810_device::LTAX_D, 2,11,11,L0|L1}, {&upd7810_device::LTAX_H, 2,11,11,L0|L1}, + {&upd7810_device::LTAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::LTAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::LTAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::LTAX_Hm, 2,11,11,L0|L1}, /* 0xC0 - 0xDF */ - {illegal2, 2, 8, 8,L0|L1}, {ADDX_B, 2,11,11,L0|L1}, - {ADDX_D, 2,11,11,L0|L1}, {ADDX_H, 2,11,11,L0|L1}, - {ADDX_Dp, 2,11,11,L0|L1}, {ADDX_Hp, 2,11,11,L0|L1}, - {ADDX_Dm, 2,11,11,L0|L1}, {ADDX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {ONAX_B, 2,11,11,L0|L1}, - {ONAX_D, 2,11,11,L0|L1}, {ONAX_H, 2,11,11,L0|L1}, - {ONAX_Dp, 2,11,11,L0|L1}, {ONAX_Hp, 2,11,11,L0|L1}, - {ONAX_Dm, 2,11,11,L0|L1}, {ONAX_Hm, 2,11,11,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {ADCX_B, 2,11,11,L0|L1}, - {ADCX_D, 2,11,11,L0|L1}, {ADCX_H, 2,11,11,L0|L1}, - {ADCX_Dp, 2,11,11,L0|L1}, {ADCX_Hp, 2,11,11,L0|L1}, - {ADCX_Dm, 2,11,11,L0|L1}, {ADCX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {OFFAX_B, 2,11,11,L0|L1}, - {OFFAX_D, 2,11,11,L0|L1}, {OFFAX_H, 2,11,11,L0|L1}, - {OFFAX_Dp, 2,11,11,L0|L1}, {OFFAX_Hp, 2,11,11,L0|L1}, - {OFFAX_Dm, 2,11,11,L0|L1}, {OFFAX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADDX_B, 2,11,11,L0|L1}, + {&upd7810_device::ADDX_D, 2,11,11,L0|L1}, {&upd7810_device::ADDX_H, 2,11,11,L0|L1}, + {&upd7810_device::ADDX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ADDX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ADDX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ADDX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ONAX_B, 2,11,11,L0|L1}, + {&upd7810_device::ONAX_D, 2,11,11,L0|L1}, {&upd7810_device::ONAX_H, 2,11,11,L0|L1}, + {&upd7810_device::ONAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ONAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ONAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ONAX_Hm, 2,11,11,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::ADCX_B, 2,11,11,L0|L1}, + {&upd7810_device::ADCX_D, 2,11,11,L0|L1}, {&upd7810_device::ADCX_H, 2,11,11,L0|L1}, + {&upd7810_device::ADCX_Dp, 2,11,11,L0|L1}, {&upd7810_device::ADCX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::ADCX_Dm, 2,11,11,L0|L1}, {&upd7810_device::ADCX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::OFFAX_B, 2,11,11,L0|L1}, + {&upd7810_device::OFFAX_D, 2,11,11,L0|L1}, {&upd7810_device::OFFAX_H, 2,11,11,L0|L1}, + {&upd7810_device::OFFAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::OFFAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::OFFAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::OFFAX_Hm, 2,11,11,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2, 8, 8,L0|L1}, {SUBX_B, 2,11,11,L0|L1}, - {SUBX_D, 2,11,11,L0|L1}, {SUBX_H, 2,11,11,L0|L1}, - {SUBX_Dp, 2,11,11,L0|L1}, {SUBX_Hp, 2,11,11,L0|L1}, - {SUBX_Dm, 2,11,11,L0|L1}, {SUBX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {NEAX_B, 2,11,11,L0|L1}, - {NEAX_D, 2,11,11,L0|L1}, {NEAX_H, 2,11,11,L0|L1}, - {NEAX_Dp, 2,11,11,L0|L1}, {NEAX_Hp, 2,11,11,L0|L1}, - {NEAX_Dm, 2,11,11,L0|L1}, {NEAX_Hm, 2,11,11,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {SBBX_B, 2,11,11,L0|L1}, - {SBBX_D, 2,11,11,L0|L1}, {SBBX_H, 2,11,11,L0|L1}, - {SBBX_Dp, 2,11,11,L0|L1}, {SBBX_Hp, 2,11,11,L0|L1}, - {SBBX_Dm, 2,11,11,L0|L1}, {SBBX_Hm, 2,11,11,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {EQAX_B, 2,11,11,L0|L1}, - {EQAX_D, 2,11,11,L0|L1}, {EQAX_H, 2,11,11,L0|L1}, - {EQAX_Dp, 2,11,11,L0|L1}, {EQAX_Hp, 2,11,11,L0|L1}, - {EQAX_Dm, 2,11,11,L0|L1}, {EQAX_Hm, 2,11,11,L0|L1} + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUBX_B, 2,11,11,L0|L1}, + {&upd7810_device::SUBX_D, 2,11,11,L0|L1}, {&upd7810_device::SUBX_H, 2,11,11,L0|L1}, + {&upd7810_device::SUBX_Dp, 2,11,11,L0|L1}, {&upd7810_device::SUBX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::SUBX_Dm, 2,11,11,L0|L1}, {&upd7810_device::SUBX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::NEAX_B, 2,11,11,L0|L1}, + {&upd7810_device::NEAX_D, 2,11,11,L0|L1}, {&upd7810_device::NEAX_H, 2,11,11,L0|L1}, + {&upd7810_device::NEAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::NEAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::NEAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::NEAX_Hm, 2,11,11,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SBBX_B, 2,11,11,L0|L1}, + {&upd7810_device::SBBX_D, 2,11,11,L0|L1}, {&upd7810_device::SBBX_H, 2,11,11,L0|L1}, + {&upd7810_device::SBBX_Dp, 2,11,11,L0|L1}, {&upd7810_device::SBBX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::SBBX_Dm, 2,11,11,L0|L1}, {&upd7810_device::SBBX_Hm, 2,11,11,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::EQAX_B, 2,11,11,L0|L1}, + {&upd7810_device::EQAX_D, 2,11,11,L0|L1}, {&upd7810_device::EQAX_H, 2,11,11,L0|L1}, + {&upd7810_device::EQAX_Dp, 2,11,11,L0|L1}, {&upd7810_device::EQAX_Hp, 2,11,11,L0|L1}, + {&upd7810_device::EQAX_Dm, 2,11,11,L0|L1}, {&upd7810_device::EQAX_Hm, 2,11,11,L0|L1} }; /* prefix 74 */ -static const struct opcode_s op74_78c05[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op74_78c05[256] = { /* 0x00 - 0x1F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ANAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {XRAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ORAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ANAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::XRAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ORAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xA0 - 0xBF */ - {ADDNCW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {GTAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {SUBNBW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {LTAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDNCW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::GTAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::SUBNBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::LTAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xC0 - 0xDF */ - {ADDW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {ONAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {ADCW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {OFFAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ADDW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::ONAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::ADCW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::OFFAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, /* 0xE0 - 0xFF */ - {SUBW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {NEAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - - {SBBW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {EQAW_wa, 3,14,14,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1}, - {illegal2, 2, 8, 8,L0|L1}, {illegal2, 2, 8, 8,L0|L1} + {&upd7810_device::SUBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::NEAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + + {&upd7810_device::SBBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::EQAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::illegal2, 2, 8, 8,L0|L1} }; -static const struct opcode_s opXX_78c05[256] = +const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c05[256] = { /* 0x00 - 0x1F */ - {NOP, 1, 4, 4,L0|L1}, {HALT, 1, 6, 6,L0|L1}, - {INX_SP, 1, 7, 7,L0|L1}, {DCX_SP, 1, 7, 7,L0|L1}, - {LXI_S_w, 3,10,10,L0|L1}, {ANIW_wa_xx, 3,16,16,L0|L1}, - {illegal, 1, 4, 4,L0|L1}, {ANI_A_xx, 2, 7, 7,L0|L1}, - {RET, 1,10,10,L0|L1}, {SIO, 1, 4, 4,L0|L1}, - {MOV_A_B, 1, 4, 4,L0|L1}, {MOV_A_C, 1, 4, 4,L0|L1}, - {MOV_A_D, 1, 4, 4,L0|L1}, {MOV_A_E, 1, 4, 4,L0|L1}, - {MOV_A_H, 1, 4, 4,L0|L1}, {MOV_A_L, 1, 4, 4,L0|L1}, - - {illegal, 1, 4, 4,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {INX_BC, 1, 7, 7,L0|L1}, {DCX_BC, 1, 7, 7,L0|L1}, - {LXI_B_w, 3,10,10,L0|L1}, {ORIW_wa_xx, 3,16,16,L0|L1}, - {XRI_A_xx, 2, 7, 7,L0|L1}, {ORI_A_xx, 2, 7, 7,L0|L1}, - {RETS, 1,10,10,L0|L1}, {STM, 1, 4, 4,L0|L1}, - {MOV_B_A, 1, 4, 4,L0|L1}, {MOV_C_A, 1, 4, 4,L0|L1}, - {MOV_D_A, 1, 4, 4,L0|L1}, {MOV_E_A, 1, 4, 4,L0|L1}, - {MOV_H_A, 1, 4, 4,L0|L1}, {MOV_L_A, 1, 4, 4,L0|L1}, + {&upd7810_device::NOP, 1, 4, 4,L0|L1}, {&upd7810_device::HALT, 1, 6, 6,L0|L1}, + {&upd7810_device::INX_SP, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_SP, 1, 7, 7,L0|L1}, + {&upd7810_device::LXI_S_w, 3,10,10,L0|L1}, {&upd7810_device::ANIW_wa_xx, 3,16,16,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::ANI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::RET, 1,10,10,L0|L1}, {&upd7810_device::SIO, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_A_B, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_A_C, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_A_D, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_A_E, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_A_H, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_A_L, 1, 4, 4,L0|L1}, + + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::INX_BC, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_BC, 1, 7, 7,L0|L1}, + {&upd7810_device::LXI_B_w, 3,10,10,L0|L1}, {&upd7810_device::ORIW_wa_xx, 3,16,16,L0|L1}, + {&upd7810_device::XRI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::ORI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::RETS, 1,10,10,L0|L1}, {&upd7810_device::STM, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_B_A, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_C_A, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_D_A, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_E_A, 1, 4, 4,L0|L1}, + {&upd7810_device::MOV_H_A, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_L_A, 1, 4, 4,L0|L1}, /* 0x20 - 0x3F */ - {INRW_wa_7801, 2,13,13,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {INX_DE, 1, 7, 7,L0|L1}, {DCX_DE, 1, 7, 7,L0|L1}, - {LXI_D_w, 3,10,10,L0|L1}, {GTIW_wa_xx, 3,13,13,L0|L1}, - {ADINC_A_xx, 2, 7, 7,L0|L1}, {GTI_A_xx, 2, 7, 7,L0|L1}, - {LDAW_wa, 2,10,10,L0|L1}, {LDAX_B, 1, 7, 7,L0|L1}, - {LDAX_D, 1, 7, 7,L0|L1}, {LDAX_H, 1, 7, 7,L0|L1}, - {LDAX_Dp, 1, 7, 7,L0|L1}, {LDAX_Hp, 1, 7, 7,L0|L1}, - {LDAX_Dm, 1, 7, 7,L0|L1}, {LDAX_Hm, 1, 7, 7,L0|L1}, - - {DCRW_wa_7801, 2,13,13,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {INX_HL, 1, 7, 7,L0|L1}, {DCX_HL, 1, 7, 7,L0|L1}, - {LXI_H_w, 3,10,10, L1}, {LTIW_wa_xx, 3,13,13,L0|L1}, - {SUINB_A_xx, 2, 7, 7,L0|L1}, {LTI_A_xx, 2, 7, 7,L0|L1}, - {STAW_wa, 2,10,10,L0|L1}, {STAX_B, 1, 7, 7,L0|L1}, - {STAX_D, 1, 7, 7,L0|L1}, {STAX_H, 1, 7, 7,L0|L1}, - {STAX_Dp, 1, 7, 7,L0|L1}, {STAX_Hp, 1, 7, 7,L0|L1}, - {STAX_Dm, 1, 7, 7,L0|L1}, {STAX_Hm, 1, 7, 7,L0|L1}, + {&upd7810_device::INRW_wa_7801, 2,13,13,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::INX_DE, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_DE, 1, 7, 7,L0|L1}, + {&upd7810_device::LXI_D_w, 3,10,10,L0|L1}, {&upd7810_device::GTIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::ADINC_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::GTI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::LDAW_wa, 2,10,10,L0|L1}, {&upd7810_device::LDAX_B, 1, 7, 7,L0|L1}, + {&upd7810_device::LDAX_D, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_H, 1, 7, 7,L0|L1}, + {&upd7810_device::LDAX_Dp, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_Hp, 1, 7, 7,L0|L1}, + {&upd7810_device::LDAX_Dm, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_Hm, 1, 7, 7,L0|L1}, + + {&upd7810_device::DCRW_wa_7801, 2,13,13,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::INX_HL, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_HL, 1, 7, 7,L0|L1}, + {&upd7810_device::LXI_H_w, 3,10,10, L1}, {&upd7810_device::LTIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SUINB_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::LTI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::STAW_wa, 2,10,10,L0|L1}, {&upd7810_device::STAX_B, 1, 7, 7,L0|L1}, + {&upd7810_device::STAX_D, 1, 7, 7,L0|L1}, {&upd7810_device::STAX_H, 1, 7, 7,L0|L1}, + {&upd7810_device::STAX_Dp, 1, 7, 7,L0|L1}, {&upd7810_device::STAX_Hp, 1, 7, 7,L0|L1}, + {&upd7810_device::STAX_Dm, 1, 7, 7,L0|L1}, {&upd7810_device::STAX_Hm, 1, 7, 7,L0|L1}, /* 0x40 - 0x5F */ - {illegal, 1, 4, 4,L0|L1}, {INR_A_7801, 1, 4, 4,L0|L1}, - {INR_B_7801, 1, 4, 4,L0|L1}, {INR_C_7801, 1, 4, 4,L0|L1}, - {CALL_w, 3,16,16,L0|L1}, {ONIW_wa_xx, 3,13,13,L0|L1}, - {ADI_A_xx, 2, 7, 7,L0|L1}, {ONI_A_xx, 2, 7, 7,L0|L1}, - {PRE_48, 1, 0, 0,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {illegal, 1, 4, 4,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {PRE_4C, 1, 0, 0,L0|L1}, {PRE_4D, 1, 0, 0,L0|L1}, - {JRE, 2,13,13,L0|L1}, {JRE, 2,13,13,L0|L1}, - - {illegal, 1, 4, 4,L0|L1}, {DCR_A_7801, 1, 4, 4,L0|L1}, - {DCR_B_7801, 1, 4, 4,L0|L1}, {DCR_C_7801, 1, 4, 4,L0|L1}, - {JMP_w, 3,10,10,L0|L1}, {OFFIW_wa_xx, 3,13,13,L0|L1}, - {ACI_A_xx, 2, 7, 7,L0|L1}, {OFFI_A_xx, 2, 7, 7,L0|L1}, - {illegal, 1, 4, 4,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {illegal, 1, 4, 4,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {illegal, 1, 4, 4,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {illegal, 1, 4, 4,L0|L1}, {illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::INR_A_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::INR_B_7801, 1, 4, 4,L0|L1}, {&upd7810_device::INR_C_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::CALL_w, 3,16,16,L0|L1}, {&upd7810_device::ONIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::ADI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::ONI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::PRE_48, 1, 0, 0,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::PRE_4C, 1, 0, 0,L0|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0|L1}, + {&upd7810_device::JRE, 2,13,13,L0|L1}, {&upd7810_device::JRE, 2,13,13,L0|L1}, + + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_A_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::DCR_B_7801, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_C_7801, 1, 4, 4,L0|L1}, + {&upd7810_device::JMP_w, 3,10,10,L0|L1}, {&upd7810_device::OFFIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::ACI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, /* 0x60 - 0x7F */ - {PRE_60, 1, 0, 0,L0|L1}, {DAA, 1, 4, 4,L0|L1}, - {RETI, 1,13,13,L0|L1}, {CALB, 2,13,13,L0|L1}, - {PRE_64, 1, 0, 0,L0|L1}, {NEIW_wa_xx, 3,13,13,L0|L1}, - {SUI_A_xx, 2, 7, 7,L0|L1}, {NEI_A_xx, 2, 7, 7,L0|L1}, - {illegal, 1, 4, 4,L0|L1}, {MVI_A_xx, 2, 7, 7,L0 }, - {MVI_B_xx, 2, 7, 7,L0|L1}, {MVI_C_xx, 2, 7, 7,L0|L1}, - {MVI_D_xx, 2, 7, 7,L0|L1}, {MVI_E_xx, 2, 7, 7,L0|L1}, - {MVI_H_xx, 2, 7, 7,L0|L1}, {MVI_L_xx, 2, 7, 7, L1}, - - {PRE_70, 1, 0, 0,L0|L1}, {MVIW_wa_xx, 3,13,13,L0|L1}, - {SOFTI, 1,19,19,L0|L1}, {JB, 1, 4, 4,L0|L1}, - {PRE_74, 1, 0, 0,L0|L1}, {EQIW_wa_xx, 3,13,13,L0|L1}, - {SBI_A_xx, 2, 7, 7,L0|L1}, {EQI_A_xx, 2, 7, 7,L0|L1}, - {CALF, 2,13,13,L0|L1}, {CALF, 2,13,13,L0|L1}, - {CALF, 2,13,13,L0|L1}, {CALF, 2,13,13,L0|L1}, - {CALF, 2,13,13,L0|L1}, {CALF, 2,13,13,L0|L1}, - {CALF, 2,13,13,L0|L1}, {CALF, 2,13,13,L0|L1}, + {&upd7810_device::PRE_60, 1, 0, 0,L0|L1}, {&upd7810_device::DAA, 1, 4, 4,L0|L1}, + {&upd7810_device::RETI, 1,13,13,L0|L1}, {&upd7810_device::CALB, 2,13,13,L0|L1}, + {&upd7810_device::PRE_64, 1, 0, 0,L0|L1}, {&upd7810_device::NEIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SUI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::NEI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::MVI_A_xx, 2, 7, 7,L0 }, + {&upd7810_device::MVI_B_xx, 2, 7, 7,L0|L1}, {&upd7810_device::MVI_C_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::MVI_D_xx, 2, 7, 7,L0|L1}, {&upd7810_device::MVI_E_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::MVI_H_xx, 2, 7, 7,L0|L1}, {&upd7810_device::MVI_L_xx, 2, 7, 7, L1}, + + {&upd7810_device::PRE_70, 1, 0, 0,L0|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SOFTI, 1,19,19,L0|L1}, {&upd7810_device::JB, 1, 4, 4,L0|L1}, + {&upd7810_device::PRE_74, 1, 0, 0,L0|L1}, {&upd7810_device::EQIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SBI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::EQI_A_xx, 2, 7, 7,L0|L1}, + {&upd7810_device::CALF, 2,13,13,L0|L1}, {&upd7810_device::CALF, 2,13,13,L0|L1}, + {&upd7810_device::CALF, 2,13,13,L0|L1}, {&upd7810_device::CALF, 2,13,13,L0|L1}, + {&upd7810_device::CALF, 2,13,13,L0|L1}, {&upd7810_device::CALF, 2,13,13,L0|L1}, + {&upd7810_device::CALF, 2,13,13,L0|L1}, {&upd7810_device::CALF, 2,13,13,L0|L1}, /* 0x80 - 0x9F */ - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, /* 0xA0 - 0xBF */ - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, /* 0xC0 - 0xDF */ - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, /* 0xE0 - 0xFF */ - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1}, - {JR, 1,10,10,L0|L1}, {JR, 1,10,10,L0|L1} + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1}, + {&upd7810_device::JR, 1,10,10,L0|L1}, {&upd7810_device::JR, 1,10,10,L0|L1} }; /*********************************************************************** @@ -6042,1247 +5003,1247 @@ static const struct opcode_s opXX_78c05[256] = * **********************************************************************/ -static const struct opcode_s op48_78c06[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op48_78c06[256] = { /* 0x00 - 0x1F */ - {SKIT_F0, 2,12,12,L0|L1}, {SKIT_FT0, 2,12,12,L0|L1}, - {SKIT_F1, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SKIT_FST, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SK_CY, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SK_Z, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {PUSH_VA, 2,21,21,L0|L1}, {POP_VA, 2,18,18,L0|L1}, - - {SKNIT_F0, 2,12,12,L0|L1}, {SKNIT_FT0, 2,12,12,L0|L1}, - {SKNIT_F1, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SKNIT_FST, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SKN_CY, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SKN_Z, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {PUSH_BC, 2,21,21,L0|L1}, {POP_BC, 2,18,18,L0|L1}, + {&upd7810_device::SKIT_F0, 2,12,12,L0|L1}, {&upd7810_device::SKIT_FT0, 2,12,12,L0|L1}, + {&upd7810_device::SKIT_F1, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SKIT_FST, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SK_CY, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SK_Z, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::PUSH_VA, 2,21,21,L0|L1}, {&upd7810_device::POP_VA, 2,18,18,L0|L1}, + + {&upd7810_device::SKNIT_F0, 2,12,12,L0|L1}, {&upd7810_device::SKNIT_FT0, 2,12,12,L0|L1}, + {&upd7810_device::SKNIT_F1, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SKNIT_FST, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SKN_CY, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SKN_Z, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::PUSH_BC, 2,21,21,L0|L1}, {&upd7810_device::POP_BC, 2,18,18,L0|L1}, /* 0x20 - 0x3F */ - {EI, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {DI, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {CLC, 2,12,12,L0|L1}, {STC, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {PEX, 2,15,15,L0|L1}, - {PUSH_DE, 2,21,21,L0|L1}, {POP_DE, 2,18,18,L0|L1}, - - {RLL_A, 2,12,12,L0|L1}, {RLR_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {RLD, 2,21,21,L0|L1}, {RRD, 2,21,21,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {PER, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {PUSH_HL, 2,21,21,L0|L1}, {POP_HL, 2,18,18,L0|L1}, + {&upd7810_device::EI, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::DI, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::CLC, 2,12,12,L0|L1}, {&upd7810_device::STC, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::PEX, 2,15,15,L0|L1}, + {&upd7810_device::PUSH_DE, 2,21,21,L0|L1}, {&upd7810_device::POP_DE, 2,18,18,L0|L1}, + + {&upd7810_device::RLL_A, 2,12,12,L0|L1}, {&upd7810_device::RLR_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::RLD, 2,21,21,L0|L1}, {&upd7810_device::RRD, 2,21,21,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::PER, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::PUSH_HL, 2,21,21,L0|L1}, {&upd7810_device::POP_HL, 2,18,18,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xC0 - 0xDF */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1} + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1} }; -static const struct opcode_s op4C_78c06[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op4C_78c06[256] = { /* 0x00 - 0x1F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xC0 - 0xDF */ - {MOV_A_PA, 2,14,14,L0|L1}, {MOV_A_PB, 2,14,14,L0|L1}, - {MOV_A_PC, 2,14,14,L0|L1}, {MOV_A_MKL, 2,14,14,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {MOV_A_S, 2,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::MOV_A_PA, 2,14,14,L0|L1}, {&upd7810_device::MOV_A_PB, 2,14,14,L0|L1}, + {&upd7810_device::MOV_A_PC, 2,14,14,L0|L1}, {&upd7810_device::MOV_A_MKL, 2,14,14,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::MOV_A_S, 2,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1} + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1} }; /* prefix 4D */ -static const struct opcode_s op4D_78c06[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op4D_78c06[256] = { /* 0x00 - 0x1F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xC0 - 0xDF */ - {MOV_PA_A, 2,14,14,L0|L1}, {MOV_PB_A, 2,14,14,L0|L1}, - {MOV_PC_A, 2,14,14,L0|L1}, {MOV_MKL_A, 2,14,14,L0|L1}, - {MOV_MB_A, 2,14,14,L0|L1}, {MOV_MC_A, 2,14,14,L0|L1}, - {MOV_TM0_A, 2,14,14,L0|L1}, {MOV_TM1_A, 2,14,14,L0|L1}, - {MOV_S_A, 2,14,14,L0|L1}, {MOV_TMM_A, 2,14,14,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::MOV_PA_A, 2,14,14,L0|L1}, {&upd7810_device::MOV_PB_A, 2,14,14,L0|L1}, + {&upd7810_device::MOV_PC_A, 2,14,14,L0|L1}, {&upd7810_device::MOV_MKL_A, 2,14,14,L0|L1}, + {&upd7810_device::MOV_MB_A, 2,14,14,L0|L1}, {&upd7810_device::MOV_MC_A, 2,14,14,L0|L1}, + {&upd7810_device::MOV_TM0_A, 2,14,14,L0|L1}, {&upd7810_device::MOV_TM1_A, 2,14,14,L0|L1}, + {&upd7810_device::MOV_S_A, 2,14,14,L0|L1}, {&upd7810_device::MOV_TMM_A, 2,14,14,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1} + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1} }; /* prefix 60 */ -static const struct opcode_s op60_78c06[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op60_78c06[256] = { /* 0x00 - 0x1F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ANA_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {XRA_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ORA_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ANA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::XRA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ORA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2,12,12,L0|L1}, {ADDNC_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {GTA_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {SUBNB_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {LTA_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADDNC_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::GTA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SUBNB_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::LTA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2,12,12,L0|L1}, {ADD_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {ADC_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADD_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADC_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2, 8, 8,L0|L1}, {SUB_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {NEA_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {SBB_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {EQA_A_A, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2, 8, 8,L0|L1}, {&upd7810_device::SUB_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::NEA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SBB_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::EQA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ANA_A_A, 2,12,12,L0|L1}, - {ANA_A_B, 2,12,12,L0|L1}, {ANA_A_C, 2,12,12,L0|L1}, - {ANA_A_D, 2,12,12,L0|L1}, {ANA_A_E, 2,12,12,L0|L1}, - {ANA_A_H, 2,12,12,L0|L1}, {ANA_A_L, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {XRA_A_A, 2,12,12,L0|L1}, - {XRA_A_B, 2,12,12,L0|L1}, {XRA_A_C, 2,12,12,L0|L1}, - {XRA_A_D, 2,12,12,L0|L1}, {XRA_A_E, 2,12,12,L0|L1}, - {XRA_A_H, 2,12,12,L0|L1}, {XRA_A_L, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ORA_A_A, 2,12,12,L0|L1}, - {ORA_A_B, 2,12,12,L0|L1}, {ORA_A_C, 2,12,12,L0|L1}, - {ORA_A_D, 2,12,12,L0|L1}, {ORA_A_E, 2,12,12,L0|L1}, - {ORA_A_H, 2,12,12,L0|L1}, {ORA_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ANA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::ANA_A_B, 2,12,12,L0|L1}, {&upd7810_device::ANA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::ANA_A_D, 2,12,12,L0|L1}, {&upd7810_device::ANA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::ANA_A_H, 2,12,12,L0|L1}, {&upd7810_device::ANA_A_L, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::XRA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::XRA_A_B, 2,12,12,L0|L1}, {&upd7810_device::XRA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::XRA_A_D, 2,12,12,L0|L1}, {&upd7810_device::XRA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::XRA_A_H, 2,12,12,L0|L1}, {&upd7810_device::XRA_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ORA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::ORA_A_B, 2,12,12,L0|L1}, {&upd7810_device::ORA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::ORA_A_D, 2,12,12,L0|L1}, {&upd7810_device::ORA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::ORA_A_H, 2,12,12,L0|L1}, {&upd7810_device::ORA_A_L, 2,12,12,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2,12,12,L0|L1}, {ADDNC_A_A, 2,12,12,L0|L1}, - {ADDNC_A_B, 2,12,12,L0|L1}, {ADDNC_A_C, 2,12,12,L0|L1}, - {ADDNC_A_D, 2,12,12,L0|L1}, {ADDNC_A_E, 2,12,12,L0|L1}, - {ADDNC_A_H, 2,12,12,L0|L1}, {ADDNC_A_L, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {GTA_A_A, 2,12,12,L0|L1}, - {GTA_A_B, 2,12,12,L0|L1}, {GTA_A_C, 2,12,12,L0|L1}, - {GTA_A_D, 2,12,12,L0|L1}, {GTA_A_E, 2,12,12,L0|L1}, - {GTA_A_H, 2,12,12,L0|L1}, {GTA_A_L, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {SUBNB_A_A, 2,12,12,L0|L1}, - {SUBNB_A_B, 2,12,12,L0|L1}, {SUBNB_A_C, 2,12,12,L0|L1}, - {SUBNB_A_D, 2,12,12,L0|L1}, {SUBNB_A_E, 2,12,12,L0|L1}, - {SUBNB_A_H, 2,12,12,L0|L1}, {SUBNB_A_L, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {LTA_A_A, 2,12,12,L0|L1}, - {LTA_A_B, 2,12,12,L0|L1}, {LTA_A_C, 2,12,12,L0|L1}, - {LTA_A_D, 2,12,12,L0|L1}, {LTA_A_E, 2,12,12,L0|L1}, - {LTA_A_H, 2,12,12,L0|L1}, {LTA_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADDNC_A_A, 2,12,12,L0|L1}, + {&upd7810_device::ADDNC_A_B, 2,12,12,L0|L1}, {&upd7810_device::ADDNC_A_C, 2,12,12,L0|L1}, + {&upd7810_device::ADDNC_A_D, 2,12,12,L0|L1}, {&upd7810_device::ADDNC_A_E, 2,12,12,L0|L1}, + {&upd7810_device::ADDNC_A_H, 2,12,12,L0|L1}, {&upd7810_device::ADDNC_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::GTA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::GTA_A_B, 2,12,12,L0|L1}, {&upd7810_device::GTA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::GTA_A_D, 2,12,12,L0|L1}, {&upd7810_device::GTA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::GTA_A_H, 2,12,12,L0|L1}, {&upd7810_device::GTA_A_L, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SUBNB_A_A, 2,12,12,L0|L1}, + {&upd7810_device::SUBNB_A_B, 2,12,12,L0|L1}, {&upd7810_device::SUBNB_A_C, 2,12,12,L0|L1}, + {&upd7810_device::SUBNB_A_D, 2,12,12,L0|L1}, {&upd7810_device::SUBNB_A_E, 2,12,12,L0|L1}, + {&upd7810_device::SUBNB_A_H, 2,12,12,L0|L1}, {&upd7810_device::SUBNB_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::LTA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::LTA_A_B, 2,12,12,L0|L1}, {&upd7810_device::LTA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::LTA_A_D, 2,12,12,L0|L1}, {&upd7810_device::LTA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::LTA_A_H, 2,12,12,L0|L1}, {&upd7810_device::LTA_A_L, 2,12,12,L0|L1}, /* 0xC0 - 0xDF */ - {illegal2, 2,12,12,L0|L1}, {ADD_A_A, 2,12,12,L0|L1}, - {ADD_A_B, 2,12,12,L0|L1}, {ADD_A_C, 2,12,12,L0|L1}, - {ADD_A_D, 2,12,12,L0|L1}, {ADD_A_E, 2,12,12,L0|L1}, - {ADD_A_H, 2,12,12,L0|L1}, {ADD_A_L, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ONA_A_A, 2,12,12,L0|L1}, - {ONA_A_B, 2,12,12,L0|L1}, {ONA_A_C, 2,12,12,L0|L1}, - {ONA_A_D, 2,12,12,L0|L1}, {ONA_A_E, 2,12,12,L0|L1}, - {ONA_A_H, 2,12,12,L0|L1}, {ONA_A_L, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {ADC_A_A, 2,12,12,L0|L1}, - {ADC_A_B, 2,12,12,L0|L1}, {ADC_A_C, 2,12,12,L0|L1}, - {ADC_A_D, 2,12,12,L0|L1}, {ADC_A_E, 2,12,12,L0|L1}, - {ADC_A_H, 2,12,12,L0|L1}, {ADC_A_L, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {OFFA_A_A, 2,12,12,L0|L1}, - {OFFA_A_B, 2,12,12,L0|L1}, {OFFA_A_C, 2,12,12,L0|L1}, - {OFFA_A_D, 2,12,12,L0|L1}, {OFFA_A_E, 2,12,12,L0|L1}, - {OFFA_A_H, 2,12,12,L0|L1}, {OFFA_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADD_A_A, 2,12,12,L0|L1}, + {&upd7810_device::ADD_A_B, 2,12,12,L0|L1}, {&upd7810_device::ADD_A_C, 2,12,12,L0|L1}, + {&upd7810_device::ADD_A_D, 2,12,12,L0|L1}, {&upd7810_device::ADD_A_E, 2,12,12,L0|L1}, + {&upd7810_device::ADD_A_H, 2,12,12,L0|L1}, {&upd7810_device::ADD_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ONA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::ONA_A_B, 2,12,12,L0|L1}, {&upd7810_device::ONA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::ONA_A_D, 2,12,12,L0|L1}, {&upd7810_device::ONA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::ONA_A_H, 2,12,12,L0|L1}, {&upd7810_device::ONA_A_L, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADC_A_A, 2,12,12,L0|L1}, + {&upd7810_device::ADC_A_B, 2,12,12,L0|L1}, {&upd7810_device::ADC_A_C, 2,12,12,L0|L1}, + {&upd7810_device::ADC_A_D, 2,12,12,L0|L1}, {&upd7810_device::ADC_A_E, 2,12,12,L0|L1}, + {&upd7810_device::ADC_A_H, 2,12,12,L0|L1}, {&upd7810_device::ADC_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::OFFA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::OFFA_A_B, 2,12,12,L0|L1}, {&upd7810_device::OFFA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::OFFA_A_D, 2,12,12,L0|L1}, {&upd7810_device::OFFA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::OFFA_A_H, 2,12,12,L0|L1}, {&upd7810_device::OFFA_A_L, 2,12,12,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2,12,12,L0|L1}, {SUB_A_A, 2,12,12,L0|L1}, - {SUB_A_B, 2,12,12,L0|L1}, {SUB_A_C, 2,12,12,L0|L1}, - {SUB_A_D, 2,12,12,L0|L1}, {SUB_A_E, 2,12,12,L0|L1}, - {SUB_A_H, 2,12,12,L0|L1}, {SUB_A_L, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {NEA_A_A, 2,12,12,L0|L1}, - {NEA_A_B, 2,12,12,L0|L1}, {NEA_A_C, 2,12,12,L0|L1}, - {NEA_A_D, 2,12,12,L0|L1}, {NEA_A_E, 2,12,12,L0|L1}, - {NEA_A_H, 2,12,12,L0|L1}, {NEA_A_L, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {SBB_A_A, 2,12,12,L0|L1}, - {SBB_A_B, 2,12,12,L0|L1}, {SBB_A_C, 2,12,12,L0|L1}, - {SBB_A_D, 2,12,12,L0|L1}, {SBB_A_E, 2,12,12,L0|L1}, - {SBB_A_H, 2,12,12,L0|L1}, {SBB_A_L, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {EQA_A_A, 2,12,12,L0|L1}, - {EQA_A_B, 2,12,12,L0|L1}, {EQA_A_C, 2,12,12,L0|L1}, - {EQA_A_D, 2,12,12,L0|L1}, {EQA_A_E, 2,12,12,L0|L1}, - {EQA_A_H, 2,12,12,L0|L1}, {EQA_A_L, 2,12,12,L0|L1} + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SUB_A_A, 2,12,12,L0|L1}, + {&upd7810_device::SUB_A_B, 2,12,12,L0|L1}, {&upd7810_device::SUB_A_C, 2,12,12,L0|L1}, + {&upd7810_device::SUB_A_D, 2,12,12,L0|L1}, {&upd7810_device::SUB_A_E, 2,12,12,L0|L1}, + {&upd7810_device::SUB_A_H, 2,12,12,L0|L1}, {&upd7810_device::SUB_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::NEA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::NEA_A_B, 2,12,12,L0|L1}, {&upd7810_device::NEA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::NEA_A_D, 2,12,12,L0|L1}, {&upd7810_device::NEA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::NEA_A_H, 2,12,12,L0|L1}, {&upd7810_device::NEA_A_L, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SBB_A_A, 2,12,12,L0|L1}, + {&upd7810_device::SBB_A_B, 2,12,12,L0|L1}, {&upd7810_device::SBB_A_C, 2,12,12,L0|L1}, + {&upd7810_device::SBB_A_D, 2,12,12,L0|L1}, {&upd7810_device::SBB_A_E, 2,12,12,L0|L1}, + {&upd7810_device::SBB_A_H, 2,12,12,L0|L1}, {&upd7810_device::SBB_A_L, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::EQA_A_A, 2,12,12,L0|L1}, + {&upd7810_device::EQA_A_B, 2,12,12,L0|L1}, {&upd7810_device::EQA_A_C, 2,12,12,L0|L1}, + {&upd7810_device::EQA_A_D, 2,12,12,L0|L1}, {&upd7810_device::EQA_A_E, 2,12,12,L0|L1}, + {&upd7810_device::EQA_A_H, 2,12,12,L0|L1}, {&upd7810_device::EQA_A_L, 2,12,12,L0|L1} }; /* prefix 64 */ -static const struct opcode_s op64_78c06[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op64_78c06[256] = { /* 0x00 - 0x1F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ANI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {XRI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ORI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ANI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::XRI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ORI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2,12,12,L0|L1}, {ADINC_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {GTI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {SUINB_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 3,12,12,L0|L1}, {LTI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADINC_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::GTI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SUINB_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 3,12,12,L0|L1}, {&upd7810_device::LTI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2,12,12,L0|L1}, {ADI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ONI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 3,12,12,L0|L1}, {ACI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 3,12,12,L0|L1}, {OFFI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ONI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 3,12,12,L0|L1}, {&upd7810_device::ACI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 3,12,12,L0|L1}, {&upd7810_device::OFFI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2,12,12,L0|L1}, {SUI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {NEI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {SBI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {EQI_A_xx, 3,17,17,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SUI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::NEI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SBI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::EQI_A_xx, 3,17,17,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {ANI_PA_xx, 3,23,23,L0|L1}, {ANI_PB_xx, 3,23,23,L0|L1}, - {ANI_PC_xx, 3,23,23,L0|L1}, {ANI_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {XRI_PA_xx, 3,23,23,L0|L1}, {XRI_PB_xx, 3,23,23,L0|L1}, - {XRI_PC_xx, 3,23,23,L0|L1}, {XRI_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {ORI_PA_xx, 3,23,23,L0|L1}, {ORI_PB_xx, 3,23,23,L0|L1}, - {ORI_PC_xx, 3,23,23,L0|L1}, {ORI_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ANI_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::ANI_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::ANI_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::ANI_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::XRI_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::XRI_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::XRI_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::XRI_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ORI_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::ORI_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::ORI_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::ORI_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xA0 - 0xBF */ - {ADINC_PA_xx, 3,23,23,L0|L1}, {ADINC_PB_xx, 3,23,23,L0|L1}, - {ADINC_PC_xx, 3,23,23,L0|L1}, {ADINC_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {GTI_PA_xx, 3,20,20,L0|L1}, {GTI_PB_xx, 3,20,20,L0|L1}, - {GTI_PC_xx, 3,20,20,L0|L1}, {GTI_MKL_xx, 3,20,20,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {SUINB_PA_xx, 3,23,23,L0|L1}, {SUINB_PB_xx, 3,23,23,L0|L1}, - {SUINB_PC_xx, 3,23,23,L0|L1}, {SUINB_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {LTI_PA_xx, 3,20,20,L0|L1}, {LTI_PB_xx, 3,20,20,L0|L1}, - {LTI_PC_xx, 3,20,20,L0|L1}, {LTI_MKL_xx, 3,20,20,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ADINC_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::ADINC_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::ADINC_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::ADINC_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::GTI_PA_xx, 3,20,20,L0|L1}, {&upd7810_device::GTI_PB_xx, 3,20,20,L0|L1}, + {&upd7810_device::GTI_PC_xx, 3,20,20,L0|L1}, {&upd7810_device::GTI_MKL_xx, 3,20,20,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::SUINB_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::SUINB_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::SUINB_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::SUINB_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::LTI_PA_xx, 3,20,20,L0|L1}, {&upd7810_device::LTI_PB_xx, 3,20,20,L0|L1}, + {&upd7810_device::LTI_PC_xx, 3,20,20,L0|L1}, {&upd7810_device::LTI_MKL_xx, 3,20,20,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xC0 - 0xDF */ - {ADI_PA_xx, 3,23,23,L0|L1}, {ADI_PB_xx, 3,23,23,L0|L1}, - {ADI_PC_xx, 3,23,23,L0|L1}, {ADI_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {ONI_PA_xx, 3,20,20,L0|L1}, {ONI_PB_xx, 3,20,20,L0|L1}, - {ONI_PC_xx, 3,20,20,L0|L1}, {ONI_MKL_xx, 3,20,20,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {ACI_PA_xx, 3,23,23,L0|L1}, {ACI_PB_xx, 3,23,23,L0|L1}, - {ACI_PC_xx, 3,23,23,L0|L1}, {ACI_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {OFFI_PA_xx, 3,20,20,L0|L1}, {OFFI_PB_xx, 3,20,20,L0|L1}, - {OFFI_PC_xx, 3,20,20,L0|L1}, {OFFI_MKL_xx, 3,20,20,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ADI_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::ADI_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::ADI_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::ADI_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ONI_PA_xx, 3,20,20,L0|L1}, {&upd7810_device::ONI_PB_xx, 3,20,20,L0|L1}, + {&upd7810_device::ONI_PC_xx, 3,20,20,L0|L1}, {&upd7810_device::ONI_MKL_xx, 3,20,20,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::ACI_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::ACI_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::ACI_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::ACI_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::OFFI_PA_xx, 3,20,20,L0|L1}, {&upd7810_device::OFFI_PB_xx, 3,20,20,L0|L1}, + {&upd7810_device::OFFI_PC_xx, 3,20,20,L0|L1}, {&upd7810_device::OFFI_MKL_xx, 3,20,20,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xE0 - 0xFF */ - {SUI_PA_xx, 3,23,23,L0|L1}, {SUI_PB_xx, 3,23,23,L0|L1}, - {SUI_PC_xx, 3,23,23,L0|L1}, {SUI_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {NEI_PA_xx, 3,20,20,L0|L1}, {NEI_PB_xx, 3,20,20,L0|L1}, - {NEI_PC_xx, 3,20,20,L0|L1}, {NEI_MKL_xx, 3,20,20,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {SBI_PA_xx, 3,23,23,L0|L1}, {SBI_PB_xx, 3,23,23,L0|L1}, - {SBI_PC_xx, 3,23,23,L0|L1}, {SBI_MKL_xx, 3,23,23,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {EQI_PA_xx, 3,20,20,L0|L1}, {EQI_PB_xx, 3,20,20,L0|L1}, - {EQI_PC_xx, 3,20,20,L0|L1}, {EQI_MKL_xx, 3,20,20,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1} + {&upd7810_device::SUI_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::SUI_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::SUI_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::SUI_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::NEI_PA_xx, 3,20,20,L0|L1}, {&upd7810_device::NEI_PB_xx, 3,20,20,L0|L1}, + {&upd7810_device::NEI_PC_xx, 3,20,20,L0|L1}, {&upd7810_device::NEI_MKL_xx, 3,20,20,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::SBI_PA_xx, 3,23,23,L0|L1}, {&upd7810_device::SBI_PB_xx, 3,23,23,L0|L1}, + {&upd7810_device::SBI_PC_xx, 3,23,23,L0|L1}, {&upd7810_device::SBI_MKL_xx, 3,23,23,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::EQI_PA_xx, 3,20,20,L0|L1}, {&upd7810_device::EQI_PB_xx, 3,20,20,L0|L1}, + {&upd7810_device::EQI_PC_xx, 3,20,20,L0|L1}, {&upd7810_device::EQI_MKL_xx, 3,20,20,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1} }; /* prefix 70 */ -static const struct opcode_s op70_78c06[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op70_78c06[256] = { /* 0x00 - 0x1F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SSPD_w, 4,28,28,L0|L1}, {LSPD_w, 4,28,28,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SBCD_w, 4,28,28,L0|L1}, {LBCD_w, 4,28,28,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SSPD_w, 4,28,28,L0|L1}, {&upd7810_device::LSPD_w, 4,28,28,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SBCD_w, 4,28,28,L0|L1}, {&upd7810_device::LBCD_w, 4,28,28,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SDED_w, 4,28,28,L0|L1}, {LDED_w, 4,28,28,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {SHLD_w, 4,28,28,L0|L1}, {LHLD_w, 4,28,28,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SDED_w, 4,28,28,L0|L1}, {&upd7810_device::LDED_w, 4,28,28,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::SHLD_w, 4,28,28,L0|L1}, {&upd7810_device::LHLD_w, 4,28,28,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {MOV_A_w, 4,25,25,L0|L1}, - {MOV_B_w, 4,25,25,L0|L1}, {MOV_C_w, 4,25,25,L0|L1}, - {MOV_D_w, 4,25,25,L0|L1}, {MOV_E_w, 4,25,25,L0|L1}, - {MOV_H_w, 4,25,25,L0|L1}, {MOV_L_w, 4,25,25,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {MOV_w_A, 4,25,25,L0|L1}, - {MOV_w_B, 4,25,25,L0|L1}, {MOV_w_C, 4,25,25,L0|L1}, - {MOV_w_D, 4,25,25,L0|L1}, {MOV_w_E, 4,25,25,L0|L1}, - {MOV_w_H, 4,25,25,L0|L1}, {MOV_w_L, 4,25,25,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::MOV_A_w, 4,25,25,L0|L1}, + {&upd7810_device::MOV_B_w, 4,25,25,L0|L1}, {&upd7810_device::MOV_C_w, 4,25,25,L0|L1}, + {&upd7810_device::MOV_D_w, 4,25,25,L0|L1}, {&upd7810_device::MOV_E_w, 4,25,25,L0|L1}, + {&upd7810_device::MOV_H_w, 4,25,25,L0|L1}, {&upd7810_device::MOV_L_w, 4,25,25,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::MOV_w_A, 4,25,25,L0|L1}, + {&upd7810_device::MOV_w_B, 4,25,25,L0|L1}, {&upd7810_device::MOV_w_C, 4,25,25,L0|L1}, + {&upd7810_device::MOV_w_D, 4,25,25,L0|L1}, {&upd7810_device::MOV_w_E, 4,25,25,L0|L1}, + {&upd7810_device::MOV_w_H, 4,25,25,L0|L1}, {&upd7810_device::MOV_w_L, 4,25,25,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ANAX_B, 2,15,15,L0|L1}, - {ANAX_D, 2,15,15,L0|L1}, {ANAX_H, 2,15,15,L0|L1}, - {ANAX_Dp, 2,15,15,L0|L1}, {ANAX_Hp, 2,15,15,L0|L1}, - {ANAX_Dm, 2,15,15,L0|L1}, {ANAX_Hm, 2,15,15,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {XRAX_B, 2,15,15,L0|L1}, - {XRAX_D, 2,15,15,L0|L1}, {XRAX_H, 2,15,15,L0|L1}, - {XRAX_Dp, 2,15,15,L0|L1}, {XRAX_Hp, 2,15,15,L0|L1}, - {XRAX_Dm, 2,15,15,L0|L1}, {XRAX_Hm, 2,15,15,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ORAX_B, 2,15,15,L0|L1}, - {ORAX_D, 2,15,15,L0|L1}, {ORAX_H, 2,15,15,L0|L1}, - {ORAX_Dp, 2,15,15,L0|L1}, {ORAX_Hp, 2,15,15,L0|L1}, - {ORAX_Dm, 2,15,15,L0|L1}, {ORAX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ANAX_B, 2,15,15,L0|L1}, + {&upd7810_device::ANAX_D, 2,15,15,L0|L1}, {&upd7810_device::ANAX_H, 2,15,15,L0|L1}, + {&upd7810_device::ANAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::ANAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::ANAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::ANAX_Hm, 2,15,15,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::XRAX_B, 2,15,15,L0|L1}, + {&upd7810_device::XRAX_D, 2,15,15,L0|L1}, {&upd7810_device::XRAX_H, 2,15,15,L0|L1}, + {&upd7810_device::XRAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::XRAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::XRAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::XRAX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ORAX_B, 2,15,15,L0|L1}, + {&upd7810_device::ORAX_D, 2,15,15,L0|L1}, {&upd7810_device::ORAX_H, 2,15,15,L0|L1}, + {&upd7810_device::ORAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::ORAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::ORAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::ORAX_Hm, 2,15,15,L0|L1}, /* 0xA0 - 0xBF */ - {illegal2, 2,12,12,L0|L1}, {ADDNCX_B, 2,15,15,L0|L1}, - {ADDNCX_D, 2,15,15,L0|L1}, {ADDNCX_H, 2,15,15,L0|L1}, - {ADDNCX_Dp, 2,15,15,L0|L1}, {ADDNCX_Hp, 2,15,15,L0|L1}, - {ADDNCX_Dm, 2,15,15,L0|L1}, {ADDNCX_Hm, 2,15,15,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {GTAX_B, 2,15,15,L0|L1}, - {GTAX_D, 2,15,15,L0|L1}, {GTAX_H, 2,15,15,L0|L1}, - {GTAX_Dp, 2,15,15,L0|L1}, {GTAX_Hp, 2,15,15,L0|L1}, - {GTAX_Dm, 2,15,15,L0|L1}, {GTAX_Hm, 2,15,15,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {SUBNBX_B, 2,15,15,L0|L1}, - {SUBNBX_D, 2,15,15,L0|L1}, {SUBNBX_H, 2,15,15,L0|L1}, - {SUBNBX_Dp, 2,15,15,L0|L1}, {SUBNBX_Hp, 2,15,15,L0|L1}, - {SUBNBX_Dm, 2,15,15,L0|L1}, {SUBNBX_Hm, 2,15,15,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {LTAX_B, 2,15,15,L0|L1}, - {LTAX_D, 2,15,15,L0|L1}, {LTAX_H, 2,15,15,L0|L1}, - {LTAX_Dp, 2,15,15,L0|L1}, {LTAX_Hp, 2,15,15,L0|L1}, - {LTAX_Dm, 2,15,15,L0|L1}, {LTAX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADDNCX_B, 2,15,15,L0|L1}, + {&upd7810_device::ADDNCX_D, 2,15,15,L0|L1}, {&upd7810_device::ADDNCX_H, 2,15,15,L0|L1}, + {&upd7810_device::ADDNCX_Dp, 2,15,15,L0|L1}, {&upd7810_device::ADDNCX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::ADDNCX_Dm, 2,15,15,L0|L1}, {&upd7810_device::ADDNCX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::GTAX_B, 2,15,15,L0|L1}, + {&upd7810_device::GTAX_D, 2,15,15,L0|L1}, {&upd7810_device::GTAX_H, 2,15,15,L0|L1}, + {&upd7810_device::GTAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::GTAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::GTAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::GTAX_Hm, 2,15,15,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SUBNBX_B, 2,15,15,L0|L1}, + {&upd7810_device::SUBNBX_D, 2,15,15,L0|L1}, {&upd7810_device::SUBNBX_H, 2,15,15,L0|L1}, + {&upd7810_device::SUBNBX_Dp, 2,15,15,L0|L1}, {&upd7810_device::SUBNBX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::SUBNBX_Dm, 2,15,15,L0|L1}, {&upd7810_device::SUBNBX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::LTAX_B, 2,15,15,L0|L1}, + {&upd7810_device::LTAX_D, 2,15,15,L0|L1}, {&upd7810_device::LTAX_H, 2,15,15,L0|L1}, + {&upd7810_device::LTAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::LTAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::LTAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::LTAX_Hm, 2,15,15,L0|L1}, /* 0xC0 - 0xDF */ - {illegal2, 2,12,12,L0|L1}, {ADDX_B, 2,15,15,L0|L1}, - {ADDX_D, 2,15,15,L0|L1}, {ADDX_H, 2,15,15,L0|L1}, - {ADDX_Dp, 2,15,15,L0|L1}, {ADDX_Hp, 2,15,15,L0|L1}, - {ADDX_Dm, 2,15,15,L0|L1}, {ADDX_Hm, 2,15,15,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {ONAX_B, 2,15,15,L0|L1}, - {ONAX_D, 2,15,15,L0|L1}, {ONAX_H, 2,15,15,L0|L1}, - {ONAX_Dp, 2,15,15,L0|L1}, {ONAX_Hp, 2,15,15,L0|L1}, - {ONAX_Dm, 2,15,15,L0|L1}, {ONAX_Hm, 2,15,15,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {ADCX_B, 2,15,15,L0|L1}, - {ADCX_D, 2,15,15,L0|L1}, {ADCX_H, 2,15,15,L0|L1}, - {ADCX_Dp, 2,15,15,L0|L1}, {ADCX_Hp, 2,15,15,L0|L1}, - {ADCX_Dm, 2,15,15,L0|L1}, {ADCX_Hm, 2,15,15,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {OFFAX_B, 2,15,15,L0|L1}, - {OFFAX_D, 2,15,15,L0|L1}, {OFFAX_H, 2,15,15,L0|L1}, - {OFFAX_Dp, 2,15,15,L0|L1}, {OFFAX_Hp, 2,15,15,L0|L1}, - {OFFAX_Dm, 2,15,15,L0|L1}, {OFFAX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADDX_B, 2,15,15,L0|L1}, + {&upd7810_device::ADDX_D, 2,15,15,L0|L1}, {&upd7810_device::ADDX_H, 2,15,15,L0|L1}, + {&upd7810_device::ADDX_Dp, 2,15,15,L0|L1}, {&upd7810_device::ADDX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::ADDX_Dm, 2,15,15,L0|L1}, {&upd7810_device::ADDX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ONAX_B, 2,15,15,L0|L1}, + {&upd7810_device::ONAX_D, 2,15,15,L0|L1}, {&upd7810_device::ONAX_H, 2,15,15,L0|L1}, + {&upd7810_device::ONAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::ONAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::ONAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::ONAX_Hm, 2,15,15,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::ADCX_B, 2,15,15,L0|L1}, + {&upd7810_device::ADCX_D, 2,15,15,L0|L1}, {&upd7810_device::ADCX_H, 2,15,15,L0|L1}, + {&upd7810_device::ADCX_Dp, 2,15,15,L0|L1}, {&upd7810_device::ADCX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::ADCX_Dm, 2,15,15,L0|L1}, {&upd7810_device::ADCX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::OFFAX_B, 2,15,15,L0|L1}, + {&upd7810_device::OFFAX_D, 2,15,15,L0|L1}, {&upd7810_device::OFFAX_H, 2,15,15,L0|L1}, + {&upd7810_device::OFFAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::OFFAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::OFFAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::OFFAX_Hm, 2,15,15,L0|L1}, /* 0xE0 - 0xFF */ - {illegal2, 2,12,12,L0|L1}, {SUBX_B, 2,15,15,L0|L1}, - {SUBX_D, 2,15,15,L0|L1}, {SUBX_H, 2,15,15,L0|L1}, - {SUBX_Dp, 2,15,15,L0|L1}, {SUBX_Hp, 2,15,15,L0|L1}, - {SUBX_Dm, 2,15,15,L0|L1}, {SUBX_Hm, 2,15,15,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {NEAX_B, 2,15,15,L0|L1}, - {NEAX_D, 2,15,15,L0|L1}, {NEAX_H, 2,15,15,L0|L1}, - {NEAX_Dp, 2,15,15,L0|L1}, {NEAX_Hp, 2,15,15,L0|L1}, - {NEAX_Dm, 2,15,15,L0|L1}, {NEAX_Hm, 2,15,15,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {SBBX_B, 2,15,15,L0|L1}, - {SBBX_D, 2,15,15,L0|L1}, {SBBX_H, 2,15,15,L0|L1}, - {SBBX_Dp, 2,15,15,L0|L1}, {SBBX_Hp, 2,15,15,L0|L1}, - {SBBX_Dm, 2,15,15,L0|L1}, {SBBX_Hm, 2,15,15,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {EQAX_B, 2,15,15,L0|L1}, - {EQAX_D, 2,15,15,L0|L1}, {EQAX_H, 2,15,15,L0|L1}, - {EQAX_Dp, 2,15,15,L0|L1}, {EQAX_Hp, 2,15,15,L0|L1}, - {EQAX_Dm, 2,15,15,L0|L1}, {EQAX_Hm, 2,15,15,L0|L1} + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SUBX_B, 2,15,15,L0|L1}, + {&upd7810_device::SUBX_D, 2,15,15,L0|L1}, {&upd7810_device::SUBX_H, 2,15,15,L0|L1}, + {&upd7810_device::SUBX_Dp, 2,15,15,L0|L1}, {&upd7810_device::SUBX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::SUBX_Dm, 2,15,15,L0|L1}, {&upd7810_device::SUBX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::NEAX_B, 2,15,15,L0|L1}, + {&upd7810_device::NEAX_D, 2,15,15,L0|L1}, {&upd7810_device::NEAX_H, 2,15,15,L0|L1}, + {&upd7810_device::NEAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::NEAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::NEAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::NEAX_Hm, 2,15,15,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::SBBX_B, 2,15,15,L0|L1}, + {&upd7810_device::SBBX_D, 2,15,15,L0|L1}, {&upd7810_device::SBBX_H, 2,15,15,L0|L1}, + {&upd7810_device::SBBX_Dp, 2,15,15,L0|L1}, {&upd7810_device::SBBX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::SBBX_Dm, 2,15,15,L0|L1}, {&upd7810_device::SBBX_Hm, 2,15,15,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::EQAX_B, 2,15,15,L0|L1}, + {&upd7810_device::EQAX_D, 2,15,15,L0|L1}, {&upd7810_device::EQAX_H, 2,15,15,L0|L1}, + {&upd7810_device::EQAX_Dp, 2,15,15,L0|L1}, {&upd7810_device::EQAX_Hp, 2,15,15,L0|L1}, + {&upd7810_device::EQAX_Dm, 2,15,15,L0|L1}, {&upd7810_device::EQAX_Hm, 2,15,15,L0|L1} }; /* prefix 74 */ -static const struct opcode_s op74_78c06[256] = +const struct upd7810_device::opcode_s upd7810_device::s_op74_78c06[256] = { /* 0x00 - 0x1F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x20 - 0x3F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x40 - 0x5F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x60 - 0x7F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0x80 - 0x9F */ - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {ANAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {XRAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {ORAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ANAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::XRAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ORAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xA0 - 0xBF */ - {ADDNCW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {GTAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {SUBNBW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {LTAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ADDNCW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::GTAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::SUBNBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::LTAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xC0 - 0xDF */ - {ADDW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {ONAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {ADCW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {OFFAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ADDW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::ONAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::ADCW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::OFFAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, /* 0xE0 - 0xFF */ - {SUBW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {NEAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - - {SBBW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {EQAW_wa, 3,14,14,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1}, - {illegal2, 2,12,12,L0|L1}, {illegal2, 2,12,12,L0|L1} + {&upd7810_device::SUBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::NEAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + + {&upd7810_device::SBBW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::EQAW_wa, 3,14,14,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1}, + {&upd7810_device::illegal2, 2,12,12,L0|L1}, {&upd7810_device::illegal2, 2,12,12,L0|L1} }; -static const struct opcode_s opXX_78c06[256] = +const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c06[256] = { /* 0x00 - 0x1F */ - {NOP, 1, 6, 6,L0|L1}, {HALT, 1, 6, 6,L0|L1}, - {INX_SP, 1, 9, 9,L0|L1}, {DCX_SP, 1, 9, 9,L0|L1}, - {LXI_S_w, 3,16,16,L0|L1}, {ANIW_wa_xx, 3,22,22,L0|L1}, - {illegal, 1, 6, 6,L0|L1}, {ANI_A_xx, 2,11,11,L0|L1}, - {RET, 1,12,12,L0|L1}, {SIO, 1, 6, 6,L0|L1}, - {MOV_A_B, 1, 6, 6,L0|L1}, {MOV_A_C, 1, 6, 6,L0|L1}, - {MOV_A_D, 1, 6, 6,L0|L1}, {MOV_A_E, 1, 6, 6,L0|L1}, - {MOV_A_H, 1, 6, 6,L0|L1}, {MOV_A_L, 1, 6, 6,L0|L1}, - - {illegal, 1, 6, 6,L0|L1}, {illegal, 1, 6, 6,L0|L1}, - {INX_BC, 1, 9, 9,L0|L1}, {DCX_BC, 1, 9, 9,L0|L1}, - {LXI_B_w, 3,16,16,L0|L1}, {ORIW_wa_xx, 3,22,2,L0|L1}, - {XRI_A_xx, 2,11,11,L0|L1}, {ORI_A_xx, 2,11,11,L0|L1}, - {RETS, 1,12,12,L0|L1}, {STM, 1, 6, 6,L0|L1}, - {MOV_B_A, 1, 6, 6,L0|L1}, {MOV_C_A, 1, 6, 6,L0|L1}, - {MOV_D_A, 1, 6, 6,L0|L1}, {MOV_E_A, 1, 6, 6,L0|L1}, - {MOV_H_A, 1, 6, 6,L0|L1}, {MOV_L_A, 1, 6, 6,L0|L1}, + {&upd7810_device::NOP, 1, 6, 6,L0|L1}, {&upd7810_device::HALT, 1, 6, 6,L0|L1}, + {&upd7810_device::INX_SP, 1, 9, 9,L0|L1}, {&upd7810_device::DCX_SP, 1, 9, 9,L0|L1}, + {&upd7810_device::LXI_S_w, 3,16,16,L0|L1}, {&upd7810_device::ANIW_wa_xx, 3,22,22,L0|L1}, + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::ANI_A_xx, 2,11,11,L0|L1}, + {&upd7810_device::RET, 1,12,12,L0|L1}, {&upd7810_device::SIO, 1, 6, 6,L0|L1}, + {&upd7810_device::MOV_A_B, 1, 6, 6,L0|L1}, {&upd7810_device::MOV_A_C, 1, 6, 6,L0|L1}, + {&upd7810_device::MOV_A_D, 1, 6, 6,L0|L1}, {&upd7810_device::MOV_A_E, 1, 6, 6,L0|L1}, + {&upd7810_device::MOV_A_H, 1, 6, 6,L0|L1}, {&upd7810_device::MOV_A_L, 1, 6, 6,L0|L1}, + + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1}, + {&upd7810_device::INX_BC, 1, 9, 9,L0|L1}, {&upd7810_device::DCX_BC, 1, 9, 9,L0|L1}, + {&upd7810_device::LXI_B_w, 3,16,16,L0|L1}, {&upd7810_device::ORIW_wa_xx, 3,22,2,L0|L1}, + {&upd7810_device::XRI_A_xx, 2,11,11,L0|L1}, {&upd7810_device::ORI_A_xx, 2,11,11,L0|L1}, + {&upd7810_device::RETS, 1,12,12,L0|L1}, {&upd7810_device::STM, 1, 6, 6,L0|L1}, + {&upd7810_device::MOV_B_A, 1, 6, 6,L0|L1}, {&upd7810_device::MOV_C_A, 1, 6, 6,L0|L1}, + {&upd7810_device::MOV_D_A, 1, 6, 6,L0|L1}, {&upd7810_device::MOV_E_A, 1, 6, 6,L0|L1}, + {&upd7810_device::MOV_H_A, 1, 6, 6,L0|L1}, {&upd7810_device::MOV_L_A, 1, 6, 6,L0|L1}, /* 0x20 - 0x3F */ - {INRW_wa_7801, 2,17,17,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {INX_DE, 1, 9, 9,L0|L1}, {DCX_DE, 1, 9, 9,L0|L1}, - {LXI_D_w, 3,16,16,L0|L1}, {GTIW_wa_xx, 3,19,19,L0|L1}, - {ADINC_A_xx, 2,11,11,L0|L1}, {GTI_A_xx, 2,11,11,L0|L1}, - {LDAW_wa, 2,14,14,L0|L1}, {LDAX_B, 1, 9, 9,L0|L1}, - {LDAX_D, 1, 9, 9,L0|L1}, {LDAX_H, 1, 9, 9,L0|L1}, - {LDAX_Dp, 1, 9, 9,L0|L1}, {LDAX_Hp, 1, 9, 9,L0|L1}, - {LDAX_Dm, 1, 9, 9,L0|L1}, {LDAX_Hm, 1, 9, 9,L0|L1}, - - {DCRW_wa_7801, 2,17,17,L0|L1}, {illegal, 1, 4, 4,L0|L1}, - {INX_HL, 1, 9, 9,L0|L1}, {DCX_HL, 1, 9, 9,L0|L1}, - {LXI_H_w, 3,16,16, L1}, {LTIW_wa_xx, 3,19,19,L0|L1}, - {SUINB_A_xx, 2,11,11,L0|L1}, {LTI_A_xx, 2,11,11,L0|L1}, - {STAW_wa, 2,14,14,L0|L1}, {STAX_B, 1, 9, 9,L0|L1}, - {STAX_D, 1, 9, 9,L0|L1}, {STAX_H, 1, 9, 9,L0|L1}, - {STAX_Dp, 1, 9, 9,L0|L1}, {STAX_Hp, 1, 9, 9,L0|L1}, - {STAX_Dm, 1, 9, 9,L0|L1}, {STAX_Hm, 1, 9, 9,L0|L1}, + {&upd7810_device::INRW_wa_7801, 2,17,17,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::INX_DE, 1, 9, 9,L0|L1}, {&upd7810_device::DCX_DE, 1, 9, 9,L0|L1}, + {&upd7810_device::LXI_D_w, 3,16,16,L0|L1}, {&upd7810_device::GTIW_wa_xx, 3,19,19,L0|L1}, + {&upd7810_device::ADINC_A_xx, 2,11,11,L0|L1}, {&upd7810_device::GTI_A_xx, 2,11,11,L0|L1}, + {&upd7810_device::LDAW_wa, 2,14,14,L0|L1}, {&upd7810_device::LDAX_B, 1, 9, 9,L0|L1}, + {&upd7810_device::LDAX_D, 1, 9, 9,L0|L1}, {&upd7810_device::LDAX_H, 1, 9, 9,L0|L1}, + {&upd7810_device::LDAX_Dp, 1, 9, 9,L0|L1}, {&upd7810_device::LDAX_Hp, 1, 9, 9,L0|L1}, + {&upd7810_device::LDAX_Dm, 1, 9, 9,L0|L1}, {&upd7810_device::LDAX_Hm, 1, 9, 9,L0|L1}, + + {&upd7810_device::DCRW_wa_7801, 2,17,17,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1}, + {&upd7810_device::INX_HL, 1, 9, 9,L0|L1}, {&upd7810_device::DCX_HL, 1, 9, 9,L0|L1}, + {&upd7810_device::LXI_H_w, 3,16,16, L1}, {&upd7810_device::LTIW_wa_xx, 3,19,19,L0|L1}, + {&upd7810_device::SUINB_A_xx, 2,11,11,L0|L1}, {&upd7810_device::LTI_A_xx, 2,11,11,L0|L1}, + {&upd7810_device::STAW_wa, 2,14,14,L0|L1}, {&upd7810_device::STAX_B, 1, 9, 9,L0|L1}, + {&upd7810_device::STAX_D, 1, 9, 9,L0|L1}, {&upd7810_device::STAX_H, 1, 9, 9,L0|L1}, + {&upd7810_device::STAX_Dp, 1, 9, 9,L0|L1}, {&upd7810_device::STAX_Hp, 1, 9, 9,L0|L1}, + {&upd7810_device::STAX_Dm, 1, 9, 9,L0|L1}, {&upd7810_device::STAX_Hm, 1, 9, 9,L0|L1}, /* 0x40 - 0x5F */ - {illegal, 1, 6, 6,L0|L1}, {INR_A_7801, 1, 6, 6,L0|L1}, - {INR_B_7801, 1, 6, 6,L0|L1}, {INR_C_7801, 1, 6, 6,L0|L1}, - {CALL_w, 3,22,22,L0|L1}, {ONIW_wa_xx, 3,19,19,L0|L1}, - {ADI_A_xx, 2,11,11,L0|L1}, {ONI_A_xx, 2,11,11,L0|L1}, - {PRE_48, 1, 0, 0,L0|L1}, {illegal, 1, 6, 6,L0|L1}, - {illegal, 1, 6, 6,L0|L1}, {illegal, 1, 6, 6,L0|L1}, - {PRE_4C, 1, 0, 0,L0|L1}, {PRE_4D, 1, 0, 0,L0|L1}, - {JRE, 2,17,17,L0|L1}, {JRE, 2,17,17,L0|L1}, - - {illegal, 1, 6, 6,L0|L1}, {DCR_A_7801, 1, 6, 6,L0|L1}, - {DCR_B_7801, 1, 6, 6,L0|L1}, {DCR_C_7801, 1, 6, 6,L0|L1}, - {JMP_w, 3,16,16,L0|L1}, {OFFIW_wa_xx, 3,19,19,L0|L1}, - {ACI_A_xx, 2,11,11,L0|L1}, {OFFI_A_xx, 2,11,11,L0|L1}, - {illegal, 1, 6, 6,L0|L1}, {illegal, 1, 6, 6,L0|L1}, - {illegal, 1, 6, 6,L0|L1}, {illegal, 1, 6, 6,L0|L1}, - {illegal, 1, 6, 6,L0|L1}, {illegal, 1, 6, 6,L0|L1}, - {illegal, 1, 6, 6,L0|L1}, {illegal, 1, 6, 6,L0|L1}, + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::INR_A_7801, 1, 6, 6,L0|L1}, + {&upd7810_device::INR_B_7801, 1, 6, 6,L0|L1}, {&upd7810_device::INR_C_7801, 1, 6, 6,L0|L1}, + {&upd7810_device::CALL_w, 3,22,22,L0|L1}, {&upd7810_device::ONIW_wa_xx, 3,19,19,L0|L1}, + {&upd7810_device::ADI_A_xx, 2,11,11,L0|L1}, {&upd7810_device::ONI_A_xx, 2,11,11,L0|L1}, + {&upd7810_device::PRE_48, 1, 0, 0,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1}, + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1}, + {&upd7810_device::PRE_4C, 1, 0, 0,L0|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0|L1}, + {&upd7810_device::JRE, 2,17,17,L0|L1}, {&upd7810_device::JRE, 2,17,17,L0|L1}, + + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::DCR_A_7801, 1, 6, 6,L0|L1}, + {&upd7810_device::DCR_B_7801, 1, 6, 6,L0|L1}, {&upd7810_device::DCR_C_7801, 1, 6, 6,L0|L1}, + {&upd7810_device::JMP_w, 3,16,16,L0|L1}, {&upd7810_device::OFFIW_wa_xx, 3,19,19,L0|L1}, + {&upd7810_device::ACI_A_xx, 2,11,11,L0|L1}, {&upd7810_device::OFFI_A_xx, 2,11,11,L0|L1}, + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1}, + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1}, + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1}, + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1}, /* 0x60 - 0x7F */ - {PRE_60, 1, 0, 0,L0|L1}, {DAA, 1, 6, 6,L0|L1}, - {RETI, 1,15,15,L0|L1}, {CALB, 2,13,13,L0|L1}, - {PRE_64, 1, 0, 0,L0|L1}, {NEIW_wa_xx, 3,19,19,L0|L1}, - {SUI_A_xx, 2,11,11,L0|L1}, {NEI_A_xx, 2,11,11,L0|L1}, - {illegal, 1, 6, 6,L0|L1}, {MVI_A_xx, 2,11,11,L0 }, - {MVI_B_xx, 2,11,11,L0|L1}, {MVI_C_xx, 2,11,11,L0|L1}, - {MVI_D_xx, 2,11,11,L0|L1}, {MVI_E_xx, 2,11,11,L0|L1}, - {MVI_H_xx, 2,11,11,L0|L1}, {MVI_L_xx, 2,11,11, L1}, - - {PRE_70, 1, 0, 0,L0|L1}, {MVIW_wa_xx, 3,13,13,L0|L1}, - {SOFTI, 1,19,19,L0|L1}, {JB, 1, 6, 6,L0|L1}, - {PRE_74, 1, 0, 0,L0|L1}, {EQIW_wa_xx, 3,19,19,L0|L1}, - {SBI_A_xx, 2,11,11,L0|L1}, {EQI_A_xx, 2,11,11,L0|L1}, - {CALF, 2,17,17,L0|L1}, {CALF, 2,17,17,L0|L1}, - {CALF, 2,17,17,L0|L1}, {CALF, 2,17,17,L0|L1}, - {CALF, 2,17,17,L0|L1}, {CALF, 2,17,17,L0|L1}, - {CALF, 2,17,17,L0|L1}, {CALF, 2,17,17,L0|L1}, + {&upd7810_device::PRE_60, 1, 0, 0,L0|L1}, {&upd7810_device::DAA, 1, 6, 6,L0|L1}, + {&upd7810_device::RETI, 1,15,15,L0|L1}, {&upd7810_device::CALB, 2,13,13,L0|L1}, + {&upd7810_device::PRE_64, 1, 0, 0,L0|L1}, {&upd7810_device::NEIW_wa_xx, 3,19,19,L0|L1}, + {&upd7810_device::SUI_A_xx, 2,11,11,L0|L1}, {&upd7810_device::NEI_A_xx, 2,11,11,L0|L1}, + {&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::MVI_A_xx, 2,11,11,L0 }, + {&upd7810_device::MVI_B_xx, 2,11,11,L0|L1}, {&upd7810_device::MVI_C_xx, 2,11,11,L0|L1}, + {&upd7810_device::MVI_D_xx, 2,11,11,L0|L1}, {&upd7810_device::MVI_E_xx, 2,11,11,L0|L1}, + {&upd7810_device::MVI_H_xx, 2,11,11,L0|L1}, {&upd7810_device::MVI_L_xx, 2,11,11, L1}, + + {&upd7810_device::PRE_70, 1, 0, 0,L0|L1}, {&upd7810_device::MVIW_wa_xx, 3,13,13,L0|L1}, + {&upd7810_device::SOFTI, 1,19,19,L0|L1}, {&upd7810_device::JB, 1, 6, 6,L0|L1}, + {&upd7810_device::PRE_74, 1, 0, 0,L0|L1}, {&upd7810_device::EQIW_wa_xx, 3,19,19,L0|L1}, + {&upd7810_device::SBI_A_xx, 2,11,11,L0|L1}, {&upd7810_device::EQI_A_xx, 2,11,11,L0|L1}, + {&upd7810_device::CALF, 2,17,17,L0|L1}, {&upd7810_device::CALF, 2,17,17,L0|L1}, + {&upd7810_device::CALF, 2,17,17,L0|L1}, {&upd7810_device::CALF, 2,17,17,L0|L1}, + {&upd7810_device::CALF, 2,17,17,L0|L1}, {&upd7810_device::CALF, 2,17,17,L0|L1}, + {&upd7810_device::CALF, 2,17,17,L0|L1}, {&upd7810_device::CALF, 2,17,17,L0|L1}, /* 0x80 - 0x9F */ - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, /* 0xA0 - 0xBF */ - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, - {CALT_7801, 1,19,19,L0|L1}, {CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, + {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, {&upd7810_device::CALT_7801, 1,19,19,L0|L1}, /* 0xC0 - 0xDF */ - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, /* 0xE0 - 0xFF */ - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1}, - {JR, 1,12,12,L0|L1}, {JR, 1,12,12,L0|L1} + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1}, + {&upd7810_device::JR, 1,12,12,L0|L1}, {&upd7810_device::JR, 1,12,12,L0|L1} }; diff --git a/src/emu/cpu/upd7810/upd7810.c b/src/emu/cpu/upd7810/upd7810.c index aa391ee4bb2..04e11049150 100644 --- a/src/emu/cpu/upd7810/upd7810.c +++ b/src/emu/cpu/upd7810/upd7810.c @@ -45,7 +45,7 @@ * "NEC Electronics User's Manual, April 1987" * * NS20030115: - * - fixed INRW_wa(cpustate) + * - fixed INRW_wa() * - TODO: add 7807, differences are listed below. * I only added support for these opcodes needed by homedata.c (yes, I am * lazy): @@ -408,114 +408,124 @@ STOP 01001000 10111011 12 stop #include "debugger.h" #include "upd7810.h" -struct upd7810_state + +const device_type UPD7810 = &device_creator<upd7810_device>; +const device_type UPD7807 = &device_creator<upd7807_device>; +const device_type UPD7801 = &device_creator<upd7801_device>; +const device_type UPD78C05 = &device_creator<upd78c05_device>; +const device_type UPD78C06 = &device_creator<upd78c06_device>; + + +upd7810_device::upd7810_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : cpu_device(mconfig, UPD7810, "uPD7810", tag, owner, clock, "upd7810", __FILE__) + , m_to_func(*this) + , m_txd_func(*this) + , m_rxd_func(*this) + , m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0) + , m_io_config("io", ENDIANNESS_LITTLE, 8, 8, 0) +{ + m_opXX = s_opXX_7810; + m_op48 = s_op48; + m_op4C = s_op4C; + m_op4D = s_op4D; + m_op60 = s_op60; + m_op64 = s_op64; + m_op70 = s_op70; + m_op74 = s_op74; +} + +upd7810_device::upd7810_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source) + , m_to_func(*this) + , m_txd_func(*this) + , m_rxd_func(*this) + , m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0) + , m_io_config("io", ENDIANNESS_LITTLE, 8, 8, 0) +{ +} + +upd7807_device::upd7807_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upd7810_device(mconfig, UPD7807, "uPD7807", tag, owner, clock, "upd7807", __FILE__) +{ + m_opXX = s_opXX_7807; + m_op48 = s_op48; + m_op4C = s_op4C; + m_op4D = s_op4D; + m_op60 = s_op60; + m_op64 = s_op64; + m_op70 = s_op70; + m_op74 = s_op74; +} + +upd7801_device::upd7801_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upd7810_device(mconfig, UPD7801, "uPD7801", tag, owner, clock, "upd7801", __FILE__) +{ + m_op48 = s_op48_7801; + m_op4C = s_op4C_7801; + m_op4D = s_op4D_7801; + m_op60 = s_op60_7801; + m_op64 = s_op64_7801; + m_op70 = s_op70_7801; + m_op74 = s_op74_7801; + m_opXX = s_opXX_7801; +} + +upd78c05_device::upd78c05_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upd7810_device(mconfig, UPD78C05, "uPD78C05", tag, owner, clock, "upd78c05", __FILE__) +{ + m_op48 = s_op48_78c05; + m_op4C = s_op4C_78c05; + m_op4D = s_op4D_78c05; + m_op60 = s_op60_78c05; + m_op64 = s_op64_78c05; + m_op70 = s_op70_78c05; + m_op74 = s_op74_78c05; + m_opXX = s_opXX_78c05; +} + +upd78c05_device::upd78c05_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) + : upd7810_device(mconfig, type, name, tag, owner, clock, shortname, source) +{ +} + +upd78c06_device::upd78c06_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : upd78c05_device(mconfig, UPD78C06, "uPD78C06", tag, owner, clock, "upd78c06", __FILE__) +{ + m_op48 = s_op48_78c06; + m_op4C = s_op4C_78c06; + m_op4D = s_op4D_78c06; + m_op60 = s_op60_78c06; + m_op64 = s_op64_78c06; + m_op70 = s_op70_78c06; + m_op74 = s_op74_78c06; + m_opXX = s_opXX_78c06; +} + +offs_t upd7810_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( upd7810 ); + return CPU_DISASSEMBLE_NAME(upd7810)(this, buffer, pc, oprom, opram, options); +} + +offs_t upd7807_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( upd7807 ); + return CPU_DISASSEMBLE_NAME(upd7807)(this, buffer, pc, oprom, opram, options); +} + +offs_t upd7801_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - PAIR ppc; /* previous program counter */ - PAIR pc; /* program counter */ - PAIR sp; /* stack pointer */ - UINT8 op; /* opcode */ - UINT8 op2; /* opcode part 2 */ - UINT8 iff; /* interrupt enable flip flop */ - UINT8 psw; /* processor status word */ - PAIR ea; /* extended accumulator */ - PAIR va; /* accumulator + vector register */ - PAIR bc; /* 8bit B and C registers / 16bit BC register */ - PAIR de; /* 8bit D and E registers / 16bit DE register */ - PAIR hl; /* 8bit H and L registers / 16bit HL register */ - PAIR ea2; /* alternate register set */ - PAIR va2; - PAIR bc2; - PAIR de2; - PAIR hl2; - PAIR cnt; /* 8 bit timer counter */ - PAIR tm; /* 8 bit timer 0/1 comparator inputs */ - PAIR ecnt; /* timer counter register / capture register */ - PAIR etm; /* timer 0/1 comparator inputs */ - UINT8 ma; /* port A input or output mask */ - UINT8 mb; /* port B input or output mask */ - UINT8 mcc; /* port C control/port select */ - UINT8 mc; /* port C input or output mask */ - UINT8 mm; /* memory mapping */ - UINT8 mf; /* port F input or output mask */ - UINT8 tmm; /* timer 0 and timer 1 operating parameters */ - UINT8 etmm; /* 16-bit multifunction timer/event counter */ - UINT8 eom; /* 16-bit timer/event counter output control */ - UINT8 sml; /* serial interface parameters low */ - UINT8 smh; /* -"- high */ - UINT8 anm; /* analog to digital converter operating parameters */ - UINT8 mkl; /* interrupt mask low */ - UINT8 mkh; /* -"- high */ - UINT8 zcm; /* bias circuitry for ac zero-cross detection */ - UINT8 pa_in; /* port A,B,C,D,F inputs */ - UINT8 pb_in; - UINT8 pc_in; - UINT8 pd_in; - UINT8 pf_in; - UINT8 pa_out; /* port A,B,C,D,F outputs */ - UINT8 pb_out; - UINT8 pc_out; - UINT8 pd_out; - UINT8 pf_out; - UINT8 cr0; /* analog digital conversion register 0 */ - UINT8 cr1; /* analog digital conversion register 1 */ - UINT8 cr2; /* analog digital conversion register 2 */ - UINT8 cr3; /* analog digital conversion register 3 */ - UINT8 txb; /* transmitter buffer */ - UINT8 rxb; /* receiver buffer */ - UINT8 txd; /* port C control line states */ - UINT8 rxd; - UINT8 sck; - UINT8 ti; - UINT8 to; - UINT8 ci; - UINT8 co0; - UINT8 co1; - UINT16 irr; /* interrupt request register */ - UINT16 itf; /* interrupt test flag register */ - int int1; /* keep track of current int1 state. Needed for 7801 irq checking. */ - int int2; /* keep track to current int2 state. Needed for 7801 irq checking. */ - -/* internal helper variables */ - UINT16 txs; /* transmitter shift register */ - UINT16 rxs; /* receiver shift register */ - UINT8 txcnt; /* transmitter shift register bit count */ - UINT8 rxcnt; /* receiver shift register bit count */ - UINT8 txbuf; /* transmitter buffer was written */ - INT32 ovc0; /* overflow counter for timer 0 (for clock div 12/384) */ - INT32 ovc1; /* overflow counter for timer 0 (for clock div 12/384) */ - INT32 ovce; /* overflow counter for ecnt */ - INT32 ovcf; /* overflow counter for fixed clock div 3 mode */ - INT32 ovcs; /* overflow counter for serial I/O */ - UINT8 edges; /* rising/falling edge flag for serial I/O */ - const struct opcode_s *opXX; /* opcode table */ - const struct opcode_s *op48; - const struct opcode_s *op4C; - const struct opcode_s *op4D; - const struct opcode_s *op60; - const struct opcode_s *op64; - const struct opcode_s *op70; - const struct opcode_s *op74; - void (*handle_timers)(upd7810_state *cpustate, int cycles); - UPD7810_CONFIG config; - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - address_space *program; - direct_read_data *direct; - address_space *io; - int icount; -}; - -INLINE upd7810_state *get_safe_token(device_t *device) + extern CPU_DISASSEMBLE( upd7801 ); + return CPU_DISASSEMBLE_NAME(upd7801)(this, buffer, pc, oprom, opram, options); +} + +offs_t upd78c05_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - assert(device != NULL); - assert(device->type() == UPD7810 || - device->type() == UPD7807 || - device->type() == UPD7801 || - device->type() == UPD78C05 || - device->type() == UPD78C06); - return (upd7810_state *)downcast<legacy_cpu_device *>(device)->token(); + extern CPU_DISASSEMBLE( upd78c05 ); + return CPU_DISASSEMBLE_NAME(upd78c05)(this, buffer, pc, oprom, opram, options); } + #define CY 0x01 #define F1 0x02 #define L0 0x04 @@ -548,104 +558,97 @@ INLINE upd7810_state *get_safe_token(device_t *device) #define INTAN7 0x0008 #define INTSB 0x0010 -#define PPC cpustate->ppc.w.l -#define PC cpustate->pc.w.l -#define PCL cpustate->pc.b.l -#define PCH cpustate->pc.b.h -#define PCD cpustate->pc.d -#define SP cpustate->sp.w.l -#define SPL cpustate->sp.b.l -#define SPH cpustate->sp.b.h -#define SPD cpustate->sp.d -#define PSW cpustate->psw -#define OP cpustate->op -#define OP2 cpustate->op2 -#define IFF cpustate->iff -#define EA cpustate->ea.w.l -#define EAL cpustate->ea.b.l -#define EAH cpustate->ea.b.h -#define VA cpustate->va.w.l -#define V cpustate->va.b.h -#define A cpustate->va.b.l -#define VAD cpustate->va.d -#define BC cpustate->bc.w.l -#define B cpustate->bc.b.h -#define C cpustate->bc.b.l -#define DE cpustate->de.w.l -#define D cpustate->de.b.h -#define E cpustate->de.b.l -#define HL cpustate->hl.w.l -#define H cpustate->hl.b.h -#define L cpustate->hl.b.l -#define EA2 cpustate->ea2.w.l -#define VA2 cpustate->va2.w.l -#define BC2 cpustate->bc2.w.l -#define DE2 cpustate->de2.w.l -#define HL2 cpustate->hl2.w.l - -#define OVC0 cpustate->ovc0 -#define OVC1 cpustate->ovc1 -#define OVCE cpustate->ovce -#define OVCF cpustate->ovcf -#define OVCS cpustate->ovcs -#define EDGES cpustate->edges - -#define CNT0 cpustate->cnt.b.l -#define CNT1 cpustate->cnt.b.h -#define TM0 cpustate->tm.b.l -#define TM1 cpustate->tm.b.h -#define ECNT cpustate->ecnt.w.l -#define ECPT cpustate->ecnt.w.h -#define ETM0 cpustate->etm.w.l -#define ETM1 cpustate->etm.w.h - -#define MA cpustate->ma -#define MB cpustate->mb -#define MCC cpustate->mcc -#define MC cpustate->mc -#define MM cpustate->mm -#define MF cpustate->mf -#define TMM cpustate->tmm -#define ETMM cpustate->etmm -#define EOM cpustate->eom -#define SML cpustate->sml -#define SMH cpustate->smh -#define ANM cpustate->anm -#define MKL cpustate->mkl -#define MKH cpustate->mkh -#define ZCM cpustate->zcm - -#define CR0 cpustate->cr0 -#define CR1 cpustate->cr1 -#define CR2 cpustate->cr2 -#define CR3 cpustate->cr3 -#define RXB cpustate->rxb -#define TXB cpustate->txb - -#define RXD cpustate->rxd -#define TXD cpustate->txd -#define SCK cpustate->sck -#define TI cpustate->ti -#define TO cpustate->to -#define CI cpustate->ci -#define CO0 cpustate->co0 -#define CO1 cpustate->co1 - -#define IRR cpustate->irr -#define ITF cpustate->itf - -struct opcode_s { - void (*opfunc)(upd7810_state *cpustate); - UINT8 oplen; - UINT8 cycles; - UINT8 cycles_skip; - UINT8 mask_l0_l1; -}; - -#define RDOP(O) O = cpustate->direct->read_decrypted_byte(PCD); PC++ -#define RDOPARG(A) A = cpustate->direct->read_raw_byte(PCD); PC++ -#define RM(A) cpustate->program->read_byte(A) -#define WM(A,V) cpustate->program->write_byte(A,V) +#define PPC m_ppc.w.l +#define PC m_pc.w.l +#define PCL m_pc.b.l +#define PCH m_pc.b.h +#define PCD m_pc.d +#define SP m_sp.w.l +#define SPL m_sp.b.l +#define SPH m_sp.b.h +#define SPD m_sp.d +#define PSW m_psw +#define OP m_op +#define OP2 m_op2 +#define IFF m_iff +#define EA m_ea.w.l +#define EAL m_ea.b.l +#define EAH m_ea.b.h +#define VA m_va.w.l +#define V m_va.b.h +#define A m_va.b.l +#define VAD m_va.d +#define BC m_bc.w.l +#define B m_bc.b.h +#define C m_bc.b.l +#define DE m_de.w.l +#define D m_de.b.h +#define E m_de.b.l +#define HL m_hl.w.l +#define H m_hl.b.h +#define L m_hl.b.l +#define EA2 m_ea2.w.l +#define VA2 m_va2.w.l +#define BC2 m_bc2.w.l +#define DE2 m_de2.w.l +#define HL2 m_hl2.w.l + +#define OVC0 m_ovc0 +#define OVC1 m_ovc1 +#define OVCE m_ovce +#define OVCF m_ovcf +#define OVCS m_ovcs +#define EDGES m_edges + +#define CNT0 m_cnt.b.l +#define CNT1 m_cnt.b.h +#define TM0 m_tm.b.l +#define TM1 m_tm.b.h +#define ECNT m_ecnt.w.l +#define ECPT m_ecnt.w.h +#define ETM0 m_etm.w.l +#define ETM1 m_etm.w.h + +#define MA m_ma +#define MB m_mb +#define MCC m_mcc +#define MC m_mc +#define MM m_mm +#define MF m_mf +#define TMM m_tmm +#define ETMM m_etmm +#define EOM m_eom +#define SML m_sml +#define SMH m_smh +#define ANM m_anm +#define MKL m_mkl +#define MKH m_mkh +#define ZCM m_zcm + +#define CR0 m_cr0 +#define CR1 m_cr1 +#define CR2 m_cr2 +#define CR3 m_cr3 +#define RXB m_rxb +#define TXB m_txb + +#define RXD m_rxd +#define TXD m_txd +#define SCK m_sck +#define TI m_ti +#define TO m_to +#define CI m_ci +#define CO0 m_co0 +#define CO1 m_co1 + +#define IRR m_irr +#define ITF m_itf + + +#define RDOP(O) O = m_direct->read_decrypted_byte(PCD); PC++ +#define RDOPARG(A) A = m_direct->read_raw_byte(PCD); PC++ +#define RM(A) m_program->read_byte(A) +#define WM(A,V) m_program->write_byte(A,V) #define ZHC_ADD(after,before,carry) \ if (after == 0) PSW |= Z; else PSW &= ~Z; \ @@ -677,51 +680,51 @@ struct opcode_s { #define SKIP_NZ if (0 == (PSW & Z)) PSW |= SK #define SET_Z(n) if (n) PSW &= ~Z; else PSW |= Z -static UINT8 RP(upd7810_state *cpustate, offs_t port) +UINT8 upd7810_device::RP(offs_t port) { UINT8 data = 0xff; switch (port) { case UPD7810_PORTA: - if (cpustate->ma) // NS20031301 no need to read if the port is set as output - cpustate->pa_in = cpustate->io->read_byte(port); - data = (cpustate->pa_in & cpustate->ma) | (cpustate->pa_out & ~cpustate->ma); + if (m_ma) // NS20031301 no need to read if the port is set as output + m_pa_in = m_io->read_byte(port); + data = (m_pa_in & m_ma) | (m_pa_out & ~m_ma); break; case UPD7810_PORTB: - if (cpustate->mb) // NS20031301 no need to read if the port is set as output - cpustate->pb_in = cpustate->io->read_byte(port); - data = (cpustate->pb_in & cpustate->mb) | (cpustate->pb_out & ~cpustate->mb); + if (m_mb) // NS20031301 no need to read if the port is set as output + m_pb_in = m_io->read_byte(port); + data = (m_pb_in & m_mb) | (m_pb_out & ~m_mb); break; case UPD7810_PORTC: - if (cpustate->mc) // NS20031301 no need to read if the port is set as output - cpustate->pc_in = cpustate->io->read_byte(port); - data = (cpustate->pc_in & cpustate->mc) | (cpustate->pc_out & ~cpustate->mc); - if (cpustate->mcc & 0x01) /* PC0 = TxD output */ - data = (data & ~0x01) | (cpustate->txd & 1 ? 0x01 : 0x00); - if (cpustate->mcc & 0x02) /* PC1 = RxD input */ - data = (data & ~0x02) | (cpustate->rxd & 1 ? 0x02 : 0x00); - if (cpustate->mcc & 0x04) /* PC2 = SCK input/output */ - data = (data & ~0x04) | (cpustate->sck & 1 ? 0x04 : 0x00); - if (cpustate->mcc & 0x08) /* PC3 = TI input */ - data = (data & ~0x08) | (cpustate->ti & 1 ? 0x08 : 0x00); - if (cpustate->mcc & 0x10) /* PC4 = TO output */ - data = (data & ~0x10) | (cpustate->to & 1 ? 0x10 : 0x00); - if (cpustate->mcc & 0x20) /* PC5 = CI input */ - data = (data & ~0x20) | (cpustate->ci & 1 ? 0x20 : 0x00); - if (cpustate->mcc & 0x40) /* PC6 = CO0 output */ - data = (data & ~0x40) | (cpustate->co0 & 1 ? 0x40 : 0x00); - if (cpustate->mcc & 0x80) /* PC7 = CO1 output */ - data = (data & ~0x80) | (cpustate->co1 & 1 ? 0x80 : 0x00); + if (m_mc) // NS20031301 no need to read if the port is set as output + m_pc_in = m_io->read_byte(port); + data = (m_pc_in & m_mc) | (m_pc_out & ~m_mc); + if (m_mcc & 0x01) /* PC0 = TxD output */ + data = (data & ~0x01) | (m_txd & 1 ? 0x01 : 0x00); + if (m_mcc & 0x02) /* PC1 = RxD input */ + data = (data & ~0x02) | (m_rxd & 1 ? 0x02 : 0x00); + if (m_mcc & 0x04) /* PC2 = SCK input/output */ + data = (data & ~0x04) | (m_sck & 1 ? 0x04 : 0x00); + if (m_mcc & 0x08) /* PC3 = TI input */ + data = (data & ~0x08) | (m_ti & 1 ? 0x08 : 0x00); + if (m_mcc & 0x10) /* PC4 = TO output */ + data = (data & ~0x10) | (m_to & 1 ? 0x10 : 0x00); + if (m_mcc & 0x20) /* PC5 = CI input */ + data = (data & ~0x20) | (m_ci & 1 ? 0x20 : 0x00); + if (m_mcc & 0x40) /* PC6 = CO0 output */ + data = (data & ~0x40) | (m_co0 & 1 ? 0x40 : 0x00); + if (m_mcc & 0x80) /* PC7 = CO1 output */ + data = (data & ~0x80) | (m_co1 & 1 ? 0x80 : 0x00); break; case UPD7810_PORTD: - cpustate->pd_in = cpustate->io->read_byte(port); - switch (cpustate->mm & 0x07) + m_pd_in = m_io->read_byte(port); + switch (m_mm & 0x07) { case 0x00: /* PD input mode, PF port mode */ - data = cpustate->pd_in; + data = m_pd_in; break; case 0x01: /* PD output mode, PF port mode */ - data = cpustate->pd_out; + data = m_pd_out; break; default: /* PD extension mode, PF port/extension mode */ data = 0xff; /* what do we see on the port here? */ @@ -729,18 +732,18 @@ static UINT8 RP(upd7810_state *cpustate, offs_t port) } break; case UPD7810_PORTF: - cpustate->pf_in = cpustate->io->read_byte(port); - switch (cpustate->mm & 0x06) + m_pf_in = m_io->read_byte(port); + switch (m_mm & 0x06) { case 0x00: /* PD input/output mode, PF port mode */ - data = (cpustate->pf_in & cpustate->mf) | (cpustate->pf_out & ~cpustate->mf); + data = (m_pf_in & m_mf) | (m_pf_out & ~m_mf); break; case 0x02: /* PD extension mode, PF0-3 extension mode, PF4-7 port mode */ - data = (cpustate->pf_in & cpustate->mf) | (cpustate->pf_out & ~cpustate->mf); + data = (m_pf_in & m_mf) | (m_pf_out & ~m_mf); data |= 0x0f; /* what would we see on the lower bits here? */ break; case 0x04: /* PD extension mode, PF0-5 extension mode, PF6-7 port mode */ - data = (cpustate->pf_in & cpustate->mf) | (cpustate->pf_out & ~cpustate->mf); + data = (m_pf_in & m_mf) | (m_pf_out & ~m_mf); data |= 0x3f; /* what would we see on the lower bits here? */ break; case 0x06: @@ -749,71 +752,71 @@ static UINT8 RP(upd7810_state *cpustate, offs_t port) } break; case UPD7807_PORTT: // NS20031301 partial implementation - data = cpustate->io->read_byte(port); + data = m_io->read_byte(port); break; default: - logerror("uPD7810 internal error: RP(cpustate) called with invalid port number\n"); + logerror("uPD7810 internal error: RP() called with invalid port number\n"); } return data; } -static void WP(upd7810_state *cpustate, offs_t port, UINT8 data) +void upd7810_device::WP(offs_t port, UINT8 data) { switch (port) { case UPD7810_PORTA: - cpustate->pa_out = data; -// data = (data & ~cpustate->ma) | (cpustate->pa_in & cpustate->ma); - data = (data & ~cpustate->ma) | (cpustate->ma); // NS20031401 - cpustate->io->write_byte(port, data); + m_pa_out = data; +// data = (data & ~m_ma) | (m_pa_in & m_ma); + data = (data & ~m_ma) | (m_ma); // NS20031401 + m_io->write_byte(port, data); break; case UPD7810_PORTB: - cpustate->pb_out = data; -// data = (data & ~cpustate->mb) | (cpustate->pb_in & cpustate->mb); - data = (data & ~cpustate->mb) | (cpustate->mb); // NS20031401 - cpustate->io->write_byte(port, data); + m_pb_out = data; +// data = (data & ~m_mb) | (m_pb_in & m_mb); + data = (data & ~m_mb) | (m_mb); // NS20031401 + m_io->write_byte(port, data); break; case UPD7810_PORTC: - cpustate->pc_out = data; -// data = (data & ~cpustate->mc) | (cpustate->pc_in & cpustate->mc); - data = (data & ~cpustate->mc) | (cpustate->mc); // NS20031401 - if (cpustate->mcc & 0x01) /* PC0 = TxD output */ - data = (data & ~0x01) | (cpustate->txd & 1 ? 0x01 : 0x00); - if (cpustate->mcc & 0x02) /* PC1 = RxD input */ - data = (data & ~0x02) | (cpustate->rxd & 1 ? 0x02 : 0x00); - if (cpustate->mcc & 0x04) /* PC2 = SCK input/output */ - data = (data & ~0x04) | (cpustate->sck & 1 ? 0x04 : 0x00); - if (cpustate->mcc & 0x08) /* PC3 = TI input */ - data = (data & ~0x08) | (cpustate->ti & 1 ? 0x08 : 0x00); - if (cpustate->mcc & 0x10) /* PC4 = TO output */ - data = (data & ~0x10) | (cpustate->to & 1 ? 0x10 : 0x00); - if (cpustate->mcc & 0x20) /* PC5 = CI input */ - data = (data & ~0x20) | (cpustate->ci & 1 ? 0x20 : 0x00); - if (cpustate->mcc & 0x40) /* PC6 = CO0 output */ - data = (data & ~0x40) | (cpustate->co0 & 1 ? 0x40 : 0x00); - if (cpustate->mcc & 0x80) /* PC7 = CO1 output */ - data = (data & ~0x80) | (cpustate->co1 & 1 ? 0x80 : 0x00); - cpustate->io->write_byte(port, data); + m_pc_out = data; +// data = (data & ~m_mc) | (m_pc_in & m_mc); + data = (data & ~m_mc) | (m_mc); // NS20031401 + if (m_mcc & 0x01) /* PC0 = TxD output */ + data = (data & ~0x01) | (m_txd & 1 ? 0x01 : 0x00); + if (m_mcc & 0x02) /* PC1 = RxD input */ + data = (data & ~0x02) | (m_rxd & 1 ? 0x02 : 0x00); + if (m_mcc & 0x04) /* PC2 = SCK input/output */ + data = (data & ~0x04) | (m_sck & 1 ? 0x04 : 0x00); + if (m_mcc & 0x08) /* PC3 = TI input */ + data = (data & ~0x08) | (m_ti & 1 ? 0x08 : 0x00); + if (m_mcc & 0x10) /* PC4 = TO output */ + data = (data & ~0x10) | (m_to & 1 ? 0x10 : 0x00); + if (m_mcc & 0x20) /* PC5 = CI input */ + data = (data & ~0x20) | (m_ci & 1 ? 0x20 : 0x00); + if (m_mcc & 0x40) /* PC6 = CO0 output */ + data = (data & ~0x40) | (m_co0 & 1 ? 0x40 : 0x00); + if (m_mcc & 0x80) /* PC7 = CO1 output */ + data = (data & ~0x80) | (m_co1 & 1 ? 0x80 : 0x00); + m_io->write_byte(port, data); break; case UPD7810_PORTD: - cpustate->pd_out = data; - switch (cpustate->mm & 0x07) + m_pd_out = data; + switch (m_mm & 0x07) { case 0x00: /* PD input mode, PF port mode */ - data = cpustate->pd_in; + data = m_pd_in; break; case 0x01: /* PD output mode, PF port mode */ - data = cpustate->pd_out; + data = m_pd_out; break; default: /* PD extension mode, PF port/extension mode */ return; } - cpustate->io->write_byte(port, data); + m_io->write_byte(port, data); break; case UPD7810_PORTF: - cpustate->pf_out = data; - data = (data & ~cpustate->mf) | (cpustate->pf_in & cpustate->mf); - switch (cpustate->mm & 0x06) + m_pf_out = data; + data = (data & ~m_mf) | (m_pf_in & m_mf); + switch (m_mm & 0x06) { case 0x00: /* PD input/output mode, PF port mode */ break; @@ -827,14 +830,14 @@ static void WP(upd7810_state *cpustate, offs_t port, UINT8 data) data |= 0xff; /* what would come out for the lower bits here? */ break; } - cpustate->io->write_byte(port, data); + m_io->write_byte(port, data); break; default: - logerror("uPD7810 internal error: RP(cpustate) called with invalid port number\n"); + logerror("uPD7810 internal error: RP() called with invalid port number\n"); } } -static void upd7810_take_irq(upd7810_state *cpustate) +void upd7810_device::upd7810_take_irq() { UINT16 vector = 0; int irqline = 0; @@ -843,117 +846,136 @@ static void upd7810_take_irq(upd7810_state *cpustate) if (0 == IFF) return; - switch ( cpustate->config.type ) + /* check the interrupts in priority sequence */ + if ((IRR & INTFT0) && 0 == (MKL & 0x02)) { - case TYPE_7801: - /* 1 - SOFTI - vector at 0x0060 */ - /* 2 - INT0 - Masked by MK0 bit */ - if ( IRR & INTF0 && 0 == (MKL & 0x01 ) ) - { - irqline = UPD7810_INTF0; - vector = 0x0004; - IRR &= ~INTF0; - } - /* 3 - INTT - Masked by MKT bit */ - if ( IRR & INTFT0 && 0 == ( MKL & 0x02 ) ) - { - vector = 0x0008; - IRR &= ~INTFT0; - } - /* 4 - INT1 - Masked by MK1 bit */ - if ( IRR & INTF1 && 0 == ( MKL & 0x04 ) ) - { - irqline = UPD7810_INTF1; - vector = 0x0010; - IRR &= ~INTF1; - } - /* 5 - INT2 - Masked by MK2 bit */ - if ( IRR & INTF2 && 0 == ( MKL & 0x08 ) ) - { - irqline = UPD7810_INTF2; - vector = 0x0020; - IRR &= ~INTF2; - } - /* 6 - INTS - Masked by MKS bit */ - if ( IRR & INTFST && 0 == ( MKL & 0x10 ) ) - { - vector = 0x0040; - IRR &= ~INTFST; - } - break; + vector = 0x0008; + if (!((IRR & INTFT1) && 0 == (MKL & 0x04))) + IRR&=~INTFT0; + } + else + if ((IRR & INTFT1) && 0 == (MKL & 0x04)) + { + vector = 0x0008; + IRR&=~INTFT1; + } + else + if ((IRR & INTF1) && 0 == (MKL & 0x08)) + { + irqline = UPD7810_INTF1; + vector = 0x0010; + if (!((IRR & INTF2) && 0 == (MKL & 0x10))) + IRR&=~INTF1; + } + else + if ((IRR & INTF2) && 0 == (MKL & 0x10)) + { + irqline = UPD7810_INTF2; + vector = 0x0010; + IRR&=~INTF2; + } + else + if ((IRR & INTFE0) && 0 == (MKL & 0x20)) + { + vector = 0x0018; + if (!((IRR & INTFE1) && 0 == (MKL & 0x40))) + IRR&=~INTFE0; + } + else + if ((IRR & INTFE1) && 0 == (MKL & 0x40)) + { + vector = 0x0018; + IRR&=~INTFE1; + } + else + if ((IRR & INTFEIN) && 0 == (MKL & 0x80)) + { + vector = 0x0020; + } + else + if ((IRR & INTFAD) && 0 == (MKH & 0x01)) + { + vector = 0x0020; + } + else + if ((IRR & INTFSR) && 0 == (MKH & 0x02)) + { + vector = 0x0028; + IRR&=~INTFSR; + } + else + if ((IRR & INTFST) && 0 == (MKH & 0x04)) + { + vector = 0x0028; + IRR&=~INTFST; + } - default: - /* check the interrupts in priority sequence */ - if ((IRR & INTFT0) && 0 == (MKL & 0x02)) - { - vector = 0x0008; - if (!((IRR & INTFT1) && 0 == (MKL & 0x04))) - IRR&=~INTFT0; - } - else - if ((IRR & INTFT1) && 0 == (MKL & 0x04)) - { - vector = 0x0008; - IRR&=~INTFT1; - } - else - if ((IRR & INTF1) && 0 == (MKL & 0x08)) - { - irqline = UPD7810_INTF1; - vector = 0x0010; - if (!((IRR & INTF2) && 0 == (MKL & 0x10))) - IRR&=~INTF1; - } - else - if ((IRR & INTF2) && 0 == (MKL & 0x10)) - { - irqline = UPD7810_INTF2; - vector = 0x0010; - IRR&=~INTF2; - } - else - if ((IRR & INTFE0) && 0 == (MKL & 0x20)) - { - vector = 0x0018; - if (!((IRR & INTFE1) && 0 == (MKL & 0x40))) - IRR&=~INTFE0; - } - else - if ((IRR & INTFE1) && 0 == (MKL & 0x40)) - { - vector = 0x0018; - IRR&=~INTFE1; - } - else - if ((IRR & INTFEIN) && 0 == (MKL & 0x80)) - { - vector = 0x0020; - } - else - if ((IRR & INTFAD) && 0 == (MKH & 0x01)) - { - vector = 0x0020; - } - else - if ((IRR & INTFSR) && 0 == (MKH & 0x02)) - { - vector = 0x0028; - IRR&=~INTFSR; - } - else - if ((IRR & INTFST) && 0 == (MKH & 0x04)) - { - vector = 0x0028; - IRR&=~INTFST; - } - break; + if (vector) + { + /* acknowledge external IRQ */ + if (irqline) + standard_irq_callback(irqline); + SP--; + WM( SP, PSW ); + SP--; + WM( SP, PCH ); + SP--; + WM( SP, PCL ); + IFF = 0; + PSW &= ~(SK|L0|L1); + PC = vector; + } +} + +void upd7801_device::upd7810_take_irq() +{ + UINT16 vector = 0; + int irqline = 0; + + /* global interrupt disable? */ + if (0 == IFF) + return; + + /* 1 - SOFTI - vector at 0x0060 */ + /* 2 - INT0 - Masked by MK0 bit */ + if ( IRR & INTF0 && 0 == (MKL & 0x01 ) ) + { + irqline = UPD7810_INTF0; + vector = 0x0004; + IRR &= ~INTF0; + } + /* 3 - INTT - Masked by MKT bit */ + if ( IRR & INTFT0 && 0 == ( MKL & 0x02 ) ) + { + vector = 0x0008; + IRR &= ~INTFT0; + } + /* 4 - INT1 - Masked by MK1 bit */ + if ( IRR & INTF1 && 0 == ( MKL & 0x04 ) ) + { + irqline = UPD7810_INTF1; + vector = 0x0010; + IRR &= ~INTF1; + } + /* 5 - INT2 - Masked by MK2 bit */ + if ( IRR & INTF2 && 0 == ( MKL & 0x08 ) ) + { + irqline = UPD7810_INTF2; + vector = 0x0020; + IRR &= ~INTF2; + } + /* 6 - INTS - Masked by MKS bit */ + if ( IRR & INTFST && 0 == ( MKL & 0x10 ) ) + { + vector = 0x0040; + IRR &= ~INTFST; } if (vector) { /* acknowledge external IRQ */ if (irqline) - (*cpustate->irq_callback)(cpustate->device, irqline); + standard_irq_callback(irqline); SP--; WM( SP, PSW ); SP--; @@ -966,7 +988,7 @@ static void upd7810_take_irq(upd7810_state *cpustate) } } -static void upd7810_write_EOM(upd7810_state *cpustate) +void upd7810_device::upd7810_write_EOM() { if (EOM & 0x01) /* output LV0 content ? */ { @@ -1000,34 +1022,33 @@ static void upd7810_write_EOM(upd7810_state *cpustate) } } -static void upd7810_write_TXB(upd7810_state *cpustate) +void upd7810_device::upd7810_write_TXB() { - cpustate->txbuf = 1; + m_txbuf = 1; } #define PAR7(n) ((((n)>>6)^((n)>>5)^((n)>>4)^((n)>>3)^((n)>>2)^((n)>>1)^((n)))&1) #define PAR8(n) ((((n)>>7)^((n)>>6)^((n)>>5)^((n)>>4)^((n)>>3)^((n)>>2)^((n)>>1)^((n)))&1) -static void upd7810_sio_output(upd7810_state *cpustate) +void upd7810_device::upd7810_sio_output() { /* shift out more bits? */ - if (cpustate->txcnt > 0) + if (m_txcnt > 0) { - TXD = cpustate->txs & 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TXD,TXD); - cpustate->txs >>= 1; - cpustate->txcnt--; - if (0 == cpustate->txcnt) + TXD = m_txs & 1; + m_txd_func(TXD); + m_txs >>= 1; + m_txcnt--; + if (0 == m_txcnt) IRR |= INTFST; /* serial transfer completed */ } else if (SMH & 0x04) /* send enable ? */ { /* nothing written into the transmitter buffer ? */ - if (0 == cpustate->txbuf) + if (0 == m_txbuf) return; - cpustate->txbuf = 0; + m_txbuf = 0; if (SML & 0x03) /* asynchronous mode ? */ { @@ -1036,88 +1057,87 @@ static void upd7810_sio_output(upd7810_state *cpustate) case 0x48: /* 7bits, no parity, 1 stop bit */ case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ /* insert start bit in bit0, stop bit int bit8 */ - cpustate->txs = (TXB << 1) | (1 << 8); - cpustate->txcnt = 9; + m_txs = (TXB << 1) | (1 << 8); + m_txcnt = 9; break; case 0x4c: /* 8bits, no parity, 1 stop bit */ case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ /* insert start bit in bit0, stop bit int bit9 */ - cpustate->txs = (TXB << 1) | (1 << 9); - cpustate->txcnt = 10; + m_txs = (TXB << 1) | (1 << 9); + m_txcnt = 10; break; case 0x58: /* 7bits, odd parity, 1 stop bit */ /* insert start bit in bit0, parity in bit 8, stop bit in bit9 */ - cpustate->txs = (TXB << 1) | (PAR7(TXB) << 8) | (1 << 9); - cpustate->txcnt = 10; + m_txs = (TXB << 1) | (PAR7(TXB) << 8) | (1 << 9); + m_txcnt = 10; break; case 0x5c: /* 8bits, odd parity, 1 stop bit */ /* insert start bit in bit0, parity in bit 9, stop bit int bit10 */ - cpustate->txs = (TXB << 1) | (PAR8(TXB) << 9) | (1 << 10); - cpustate->txcnt = 11; + m_txs = (TXB << 1) | (PAR8(TXB) << 9) | (1 << 10); + m_txcnt = 11; break; case 0x78: /* 7bits, even parity, 1 stop bit */ /* insert start bit in bit0, parity in bit 8, stop bit in bit9 */ - cpustate->txs = (TXB << 1) | ((PAR7(TXB) ^ 1) << 8) | (1 << 9); - cpustate->txcnt = 10; + m_txs = (TXB << 1) | ((PAR7(TXB) ^ 1) << 8) | (1 << 9); + m_txcnt = 10; break; case 0x7c: /* 8bits, even parity, 1 stop bit */ /* insert start bit in bit0, parity in bit 9, stop bit int bit10 */ - cpustate->txs = (TXB << 1) | ((PAR8(TXB) ^ 1) << 9) | (1 << 10); - cpustate->txcnt = 11; + m_txs = (TXB << 1) | ((PAR8(TXB) ^ 1) << 9) | (1 << 10); + m_txcnt = 11; break; case 0xc8: /* 7bits, no parity, 2 stop bits */ case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ /* insert start bit in bit0, stop bits int bit8+9 */ - cpustate->txs = (TXB << 1) | (3 << 8); - cpustate->txcnt = 10; + m_txs = (TXB << 1) | (3 << 8); + m_txcnt = 10; break; case 0xcc: /* 8bits, no parity, 2 stop bits */ case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ /* insert start bit in bit0, stop bits in bits9+10 */ - cpustate->txs = (TXB << 1) | (3 << 9); - cpustate->txcnt = 11; + m_txs = (TXB << 1) | (3 << 9); + m_txcnt = 11; break; case 0xd8: /* 7bits, odd parity, 2 stop bits */ /* insert start bit in bit0, parity in bit 8, stop bits in bits9+10 */ - cpustate->txs = (TXB << 1) | (PAR7(TXB) << 8) | (3 << 9); - cpustate->txcnt = 11; + m_txs = (TXB << 1) | (PAR7(TXB) << 8) | (3 << 9); + m_txcnt = 11; break; case 0xdc: /* 8bits, odd parity, 2 stop bits */ /* insert start bit in bit0, parity in bit 9, stop bits int bit10+11 */ - cpustate->txs = (TXB << 1) | (PAR8(TXB) << 9) | (3 << 10); - cpustate->txcnt = 12; + m_txs = (TXB << 1) | (PAR8(TXB) << 9) | (3 << 10); + m_txcnt = 12; break; case 0xf8: /* 7bits, even parity, 2 stop bits */ /* insert start bit in bit0, parity in bit 8, stop bits in bit9+10 */ - cpustate->txs = (TXB << 1) | ((PAR7(TXB) ^ 1) << 8) | (3 << 9); - cpustate->txcnt = 11; + m_txs = (TXB << 1) | ((PAR7(TXB) ^ 1) << 8) | (3 << 9); + m_txcnt = 11; break; case 0xfc: /* 8bits, even parity, 2 stop bits */ /* insert start bit in bit0, parity in bit 9, stop bits int bits10+10 */ - cpustate->txs = (TXB << 1) | ((PAR8(TXB) ^ 1) << 9) | (1 << 10); - cpustate->txcnt = 12; + m_txs = (TXB << 1) | ((PAR8(TXB) ^ 1) << 9) | (1 << 10); + m_txcnt = 12; break; } } else { /* synchronous mode */ - cpustate->txs = TXB; - cpustate->txcnt = 8; + m_txs = TXB; + m_txcnt = 8; } } } -static void upd7810_sio_input(upd7810_state *cpustate) +void upd7810_device::upd7810_sio_input() { /* sample next bit? */ - if (cpustate->rxcnt > 0) + if (m_rxcnt > 0) { - if (cpustate->config.io_callback) - RXD = (*cpustate->config.io_callback)(cpustate->device,UPD7810_RXD,RXD); - cpustate->rxs = (cpustate->rxs >> 1) | ((UINT16)RXD << 15); - cpustate->rxcnt--; - if (0 == cpustate->rxcnt) + RXD = m_rxd_func(); + m_rxs = (m_rxs >> 1) | ((UINT16)RXD << 15); + m_rxcnt--; + if (0 == m_rxcnt) { /* reset the TSK bit */ SMH &= ~0x40; @@ -1130,107 +1150,107 @@ static void upd7810_sio_input(upd7810_state *cpustate) { case 0x48: /* 7bits, no parity, 1 stop bit */ case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ - cpustate->rxs >>= 16 - 9; - RXB = (cpustate->rxs >> 1) & 0x7f; - if ((1 << 8) != (cpustate->rxs & (1 | (1 << 8)))) + m_rxs >>= 16 - 9; + RXB = (m_rxs >> 1) & 0x7f; + if ((1 << 8) != (m_rxs & (1 | (1 << 8)))) IRR |= INTER; /* framing error */ break; case 0x4c: /* 8bits, no parity, 1 stop bit */ case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ - cpustate->rxs >>= 16 - 10; - RXB = (cpustate->rxs >> 1) & 0xff; - if ((1 << 9) != (cpustate->rxs & (1 | (1 << 9)))) + m_rxs >>= 16 - 10; + RXB = (m_rxs >> 1) & 0xff; + if ((1 << 9) != (m_rxs & (1 | (1 << 9)))) IRR |= INTER; /* framing error */ break; case 0x58: /* 7bits, odd parity, 1 stop bit */ - cpustate->rxs >>= 16 - 10; - RXB = (cpustate->rxs >> 1) & 0x7f; - if ((1 << 9) != (cpustate->rxs & (1 | (1 << 9)))) + m_rxs >>= 16 - 10; + RXB = (m_rxs >> 1) & 0x7f; + if ((1 << 9) != (m_rxs & (1 | (1 << 9)))) IRR |= INTER; /* framing error */ - if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) + if (PAR7(RXB) != ((m_rxs >> 8) & 1)) IRR |= INTER; /* parity error */ break; case 0x5c: /* 8bits, odd parity, 1 stop bit */ - cpustate->rxs >>= 16 - 11; - RXB = (cpustate->rxs >> 1) & 0xff; - if ((1 << 10) != (cpustate->rxs & (1 | (1 << 10)))) + m_rxs >>= 16 - 11; + RXB = (m_rxs >> 1) & 0xff; + if ((1 << 10) != (m_rxs & (1 | (1 << 10)))) IRR |= INTER; /* framing error */ - if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) + if (PAR8(RXB) != ((m_rxs >> 9) & 1)) IRR |= INTER; /* parity error */ break; case 0x78: /* 7bits, even parity, 1 stop bit */ - cpustate->rxs >>= 16 - 10; - RXB = (cpustate->rxs >> 1) & 0x7f; - if ((1 << 9) != (cpustate->rxs & (1 | (1 << 9)))) + m_rxs >>= 16 - 10; + RXB = (m_rxs >> 1) & 0x7f; + if ((1 << 9) != (m_rxs & (1 | (1 << 9)))) IRR |= INTER; /* framing error */ - if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) + if (PAR7(RXB) != ((m_rxs >> 8) & 1)) IRR |= INTER; /* parity error */ break; case 0x7c: /* 8bits, even parity, 1 stop bit */ - cpustate->rxs >>= 16 - 11; - RXB = (cpustate->rxs >> 1) & 0xff; - if ((1 << 10) != (cpustate->rxs & (1 | (1 << 10)))) + m_rxs >>= 16 - 11; + RXB = (m_rxs >> 1) & 0xff; + if ((1 << 10) != (m_rxs & (1 | (1 << 10)))) IRR |= INTER; /* framing error */ - if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) + if (PAR8(RXB) != ((m_rxs >> 9) & 1)) IRR |= INTER; /* parity error */ break; case 0xc8: /* 7bits, no parity, 2 stop bits */ case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ - cpustate->rxs >>= 16 - 10; - RXB = (cpustate->rxs >> 1) & 0x7f; - if ((3 << 9) != (cpustate->rxs & (1 | (3 << 9)))) + m_rxs >>= 16 - 10; + RXB = (m_rxs >> 1) & 0x7f; + if ((3 << 9) != (m_rxs & (1 | (3 << 9)))) IRR |= INTER; /* framing error */ - if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) + if (PAR7(RXB) != ((m_rxs >> 8) & 1)) IRR |= INTER; /* parity error */ break; case 0xcc: /* 8bits, no parity, 2 stop bits */ case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ - cpustate->rxs >>= 16 - 11; - RXB = (cpustate->rxs >> 1) & 0xff; - if ((3 << 10) != (cpustate->rxs & (1 | (3 << 10)))) + m_rxs >>= 16 - 11; + RXB = (m_rxs >> 1) & 0xff; + if ((3 << 10) != (m_rxs & (1 | (3 << 10)))) IRR |= INTER; /* framing error */ - if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) + if (PAR8(RXB) != ((m_rxs >> 9) & 1)) IRR |= INTER; /* parity error */ break; case 0xd8: /* 7bits, odd parity, 2 stop bits */ - cpustate->rxs >>= 16 - 11; - RXB = (cpustate->rxs >> 1) & 0x7f; - if ((3 << 10) != (cpustate->rxs & (1 | (3 << 10)))) + m_rxs >>= 16 - 11; + RXB = (m_rxs >> 1) & 0x7f; + if ((3 << 10) != (m_rxs & (1 | (3 << 10)))) IRR |= INTER; /* framing error */ - if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) + if (PAR7(RXB) != ((m_rxs >> 8) & 1)) IRR |= INTER; /* parity error */ break; case 0xdc: /* 8bits, odd parity, 2 stop bits */ - cpustate->rxs >>= 16 - 12; - RXB = (cpustate->rxs >> 1) & 0xff; - if ((3 << 11) != (cpustate->rxs & (1 | (3 << 11)))) + m_rxs >>= 16 - 12; + RXB = (m_rxs >> 1) & 0xff; + if ((3 << 11) != (m_rxs & (1 | (3 << 11)))) IRR |= INTER; /* framing error */ - if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) + if (PAR8(RXB) != ((m_rxs >> 9) & 1)) IRR |= INTER; /* parity error */ break; case 0xf8: /* 7bits, even parity, 2 stop bits */ - cpustate->rxs >>= 16 - 11; - RXB = (cpustate->rxs >> 1) & 0x7f; - if ((3 << 10) != (cpustate->rxs & (1 | (3 << 10)))) + m_rxs >>= 16 - 11; + RXB = (m_rxs >> 1) & 0x7f; + if ((3 << 10) != (m_rxs & (1 | (3 << 10)))) IRR |= INTER; /* framing error */ - if (PAR7(RXB) != ((cpustate->rxs >> 8) & 1)) + if (PAR7(RXB) != ((m_rxs >> 8) & 1)) IRR |= INTER; /* parity error */ break; case 0xfc: /* 8bits, even parity, 2 stop bits */ - cpustate->rxs >>= 16 - 12; - RXB = (cpustate->rxs >> 1) & 0xff; - if ((3 << 11) != (cpustate->rxs & (1 | (3 << 11)))) + m_rxs >>= 16 - 12; + RXB = (m_rxs >> 1) & 0xff; + if ((3 << 11) != (m_rxs & (1 | (3 << 11)))) IRR |= INTER; /* framing error */ - if (PAR8(RXB) != ((cpustate->rxs >> 9) & 1)) + if (PAR8(RXB) != ((m_rxs >> 9) & 1)) IRR |= INTER; /* parity error */ break; } } else { - cpustate->rxs >>= 16 - 8; - RXB = cpustate->rxs; -// cpustate->rxcnt = 8; + m_rxs >>= 16 - 8; + RXB = m_rxs; +// m_rxcnt = 8; } } } @@ -1243,43 +1263,43 @@ static void upd7810_sio_input(upd7810_state *cpustate) { case 0x48: /* 7bits, no parity, 1 stop bit */ case 0x68: /* 7bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ - cpustate->rxcnt = 9; + m_rxcnt = 9; break; case 0x4c: /* 8bits, no parity, 1 stop bit */ case 0x6c: /* 8bits, no parity, 1 stop bit (parity select = 1 but parity is off) */ - cpustate->rxcnt = 10; + m_rxcnt = 10; break; case 0x58: /* 7bits, odd parity, 1 stop bit */ - cpustate->rxcnt = 10; + m_rxcnt = 10; break; case 0x5c: /* 8bits, odd parity, 1 stop bit */ - cpustate->rxcnt = 11; + m_rxcnt = 11; break; case 0x78: /* 7bits, even parity, 1 stop bit */ - cpustate->rxcnt = 10; + m_rxcnt = 10; break; case 0x7c: /* 8bits, even parity, 1 stop bit */ - cpustate->rxcnt = 11; + m_rxcnt = 11; break; case 0xc8: /* 7bits, no parity, 2 stop bits */ case 0xe8: /* 7bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ - cpustate->rxcnt = 10; + m_rxcnt = 10; break; case 0xcc: /* 8bits, no parity, 2 stop bits */ case 0xec: /* 8bits, no parity, 2 stop bits (parity select = 1 but parity is off) */ - cpustate->rxcnt = 11; + m_rxcnt = 11; break; case 0xd8: /* 7bits, odd parity, 2 stop bits */ - cpustate->rxcnt = 11; + m_rxcnt = 11; break; case 0xdc: /* 8bits, odd parity, 2 stop bits */ - cpustate->rxcnt = 12; + m_rxcnt = 12; break; case 0xf8: /* 7bits, even parity, 2 stop bits */ - cpustate->rxcnt = 11; + m_rxcnt = 11; break; case 0xfc: /* 8bits, even parity, 2 stop bits */ - cpustate->rxcnt = 12; + m_rxcnt = 12; break; } } @@ -1287,12 +1307,12 @@ static void upd7810_sio_input(upd7810_state *cpustate) /* TSK bit set ? */ if (SMH & 0x40) { - cpustate->rxcnt = 8; + m_rxcnt = 8; } } } -static void upd7810_timers(upd7810_state *cpustate, int cycles) +void upd7810_device::handle_timers(int cycles) { /**** TIMER 0 ****/ if (TMM & 0x10) /* timer 0 upcounter reset ? */ @@ -1315,8 +1335,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) if (0x00 == (TMM & 0x03)) { TO ^= 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); } /* timer 1 chained with timer 0 ? */ if ((TMM & 0xe0) == 0x60) @@ -1330,8 +1349,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) if (0x01 == (TMM & 0x03)) { TO ^= 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); } } } @@ -1352,8 +1370,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) if (0x00 == (TMM & 0x03)) { TO ^= 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); } /* timer 1 chained with timer 0 ? */ if ((TMM & 0xe0) == 0x60) @@ -1367,8 +1384,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) if (0x01 == (TMM & 0x03)) { TO ^= 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); } } } @@ -1403,8 +1419,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) if (0x01 == (TMM & 0x03)) { TO ^= 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); } } } @@ -1423,8 +1438,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) if (0x01 == (TMM & 0x03)) { TO ^= 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); } } } @@ -1444,8 +1458,7 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) while (OVCF >= 3) { TO ^= 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); OVCF -= 3; } } @@ -1604,9 +1617,9 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) { OVCS -= 384; if (0 == (EDGES ^= 1)) - upd7810_sio_input(cpustate); + upd7810_sio_input(); else - upd7810_sio_output(cpustate); + upd7810_sio_output(); } break; case 0x02: /* internal clock divided by 24 */ @@ -1615,160 +1628,325 @@ static void upd7810_timers(upd7810_state *cpustate, int cycles) { OVCS -= 24; if (0 == (EDGES ^= 1)) - upd7810_sio_input(cpustate); + upd7810_sio_input(); else - upd7810_sio_output(cpustate); + upd7810_sio_output(); } break; } } -static void upd7801_timers(upd7810_state *cpustate, int cycles) +void upd7801_device::handle_timers(int cycles) { - if ( cpustate->ovc0 ) + if ( m_ovc0 ) { - cpustate->ovc0 -= cycles; + m_ovc0 -= cycles; /* Check if timer expired */ - if ( cpustate->ovc0 <= 0 ) + if ( m_ovc0 <= 0 ) { IRR |= INTFT0; /* Reset the timer flip/fliop */ TO = 0; - if ( cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); /* Reload the timer */ - cpustate->ovc0 = 16 * ( TM0 + ( ( TM1 & 0x0f ) << 8 ) ); + m_ovc0 = 16 * ( TM0 + ( ( TM1 & 0x0f ) << 8 ) ); } } } -static void upd78c05_timers(upd7810_state *cpustate, int cycles) +void upd78c05_device::handle_timers(int cycles) { - if ( cpustate->ovc0 ) { - cpustate->ovc0 -= cycles; + if ( m_ovc0 ) { + m_ovc0 -= cycles; - if ( cpustate->ovc0 <= 0 ) { + if ( m_ovc0 <= 0 ) { IRR |= INTFT0; if (0x00 == (TMM & 0x03)) { TO ^= 1; - if (cpustate->config.io_callback) - (*cpustate->config.io_callback)(cpustate->device,UPD7810_TO,TO); + m_to_func(TO); } - while ( cpustate->ovc0 <= 0 ) { - cpustate->ovc0 += ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0; + while ( m_ovc0 <= 0 ) { + m_ovc0 += ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0; } } } } -static CPU_INIT( upd7810 ) +void upd7810_device::base_device_start() +{ + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + m_io = &space(AS_IO); + + m_to_func.resolve_safe(); + m_txd_func.resolve_safe(); + m_rxd_func.resolve_safe(0); + + save_item(NAME(m_ppc.w.l)); + save_item(NAME(m_pc.w.l)); + save_item(NAME(m_sp.w.l)); + save_item(NAME(m_psw)); + save_item(NAME(m_op)); + save_item(NAME(m_op2)); + save_item(NAME(m_iff)); + save_item(NAME(m_ea.w.l)); + save_item(NAME(m_va.w.l)); + save_item(NAME(m_bc.w.l)); + save_item(NAME(m_de.w.l)); + save_item(NAME(m_hl.w.l)); + save_item(NAME(m_ea2.w.l)); + save_item(NAME(m_va2.w.l)); + save_item(NAME(m_bc2.w.l)); + save_item(NAME(m_de2.w.l)); + save_item(NAME(m_hl2.w.l)); + save_item(NAME(m_cnt.d)); + save_item(NAME(m_tm.d)); + save_item(NAME(m_ecnt.d)); + save_item(NAME(m_etm.d)); + save_item(NAME(m_ma)); + save_item(NAME(m_mb)); + save_item(NAME(m_mcc)); + save_item(NAME(m_mc)); + save_item(NAME(m_mm)); + save_item(NAME(m_mf)); + save_item(NAME(m_tmm)); + save_item(NAME(m_etmm)); + save_item(NAME(m_eom)); + save_item(NAME(m_sml)); + save_item(NAME(m_smh)); + save_item(NAME(m_anm)); + save_item(NAME(m_mkl)); + save_item(NAME(m_mkh)); + save_item(NAME(m_zcm)); + save_item(NAME(m_pa_out)); + save_item(NAME(m_pb_out)); + save_item(NAME(m_pc_out)); + save_item(NAME(m_pd_out)); + save_item(NAME(m_pf_out)); + save_item(NAME(m_cr0)); + save_item(NAME(m_cr1)); + save_item(NAME(m_cr2)); + save_item(NAME(m_cr3)); + save_item(NAME(m_txb)); + save_item(NAME(m_rxb)); + save_item(NAME(m_txd)); + save_item(NAME(m_rxd)); + save_item(NAME(m_sck)); + save_item(NAME(m_ti)); + save_item(NAME(m_to)); + save_item(NAME(m_ci)); + save_item(NAME(m_co0)); + save_item(NAME(m_co1)); + save_item(NAME(m_irr)); + save_item(NAME(m_itf)); + save_item(NAME(m_ovc0)); + save_item(NAME(m_ovc1)); + save_item(NAME(m_ovcf)); + save_item(NAME(m_ovcs)); + save_item(NAME(m_edges)); + save_item(NAME(m_int1)); + save_item(NAME(m_int2)); + + m_icountptr = &m_icount; +} + +void upd7810_device::device_start() +{ + base_device_start(); + + state_add( UPD7810_PC, "PC", m_pc.w.l).formatstr("%04X"); + state_add( UPD7810_SP, "SP", m_sp.w.l).formatstr("%04X"); + state_add( UPD7810_PSW, "PSW", m_psw).formatstr("%02X"); + state_add( UPD7810_A, "A", m_va.b.l).formatstr("%02X"); + state_add( UPD7810_V, "V", m_va.b.h).formatstr("%02X"); + state_add( UPD7810_EA, "EA", m_ea.w.l).formatstr("%04X"); + state_add( UPD7810_BC, "BC", m_bc.w.l).formatstr("%04X"); + state_add( UPD7810_DE, "DE", m_de.w.l).formatstr("%04X"); + state_add( UPD7810_HL, "HL", m_hl.w.l).formatstr("%04X"); + state_add( UPD7810_A2, "A'", m_va2.b.l).formatstr("%02X"); + state_add( UPD7810_V2, "V'", m_va2.b.h).formatstr("%02X"); + state_add( UPD7810_EA2, "EA'", m_ea2.w.l).formatstr("%04X"); + state_add( UPD7810_BC2, "BC'", m_bc2.w.l).formatstr("%04X"); + state_add( UPD7810_DE2, "DE'", m_de2.w.l).formatstr("%04X"); + state_add( UPD7810_HL2, "HL'", m_hl2.w.l).formatstr("%04X"); + state_add( UPD7810_CNT0, "CNT0", m_cnt.b.l).formatstr("%02X"); + state_add( UPD7810_CNT1, "CNT1", m_cnt.b.h).formatstr("%02X"); + state_add( UPD7810_TM0, "TM0", m_tm.b.l).formatstr("%02X"); + state_add( UPD7810_TM1, "TM1", m_tm.b.h).formatstr("%02X"); + state_add( UPD7810_ECNT, "ECNT", m_ecnt.w.l).formatstr("%04X"); + state_add( UPD7810_ECPT, "ECPT", m_ecnt.w.h).formatstr("%04X"); + state_add( UPD7810_ETM0, "ETM0", m_etm.w.l).formatstr("%04X"); + state_add( UPD7810_ETM1, "ETM1", m_etm.w.h).formatstr("%04X"); + state_add( UPD7810_MA, "MA", m_ma).formatstr("%02X"); + state_add( UPD7810_MB, "MB", m_mb).formatstr("%02X"); + state_add( UPD7810_MCC, "MCC", m_mcc).formatstr("%02X"); + state_add( UPD7810_MC, "MC", m_mc).formatstr("%02X"); + state_add( UPD7810_MM, "MM", m_mm).formatstr("%02X"); + state_add( UPD7810_MF, "MF", m_mf).formatstr("%02X"); + state_add( UPD7810_TMM, "TMM", m_tmm).formatstr("%02X"); + state_add( UPD7810_ETMM, "ETMM", m_etmm).formatstr("%02X"); + state_add( UPD7810_EOM, "EOM", m_eom).formatstr("%02X"); + state_add( UPD7810_SML, "SML", m_sml).formatstr("%02X"); + state_add( UPD7810_SMH, "SMH", m_smh).formatstr("%02X"); + state_add( UPD7810_ANM, "ANM", m_anm).formatstr("%02X"); + state_add( UPD7810_MKL, "MKL", m_mkl).formatstr("%02X"); + state_add( UPD7810_MKH, "MKH", m_mkh).formatstr("%02X"); + state_add( UPD7810_ZCM, "ZCM", m_zcm).formatstr("%02X"); + state_add( UPD7810_CR0, "CR0", m_cr0).formatstr("%02X"); + state_add( UPD7810_CR1, "CR1", m_cr1).formatstr("%02X"); + state_add( UPD7810_CR2, "CR2", m_cr2).formatstr("%02X"); + state_add( UPD7810_CR3, "CR3", m_cr3).formatstr("%02X"); + state_add( UPD7810_RXB, "RXB", m_rxb).formatstr("%02X"); + state_add( UPD7810_TXB, "TXB", m_txb).formatstr("%02X"); + state_add( UPD7810_TXD, "TXD", m_txd).formatstr("%3u"); + state_add( UPD7810_RXD, "RXD", m_rxd).formatstr("%3u"); + state_add( UPD7810_SCK, "SCK", m_sck).formatstr("%3u"); + state_add( UPD7810_TI, "TI", m_ti).formatstr("%3u"); + state_add( UPD7810_TO, "TO", m_to).formatstr("%3u"); + state_add( UPD7810_CI, "CI", m_ci).formatstr("%3u"); + state_add( UPD7810_CO0, "CO0", m_co0).mask(0x01).formatstr("%1X"); + state_add( UPD7810_CO1, "CO1", m_co1).mask(0x01).formatstr("%1X"); + + state_add( STATE_GENPC, "GENPC", m_pc.w.l ).formatstr("%04X").noshow(); + state_add( STATE_GENPCBASE, "GENPCBASE", m_ppc.w.l ).formatstr("%04X").noshow(); + state_add( STATE_GENSP, "GENSP", m_sp.w.l ).formatstr("%04X").noshow(); + state_add( STATE_GENFLAGS, "GENFLAGS", m_psw ).formatstr("%17s").noshow(); +} + +void upd78c05_device::device_start() +{ + base_device_start(); + + state_add( UPD7810_PC, "PC", m_pc.w.l).formatstr("%04X"); + state_add( UPD7810_SP, "SP", m_sp.w.l).formatstr("%04X"); + state_add( UPD7810_PSW, "PSW", m_psw).formatstr("%02X"); + state_add( UPD7810_A, "A", m_va.b.l).formatstr("%02X"); + state_add( UPD7810_V, "V", m_va.b.h).formatstr("%02X"); + state_add( UPD7810_EA, "EA", m_ea.w.l).formatstr("%04X"); + state_add( UPD7810_BC, "BC", m_bc.w.l).formatstr("%04X"); + state_add( UPD7810_DE, "DE", m_de.w.l).formatstr("%04X"); + state_add( UPD7810_HL, "HL", m_hl.w.l).formatstr("%04X"); + state_add( UPD7810_CNT0, "CNT0", m_cnt.b.l).formatstr("%02X"); + state_add( UPD7810_CNT1, "CNT1", m_cnt.b.h).formatstr("%02X"); + state_add( UPD7810_TM0, "TM0", m_tm.b.l).formatstr("%02X"); + state_add( UPD7810_TM1, "TM1", m_tm.b.h).formatstr("%02X"); + state_add( UPD7810_ECNT, "ECNT", m_ecnt.w.l).formatstr("%04X"); + state_add( UPD7810_ECPT, "ECPT", m_ecnt.w.h).formatstr("%04X"); + state_add( UPD7810_ETM0, "ETM0", m_etm.w.l).formatstr("%04X"); + state_add( UPD7810_ETM1, "ETM1", m_etm.w.h).formatstr("%04X"); + state_add( UPD7810_MB, "MB", m_mb).formatstr("%02X"); + state_add( UPD7810_TMM, "TMM", m_tmm).formatstr("%02X"); + state_add( UPD7810_MKL, "MKL", m_mkl).formatstr("%02X"); + + state_add( STATE_GENPC, "GENPC", m_pc.w.l ).formatstr("%04X").noshow(); + state_add( STATE_GENPCBASE, "GENPCBASE", m_ppc.w.l ).formatstr("%04X").noshow(); + state_add( STATE_GENSP, "GENSP", m_sp.w.l ).formatstr("%04X").noshow(); + state_add( STATE_GENFLAGS, "GENFLAGS", m_psw ).formatstr("%17s").noshow(); + +} + +void upd7810_device::state_string_export(const device_state_entry &entry, astring &string) { - upd7810_state *cpustate = get_safe_token(device); - - cpustate->config = *(const UPD7810_CONFIG*) device->static_config(); - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->program->direct(); - cpustate->io = &device->space(AS_IO); - - device->save_item(NAME(cpustate->ppc.w.l)); - device->save_item(NAME(cpustate->pc.w.l)); - device->save_item(NAME(cpustate->sp.w.l)); - device->save_item(NAME(cpustate->psw)); - device->save_item(NAME(cpustate->op)); - device->save_item(NAME(cpustate->op2)); - device->save_item(NAME(cpustate->iff)); - device->save_item(NAME(cpustate->ea.w.l)); - device->save_item(NAME(cpustate->va.w.l)); - device->save_item(NAME(cpustate->bc.w.l)); - device->save_item(NAME(cpustate->de.w.l)); - device->save_item(NAME(cpustate->hl.w.l)); - device->save_item(NAME(cpustate->ea2.w.l)); - device->save_item(NAME(cpustate->va2.w.l)); - device->save_item(NAME(cpustate->bc2.w.l)); - device->save_item(NAME(cpustate->de2.w.l)); - device->save_item(NAME(cpustate->hl2.w.l)); - device->save_item(NAME(cpustate->cnt.d)); - device->save_item(NAME(cpustate->tm.d)); - device->save_item(NAME(cpustate->ecnt.d)); - device->save_item(NAME(cpustate->etm.d)); - device->save_item(NAME(cpustate->ma)); - device->save_item(NAME(cpustate->mb)); - device->save_item(NAME(cpustate->mcc)); - device->save_item(NAME(cpustate->mc)); - device->save_item(NAME(cpustate->mm)); - device->save_item(NAME(cpustate->mf)); - device->save_item(NAME(cpustate->tmm)); - device->save_item(NAME(cpustate->etmm)); - device->save_item(NAME(cpustate->eom)); - device->save_item(NAME(cpustate->sml)); - device->save_item(NAME(cpustate->smh)); - device->save_item(NAME(cpustate->anm)); - device->save_item(NAME(cpustate->mkl)); - device->save_item(NAME(cpustate->mkh)); - device->save_item(NAME(cpustate->zcm)); - device->save_item(NAME(cpustate->pa_out)); - device->save_item(NAME(cpustate->pb_out)); - device->save_item(NAME(cpustate->pc_out)); - device->save_item(NAME(cpustate->pd_out)); - device->save_item(NAME(cpustate->pf_out)); - device->save_item(NAME(cpustate->cr0)); - device->save_item(NAME(cpustate->cr1)); - device->save_item(NAME(cpustate->cr2)); - device->save_item(NAME(cpustate->cr3)); - device->save_item(NAME(cpustate->txb)); - device->save_item(NAME(cpustate->rxb)); - device->save_item(NAME(cpustate->txd)); - device->save_item(NAME(cpustate->rxd)); - device->save_item(NAME(cpustate->sck)); - device->save_item(NAME(cpustate->ti)); - device->save_item(NAME(cpustate->to)); - device->save_item(NAME(cpustate->ci)); - device->save_item(NAME(cpustate->co0)); - device->save_item(NAME(cpustate->co1)); - device->save_item(NAME(cpustate->irr)); - device->save_item(NAME(cpustate->itf)); - device->save_item(NAME(cpustate->ovc0)); - device->save_item(NAME(cpustate->ovc1)); - device->save_item(NAME(cpustate->ovcf)); - device->save_item(NAME(cpustate->ovcs)); - device->save_item(NAME(cpustate->edges)); - device->save_item(NAME(cpustate->int1)); - device->save_item(NAME(cpustate->int2)); + switch (entry.index()) + { + case STATE_GENFLAGS: + string.printf("%s:%s:%s:%s:%s:%s", + m_psw & 0x40 ? "ZF":"--", + m_psw & 0x20 ? "SK":"--", + m_psw & 0x10 ? "HC":"--", + m_psw & 0x08 ? "L1":"--", + m_psw & 0x04 ? "L0":"--", + m_psw & 0x01 ? "CY":"--"); + break; + } } #include "7810tbl.c" #include "7810ops.c" -static CPU_RESET( upd7810 ) +void upd7810_device::device_reset() { - upd7810_state *cpustate = get_safe_token(device); - UPD7810_CONFIG save_config; - device_irq_acknowledge_callback save_irqcallback; - - save_config = cpustate->config; - save_irqcallback = cpustate->irq_callback; - memset(cpustate, 0, sizeof(*cpustate)); - cpustate->config = save_config; - cpustate->irq_callback = save_irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->program->direct(); - cpustate->io = &device->space(AS_IO); - - cpustate->opXX = opXX_7810; - cpustate->op48 = op48; - cpustate->op4C = op4C; - cpustate->op4D = op4D; - cpustate->op60 = op60; - cpustate->op64 = op64; - cpustate->op70 = op70; - cpustate->op74 = op74; + m_ppc.d = 0; + m_pc.d = 0; + m_sp.d = 0; + m_op = 0; + m_op2 = 0; + m_iff = 0; + m_psw = 0; + m_ea.d = 0; + m_va.d = 0; + m_bc.d = 0; + m_de.d = 0; + m_hl.d = 0; + m_ea2.d = 0; + m_va2.d = 0; + m_bc2.d = 0; + m_de2.d = 0; + m_hl2.d = 0; + m_cnt.d = 0; + m_tm.d = 0; + m_ecnt.d = 0; + m_etm.d = 0; + m_ma = 0; + m_mb = 0; + m_mcc = 0; + m_mc = 0; + m_mm = 0; + m_mf = 0; + m_tmm = 0; + m_etmm = 0; + m_eom = 0; + m_sml = 0; + m_smh = 0; + m_anm = 0; + m_mkl = 0; + m_mkh = 0; + m_zcm = 0; + m_pa_in = 0; + m_pb_in = 0; + m_pc_in = 0; + m_pd_in = 0; + m_pf_in = 0; + m_pa_out = 0; + m_pb_out = 0; + m_pc_out = 0; + m_pd_out = 0; + m_pf_out = 0; + m_cr0 = 0; + m_cr1 = 0; + m_cr2 = 0; + m_cr3 = 0; + m_txb = 0; + m_rxb = 0; + m_txd = 0; + m_rxd = 0; + m_sck = 0; + m_ti = 0; + m_to = 0; + m_ci = 0; + m_co0 = 0; + m_co1 = 0; + m_irr = 0; + m_itf = 0; + m_int1 = 0; + m_int2 = 0; + + m_txs = 0; + m_rxs = 0; + m_txcnt = 0; + m_rxcnt = 0; + m_txbuf = 0; + m_ovc0 = 0; + m_ovc1 = 0; + m_ovce = 0; + m_ovcf = 0; + m_ovcs = 0; + m_edges = 0; + ETMM = 0xff; TMM = 0xff; MA = 0xff; @@ -1777,80 +1955,33 @@ static CPU_RESET( upd7810 ) MF = 0xff; MKL = 0xff; MKH = 0xff; //? - cpustate->handle_timers = upd7810_timers; -} - -static CPU_RESET( upd7807 ) -{ - upd7810_state *cpustate = get_safe_token(device); - CPU_RESET_CALL(upd7810); - cpustate->opXX = opXX_7807; } -static CPU_RESET( upd7801 ) +void upd7801_device::device_reset() { - upd7810_state *cpustate = get_safe_token(device); - CPU_RESET_CALL(upd7810); - cpustate->op48 = op48_7801; - cpustate->op4C = op4C_7801; - cpustate->op4D = op4D_7801; - cpustate->op60 = op60_7801; - cpustate->op64 = op64_7801; - cpustate->op70 = op70_7801; - cpustate->op74 = op74_7801; - cpustate->opXX = opXX_7801; - cpustate->handle_timers = upd7801_timers; + upd7810_device::device_reset(); MA = 0; /* Port A is output port on the uPD7801 */ - cpustate->ovc0 = 0; + m_ovc0 = 0; } -static CPU_RESET( upd78c05 ) +void upd78c05_device::device_reset() { - upd7810_state *cpustate = get_safe_token(device); - CPU_RESET_CALL(upd7810); - cpustate->op48 = op48_78c05; - cpustate->op4C = op4C_78c05; - cpustate->op4D = op4D_78c05; - cpustate->op60 = op60_78c05; - cpustate->op64 = op64_78c05; - cpustate->op70 = op70_78c05; - cpustate->op74 = op74_78c05; - cpustate->opXX = opXX_78c05; + upd7810_device::device_reset(); MA = 0; /* All outputs */ MC = 0xFF; /* All inputs */ V = 0xFF; /* The vector register is always pointing to FF00 */ - cpustate->handle_timers = upd78c05_timers; TM0 = 0xFF; /* Timer seems to be running from boot */ - cpustate->ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0; + m_ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0; } -static CPU_RESET( upd78c06 ) -{ - upd7810_state *cpustate = get_safe_token(device); - CPU_RESET_CALL(upd78c05); - cpustate->op48 = op48_78c06; - cpustate->op4C = op4C_78c06; - cpustate->op4D = op4D_78c06; - cpustate->op60 = op60_78c06; - cpustate->op64 = op64_78c06; - cpustate->op70 = op70_78c06; - cpustate->op74 = op74_78c06; - cpustate->opXX = opXX_78c06; -} -static CPU_EXIT( upd7810 ) +void upd7810_device::execute_run() { -} - -static CPU_EXECUTE( upd7810 ) -{ - upd7810_state *cpustate = get_safe_token(device); - do { int cc = 0; - debugger_instruction_hook(device, PC); + debugger_instruction_hook(this, PC); PPC = PC; RDOP(OP); @@ -1860,15 +1991,15 @@ static CPU_EXECUTE( upd7810 ) * L0 for "MVI L,xx" or "LXI H,xxxx" * L1 for "MVI A,xx" */ - PSW &= ~cpustate->opXX[OP].mask_l0_l1; + PSW &= ~m_opXX[OP].mask_l0_l1; /* skip flag set and not SOFTI opcode? */ if ((PSW & SK) && (OP != 0x72)) { - if (cpustate->opXX[OP].cycles) + if (m_opXX[OP].cycles) { - cc = cpustate->opXX[OP].cycles_skip; - PC += cpustate->opXX[OP].oplen - 1; + cc = m_opXX[OP].cycles_skip; + PC += m_opXX[OP].oplen - 1; } else { @@ -1876,478 +2007,129 @@ static CPU_EXECUTE( upd7810 ) switch (OP) { case 0x48: - cc = cpustate->op48[OP2].cycles_skip; - PC += cpustate->op48[OP2].oplen - 2; + cc = m_op48[OP2].cycles_skip; + PC += m_op48[OP2].oplen - 2; break; case 0x4c: - cc = cpustate->op4C[OP2].cycles_skip; - PC += cpustate->op4C[OP2].oplen - 2; + cc = m_op4C[OP2].cycles_skip; + PC += m_op4C[OP2].oplen - 2; break; case 0x4d: - cc = cpustate->op4D[OP2].cycles_skip; - PC += cpustate->op4D[OP2].oplen - 2; + cc = m_op4D[OP2].cycles_skip; + PC += m_op4D[OP2].oplen - 2; break; case 0x60: - cc = cpustate->op60[OP2].cycles_skip; - PC += cpustate->op60[OP2].oplen - 2; + cc = m_op60[OP2].cycles_skip; + PC += m_op60[OP2].oplen - 2; break; case 0x64: - cc = cpustate->op64[OP2].cycles_skip; - PC += cpustate->op64[OP2].oplen - 2; + cc = m_op64[OP2].cycles_skip; + PC += m_op64[OP2].oplen - 2; break; case 0x70: - cc = cpustate->op70[OP2].cycles_skip; - PC += cpustate->op70[OP2].oplen - 2; + cc = m_op70[OP2].cycles_skip; + PC += m_op70[OP2].oplen - 2; break; case 0x74: - cc = cpustate->op74[OP2].cycles_skip; - PC += cpustate->op74[OP2].oplen - 2; + cc = m_op74[OP2].cycles_skip; + PC += m_op74[OP2].oplen - 2; break; default: fatalerror("uPD7810 internal error: check cycle counts for main\n"); } } PSW &= ~SK; - cpustate->handle_timers( cpustate, cc ); + handle_timers( cc ); } else { - cc = cpustate->opXX[OP].cycles; - cpustate->handle_timers( cpustate, cc ); - (*cpustate->opXX[OP].opfunc)(cpustate); + cc = m_opXX[OP].cycles; + handle_timers( cc ); + (this->*m_opXX[OP].opfunc)(); } - cpustate->icount -= cc; - upd7810_take_irq(cpustate); + m_icount -= cc; + upd7810_take_irq(); - } while (cpustate->icount > 0); + } while (m_icount > 0); } -static void set_irq_line(upd7810_state *cpustate, int irqline, int state) +void upd7801_device::execute_set_input(int irqline, int state) { /* The uPD7801 can check for falling and rising edges changes on the INT2 input */ - switch ( cpustate->config.type ) + switch ( irqline ) { - case TYPE_7801: - switch ( irqline ) - { - case UPD7810_INTF0: - /* INT0 is level sensitive */ - if ( state == ASSERT_LINE ) - IRR |= INTF0; - else - IRR &= INTF0; - break; + case UPD7810_INTF0: + /* INT0 is level sensitive */ + if ( state == ASSERT_LINE ) + IRR |= INTF0; + else + IRR &= INTF0; + break; - case UPD7810_INTF1: - /* INT1 is rising edge sensitive */ - if ( cpustate->int1 == CLEAR_LINE && state == ASSERT_LINE ) - IRR |= INTF1; + case UPD7810_INTF1: + /* INT1 is rising edge sensitive */ + if ( m_int1 == CLEAR_LINE && state == ASSERT_LINE ) + IRR |= INTF1; - cpustate->int1 = state; - break; + m_int1 = state; + break; - case UPD7810_INTF2: - /* INT2 is rising or falling edge sensitive */ - /* Check if the ES bit is set then check for rising edge, otherwise falling edge */ - if ( MKL & 0x20 ) - { - if ( cpustate->int2 == CLEAR_LINE && state == ASSERT_LINE ) - { - IRR |= INTF2; - } - } - else + case UPD7810_INTF2: + /* INT2 is rising or falling edge sensitive */ + /* Check if the ES bit is set then check for rising edge, otherwise falling edge */ + if ( MKL & 0x20 ) + { + if ( m_int2 == CLEAR_LINE && state == ASSERT_LINE ) { - if ( cpustate->int2 == ASSERT_LINE && state == CLEAR_LINE ) - { - IRR |= INTF2; - } + IRR |= INTF2; } - cpustate->int2 = state; - break; } - break; - - default: - if (state != CLEAR_LINE) + else { - if (irqline == INPUT_LINE_NMI) + if ( m_int2 == ASSERT_LINE && state == CLEAR_LINE ) { - /* no nested NMIs ? */ -// if (0 == (IRR & INTNMI)) - { - IRR |= INTNMI; - SP--; - WM( SP, PSW ); - SP--; - WM( SP, PCH ); - SP--; - WM( SP, PCL ); - IFF = 0; - PSW &= ~(SK|L0|L1); - PC = 0x0004; - } - } - else - if (irqline == UPD7810_INTF1) - IRR |= INTF1; - else - if ( irqline == UPD7810_INTF2 && ( MKL & 0x20 ) ) IRR |= INTF2; - // gamemaster hack - else - if (irqline == UPD7810_INTFE1) - IRR |= INTFE1; - else - logerror("upd7810_set_irq_line invalid irq line #%d\n", irqline); + } } - /* resetting interrupt requests is done with the SKIT/SKNIT opcodes only! */ - } -} - - -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( upd7810 ) -{ - upd7810_state *cpustate = get_safe_token(device); - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTF1: set_irq_line(cpustate, UPD7810_INTF1, info->i); break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTF2: set_irq_line(cpustate, UPD7810_INTF2, info->i); break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTFE1: set_irq_line(cpustate, UPD7810_INTFE1, info->i); break; - - case CPUINFO_INT_PC: PC = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_PC: PC = info->i; break; - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + UPD7810_SP: SP = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_PSW: PSW = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_A: A = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_V: V = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_EA: EA = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_VA: VA = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_BC: BC = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_DE: DE = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_HL: HL = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_EA2: EA2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_VA2: VA2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_BC2: BC2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_DE2: DE2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_HL2: HL2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CNT0: CNT0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CNT1: CNT1 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TM0: TM0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TM1: TM1 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ECNT: ECNT = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ECPT: ECPT = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ETM0: ETM0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ETM1: ETM1 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MA: MA = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MB: MB = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MCC: MCC = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MC: MC = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MM: MM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MF: MF = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TMM: TMM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ETMM: ETMM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_EOM: EOM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_SML: SML = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_SMH: SMH = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ANM: ANM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MKL: MKL = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_MKH: MKH = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_ZCM: ZCM = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TXB: TXB = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_RXB: RXB = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CR0: CR0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CR1: CR1 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CR2: CR2 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CR3: CR3 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TXD: TXD = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_RXD: RXD = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_SCK: SCK = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TI: TI = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_TO: TO = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CI: CI = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CO0: CO0 = info->i; break; - case CPUINFO_INT_REGISTER + UPD7810_CO1: CO1 = info->i; break; - } -} - - - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( upd7810 ) -{ - upd7810_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(upd7810_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 2; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = (IRR & INTNMI) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTF1: info->i = (IRR & INTF1) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTF2: info->i = (IRR & INTF2) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + UPD7810_INTFE1: info->i = (IRR & INTFE1) ? ASSERT_LINE : CLEAR_LINE; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + UPD7810_PC: info->i = PC; break; - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + UPD7810_SP: info->i = SP; break; - case CPUINFO_INT_REGISTER + UPD7810_PSW: info->i = PSW; break; - case CPUINFO_INT_REGISTER + UPD7810_EA: info->i = EA; break; - case CPUINFO_INT_REGISTER + UPD7810_VA: info->i = VA; break; - case CPUINFO_INT_REGISTER + UPD7810_BC: info->i = BC; break; - case CPUINFO_INT_REGISTER + UPD7810_DE: info->i = DE; break; - case CPUINFO_INT_REGISTER + UPD7810_HL: info->i = HL; break; - case CPUINFO_INT_REGISTER + UPD7810_EA2: info->i = EA2; break; - case CPUINFO_INT_REGISTER + UPD7810_VA2: info->i = VA2; break; - case CPUINFO_INT_REGISTER + UPD7810_BC2: info->i = BC2; break; - case CPUINFO_INT_REGISTER + UPD7810_DE2: info->i = DE2; break; - case CPUINFO_INT_REGISTER + UPD7810_HL2: info->i = HL2; break; - case CPUINFO_INT_REGISTER + UPD7810_CNT0: info->i = CNT0; break; - case CPUINFO_INT_REGISTER + UPD7810_CNT1: info->i = CNT1; break; - case CPUINFO_INT_REGISTER + UPD7810_TM0: info->i = TM0; break; - case CPUINFO_INT_REGISTER + UPD7810_TM1: info->i = TM1; break; - case CPUINFO_INT_REGISTER + UPD7810_ECNT: info->i = ECNT; break; - case CPUINFO_INT_REGISTER + UPD7810_ECPT: info->i = ECPT; break; - case CPUINFO_INT_REGISTER + UPD7810_ETM0: info->i = ETM0; break; - case CPUINFO_INT_REGISTER + UPD7810_ETM1: info->i = ETM1; break; - case CPUINFO_INT_REGISTER + UPD7810_MA: info->i = MA; break; - case CPUINFO_INT_REGISTER + UPD7810_MB: info->i = MB; break; - case CPUINFO_INT_REGISTER + UPD7810_MCC: info->i = MCC; break; - case CPUINFO_INT_REGISTER + UPD7810_MC: info->i = MC; break; - case CPUINFO_INT_REGISTER + UPD7810_MM: info->i = MM; break; - case CPUINFO_INT_REGISTER + UPD7810_MF: info->i = MF; break; - case CPUINFO_INT_REGISTER + UPD7810_TMM: info->i = TMM; break; - case CPUINFO_INT_REGISTER + UPD7810_ETMM: info->i = ETMM; break; - case CPUINFO_INT_REGISTER + UPD7810_EOM: info->i = EOM; break; - case CPUINFO_INT_REGISTER + UPD7810_SML: info->i = SML; break; - case CPUINFO_INT_REGISTER + UPD7810_SMH: info->i = SMH; break; - case CPUINFO_INT_REGISTER + UPD7810_ANM: info->i = ANM; break; - case CPUINFO_INT_REGISTER + UPD7810_MKL: info->i = MKL; break; - case CPUINFO_INT_REGISTER + UPD7810_MKH: info->i = MKH; break; - case CPUINFO_INT_REGISTER + UPD7810_ZCM: info->i = ZCM; break; - case CPUINFO_INT_REGISTER + UPD7810_TXB: info->i = TXB; break; - case CPUINFO_INT_REGISTER + UPD7810_RXB: info->i = RXB; break; - case CPUINFO_INT_REGISTER + UPD7810_CR0: info->i = CR0; break; - case CPUINFO_INT_REGISTER + UPD7810_CR1: info->i = CR1; break; - case CPUINFO_INT_REGISTER + UPD7810_CR2: info->i = CR2; break; - case CPUINFO_INT_REGISTER + UPD7810_CR3: info->i = CR3; break; - case CPUINFO_INT_REGISTER + UPD7810_TXD: info->i = TXD; break; - case CPUINFO_INT_REGISTER + UPD7810_RXD: info->i = RXD; break; - case CPUINFO_INT_REGISTER + UPD7810_SCK: info->i = SCK; break; - case CPUINFO_INT_REGISTER + UPD7810_TI: info->i = TI; break; - case CPUINFO_INT_REGISTER + UPD7810_TO: info->i = TO; break; - case CPUINFO_INT_REGISTER + UPD7810_CI: info->i = CI; break; - case CPUINFO_INT_REGISTER + UPD7810_CO0: info->i = CO0; break; - case CPUINFO_INT_REGISTER + UPD7810_CO1: info->i = CO1; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(upd7810); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(upd7810); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7810); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(upd7810); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(upd7810); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7810); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "uPD7810"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "upd7810"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "NEC uPD7810"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "0.3"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%s:%s:%s:%s:%s:%s", - cpustate->psw & 0x40 ? "ZF":"--", - cpustate->psw & 0x20 ? "SK":"--", - cpustate->psw & 0x10 ? "HC":"--", - cpustate->psw & 0x08 ? "L1":"--", - cpustate->psw & 0x04 ? "L0":"--", - cpustate->psw & 0x01 ? "CY":"--"); - break; - - case CPUINFO_STR_REGISTER + UPD7810_PC: sprintf(info->s, "PC :%04X", cpustate->pc.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_SP: sprintf(info->s, "SP :%04X", cpustate->sp.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_PSW: sprintf(info->s, "PSW :%02X", cpustate->psw); break; - case CPUINFO_STR_REGISTER + UPD7810_A: sprintf(info->s, "A :%02X", cpustate->va.b.l); break; - case CPUINFO_STR_REGISTER + UPD7810_V: sprintf(info->s, "V :%02X", cpustate->va.b.h); break; - case CPUINFO_STR_REGISTER + UPD7810_EA: sprintf(info->s, "EA :%04X", cpustate->ea.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_BC: sprintf(info->s, "BC :%04X", cpustate->bc.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_DE: sprintf(info->s, "DE :%04X", cpustate->de.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_HL: sprintf(info->s, "HL :%04X", cpustate->hl.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_A2: sprintf(info->s, "A' :%02X", cpustate->va2.b.l); break; - case CPUINFO_STR_REGISTER + UPD7810_V2: sprintf(info->s, "V' :%02X", cpustate->va2.b.h); break; - case CPUINFO_STR_REGISTER + UPD7810_EA2: sprintf(info->s, "EA' :%04X", cpustate->ea2.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_BC2: sprintf(info->s, "BC' :%04X", cpustate->bc2.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_DE2: sprintf(info->s, "DE' :%04X", cpustate->de2.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_HL2: sprintf(info->s, "HL' :%04X", cpustate->hl2.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_CNT0: sprintf(info->s, "CNT0:%02X", cpustate->cnt.b.l); break; - case CPUINFO_STR_REGISTER + UPD7810_CNT1: sprintf(info->s, "CNT1:%02X", cpustate->cnt.b.h); break; - case CPUINFO_STR_REGISTER + UPD7810_TM0: sprintf(info->s, "TM0 :%02X", cpustate->tm.b.l); break; - case CPUINFO_STR_REGISTER + UPD7810_TM1: sprintf(info->s, "TM1 :%02X", cpustate->tm.b.h); break; - case CPUINFO_STR_REGISTER + UPD7810_ECNT: sprintf(info->s, "ECNT:%04X", cpustate->ecnt.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_ECPT: sprintf(info->s, "ECPT:%04X", cpustate->ecnt.w.h); break; - case CPUINFO_STR_REGISTER + UPD7810_ETM0: sprintf(info->s, "ETM0:%04X", cpustate->etm.w.l); break; - case CPUINFO_STR_REGISTER + UPD7810_ETM1: sprintf(info->s, "ETM1:%04X", cpustate->etm.w.h); break; - case CPUINFO_STR_REGISTER + UPD7810_MA: sprintf(info->s, "MA :%02X", cpustate->ma); break; - case CPUINFO_STR_REGISTER + UPD7810_MB: sprintf(info->s, "MB :%02X", cpustate->mb); break; - case CPUINFO_STR_REGISTER + UPD7810_MCC: sprintf(info->s, "MCC :%02X", cpustate->mcc); break; - case CPUINFO_STR_REGISTER + UPD7810_MC: sprintf(info->s, "MC :%02X", cpustate->mc); break; - case CPUINFO_STR_REGISTER + UPD7810_MM: sprintf(info->s, "MM :%02X", cpustate->mm); break; - case CPUINFO_STR_REGISTER + UPD7810_MF: sprintf(info->s, "MF :%02X", cpustate->mf); break; - case CPUINFO_STR_REGISTER + UPD7810_TMM: sprintf(info->s, "TMM :%02X", cpustate->tmm); break; - case CPUINFO_STR_REGISTER + UPD7810_ETMM: sprintf(info->s, "ETMM:%02X", cpustate->etmm); break; - case CPUINFO_STR_REGISTER + UPD7810_EOM: sprintf(info->s, "EOM :%02X", cpustate->eom); break; - case CPUINFO_STR_REGISTER + UPD7810_SML: sprintf(info->s, "SML :%02X", cpustate->sml); break; - case CPUINFO_STR_REGISTER + UPD7810_SMH: sprintf(info->s, "SMH :%02X", cpustate->smh); break; - case CPUINFO_STR_REGISTER + UPD7810_ANM: sprintf(info->s, "ANM :%02X", cpustate->anm); break; - case CPUINFO_STR_REGISTER + UPD7810_MKL: sprintf(info->s, "MKL :%02X", cpustate->mkl); break; - case CPUINFO_STR_REGISTER + UPD7810_MKH: sprintf(info->s, "MKH :%02X", cpustate->mkh); break; - case CPUINFO_STR_REGISTER + UPD7810_ZCM: sprintf(info->s, "ZCM :%02X", cpustate->zcm); break; - case CPUINFO_STR_REGISTER + UPD7810_CR0: sprintf(info->s, "CR0 :%02X", cpustate->cr0); break; - case CPUINFO_STR_REGISTER + UPD7810_CR1: sprintf(info->s, "CR1 :%02X", cpustate->cr1); break; - case CPUINFO_STR_REGISTER + UPD7810_CR2: sprintf(info->s, "CR2 :%02X", cpustate->cr2); break; - case CPUINFO_STR_REGISTER + UPD7810_CR3: sprintf(info->s, "CR3 :%02X", cpustate->cr3); break; - case CPUINFO_STR_REGISTER + UPD7810_RXB: sprintf(info->s, "RXB :%02X", cpustate->rxb); break; - case CPUINFO_STR_REGISTER + UPD7810_TXB: sprintf(info->s, "TXB :%02X", cpustate->txb); break; - case CPUINFO_STR_REGISTER + UPD7810_TXD: sprintf(info->s, "TXD :%d", cpustate->txd); break; - case CPUINFO_STR_REGISTER + UPD7810_RXD: sprintf(info->s, "RXD :%d", cpustate->rxd); break; - case CPUINFO_STR_REGISTER + UPD7810_SCK: sprintf(info->s, "SCK :%d", cpustate->sck); break; - case CPUINFO_STR_REGISTER + UPD7810_TI: sprintf(info->s, "TI :%d", cpustate->ti); break; - case CPUINFO_STR_REGISTER + UPD7810_TO: sprintf(info->s, "TO :%d", cpustate->to); break; - case CPUINFO_STR_REGISTER + UPD7810_CI: sprintf(info->s, "CI :%d", cpustate->ci); break; - case CPUINFO_STR_REGISTER + UPD7810_CO0: sprintf(info->s, "CO0 :%d", cpustate->co0 & 1); break; - case CPUINFO_STR_REGISTER + UPD7810_CO1: sprintf(info->s, "CO1 :%d", cpustate->co1 & 1); break; + m_int2 = state; + break; } } - -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -CPU_GET_INFO( upd7807 ) +void upd7810_device::execute_set_input(int irqline, int state) { - switch (state) + if (state != CLEAR_LINE) { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7807); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7807); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "uPD7807"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "upd7807"); break; - - default: CPU_GET_INFO_CALL(upd7810); break; - } -} - -CPU_GET_INFO( upd7801 ) { - switch( state ) { - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd7801); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd7801); break; - - case CPUINFO_STR_NAME: strcpy(info->s, "uPD7801"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "upd7801"); break; - - default: CPU_GET_INFO_CALL(upd7810); break; - } -} - -CPU_GET_INFO( upd78c05 ) { - switch ( state ) { - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 4; break; - - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd78c05); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(upd78c05); break; - - case CPUINFO_STR_NAME: strcpy(info->s, "uPD78C05"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "upd78c05"); break; - - /* These registers are not present in the uPD78C05 cpu */ - case CPUINFO_STR_REGISTER + UPD7810_A2: - case CPUINFO_STR_REGISTER + UPD7810_V2: - case CPUINFO_STR_REGISTER + UPD7810_EA2: - case CPUINFO_STR_REGISTER + UPD7810_BC2: - case CPUINFO_STR_REGISTER + UPD7810_DE2: - case CPUINFO_STR_REGISTER + UPD7810_HL2: - case CPUINFO_STR_REGISTER + UPD7810_MA: - case CPUINFO_STR_REGISTER + UPD7810_MCC: - case CPUINFO_STR_REGISTER + UPD7810_MC: - case CPUINFO_STR_REGISTER + UPD7810_MM: - case CPUINFO_STR_REGISTER + UPD7810_MF: - case CPUINFO_STR_REGISTER + UPD7810_ETMM: - case CPUINFO_STR_REGISTER + UPD7810_EOM: - case CPUINFO_STR_REGISTER + UPD7810_SML: - case CPUINFO_STR_REGISTER + UPD7810_SMH: - case CPUINFO_STR_REGISTER + UPD7810_ANM: - case CPUINFO_STR_REGISTER + UPD7810_MKH: - case CPUINFO_STR_REGISTER + UPD7810_ZCM: - case CPUINFO_STR_REGISTER + UPD7810_CR0: - case CPUINFO_STR_REGISTER + UPD7810_CR1: - case CPUINFO_STR_REGISTER + UPD7810_CR2: - case CPUINFO_STR_REGISTER + UPD7810_CR3: - case CPUINFO_STR_REGISTER + UPD7810_RXB: - case CPUINFO_STR_REGISTER + UPD7810_TXB: - case CPUINFO_STR_REGISTER + UPD7810_TXD: - case CPUINFO_STR_REGISTER + UPD7810_RXD: - case CPUINFO_STR_REGISTER + UPD7810_SCK: - case CPUINFO_STR_REGISTER + UPD7810_TI: - case CPUINFO_STR_REGISTER + UPD7810_TO: - case CPUINFO_STR_REGISTER + UPD7810_CI: - case CPUINFO_STR_REGISTER + UPD7810_CO0: - case CPUINFO_STR_REGISTER + UPD7810_CO1: break; - - default: CPU_GET_INFO_CALL(upd7801); break; - } -} - -CPU_GET_INFO( upd78c06 ) { - switch ( state ) { - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(upd78c06); break; - - case CPUINFO_STR_NAME: strcpy(info->s, "uPD78C06"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "upd78c06"); break; - - default: CPU_GET_INFO_CALL(upd78c05); break; + if (irqline == INPUT_LINE_NMI) + { + /* no nested NMIs ? */ +// if (0 == (IRR & INTNMI)) + { + IRR |= INTNMI; + SP--; + WM( SP, PSW ); + SP--; + WM( SP, PCH ); + SP--; + WM( SP, PCL ); + IFF = 0; + PSW &= ~(SK|L0|L1); + PC = 0x0004; + } + } + else + if (irqline == UPD7810_INTF1) + IRR |= INTF1; + else + if ( irqline == UPD7810_INTF2 && ( MKL & 0x20 ) ) + IRR |= INTF2; + // gamemaster hack + else + if (irqline == UPD7810_INTFE1) + IRR |= INTFE1; + else + logerror("upd7810_set_irq_line invalid irq line #%d\n", irqline); } + /* resetting interrupt requests is done with the SKIT/SKNIT opcodes only! */ } -DEFINE_LEGACY_CPU_DEVICE(UPD7810, upd7810); -DEFINE_LEGACY_CPU_DEVICE(UPD7807, upd7807); -DEFINE_LEGACY_CPU_DEVICE(UPD7801, upd7801); -DEFINE_LEGACY_CPU_DEVICE(UPD78C05, upd78c05); -DEFINE_LEGACY_CPU_DEVICE(UPD78C06, upd78c06); diff --git a/src/emu/cpu/upd7810/upd7810.h b/src/emu/cpu/upd7810/upd7810.h index b493dbd4e24..f73d3df8d7c 100644 --- a/src/emu/cpu/upd7810/upd7810.h +++ b/src/emu/cpu/upd7810/upd7810.h @@ -10,30 +10,6 @@ 7811 (4kbyte),7812(8),7814(16) have internal rom at 0x0000 */ -// unfortunatly memory configuration differs with internal rom size -enum UPD7810_TYPE -{ - TYPE_7801, - TYPE_78C05, - TYPE_78C06, - TYPE_7807, - TYPE_7810 -// TYPE_78C10, // stop instruction added -// TYPE_78IV, -// millions of subtypes -}; - -/* Supply an instance of this function in your driver code: - * It will be called whenever an output signal changes or a new - * input line state is to be sampled. - */ -typedef int (*upd7810_io_callback)(device_t *device, int ioline, int state); - -// use it as reset parameter in the Machine struct -struct UPD7810_CONFIG { - UPD7810_TYPE type; - upd7810_io_callback io_callback; -}; enum { @@ -68,15 +44,1273 @@ enum #define UPD7810_INTF0 2 #define UPD7810_INTFE1 4 -DECLARE_LEGACY_CPU_DEVICE(UPD7810, upd7810); -DECLARE_LEGACY_CPU_DEVICE(UPD7807, upd7807); -DECLARE_LEGACY_CPU_DEVICE(UPD7801, upd7801); -DECLARE_LEGACY_CPU_DEVICE(UPD78C05, upd78c05); -DECLARE_LEGACY_CPU_DEVICE(UPD78C06, upd78c06); -CPU_DISASSEMBLE( upd7810 ); -CPU_DISASSEMBLE( upd7807 ); -CPU_DISASSEMBLE( upd7801 ); -CPU_DISASSEMBLE( upd78c05 ); + +#define MCFG_UPD7810_TO(_devcb) \ + upd7810_device::set_to_func(*device, DEVCB2_##_devcb); + +#define MCFG_UPD7810_TXD(_devcb) \ + upd7810_device::set_txd_func(*device, DEVCB2_##_devcb); + +#define MCFG_UPD7810_RXD(_devcb) \ + upd7810_device::set_rxd_func(*device, DEVCB2_##_devcb); + +class upd7810_device : public cpu_device +{ +public: + // construction/destruction + upd7810_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + upd7810_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); + + // static configuration helpers + template<class _Object> static devcb2_base &set_to_func(device_t &device, _Object object) { return downcast<upd7810_device &>(device).m_to_func.set_callback(object); } + template<class _Object> static devcb2_base &set_txd_func(device_t &device, _Object object) { return downcast<upd7810_device &>(device).m_txd_func.set_callback(object); } + template<class _Object> static devcb2_base &set_rxd_func(device_t &device, _Object object) { return downcast<upd7810_device &>(device).m_rxd_func.set_callback(object); } + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 40; } + virtual UINT32 execute_input_lines() const { return 2; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } + + // device_state_interface overrides + void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 1; } + virtual UINT32 disasm_max_opcode_bytes() const { return 4; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + + virtual void handle_timers(int cycles); + virtual void upd7810_take_irq(); + + devcb2_write_line m_to_func; + devcb2_write_line m_txd_func; + devcb2_read_line m_rxd_func; + + typedef void (upd7810_device::*opcode_func)(); + + struct opcode_s { + opcode_func opfunc; + UINT8 oplen; + UINT8 cycles; + UINT8 cycles_skip; + UINT8 mask_l0_l1; + }; + + static const struct opcode_s s_op48[256]; + static const struct opcode_s s_op4C[256]; + static const struct opcode_s s_op4D[256]; + static const struct opcode_s s_op60[256]; + static const struct opcode_s s_op64[256]; + static const struct opcode_s s_op70[256]; + static const struct opcode_s s_op74[256]; + static const struct opcode_s s_opXX_7810[256]; + static const struct opcode_s s_opXX_7807[256]; + static const struct opcode_s s_op48_7801[256]; + static const struct opcode_s s_op4C_7801[256]; + static const struct opcode_s s_op4D_7801[256]; + static const struct opcode_s s_op60_7801[256]; + static const struct opcode_s s_op64_7801[256]; + static const struct opcode_s s_op70_7801[256]; + static const struct opcode_s s_op74_7801[256]; + static const struct opcode_s s_opXX_7801[256]; + static const struct opcode_s s_op48_78c05[256]; + static const struct opcode_s s_op4C_78c05[256]; + static const struct opcode_s s_op4D_78c05[256]; + static const struct opcode_s s_op60_78c05[256]; + static const struct opcode_s s_op64_78c05[256]; + static const struct opcode_s s_op70_78c05[256]; + static const struct opcode_s s_op74_78c05[256]; + static const struct opcode_s s_opXX_78c05[256]; + static const struct opcode_s s_op48_78c06[256]; + static const struct opcode_s s_op4C_78c06[256]; + static const struct opcode_s s_op4D_78c06[256]; + static const struct opcode_s s_op60_78c06[256]; + static const struct opcode_s s_op64_78c06[256]; + static const struct opcode_s s_op70_78c06[256]; + static const struct opcode_s s_op74_78c06[256]; + static const struct opcode_s s_opXX_78c06[256]; + + address_space_config m_program_config; + address_space_config m_io_config; + + PAIR m_ppc; /* previous program counter */ + PAIR m_pc; /* program counter */ + PAIR m_sp; /* stack pointer */ + UINT8 m_op; /* opcode */ + UINT8 m_op2; /* opcode part 2 */ + UINT8 m_iff; /* interrupt enable flip flop */ + UINT8 m_psw; /* processor status word */ + PAIR m_ea; /* extended accumulator */ + PAIR m_va; /* accumulator + vector register */ + PAIR m_bc; /* 8bit B and C registers / 16bit BC register */ + PAIR m_de; /* 8bit D and E registers / 16bit DE register */ + PAIR m_hl; /* 8bit H and L registers / 16bit HL register */ + PAIR m_ea2; /* alternate register set */ + PAIR m_va2; + PAIR m_bc2; + PAIR m_de2; + PAIR m_hl2; + PAIR m_cnt; /* 8 bit timer counter */ + PAIR m_tm; /* 8 bit timer 0/1 comparator inputs */ + PAIR m_ecnt; /* timer counter register / capture register */ + PAIR m_etm; /* timer 0/1 comparator inputs */ + UINT8 m_ma; /* port A input or output mask */ + UINT8 m_mb; /* port B input or output mask */ + UINT8 m_mcc; /* port C control/port select */ + UINT8 m_mc; /* port C input or output mask */ + UINT8 m_mm; /* memory mapping */ + UINT8 m_mf; /* port F input or output mask */ + UINT8 m_tmm; /* timer 0 and timer 1 operating parameters */ + UINT8 m_etmm; /* 16-bit multifunction timer/event counter */ + UINT8 m_eom; /* 16-bit timer/event counter output control */ + UINT8 m_sml; /* serial interface parameters low */ + UINT8 m_smh; /* -"- high */ + UINT8 m_anm; /* analog to digital converter operating parameters */ + UINT8 m_mkl; /* interrupt mask low */ + UINT8 m_mkh; /* -"- high */ + UINT8 m_zcm; /* bias circuitry for ac zero-cross detection */ + UINT8 m_pa_in; /* port A,B,C,D,F inputs */ + UINT8 m_pb_in; + UINT8 m_pc_in; + UINT8 m_pd_in; + UINT8 m_pf_in; + UINT8 m_pa_out; /* port A,B,C,D,F outputs */ + UINT8 m_pb_out; + UINT8 m_pc_out; + UINT8 m_pd_out; + UINT8 m_pf_out; + UINT8 m_cr0; /* analog digital conversion register 0 */ + UINT8 m_cr1; /* analog digital conversion register 1 */ + UINT8 m_cr2; /* analog digital conversion register 2 */ + UINT8 m_cr3; /* analog digital conversion register 3 */ + UINT8 m_txb; /* transmitter buffer */ + UINT8 m_rxb; /* receiver buffer */ + UINT8 m_txd; /* port C control line states */ + UINT8 m_rxd; + UINT8 m_sck; + UINT8 m_ti; + UINT8 m_to; + UINT8 m_ci; + UINT8 m_co0; + UINT8 m_co1; + UINT16 m_irr; /* interrupt request register */ + UINT16 m_itf; /* interrupt test flag register */ + int m_int1; /* keep track of current int1 state. Needed for 7801 irq checking. */ + int m_int2; /* keep track to current int2 state. Needed for 7801 irq checking. */ + + /* internal helper variables */ + UINT16 m_txs; /* transmitter shift register */ + UINT16 m_rxs; /* receiver shift register */ + UINT8 m_txcnt; /* transmitter shift register bit count */ + UINT8 m_rxcnt; /* receiver shift register bit count */ + UINT8 m_txbuf; /* transmitter buffer was written */ + INT32 m_ovc0; /* overflow counter for timer 0 (for clock div 12/384) */ + INT32 m_ovc1; /* overflow counter for timer 0 (for clock div 12/384) */ + INT32 m_ovce; /* overflow counter for ecnt */ + INT32 m_ovcf; /* overflow counter for fixed clock div 3 mode */ + INT32 m_ovcs; /* overflow counter for serial I/O */ + UINT8 m_edges; /* rising/falling edge flag for serial I/O */ + + const struct opcode_s *m_opXX; /* opcode table */ + const struct opcode_s *m_op48; + const struct opcode_s *m_op4C; + const struct opcode_s *m_op4D; + const struct opcode_s *m_op60; + const struct opcode_s *m_op64; + const struct opcode_s *m_op70; + const struct opcode_s *m_op74; + address_space *m_program; + direct_read_data *m_direct; + address_space *m_io; + int m_icount; + + UINT8 RP(offs_t port); + void WP(offs_t port, UINT8 data); + void upd7810_write_EOM(); + void upd7810_write_TXB(); + void upd7810_sio_output(); + void upd7810_sio_input(); + void illegal(); + void illegal2(); + void SLRC_A(); + void SLRC_B(); + void SLRC_C(); + void SLLC_A(); + void SLLC_B(); + void SLLC_C(); + void SK_NV(); + void SK_CY(); + void SK_HC(); + void SK_Z(); + void SKN_NV(); + void SKN_CY(); + void SKN_HC(); + void SKN_Z(); + void SLR_A(); + void SLR_B(); + void SLR_C(); + void SLL_A(); + void SLL_B(); + void SLL_C(); + void JEA(); + void CALB(); + void CLC(); + void STC(); + void MUL_A(); + void MUL_B(); + void MUL_C(); + void RLR_A(); + void RLR_B(); + void RLR_C(); + void RLL_A(); + void RLL_B(); + void RLL_C(); + void RLD(); + void RRD(); + void NEGA(); + void HALT(); + void DIV_A(); + void DIV_B(); + void DIV_C(); + void SKIT_NMI(); + void SKIT_FT0(); + void SKIT_FT1(); + void SKIT_F1(); + void SKIT_F2(); + void SKIT_FE0(); + void SKIT_FE1(); + void SKIT_FEIN(); + void SKIT_FAD(); + void SKIT_FSR(); + void SKIT_FST(); + void SKIT_ER(); + void SKIT_OV(); + void SKIT_AN4(); + void SKIT_AN5(); + void SKIT_AN6(); + void SKIT_AN7(); + void SKIT_SB(); + void SKNIT_NMI(); + void SKNIT_FT0(); + void SKNIT_FT1(); + void SKNIT_F1(); + void SKNIT_F2(); + void SKNIT_FE0(); + void SKNIT_FE1(); + void SKNIT_FEIN(); + void SKNIT_FAD(); + void SKNIT_FSR(); + void SKNIT_FST(); + void SKNIT_ER(); + void SKNIT_OV(); + void SKNIT_AN4(); + void SKNIT_AN5(); + void SKNIT_AN6(); + void SKNIT_AN7(); + void SKNIT_SB(); + void LDEAX_D(); + void LDEAX_H(); + void LDEAX_Dp(); + void LDEAX_Hp(); + void LDEAX_D_xx(); + void LDEAX_H_A(); + void LDEAX_H_B(); + void LDEAX_H_EA(); + void LDEAX_H_xx(); + void STEAX_D(); + void STEAX_H(); + void STEAX_Dp(); + void STEAX_Hp(); + void STEAX_D_xx(); + void STEAX_H_A(); + void STEAX_H_B(); + void STEAX_H_EA(); + void STEAX_H_xx(); + void DSLR_EA(); + void DSLL_EA(); + void TABLE(); + void DRLR_EA(); + void DRLL_EA(); + void STOP(); + void DMOV_EA_ECNT(); + void DMOV_EA_ECPT(); + void DMOV_ETM0_EA(); + void DMOV_ETM1_EA(); + void MOV_A_PA(); + void MOV_A_PB(); + void MOV_A_PC(); + void MOV_A_PD(); + void MOV_A_PF(); + void MOV_A_MKH(); + void MOV_A_MKL(); + void MOV_A_ANM(); + void MOV_A_SMH(); + void MOV_A_EOM(); + void MOV_A_TMM(); + void MOV_A_PT(); + void MOV_A_RXB(); + void MOV_A_CR0(); + void MOV_A_CR1(); + void MOV_A_CR2(); + void MOV_A_CR3(); + void MOV_PA_A(); + void MOV_PB_A(); + void MOV_PC_A(); + void MOV_PD_A(); + void MOV_PF_A(); + void MOV_MKH_A(); + void MOV_MKL_A(); + void MOV_ANM_A(); + void MOV_SMH_A(); + void MOV_SML_A(); + void MOV_EOM_A(); + void MOV_ETMM_A(); + void MOV_TMM_A(); + void MOV_MM_A(); + void MOV_MCC_A(); + void MOV_MA_A(); + void MOV_MB_A(); + void MOV_MC_A(); + void MOV_MF_A(); + void MOV_TXB_A(); + void MOV_TM0_A(); + void MOV_TM1_A(); + void MOV_ZCM_A(); + void ANA_V_A(); + void ANA_A_A(); + void ANA_B_A(); + void ANA_C_A(); + void ANA_D_A(); + void ANA_E_A(); + void ANA_H_A(); + void ANA_L_A(); + void XRA_V_A(); + void XRA_A_A(); + void XRA_B_A(); + void XRA_C_A(); + void XRA_D_A(); + void XRA_E_A(); + void XRA_H_A(); + void XRA_L_A(); + void ORA_V_A(); + void ORA_A_A(); + void ORA_B_A(); + void ORA_C_A(); + void ORA_D_A(); + void ORA_E_A(); + void ORA_H_A(); + void ORA_L_A(); + void ADDNC_V_A(); + void ADDNC_A_A(); + void ADDNC_B_A(); + void ADDNC_C_A(); + void ADDNC_D_A(); + void ADDNC_E_A(); + void ADDNC_H_A(); + void ADDNC_L_A(); + void GTA_V_A(); + void GTA_A_A(); + void GTA_B_A(); + void GTA_C_A(); + void GTA_D_A(); + void GTA_E_A(); + void GTA_H_A(); + void GTA_L_A(); + void SUBNB_V_A(); + void SUBNB_A_A(); + void SUBNB_B_A(); + void SUBNB_C_A(); + void SUBNB_D_A(); + void SUBNB_E_A(); + void SUBNB_H_A(); + void SUBNB_L_A(); + void LTA_V_A(); + void LTA_A_A(); + void LTA_B_A(); + void LTA_C_A(); + void LTA_D_A(); + void LTA_E_A(); + void LTA_H_A(); + void LTA_L_A(); + void ADD_V_A(); + void ADD_A_A(); + void ADD_B_A(); + void ADD_C_A(); + void ADD_D_A(); + void ADD_E_A(); + void ADD_H_A(); + void ADD_L_A(); + void ADC_V_A(); + void ADC_A_A(); + void ADC_B_A(); + void ADC_C_A(); + void ADC_D_A(); + void ADC_E_A(); + void ADC_H_A(); + void ADC_L_A(); + void SUB_V_A(); + void SUB_A_A(); + void SUB_B_A(); + void SUB_C_A(); + void SUB_D_A(); + void SUB_E_A(); + void SUB_H_A(); + void SUB_L_A(); + void NEA_V_A(); + void NEA_A_A(); + void NEA_B_A(); + void NEA_C_A(); + void NEA_D_A(); + void NEA_E_A(); + void NEA_H_A(); + void NEA_L_A(); + void SBB_V_A(); + void SBB_A_A(); + void SBB_B_A(); + void SBB_C_A(); + void SBB_D_A(); + void SBB_E_A(); + void SBB_H_A(); + void SBB_L_A(); + void EQA_V_A(); + void EQA_A_A(); + void EQA_B_A(); + void EQA_C_A(); + void EQA_D_A(); + void EQA_E_A(); + void EQA_H_A(); + void EQA_L_A(); + void ANA_A_V(); + void ANA_A_B(); + void ANA_A_C(); + void ANA_A_D(); + void ANA_A_E(); + void ANA_A_H(); + void ANA_A_L(); + void XRA_A_V(); + void XRA_A_B(); + void XRA_A_C(); + void XRA_A_D(); + void XRA_A_E(); + void XRA_A_H(); + void XRA_A_L(); + void ORA_A_V(); + void ORA_A_B(); + void ORA_A_C(); + void ORA_A_D(); + void ORA_A_E(); + void ORA_A_H(); + void ORA_A_L(); + void ADDNC_A_V(); + void ADDNC_A_B(); + void ADDNC_A_C(); + void ADDNC_A_D(); + void ADDNC_A_E(); + void ADDNC_A_H(); + void ADDNC_A_L(); + void GTA_A_V(); + void GTA_A_B(); + void GTA_A_C(); + void GTA_A_D(); + void GTA_A_E(); + void GTA_A_H(); + void GTA_A_L(); + void SUBNB_A_V(); + void SUBNB_A_B(); + void SUBNB_A_C(); + void SUBNB_A_D(); + void SUBNB_A_E(); + void SUBNB_A_H(); + void SUBNB_A_L(); + void LTA_A_V(); + void LTA_A_B(); + void LTA_A_C(); + void LTA_A_D(); + void LTA_A_E(); + void LTA_A_H(); + void LTA_A_L(); + void ADD_A_V(); + void ADD_A_B(); + void ADD_A_C(); + void ADD_A_D(); + void ADD_A_E(); + void ADD_A_H(); + void ADD_A_L(); + void ONA_A_V(); + void ONA_A_A(); + void ONA_A_B(); + void ONA_A_C(); + void ONA_A_D(); + void ONA_A_E(); + void ONA_A_H(); + void ONA_A_L(); + void ADC_A_V(); + void ADC_A_B(); + void ADC_A_C(); + void ADC_A_D(); + void ADC_A_E(); + void ADC_A_H(); + void ADC_A_L(); + void OFFA_A_V(); + void OFFA_A_A(); + void OFFA_A_B(); + void OFFA_A_C(); + void OFFA_A_D(); + void OFFA_A_E(); + void OFFA_A_H(); + void OFFA_A_L(); + void SUB_A_V(); + void SUB_A_B(); + void SUB_A_C(); + void SUB_A_D(); + void SUB_A_E(); + void SUB_A_H(); + void SUB_A_L(); + void NEA_A_V(); + void NEA_A_B(); + void NEA_A_C(); + void NEA_A_D(); + void NEA_A_E(); + void NEA_A_H(); + void NEA_A_L(); + void SBB_A_V(); + void SBB_A_B(); + void SBB_A_C(); + void SBB_A_D(); + void SBB_A_E(); + void SBB_A_H(); + void SBB_A_L(); + void EQA_A_V(); + void EQA_A_B(); + void EQA_A_C(); + void EQA_A_D(); + void EQA_A_E(); + void EQA_A_H(); + void EQA_A_L(); + void MVI_PA_xx(); + void MVI_PB_xx(); + void MVI_PC_xx(); + void MVI_PD_xx(); + void MVI_PF_xx(); + void MVI_MKH_xx(); + void MVI_MKL_xx(); + void ANI_PA_xx(); + void ANI_PB_xx(); + void ANI_PC_xx(); + void ANI_PD_xx(); + void ANI_PF_xx(); + void ANI_MKH_xx(); + void ANI_MKL_xx(); + void XRI_PA_xx(); + void XRI_PB_xx(); + void XRI_PC_xx(); + void XRI_PD_xx(); + void XRI_PF_xx(); + void XRI_MKH_xx(); + void XRI_MKL_xx(); + void ORI_PA_xx(); + void ORI_PB_xx(); + void ORI_PC_xx(); + void ORI_PD_xx(); + void ORI_PF_xx(); + void ORI_MKH_xx(); + void ORI_MKL_xx(); + void ADINC_PA_xx(); + void ADINC_PB_xx(); + void ADINC_PC_xx(); + void ADINC_PD_xx(); + void ADINC_PF_xx(); + void ADINC_MKH_xx(); + void ADINC_MKL_xx(); + void GTI_PA_xx(); + void GTI_PB_xx(); + void GTI_PC_xx(); + void GTI_PD_xx(); + void GTI_PF_xx(); + void GTI_MKH_xx(); + void GTI_MKL_xx(); + void SUINB_PA_xx(); + void SUINB_PB_xx(); + void SUINB_PC_xx(); + void SUINB_PD_xx(); + void SUINB_PF_xx(); + void SUINB_MKH_xx(); + void SUINB_MKL_xx(); + void LTI_PA_xx(); + void LTI_PB_xx(); + void LTI_PC_xx(); + void LTI_PD_xx(); + void LTI_PF_xx(); + void LTI_MKH_xx(); + void LTI_MKL_xx(); + void ADI_PA_xx(); + void ADI_PB_xx(); + void ADI_PC_xx(); + void ADI_PD_xx(); + void ADI_PF_xx(); + void ADI_MKH_xx(); + void ADI_MKL_xx(); + void ONI_PA_xx(); + void ONI_PB_xx(); + void ONI_PC_xx(); + void ONI_PD_xx(); + void ONI_PF_xx(); + void ONI_MKH_xx(); + void ONI_MKL_xx(); + void ACI_PA_xx(); + void ACI_PB_xx(); + void ACI_PC_xx(); + void ACI_PD_xx(); + void ACI_PF_xx(); + void ACI_MKH_xx(); + void ACI_MKL_xx(); + void OFFI_PA_xx(); + void OFFI_PB_xx(); + void OFFI_PC_xx(); + void OFFI_PD_xx(); + void OFFI_PF_xx(); + void OFFI_MKH_xx(); + void OFFI_MKL_xx(); + void SUI_PA_xx(); + void SUI_PB_xx(); + void SUI_PC_xx(); + void SUI_PD_xx(); + void SUI_PF_xx(); + void SUI_MKH_xx(); + void SUI_MKL_xx(); + void NEI_PA_xx(); + void NEI_PB_xx(); + void NEI_PC_xx(); + void NEI_PD_xx(); + void NEI_PF_xx(); + void NEI_MKH_xx(); + void NEI_MKL_xx(); + void SBI_PA_xx(); + void SBI_PB_xx(); + void SBI_PC_xx(); + void SBI_PD_xx(); + void SBI_PF_xx(); + void SBI_MKH_xx(); + void SBI_MKL_xx(); + void EQI_PA_xx(); + void EQI_PB_xx(); + void EQI_PC_xx(); + void EQI_PD_xx(); + void EQI_PF_xx(); + void EQI_MKH_xx(); + void EQI_MKL_xx(); + void MVI_ANM_xx(); + void MVI_SMH_xx(); + void MVI_EOM_xx(); + void MVI_TMM_xx(); + void ANI_ANM_xx(); + void ANI_SMH_xx(); + void ANI_EOM_xx(); + void ANI_TMM_xx(); + void XRI_ANM_xx(); + void XRI_SMH_xx(); + void XRI_EOM_xx(); + void XRI_TMM_xx(); + void ORI_ANM_xx(); + void ORI_SMH_xx(); + void ORI_EOM_xx(); + void ORI_TMM_xx(); + void ADINC_ANM_xx(); + void ADINC_SMH_xx(); + void ADINC_EOM_xx(); + void ADINC_TMM_xx(); + void GTI_ANM_xx(); + void GTI_SMH_xx(); + void GTI_EOM_xx(); + void GTI_TMM_xx(); + void SUINB_ANM_xx(); + void SUINB_SMH_xx(); + void SUINB_EOM_xx(); + void SUINB_TMM_xx(); + void LTI_ANM_xx(); + void LTI_SMH_xx(); + void LTI_EOM_xx(); + void LTI_TMM_xx(); + void ADI_ANM_xx(); + void ADI_SMH_xx(); + void ADI_EOM_xx(); + void ADI_TMM_xx(); + void ONI_ANM_xx(); + void ONI_SMH_xx(); + void ONI_EOM_xx(); + void ONI_TMM_xx(); + void ACI_ANM_xx(); + void ACI_SMH_xx(); + void ACI_EOM_xx(); + void ACI_TMM_xx(); + void OFFI_ANM_xx(); + void OFFI_SMH_xx(); + void OFFI_EOM_xx(); + void OFFI_TMM_xx(); + void SUI_ANM_xx(); + void SUI_SMH_xx(); + void SUI_EOM_xx(); + void SUI_TMM_xx(); + void NEI_ANM_xx(); + void NEI_SMH_xx(); + void NEI_EOM_xx(); + void NEI_TMM_xx(); + void SBI_ANM_xx(); + void SBI_SMH_xx(); + void SBI_EOM_xx(); + void SBI_TMM_xx(); + void EQI_ANM_xx(); + void EQI_SMH_xx(); + void EQI_EOM_xx(); + void EQI_TMM_xx(); + void SSPD_w(); + void LSPD_w(); + void SBCD_w(); + void LBCD_w(); + void SDED_w(); + void LDED_w(); + void SHLD_w(); + void LHLD_w(); + void EADD_EA_A(); + void EADD_EA_B(); + void EADD_EA_C(); + void ESUB_EA_A(); + void ESUB_EA_B(); + void ESUB_EA_C(); + void MOV_V_w(); + void MOV_A_w(); + void MOV_B_w(); + void MOV_C_w(); + void MOV_D_w(); + void MOV_E_w(); + void MOV_H_w(); + void MOV_L_w(); + void MOV_w_V(); + void MOV_w_A(); + void MOV_w_B(); + void MOV_w_C(); + void MOV_w_D(); + void MOV_w_E(); + void MOV_w_H(); + void MOV_w_L(); + void ANAX_B(); + void ANAX_D(); + void ANAX_H(); + void ANAX_Dp(); + void ANAX_Hp(); + void ANAX_Dm(); + void ANAX_Hm(); + void XRAX_B(); + void XRAX_D(); + void XRAX_H(); + void XRAX_Dp(); + void XRAX_Hp(); + void XRAX_Dm(); + void XRAX_Hm(); + void ORAX_B(); + void ORAX_D(); + void ORAX_H(); + void ORAX_Dp(); + void ORAX_Hp(); + void ORAX_Dm(); + void ORAX_Hm(); + void ADDNCX_B(); + void ADDNCX_D(); + void ADDNCX_H(); + void ADDNCX_Dp(); + void ADDNCX_Hp(); + void ADDNCX_Dm(); + void ADDNCX_Hm(); + void GTAX_B(); + void GTAX_D(); + void GTAX_H(); + void GTAX_Dp(); + void GTAX_Hp(); + void GTAX_Dm(); + void GTAX_Hm(); + void SUBNBX_B(); + void SUBNBX_D(); + void SUBNBX_H(); + void SUBNBX_Dp(); + void SUBNBX_Hp(); + void SUBNBX_Dm(); + void SUBNBX_Hm(); + void LTAX_B(); + void LTAX_D(); + void LTAX_H(); + void LTAX_Dp(); + void LTAX_Hp(); + void LTAX_Dm(); + void LTAX_Hm(); + void ADDX_B(); + void ADDX_D(); + void ADDX_H(); + void ADDX_Dp(); + void ADDX_Hp(); + void ADDX_Dm(); + void ADDX_Hm(); + void ONAX_B(); + void ONAX_D(); + void ONAX_H(); + void ONAX_Dp(); + void ONAX_Hp(); + void ONAX_Dm(); + void ONAX_Hm(); + void ADCX_B(); + void ADCX_D(); + void ADCX_H(); + void ADCX_Dp(); + void ADCX_Hp(); + void ADCX_Dm(); + void ADCX_Hm(); + void OFFAX_B(); + void OFFAX_D(); + void OFFAX_H(); + void OFFAX_Dp(); + void OFFAX_Hp(); + void OFFAX_Dm(); + void OFFAX_Hm(); + void SUBX_B(); + void SUBX_D(); + void SUBX_H(); + void SUBX_Dp(); + void SUBX_Hp(); + void SUBX_Dm(); + void SUBX_Hm(); + void NEAX_B(); + void NEAX_D(); + void NEAX_H(); + void NEAX_Dp(); + void NEAX_Hp(); + void NEAX_Dm(); + void NEAX_Hm(); + void SBBX_B(); + void SBBX_D(); + void SBBX_H(); + void SBBX_Dp(); + void SBBX_Hp(); + void SBBX_Dm(); + void SBBX_Hm(); + void EQAX_B(); + void EQAX_D(); + void EQAX_H(); + void EQAX_Dp(); + void EQAX_Hp(); + void EQAX_Dm(); + void EQAX_Hm(); + void ANI_V_xx(); + void ANI_A_xx(); + void ANI_B_xx(); + void ANI_C_xx(); + void ANI_D_xx(); + void ANI_E_xx(); + void ANI_H_xx(); + void ANI_L_xx(); + void XRI_V_xx(); + void XRI_A_xx(); + void XRI_B_xx(); + void XRI_C_xx(); + void XRI_D_xx(); + void XRI_E_xx(); + void XRI_H_xx(); + void XRI_L_xx(); + void ORI_V_xx(); + void ORI_A_xx(); + void ORI_B_xx(); + void ORI_C_xx(); + void ORI_D_xx(); + void ORI_E_xx(); + void ORI_H_xx(); + void ORI_L_xx(); + void ADINC_V_xx(); + void ADINC_A_xx(); + void ADINC_B_xx(); + void ADINC_C_xx(); + void ADINC_D_xx(); + void ADINC_E_xx(); + void ADINC_H_xx(); + void ADINC_L_xx(); + void GTI_V_xx(); + void GTI_A_xx(); + void GTI_B_xx(); + void GTI_C_xx(); + void GTI_D_xx(); + void GTI_E_xx(); + void GTI_H_xx(); + void GTI_L_xx(); + void SUINB_V_xx(); + void SUINB_A_xx(); + void SUINB_B_xx(); + void SUINB_C_xx(); + void SUINB_D_xx(); + void SUINB_E_xx(); + void SUINB_H_xx(); + void SUINB_L_xx(); + void LTI_V_xx(); + void LTI_A_xx(); + void LTI_B_xx(); + void LTI_C_xx(); + void LTI_D_xx(); + void LTI_E_xx(); + void LTI_H_xx(); + void LTI_L_xx(); + void ADI_V_xx(); + void ADI_A_xx(); + void ADI_B_xx(); + void ADI_C_xx(); + void ADI_D_xx(); + void ADI_E_xx(); + void ADI_H_xx(); + void ADI_L_xx(); + void ONI_V_xx(); + void ONI_A_xx(); + void ONI_B_xx(); + void ONI_C_xx(); + void ONI_D_xx(); + void ONI_E_xx(); + void ONI_H_xx(); + void ONI_L_xx(); + void ACI_V_xx(); + void ACI_A_xx(); + void ACI_B_xx(); + void ACI_C_xx(); + void ACI_D_xx(); + void ACI_E_xx(); + void ACI_H_xx(); + void ACI_L_xx(); + void OFFI_V_xx(); + void OFFI_A_xx(); + void OFFI_B_xx(); + void OFFI_C_xx(); + void OFFI_D_xx(); + void OFFI_E_xx(); + void OFFI_H_xx(); + void OFFI_L_xx(); + void SUI_V_xx(); + void SUI_A_xx(); + void SUI_B_xx(); + void SUI_C_xx(); + void SUI_D_xx(); + void SUI_E_xx(); + void SUI_H_xx(); + void SUI_L_xx(); + void NEI_V_xx(); + void NEI_A_xx(); + void NEI_B_xx(); + void NEI_C_xx(); + void NEI_D_xx(); + void NEI_E_xx(); + void NEI_H_xx(); + void NEI_L_xx(); + void SBI_V_xx(); + void SBI_A_xx(); + void SBI_B_xx(); + void SBI_C_xx(); + void SBI_D_xx(); + void SBI_E_xx(); + void SBI_H_xx(); + void SBI_L_xx(); + void EQI_V_xx(); + void EQI_A_xx(); + void EQI_B_xx(); + void EQI_C_xx(); + void EQI_D_xx(); + void EQI_E_xx(); + void EQI_H_xx(); + void EQI_L_xx(); + void ANAW_wa(); + void DAN_EA_BC(); + void DAN_EA_DE(); + void DAN_EA_HL(); + void XRAW_wa(); + void DXR_EA_BC(); + void DXR_EA_DE(); + void DXR_EA_HL(); + void ORAW_wa(); + void DOR_EA_BC(); + void DOR_EA_DE(); + void DOR_EA_HL(); + void ADDNCW_wa(); + void DADDNC_EA_BC(); + void DADDNC_EA_DE(); + void DADDNC_EA_HL(); + void GTAW_wa(); + void DGT_EA_BC(); + void DGT_EA_DE(); + void DGT_EA_HL(); + void SUBNBW_wa(); + void DSUBNB_EA_BC(); + void DSUBNB_EA_DE(); + void DSUBNB_EA_HL(); + void LTAW_wa(); + void DLT_EA_BC(); + void DLT_EA_DE(); + void DLT_EA_HL(); + void ADDW_wa(); + void DADD_EA_BC(); + void DADD_EA_DE(); + void DADD_EA_HL(); + void ONAW_wa(); + void DON_EA_BC(); + void DON_EA_DE(); + void DON_EA_HL(); + void ADCW_wa(); + void DADC_EA_BC(); + void DADC_EA_DE(); + void DADC_EA_HL(); + void OFFAW_wa(); + void DOFF_EA_BC(); + void DOFF_EA_DE(); + void DOFF_EA_HL(); + void SUBW_wa(); + void DSUB_EA_BC(); + void DSUB_EA_DE(); + void DSUB_EA_HL(); + void NEAW_wa(); + void DNE_EA_BC(); + void DNE_EA_DE(); + void DNE_EA_HL(); + void SBBW_wa(); + void DSBB_EA_BC(); + void DSBB_EA_DE(); + void DSBB_EA_HL(); + void EQAW_wa(); + void DEQ_EA_BC(); + void DEQ_EA_DE(); + void DEQ_EA_HL(); + void NOP(); + void LDAW_wa(); + void INX_SP(); + void DCX_SP(); + void LXI_S_w(); + void ANIW_wa_xx(); + void MOV_A_EAH(); + void MOV_A_EAL(); + void MOV_A_B(); + void MOV_A_C(); + void MOV_A_D(); + void MOV_A_E(); + void MOV_A_H(); + void MOV_A_L(); + void EXA(); + void EXX(); + void EXR(); + void INX_BC(); + void DCX_BC(); + void LXI_B_w(); + void ORIW_wa_xx(); + void MOV_EAH_A(); + void MOV_EAL_A(); + void MOV_B_A(); + void MOV_C_A(); + void MOV_D_A(); + void MOV_E_A(); + void MOV_H_A(); + void MOV_L_A(); + void INRW_wa(); + void JB(); + void INX_DE(); + void DCX_DE(); + void LXI_D_w(); + void GTIW_wa_xx(); + void LDAX_B(); + void LDAX_D(); + void LDAX_H(); + void LDAX_Dp(); + void LDAX_Hp(); + void LDAX_Dm(); + void LDAX_Hm(); + void DCRW_wa(); + void BLOCK(); + void INX_HL(); + void DCX_HL(); + void LXI_H_w(); + void LTIW_wa_xx(); + void STAX_B(); + void STAX_D(); + void STAX_H(); + void STAX_Dp(); + void STAX_Hp(); + void STAX_Dm(); + void STAX_Hm(); + void CALL_w(); + void INR_A(); + void INR_B(); + void INR_C(); + void LXI_EA_s(); + void ONIW_wa_xx(); + void PRE_48(); + void MVIX_BC_xx(); + void MVIX_DE_xx(); + void MVIX_HL_xx(); + void PRE_4C(); + void PRE_4D(); + void JRE(); + void EXH(); + void DCR_A(); + void DCR_B(); + void DCR_C(); + void JMP_w(); + void OFFIW_wa_xx(); + void BIT_0_wa(); + void BIT_1_wa(); + void BIT_2_wa(); + void BIT_3_wa(); + void BIT_4_wa(); + void BIT_5_wa(); + void BIT_6_wa(); + void BIT_7_wa(); + void SKN_bit(); + void SETB(); + void CLR(); + void SK_bit(); + void PRE_60(); + void DAA(); + void RETI(); + void STAW_wa(); + void PRE_64(); + void NEIW_wa_xx(); + void MVI_V_xx(); + void MVI_A_xx(); + void MVI_B_xx(); + void MVI_C_xx(); + void MVI_D_xx(); + void MVI_E_xx(); + void MVI_H_xx(); + void MVI_L_xx(); + void PRE_70(); + void MVIW_wa_xx(); + void SOFTI(); + void PRE_74(); + void EQIW_wa_xx(); + void CALF(); + void CALT(); + void POP_VA(); + void POP_BC(); + void POP_DE(); + void POP_HL(); + void POP_EA(); + void DMOV_EA_BC(); + void DMOV_EA_DE(); + void DMOV_EA_HL(); + void INX_EA(); + void DCX_EA(); + void EI(); + void LDAX_D_xx(); + void LDAX_H_A(); + void LDAX_H_B(); + void LDAX_H_EA(); + void LDAX_H_xx(); + void PUSH_VA(); + void PUSH_BC(); + void PUSH_DE(); + void PUSH_HL(); + void PUSH_EA(); + void DMOV_BC_EA(); + void DMOV_DE_EA(); + void DMOV_HL_EA(); + void RET(); + void RETS(); + void DI(); + void STAX_D_xx(); + void STAX_H_A(); + void STAX_H_B(); + void STAX_H_EA(); + void STAX_H_xx(); + void JR(); + void CALT_7801(); + void DCR_A_7801(); + void DCR_B_7801(); + void DCR_C_7801(); + void DCRW_wa_7801(); + void INR_A_7801(); + void INR_B_7801(); + void INR_C_7801(); + void INRW_wa_7801(); + void IN(); + void OUT(); + void MOV_A_S(); + void MOV_S_A(); + void PEN(); + void PER(); + void PEX(); + void SIO(); + void SKIT_F0(); + void SKNIT_F0(); + void STM(); + void STM_7801(); + void MOV_MC_A_7801(); + void base_device_start(); +}; + + +class upd7807_device : public upd7810_device +{ +public: + // construction/destruction + upd7807_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); +}; + + +class upd7801_device : public upd7810_device +{ +public: + // construction/destruction + upd7801_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + virtual void device_reset(); + virtual void execute_set_input(int inputnum, int state); + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void handle_timers(int cycles); + virtual void upd7810_take_irq(); +}; + + +class upd78c05_device : public upd7810_device +{ +public: + // construction/destruction + upd78c05_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + upd78c05_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); + +protected: + virtual void device_start(); + virtual void device_reset(); + virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 4 - 1) / 4; } + virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 4); } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + virtual void handle_timers(int cycles); +}; + + +class upd78c06_device : public upd78c05_device +{ +public: + // construction/destruction + upd78c06_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +extern const device_type UPD7810; +extern const device_type UPD7807; +extern const device_type UPD7801; +extern const device_type UPD78C05; +extern const device_type UPD78C06; + #endif /* __UPD7810_H__ */ |