diff options
author | Ville Linde <villelin@mamedev.org> | 2014-05-06 16:46:08 +0000 |
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committer | Ville Linde <villelin@mamedev.org> | 2014-05-06 16:46:08 +0000 |
commit | efcbcca87c13f025623f3ae0df494058a8f93610 (patch) | |
tree | 606f15bc8c178717253d0d85a467ef444e9ce9af /src/emu/cpu/sharc/sharc.c | |
parent | fa7c52129a600cf4c00fe5338b4d6fa6a98506e4 (diff) |
sharc: DMA internal index registers are only 17 bits long. (nw)
Diffstat (limited to 'src/emu/cpu/sharc/sharc.c')
-rw-r--r-- | src/emu/cpu/sharc/sharc.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/emu/cpu/sharc/sharc.c b/src/emu/cpu/sharc/sharc.c index 676dca6cb39..6eace66bc84 100644 --- a/src/emu/cpu/sharc/sharc.c +++ b/src/emu/cpu/sharc/sharc.c @@ -281,17 +281,22 @@ void adsp21062_device::external_iop_write(UINT32 address, UINT32 data) void adsp21062_device::external_dma_write(UINT32 address, UINT64 data) { + /* + All addresses in the 17-bit index registers are offset by 0x0002 0000, the + first internal RAM location, before they are used by the DMA controller. + */ + switch ((m_dma[6].control >> 6) & 0x3) { case 2: // 16/48 packing { int shift = address % 3; - UINT64 r = pm_read48(m_dma[6].int_index); + UINT64 r = pm_read48((m_dma[6].int_index & 0x1ffff) | 0x20000); r &= ~((UINT64)(0xffff) << (shift*16)); r |= (data & 0xffff) << (shift*16); - pm_write48(m_dma[6].int_index, r); + pm_write48((m_dma[6].int_index & 0x1ffff) | 0x20000, r); if (shift == 2) { |