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author Wilbert Pol <wilbert@jdg.info>2014-01-26 22:07:42 +0000
committer Wilbert Pol <wilbert@jdg.info>2014-01-26 22:07:42 +0000
commite5a80b0bdbdf60230239e0349680715686807632 (patch)
tree521cd83773160f34a70caade3a681c7865826747 /src/emu/cpu/sharc/sharc.c
parent91a1d90bb69e8f9032471082cc2a7ddbefbf9993 (diff)
sharc.c: Modernized cpu core. [Wilbert Pol]
Diffstat (limited to 'src/emu/cpu/sharc/sharc.c')
-rw-r--r--src/emu/cpu/sharc/sharc.c1345
1 files changed, 497 insertions, 848 deletions
diff --git a/src/emu/cpu/sharc/sharc.c b/src/emu/cpu/sharc/sharc.c
index defd40778bf..3e68d1ce186 100644
--- a/src/emu/cpu/sharc/sharc.c
+++ b/src/emu/cpu/sharc/sharc.c
@@ -7,7 +7,6 @@
#include "debugger.h"
#include "sharc.h"
-CPU_DISASSEMBLE( sharc );
enum
{
@@ -39,225 +38,92 @@ enum
SHARC_B12, SHARC_B13, SHARC_B14, SHARC_B15,
};
-struct SHARC_DAG
-{
- UINT32 i[8];
- UINT32 m[8];
- UINT32 b[8];
- UINT32 l[8];
-};
-
-union SHARC_REG
-{
- INT32 r;
- float f;
-};
-
-struct DMA_REGS
-{
- UINT32 control;
- UINT32 int_index;
- UINT32 int_modifier;
- UINT32 int_count;
- UINT32 chain_ptr;
- UINT32 gen_purpose;
- UINT32 ext_index;
- UINT32 ext_modifier;
- UINT32 ext_count;
-};
-
-struct LADDR
-{
- UINT32 addr;
- UINT32 code;
- UINT32 loop_type;
-};
-
-struct DMA_OP
-{
- UINT32 src;
- UINT32 dst;
- UINT32 chain_ptr;
- INT32 src_modifier;
- INT32 dst_modifier;
- INT32 src_count;
- INT32 dst_count;
- INT32 pmode;
- INT32 chained_direction;
- emu_timer *timer;
- bool active;
-};
-
-struct SHARC_REGS
-{
- UINT32 pc;
- SHARC_REG r[16];
- SHARC_REG reg_alt[16];
- UINT64 mrf;
- UINT64 mrb;
-
- UINT32 pcstack[32];
- UINT32 lcstack[6];
- UINT32 lastack[6];
- UINT32 lstkp;
-
- UINT32 faddr;
- UINT32 daddr;
- UINT32 pcstk;
- UINT32 pcstkp;
- LADDR laddr;
- UINT32 curlcntr;
- UINT32 lcntr;
-
- /* Data Address Generator (DAG) */
- SHARC_DAG dag1; // (DM bus)
- SHARC_DAG dag2; // (PM bus)
- SHARC_DAG dag1_alt;
- SHARC_DAG dag2_alt;
-
- DMA_REGS dma[12];
-
- /* System registers */
- UINT32 mode1;
- UINT32 mode2;
- UINT32 astat;
- UINT32 stky;
- UINT32 irptl;
- UINT32 imask;
- UINT32 imaskp;
- UINT32 ustat1;
- UINT32 ustat2;
-
- UINT32 flag[4];
-
- UINT32 syscon;
- UINT32 sysstat;
-
- struct
- {
- UINT32 mode1;
- UINT32 astat;
- } status_stack[5];
- INT32 status_stkp;
-
- UINT64 px;
-
- UINT16 *internal_ram;
- UINT16 *internal_ram_block0, *internal_ram_block1;
-
- device_irq_acknowledge_callback irq_callback;
- legacy_cpu_device *device;
- address_space *program;
- address_space *data;
- void (*opcode_handler)(SHARC_REGS *cpustate);
- int icount;
- UINT64 opcode;
-
- UINT32 nfaddr;
-
- INT32 idle;
- INT32 irq_active;
- INT32 active_irq_num;
-
- SHARC_BOOT_MODE boot_mode;
-
- DMA_OP dma_op[12];
- UINT32 dma_status;
-
- INT32 interrupt_active;
-
- UINT32 iop_delayed_reg;
- UINT32 iop_delayed_data;
- emu_timer *delayed_iop_timer;
- UINT32 delay_slot1, delay_slot2;
+#define ROPCODE(pc) ((UINT64)(m_internal_ram[((pc-0x20000) * 3) + 0]) << 32) | \
+ ((UINT64)(m_internal_ram[((pc-0x20000) * 3) + 1]) << 16) | \
+ ((UINT64)(m_internal_ram[((pc-0x20000) * 3) + 2]) << 0)
- INT32 systemreg_latency_cycles;
- INT32 systemreg_latency_reg;
- UINT32 systemreg_latency_data;
- UINT32 systemreg_previous_data;
-
- UINT32 astat_old;
- UINT32 astat_old_old;
- UINT32 astat_old_old_old;
-};
+const device_type ADSP21062 = &device_creator<adsp21062_device>;
-static void sharc_dma_exec(SHARC_REGS *cpustate, int channel);
-static void check_interrupts(SHARC_REGS *cpustate);
-static void (* sharc_op[512])(SHARC_REGS *cpustate);
+// This is just used to stop the debugger from complaining about executing from I/O space
+static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 64, adsp21062_device )
+ AM_RANGE(0x20000, 0x7ffff) AM_RAM
+ADDRESS_MAP_END
+adsp21062_device::adsp21062_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : cpu_device(mconfig, ADSP21062, "ADSP21062", tag, owner, clock, "adsp21062", __FILE__)
+ , m_program_config("program", ENDIANNESS_LITTLE, 64, 24, -3, ADDRESS_MAP_NAME(internal_pgm))
+ , m_data_config("data", ENDIANNESS_LITTLE, 32, 32, -2)
+ , m_boot_mode(BOOT_MODE_HOST)
+{
+}
-#define ROPCODE(pc) ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 0]) << 32) | \
- ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 1]) << 16) | \
- ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 2]) << 0)
-INLINE SHARC_REGS *get_safe_token(device_t *device)
+offs_t adsp21062_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
- assert(device != NULL);
- assert(device->type() == ADSP21062);
- return (SHARC_REGS *)downcast<legacy_cpu_device *>(device)->token();
+ extern CPU_DISASSEMBLE( sharc );
+ return CPU_DISASSEMBLE_NAME(sharc)(this, buffer, pc, oprom, opram, options);
}
-INLINE void CHANGE_PC(SHARC_REGS *cpustate, UINT32 newpc)
+
+void adsp21062_device::CHANGE_PC(UINT32 newpc)
{
- cpustate->pc = newpc;
- cpustate->daddr = newpc;
- cpustate->faddr = newpc+1;
- cpustate->nfaddr = newpc+2;
+ m_pc = newpc;
+ m_daddr = newpc;
+ m_faddr = newpc+1;
+ m_nfaddr = newpc+2;
}
-INLINE void CHANGE_PC_DELAYED(SHARC_REGS *cpustate, UINT32 newpc)
+void adsp21062_device::CHANGE_PC_DELAYED(UINT32 newpc)
{
- cpustate->nfaddr = newpc;
+ m_nfaddr = newpc;
- cpustate->delay_slot1 = cpustate->pc;
- cpustate->delay_slot2 = cpustate->daddr;
+ m_delay_slot1 = m_pc;
+ m_delay_slot2 = m_daddr;
}
-static TIMER_CALLBACK(sharc_iop_delayed_write_callback)
+TIMER_CALLBACK_MEMBER(adsp21062_device::sharc_iop_delayed_write_callback)
{
- SHARC_REGS *cpustate = (SHARC_REGS *)ptr;
-
- switch (cpustate->iop_delayed_reg)
+ switch (m_iop_delayed_reg)
{
case 0x1c:
{
- if (cpustate->iop_delayed_data & 0x1)
+ if (m_iop_delayed_data & 0x1)
{
- sharc_dma_exec(cpustate, 6);
+ sharc_dma_exec(6);
}
break;
}
case 0x1d:
{
- if (cpustate->iop_delayed_data & 0x1)
+ if (m_iop_delayed_data & 0x1)
{
- sharc_dma_exec(cpustate, 7);
+ sharc_dma_exec(7);
}
break;
}
- default: fatalerror("SHARC: sharc_iop_delayed_write: unknown IOP register %02X\n", cpustate->iop_delayed_reg);
+ default: fatalerror("SHARC: sharc_iop_delayed_write: unknown IOP register %02X\n", m_iop_delayed_reg);
}
- cpustate->delayed_iop_timer->adjust(attotime::never, 0);
+ m_delayed_iop_timer->adjust(attotime::never, 0);
}
-static void sharc_iop_delayed_w(SHARC_REGS *cpustate, UINT32 reg, UINT32 data, int cycles)
+void adsp21062_device::sharc_iop_delayed_w(UINT32 reg, UINT32 data, int cycles)
{
- cpustate->iop_delayed_reg = reg;
- cpustate->iop_delayed_data = data;
+ m_iop_delayed_reg = reg;
+ m_iop_delayed_data = data;
- cpustate->delayed_iop_timer->adjust(cpustate->device->cycles_to_attotime(cycles), 0);
+ m_delayed_iop_timer->adjust(cycles_to_attotime(cycles), 0);
}
/* IOP registers */
-static UINT32 sharc_iop_r(SHARC_REGS *cpustate, UINT32 address)
+UINT32 adsp21062_device::sharc_iop_r(UINT32 address)
{
switch (address)
{
@@ -265,14 +131,14 @@ static UINT32 sharc_iop_r(SHARC_REGS *cpustate, UINT32 address)
case 0x37: // DMA status
{
- return cpustate->dma_status;
+ return m_dma_status;
}
- default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X\n", address, cpustate->pc);
+ default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X\n", address, m_pc);
}
return 0;
}
-static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data)
+void adsp21062_device::sharc_iop_w(UINT32 address, UINT32 data)
{
switch (address)
{
@@ -291,40 +157,40 @@ static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data)
// DMA 6
case 0x1c:
{
- cpustate->dma[6].control = data;
- sharc_iop_delayed_w(cpustate, 0x1c, data, 1);
+ m_dma[6].control = data;
+ sharc_iop_delayed_w(0x1c, data, 1);
break;
}
case 0x20: break;
- case 0x40: cpustate->dma[6].int_index = data; return;
- case 0x41: cpustate->dma[6].int_modifier = data; return;
- case 0x42: cpustate->dma[6].int_count = data; return;
- case 0x43: cpustate->dma[6].chain_ptr = data; return;
- case 0x44: cpustate->dma[6].gen_purpose = data; return;
- case 0x45: cpustate->dma[6].ext_index = data; return;
- case 0x46: cpustate->dma[6].ext_modifier = data; return;
- case 0x47: cpustate->dma[6].ext_count = data; return;
+ case 0x40: m_dma[6].int_index = data; return;
+ case 0x41: m_dma[6].int_modifier = data; return;
+ case 0x42: m_dma[6].int_count = data; return;
+ case 0x43: m_dma[6].chain_ptr = data; return;
+ case 0x44: m_dma[6].gen_purpose = data; return;
+ case 0x45: m_dma[6].ext_index = data; return;
+ case 0x46: m_dma[6].ext_modifier = data; return;
+ case 0x47: m_dma[6].ext_count = data; return;
// DMA 7
case 0x1d:
{
- cpustate->dma[7].control = data;
- sharc_iop_delayed_w(cpustate, 0x1d, data, 30);
+ m_dma[7].control = data;
+ sharc_iop_delayed_w(0x1d, data, 30);
break;
}
- case 0x48: cpustate->dma[7].int_index = data; return;
- case 0x49: cpustate->dma[7].int_modifier = data; return;
- case 0x4a: cpustate->dma[7].int_count = data; return;
- case 0x4b: cpustate->dma[7].chain_ptr = data; return;
- case 0x4c: cpustate->dma[7].gen_purpose = data; return;
- case 0x4d: cpustate->dma[7].ext_index = data; return;
- case 0x4e: cpustate->dma[7].ext_modifier = data; return;
- case 0x4f: cpustate->dma[7].ext_count = data; return;
+ case 0x48: m_dma[7].int_index = data; return;
+ case 0x49: m_dma[7].int_modifier = data; return;
+ case 0x4a: m_dma[7].int_count = data; return;
+ case 0x4b: m_dma[7].chain_ptr = data; return;
+ case 0x4c: m_dma[7].gen_purpose = data; return;
+ case 0x4d: m_dma[7].ext_index = data; return;
+ case 0x4e: m_dma[7].ext_modifier = data; return;
+ case 0x4f: m_dma[7].ext_count = data; return;
- default: fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X\n", address, data, cpustate->pc);
+ default: fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X\n", address, data, m_pc);
}
}
@@ -336,14 +202,14 @@ static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data)
-static void build_opcode_table(void)
+void adsp21062_device::build_opcode_table()
{
int i, j;
- int num_ops = sizeof(sharc_opcode_table) / sizeof(SHARC_OP);
+ int num_ops = sizeof(s_sharc_opcode_table) / sizeof(SHARC_OP);
for (i=0; i < 512; i++)
{
- sharc_op[i] = sharcop_unimplemented;
+ m_sharc_op[i] = &adsp21062_device::sharcop_unimplemented;
}
for (i=0; i < 512; i++)
@@ -352,15 +218,15 @@ static void build_opcode_table(void)
for (j=0; j < num_ops; j++)
{
- if ((sharc_opcode_table[j].op_mask & op) == sharc_opcode_table[j].op_bits)
+ if ((s_sharc_opcode_table[j].op_mask & op) == s_sharc_opcode_table[j].op_bits)
{
- if (sharc_op[i] != sharcop_unimplemented)
+ if (m_sharc_op[i] != &adsp21062_device::sharcop_unimplemented)
{
fatalerror("build_opcode_table: table already filled! (i=%04X, j=%d)\n", i, j);
}
else
{
- sharc_op[i] = sharc_opcode_table[j].handler;
+ m_sharc_op[i] = s_sharc_opcode_table[j].handler;
}
}
}
@@ -369,218 +235,397 @@ static void build_opcode_table(void)
/*****************************************************************************/
-void sharc_external_iop_write(device_t *device, UINT32 address, UINT32 data)
+void adsp21062_device::external_iop_write(UINT32 address, UINT32 data)
{
- SHARC_REGS *cpustate = get_safe_token(device);
if (address == 0x1c)
{
if (data != 0)
{
- cpustate->dma[6].control = data;
+ m_dma[6].control = data;
}
}
else
{
mame_printf_debug("SHARC IOP write %08X, %08X\n", address, data);
- sharc_iop_w(cpustate, address, data);
+ sharc_iop_w(address, data);
}
}
-void sharc_external_dma_write(device_t *device, UINT32 address, UINT64 data)
+void adsp21062_device::external_dma_write(UINT32 address, UINT64 data)
{
- SHARC_REGS *cpustate = get_safe_token(device);
- switch ((cpustate->dma[6].control >> 6) & 0x3)
+ switch ((m_dma[6].control >> 6) & 0x3)
{
case 2: // 16/48 packing
{
int shift = address % 3;
- UINT64 r = pm_read48(cpustate, cpustate->dma[6].int_index);
+ UINT64 r = pm_read48(m_dma[6].int_index);
r &= ~((UINT64)(0xffff) << (shift*16));
r |= (data & 0xffff) << (shift*16);
- pm_write48(cpustate, cpustate->dma[6].int_index, r);
+ pm_write48(m_dma[6].int_index, r);
if (shift == 2)
{
- cpustate->dma[6].int_index += cpustate->dma[6].int_modifier;
+ m_dma[6].int_index += m_dma[6].int_modifier;
}
break;
}
default:
{
- fatalerror("sharc_external_dma_write: unimplemented packing mode %d\n", (cpustate->dma[6].control >> 6) & 0x3);
+ fatalerror("sharc_external_dma_write: unimplemented packing mode %d\n", (m_dma[6].control >> 6) & 0x3);
}
}
}
-static CPU_INIT( sharc )
+void adsp21062_device::device_start()
{
- SHARC_REGS *cpustate = get_safe_token(device);
- const sharc_config *cfg = (const sharc_config *)device->static_config();
int saveindex;
- cpustate->boot_mode = cfg->boot_mode;
-
- cpustate->irq_callback = irqcallback;
- cpustate->device = device;
- cpustate->program = &device->space(AS_PROGRAM);
- cpustate->data = &device->space(AS_DATA);
+ m_program = &space(AS_PROGRAM);
+ m_data = &space(AS_DATA);
build_opcode_table();
- cpustate->internal_ram = auto_alloc_array(device->machine(), UINT16, 2 * 0x10000); // 2x 128KB
- cpustate->internal_ram_block0 = &cpustate->internal_ram[0];
- cpustate->internal_ram_block1 = &cpustate->internal_ram[0x20000/2];
+ m_internal_ram = auto_alloc_array(machine(), UINT16, 2 * 0x10000); // 2x 128KB
+ m_internal_ram_block0 = &m_internal_ram[0];
+ m_internal_ram_block1 = &m_internal_ram[0x20000/2];
- cpustate->delayed_iop_timer = device->machine().scheduler().timer_alloc(FUNC(sharc_iop_delayed_write_callback), cpustate);
+ m_delayed_iop_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(adsp21062_device::sharc_iop_delayed_write_callback), this));
for (int i=0; i < 12; i++)
{
- cpustate->dma_op[i].active = false;
- cpustate->dma_op[i].timer = device->machine().scheduler().timer_alloc(FUNC(sharc_dma_callback), cpustate);
+ m_dma_op[i].src = 0;
+ m_dma_op[i].dst = 0;
+ m_dma_op[i].chain_ptr = 0;
+ m_dma_op[i].src_modifier = 0;
+ m_dma_op[i].dst_modifier = 0;
+ m_dma_op[i].src_count = 0;
+ m_dma_op[i].dst_count = 0;
+ m_dma_op[i].pmode = 0;
+ m_dma_op[i].chained_direction = 0;
+ m_dma_op[i].active = false;
+ m_dma_op[i].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(adsp21062_device::sharc_dma_callback), this));
}
- device->save_item(NAME(cpustate->pc));
- device->save_pointer(NAME(&cpustate->r[0].r), ARRAY_LENGTH(cpustate->r));
- device->save_pointer(NAME(&cpustate->reg_alt[0].r), ARRAY_LENGTH(cpustate->reg_alt));
- device->save_item(NAME(cpustate->mrf));
- device->save_item(NAME(cpustate->mrb));
-
- device->save_item(NAME(cpustate->pcstack));
- device->save_item(NAME(cpustate->lcstack));
- device->save_item(NAME(cpustate->lastack));
- device->save_item(NAME(cpustate->lstkp));
-
- device->save_item(NAME(cpustate->faddr));
- device->save_item(NAME(cpustate->daddr));
- device->save_item(NAME(cpustate->pcstk));
- device->save_item(NAME(cpustate->pcstkp));
- device->save_item(NAME(cpustate->laddr.addr));
- device->save_item(NAME(cpustate->laddr.code));
- device->save_item(NAME(cpustate->laddr.loop_type));
- device->save_item(NAME(cpustate->curlcntr));
- device->save_item(NAME(cpustate->lcntr));
-
- device->save_item(NAME(cpustate->dag1.i));
- device->save_item(NAME(cpustate->dag1.m));
- device->save_item(NAME(cpustate->dag1.b));
- device->save_item(NAME(cpustate->dag1.l));
- device->save_item(NAME(cpustate->dag2.i));
- device->save_item(NAME(cpustate->dag2.m));
- device->save_item(NAME(cpustate->dag2.b));
- device->save_item(NAME(cpustate->dag2.l));
- device->save_item(NAME(cpustate->dag1_alt.i));
- device->save_item(NAME(cpustate->dag1_alt.m));
- device->save_item(NAME(cpustate->dag1_alt.b));
- device->save_item(NAME(cpustate->dag1_alt.l));
- device->save_item(NAME(cpustate->dag2_alt.i));
- device->save_item(NAME(cpustate->dag2_alt.m));
- device->save_item(NAME(cpustate->dag2_alt.b));
- device->save_item(NAME(cpustate->dag2_alt.l));
-
- for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->dma); saveindex++)
+ for (int i=0; i < 16; i++)
+ {
+ m_r[i].r = 0;
+ m_reg_alt[i].r = 0;
+ }
+ m_mrf = 0;
+ m_mrb = 0;
+ for (int i=0; i < 32; i++)
{
- device->save_item(NAME(cpustate->dma[saveindex].control), saveindex);
- device->save_item(NAME(cpustate->dma[saveindex].int_index), saveindex);
- device->save_item(NAME(cpustate->dma[saveindex].int_modifier), saveindex);
- device->save_item(NAME(cpustate->dma[saveindex].int_count), saveindex);
- device->save_item(NAME(cpustate->dma[saveindex].chain_ptr), saveindex);
- device->save_item(NAME(cpustate->dma[saveindex].gen_purpose), saveindex);
- device->save_item(NAME(cpustate->dma[saveindex].ext_index), saveindex);
- device->save_item(NAME(cpustate->dma[saveindex].ext_modifier), saveindex);
- device->save_item(NAME(cpustate->dma[saveindex].ext_count), saveindex);
+ m_pcstack[i] = 0;
+ }
+ for (int i=0; i < 6; i++)
+ {
+ m_lcstack[i] = 0;
+ m_lastack[i] = 0;
+ }
+ m_lstkp = 0;
+ m_pcstk = 0;
+ m_pcstkp = 0;
+ m_laddr.addr = m_laddr.code = m_laddr.loop_type = 0;
+ m_curlcntr = 0;
+ m_lcntr = 0;
+ for (int i=0; i < 8; i++)
+ {
+ m_dag1.i[i] = m_dag1.m[i] = m_dag1.b[i] = m_dag1.l[i] = 0;
+ m_dag2.i[i] = m_dag2.m[i] = m_dag2.b[i] = m_dag2.l[i] = 0;
+ m_dag1_alt.i[i] = m_dag1_alt.m[i] = m_dag1_alt.b[i] = m_dag1_alt.l[i] = 0;
+ m_dag2_alt.i[i] = m_dag2_alt.m[i] = m_dag2_alt.b[i] = m_dag2_alt.l[i] = 0;
+ }
+ for (int i=0; i < 12; i++)
+ {
+ m_dma[i].control = 0;
+ m_dma[i].int_index = 0;
+ m_dma[i].int_modifier = 0;
+ m_dma[i].int_count = 0;
+ m_dma[i].chain_ptr = 0;
+ m_dma[i].gen_purpose = 0;
+ m_dma[i].ext_index = 0;
+ m_dma[i].ext_modifier = 0;
+ m_dma[i].ext_count = 0;
+ }
+ m_mode1 = 0;
+ m_mode2 = 0;
+ m_astat = 0;
+ m_irptl = 0;
+ m_imask = 0;
+ m_imaskp = 0;
+ m_ustat1 = 0;
+ m_ustat2 = 0;
+ m_flag[0] = m_flag[1] = m_flag[2] = m_flag[3] = 0;
+ m_syscon = 0;
+ m_sysstat = 0;
+ for (int i=0; i < 5; i++)
+ {
+ m_status_stack[i].mode1 = 0;
+ m_status_stack[i].astat = 0;
+ }
+ m_status_stkp = 0;
+ m_px = 0;
+ m_opcode = 0;
+ m_irq_active = 0;
+ m_active_irq_num = 0;
+ m_dma_status = 0;
+ m_iop_delayed_reg = 0;
+ m_iop_delayed_data = 0;
+ m_delay_slot1 = 0;
+ m_delay_slot2 = 0;
+ m_systemreg_latency_cycles = 0;
+ m_systemreg_latency_reg = 0;
+ m_systemreg_latency_data = 0;
+ m_systemreg_previous_data = 0;
+ m_astat_old = 0;
+ m_astat_old_old = 0;
+ m_astat_old_old_old = 0;
+
+ save_item(NAME(m_pc));
+ save_pointer(NAME(&m_r[0].r), ARRAY_LENGTH(m_r));
+ save_pointer(NAME(&m_reg_alt[0].r), ARRAY_LENGTH(m_reg_alt));
+ save_item(NAME(m_mrf));
+ save_item(NAME(m_mrb));
+
+ save_item(NAME(m_pcstack));
+ save_item(NAME(m_lcstack));
+ save_item(NAME(m_lastack));
+ save_item(NAME(m_lstkp));
+
+ save_item(NAME(m_faddr));
+ save_item(NAME(m_daddr));
+ save_item(NAME(m_pcstk));
+ save_item(NAME(m_pcstkp));
+ save_item(NAME(m_laddr.addr));
+ save_item(NAME(m_laddr.code));
+ save_item(NAME(m_laddr.loop_type));
+ save_item(NAME(m_curlcntr));
+ save_item(NAME(m_lcntr));
+
+ save_item(NAME(m_dag1.i));
+ save_item(NAME(m_dag1.m));
+ save_item(NAME(m_dag1.b));
+ save_item(NAME(m_dag1.l));
+ save_item(NAME(m_dag2.i));
+ save_item(NAME(m_dag2.m));
+ save_item(NAME(m_dag2.b));
+ save_item(NAME(m_dag2.l));
+ save_item(NAME(m_dag1_alt.i));
+ save_item(NAME(m_dag1_alt.m));
+ save_item(NAME(m_dag1_alt.b));
+ save_item(NAME(m_dag1_alt.l));
+ save_item(NAME(m_dag2_alt.i));
+ save_item(NAME(m_dag2_alt.m));
+ save_item(NAME(m_dag2_alt.b));
+ save_item(NAME(m_dag2_alt.l));
+
+ for (saveindex = 0; saveindex < ARRAY_LENGTH(m_dma); saveindex++)
+ {
+ save_item(NAME(m_dma[saveindex].control), saveindex);
+ save_item(NAME(m_dma[saveindex].int_index), saveindex);
+ save_item(NAME(m_dma[saveindex].int_modifier), saveindex);
+ save_item(NAME(m_dma[saveindex].int_count), saveindex);
+ save_item(NAME(m_dma[saveindex].chain_ptr), saveindex);
+ save_item(NAME(m_dma[saveindex].gen_purpose), saveindex);
+ save_item(NAME(m_dma[saveindex].ext_index), saveindex);
+ save_item(NAME(m_dma[saveindex].ext_modifier), saveindex);
+ save_item(NAME(m_dma[saveindex].ext_count), saveindex);
}
- device->save_item(NAME(cpustate->mode1));
- device->save_item(NAME(cpustate->mode2));
- device->save_item(NAME(cpustate->astat));
- device->save_item(NAME(cpustate->stky));
- device->save_item(NAME(cpustate->irptl));
- device->save_item(NAME(cpustate->imask));
- device->save_item(NAME(cpustate->imaskp));
- device->save_item(NAME(cpustate->ustat1));
- device->save_item(NAME(cpustate->ustat2));
+ save_item(NAME(m_mode1));
+ save_item(NAME(m_mode2));
+ save_item(NAME(m_astat));
+ save_item(NAME(m_stky));
+ save_item(NAME(m_irptl));
+ save_item(NAME(m_imask));
+ save_item(NAME(m_imaskp));
+ save_item(NAME(m_ustat1));
+ save_item(NAME(m_ustat2));
- device->save_item(NAME(cpustate->flag));
+ save_item(NAME(m_flag));
- device->save_item(NAME(cpustate->syscon));
- device->save_item(NAME(cpustate->sysstat));
+ save_item(NAME(m_syscon));
+ save_item(NAME(m_sysstat));
- for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->status_stack); saveindex++)
+ for (saveindex = 0; saveindex < ARRAY_LENGTH(m_status_stack); saveindex++)
{
- device->save_item(NAME(cpustate->status_stack[saveindex].mode1), saveindex);
- device->save_item(NAME(cpustate->status_stack[saveindex].astat), saveindex);
+ save_item(NAME(m_status_stack[saveindex].mode1), saveindex);
+ save_item(NAME(m_status_stack[saveindex].astat), saveindex);
}
- device->save_item(NAME(cpustate->status_stkp));
+ save_item(NAME(m_status_stkp));
- device->save_item(NAME(cpustate->px));
+ save_item(NAME(m_px));
- device->save_pointer(NAME(cpustate->internal_ram), 2 * 0x10000);
+ save_pointer(NAME(m_internal_ram), 2 * 0x10000);
- device->save_item(NAME(cpustate->opcode));
+ save_item(NAME(m_opcode));
- device->save_item(NAME(cpustate->nfaddr));
+ save_item(NAME(m_nfaddr));
- device->save_item(NAME(cpustate->idle));
- device->save_item(NAME(cpustate->irq_active));
- device->save_item(NAME(cpustate->active_irq_num));
+ save_item(NAME(m_idle));
+ save_item(NAME(m_irq_active));
+ save_item(NAME(m_active_irq_num));
- for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->dma_op); saveindex++)
+ for (saveindex = 0; saveindex < ARRAY_LENGTH(m_dma_op); saveindex++)
{
- device->save_item(NAME(cpustate->dma_op[saveindex].src), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].dst), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].chain_ptr), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].src_modifier), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].dst_modifier), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].src_count), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].dst_count), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].pmode), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].chained_direction), saveindex);
- device->save_item(NAME(cpustate->dma_op[saveindex].active), saveindex);
+ save_item(NAME(m_dma_op[saveindex].src), saveindex);
+ save_item(NAME(m_dma_op[saveindex].dst), saveindex);
+ save_item(NAME(m_dma_op[saveindex].chain_ptr), saveindex);
+ save_item(NAME(m_dma_op[saveindex].src_modifier), saveindex);
+ save_item(NAME(m_dma_op[saveindex].dst_modifier), saveindex);
+ save_item(NAME(m_dma_op[saveindex].src_count), saveindex);
+ save_item(NAME(m_dma_op[saveindex].dst_count), saveindex);
+ save_item(NAME(m_dma_op[saveindex].pmode), saveindex);
+ save_item(NAME(m_dma_op[saveindex].chained_direction), saveindex);
+ save_item(NAME(m_dma_op[saveindex].active), saveindex);
}
- device->save_item(NAME(cpustate->dma_status));
-
- device->save_item(NAME(cpustate->interrupt_active));
-
- device->save_item(NAME(cpustate->iop_delayed_reg));
- device->save_item(NAME(cpustate->iop_delayed_data));
-
- device->save_item(NAME(cpustate->delay_slot1));
- device->save_item(NAME(cpustate->delay_slot2));
-
- device->save_item(NAME(cpustate->systemreg_latency_cycles));
- device->save_item(NAME(cpustate->systemreg_latency_reg));
- device->save_item(NAME(cpustate->systemreg_latency_data));
- device->save_item(NAME(cpustate->systemreg_previous_data));
-
- device->save_item(NAME(cpustate->astat_old));
- device->save_item(NAME(cpustate->astat_old_old));
- device->save_item(NAME(cpustate->astat_old_old_old));
+ save_item(NAME(m_dma_status));
+
+ save_item(NAME(m_interrupt_active));
+
+ save_item(NAME(m_iop_delayed_reg));
+ save_item(NAME(m_iop_delayed_data));
+
+ save_item(NAME(m_delay_slot1));
+ save_item(NAME(m_delay_slot2));
+
+ save_item(NAME(m_systemreg_latency_cycles));
+ save_item(NAME(m_systemreg_latency_reg));
+ save_item(NAME(m_systemreg_latency_data));
+ save_item(NAME(m_systemreg_previous_data));
+
+ save_item(NAME(m_astat_old));
+ save_item(NAME(m_astat_old_old));
+ save_item(NAME(m_astat_old_old_old));
+
+ state_add( SHARC_PC, "PC", m_pc).formatstr("%08X");
+ state_add( SHARC_PCSTK, "PCSTK", m_pcstk).formatstr("%08X");
+ state_add( SHARC_PCSTKP, "PCSTKP", m_pcstkp).formatstr("%08X");
+ state_add( SHARC_LSTKP, "LSTKP", m_lstkp).formatstr("%08X");
+ state_add( SHARC_FADDR, "FADDR", m_faddr).formatstr("%08X");
+ state_add( SHARC_DADDR, "DADDR", m_daddr).formatstr("%08X");
+ state_add( SHARC_MODE1, "MODE1", m_mode1).formatstr("%08X");
+ state_add( SHARC_MODE2, "MODE2", m_mode2).formatstr("%08X");
+ state_add( SHARC_ASTAT, "ASTAT", m_astat).formatstr("%08X");
+ state_add( SHARC_IRPTL, "IRPTL", m_irptl).formatstr("%08X");
+ state_add( SHARC_IMASK, "IMASK", m_imask).formatstr("%08X");
+ state_add( SHARC_USTAT1, "USTAT1", m_ustat1).formatstr("%08X");
+ state_add( SHARC_USTAT2, "USTAT2", m_ustat2).formatstr("%08X");
+ state_add( SHARC_STSTKP, "STSTKP", m_status_stkp).formatstr("%08X");
+
+ state_add( SHARC_R0, "R0", m_r[0].r).formatstr("%08X");
+ state_add( SHARC_R1, "R1", m_r[1].r).formatstr("%08X");
+ state_add( SHARC_R2, "R2", m_r[2].r).formatstr("%08X");
+ state_add( SHARC_R3, "R3", m_r[3].r).formatstr("%08X");
+ state_add( SHARC_R4, "R4", m_r[4].r).formatstr("%08X");
+ state_add( SHARC_R5, "R5", m_r[5].r).formatstr("%08X");
+ state_add( SHARC_R6, "R6", m_r[6].r).formatstr("%08X");
+ state_add( SHARC_R7, "R7", m_r[7].r).formatstr("%08X");
+ state_add( SHARC_R8, "R8", m_r[8].r).formatstr("%08X");
+ state_add( SHARC_R9, "R9", m_r[9].r).formatstr("%08X");
+ state_add( SHARC_R10, "R10", m_r[10].r).formatstr("%08X");
+ state_add( SHARC_R11, "R11", m_r[11].r).formatstr("%08X");
+ state_add( SHARC_R12, "R12", m_r[12].r).formatstr("%08X");
+ state_add( SHARC_R13, "R13", m_r[13].r).formatstr("%08X");
+ state_add( SHARC_R14, "R14", m_r[14].r).formatstr("%08X");
+ state_add( SHARC_R15, "R15", m_r[15].r).formatstr("%08X");
+
+ state_add( SHARC_I0, "I0", m_dag1.i[0]).formatstr("%08X");
+ state_add( SHARC_I1, "I1", m_dag1.i[1]).formatstr("%08X");
+ state_add( SHARC_I2, "I2", m_dag1.i[2]).formatstr("%08X");
+ state_add( SHARC_I3, "I3", m_dag1.i[3]).formatstr("%08X");
+ state_add( SHARC_I4, "I4", m_dag1.i[4]).formatstr("%08X");
+ state_add( SHARC_I5, "I5", m_dag1.i[5]).formatstr("%08X");
+ state_add( SHARC_I6, "I6", m_dag1.i[6]).formatstr("%08X");
+ state_add( SHARC_I7, "I7", m_dag1.i[7]).formatstr("%08X");
+ state_add( SHARC_I8, "I8", m_dag2.i[0]).formatstr("%08X");
+ state_add( SHARC_I9, "I9", m_dag2.i[1]).formatstr("%08X");
+ state_add( SHARC_I10, "I10", m_dag2.i[2]).formatstr("%08X");
+ state_add( SHARC_I11, "I11", m_dag2.i[3]).formatstr("%08X");
+ state_add( SHARC_I12, "I12", m_dag2.i[4]).formatstr("%08X");
+ state_add( SHARC_I13, "I13", m_dag2.i[5]).formatstr("%08X");
+ state_add( SHARC_I14, "I14", m_dag2.i[6]).formatstr("%08X");
+ state_add( SHARC_I15, "I15", m_dag2.i[7]).formatstr("%08X");
+
+ state_add( SHARC_M0, "M0", m_dag1.m[0]).formatstr("%08X");
+ state_add( SHARC_M1, "M1", m_dag1.m[1]).formatstr("%08X");
+ state_add( SHARC_M2, "M2", m_dag1.m[2]).formatstr("%08X");
+ state_add( SHARC_M3, "M3", m_dag1.m[3]).formatstr("%08X");
+ state_add( SHARC_M4, "M4", m_dag1.m[4]).formatstr("%08X");
+ state_add( SHARC_M5, "M5", m_dag1.m[5]).formatstr("%08X");
+ state_add( SHARC_M6, "M6", m_dag1.m[6]).formatstr("%08X");
+ state_add( SHARC_M7, "M7", m_dag1.m[7]).formatstr("%08X");
+ state_add( SHARC_M8, "M8", m_dag2.m[0]).formatstr("%08X");
+ state_add( SHARC_M9, "M9", m_dag2.m[1]).formatstr("%08X");
+ state_add( SHARC_M10, "M10", m_dag2.m[2]).formatstr("%08X");
+ state_add( SHARC_M11, "M11", m_dag2.m[3]).formatstr("%08X");
+ state_add( SHARC_M12, "M12", m_dag2.m[4]).formatstr("%08X");
+ state_add( SHARC_M13, "M13", m_dag2.m[5]).formatstr("%08X");
+ state_add( SHARC_M14, "M14", m_dag2.m[6]).formatstr("%08X");
+ state_add( SHARC_M15, "M15", m_dag2.m[7]).formatstr("%08X");
+
+ state_add( SHARC_L0, "L0", m_dag1.l[0]).formatstr("%08X");
+ state_add( SHARC_L1, "L1", m_dag1.l[1]).formatstr("%08X");
+ state_add( SHARC_L2, "L2", m_dag1.l[2]).formatstr("%08X");
+ state_add( SHARC_L3, "L3", m_dag1.l[3]).formatstr("%08X");
+ state_add( SHARC_L4, "L4", m_dag1.l[4]).formatstr("%08X");
+ state_add( SHARC_L5, "L5", m_dag1.l[5]).formatstr("%08X");
+ state_add( SHARC_L6, "L6", m_dag1.l[6]).formatstr("%08X");
+ state_add( SHARC_L7, "L7", m_dag1.l[7]).formatstr("%08X");
+ state_add( SHARC_L8, "L8", m_dag2.l[0]).formatstr("%08X");
+ state_add( SHARC_L9, "L9", m_dag2.l[1]).formatstr("%08X");
+ state_add( SHARC_L10, "L10", m_dag2.l[2]).formatstr("%08X");
+ state_add( SHARC_L11, "L11", m_dag2.l[3]).formatstr("%08X");
+ state_add( SHARC_L12, "L12", m_dag2.l[4]).formatstr("%08X");
+ state_add( SHARC_L13, "L13", m_dag2.l[5]).formatstr("%08X");
+ state_add( SHARC_L14, "L14", m_dag2.l[6]).formatstr("%08X");
+ state_add( SHARC_L15, "L15", m_dag2.l[7]).formatstr("%08X");
+
+ state_add( SHARC_B0, "B0", m_dag1.b[0]).formatstr("%08X");
+ state_add( SHARC_B1, "B1", m_dag1.b[1]).formatstr("%08X");
+ state_add( SHARC_B2, "B2", m_dag1.b[2]).formatstr("%08X");
+ state_add( SHARC_B3, "B3", m_dag1.b[3]).formatstr("%08X");
+ state_add( SHARC_B4, "B4", m_dag1.b[4]).formatstr("%08X");
+ state_add( SHARC_B5, "B5", m_dag1.b[5]).formatstr("%08X");
+ state_add( SHARC_B6, "B6", m_dag1.b[6]).formatstr("%08X");
+ state_add( SHARC_B7, "B7", m_dag1.b[7]).formatstr("%08X");
+ state_add( SHARC_B8, "B8", m_dag2.b[0]).formatstr("%08X");
+ state_add( SHARC_B9, "B9", m_dag2.b[1]).formatstr("%08X");
+ state_add( SHARC_B10, "B10", m_dag2.b[2]).formatstr("%08X");
+ state_add( SHARC_B11, "B11", m_dag2.b[3]).formatstr("%08X");
+ state_add( SHARC_B12, "B12", m_dag2.b[4]).formatstr("%08X");
+ state_add( SHARC_B13, "B13", m_dag2.b[5]).formatstr("%08X");
+ state_add( SHARC_B14, "B14", m_dag2.b[6]).formatstr("%08X");
+ state_add( SHARC_B15, "B15", m_dag2.b[7]).formatstr("%08X");
+
+ state_add( STATE_GENPC, "GENPC", m_pc).noshow();
+
+ m_icountptr = &m_icount;
}
-static CPU_RESET( sharc )
+void adsp21062_device::device_reset()
{
- SHARC_REGS *cpustate = get_safe_token(device);
- memset(cpustate->internal_ram, 0, 2 * 0x10000 * sizeof(UINT16));
+ memset(m_internal_ram, 0, 2 * 0x10000 * sizeof(UINT16));
- switch(cpustate->boot_mode)
+ switch(m_boot_mode)
{
case BOOT_MODE_EPROM:
{
- cpustate->dma[6].int_index = 0x20000;
- cpustate->dma[6].int_modifier = 1;
- cpustate->dma[6].int_count = 0x100;
- cpustate->dma[6].ext_index = 0x400000;
- cpustate->dma[6].ext_modifier = 1;
- cpustate->dma[6].ext_count = 0x600;
- cpustate->dma[6].control = 0x2a1;
-
- sharc_dma_exec(cpustate, 6);
- dma_op(cpustate, 6);
-
- cpustate->dma_op[6].timer->adjust(attotime::never, 0);
+ m_dma[6].int_index = 0x20000;
+ m_dma[6].int_modifier = 1;
+ m_dma[6].int_count = 0x100;
+ m_dma[6].ext_index = 0x400000;
+ m_dma[6].ext_modifier = 1;
+ m_dma[6].ext_count = 0x600;
+ m_dma[6].control = 0x2a1;
+
+ sharc_dma_exec(6);
+ dma_op(6);
+
+ m_dma_op[6].timer->adjust(attotime::never, 0);
break;
}
@@ -588,46 +633,48 @@ static CPU_RESET( sharc )
break;
default:
- fatalerror("SHARC: Unimplemented boot mode %d\n", cpustate->boot_mode);
+ fatalerror("SHARC: Unimplemented boot mode %d\n", m_boot_mode);
}
- cpustate->pc = 0x20004;
- cpustate->daddr = cpustate->pc + 1;
- cpustate->faddr = cpustate->daddr + 1;
- cpustate->nfaddr = cpustate->faddr+1;
+ m_pc = 0x20004;
+ m_daddr = m_pc + 1;
+ m_faddr = m_daddr + 1;
+ m_nfaddr = m_faddr+1;
- cpustate->idle = 0;
- cpustate->stky = 0x5400000;
+ m_idle = 0;
+ m_stky = 0x5400000;
- cpustate->interrupt_active = 0;
+ m_interrupt_active = 0;
}
-static CPU_EXIT( sharc )
-{
- /* TODO */
-}
-static void sharc_set_irq_line(SHARC_REGS *cpustate, int irqline, int state)
+void adsp21062_device::execute_set_input(int irqline, int state)
{
- if (state == ASSERT_LINE)
+ if (irqline >= 0 && irqline <= 2)
{
- cpustate->irq_active |= 1 << (8-irqline);
- }
- else
- {
- cpustate->irq_active &= ~(1 << (8-irqline));
- }
+ if (state == ASSERT_LINE)
+ {
+ m_irq_active |= 1 << (8-irqline);
+ }
+ else
+ {
+ m_irq_active &= ~(1 << (8-irqline));
+ }
+ }
+ else if (irqline >= SHARC_INPUT_FLAG0 && irqline <= SHARC_INPUT_FLAG3)
+ {
+ set_flag_input(irqline - SHARC_INPUT_FLAG0, state);
+ }
}
-void sharc_set_flag_input(device_t *device, int flag_num, int state)
+void adsp21062_device::set_flag_input(int flag_num, int state)
{
- SHARC_REGS *cpustate = get_safe_token(device);
if (flag_num >= 0 && flag_num < 4)
{
// Check if flag is set to input in MODE2 (bit == 0)
- if ((cpustate->mode2 & (1 << (flag_num+15))) == 0)
+ if ((m_mode2 & (1 << (flag_num+15))) == 0)
{
- cpustate->flag[flag_num] = state ? 1 : 0;
+ m_flag[flag_num] = state ? 1 : 0;
}
else
{
@@ -636,280 +683,156 @@ void sharc_set_flag_input(device_t *device, int flag_num, int state)
}
}
-static void check_interrupts(SHARC_REGS *cpustate)
+void adsp21062_device::check_interrupts()
{
int i;
- if ((cpustate->imask & cpustate->irq_active) && (cpustate->mode1 & MODE1_IRPTEN) && !cpustate->interrupt_active &&
- cpustate->pc != cpustate->delay_slot1 && cpustate->pc != cpustate->delay_slot2)
+ if ((m_imask & m_irq_active) && (m_mode1 & MODE1_IRPTEN) && !m_interrupt_active &&
+ m_pc != m_delay_slot1 && m_pc != m_delay_slot2)
{
int which = 0;
for (i=0; i < 32; i++)
{
- if (cpustate->irq_active & (1 << i))
+ if (m_irq_active & (1 << i))
{
break;
}
which++;
}
- if (cpustate->idle)
+ if (m_idle)
{
- PUSH_PC(cpustate, cpustate->pc+1);
+ PUSH_PC(m_pc+1);
}
else
{
- PUSH_PC(cpustate, cpustate->daddr);
+ PUSH_PC(m_daddr);
}
- cpustate->irptl |= 1 << which;
+ m_irptl |= 1 << which;
if (which >= 6 && which <= 8)
{
- PUSH_STATUS_STACK(cpustate);
+ PUSH_STATUS_STACK();
}
- CHANGE_PC(cpustate, 0x20000 + (which * 0x4));
+ CHANGE_PC(0x20000 + (which * 0x4));
/* TODO: alter IMASKP */
- cpustate->active_irq_num = which;
- cpustate->irq_active &= ~(1 << which);
+ m_active_irq_num = which;
+ m_irq_active &= ~(1 << which);
- cpustate->interrupt_active = 1;
+ m_interrupt_active = 1;
}
}
-static CPU_EXECUTE( sharc )
+void adsp21062_device::execute_run()
{
- SHARC_REGS *cpustate = get_safe_token(device);
-
- if (cpustate->idle && cpustate->irq_active == 0)
+ if (m_idle && m_irq_active == 0)
{
- cpustate->icount = 0;
- debugger_instruction_hook(device, cpustate->daddr);
+ m_icount = 0;
+ debugger_instruction_hook(this, m_daddr);
}
- if (cpustate->irq_active != 0)
+ if (m_irq_active != 0)
{
- check_interrupts(cpustate);
- cpustate->idle = 0;
+ check_interrupts();
+ m_idle = 0;
}
- while (cpustate->icount > 0 && !cpustate->idle)
+ while (m_icount > 0 && !m_idle)
{
- cpustate->pc = cpustate->daddr;
- cpustate->daddr = cpustate->faddr;
- cpustate->faddr = cpustate->nfaddr;
- cpustate->nfaddr++;
+ m_pc = m_daddr;
+ m_daddr = m_faddr;
+ m_faddr = m_nfaddr;
+ m_nfaddr++;
- cpustate->astat_old_old_old = cpustate->astat_old_old;
- cpustate->astat_old_old = cpustate->astat_old;
- cpustate->astat_old = cpustate->astat;
+ m_astat_old_old_old = m_astat_old_old;
+ m_astat_old_old = m_astat_old;
+ m_astat_old = m_astat;
- cpustate->opcode = ROPCODE(cpustate->pc);
+ m_opcode = ROPCODE(m_pc);
- debugger_instruction_hook(device, cpustate->pc);
+ debugger_instruction_hook(this, m_pc);
// handle looping
- if (cpustate->pc == cpustate->laddr.addr)
+ if (m_pc == m_laddr.addr)
{
- switch (cpustate->laddr.loop_type)
+ switch (m_laddr.loop_type)
{
case 0: // arithmetic condition-based
{
- int condition = cpustate->laddr.code;
+ int condition = m_laddr.code;
{
- UINT32 looptop = TOP_PC(cpustate);
- if (cpustate->pc - looptop > 2)
+ UINT32 looptop = TOP_PC();
+ if (m_pc - looptop > 2)
{
- cpustate->astat = cpustate->astat_old_old_old;
+ m_astat = m_astat_old_old_old;
}
}
- if (DO_CONDITION_CODE(cpustate, condition))
+ if (DO_CONDITION_CODE(condition))
{
- POP_LOOP(cpustate);
- POP_PC(cpustate);
+ POP_LOOP();
+ POP_PC();
}
else
{
- CHANGE_PC(cpustate, TOP_PC(cpustate));
+ CHANGE_PC(TOP_PC());
}
- cpustate->astat = cpustate->astat_old;
+ m_astat = m_astat_old;
break;
}
case 1: // counter-based, length 1
{
- //fatalerror("SHARC: counter-based loop, length 1 at %08X\n", cpustate->pc);
+ //fatalerror("SHARC: counter-based loop, length 1 at %08X\n", m_pc);
//break;
}
case 2: // counter-based, length 2
{
- //fatalerror("SHARC: counter-based loop, length 2 at %08X\n", cpustate->pc);
+ //fatalerror("SHARC: counter-based loop, length 2 at %08X\n", m_pc);
//break;
}
case 3: // counter-based, length >2
{
- --cpustate->lcstack[cpustate->lstkp];
- --cpustate->curlcntr;
- if (cpustate->curlcntr == 0)
+ --m_lcstack[m_lstkp];
+ --m_curlcntr;
+ if (m_curlcntr == 0)
{
- POP_LOOP(cpustate);
- POP_PC(cpustate);
+ POP_LOOP();
+ POP_PC();
}
else
{
- CHANGE_PC(cpustate, TOP_PC(cpustate));
+ CHANGE_PC(TOP_PC());
}
}
}
}
- sharc_op[(cpustate->opcode >> 39) & 0x1ff](cpustate);
+ (this->*m_sharc_op[(m_opcode >> 39) & 0x1ff])();
// System register latency effect
- if (cpustate->systemreg_latency_cycles > 0)
+ if (m_systemreg_latency_cycles > 0)
{
- --cpustate->systemreg_latency_cycles;
- if (cpustate->systemreg_latency_cycles <= 0)
+ --m_systemreg_latency_cycles;
+ if (m_systemreg_latency_cycles <= 0)
{
- systemreg_write_latency_effect(cpustate);
+ systemreg_write_latency_effect();
}
}
- --cpustate->icount;
+ --m_icount;
};
}
-/**************************************************************************
- * Generic set_info
- **************************************************************************/
-
-static CPU_SET_INFO( sharc )
+bool adsp21062_device::memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value)
{
- SHARC_REGS *cpustate = get_safe_token(device);
-
- switch (state)
- {
- case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + SHARC_PC: cpustate->pc = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_FADDR: cpustate->faddr = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_DADDR: cpustate->daddr = info->i; break;
-
- case CPUINFO_INT_REGISTER + SHARC_R0: cpustate->r[0].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R1: cpustate->r[1].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R2: cpustate->r[2].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R3: cpustate->r[3].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R4: cpustate->r[4].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R5: cpustate->r[5].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R6: cpustate->r[6].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R7: cpustate->r[7].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R8: cpustate->r[8].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R9: cpustate->r[9].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R10: cpustate->r[10].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R11: cpustate->r[11].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R12: cpustate->r[12].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R13: cpustate->r[13].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R14: cpustate->r[14].r = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_R15: cpustate->r[15].r = info->i; break;
-
- case CPUINFO_INT_REGISTER + SHARC_I0: cpustate->dag1.i[0] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I1: cpustate->dag1.i[1] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I2: cpustate->dag1.i[2] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I3: cpustate->dag1.i[3] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I4: cpustate->dag1.i[4] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I5: cpustate->dag1.i[5] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I6: cpustate->dag1.i[6] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I7: cpustate->dag1.i[7] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I8: cpustate->dag2.i[0] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I9: cpustate->dag2.i[1] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I10: cpustate->dag2.i[2] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I11: cpustate->dag2.i[3] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I12: cpustate->dag2.i[4] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I13: cpustate->dag2.i[5] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I14: cpustate->dag2.i[6] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_I15: cpustate->dag2.i[7] = info->i; break;
-
- case CPUINFO_INT_REGISTER + SHARC_M0: cpustate->dag1.m[0] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M1: cpustate->dag1.m[1] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M2: cpustate->dag1.m[2] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M3: cpustate->dag1.m[3] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M4: cpustate->dag1.m[4] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M5: cpustate->dag1.m[5] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M6: cpustate->dag1.m[6] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M7: cpustate->dag1.m[7] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M8: cpustate->dag2.m[0] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M9: cpustate->dag2.m[1] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M10: cpustate->dag2.m[2] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M11: cpustate->dag2.m[3] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M12: cpustate->dag2.m[4] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M13: cpustate->dag2.m[5] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M14: cpustate->dag2.m[6] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_M15: cpustate->dag2.m[7] = info->i; break;
-
- case CPUINFO_INT_REGISTER + SHARC_L0: cpustate->dag1.l[0] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L1: cpustate->dag1.l[1] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L2: cpustate->dag1.l[2] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L3: cpustate->dag1.l[3] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L4: cpustate->dag1.l[4] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L5: cpustate->dag1.l[5] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L6: cpustate->dag1.l[6] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L7: cpustate->dag1.l[7] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L8: cpustate->dag2.l[0] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L9: cpustate->dag2.l[1] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L10: cpustate->dag2.l[2] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L11: cpustate->dag2.l[3] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L12: cpustate->dag2.l[4] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L13: cpustate->dag2.l[5] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L14: cpustate->dag2.l[6] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_L15: cpustate->dag2.m[7] = info->i; break;
-
- case CPUINFO_INT_REGISTER + SHARC_B0: cpustate->dag1.b[0] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B1: cpustate->dag1.b[1] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B2: cpustate->dag1.b[2] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B3: cpustate->dag1.b[3] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B4: cpustate->dag1.b[4] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B5: cpustate->dag1.b[5] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B6: cpustate->dag1.b[6] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B7: cpustate->dag1.b[7] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B8: cpustate->dag2.b[0] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B9: cpustate->dag2.b[1] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B10: cpustate->dag2.b[2] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B11: cpustate->dag2.b[3] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B12: cpustate->dag2.b[4] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B13: cpustate->dag2.b[5] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B14: cpustate->dag2.b[6] = info->i; break;
- case CPUINFO_INT_REGISTER + SHARC_B15: cpustate->dag2.b[7] = info->i; break;
- }
-}
-
-static CPU_SET_INFO( adsp21062 )
-{
- if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 2)
- {
- sharc_set_irq_line(get_safe_token(device), state-CPUINFO_INT_INPUT_STATE, info->i);
- return;
- }
- else if (state >= CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG0 && state <= CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG3)
- {
- sharc_set_flag_input(device, state-(CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG0), info->i);
- return;
- }
- switch(state)
- {
- default: CPU_SET_INFO_CALL(sharc); break;
- }
-}
-
-
-static CPU_READ( sharc )
-{
- SHARC_REGS *cpustate = get_safe_token(device);
- if (space == AS_PROGRAM)
+ if (spacenum == AS_PROGRAM)
{
int address = offset >> 3;
@@ -920,24 +843,25 @@ static CPU_READ( sharc )
case 1:
{
int frac = offset & 7;
- *value = (pm_read48(cpustate, offset >> 3) >> ((frac^7) * 8)) & 0xff;
+ value = (pm_read48(offset >> 3) >> ((frac^7) * 8)) & 0xff;
break;
}
case 8:
{
- *value = pm_read48(cpustate, offset >> 3);
+ value = pm_read48(offset >> 3);
break;
}
}
}
else
{
- *value = 0;
+ value = 0;
}
}
- else if (space == AS_DATA)
+ else if (spacenum == AS_DATA)
{
int address = offset >> 2;
+
if (address >= 0x20000)
{
switch (size)
@@ -945,328 +869,53 @@ static CPU_READ( sharc )
case 1:
{
int frac = offset & 3;
- *value = (dm_read32(cpustate, offset >> 2) >> ((frac^3) * 8)) & 0xff;
+ value = (dm_read32(offset >> 2) >> ((frac^3) * 8)) & 0xff;
break;
}
case 2:
{
int frac = (offset >> 1) & 1;
- *value = (dm_read32(cpustate, offset >> 2) >> ((frac^1) * 16)) & 0xffff;
+ value = (dm_read32(offset >> 2) >> ((frac^1) * 16)) & 0xffff;
break;
}
case 4:
{
- *value = dm_read32(cpustate, offset >> 2);
+ value = dm_read32(offset >> 2);
break;
}
}
}
else
{
- *value = 0;
+ value = 0;
}
}
- return 1;
+ return true;
}
-static CPU_READOP( sharc )
+bool adsp21062_device::memory_readop(offs_t offset, int size, UINT64 &value)
{
- SHARC_REGS *cpustate = get_safe_token(device);
UINT64 mask = (size < 8) ? (((UINT64)1 << (8 * size)) - 1) : ~(UINT64)0;
int shift = 8 * (offset & 7);
offset >>= 3;
if (offset >= 0x20000 && offset < 0x28000)
{
- UINT64 op = ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 0]) << 32) |
- ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 1]) << 16) |
- ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 2]) << 0);
- *value = (op >> shift) & mask;
+ UINT64 op = ((UINT64)(m_internal_ram_block0[((offset-0x20000) * 3) + 0]) << 32) |
+ ((UINT64)(m_internal_ram_block0[((offset-0x20000) * 3) + 1]) << 16) |
+ ((UINT64)(m_internal_ram_block0[((offset-0x20000) * 3) + 2]) << 0);
+ value = (op >> shift) & mask;
+ return true;
}
else if (offset >= 0x28000 && offset < 0x30000)
{
- UINT64 op = ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 0]) << 32) |
- ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 1]) << 16) |
- ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 2]) << 0);
- *value = (op >> shift) & mask;
+ UINT64 op = ((UINT64)(m_internal_ram_block1[((offset-0x28000) * 3) + 0]) << 32) |
+ ((UINT64)(m_internal_ram_block1[((offset-0x28000) * 3) + 1]) << 16) |
+ ((UINT64)(m_internal_ram_block1[((offset-0x28000) * 3) + 2]) << 0);
+ value = (op >> shift) & mask;
+ return true;
}
- return 1;
-}
-
-// This is just used to stop the debugger from complaining about executing from I/O space
-static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 64, adsp21062_device )
- AM_RANGE(0x20000, 0x7ffff) AM_RAM
-ADDRESS_MAP_END
-
-static CPU_GET_INFO( sharc )
-{
- SHARC_REGS *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
-
- switch(state)
- {
- /* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(SHARC_REGS); break;
- case CPUINFO_INT_INPUT_LINES: info->i = 32; break;
- case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
- case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
- case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
- case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
- case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 8; break;
- case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 8; break;
- case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
- case CPUINFO_INT_MAX_CYCLES: info->i = 40; break;
-
- case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 64; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -3; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 32; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = -2; break;
- case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
-
- case CPUINFO_INT_INPUT_STATE: info->i = CLEAR_LINE; break;
-
- case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
-
- case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + SHARC_PC: info->i = cpustate->pc; break;
- case CPUINFO_INT_REGISTER + SHARC_PCSTK: info->i = cpustate->pcstk; break;
- case CPUINFO_INT_REGISTER + SHARC_PCSTKP: info->i = cpustate->pcstkp; break;
- case CPUINFO_INT_REGISTER + SHARC_LSTKP: info->i = cpustate->lstkp; break;
- case CPUINFO_INT_REGISTER + SHARC_FADDR: info->i = cpustate->faddr; break;
- case CPUINFO_INT_REGISTER + SHARC_DADDR: info->i = cpustate->daddr; break;
- case CPUINFO_INT_REGISTER + SHARC_MODE1: info->i = cpustate->mode1; break;
- case CPUINFO_INT_REGISTER + SHARC_MODE2: info->i = cpustate->mode2; break;
- case CPUINFO_INT_REGISTER + SHARC_ASTAT: info->i = cpustate->astat; break;
- case CPUINFO_INT_REGISTER + SHARC_IRPTL: info->i = cpustate->irptl; break;
- case CPUINFO_INT_REGISTER + SHARC_IMASK: info->i = cpustate->imask; break;
- case CPUINFO_INT_REGISTER + SHARC_USTAT1: info->i = cpustate->ustat1; break;
- case CPUINFO_INT_REGISTER + SHARC_USTAT2: info->i = cpustate->ustat2; break;
- case CPUINFO_INT_REGISTER + SHARC_STSTKP: info->i = cpustate->status_stkp; break;
-
- case CPUINFO_INT_REGISTER + SHARC_R0: info->i = cpustate->r[0].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R1: info->i = cpustate->r[1].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R2: info->i = cpustate->r[2].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R3: info->i = cpustate->r[3].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R4: info->i = cpustate->r[4].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R5: info->i = cpustate->r[5].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R6: info->i = cpustate->r[6].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R7: info->i = cpustate->r[7].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R8: info->i = cpustate->r[8].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R9: info->i = cpustate->r[9].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R10: info->i = cpustate->r[10].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R11: info->i = cpustate->r[11].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R12: info->i = cpustate->r[12].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R13: info->i = cpustate->r[13].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R14: info->i = cpustate->r[14].r; break;
- case CPUINFO_INT_REGISTER + SHARC_R15: info->i = cpustate->r[15].r; break;
-
- case CPUINFO_INT_REGISTER + SHARC_I0: info->i = cpustate->dag1.i[0]; break;
- case CPUINFO_INT_REGISTER + SHARC_I1: info->i = cpustate->dag1.i[1]; break;
- case CPUINFO_INT_REGISTER + SHARC_I2: info->i = cpustate->dag1.i[2]; break;
- case CPUINFO_INT_REGISTER + SHARC_I3: info->i = cpustate->dag1.i[3]; break;
- case CPUINFO_INT_REGISTER + SHARC_I4: info->i = cpustate->dag1.i[4]; break;
- case CPUINFO_INT_REGISTER + SHARC_I5: info->i = cpustate->dag1.i[5]; break;
- case CPUINFO_INT_REGISTER + SHARC_I6: info->i = cpustate->dag1.i[6]; break;
- case CPUINFO_INT_REGISTER + SHARC_I7: info->i = cpustate->dag1.i[7]; break;
- case CPUINFO_INT_REGISTER + SHARC_I8: info->i = cpustate->dag2.i[0]; break;
- case CPUINFO_INT_REGISTER + SHARC_I9: info->i = cpustate->dag2.i[1]; break;
- case CPUINFO_INT_REGISTER + SHARC_I10: info->i = cpustate->dag2.i[2]; break;
- case CPUINFO_INT_REGISTER + SHARC_I11: info->i = cpustate->dag2.i[3]; break;
- case CPUINFO_INT_REGISTER + SHARC_I12: info->i = cpustate->dag2.i[4]; break;
- case CPUINFO_INT_REGISTER + SHARC_I13: info->i = cpustate->dag2.i[5]; break;
- case CPUINFO_INT_REGISTER + SHARC_I14: info->i = cpustate->dag2.i[6]; break;
- case CPUINFO_INT_REGISTER + SHARC_I15: info->i = cpustate->dag2.i[7]; break;
-
- case CPUINFO_INT_REGISTER + SHARC_M0: info->i = cpustate->dag1.m[0]; break;
- case CPUINFO_INT_REGISTER + SHARC_M1: info->i = cpustate->dag1.m[1]; break;
- case CPUINFO_INT_REGISTER + SHARC_M2: info->i = cpustate->dag1.m[2]; break;
- case CPUINFO_INT_REGISTER + SHARC_M3: info->i = cpustate->dag1.m[3]; break;
- case CPUINFO_INT_REGISTER + SHARC_M4: info->i = cpustate->dag1.m[4]; break;
- case CPUINFO_INT_REGISTER + SHARC_M5: info->i = cpustate->dag1.m[5]; break;
- case CPUINFO_INT_REGISTER + SHARC_M6: info->i = cpustate->dag1.m[6]; break;
- case CPUINFO_INT_REGISTER + SHARC_M7: info->i = cpustate->dag1.m[7]; break;
- case CPUINFO_INT_REGISTER + SHARC_M8: info->i = cpustate->dag2.m[0]; break;
- case CPUINFO_INT_REGISTER + SHARC_M9: info->i = cpustate->dag2.m[1]; break;
- case CPUINFO_INT_REGISTER + SHARC_M10: info->i = cpustate->dag2.m[2]; break;
- case CPUINFO_INT_REGISTER + SHARC_M11: info->i = cpustate->dag2.m[3]; break;
- case CPUINFO_INT_REGISTER + SHARC_M12: info->i = cpustate->dag2.m[4]; break;
- case CPUINFO_INT_REGISTER + SHARC_M13: info->i = cpustate->dag2.m[5]; break;
- case CPUINFO_INT_REGISTER + SHARC_M14: info->i = cpustate->dag2.m[6]; break;
- case CPUINFO_INT_REGISTER + SHARC_M15: info->i = cpustate->dag2.m[7]; break;
-
- case CPUINFO_INT_REGISTER + SHARC_L0: info->i = cpustate->dag1.l[0]; break;
- case CPUINFO_INT_REGISTER + SHARC_L1: info->i = cpustate->dag1.l[1]; break;
- case CPUINFO_INT_REGISTER + SHARC_L2: info->i = cpustate->dag1.l[2]; break;
- case CPUINFO_INT_REGISTER + SHARC_L3: info->i = cpustate->dag1.l[3]; break;
- case CPUINFO_INT_REGISTER + SHARC_L4: info->i = cpustate->dag1.l[4]; break;
- case CPUINFO_INT_REGISTER + SHARC_L5: info->i = cpustate->dag1.l[5]; break;
- case CPUINFO_INT_REGISTER + SHARC_L6: info->i = cpustate->dag1.l[6]; break;
- case CPUINFO_INT_REGISTER + SHARC_L7: info->i = cpustate->dag1.l[7]; break;
- case CPUINFO_INT_REGISTER + SHARC_L8: info->i = cpustate->dag2.l[0]; break;
- case CPUINFO_INT_REGISTER + SHARC_L9: info->i = cpustate->dag2.l[1]; break;
- case CPUINFO_INT_REGISTER + SHARC_L10: info->i = cpustate->dag2.l[2]; break;
- case CPUINFO_INT_REGISTER + SHARC_L11: info->i = cpustate->dag2.l[3]; break;
- case CPUINFO_INT_REGISTER + SHARC_L12: info->i = cpustate->dag2.l[4]; break;
- case CPUINFO_INT_REGISTER + SHARC_L13: info->i = cpustate->dag2.l[5]; break;
- case CPUINFO_INT_REGISTER + SHARC_L14: info->i = cpustate->dag2.l[6]; break;
- case CPUINFO_INT_REGISTER + SHARC_L15: info->i = cpustate->dag2.l[7]; break;
-
- case CPUINFO_INT_REGISTER + SHARC_B0: info->i = cpustate->dag1.b[0]; break;
- case CPUINFO_INT_REGISTER + SHARC_B1: info->i = cpustate->dag1.b[1]; break;
- case CPUINFO_INT_REGISTER + SHARC_B2: info->i = cpustate->dag1.b[2]; break;
- case CPUINFO_INT_REGISTER + SHARC_B3: info->i = cpustate->dag1.b[3]; break;
- case CPUINFO_INT_REGISTER + SHARC_B4: info->i = cpustate->dag1.b[4]; break;
- case CPUINFO_INT_REGISTER + SHARC_B5: info->i = cpustate->dag1.b[5]; break;
- case CPUINFO_INT_REGISTER + SHARC_B6: info->i = cpustate->dag1.b[6]; break;
- case CPUINFO_INT_REGISTER + SHARC_B7: info->i = cpustate->dag1.b[7]; break;
- case CPUINFO_INT_REGISTER + SHARC_B8: info->i = cpustate->dag2.b[0]; break;
- case CPUINFO_INT_REGISTER + SHARC_B9: info->i = cpustate->dag2.b[1]; break;
- case CPUINFO_INT_REGISTER + SHARC_B10: info->i = cpustate->dag2.b[2]; break;
- case CPUINFO_INT_REGISTER + SHARC_B11: info->i = cpustate->dag2.b[3]; break;
- case CPUINFO_INT_REGISTER + SHARC_B12: info->i = cpustate->dag2.b[4]; break;
- case CPUINFO_INT_REGISTER + SHARC_B13: info->i = cpustate->dag2.b[5]; break;
- case CPUINFO_INT_REGISTER + SHARC_B14: info->i = cpustate->dag2.b[6]; break;
- case CPUINFO_INT_REGISTER + SHARC_B15: info->i = cpustate->dag2.b[7]; break;
-
- /* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(sharc); break;
- case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sharc); break;
- case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(sharc); break;
- case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sharc);break;
- case CPUINFO_FCT_BURN: info->burn = NULL; break;
- case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sharc); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
- case CPUINFO_FCT_READ: info->read = CPU_READ_NAME(sharc); break;
- case CPUINFO_FCT_READOP: info->readop = CPU_READOP_NAME(sharc); break;
- case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(internal_pgm); break;
-
- /* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_FAMILY: strcpy(info->s, "SHARC"); break;
- case CPUINFO_STR_VERSION: strcpy(info->s, "2.01"); break;
- case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break;
-
- case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break;
-
- case CPUINFO_STR_REGISTER + SHARC_PC: sprintf(info->s, "PC: %08X", cpustate->pc); break;
- case CPUINFO_STR_REGISTER + SHARC_PCSTK: sprintf(info->s, "PCSTK: %08X", cpustate->pcstk); break;
- case CPUINFO_STR_REGISTER + SHARC_PCSTKP: sprintf(info->s, "PCSTKP: %08X", cpustate->pcstkp); break;
- case CPUINFO_STR_REGISTER + SHARC_LSTKP: sprintf(info->s, "LSTKP: %08X", cpustate->lstkp); break;
- case CPUINFO_STR_REGISTER + SHARC_FADDR: sprintf(info->s, "FADDR: %08X", cpustate->faddr); break;
- case CPUINFO_STR_REGISTER + SHARC_DADDR: sprintf(info->s, "DADDR: %08X", cpustate->daddr); break;
- case CPUINFO_STR_REGISTER + SHARC_MODE1: sprintf(info->s, "MODE1: %08X", cpustate->mode1); break;
- case CPUINFO_STR_REGISTER + SHARC_MODE2: sprintf(info->s, "MODE2: %08X", cpustate->mode2); break;
- case CPUINFO_STR_REGISTER + SHARC_ASTAT: sprintf(info->s, "ASTAT: %08X", cpustate->astat); break;
- case CPUINFO_STR_REGISTER + SHARC_IRPTL: sprintf(info->s, "IRPTL: %08X", cpustate->irptl); break;
- case CPUINFO_STR_REGISTER + SHARC_IMASK: sprintf(info->s, "IMASK: %08X", cpustate->imask); break;
- case CPUINFO_STR_REGISTER + SHARC_USTAT1: sprintf(info->s, "USTAT1: %08X", cpustate->ustat1); break;
- case CPUINFO_STR_REGISTER + SHARC_USTAT2: sprintf(info->s, "USTAT2: %08X", cpustate->ustat2); break;
- case CPUINFO_STR_REGISTER + SHARC_STSTKP: sprintf(info->s, "STSTKP: %08X", cpustate->status_stkp); break;
-
- case CPUINFO_STR_REGISTER + SHARC_R0: sprintf(info->s, "R0: %08X", (UINT32)cpustate->r[0].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R1: sprintf(info->s, "R1: %08X", (UINT32)cpustate->r[1].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R2: sprintf(info->s, "R2: %08X", (UINT32)cpustate->r[2].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R3: sprintf(info->s, "R3: %08X", (UINT32)cpustate->r[3].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R4: sprintf(info->s, "R4: %08X", (UINT32)cpustate->r[4].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R5: sprintf(info->s, "R5: %08X", (UINT32)cpustate->r[5].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R6: sprintf(info->s, "R6: %08X", (UINT32)cpustate->r[6].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R7: sprintf(info->s, "R7: %08X", (UINT32)cpustate->r[7].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R8: sprintf(info->s, "R8: %08X", (UINT32)cpustate->r[8].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R9: sprintf(info->s, "R9: %08X", (UINT32)cpustate->r[9].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R10: sprintf(info->s, "R10: %08X", (UINT32)cpustate->r[10].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R11: sprintf(info->s, "R11: %08X", (UINT32)cpustate->r[11].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R12: sprintf(info->s, "R12: %08X", (UINT32)cpustate->r[12].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R13: sprintf(info->s, "R13: %08X", (UINT32)cpustate->r[13].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R14: sprintf(info->s, "R14: %08X", (UINT32)cpustate->r[14].r); break;
- case CPUINFO_STR_REGISTER + SHARC_R15: sprintf(info->s, "R15: %08X", (UINT32)cpustate->r[15].r); break;
-
- case CPUINFO_STR_REGISTER + SHARC_I0: sprintf(info->s, "I0: %08X", (UINT32)cpustate->dag1.i[0]); break;
- case CPUINFO_STR_REGISTER + SHARC_I1: sprintf(info->s, "I1: %08X", (UINT32)cpustate->dag1.i[1]); break;
- case CPUINFO_STR_REGISTER + SHARC_I2: sprintf(info->s, "I2: %08X", (UINT32)cpustate->dag1.i[2]); break;
- case CPUINFO_STR_REGISTER + SHARC_I3: sprintf(info->s, "I3: %08X", (UINT32)cpustate->dag1.i[3]); break;
- case CPUINFO_STR_REGISTER + SHARC_I4: sprintf(info->s, "I4: %08X", (UINT32)cpustate->dag1.i[4]); break;
- case CPUINFO_STR_REGISTER + SHARC_I5: sprintf(info->s, "I5: %08X", (UINT32)cpustate->dag1.i[5]); break;
- case CPUINFO_STR_REGISTER + SHARC_I6: sprintf(info->s, "I6: %08X", (UINT32)cpustate->dag1.i[6]); break;
- case CPUINFO_STR_REGISTER + SHARC_I7: sprintf(info->s, "I7: %08X", (UINT32)cpustate->dag1.i[7]); break;
- case CPUINFO_STR_REGISTER + SHARC_I8: sprintf(info->s, "I8: %08X", (UINT32)cpustate->dag2.i[0]); break;
- case CPUINFO_STR_REGISTER + SHARC_I9: sprintf(info->s, "I9: %08X", (UINT32)cpustate->dag2.i[1]); break;
- case CPUINFO_STR_REGISTER + SHARC_I10: sprintf(info->s, "I10: %08X", (UINT32)cpustate->dag2.i[2]); break;
- case CPUINFO_STR_REGISTER + SHARC_I11: sprintf(info->s, "I11: %08X", (UINT32)cpustate->dag2.i[3]); break;
- case CPUINFO_STR_REGISTER + SHARC_I12: sprintf(info->s, "I12: %08X", (UINT32)cpustate->dag2.i[4]); break;
- case CPUINFO_STR_REGISTER + SHARC_I13: sprintf(info->s, "I13: %08X", (UINT32)cpustate->dag2.i[5]); break;
- case CPUINFO_STR_REGISTER + SHARC_I14: sprintf(info->s, "I14: %08X", (UINT32)cpustate->dag2.i[6]); break;
- case CPUINFO_STR_REGISTER + SHARC_I15: sprintf(info->s, "I15: %08X", (UINT32)cpustate->dag2.i[7]); break;
-
- case CPUINFO_STR_REGISTER + SHARC_M0: sprintf(info->s, "M0: %08X", (UINT32)cpustate->dag1.m[0]); break;
- case CPUINFO_STR_REGISTER + SHARC_M1: sprintf(info->s, "M1: %08X", (UINT32)cpustate->dag1.m[1]); break;
- case CPUINFO_STR_REGISTER + SHARC_M2: sprintf(info->s, "M2: %08X", (UINT32)cpustate->dag1.m[2]); break;
- case CPUINFO_STR_REGISTER + SHARC_M3: sprintf(info->s, "M3: %08X", (UINT32)cpustate->dag1.m[3]); break;
- case CPUINFO_STR_REGISTER + SHARC_M4: sprintf(info->s, "M4: %08X", (UINT32)cpustate->dag1.m[4]); break;
- case CPUINFO_STR_REGISTER + SHARC_M5: sprintf(info->s, "M5: %08X", (UINT32)cpustate->dag1.m[5]); break;
- case CPUINFO_STR_REGISTER + SHARC_M6: sprintf(info->s, "M6: %08X", (UINT32)cpustate->dag1.m[6]); break;
- case CPUINFO_STR_REGISTER + SHARC_M7: sprintf(info->s, "M7: %08X", (UINT32)cpustate->dag1.m[7]); break;
- case CPUINFO_STR_REGISTER + SHARC_M8: sprintf(info->s, "M8: %08X", (UINT32)cpustate->dag2.m[0]); break;
- case CPUINFO_STR_REGISTER + SHARC_M9: sprintf(info->s, "M9: %08X", (UINT32)cpustate->dag2.m[1]); break;
- case CPUINFO_STR_REGISTER + SHARC_M10: sprintf(info->s, "M10: %08X", (UINT32)cpustate->dag2.m[2]); break;
- case CPUINFO_STR_REGISTER + SHARC_M11: sprintf(info->s, "M11: %08X", (UINT32)cpustate->dag2.m[3]); break;
- case CPUINFO_STR_REGISTER + SHARC_M12: sprintf(info->s, "M12: %08X", (UINT32)cpustate->dag2.m[4]); break;
- case CPUINFO_STR_REGISTER + SHARC_M13: sprintf(info->s, "M13: %08X", (UINT32)cpustate->dag2.m[5]); break;
- case CPUINFO_STR_REGISTER + SHARC_M14: sprintf(info->s, "M14: %08X", (UINT32)cpustate->dag2.m[6]); break;
- case CPUINFO_STR_REGISTER + SHARC_M15: sprintf(info->s, "M15: %08X", (UINT32)cpustate->dag2.m[7]); break;
-
- case CPUINFO_STR_REGISTER + SHARC_L0: sprintf(info->s, "L0: %08X", (UINT32)cpustate->dag1.l[0]); break;
- case CPUINFO_STR_REGISTER + SHARC_L1: sprintf(info->s, "L1: %08X", (UINT32)cpustate->dag1.l[1]); break;
- case CPUINFO_STR_REGISTER + SHARC_L2: sprintf(info->s, "L2: %08X", (UINT32)cpustate->dag1.l[2]); break;
- case CPUINFO_STR_REGISTER + SHARC_L3: sprintf(info->s, "L3: %08X", (UINT32)cpustate->dag1.l[3]); break;
- case CPUINFO_STR_REGISTER + SHARC_L4: sprintf(info->s, "L4: %08X", (UINT32)cpustate->dag1.l[4]); break;
- case CPUINFO_STR_REGISTER + SHARC_L5: sprintf(info->s, "L5: %08X", (UINT32)cpustate->dag1.l[5]); break;
- case CPUINFO_STR_REGISTER + SHARC_L6: sprintf(info->s, "L6: %08X", (UINT32)cpustate->dag1.l[6]); break;
- case CPUINFO_STR_REGISTER + SHARC_L7: sprintf(info->s, "L7: %08X", (UINT32)cpustate->dag1.l[7]); break;
- case CPUINFO_STR_REGISTER + SHARC_L8: sprintf(info->s, "L8: %08X", (UINT32)cpustate->dag2.l[0]); break;
- case CPUINFO_STR_REGISTER + SHARC_L9: sprintf(info->s, "L9: %08X", (UINT32)cpustate->dag2.l[1]); break;
- case CPUINFO_STR_REGISTER + SHARC_L10: sprintf(info->s, "L10: %08X", (UINT32)cpustate->dag2.l[2]); break;
- case CPUINFO_STR_REGISTER + SHARC_L11: sprintf(info->s, "L11: %08X", (UINT32)cpustate->dag2.l[3]); break;
- case CPUINFO_STR_REGISTER + SHARC_L12: sprintf(info->s, "L12: %08X", (UINT32)cpustate->dag2.l[4]); break;
- case CPUINFO_STR_REGISTER + SHARC_L13: sprintf(info->s, "L13: %08X", (UINT32)cpustate->dag2.l[5]); break;
- case CPUINFO_STR_REGISTER + SHARC_L14: sprintf(info->s, "L14: %08X", (UINT32)cpustate->dag2.l[6]); break;
- case CPUINFO_STR_REGISTER + SHARC_L15: sprintf(info->s, "L15: %08X", (UINT32)cpustate->dag2.l[7]); break;
-
- case CPUINFO_STR_REGISTER + SHARC_B0: sprintf(info->s, "B0: %08X", (UINT32)cpustate->dag1.b[0]); break;
- case CPUINFO_STR_REGISTER + SHARC_B1: sprintf(info->s, "B1: %08X", (UINT32)cpustate->dag1.b[1]); break;
- case CPUINFO_STR_REGISTER + SHARC_B2: sprintf(info->s, "B2: %08X", (UINT32)cpustate->dag1.b[2]); break;
- case CPUINFO_STR_REGISTER + SHARC_B3: sprintf(info->s, "B3: %08X", (UINT32)cpustate->dag1.b[3]); break;
- case CPUINFO_STR_REGISTER + SHARC_B4: sprintf(info->s, "B4: %08X", (UINT32)cpustate->dag1.b[4]); break;
- case CPUINFO_STR_REGISTER + SHARC_B5: sprintf(info->s, "B5: %08X", (UINT32)cpustate->dag1.b[5]); break;
- case CPUINFO_STR_REGISTER + SHARC_B6: sprintf(info->s, "B6: %08X", (UINT32)cpustate->dag1.b[6]); break;
- case CPUINFO_STR_REGISTER + SHARC_B7: sprintf(info->s, "B7: %08X", (UINT32)cpustate->dag1.b[7]); break;
- case CPUINFO_STR_REGISTER + SHARC_B8: sprintf(info->s, "B8: %08X", (UINT32)cpustate->dag2.b[0]); break;
- case CPUINFO_STR_REGISTER + SHARC_B9: sprintf(info->s, "B9: %08X", (UINT32)cpustate->dag2.b[1]); break;
- case CPUINFO_STR_REGISTER + SHARC_B10: sprintf(info->s, "B10: %08X", (UINT32)cpustate->dag2.b[2]); break;
- case CPUINFO_STR_REGISTER + SHARC_B11: sprintf(info->s, "B11: %08X", (UINT32)cpustate->dag2.b[3]); break;
- case CPUINFO_STR_REGISTER + SHARC_B12: sprintf(info->s, "B12: %08X", (UINT32)cpustate->dag2.b[4]); break;
- case CPUINFO_STR_REGISTER + SHARC_B13: sprintf(info->s, "B13: %08X", (UINT32)cpustate->dag2.b[5]); break;
- case CPUINFO_STR_REGISTER + SHARC_B14: sprintf(info->s, "B14: %08X", (UINT32)cpustate->dag2.b[6]); break;
- case CPUINFO_STR_REGISTER + SHARC_B15: sprintf(info->s, "B15: %08X", (UINT32)cpustate->dag2.b[7]); break;
- }
-}
-
-CPU_GET_INFO( adsp21062 )
-{
- switch(state)
- {
- /* --- the following bits of info are returned as pointers to data or functions --- */
- case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(adsp21062); break;
-
- /* --- the following bits of info are returned as NULL-terminated strings --- */
- case CPUINFO_STR_NAME: strcpy(info->s, "ADSP21062"); break;
- case CPUINFO_STR_SHORTNAME: strcpy(info->s, "adsp21062"); break;
-
- default: CPU_GET_INFO_CALL(sharc); break;
- }
+ return false;
}
-DEFINE_LEGACY_CPU_DEVICE(ADSP21062, adsp21062);