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author | 2011-01-16 00:35:56 +0000 | |
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committer | 2011-01-16 00:35:56 +0000 | |
commit | b85af379a8d81f07b207a1f7eb2bb3b0e2f0108a (patch) | |
tree | e30d4958c66965590dae23bef1db112dec441431 /src/emu/cpu/sh4/sh4comn.h | |
parent | 74bbf1d033d67b5aedd8f1bf8b9caf1ea4fdba59 (diff) |
SH4: cleanup and better common/interpreter separation [R. Belmont]
Diffstat (limited to 'src/emu/cpu/sh4/sh4comn.h')
-rw-r--r-- | src/emu/cpu/sh4/sh4comn.h | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/src/emu/cpu/sh4/sh4comn.h b/src/emu/cpu/sh4/sh4comn.h index 810fe094cc8..d627316338e 100644 --- a/src/emu/cpu/sh4/sh4comn.h +++ b/src/emu/cpu/sh4/sh4comn.h @@ -18,6 +18,17 @@ #define VERBOSE 0 +#ifdef USE_SH4DRC +#include "cpu/drcfe.h" +#include "cpu/drcuml.h" +#include "cpu/drcumlsh.h" + +class sh4_frontend; +#endif + +#define CPU_TYPE_SH3 (2) +#define CPU_TYPE_SH4 (3) + #define LOG(x) do { if (VERBOSE) logerror x; } while (0) #define EXPPRI(pl,po,p,n) (((4-(pl)) << 24) | ((15-(po)) << 16) | ((p) << 8) | (255-(n))) @@ -99,8 +110,88 @@ typedef struct UINT32 sh4_tlb_data[64]; UINT8 sh4_mmu_enabled; +#ifdef USE_SH4DRC + int icount; + int cpu_type; + + int pcfsel; // last pcflush entry set + int maxpcfsel; // highest valid pcflush entry + UINT32 pcflushes[16]; // pcflush entries + + drc_cache * cache; /* pointer to the DRC code cache */ + drcuml_state * drcuml; /* DRC UML generator state */ + sh4_frontend * drcfe; /* pointer to the DRC front-end class */ + UINT32 drcoptions; /* configurable DRC options */ + + /* internal stuff */ + UINT8 cache_dirty; /* true if we need to flush the cache */ + + /* parameters for subroutines */ + UINT64 numcycles; /* return value from gettotalcycles */ + UINT32 arg0; /* print_debug argument 1 */ + UINT32 arg1; /* print_debug argument 2 */ + UINT32 irq; /* irq we're taking */ + + /* register mappings */ + drcuml_parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */ + + drcuml_codehandle * entry; /* entry point */ + drcuml_codehandle * read8; /* read byte */ + drcuml_codehandle * write8; /* write byte */ + drcuml_codehandle * read16; /* read half */ + drcuml_codehandle * write16; /* write half */ + drcuml_codehandle * read32; /* read word */ + drcuml_codehandle * write32; /* write word */ + + drcuml_codehandle * interrupt; /* interrupt */ + drcuml_codehandle * nocode; /* nocode */ + drcuml_codehandle * out_of_cycles; /* out of cycles exception handler */ + + UINT32 prefadr; + UINT32 target; +#endif } sh4_state; +#ifdef USE_SH4DRC +class sh4_frontend : public drc_frontend +{ +public: + sh4_frontend(sh4_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence); + +protected: + virtual bool describe(opcode_desc &desc, const opcode_desc *prev); + +private: + bool describe_group_0(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_2(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_3(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_4(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_6(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_8(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_12(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_15(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + + sh4_state &m_context; +}; + +INLINE sh4_state *get_safe_token(device_t *device) +{ + assert(device != NULL); + assert(device->type() == SH3 || + device->type() == SH4); + return *(sh4_state **)downcast<legacy_cpu_device *>(device)->token(); +} +#else +INLINE sh4_state *get_safe_token(device_t *device) +{ + assert(device != NULL); + assert(device->type() == SH3 || + device->type() == SH4); + return (sh4_state *)downcast<legacy_cpu_device *>(device)->token(); +} +#endif + + enum { ICF = 0x00800000, @@ -135,6 +226,24 @@ enum #define Rn ((opcode>>8)&15) #define Rm ((opcode>>4)&15) +#define REGFLAG_R(n) (1 << (n)) +#define REGFLAG_FR(n) (1 << (n)) +#define REGFLAG_XR(n) (1 << (n)) + +/* register flags 1 */ +#define REGFLAG_PR (1 << 0) +#define REGFLAG_MACL (1 << 1) +#define REGFLAG_MACH (1 << 2) +#define REGFLAG_GBR (1 << 3) +#define REGFLAG_VBR (1 << 4) +#define REGFLAG_SR (1 << 5) +#define REGFLAG_SGR (1 << 6) +#define REGFLAG_FPUL (1 << 7) +#define REGFLAG_FPSCR (1 << 8) +#define REGFLAG_DBR (1 << 9) +#define REGFLAG_SSR (1 << 10) +#define REGFLAG_SPC (1 << 11) + void sh4_exception_recompute(sh4_state *sh4); // checks if there is any interrupt with high enough priority void sh4_exception_request(sh4_state *sh4, int exception); // start requesting an exception void sh4_exception_unrequest(sh4_state *sh4, int exception); // stop requesting an exception @@ -150,6 +259,10 @@ void sh4_set_irq_line(sh4_state *sh4, int irqline, int state); // set state of e void sh4_swap_fp_couples(sh4_state *sh4); #endif void sh4_common_init(device_t *device); +UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address); + +READ64_HANDLER( sh4_tlb_r ); +WRITE64_HANDLER( sh4_tlb_w ); INLINE void sh4_check_pending_irq(sh4_state *sh4, const char *message) // look for highest priority active exception and handle it { |