diff options
author | 2008-12-10 05:14:09 +0000 | |
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committer | 2008-12-10 05:14:09 +0000 | |
commit | 36d63663d354f79af5898a4666d4e4e7ccc278a3 (patch) | |
tree | 0de72604b8b054b6bb56f63b84d5079cbf4fa8f4 /src/emu/cpu/i386/pentops.c | |
parent | 129c08982ee3754dd1abcb1bb4764e667e71c042 (diff) |
Pointer-ified the i386.
Diffstat (limited to 'src/emu/cpu/i386/pentops.c')
-rw-r--r-- | src/emu/cpu/i386/pentops.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/emu/cpu/i386/pentops.c b/src/emu/cpu/i386/pentops.c index b7fb394e301..6a6ee1aa187 100644 --- a/src/emu/cpu/i386/pentops.c +++ b/src/emu/cpu/i386/pentops.c @@ -1,51 +1,51 @@ // Pentium+ specific opcodes -static void PENTIUMOP(rdmsr)(void) // Opcode 0x0f 32 +static void PENTIUMOP(rdmsr)(i386_state *cpustate) // Opcode 0x0f 32 { // TODO - CYCLES(CYCLES_RDMSR); + CYCLES(cpustate,CYCLES_RDMSR); } -static void PENTIUMOP(wrmsr)(void) // Opcode 0x0f 30 +static void PENTIUMOP(wrmsr)(i386_state *cpustate) // Opcode 0x0f 30 { // TODO - CYCLES(1); // TODO: correct cycle count + CYCLES(cpustate,1); // TODO: correct cycle count } -static void PENTIUMOP(rdtsc)(void) // Opcode 0x0f 31 +static void PENTIUMOP(rdtsc)(i386_state *cpustate) // Opcode 0x0f 31 { - UINT64 ts = I.tsc + (I.base_cycles - I.cycles); + UINT64 ts = cpustate->tsc + (cpustate->base_cycles - cpustate->cycles); REG32(EAX) = (UINT32)(ts); REG32(EDX) = (UINT32)(ts >> 32); - CYCLES(CYCLES_RDTSC); + CYCLES(cpustate,CYCLES_RDTSC); } -static void I386OP(cyrix_unknown)(void) // Opcode 0x0f 74 +static void I386OP(cyrix_unknown)(i386_state *cpustate) // Opcode 0x0f 74 { - CYCLES(1); + CYCLES(cpustate,1); } -static void PENTIUMOP(cmpxchg8b_m64)(void) // Opcode 0x0f c7 +static void PENTIUMOP(cmpxchg8b_m64)(i386_state *cpustate) // Opcode 0x0f c7 { - UINT8 modm = FETCH(); + UINT8 modm = FETCH(cpustate); if( modm >= 0xc0 ) { fatalerror("invalid modm"); } else { - UINT32 ea = GetEA(modm); - UINT64 value = READ64(ea); + UINT32 ea = GetEA(cpustate,modm); + UINT64 value = READ64(cpustate,ea); UINT64 edx_eax = (((UINT64) REG32(EDX)) << 32) | REG32(EAX); UINT64 ecx_ebx = (((UINT64) REG32(ECX)) << 32) | REG32(EBX); if( value == edx_eax ) { - WRITE64(ea, ecx_ebx); - I.ZF = 1; - CYCLES(CYCLES_CMPXCHG_REG_MEM_T); + WRITE64(cpustate,ea, ecx_ebx); + cpustate->ZF = 1; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T); } else { REG32(EDX) = (UINT32) (value >> 32); REG32(EAX) = (UINT32) (value >> 0); - I.ZF = 0; - CYCLES(CYCLES_CMPXCHG_REG_MEM_F); + cpustate->ZF = 0; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F); } } } |