diff options
author | 2013-01-11 07:32:46 +0000 | |
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committer | 2013-01-11 07:32:46 +0000 | |
commit | 0e19f641d3186cdbf51f8ca857e2b07ab95779c2 (patch) | |
tree | 234109de1123b13f217494af4b3f8efad346d5cc /src/emu/cpu/f8 | |
parent | 111157ca09a9ff60fe4a9ba49173c315e94314fa (diff) |
Cleanups and version bumpmame0148
Diffstat (limited to 'src/emu/cpu/f8')
-rw-r--r-- | src/emu/cpu/f8/f8.c | 2002 | ||||
-rw-r--r-- | src/emu/cpu/f8/f8.h | 20 | ||||
-rw-r--r-- | src/emu/cpu/f8/f8dasm.c | 307 |
3 files changed, 1164 insertions, 1165 deletions
diff --git a/src/emu/cpu/f8/f8.c b/src/emu/cpu/f8/f8.c index be67cf7a2ac..605056e99e2 100644 --- a/src/emu/cpu/f8/f8.c +++ b/src/emu/cpu/f8/f8.c @@ -30,26 +30,26 @@ #include "debugger.h" #include "f8.h" -#define S 0x01 -#define C 0x02 -#define Z 0x04 -#define O 0x08 -#define I 0x10 +#define S 0x01 +#define C 0x02 +#define Z 0x04 +#define O 0x08 +#define I 0x10 #define cS 4 -#define cL 6 +#define cL 6 struct f8_Regs { - UINT16 pc0; /* program counter 0 */ - UINT16 pc1; /* program counter 1 */ - UINT16 dc0; /* data counter 0 */ - UINT16 dc1; /* data counter 1 */ - UINT8 a; /* accumulator */ - UINT8 w; /* processor status */ - UINT8 is; /* scratchpad pointer */ - UINT8 dbus; /* data bus value */ - UINT16 io; /* last I/O address */ + UINT16 pc0; /* program counter 0 */ + UINT16 pc1; /* program counter 1 */ + UINT16 dc0; /* data counter 0 */ + UINT16 dc1; /* data counter 1 */ + UINT8 a; /* accumulator */ + UINT8 w; /* processor status */ + UINT8 is; /* scratchpad pointer */ + UINT8 dbus; /* data bus value */ + UINT16 io; /* last I/O address */ UINT16 irq_vector; device_irq_acknowledge_callback irq_callback; legacy_cpu_device *device; @@ -77,25 +77,25 @@ static UINT8 timer_shifter[256]; /* set sign and zero flags (note: the S flag is complementary) */ #define SET_SZ(n) \ - if (n == 0) \ - cpustate->w |= Z | S; \ - else \ - if (n < 128) \ + if (n == 0) \ + cpustate->w |= Z | S; \ + else \ + if (n < 128) \ cpustate->w |= S /* set overflow and carry flags */ #define SET_OC(n,m) \ - if (n + m > 255) \ - cpustate->w |= C; \ - if ((n&127)+(m&127) > 127) \ - { \ - if (!(cpustate->w & C)) \ - cpustate->w |= O; \ - } \ - else \ - { \ - if (cpustate->w & C) \ - cpustate->w |= O; \ + if (n + m > 255) \ + cpustate->w |= C; \ + if ((n&127)+(m&127) > 127) \ + { \ + if (!(cpustate->w & C)) \ + cpustate->w |= O; \ + } \ + else \ + { \ + if (cpustate->w & C) \ + cpustate->w |= O; \ } /****************************************************************************** @@ -108,367 +108,367 @@ static UINT8 timer_shifter[256]; * Currently the emulation does not handle distinct PCs and DCs, but * only one instance inside the CPU context. ******************************************************************************/ -static void ROMC_00(f8_Regs *cpustate, int insttim) /* SKR - added parameter to tell if */ - /* it is long or short based on inst */ +static void ROMC_00(f8_Regs *cpustate, int insttim) /* SKR - added parameter to tell if */ + /* it is long or short based on inst */ { - /* - * Instruction Fetch. The device whose address space includes the - * contents of the PC0 register must place on the data bus the op - * code addressed by PC0; then all devices increment the contents - * of PC0. - */ + /* + * Instruction Fetch. The device whose address space includes the + * contents of the PC0 register must place on the data bus the op + * code addressed by PC0; then all devices increment the contents + * of PC0. + */ cpustate->dbus = cpustate->direct->read_decrypted_byte(cpustate->pc0); - cpustate->pc0 += 1; - cpustate->icount -= insttim; /* SKR - ROMC00 is usually short, not short+long, */ - /* but DS is long */ + cpustate->pc0 += 1; + cpustate->icount -= insttim; /* SKR - ROMC00 is usually short, not short+long, */ + /* but DS is long */ } static void ROMC_01(f8_Regs *cpustate) { - /* - * The device whose address space includes the contents of the PC0 - * register must place on the data bus the contents of the memory - * location addressed by PC0; then all devices add the 8-bit value - * on the data bus as signed binary number to PC0. - */ + /* + * The device whose address space includes the contents of the PC0 + * register must place on the data bus the contents of the memory + * location addressed by PC0; then all devices add the 8-bit value + * on the data bus as signed binary number to PC0. + */ cpustate->dbus = cpustate->direct->read_raw_byte(cpustate->pc0); cpustate->pc0 += (INT8)cpustate->dbus; - cpustate->icount -= cL; + cpustate->icount -= cL; } static void ROMC_02(f8_Regs *cpustate) { - /* - * The device whose DC0 addresses a memory word within the address - * space of that device must place on the data bus the contents of - * the memory location addressed by DC0; then all devices increment - * DC0. - */ - cpustate->dbus = cpustate->program->read_byte(cpustate->dc0); - cpustate->dc0 += 1; - cpustate->icount -= cL; + /* + * The device whose DC0 addresses a memory word within the address + * space of that device must place on the data bus the contents of + * the memory location addressed by DC0; then all devices increment + * DC0. + */ + cpustate->dbus = cpustate->program->read_byte(cpustate->dc0); + cpustate->dc0 += 1; + cpustate->icount -= cL; } -static void ROMC_03(f8_Regs *cpustate, int insttim) /* SKR - added parameter to tell if */ +static void ROMC_03(f8_Regs *cpustate, int insttim) /* SKR - added parameter to tell if */ { /* it is long or short based on inst */ - /* - * Similiar to 0x00, except that it is used for immediate operands - * fetches (using PC0) instead of instruction fetches. - */ - cpustate->dbus = cpustate->io = cpustate->direct->read_raw_byte(cpustate->pc0); - cpustate->pc0 += 1; - cpustate->icount -= insttim; + /* + * Similiar to 0x00, except that it is used for immediate operands + * fetches (using PC0) instead of instruction fetches. + */ + cpustate->dbus = cpustate->io = cpustate->direct->read_raw_byte(cpustate->pc0); + cpustate->pc0 += 1; + cpustate->icount -= insttim; } static void ROMC_04(f8_Regs *cpustate) { - /* - * Copy the contents of PC1 into PC0 - */ - cpustate->pc0 = cpustate->pc1; - cpustate->icount -= cS; + /* + * Copy the contents of PC1 into PC0 + */ + cpustate->pc0 = cpustate->pc1; + cpustate->icount -= cS; } static void ROMC_05(f8_Regs *cpustate) { - /* - * Store the data bus contents into the memory location pointed - * to by DC0; increment DC0. - */ - cpustate->program->write_byte(cpustate->dc0, cpustate->dbus); - cpustate->dc0 += 1; - cpustate->icount -= cL; + /* + * Store the data bus contents into the memory location pointed + * to by DC0; increment DC0. + */ + cpustate->program->write_byte(cpustate->dc0, cpustate->dbus); + cpustate->dc0 += 1; + cpustate->icount -= cL; } static void ROMC_06(f8_Regs *cpustate) { - /* - * Place the high order byte of DC0 on the data bus. - */ - cpustate->dbus = cpustate->dc0 >> 8; - cpustate->icount -= cL; + /* + * Place the high order byte of DC0 on the data bus. + */ + cpustate->dbus = cpustate->dc0 >> 8; + cpustate->icount -= cL; } static void ROMC_07(f8_Regs *cpustate) { - /* - * Place the high order byte of PC1 on the data bus. - */ - cpustate->dbus = cpustate->pc1 >> 8; - cpustate->icount -= cL; + /* + * Place the high order byte of PC1 on the data bus. + */ + cpustate->dbus = cpustate->pc1 >> 8; + cpustate->icount -= cL; } static void ROMC_08(f8_Regs *cpustate) { - /* - * All devices copy the contents of PC0 into PC1. The CPU outputs - * zero on the data bus in this ROMC state. Load the data bus into - * both halves of PC0, thus clearing the register. - */ - cpustate->pc1 = cpustate->pc0; - cpustate->dbus = 0; - cpustate->pc0 = 0; - cpustate->icount -= cL; + /* + * All devices copy the contents of PC0 into PC1. The CPU outputs + * zero on the data bus in this ROMC state. Load the data bus into + * both halves of PC0, thus clearing the register. + */ + cpustate->pc1 = cpustate->pc0; + cpustate->dbus = 0; + cpustate->pc0 = 0; + cpustate->icount -= cL; } static void ROMC_09(f8_Regs *cpustate) { - /* - * The device whose address space includes the contents of the DC0 - * register must place the low order byte of DC0 onto the data bus. - */ - cpustate->dbus = cpustate->dc0 & 0xff; - cpustate->icount -= cL; + /* + * The device whose address space includes the contents of the DC0 + * register must place the low order byte of DC0 onto the data bus. + */ + cpustate->dbus = cpustate->dc0 & 0xff; + cpustate->icount -= cL; } static void ROMC_0A(f8_Regs *cpustate) { - /* - * All devices add the 8-bit value on the data bus, treated as - * signed binary number, to the data counter. - */ - cpustate->dc0 += (INT8)cpustate->dbus; - cpustate->icount -= cL; + /* + * All devices add the 8-bit value on the data bus, treated as + * signed binary number, to the data counter. + */ + cpustate->dc0 += (INT8)cpustate->dbus; + cpustate->icount -= cL; } static void ROMC_0B(f8_Regs *cpustate) { - /* - * The device whose address space includes the value in PC1 - * must place the low order byte of PC1 onto the data bus. - */ - cpustate->dbus = cpustate->pc1 & 0xff; - cpustate->icount -= cL; + /* + * The device whose address space includes the value in PC1 + * must place the low order byte of PC1 onto the data bus. + */ + cpustate->dbus = cpustate->pc1 & 0xff; + cpustate->icount -= cL; } static void ROMC_0C(f8_Regs *cpustate) { - /* - * The device whose address space includes the contents of the PC0 - * register must place the contents of the memory word addressed - * by PC0 into the data bus; then all devices move the value that - * has just been placed on the data bus into the low order byte of PC0. - */ - cpustate->dbus = cpustate->direct->read_raw_byte(cpustate->pc0); - cpustate->pc0 = (cpustate->pc0 & 0xff00) | cpustate->dbus; - cpustate->icount -= cL; + /* + * The device whose address space includes the contents of the PC0 + * register must place the contents of the memory word addressed + * by PC0 into the data bus; then all devices move the value that + * has just been placed on the data bus into the low order byte of PC0. + */ + cpustate->dbus = cpustate->direct->read_raw_byte(cpustate->pc0); + cpustate->pc0 = (cpustate->pc0 & 0xff00) | cpustate->dbus; + cpustate->icount -= cL; } static void ROMC_0D(f8_Regs *cpustate) { - /* - * All devices store in PC1 the current contents of PC0, incremented - * by 1; PC0 is unaltered. - */ - cpustate->pc1 = cpustate->pc0 + 1; - cpustate->icount -= cS; + /* + * All devices store in PC1 the current contents of PC0, incremented + * by 1; PC0 is unaltered. + */ + cpustate->pc1 = cpustate->pc0 + 1; + cpustate->icount -= cS; } static void ROMC_0E(f8_Regs *cpustate) { - /* - * The device whose address space includes the contents of the PC0 - * register must place the word addressed by PC0 into the data bus. - * The value on the data bus is then moved to the low order byte - * of DC0 by all devices. - */ - cpustate->dbus = cpustate->direct->read_raw_byte(cpustate->pc0); - cpustate->dc0 = (cpustate->dc0 & 0xff00) | cpustate->dbus; - cpustate->icount -= cL; + /* + * The device whose address space includes the contents of the PC0 + * register must place the word addressed by PC0 into the data bus. + * The value on the data bus is then moved to the low order byte + * of DC0 by all devices. + */ + cpustate->dbus = cpustate->direct->read_raw_byte(cpustate->pc0); + cpustate->dc0 = (cpustate->dc0 & 0xff00) | cpustate->dbus; + cpustate->icount -= cL; } static void ROMC_0F(f8_Regs *cpustate) { - /* - * The interrupting device with highest priority must place the - * low order byte of the interrupt vector on the data bus. - * All devices must copy the contents of PC0 into PC1. All devices - * must move the contents of the data bus into the low order - * byte of PC0. - */ - cpustate->irq_vector = (*cpustate->irq_callback)(cpustate->device, F8_INPUT_LINE_INT_REQ); - cpustate->dbus = cpustate->irq_vector & 0x00ff; - cpustate->pc1 = cpustate->pc0; - cpustate->pc0 = (cpustate->pc0 & 0xff00) | cpustate->dbus; - cpustate->icount -= cL; + /* + * The interrupting device with highest priority must place the + * low order byte of the interrupt vector on the data bus. + * All devices must copy the contents of PC0 into PC1. All devices + * must move the contents of the data bus into the low order + * byte of PC0. + */ + cpustate->irq_vector = (*cpustate->irq_callback)(cpustate->device, F8_INPUT_LINE_INT_REQ); + cpustate->dbus = cpustate->irq_vector & 0x00ff; + cpustate->pc1 = cpustate->pc0; + cpustate->pc0 = (cpustate->pc0 & 0xff00) | cpustate->dbus; + cpustate->icount -= cL; } #ifdef UNUSED_FUNCTION static void ROMC_10(f8_Regs *cpustate) { - /* - * Inhibit any modification to the interrupt priority logic. - */ - cpustate->w |= 0x20; /* ???? */ - cpustate->icount -= cL; + /* + * Inhibit any modification to the interrupt priority logic. + */ + cpustate->w |= 0x20; /* ???? */ + cpustate->icount -= cL; } #endif static void ROMC_11(f8_Regs *cpustate) { - /* - * The device whose address space includes the contents of PC0 - * must place the contents of the addressed memory word on the - * data bus. All devices must then move the contents of the - * data bus to the upper byte of DC0. - */ - cpustate->dbus = cpustate->direct->read_raw_byte(cpustate->pc0); + /* + * The device whose address space includes the contents of PC0 + * must place the contents of the addressed memory word on the + * data bus. All devices must then move the contents of the + * data bus to the upper byte of DC0. + */ + cpustate->dbus = cpustate->direct->read_raw_byte(cpustate->pc0); cpustate->dc0 = (cpustate->dc0 & 0x00ff) | (cpustate->dbus << 8); - cpustate->icount -= cL; + cpustate->icount -= cL; } static void ROMC_12(f8_Regs *cpustate) { - /* - * All devices copy the contents of PC0 into PC1. All devices then - * move the contents of the data bus into the low order byte of PC0. - */ - cpustate->pc1 = cpustate->pc0; - cpustate->pc0 = (cpustate->pc0 & 0xff00) | cpustate->dbus; - cpustate->icount -= cL; + /* + * All devices copy the contents of PC0 into PC1. All devices then + * move the contents of the data bus into the low order byte of PC0. + */ + cpustate->pc1 = cpustate->pc0; + cpustate->pc0 = (cpustate->pc0 & 0xff00) | cpustate->dbus; + cpustate->icount -= cL; } static void ROMC_13(f8_Regs *cpustate) { - /* - * The interrupting device with highest priority must move the high - * order half of the interrupt vector onto the data bus. All devices - * must then move the contents of the data bus into the high order - * byte of PC0. The interrupting device resets its interrupt circuitry - * (so that it is no longer requesting CPU servicing and can respond - * to another interrupt). - */ - cpustate->dbus = cpustate->irq_vector >> 8; - cpustate->pc0 = (cpustate->pc0 & 0x00ff) | (cpustate->dbus << 8); - cpustate->w&=~I; - cpustate->icount -= cL; + /* + * The interrupting device with highest priority must move the high + * order half of the interrupt vector onto the data bus. All devices + * must then move the contents of the data bus into the high order + * byte of PC0. The interrupting device resets its interrupt circuitry + * (so that it is no longer requesting CPU servicing and can respond + * to another interrupt). + */ + cpustate->dbus = cpustate->irq_vector >> 8; + cpustate->pc0 = (cpustate->pc0 & 0x00ff) | (cpustate->dbus << 8); + cpustate->w&=~I; + cpustate->icount -= cL; } static void ROMC_14(f8_Regs *cpustate) { - /* - * All devices move the contents of the data bus into the high - * order byte of PC0. - */ - cpustate->pc0 = (cpustate->pc0 & 0x00ff) | (cpustate->dbus << 8); - cpustate->icount -= cL; + /* + * All devices move the contents of the data bus into the high + * order byte of PC0. + */ + cpustate->pc0 = (cpustate->pc0 & 0x00ff) | (cpustate->dbus << 8); + cpustate->icount -= cL; } static void ROMC_15(f8_Regs *cpustate) { - /* - * All devices move the contents of the data bus into the high - * order byte of PC1. - */ - cpustate->pc1 = (cpustate->pc1 & 0x00ff) | (cpustate->dbus << 8); - cpustate->icount -= cL; + /* + * All devices move the contents of the data bus into the high + * order byte of PC1. + */ + cpustate->pc1 = (cpustate->pc1 & 0x00ff) | (cpustate->dbus << 8); + cpustate->icount -= cL; } static void ROMC_16(f8_Regs *cpustate) { - /* - * All devices move the contents of the data bus into the high - * order byte of DC0. - */ - cpustate->dc0 = (cpustate->dc0 & 0x00ff) | (cpustate->dbus << 8); - cpustate->icount -= cL; + /* + * All devices move the contents of the data bus into the high + * order byte of DC0. + */ + cpustate->dc0 = (cpustate->dc0 & 0x00ff) | (cpustate->dbus << 8); + cpustate->icount -= cL; } static void ROMC_17(f8_Regs *cpustate) { - /* - * All devices move the contents of the data bus into the low - * order byte of PC0. - */ - cpustate->pc0 = (cpustate->pc0 & 0xff00) | cpustate->dbus; - cpustate->icount -= cL; + /* + * All devices move the contents of the data bus into the low + * order byte of PC0. + */ + cpustate->pc0 = (cpustate->pc0 & 0xff00) | cpustate->dbus; + cpustate->icount -= cL; } static void ROMC_18(f8_Regs *cpustate) { - /* - * All devices move the contents of the data bus into the low - * order byte of PC1. - */ - cpustate->pc1 = (cpustate->pc1 & 0xff00) | cpustate->dbus; - cpustate->icount -= cL; + /* + * All devices move the contents of the data bus into the low + * order byte of PC1. + */ + cpustate->pc1 = (cpustate->pc1 & 0xff00) | cpustate->dbus; + cpustate->icount -= cL; } static void ROMC_19(f8_Regs *cpustate) { - /* - * All devices move the contents of the data bus into the low - * order byte of DC0. - */ - cpustate->dc0 = (cpustate->dc0 & 0xff00) | cpustate->dbus; - cpustate->icount -= cL; + /* + * All devices move the contents of the data bus into the low + * order byte of DC0. + */ + cpustate->dc0 = (cpustate->dc0 & 0xff00) | cpustate->dbus; + cpustate->icount -= cL; } static void ROMC_1A(f8_Regs *cpustate) { - /* - * During the prior cycle, an I/O port timer or interrupt control - * register was addressed; the device containing the addressed port - * must place the contents of the data bus into the address port. - */ - cpustate->iospace->write_byte(cpustate->io, cpustate->dbus); - cpustate->icount -= cL; + /* + * During the prior cycle, an I/O port timer or interrupt control + * register was addressed; the device containing the addressed port + * must place the contents of the data bus into the address port. + */ + cpustate->iospace->write_byte(cpustate->io, cpustate->dbus); + cpustate->icount -= cL; } static void ROMC_1B(f8_Regs *cpustate) { - /* - * During the prior cycle, the data bus specified the address of an - * I/O port. The device containing the addressed I/O port must place - * the contents of the I/O port on the data bus. (Note that the - * contents of timer and interrupt control registers cannot be read - * back onto the data bus). - */ + /* + * During the prior cycle, the data bus specified the address of an + * I/O port. The device containing the addressed I/O port must place + * the contents of the I/O port on the data bus. (Note that the + * contents of timer and interrupt control registers cannot be read + * back onto the data bus). + */ cpustate->dbus = cpustate->iospace->read_byte(cpustate->io); - cpustate->icount -= cL; + cpustate->icount -= cL; } -static void ROMC_1C(f8_Regs *cpustate, int insttim) /* SKR - added parameter to tell if */ - /* it is long or short based on inst */ +static void ROMC_1C(f8_Regs *cpustate, int insttim) /* SKR - added parameter to tell if */ + /* it is long or short based on inst */ { - /* - * None. - */ - cpustate->icount -= insttim; + /* + * None. + */ + cpustate->icount -= insttim; } static void ROMC_1D(f8_Regs *cpustate) { - /* - * Devices with DC0 and DC1 registers must switch registers. - * Devices without a DC1 register perform no operation. - */ - UINT16 tmp = cpustate->dc0; - cpustate->dc0 = cpustate->dc1; - cpustate->dc1 = tmp; - cpustate->icount -= cS; + /* + * Devices with DC0 and DC1 registers must switch registers. + * Devices without a DC1 register perform no operation. + */ + UINT16 tmp = cpustate->dc0; + cpustate->dc0 = cpustate->dc1; + cpustate->dc1 = tmp; + cpustate->icount -= cS; } #ifdef UNUSED_FUNCTION static void ROMC_1E(f8_Regs *cpustate) { - /* - * The devices whose address space includes the contents of PC0 - * must place the low order byte of PC0 onto the data bus. - */ - cpustate->dbus = cpustate->pc0 & 0xff; - cpustate->icount -= cL; + /* + * The devices whose address space includes the contents of PC0 + * must place the low order byte of PC0 onto the data bus. + */ + cpustate->dbus = cpustate->pc0 & 0xff; + cpustate->icount -= cL; } static void ROMC_1F(f8_Regs *cpustate) { - /* - * The devices whose address space includes the contents of PC0 - * must place the high order byte of PC0 onto the data bus. - */ - cpustate->dbus = (cpustate->pc0 >> 8) & 0xff; - cpustate->icount -= cL; + /* + * The devices whose address space includes the contents of PC0 + * must place the high order byte of PC0 onto the data bus. + */ + cpustate->dbus = (cpustate->pc0 >> 8) & 0xff; + cpustate->icount -= cL; } #endif @@ -477,7 +477,7 @@ static void ROMC_1F(f8_Regs *cpustate) ***********************************/ static void illegal(f8_Regs *cpustate) { - logerror("f8 illegal opcode at 0x%04x: %02x\n", cpustate->pc0, cpustate->dbus); + logerror("f8 illegal opcode at 0x%04x: %02x\n", cpustate->pc0, cpustate->dbus); } /*************************************************** @@ -486,7 +486,7 @@ static void illegal(f8_Regs *cpustate) ***************************************************/ static void f8_lr_a_ku(f8_Regs *cpustate) { - cpustate->a = cpustate->r[12]; + cpustate->a = cpustate->r[12]; } /*************************************************** @@ -495,7 +495,7 @@ static void f8_lr_a_ku(f8_Regs *cpustate) ***************************************************/ static void f8_lr_a_kl(f8_Regs *cpustate) { - cpustate->a = cpustate->r[13]; + cpustate->a = cpustate->r[13]; } /*************************************************** @@ -504,7 +504,7 @@ static void f8_lr_a_kl(f8_Regs *cpustate) ***************************************************/ static void f8_lr_a_qu(f8_Regs *cpustate) { - cpustate->a = cpustate->r[14]; + cpustate->a = cpustate->r[14]; } /*************************************************** @@ -513,7 +513,7 @@ static void f8_lr_a_qu(f8_Regs *cpustate) ***************************************************/ static void f8_lr_a_ql(f8_Regs *cpustate) { - cpustate->a = cpustate->r[15]; + cpustate->a = cpustate->r[15]; } /*************************************************** @@ -522,7 +522,7 @@ static void f8_lr_a_ql(f8_Regs *cpustate) ***************************************************/ static void f8_lr_ku_a(f8_Regs *cpustate) { - cpustate->r[12] = cpustate->a; + cpustate->r[12] = cpustate->a; } /*************************************************** @@ -531,7 +531,7 @@ static void f8_lr_ku_a(f8_Regs *cpustate) ***************************************************/ static void f8_lr_kl_a(f8_Regs *cpustate) { - cpustate->r[13] = cpustate->a; + cpustate->r[13] = cpustate->a; } /*************************************************** @@ -540,7 +540,7 @@ static void f8_lr_kl_a(f8_Regs *cpustate) ***************************************************/ static void f8_lr_qu_a(f8_Regs *cpustate) { - cpustate->r[14] = cpustate->a; + cpustate->r[14] = cpustate->a; } /*************************************************** @@ -549,7 +549,7 @@ static void f8_lr_qu_a(f8_Regs *cpustate) ***************************************************/ static void f8_lr_ql_a(f8_Regs *cpustate) { - cpustate->r[15] = cpustate->a; + cpustate->r[15] = cpustate->a; } /*************************************************** @@ -558,10 +558,10 @@ static void f8_lr_ql_a(f8_Regs *cpustate) ***************************************************/ static void f8_lr_k_p(f8_Regs *cpustate) { - ROMC_07(cpustate); - cpustate->r[12] = cpustate->dbus; - ROMC_0B(cpustate); - cpustate->r[13] = cpustate->dbus; + ROMC_07(cpustate); + cpustate->r[12] = cpustate->dbus; + ROMC_0B(cpustate); + cpustate->r[13] = cpustate->dbus; } /*************************************************** @@ -570,10 +570,10 @@ static void f8_lr_k_p(f8_Regs *cpustate) ***************************************************/ static void f8_lr_p_k(f8_Regs *cpustate) { - cpustate->dbus = cpustate->r[12]; - ROMC_15(cpustate); - cpustate->dbus = cpustate->r[13]; - ROMC_18(cpustate); + cpustate->dbus = cpustate->r[12]; + ROMC_15(cpustate); + cpustate->dbus = cpustate->r[13]; + ROMC_18(cpustate); } /*************************************************** @@ -582,7 +582,7 @@ static void f8_lr_p_k(f8_Regs *cpustate) ***************************************************/ static void f8_lr_a_is(f8_Regs *cpustate) { - cpustate->a = cpustate->is; + cpustate->a = cpustate->is; } /*************************************************** @@ -591,7 +591,7 @@ static void f8_lr_a_is(f8_Regs *cpustate) ***************************************************/ static void f8_lr_is_a(f8_Regs *cpustate) { - cpustate->is = cpustate->a & 0x3f; + cpustate->is = cpustate->a & 0x3f; } /*************************************************** @@ -600,10 +600,10 @@ static void f8_lr_is_a(f8_Regs *cpustate) ***************************************************/ static void f8_pk(f8_Regs *cpustate) { - cpustate->dbus = cpustate->r[13]; - ROMC_12(cpustate); - cpustate->dbus = cpustate->r[12]; - ROMC_14(cpustate); + cpustate->dbus = cpustate->r[13]; + ROMC_12(cpustate); + cpustate->dbus = cpustate->r[12]; + ROMC_14(cpustate); } /*************************************************** @@ -612,10 +612,10 @@ static void f8_pk(f8_Regs *cpustate) ***************************************************/ static void f8_lr_p0_q(f8_Regs *cpustate) { - cpustate->dbus = cpustate->r[15]; - ROMC_17(cpustate); - cpustate->dbus = cpustate->r[14]; - ROMC_14(cpustate); + cpustate->dbus = cpustate->r[15]; + ROMC_17(cpustate); + cpustate->dbus = cpustate->r[14]; + ROMC_14(cpustate); } /*************************************************** @@ -624,10 +624,10 @@ static void f8_lr_p0_q(f8_Regs *cpustate) ***************************************************/ static void f8_lr_q_dc(f8_Regs *cpustate) { - ROMC_06(cpustate); - cpustate->r[14] = cpustate->dbus; - ROMC_09(cpustate); - cpustate->r[15] = cpustate->dbus; + ROMC_06(cpustate); + cpustate->r[14] = cpustate->dbus; + ROMC_09(cpustate); + cpustate->r[15] = cpustate->dbus; } /*************************************************** @@ -636,10 +636,10 @@ static void f8_lr_q_dc(f8_Regs *cpustate) ***************************************************/ static void f8_lr_dc_q(f8_Regs *cpustate) { - cpustate->dbus = cpustate->r[14]; - ROMC_16(cpustate); - cpustate->dbus = cpustate->r[15]; - ROMC_19(cpustate); + cpustate->dbus = cpustate->r[14]; + ROMC_16(cpustate); + cpustate->dbus = cpustate->r[15]; + ROMC_19(cpustate); } /*************************************************** @@ -648,10 +648,10 @@ static void f8_lr_dc_q(f8_Regs *cpustate) ***************************************************/ static void f8_lr_dc_h(f8_Regs *cpustate) { - cpustate->dbus = cpustate->r[10]; - ROMC_16(cpustate); - cpustate->dbus = cpustate->r[11]; - ROMC_19(cpustate); + cpustate->dbus = cpustate->r[10]; + ROMC_16(cpustate); + cpustate->dbus = cpustate->r[11]; + ROMC_19(cpustate); } /*************************************************** @@ -660,10 +660,10 @@ static void f8_lr_dc_h(f8_Regs *cpustate) ***************************************************/ static void f8_lr_h_dc(f8_Regs *cpustate) { - ROMC_06(cpustate); - cpustate->r[10] = cpustate->dbus; - ROMC_09(cpustate); - cpustate->r[11] = cpustate->dbus; + ROMC_06(cpustate); + cpustate->r[10] = cpustate->dbus; + ROMC_09(cpustate); + cpustate->r[11] = cpustate->dbus; } /*************************************************** @@ -672,9 +672,9 @@ static void f8_lr_h_dc(f8_Regs *cpustate) ***************************************************/ static void f8_sr_1(f8_Regs *cpustate) { - cpustate->a >>= 1; - CLR_OZCS; - SET_SZ(cpustate->a); + cpustate->a >>= 1; + CLR_OZCS; + SET_SZ(cpustate->a); } /*************************************************** @@ -683,9 +683,9 @@ static void f8_sr_1(f8_Regs *cpustate) ***************************************************/ static void f8_sl_1(f8_Regs *cpustate) { - cpustate->a <<= 1; - CLR_OZCS; - SET_SZ(cpustate->a); + cpustate->a <<= 1; + CLR_OZCS; + SET_SZ(cpustate->a); } /*************************************************** @@ -694,9 +694,9 @@ static void f8_sl_1(f8_Regs *cpustate) ***************************************************/ static void f8_sr_4(f8_Regs *cpustate) { - cpustate->a >>= 4; - CLR_OZCS; - SET_SZ(cpustate->a); + cpustate->a >>= 4; + CLR_OZCS; + SET_SZ(cpustate->a); } /*************************************************** @@ -705,9 +705,9 @@ static void f8_sr_4(f8_Regs *cpustate) ***************************************************/ static void f8_sl_4(f8_Regs *cpustate) { - cpustate->a <<= 4; - CLR_OZCS; - SET_SZ(cpustate->a); + cpustate->a <<= 4; + CLR_OZCS; + SET_SZ(cpustate->a); } /*************************************************** @@ -716,8 +716,8 @@ static void f8_sl_4(f8_Regs *cpustate) ***************************************************/ static void f8_lm(f8_Regs *cpustate) { - ROMC_02(cpustate); - cpustate->a = cpustate->dbus; + ROMC_02(cpustate); + cpustate->a = cpustate->dbus; } /*************************************************** @@ -726,8 +726,8 @@ static void f8_lm(f8_Regs *cpustate) ***************************************************/ static void f8_st(f8_Regs *cpustate) { - cpustate->dbus = cpustate->a; - ROMC_05(cpustate); + cpustate->dbus = cpustate->a; + ROMC_05(cpustate); } /*************************************************** @@ -736,9 +736,9 @@ static void f8_st(f8_Regs *cpustate) ***************************************************/ static void f8_com(f8_Regs *cpustate) { - cpustate->a = ~cpustate->a; - CLR_OZCS; - SET_SZ(cpustate->a); + cpustate->a = ~cpustate->a; + CLR_OZCS; + SET_SZ(cpustate->a); } /*************************************************** @@ -747,17 +747,17 @@ static void f8_com(f8_Regs *cpustate) ***************************************************/ static void f8_lnk(f8_Regs *cpustate) { - if (cpustate->w & C) - { + if (cpustate->w & C) + { CLR_OZCS; SET_OC(cpustate->a,1); cpustate->a += 1; - } - else - { + } + else + { CLR_OZCS; - } - SET_SZ(cpustate->a); + } + SET_SZ(cpustate->a); } /*************************************************** @@ -766,8 +766,8 @@ static void f8_lnk(f8_Regs *cpustate) ***************************************************/ static void f8_di(f8_Regs *cpustate) { - ROMC_1C(cpustate, cS); - cpustate->w &= ~I; + ROMC_1C(cpustate, cS); + cpustate->w &= ~I; } /*************************************************** @@ -776,8 +776,8 @@ static void f8_di(f8_Regs *cpustate) ***************************************************/ static void f8_ei(f8_Regs *cpustate) { - ROMC_1C(cpustate, cS); - cpustate->w |= I; + ROMC_1C(cpustate, cS); + cpustate->w |= I; } /*************************************************** @@ -786,7 +786,7 @@ static void f8_ei(f8_Regs *cpustate) ***************************************************/ static void f8_pop(f8_Regs *cpustate) { - ROMC_04(cpustate); + ROMC_04(cpustate); } /*************************************************** @@ -795,8 +795,8 @@ static void f8_pop(f8_Regs *cpustate) ***************************************************/ static void f8_lr_w_j(f8_Regs *cpustate) { - ROMC_1C(cpustate, cS); - cpustate->w = cpustate->r[9]; + ROMC_1C(cpustate, cS); + cpustate->w = cpustate->r[9]; } /*************************************************** @@ -805,7 +805,7 @@ static void f8_lr_w_j(f8_Regs *cpustate) ***************************************************/ static void f8_lr_j_w(f8_Regs *cpustate) { - cpustate->r[9] = cpustate->w; + cpustate->r[9] = cpustate->w; } /*************************************************** @@ -814,10 +814,10 @@ static void f8_lr_j_w(f8_Regs *cpustate) ***************************************************/ static void f8_inc(f8_Regs *cpustate) { - CLR_OZCS; - SET_OC(cpustate->a,1); - cpustate->a += 1; - SET_SZ(cpustate->a); + CLR_OZCS; + SET_OC(cpustate->a,1); + cpustate->a += 1; + SET_SZ(cpustate->a); } /*************************************************** @@ -826,8 +826,8 @@ static void f8_inc(f8_Regs *cpustate) ***************************************************/ static void f8_li(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - cpustate->a = cpustate->dbus; + ROMC_03(cpustate, cL); + cpustate->a = cpustate->dbus; } /*************************************************** @@ -836,10 +836,10 @@ static void f8_li(f8_Regs *cpustate) ***************************************************/ static void f8_ni(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - CLR_OZCS; - cpustate->a &= cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_03(cpustate, cL); + CLR_OZCS; + cpustate->a &= cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -848,10 +848,10 @@ static void f8_ni(f8_Regs *cpustate) ***************************************************/ static void f8_oi(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - CLR_OZCS; - cpustate->a |= cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_03(cpustate, cL); + CLR_OZCS; + cpustate->a |= cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -860,10 +860,10 @@ static void f8_oi(f8_Regs *cpustate) ***************************************************/ static void f8_xi(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - CLR_OZCS; - cpustate->a ^= cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_03(cpustate, cL); + CLR_OZCS; + cpustate->a ^= cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -872,11 +872,11 @@ static void f8_xi(f8_Regs *cpustate) ***************************************************/ static void f8_ai(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - CLR_OZCS; - SET_OC(cpustate->a,cpustate->dbus); - cpustate->a += cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_03(cpustate, cL); + CLR_OZCS; + SET_OC(cpustate->a,cpustate->dbus); + cpustate->a += cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -885,12 +885,12 @@ static void f8_ai(f8_Regs *cpustate) ***************************************************/ static void f8_ci(f8_Regs *cpustate) { - UINT16 tmp = ((UINT8)~cpustate->a) + 1; - ROMC_03(cpustate, cL); - CLR_OZCS; - SET_OC(tmp,cpustate->dbus); - tmp += cpustate->dbus; - SET_SZ((UINT8)tmp); + UINT16 tmp = ((UINT8)~cpustate->a) + 1; + ROMC_03(cpustate, cL); + CLR_OZCS; + SET_OC(tmp,cpustate->dbus); + tmp += cpustate->dbus; + SET_SZ((UINT8)tmp); } /*************************************************** @@ -899,11 +899,11 @@ static void f8_ci(f8_Regs *cpustate) ***************************************************/ static void f8_in(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - CLR_OZCS; - ROMC_1B(cpustate); - cpustate->a = cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_03(cpustate, cL); + CLR_OZCS; + ROMC_1B(cpustate); + cpustate->a = cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -912,9 +912,9 @@ static void f8_in(f8_Regs *cpustate) ***************************************************/ static void f8_out(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - cpustate->dbus = cpustate->a; - ROMC_1A(cpustate); + ROMC_03(cpustate, cL); + cpustate->dbus = cpustate->a; + ROMC_1A(cpustate); } /*************************************************** @@ -923,12 +923,12 @@ static void f8_out(f8_Regs *cpustate) ***************************************************/ static void f8_pi(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - cpustate->a = cpustate->dbus; - ROMC_0D(cpustate); - ROMC_0C(cpustate); - cpustate->dbus = cpustate->a; - ROMC_14(cpustate); + ROMC_03(cpustate, cL); + cpustate->a = cpustate->dbus; + ROMC_0D(cpustate); + ROMC_0C(cpustate); + cpustate->dbus = cpustate->a; + ROMC_14(cpustate); } /*************************************************** @@ -937,11 +937,11 @@ static void f8_pi(f8_Regs *cpustate) ***************************************************/ static void f8_jmp(f8_Regs *cpustate) { - ROMC_03(cpustate, cL); - cpustate->a = cpustate->dbus; - ROMC_0C(cpustate); - cpustate->dbus = cpustate->a; - ROMC_14(cpustate); + ROMC_03(cpustate, cL); + cpustate->a = cpustate->dbus; + ROMC_0C(cpustate); + cpustate->dbus = cpustate->a; + ROMC_14(cpustate); } /*************************************************** @@ -950,10 +950,10 @@ static void f8_jmp(f8_Regs *cpustate) ***************************************************/ static void f8_dci(f8_Regs *cpustate) { - ROMC_11(cpustate); - ROMC_03(cpustate, cS); - ROMC_0E(cpustate); - ROMC_03(cpustate, cS); + ROMC_11(cpustate); + ROMC_03(cpustate, cS); + ROMC_0E(cpustate); + ROMC_03(cpustate, cS); } /*************************************************** @@ -970,7 +970,7 @@ static void f8_nop(f8_Regs *cpustate) ***************************************************/ static void f8_xdc(f8_Regs *cpustate) { - ROMC_1D(cpustate); + ROMC_1D(cpustate); } /*************************************************** @@ -979,10 +979,10 @@ static void f8_xdc(f8_Regs *cpustate) ***************************************************/ static void f8_ds_r(f8_Regs *cpustate, int r) { - CLR_OZCS; - SET_OC(cpustate->r[r], 0xff); - cpustate->r[r] = cpustate->r[r] + 0xff; - SET_SZ(cpustate->r[r]); + CLR_OZCS; + SET_OC(cpustate->r[r], 0xff); + cpustate->r[r] = cpustate->r[r] + 0xff; + SET_SZ(cpustate->r[r]); } /*************************************************** @@ -991,10 +991,10 @@ static void f8_ds_r(f8_Regs *cpustate, int r) ***************************************************/ static void f8_ds_isar(f8_Regs *cpustate) { - CLR_OZCS; - SET_OC(cpustate->r[cpustate->is], 0xff); - cpustate->r[cpustate->is] = cpustate->r[cpustate->is] + 0xff; - SET_SZ(cpustate->r[cpustate->is]); + CLR_OZCS; + SET_OC(cpustate->r[cpustate->is], 0xff); + cpustate->r[cpustate->is] = cpustate->r[cpustate->is] + 0xff; + SET_SZ(cpustate->r[cpustate->is]); } /*************************************************** @@ -1003,11 +1003,11 @@ static void f8_ds_isar(f8_Regs *cpustate) ***************************************************/ static void f8_ds_isar_i(f8_Regs *cpustate) { - CLR_OZCS; - SET_OC(cpustate->r[cpustate->is], 0xff); - cpustate->r[cpustate->is] = cpustate->r[cpustate->is] + 0xff; - SET_SZ(cpustate->r[cpustate->is]); - cpustate->is = (cpustate->is & 0x38) | ((cpustate->is + 1) & 0x07); + CLR_OZCS; + SET_OC(cpustate->r[cpustate->is], 0xff); + cpustate->r[cpustate->is] = cpustate->r[cpustate->is] + 0xff; + SET_SZ(cpustate->r[cpustate->is]); + cpustate->is = (cpustate->is & 0x38) | ((cpustate->is + 1) & 0x07); } /*************************************************** @@ -1016,11 +1016,11 @@ static void f8_ds_isar_i(f8_Regs *cpustate) ***************************************************/ static void f8_ds_isar_d(f8_Regs *cpustate) { - CLR_OZCS; - SET_OC(cpustate->r[cpustate->is], 0xff); - cpustate->r[cpustate->is] = cpustate->r[cpustate->is] + 0xff; - SET_SZ(cpustate->r[cpustate->is]); - cpustate->is = (cpustate->is & 0x38) | ((cpustate->is - 1) & 0x07); + CLR_OZCS; + SET_OC(cpustate->r[cpustate->is], 0xff); + cpustate->r[cpustate->is] = cpustate->r[cpustate->is] + 0xff; + SET_SZ(cpustate->r[cpustate->is]); + cpustate->is = (cpustate->is & 0x38) | ((cpustate->is - 1) & 0x07); } /*************************************************** @@ -1029,7 +1029,7 @@ static void f8_ds_isar_d(f8_Regs *cpustate) ***************************************************/ static void f8_lr_a_r(f8_Regs *cpustate, int r) { - cpustate->a = cpustate->r[r]; + cpustate->a = cpustate->r[r]; } /*************************************************** @@ -1038,7 +1038,7 @@ static void f8_lr_a_r(f8_Regs *cpustate, int r) ***************************************************/ static void f8_lr_a_isar(f8_Regs *cpustate) { - cpustate->a = cpustate->r[cpustate->is]; + cpustate->a = cpustate->r[cpustate->is]; } /*************************************************** @@ -1047,8 +1047,8 @@ static void f8_lr_a_isar(f8_Regs *cpustate) ***************************************************/ static void f8_lr_a_isar_i(f8_Regs *cpustate) { - cpustate->a = cpustate->r[cpustate->is]; - cpustate->is = (cpustate->is & 0x38) | ((cpustate->is + 1) & 0x07); + cpustate->a = cpustate->r[cpustate->is]; + cpustate->is = (cpustate->is & 0x38) | ((cpustate->is + 1) & 0x07); } /*************************************************** @@ -1057,8 +1057,8 @@ static void f8_lr_a_isar_i(f8_Regs *cpustate) ***************************************************/ static void f8_lr_a_isar_d(f8_Regs *cpustate) { - cpustate->a = cpustate->r[cpustate->is]; - cpustate->is = (cpustate->is & 0x38) | ((cpustate->is - 1) & 0x07); + cpustate->a = cpustate->r[cpustate->is]; + cpustate->is = (cpustate->is & 0x38) | ((cpustate->is - 1) & 0x07); } /*************************************************** @@ -1067,7 +1067,7 @@ static void f8_lr_a_isar_d(f8_Regs *cpustate) ***************************************************/ static void f8_lr_r_a(f8_Regs *cpustate, int r) { - cpustate->r[r] = cpustate->a; + cpustate->r[r] = cpustate->a; } /*************************************************** @@ -1076,7 +1076,7 @@ static void f8_lr_r_a(f8_Regs *cpustate, int r) ***************************************************/ static void f8_lr_isar_a(f8_Regs *cpustate) { - cpustate->r[cpustate->is] = cpustate->a; + cpustate->r[cpustate->is] = cpustate->a; } /*************************************************** @@ -1085,8 +1085,8 @@ static void f8_lr_isar_a(f8_Regs *cpustate) ***************************************************/ static void f8_lr_isar_i_a(f8_Regs *cpustate) { - cpustate->r[cpustate->is] = cpustate->a; - cpustate->is = (cpustate->is & 0x38) | ((cpustate->is + 1) & 0x07); + cpustate->r[cpustate->is] = cpustate->a; + cpustate->is = (cpustate->is & 0x38) | ((cpustate->is + 1) & 0x07); } /*************************************************** @@ -1095,8 +1095,8 @@ static void f8_lr_isar_i_a(f8_Regs *cpustate) ***************************************************/ static void f8_lr_isar_d_a(f8_Regs *cpustate) { - cpustate->r[cpustate->is] = cpustate->a; - cpustate->is = (cpustate->is & 0x38) | ((cpustate->is - 1) & 0x07); + cpustate->r[cpustate->is] = cpustate->a; + cpustate->is = (cpustate->is & 0x38) | ((cpustate->is - 1) & 0x07); } /*************************************************** @@ -1105,7 +1105,7 @@ static void f8_lr_isar_d_a(f8_Regs *cpustate) ***************************************************/ static void f8_lisu(f8_Regs *cpustate, int e) { - cpustate->is = (cpustate->is & 0x07) | e; + cpustate->is = (cpustate->is & 0x07) | e; } /*************************************************** @@ -1114,7 +1114,7 @@ static void f8_lisu(f8_Regs *cpustate, int e) ***************************************************/ static void f8_lisl(f8_Regs *cpustate, int e) { - cpustate->is = (cpustate->is & 0x38) | e; + cpustate->is = (cpustate->is & 0x38) | e; } /*************************************************** @@ -1123,7 +1123,7 @@ static void f8_lisl(f8_Regs *cpustate, int e) ***************************************************/ static void f8_lis(f8_Regs *cpustate, int i) { - cpustate->a = i; + cpustate->a = i; } /*************************************************** @@ -1132,11 +1132,11 @@ static void f8_lis(f8_Regs *cpustate, int i) ***************************************************/ static void f8_bt(f8_Regs *cpustate, int e) { - ROMC_1C(cpustate, cS); - if (cpustate->w & e) - ROMC_01(cpustate); /* take the relative branch */ - else - ROMC_03(cpustate, cS); /* just read the argument on the data bus */ + ROMC_1C(cpustate, cS); + if (cpustate->w & e) + ROMC_01(cpustate); /* take the relative branch */ + else + ROMC_03(cpustate, cS); /* just read the argument on the data bus */ } /*************************************************** @@ -1145,11 +1145,11 @@ static void f8_bt(f8_Regs *cpustate, int e) ***************************************************/ static void f8_am(f8_Regs *cpustate) { - ROMC_02(cpustate); - CLR_OZCS; - SET_OC(cpustate->a, cpustate->dbus); - cpustate->a += cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_02(cpustate); + CLR_OZCS; + SET_OC(cpustate->a, cpustate->dbus); + cpustate->a += cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -1173,30 +1173,30 @@ static void f8_amd(f8_Regs *cpustate) *NOTE* status flags are updated prior to the factor being added */ - UINT8 augend=cpustate->a; - ROMC_02(cpustate); - UINT8 addend=cpustate->dbus; - UINT8 tmp=addend+augend; + UINT8 augend=cpustate->a; + ROMC_02(cpustate); + UINT8 addend=cpustate->dbus; + UINT8 tmp=addend+augend; - UINT8 c=0; /* high order carry */ - UINT8 ic=0; /* low order carry */ - if(((augend+addend)&0xff0)>0xf0) - c=1; - if((augend&0x0f)+(addend&0x0f)>0x0F) - ic=1; + UINT8 c=0; /* high order carry */ + UINT8 ic=0; /* low order carry */ + if(((augend+addend)&0xff0)>0xf0) + c=1; + if((augend&0x0f)+(addend&0x0f)>0x0F) + ic=1; - CLR_OZCS; - SET_OC(augend,addend); - SET_SZ(tmp); + CLR_OZCS; + SET_OC(augend,addend); + SET_SZ(tmp); - if(c==0&&ic==0) - tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); - if(c==0&&ic==1) - tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); - if(c==1&&ic==0) - tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==0) + tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==1) + tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); + if(c==1&&ic==0) + tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); - cpustate->a = tmp; + cpustate->a = tmp; } /*************************************************** @@ -1205,10 +1205,10 @@ static void f8_amd(f8_Regs *cpustate) ***************************************************/ static void f8_nm(f8_Regs *cpustate) { - ROMC_02(cpustate); - CLR_OZCS; - cpustate->a &= cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_02(cpustate); + CLR_OZCS; + cpustate->a &= cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -1217,10 +1217,10 @@ static void f8_nm(f8_Regs *cpustate) ***************************************************/ static void f8_om(f8_Regs *cpustate) { - ROMC_02(cpustate); - CLR_OZCS; - cpustate->a |= cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_02(cpustate); + CLR_OZCS; + cpustate->a |= cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -1229,19 +1229,19 @@ static void f8_om(f8_Regs *cpustate) ***************************************************/ static void f8_xm(f8_Regs *cpustate) { - ROMC_02(cpustate); - CLR_OZCS; - cpustate->a ^= cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_02(cpustate); + CLR_OZCS; + cpustate->a ^= cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** * O Z C S 1000 1101 * x x x x CM ***************************************************/ -static void f8_cm(f8_Regs *cpustate) /* SKR changed to match f8_ci(cpustate) */ +static void f8_cm(f8_Regs *cpustate) /* SKR changed to match f8_ci(cpustate) */ { - UINT16 tmp = ((UINT8)~cpustate->a) + 1; + UINT16 tmp = ((UINT8)~cpustate->a) + 1; ROMC_02(cpustate); CLR_OZCS; SET_OC(tmp,cpustate->dbus); @@ -1255,8 +1255,8 @@ static void f8_cm(f8_Regs *cpustate) /* SKR changed to match f8_ci(cpustate) */ ***************************************************/ static void f8_adc(f8_Regs *cpustate) { - cpustate->dbus = cpustate->a; - ROMC_0A(cpustate); /* add data bus value to DC0 */ + cpustate->dbus = cpustate->a; + ROMC_0A(cpustate); /* add data bus value to DC0 */ } /*************************************************** @@ -1265,10 +1265,10 @@ static void f8_adc(f8_Regs *cpustate) ***************************************************/ static void f8_br7(f8_Regs *cpustate) { - if ((cpustate->is & 7) == 7) - ROMC_03(cpustate, cS); /* just read the argument on the data bus */ - else - ROMC_01(cpustate); /* take the relative branch */ + if ((cpustate->is & 7) == 7) + ROMC_03(cpustate, cS); /* just read the argument on the data bus */ + else + ROMC_01(cpustate); /* take the relative branch */ } /*************************************************** @@ -1277,11 +1277,11 @@ static void f8_br7(f8_Regs *cpustate) ***************************************************/ static void f8_bf(f8_Regs *cpustate, int t) { - ROMC_1C(cpustate, cS); - if (cpustate->w & t) - ROMC_03(cpustate, cS); /* just read the argument on the data bus */ - else - ROMC_01(cpustate); /* take the relative branch */ + ROMC_1C(cpustate, cS); + if (cpustate->w & t) + ROMC_03(cpustate, cS); /* just read the argument on the data bus */ + else + ROMC_01(cpustate); /* take the relative branch */ } /*************************************************** @@ -1290,10 +1290,10 @@ static void f8_bf(f8_Regs *cpustate, int t) ***************************************************/ static void f8_ins_0(f8_Regs *cpustate, int n) { - ROMC_1C(cpustate, cS); - CLR_OZCS; - cpustate->a = cpustate->iospace->read_byte(n); - SET_SZ(cpustate->a); + ROMC_1C(cpustate, cS); + CLR_OZCS; + cpustate->a = cpustate->iospace->read_byte(n); + SET_SZ(cpustate->a); } /*************************************************** @@ -1302,12 +1302,12 @@ static void f8_ins_0(f8_Regs *cpustate, int n) ***************************************************/ static void f8_ins_1(f8_Regs *cpustate, int n) { - ROMC_1C(cpustate, cL); - cpustate->io = n; - ROMC_1B(cpustate); - CLR_OZCS; - cpustate->a = cpustate->dbus; - SET_SZ(cpustate->a); + ROMC_1C(cpustate, cL); + cpustate->io = n; + ROMC_1B(cpustate); + CLR_OZCS; + cpustate->a = cpustate->dbus; + SET_SZ(cpustate->a); } /*************************************************** @@ -1316,8 +1316,8 @@ static void f8_ins_1(f8_Regs *cpustate, int n) ***************************************************/ static void f8_outs_0(f8_Regs *cpustate, int n) { - ROMC_1C(cpustate, cS); - cpustate->iospace->write_byte(n, cpustate->a); + ROMC_1C(cpustate, cS); + cpustate->iospace->write_byte(n, cpustate->a); } /*************************************************** @@ -1326,10 +1326,10 @@ static void f8_outs_0(f8_Regs *cpustate, int n) ***************************************************/ static void f8_outs_1(f8_Regs *cpustate, int n) { - ROMC_1C(cpustate, cL); - cpustate->io = n; - cpustate->dbus = cpustate->a; - ROMC_1A(cpustate); + ROMC_1C(cpustate, cL); + cpustate->io = n; + cpustate->dbus = cpustate->a; + ROMC_1A(cpustate); } /*************************************************** @@ -1389,30 +1389,30 @@ static void f8_as_isar_d(f8_Regs *cpustate) static void f8_asd(f8_Regs *cpustate, int r) { /*SKR from F8 Guide To programming description of AMD */ - UINT8 augend=cpustate->a; - ROMC_1C(cpustate, cS); - UINT8 addend=cpustate->r[r]; - UINT8 tmp=augend+addend; + UINT8 augend=cpustate->a; + ROMC_1C(cpustate, cS); + UINT8 addend=cpustate->r[r]; + UINT8 tmp=augend+addend; + + UINT8 c=0; + UINT8 ic=0; + if(((augend+addend)&0xff0)>0xf0) + c=1; + if((augend&0x0f)+(addend&0x0f)>0x0F) + ic=1; - UINT8 c=0; - UINT8 ic=0; - if(((augend+addend)&0xff0)>0xf0) - c=1; - if((augend&0x0f)+(addend&0x0f)>0x0F) - ic=1; - - CLR_OZCS; - SET_OC(augend,addend); - SET_SZ(tmp); + CLR_OZCS; + SET_OC(augend,addend); + SET_SZ(tmp); - if(c==0&&ic==0) - tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); - if(c==0&&ic==1) - tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); - if(c==1&&ic==0) - tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==0) + tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==1) + tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); + if(c==1&&ic==0) + tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); - cpustate->a = tmp; + cpustate->a = tmp; } /*************************************************** @@ -1422,30 +1422,30 @@ static void f8_asd(f8_Regs *cpustate, int r) static void f8_asd_isar(f8_Regs *cpustate) { /*SKR from F8 Guide To programming description of AMD */ - UINT8 augend=cpustate->a; - ROMC_1C(cpustate, cS); - UINT8 addend=cpustate->r[cpustate->is]; - UINT8 tmp=augend+addend; + UINT8 augend=cpustate->a; + ROMC_1C(cpustate, cS); + UINT8 addend=cpustate->r[cpustate->is]; + UINT8 tmp=augend+addend; + + UINT8 c=0; + UINT8 ic=0; + if(((augend+addend)&0xff0)>0xf0) + c=1; + if((augend&0x0f)+(addend&0x0f)>0x0F) + ic=1; - UINT8 c=0; - UINT8 ic=0; - if(((augend+addend)&0xff0)>0xf0) - c=1; - if((augend&0x0f)+(addend&0x0f)>0x0F) - ic=1; - - CLR_OZCS; - SET_OC(augend,addend); - SET_SZ(tmp); + CLR_OZCS; + SET_OC(augend,addend); + SET_SZ(tmp); - if(c==0&&ic==0) - tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); - if(c==0&&ic==1) - tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); - if(c==1&&ic==0) - tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==0) + tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==1) + tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); + if(c==1&&ic==0) + tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); - cpustate->a = tmp; + cpustate->a = tmp; } /*************************************************** @@ -1455,31 +1455,31 @@ static void f8_asd_isar(f8_Regs *cpustate) static void f8_asd_isar_i(f8_Regs *cpustate) { /*SKR from F8 Guide To programming description of AMD */ - UINT8 augend=cpustate->a; - ROMC_1C(cpustate, cS); - UINT8 addend=cpustate->r[cpustate->is]; - UINT8 tmp=augend+addend; + UINT8 augend=cpustate->a; + ROMC_1C(cpustate, cS); + UINT8 addend=cpustate->r[cpustate->is]; + UINT8 tmp=augend+addend; + + UINT8 c=0; + UINT8 ic=0; + if(((augend+addend)&0xff0)>0xf0) + c=1; + if((augend&0x0f)+(addend&0x0f)>0x0F) + ic=1; - UINT8 c=0; - UINT8 ic=0; - if(((augend+addend)&0xff0)>0xf0) - c=1; - if((augend&0x0f)+(addend&0x0f)>0x0F) - ic=1; - - CLR_OZCS; - SET_OC(augend,addend); - SET_SZ(tmp); + CLR_OZCS; + SET_OC(augend,addend); + SET_SZ(tmp); - if(c==0&&ic==0) - tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); - if(c==0&&ic==1) - tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); - if(c==1&&ic==0) - tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==0) + tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==1) + tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); + if(c==1&&ic==0) + tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); - cpustate->a = tmp; - cpustate->is = (cpustate->is & 0x38) | ((cpustate->is + 1) & 0x07); + cpustate->a = tmp; + cpustate->is = (cpustate->is & 0x38) | ((cpustate->is + 1) & 0x07); } /*************************************************** @@ -1489,31 +1489,31 @@ static void f8_asd_isar_i(f8_Regs *cpustate) static void f8_asd_isar_d(f8_Regs *cpustate) { /*SKR from F8 Guide To programming description of AMD */ - UINT8 augend=cpustate->a; - ROMC_1C(cpustate, cS); - UINT8 addend=cpustate->r[cpustate->is]; - UINT8 tmp=augend+addend; + UINT8 augend=cpustate->a; + ROMC_1C(cpustate, cS); + UINT8 addend=cpustate->r[cpustate->is]; + UINT8 tmp=augend+addend; + + UINT8 c=0; + UINT8 ic=0; + if(((augend+addend)&0xff0)>0xf0) + c=1; + if((augend&0x0f)+(addend&0x0f)>0x0F) + ic=1; - UINT8 c=0; - UINT8 ic=0; - if(((augend+addend)&0xff0)>0xf0) - c=1; - if((augend&0x0f)+(addend&0x0f)>0x0F) - ic=1; - - CLR_OZCS; - SET_OC(augend,addend); - SET_SZ(tmp); + CLR_OZCS; + SET_OC(augend,addend); + SET_SZ(tmp); - if(c==0&&ic==0) - tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); - if(c==0&&ic==1) - tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); - if(c==1&&ic==0) - tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==0) + tmp=((tmp+0xa0)&0xf0)+((tmp+0x0a)&0x0f); + if(c==0&&ic==1) + tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f); + if(c==1&&ic==0) + tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f); - cpustate->a = tmp; - cpustate->is = (cpustate->is & 0x38) | ((cpustate->is - 1) & 0x07); + cpustate->a = tmp; + cpustate->is = (cpustate->is & 0x38) | ((cpustate->is - 1) & 0x07); } /*************************************************** @@ -1630,21 +1630,21 @@ static CPU_RESET( f8 ) ROMC_00(cpustate, cS); /* initialize the timer shift register - * this is an 8 bit polynome counter which can be loaded parallel - * with 0xff the outputs never change and thus the timer is disabled. - * with 0xfe the shifter starts cycling through 255 states until it - * reaches 0xfe again (and then issues an interrupt). - * the counter output values are not sequential, but go like this: - * 0xfe, 0xfd, 0xfb, 0xf7, 0xee, 0xdc ... etc. :-) - * We have to build a lookup table to tell how many cycles a write - - */ - data = 0xfe; /* initial value */ + * this is an 8 bit polynome counter which can be loaded parallel + * with 0xff the outputs never change and thus the timer is disabled. + * with 0xfe the shifter starts cycling through 255 states until it + * reaches 0xfe again (and then issues an interrupt). + * the counter output values are not sequential, but go like this: + * 0xfe, 0xfd, 0xfb, 0xf7, 0xee, 0xdc ... etc. :-) + * We have to build a lookup table to tell how many cycles a write + + */ + data = 0xfe; /* initial value */ for (i = 0; i < 256; i++) { timer_shifter[i] = data; if ( (((data >> 3) ^ (data >> 4)) ^ - ((data >> 5) ^ (data >> 7))) & 1 ) + ((data >> 5) ^ (data >> 7))) & 1 ) data <<= 1; else data = (data << 1) | 1; @@ -1654,310 +1654,310 @@ static CPU_RESET( f8 ) /* Execute cycles - returns number of cycles actually run */ static CPU_EXECUTE( f8 ) { - f8_Regs *cpustate = get_safe_token(device); + f8_Regs *cpustate = get_safe_token(device); - do - { + do + { UINT8 op=cpustate->dbus; - debugger_instruction_hook(device, (cpustate->pc0 - 1) & 0xffff); + debugger_instruction_hook(device, (cpustate->pc0 - 1) & 0xffff); switch( op ) - { + { /* opcode bitmask */ - case 0x00: /* 0000 0000 */ f8_lr_a_ku(cpustate); break; - case 0x01: /* 0000 0001 */ f8_lr_a_kl(cpustate); break; - case 0x02: /* 0000 0010 */ f8_lr_a_qu(cpustate); break; - case 0x03: /* 0000 0011 */ f8_lr_a_ql(cpustate); break; - case 0x04: /* 0000 0100 */ f8_lr_ku_a(cpustate); break; - case 0x05: /* 0000 0101 */ f8_lr_kl_a(cpustate); break; - case 0x06: /* 0000 0110 */ f8_lr_qu_a(cpustate); break; - case 0x07: /* 0000 0111 */ f8_lr_ql_a(cpustate); break; - case 0x08: /* 0000 1000 */ f8_lr_k_p(cpustate); break; - case 0x09: /* 0000 1001 */ f8_lr_p_k(cpustate); break; - case 0x0a: /* 0000 1010 */ f8_lr_a_is(cpustate); break; - case 0x0b: /* 0000 1011 */ f8_lr_is_a(cpustate); break; - case 0x0c: /* 0000 1100 */ f8_pk(cpustate); break; - case 0x0d: /* 0000 1101 */ f8_lr_p0_q(cpustate); break; - case 0x0e: /* 0000 1110 */ f8_lr_q_dc(cpustate); break; - case 0x0f: /* 0000 1111 */ f8_lr_dc_q(cpustate); break; - - case 0x10: /* 0001 0000 */ f8_lr_dc_h(cpustate); break; - case 0x11: /* 0001 0001 */ f8_lr_h_dc(cpustate); break; - case 0x12: /* 0001 0010 */ f8_sr_1(cpustate); break; - case 0x13: /* 0001 0011 */ f8_sl_1(cpustate); break; - case 0x14: /* 0001 0100 */ f8_sr_4(cpustate); break; - case 0x15: /* 0001 0101 */ f8_sl_4(cpustate); break; - case 0x16: /* 0001 0110 */ f8_lm(cpustate); break; - case 0x17: /* 0001 0111 */ f8_st(cpustate); break; - case 0x18: /* 0001 1000 */ f8_com(cpustate); break; - case 0x19: /* 0001 1001 */ f8_lnk(cpustate); break; - case 0x1a: /* 0001 1010 */ f8_di(cpustate); break; - case 0x1b: /* 0001 1011 */ f8_ei(cpustate); break; - case 0x1c: /* 0001 1100 */ f8_pop(cpustate); break; - case 0x1d: /* 0001 1101 */ f8_lr_w_j(cpustate); break; - case 0x1e: /* 0001 1110 */ f8_lr_j_w(cpustate); break; - case 0x1f: /* 0001 1111 */ f8_inc(cpustate); break; - - case 0x20: /* 0010 0000 */ f8_li(cpustate); break; - case 0x21: /* 0010 0001 */ f8_ni(cpustate); break; - case 0x22: /* 0010 0010 */ f8_oi(cpustate); break; - case 0x23: /* 0010 0011 */ f8_xi(cpustate); break; - case 0x24: /* 0010 0100 */ f8_ai(cpustate); break; - case 0x25: /* 0010 0101 */ f8_ci(cpustate); break; - case 0x26: /* 0010 0110 */ f8_in(cpustate); break; - case 0x27: /* 0010 0111 */ f8_out(cpustate); break; - case 0x28: /* 0010 1000 */ f8_pi(cpustate); break; - case 0x29: /* 0010 1001 */ f8_jmp(cpustate); break; - case 0x2a: /* 0010 1010 */ f8_dci(cpustate); break; - case 0x2b: /* 0010 1011 */ f8_nop(cpustate); break; - case 0x2c: /* 0010 1100 */ f8_xdc(cpustate); break; - case 0x2d: /* 0010 1101 */ illegal(cpustate); break; - case 0x2e: /* 0010 1110 */ illegal(cpustate); break; - case 0x2f: /* 0010 1111 */ illegal(cpustate); break; - - case 0x30: /* 0011 0000 */ f8_ds_r(cpustate, 0); break; - case 0x31: /* 0011 0001 */ f8_ds_r(cpustate, 1); break; - case 0x32: /* 0011 0010 */ f8_ds_r(cpustate, 2); break; - case 0x33: /* 0011 0011 */ f8_ds_r(cpustate, 3); break; - case 0x34: /* 0011 0100 */ f8_ds_r(cpustate, 4); break; - case 0x35: /* 0011 0101 */ f8_ds_r(cpustate, 5); break; - case 0x36: /* 0011 0110 */ f8_ds_r(cpustate, 6); break; - case 0x37: /* 0011 0111 */ f8_ds_r(cpustate, 7); break; - case 0x38: /* 0011 1000 */ f8_ds_r(cpustate, 8); break; - case 0x39: /* 0011 1001 */ f8_ds_r(cpustate, 9); break; - case 0x3a: /* 0011 1010 */ f8_ds_r(cpustate, 10); break; - case 0x3b: /* 0011 1011 */ f8_ds_r(cpustate, 11); break; - case 0x3c: /* 0011 1100 */ f8_ds_isar(cpustate); break; - case 0x3d: /* 0011 1101 */ f8_ds_isar_i(cpustate); break; - case 0x3e: /* 0011 1110 */ f8_ds_isar_d(cpustate); break; - case 0x3f: /* 0011 1111 */ illegal(cpustate); break; - - case 0x40: /* 0100 0000 */ f8_lr_a_r(cpustate, 0); break; - case 0x41: /* 0100 0001 */ f8_lr_a_r(cpustate, 1); break; - case 0x42: /* 0100 0010 */ f8_lr_a_r(cpustate, 2); break; - case 0x43: /* 0100 0011 */ f8_lr_a_r(cpustate, 3); break; - case 0x44: /* 0100 0100 */ f8_lr_a_r(cpustate, 4); break; - case 0x45: /* 0100 0101 */ f8_lr_a_r(cpustate, 5); break; - case 0x46: /* 0100 0110 */ f8_lr_a_r(cpustate, 6); break; - case 0x47: /* 0100 0111 */ f8_lr_a_r(cpustate, 7); break; - case 0x48: /* 0100 1000 */ f8_lr_a_r(cpustate, 8); break; - case 0x49: /* 0100 1001 */ f8_lr_a_r(cpustate, 9); break; - case 0x4a: /* 0100 1010 */ f8_lr_a_r(cpustate, 10); break; - case 0x4b: /* 0100 1011 */ f8_lr_a_r(cpustate, 11); break; - case 0x4c: /* 0100 1100 */ f8_lr_a_isar(cpustate); break; - case 0x4d: /* 0100 1101 */ f8_lr_a_isar_i(cpustate); break; - case 0x4e: /* 0100 1110 */ f8_lr_a_isar_d(cpustate); break; - case 0x4f: /* 0100 1111 */ illegal(cpustate); break; - - case 0x50: /* 0101 0000 */ f8_lr_r_a(cpustate, 0); break; - case 0x51: /* 0101 0001 */ f8_lr_r_a(cpustate, 1); break; - case 0x52: /* 0101 0010 */ f8_lr_r_a(cpustate, 2); break; - case 0x53: /* 0101 0011 */ f8_lr_r_a(cpustate, 3); break; - case 0x54: /* 0101 0100 */ f8_lr_r_a(cpustate, 4); break; - case 0x55: /* 0101 0101 */ f8_lr_r_a(cpustate, 5); break; - case 0x56: /* 0101 0110 */ f8_lr_r_a(cpustate, 6); break; - case 0x57: /* 0101 0111 */ f8_lr_r_a(cpustate, 7); break; - case 0x58: /* 0101 1000 */ f8_lr_r_a(cpustate, 8); break; - case 0x59: /* 0101 1001 */ f8_lr_r_a(cpustate, 9); break; - case 0x5a: /* 0101 1010 */ f8_lr_r_a(cpustate, 10); break; - case 0x5b: /* 0101 1011 */ f8_lr_r_a(cpustate, 11); break; - case 0x5c: /* 0101 1100 */ f8_lr_isar_a(cpustate); break; - case 0x5d: /* 0101 1101 */ f8_lr_isar_i_a(cpustate); break; - case 0x5e: /* 0101 1110 */ f8_lr_isar_d_a(cpustate); break; - case 0x5f: /* 0101 1111 */ illegal(cpustate); break; - - case 0x60: /* 0110 0000 */ f8_lisu(cpustate, 0x00); break; - case 0x61: /* 0110 0001 */ f8_lisu(cpustate, 0x08); break; - case 0x62: /* 0110 0010 */ f8_lisu(cpustate, 0x10); break; - case 0x63: /* 0110 0011 */ f8_lisu(cpustate, 0x18); break; - case 0x64: /* 0110 0100 */ f8_lisu(cpustate, 0x20); break; - case 0x65: /* 0110 0101 */ f8_lisu(cpustate, 0x28); break; - case 0x66: /* 0110 0110 */ f8_lisu(cpustate, 0x30); break; - case 0x67: /* 0110 0111 */ f8_lisu(cpustate, 0x38); break; - case 0x68: /* 0110 1000 */ f8_lisl(cpustate, 0x00); break; - case 0x69: /* 0110 1001 */ f8_lisl(cpustate, 0x01); break; - case 0x6a: /* 0110 1010 */ f8_lisl(cpustate, 0x02); break; - case 0x6b: /* 0110 1011 */ f8_lisl(cpustate, 0x03); break; - case 0x6c: /* 0110 1100 */ f8_lisl(cpustate, 0x04); break; - case 0x6d: /* 0110 1101 */ f8_lisl(cpustate, 0x05); break; - case 0x6e: /* 0110 1110 */ f8_lisl(cpustate, 0x06); break; - case 0x6f: /* 0110 1111 */ f8_lisl(cpustate, 0x07); break; - - case 0x70: /* 0111 0000 */ f8_lis(cpustate, 0x0); break; - case 0x71: /* 0111 0001 */ f8_lis(cpustate, 0x1); break; - case 0x72: /* 0111 0010 */ f8_lis(cpustate, 0x2); break; - case 0x73: /* 0111 0011 */ f8_lis(cpustate, 0x3); break; - case 0x74: /* 0111 0100 */ f8_lis(cpustate, 0x4); break; - case 0x75: /* 0111 0101 */ f8_lis(cpustate, 0x5); break; - case 0x76: /* 0111 0110 */ f8_lis(cpustate, 0x6); break; - case 0x77: /* 0111 0111 */ f8_lis(cpustate, 0x7); break; - case 0x78: /* 0111 1000 */ f8_lis(cpustate, 0x8); break; - case 0x79: /* 0111 1001 */ f8_lis(cpustate, 0x9); break; - case 0x7a: /* 0111 1010 */ f8_lis(cpustate, 0xa); break; - case 0x7b: /* 0111 1011 */ f8_lis(cpustate, 0xb); break; - case 0x7c: /* 0111 1100 */ f8_lis(cpustate, 0xc); break; - case 0x7d: /* 0111 1101 */ f8_lis(cpustate, 0xd); break; - case 0x7e: /* 0111 1110 */ f8_lis(cpustate, 0xe); break; - case 0x7f: /* 0111 1111 */ f8_lis(cpustate, 0xf); break; - - case 0x80: /* 1000 0000 */ f8_bt(cpustate, 0); break; - case 0x81: /* 1000 0001 */ f8_bt(cpustate, 1); break; - case 0x82: /* 1000 0010 */ f8_bt(cpustate, 2); break; - case 0x83: /* 1000 0011 */ f8_bt(cpustate, 3); break; - case 0x84: /* 1000 0100 */ f8_bt(cpustate, 4); break; - case 0x85: /* 1000 0101 */ f8_bt(cpustate, 5); break; - case 0x86: /* 1000 0110 */ f8_bt(cpustate, 6); break; - case 0x87: /* 1000 0111 */ f8_bt(cpustate, 7); break; - case 0x88: /* 1000 1000 */ f8_am(cpustate); break; - case 0x89: /* 1000 1001 */ f8_amd(cpustate); break; - case 0x8a: /* 1000 1010 */ f8_nm(cpustate); break; - case 0x8b: /* 1000 1011 */ f8_om(cpustate); break; - case 0x8c: /* 1000 1100 */ f8_xm(cpustate); break; - case 0x8d: /* 1000 1101 */ f8_cm(cpustate); break; - case 0x8e: /* 1000 1110 */ f8_adc(cpustate); break; - case 0x8f: /* 1000 1111 */ f8_br7(cpustate); break; - - case 0x90: /* 1001 0000 */ f8_bf(cpustate, 0x0); break; - case 0x91: /* 1001 0001 */ f8_bf(cpustate, 0x1); break; - case 0x92: /* 1001 0010 */ f8_bf(cpustate, 0x2); break; - case 0x93: /* 1001 0011 */ f8_bf(cpustate, 0x3); break; - case 0x94: /* 1001 0100 */ f8_bf(cpustate, 0x4); break; - case 0x95: /* 1001 0101 */ f8_bf(cpustate, 0x5); break; - case 0x96: /* 1001 0110 */ f8_bf(cpustate, 0x6); break; - case 0x97: /* 1001 0111 */ f8_bf(cpustate, 0x7); break; - case 0x98: /* 1001 1000 */ f8_bf(cpustate, 0x8); break; - case 0x99: /* 1001 1001 */ f8_bf(cpustate, 0x9); break; - case 0x9a: /* 1001 1010 */ f8_bf(cpustate, 0xa); break; - case 0x9b: /* 1001 1011 */ f8_bf(cpustate, 0xb); break; - case 0x9c: /* 1001 1100 */ f8_bf(cpustate, 0xc); break; - case 0x9d: /* 1001 1101 */ f8_bf(cpustate, 0xd); break; - case 0x9e: /* 1001 1110 */ f8_bf(cpustate, 0xe); break; - case 0x9f: /* 1001 1111 */ f8_bf(cpustate, 0xf); break; - - case 0xa0: /* 1010 0000 */ f8_ins_0(cpustate, 0x0); break; - case 0xa1: /* 1010 0001 */ f8_ins_0(cpustate, 0x1); break; - case 0xa2: /* 1010 0010 */ illegal(cpustate); break; - case 0xa3: /* 1010 0011 */ illegal(cpustate); break; - case 0xa4: /* 1010 0100 */ f8_ins_1(cpustate, 0x4); break; - case 0xa5: /* 1010 0101 */ f8_ins_1(cpustate, 0x5); break; - case 0xa6: /* 1010 0110 */ f8_ins_1(cpustate, 0x6); break; - case 0xa7: /* 1010 0111 */ f8_ins_1(cpustate, 0x7); break; - case 0xa8: /* 1010 1000 */ f8_ins_1(cpustate, 0x8); break; - case 0xa9: /* 1010 1001 */ f8_ins_1(cpustate, 0x9); break; - case 0xaa: /* 1010 1010 */ f8_ins_1(cpustate, 0xa); break; - case 0xab: /* 1010 1011 */ f8_ins_1(cpustate, 0xb); break; - case 0xac: /* 1010 1100 */ f8_ins_1(cpustate, 0xc); break; - case 0xad: /* 1010 1101 */ f8_ins_1(cpustate, 0xd); break; - case 0xae: /* 1010 1110 */ f8_ins_1(cpustate, 0xe); break; - case 0xaf: /* 1010 1111 */ f8_ins_1(cpustate, 0xf); break; - - case 0xb0: /* 1011 0000 */ f8_outs_0(cpustate, 0x0); break; - case 0xb1: /* 1011 0001 */ f8_outs_0(cpustate, 0x1); break; - case 0xb2: /* 1011 0010 */ illegal(cpustate); break; - case 0xb3: /* 1011 0011 */ illegal(cpustate); break; - case 0xb4: /* 1011 0100 */ f8_outs_1(cpustate, 0x4); break; - case 0xb5: /* 1011 0101 */ f8_outs_1(cpustate, 0x5); break; - case 0xb6: /* 1011 0110 */ f8_outs_1(cpustate, 0x6); break; - case 0xb7: /* 1011 0111 */ f8_outs_1(cpustate, 0x7); break; - case 0xb8: /* 1011 1000 */ f8_outs_1(cpustate, 0x8); break; - case 0xb9: /* 1011 1001 */ f8_outs_1(cpustate, 0x9); break; - case 0xba: /* 1011 1010 */ f8_outs_1(cpustate, 0xa); break; - case 0xbb: /* 1011 1011 */ f8_outs_1(cpustate, 0xb); break; - case 0xbc: /* 1011 1100 */ f8_outs_1(cpustate, 0xc); break; - case 0xbd: /* 1011 1101 */ f8_outs_1(cpustate, 0xd); break; - case 0xbe: /* 1011 1110 */ f8_outs_1(cpustate, 0xe); break; - case 0xbf: /* 1011 1111 */ f8_outs_1(cpustate, 0xf); break; - - case 0xc0: /* 1100 0000 */ f8_as(cpustate, 0x0); break; - case 0xc1: /* 1100 0001 */ f8_as(cpustate, 0x1); break; - case 0xc2: /* 1100 0010 */ f8_as(cpustate, 0x2); break; - case 0xc3: /* 1100 0011 */ f8_as(cpustate, 0x3); break; - case 0xc4: /* 1100 0100 */ f8_as(cpustate, 0x4); break; - case 0xc5: /* 1100 0101 */ f8_as(cpustate, 0x5); break; - case 0xc6: /* 1100 0110 */ f8_as(cpustate, 0x6); break; - case 0xc7: /* 1100 0111 */ f8_as(cpustate, 0x7); break; - case 0xc8: /* 1100 1000 */ f8_as(cpustate, 0x8); break; - case 0xc9: /* 1100 1001 */ f8_as(cpustate, 0x9); break; - case 0xca: /* 1100 1010 */ f8_as(cpustate, 0xa); break; - case 0xcb: /* 1100 1011 */ f8_as(cpustate, 0xb); break; - case 0xcc: /* 1100 1100 */ f8_as_isar(cpustate); break; - case 0xcd: /* 1100 1101 */ f8_as_isar_i(cpustate); break; - case 0xce: /* 1100 1110 */ f8_as_isar_d(cpustate); break; - case 0xcf: /* 1100 1111 */ illegal(cpustate); break; - - case 0xd0: /* 1101 0000 */ f8_asd(cpustate, 0x0); break; - case 0xd1: /* 1101 0001 */ f8_asd(cpustate, 0x1); break; - case 0xd2: /* 1101 0010 */ f8_asd(cpustate, 0x2); break; - case 0xd3: /* 1101 0011 */ f8_asd(cpustate, 0x3); break; - case 0xd4: /* 1101 0100 */ f8_asd(cpustate, 0x4); break; - case 0xd5: /* 1101 0101 */ f8_asd(cpustate, 0x5); break; - case 0xd6: /* 1101 0110 */ f8_asd(cpustate, 0x6); break; - case 0xd7: /* 1101 0111 */ f8_asd(cpustate, 0x7); break; - case 0xd8: /* 1101 1000 */ f8_asd(cpustate, 0x8); break; - case 0xd9: /* 1101 1001 */ f8_asd(cpustate, 0x9); break; - case 0xda: /* 1101 1010 */ f8_asd(cpustate, 0xa); break; - case 0xdb: /* 1101 1011 */ f8_asd(cpustate, 0xb); break; - case 0xdc: /* 1101 1100 */ f8_asd_isar(cpustate); break; - case 0xdd: /* 1101 1101 */ f8_asd_isar_i(cpustate); break; - case 0xde: /* 1101 1110 */ f8_asd_isar_d(cpustate); break; - case 0xdf: /* 1101 1111 */ illegal(cpustate); break; - - case 0xe0: /* 1110 0000 */ f8_xs(cpustate, 0x0); break; - case 0xe1: /* 1110 0001 */ f8_xs(cpustate, 0x1); break; - case 0xe2: /* 1110 0010 */ f8_xs(cpustate, 0x2); break; - case 0xe3: /* 1110 0011 */ f8_xs(cpustate, 0x3); break; - case 0xe4: /* 1110 0100 */ f8_xs(cpustate, 0x4); break; - case 0xe5: /* 1110 0101 */ f8_xs(cpustate, 0x5); break; - case 0xe6: /* 1110 0110 */ f8_xs(cpustate, 0x6); break; - case 0xe7: /* 1110 0111 */ f8_xs(cpustate, 0x7); break; - case 0xe8: /* 1110 1000 */ f8_xs(cpustate, 0x8); break; - case 0xe9: /* 1110 1001 */ f8_xs(cpustate, 0x9); break; - case 0xea: /* 1110 1010 */ f8_xs(cpustate, 0xa); break; - case 0xeb: /* 1110 1011 */ f8_xs(cpustate, 0xb); break; - case 0xec: /* 1110 1100 */ f8_xs_isar(cpustate); break; - case 0xed: /* 1110 1101 */ f8_xs_isar_i(cpustate); break; - case 0xee: /* 1110 1110 */ f8_xs_isar_d(cpustate); break; - case 0xef: /* 1110 1111 */ illegal(cpustate); break; - - case 0xf0: /* 1111 0000 */ f8_ns(cpustate, 0x0); break; - case 0xf1: /* 1111 0001 */ f8_ns(cpustate, 0x1); break; - case 0xf2: /* 1111 0010 */ f8_ns(cpustate, 0x2); break; - case 0xf3: /* 1111 0011 */ f8_ns(cpustate, 0x3); break; - case 0xf4: /* 1111 0100 */ f8_ns(cpustate, 0x4); break; - case 0xf5: /* 1111 0101 */ f8_ns(cpustate, 0x5); break; - case 0xf6: /* 1111 0110 */ f8_ns(cpustate, 0x6); break; - case 0xf7: /* 1111 0111 */ f8_ns(cpustate, 0x7); break; - case 0xf8: /* 1111 1000 */ f8_ns(cpustate, 0x8); break; - case 0xf9: /* 1111 1001 */ f8_ns(cpustate, 0x9); break; - case 0xfa: /* 1111 1010 */ f8_ns(cpustate, 0xa); break; - case 0xfb: /* 1111 1011 */ f8_ns(cpustate, 0xb); break; - case 0xfc: /* 1111 1100 */ f8_ns_isar(cpustate); break; - case 0xfd: /* 1111 1101 */ f8_ns_isar_i(cpustate); break; - case 0xfe: /* 1111 1110 */ f8_ns_isar_d(cpustate); break; - case 0xff: /* 1111 1111 */ illegal(cpustate); break; - } + case 0x00: /* 0000 0000 */ f8_lr_a_ku(cpustate); break; + case 0x01: /* 0000 0001 */ f8_lr_a_kl(cpustate); break; + case 0x02: /* 0000 0010 */ f8_lr_a_qu(cpustate); break; + case 0x03: /* 0000 0011 */ f8_lr_a_ql(cpustate); break; + case 0x04: /* 0000 0100 */ f8_lr_ku_a(cpustate); break; + case 0x05: /* 0000 0101 */ f8_lr_kl_a(cpustate); break; + case 0x06: /* 0000 0110 */ f8_lr_qu_a(cpustate); break; + case 0x07: /* 0000 0111 */ f8_lr_ql_a(cpustate); break; + case 0x08: /* 0000 1000 */ f8_lr_k_p(cpustate); break; + case 0x09: /* 0000 1001 */ f8_lr_p_k(cpustate); break; + case 0x0a: /* 0000 1010 */ f8_lr_a_is(cpustate); break; + case 0x0b: /* 0000 1011 */ f8_lr_is_a(cpustate); break; + case 0x0c: /* 0000 1100 */ f8_pk(cpustate); break; + case 0x0d: /* 0000 1101 */ f8_lr_p0_q(cpustate); break; + case 0x0e: /* 0000 1110 */ f8_lr_q_dc(cpustate); break; + case 0x0f: /* 0000 1111 */ f8_lr_dc_q(cpustate); break; + + case 0x10: /* 0001 0000 */ f8_lr_dc_h(cpustate); break; + case 0x11: /* 0001 0001 */ f8_lr_h_dc(cpustate); break; + case 0x12: /* 0001 0010 */ f8_sr_1(cpustate); break; + case 0x13: /* 0001 0011 */ f8_sl_1(cpustate); break; + case 0x14: /* 0001 0100 */ f8_sr_4(cpustate); break; + case 0x15: /* 0001 0101 */ f8_sl_4(cpustate); break; + case 0x16: /* 0001 0110 */ f8_lm(cpustate); break; + case 0x17: /* 0001 0111 */ f8_st(cpustate); break; + case 0x18: /* 0001 1000 */ f8_com(cpustate); break; + case 0x19: /* 0001 1001 */ f8_lnk(cpustate); break; + case 0x1a: /* 0001 1010 */ f8_di(cpustate); break; + case 0x1b: /* 0001 1011 */ f8_ei(cpustate); break; + case 0x1c: /* 0001 1100 */ f8_pop(cpustate); break; + case 0x1d: /* 0001 1101 */ f8_lr_w_j(cpustate); break; + case 0x1e: /* 0001 1110 */ f8_lr_j_w(cpustate); break; + case 0x1f: /* 0001 1111 */ f8_inc(cpustate); break; + + case 0x20: /* 0010 0000 */ f8_li(cpustate); break; + case 0x21: /* 0010 0001 */ f8_ni(cpustate); break; + case 0x22: /* 0010 0010 */ f8_oi(cpustate); break; + case 0x23: /* 0010 0011 */ f8_xi(cpustate); break; + case 0x24: /* 0010 0100 */ f8_ai(cpustate); break; + case 0x25: /* 0010 0101 */ f8_ci(cpustate); break; + case 0x26: /* 0010 0110 */ f8_in(cpustate); break; + case 0x27: /* 0010 0111 */ f8_out(cpustate); break; + case 0x28: /* 0010 1000 */ f8_pi(cpustate); break; + case 0x29: /* 0010 1001 */ f8_jmp(cpustate); break; + case 0x2a: /* 0010 1010 */ f8_dci(cpustate); break; + case 0x2b: /* 0010 1011 */ f8_nop(cpustate); break; + case 0x2c: /* 0010 1100 */ f8_xdc(cpustate); break; + case 0x2d: /* 0010 1101 */ illegal(cpustate); break; + case 0x2e: /* 0010 1110 */ illegal(cpustate); break; + case 0x2f: /* 0010 1111 */ illegal(cpustate); break; + + case 0x30: /* 0011 0000 */ f8_ds_r(cpustate, 0); break; + case 0x31: /* 0011 0001 */ f8_ds_r(cpustate, 1); break; + case 0x32: /* 0011 0010 */ f8_ds_r(cpustate, 2); break; + case 0x33: /* 0011 0011 */ f8_ds_r(cpustate, 3); break; + case 0x34: /* 0011 0100 */ f8_ds_r(cpustate, 4); break; + case 0x35: /* 0011 0101 */ f8_ds_r(cpustate, 5); break; + case 0x36: /* 0011 0110 */ f8_ds_r(cpustate, 6); break; + case 0x37: /* 0011 0111 */ f8_ds_r(cpustate, 7); break; + case 0x38: /* 0011 1000 */ f8_ds_r(cpustate, 8); break; + case 0x39: /* 0011 1001 */ f8_ds_r(cpustate, 9); break; + case 0x3a: /* 0011 1010 */ f8_ds_r(cpustate, 10); break; + case 0x3b: /* 0011 1011 */ f8_ds_r(cpustate, 11); break; + case 0x3c: /* 0011 1100 */ f8_ds_isar(cpustate); break; + case 0x3d: /* 0011 1101 */ f8_ds_isar_i(cpustate); break; + case 0x3e: /* 0011 1110 */ f8_ds_isar_d(cpustate); break; + case 0x3f: /* 0011 1111 */ illegal(cpustate); break; + + case 0x40: /* 0100 0000 */ f8_lr_a_r(cpustate, 0); break; + case 0x41: /* 0100 0001 */ f8_lr_a_r(cpustate, 1); break; + case 0x42: /* 0100 0010 */ f8_lr_a_r(cpustate, 2); break; + case 0x43: /* 0100 0011 */ f8_lr_a_r(cpustate, 3); break; + case 0x44: /* 0100 0100 */ f8_lr_a_r(cpustate, 4); break; + case 0x45: /* 0100 0101 */ f8_lr_a_r(cpustate, 5); break; + case 0x46: /* 0100 0110 */ f8_lr_a_r(cpustate, 6); break; + case 0x47: /* 0100 0111 */ f8_lr_a_r(cpustate, 7); break; + case 0x48: /* 0100 1000 */ f8_lr_a_r(cpustate, 8); break; + case 0x49: /* 0100 1001 */ f8_lr_a_r(cpustate, 9); break; + case 0x4a: /* 0100 1010 */ f8_lr_a_r(cpustate, 10); break; + case 0x4b: /* 0100 1011 */ f8_lr_a_r(cpustate, 11); break; + case 0x4c: /* 0100 1100 */ f8_lr_a_isar(cpustate); break; + case 0x4d: /* 0100 1101 */ f8_lr_a_isar_i(cpustate); break; + case 0x4e: /* 0100 1110 */ f8_lr_a_isar_d(cpustate); break; + case 0x4f: /* 0100 1111 */ illegal(cpustate); break; + + case 0x50: /* 0101 0000 */ f8_lr_r_a(cpustate, 0); break; + case 0x51: /* 0101 0001 */ f8_lr_r_a(cpustate, 1); break; + case 0x52: /* 0101 0010 */ f8_lr_r_a(cpustate, 2); break; + case 0x53: /* 0101 0011 */ f8_lr_r_a(cpustate, 3); break; + case 0x54: /* 0101 0100 */ f8_lr_r_a(cpustate, 4); break; + case 0x55: /* 0101 0101 */ f8_lr_r_a(cpustate, 5); break; + case 0x56: /* 0101 0110 */ f8_lr_r_a(cpustate, 6); break; + case 0x57: /* 0101 0111 */ f8_lr_r_a(cpustate, 7); break; + case 0x58: /* 0101 1000 */ f8_lr_r_a(cpustate, 8); break; + case 0x59: /* 0101 1001 */ f8_lr_r_a(cpustate, 9); break; + case 0x5a: /* 0101 1010 */ f8_lr_r_a(cpustate, 10); break; + case 0x5b: /* 0101 1011 */ f8_lr_r_a(cpustate, 11); break; + case 0x5c: /* 0101 1100 */ f8_lr_isar_a(cpustate); break; + case 0x5d: /* 0101 1101 */ f8_lr_isar_i_a(cpustate); break; + case 0x5e: /* 0101 1110 */ f8_lr_isar_d_a(cpustate); break; + case 0x5f: /* 0101 1111 */ illegal(cpustate); break; + + case 0x60: /* 0110 0000 */ f8_lisu(cpustate, 0x00); break; + case 0x61: /* 0110 0001 */ f8_lisu(cpustate, 0x08); break; + case 0x62: /* 0110 0010 */ f8_lisu(cpustate, 0x10); break; + case 0x63: /* 0110 0011 */ f8_lisu(cpustate, 0x18); break; + case 0x64: /* 0110 0100 */ f8_lisu(cpustate, 0x20); break; + case 0x65: /* 0110 0101 */ f8_lisu(cpustate, 0x28); break; + case 0x66: /* 0110 0110 */ f8_lisu(cpustate, 0x30); break; + case 0x67: /* 0110 0111 */ f8_lisu(cpustate, 0x38); break; + case 0x68: /* 0110 1000 */ f8_lisl(cpustate, 0x00); break; + case 0x69: /* 0110 1001 */ f8_lisl(cpustate, 0x01); break; + case 0x6a: /* 0110 1010 */ f8_lisl(cpustate, 0x02); break; + case 0x6b: /* 0110 1011 */ f8_lisl(cpustate, 0x03); break; + case 0x6c: /* 0110 1100 */ f8_lisl(cpustate, 0x04); break; + case 0x6d: /* 0110 1101 */ f8_lisl(cpustate, 0x05); break; + case 0x6e: /* 0110 1110 */ f8_lisl(cpustate, 0x06); break; + case 0x6f: /* 0110 1111 */ f8_lisl(cpustate, 0x07); break; + + case 0x70: /* 0111 0000 */ f8_lis(cpustate, 0x0); break; + case 0x71: /* 0111 0001 */ f8_lis(cpustate, 0x1); break; + case 0x72: /* 0111 0010 */ f8_lis(cpustate, 0x2); break; + case 0x73: /* 0111 0011 */ f8_lis(cpustate, 0x3); break; + case 0x74: /* 0111 0100 */ f8_lis(cpustate, 0x4); break; + case 0x75: /* 0111 0101 */ f8_lis(cpustate, 0x5); break; + case 0x76: /* 0111 0110 */ f8_lis(cpustate, 0x6); break; + case 0x77: /* 0111 0111 */ f8_lis(cpustate, 0x7); break; + case 0x78: /* 0111 1000 */ f8_lis(cpustate, 0x8); break; + case 0x79: /* 0111 1001 */ f8_lis(cpustate, 0x9); break; + case 0x7a: /* 0111 1010 */ f8_lis(cpustate, 0xa); break; + case 0x7b: /* 0111 1011 */ f8_lis(cpustate, 0xb); break; + case 0x7c: /* 0111 1100 */ f8_lis(cpustate, 0xc); break; + case 0x7d: /* 0111 1101 */ f8_lis(cpustate, 0xd); break; + case 0x7e: /* 0111 1110 */ f8_lis(cpustate, 0xe); break; + case 0x7f: /* 0111 1111 */ f8_lis(cpustate, 0xf); break; + + case 0x80: /* 1000 0000 */ f8_bt(cpustate, 0); break; + case 0x81: /* 1000 0001 */ f8_bt(cpustate, 1); break; + case 0x82: /* 1000 0010 */ f8_bt(cpustate, 2); break; + case 0x83: /* 1000 0011 */ f8_bt(cpustate, 3); break; + case 0x84: /* 1000 0100 */ f8_bt(cpustate, 4); break; + case 0x85: /* 1000 0101 */ f8_bt(cpustate, 5); break; + case 0x86: /* 1000 0110 */ f8_bt(cpustate, 6); break; + case 0x87: /* 1000 0111 */ f8_bt(cpustate, 7); break; + case 0x88: /* 1000 1000 */ f8_am(cpustate); break; + case 0x89: /* 1000 1001 */ f8_amd(cpustate); break; + case 0x8a: /* 1000 1010 */ f8_nm(cpustate); break; + case 0x8b: /* 1000 1011 */ f8_om(cpustate); break; + case 0x8c: /* 1000 1100 */ f8_xm(cpustate); break; + case 0x8d: /* 1000 1101 */ f8_cm(cpustate); break; + case 0x8e: /* 1000 1110 */ f8_adc(cpustate); break; + case 0x8f: /* 1000 1111 */ f8_br7(cpustate); break; + + case 0x90: /* 1001 0000 */ f8_bf(cpustate, 0x0); break; + case 0x91: /* 1001 0001 */ f8_bf(cpustate, 0x1); break; + case 0x92: /* 1001 0010 */ f8_bf(cpustate, 0x2); break; + case 0x93: /* 1001 0011 */ f8_bf(cpustate, 0x3); break; + case 0x94: /* 1001 0100 */ f8_bf(cpustate, 0x4); break; + case 0x95: /* 1001 0101 */ f8_bf(cpustate, 0x5); break; + case 0x96: /* 1001 0110 */ f8_bf(cpustate, 0x6); break; + case 0x97: /* 1001 0111 */ f8_bf(cpustate, 0x7); break; + case 0x98: /* 1001 1000 */ f8_bf(cpustate, 0x8); break; + case 0x99: /* 1001 1001 */ f8_bf(cpustate, 0x9); break; + case 0x9a: /* 1001 1010 */ f8_bf(cpustate, 0xa); break; + case 0x9b: /* 1001 1011 */ f8_bf(cpustate, 0xb); break; + case 0x9c: /* 1001 1100 */ f8_bf(cpustate, 0xc); break; + case 0x9d: /* 1001 1101 */ f8_bf(cpustate, 0xd); break; + case 0x9e: /* 1001 1110 */ f8_bf(cpustate, 0xe); break; + case 0x9f: /* 1001 1111 */ f8_bf(cpustate, 0xf); break; + + case 0xa0: /* 1010 0000 */ f8_ins_0(cpustate, 0x0); break; + case 0xa1: /* 1010 0001 */ f8_ins_0(cpustate, 0x1); break; + case 0xa2: /* 1010 0010 */ illegal(cpustate); break; + case 0xa3: /* 1010 0011 */ illegal(cpustate); break; + case 0xa4: /* 1010 0100 */ f8_ins_1(cpustate, 0x4); break; + case 0xa5: /* 1010 0101 */ f8_ins_1(cpustate, 0x5); break; + case 0xa6: /* 1010 0110 */ f8_ins_1(cpustate, 0x6); break; + case 0xa7: /* 1010 0111 */ f8_ins_1(cpustate, 0x7); break; + case 0xa8: /* 1010 1000 */ f8_ins_1(cpustate, 0x8); break; + case 0xa9: /* 1010 1001 */ f8_ins_1(cpustate, 0x9); break; + case 0xaa: /* 1010 1010 */ f8_ins_1(cpustate, 0xa); break; + case 0xab: /* 1010 1011 */ f8_ins_1(cpustate, 0xb); break; + case 0xac: /* 1010 1100 */ f8_ins_1(cpustate, 0xc); break; + case 0xad: /* 1010 1101 */ f8_ins_1(cpustate, 0xd); break; + case 0xae: /* 1010 1110 */ f8_ins_1(cpustate, 0xe); break; + case 0xaf: /* 1010 1111 */ f8_ins_1(cpustate, 0xf); break; + + case 0xb0: /* 1011 0000 */ f8_outs_0(cpustate, 0x0); break; + case 0xb1: /* 1011 0001 */ f8_outs_0(cpustate, 0x1); break; + case 0xb2: /* 1011 0010 */ illegal(cpustate); break; + case 0xb3: /* 1011 0011 */ illegal(cpustate); break; + case 0xb4: /* 1011 0100 */ f8_outs_1(cpustate, 0x4); break; + case 0xb5: /* 1011 0101 */ f8_outs_1(cpustate, 0x5); break; + case 0xb6: /* 1011 0110 */ f8_outs_1(cpustate, 0x6); break; + case 0xb7: /* 1011 0111 */ f8_outs_1(cpustate, 0x7); break; + case 0xb8: /* 1011 1000 */ f8_outs_1(cpustate, 0x8); break; + case 0xb9: /* 1011 1001 */ f8_outs_1(cpustate, 0x9); break; + case 0xba: /* 1011 1010 */ f8_outs_1(cpustate, 0xa); break; + case 0xbb: /* 1011 1011 */ f8_outs_1(cpustate, 0xb); break; + case 0xbc: /* 1011 1100 */ f8_outs_1(cpustate, 0xc); break; + case 0xbd: /* 1011 1101 */ f8_outs_1(cpustate, 0xd); break; + case 0xbe: /* 1011 1110 */ f8_outs_1(cpustate, 0xe); break; + case 0xbf: /* 1011 1111 */ f8_outs_1(cpustate, 0xf); break; + + case 0xc0: /* 1100 0000 */ f8_as(cpustate, 0x0); break; + case 0xc1: /* 1100 0001 */ f8_as(cpustate, 0x1); break; + case 0xc2: /* 1100 0010 */ f8_as(cpustate, 0x2); break; + case 0xc3: /* 1100 0011 */ f8_as(cpustate, 0x3); break; + case 0xc4: /* 1100 0100 */ f8_as(cpustate, 0x4); break; + case 0xc5: /* 1100 0101 */ f8_as(cpustate, 0x5); break; + case 0xc6: /* 1100 0110 */ f8_as(cpustate, 0x6); break; + case 0xc7: /* 1100 0111 */ f8_as(cpustate, 0x7); break; + case 0xc8: /* 1100 1000 */ f8_as(cpustate, 0x8); break; + case 0xc9: /* 1100 1001 */ f8_as(cpustate, 0x9); break; + case 0xca: /* 1100 1010 */ f8_as(cpustate, 0xa); break; + case 0xcb: /* 1100 1011 */ f8_as(cpustate, 0xb); break; + case 0xcc: /* 1100 1100 */ f8_as_isar(cpustate); break; + case 0xcd: /* 1100 1101 */ f8_as_isar_i(cpustate); break; + case 0xce: /* 1100 1110 */ f8_as_isar_d(cpustate); break; + case 0xcf: /* 1100 1111 */ illegal(cpustate); break; + + case 0xd0: /* 1101 0000 */ f8_asd(cpustate, 0x0); break; + case 0xd1: /* 1101 0001 */ f8_asd(cpustate, 0x1); break; + case 0xd2: /* 1101 0010 */ f8_asd(cpustate, 0x2); break; + case 0xd3: /* 1101 0011 */ f8_asd(cpustate, 0x3); break; + case 0xd4: /* 1101 0100 */ f8_asd(cpustate, 0x4); break; + case 0xd5: /* 1101 0101 */ f8_asd(cpustate, 0x5); break; + case 0xd6: /* 1101 0110 */ f8_asd(cpustate, 0x6); break; + case 0xd7: /* 1101 0111 */ f8_asd(cpustate, 0x7); break; + case 0xd8: /* 1101 1000 */ f8_asd(cpustate, 0x8); break; + case 0xd9: /* 1101 1001 */ f8_asd(cpustate, 0x9); break; + case 0xda: /* 1101 1010 */ f8_asd(cpustate, 0xa); break; + case 0xdb: /* 1101 1011 */ f8_asd(cpustate, 0xb); break; + case 0xdc: /* 1101 1100 */ f8_asd_isar(cpustate); break; + case 0xdd: /* 1101 1101 */ f8_asd_isar_i(cpustate); break; + case 0xde: /* 1101 1110 */ f8_asd_isar_d(cpustate); break; + case 0xdf: /* 1101 1111 */ illegal(cpustate); break; + + case 0xe0: /* 1110 0000 */ f8_xs(cpustate, 0x0); break; + case 0xe1: /* 1110 0001 */ f8_xs(cpustate, 0x1); break; + case 0xe2: /* 1110 0010 */ f8_xs(cpustate, 0x2); break; + case 0xe3: /* 1110 0011 */ f8_xs(cpustate, 0x3); break; + case 0xe4: /* 1110 0100 */ f8_xs(cpustate, 0x4); break; + case 0xe5: /* 1110 0101 */ f8_xs(cpustate, 0x5); break; + case 0xe6: /* 1110 0110 */ f8_xs(cpustate, 0x6); break; + case 0xe7: /* 1110 0111 */ f8_xs(cpustate, 0x7); break; + case 0xe8: /* 1110 1000 */ f8_xs(cpustate, 0x8); break; + case 0xe9: /* 1110 1001 */ f8_xs(cpustate, 0x9); break; + case 0xea: /* 1110 1010 */ f8_xs(cpustate, 0xa); break; + case 0xeb: /* 1110 1011 */ f8_xs(cpustate, 0xb); break; + case 0xec: /* 1110 1100 */ f8_xs_isar(cpustate); break; + case 0xed: /* 1110 1101 */ f8_xs_isar_i(cpustate); break; + case 0xee: /* 1110 1110 */ f8_xs_isar_d(cpustate); break; + case 0xef: /* 1110 1111 */ illegal(cpustate); break; + + case 0xf0: /* 1111 0000 */ f8_ns(cpustate, 0x0); break; + case 0xf1: /* 1111 0001 */ f8_ns(cpustate, 0x1); break; + case 0xf2: /* 1111 0010 */ f8_ns(cpustate, 0x2); break; + case 0xf3: /* 1111 0011 */ f8_ns(cpustate, 0x3); break; + case 0xf4: /* 1111 0100 */ f8_ns(cpustate, 0x4); break; + case 0xf5: /* 1111 0101 */ f8_ns(cpustate, 0x5); break; + case 0xf6: /* 1111 0110 */ f8_ns(cpustate, 0x6); break; + case 0xf7: /* 1111 0111 */ f8_ns(cpustate, 0x7); break; + case 0xf8: /* 1111 1000 */ f8_ns(cpustate, 0x8); break; + case 0xf9: /* 1111 1001 */ f8_ns(cpustate, 0x9); break; + case 0xfa: /* 1111 1010 */ f8_ns(cpustate, 0xa); break; + case 0xfb: /* 1111 1011 */ f8_ns(cpustate, 0xb); break; + case 0xfc: /* 1111 1100 */ f8_ns_isar(cpustate); break; + case 0xfd: /* 1111 1101 */ f8_ns_isar_i(cpustate); break; + case 0xfe: /* 1111 1110 */ f8_ns_isar_d(cpustate); break; + case 0xff: /* 1111 1111 */ illegal(cpustate); break; + } switch (op) { case 0x0d:case 0x1b:case 0x1c:case 0x1d: case 0x27:case 0x28:case 0x29: case 0xb4:case 0xb5:case 0xb6:case 0xb7: case 0xb8:case 0xb9:case 0xba:case 0xbb: case 0xbc:case 0xbd:case 0xbe:case 0xbf: - ROMC_00(cpustate, cS); - break; + ROMC_00(cpustate, cS); + break; default: - if (cpustate->w&I && cpustate->irq_request) { + if (cpustate->w&I && cpustate->irq_request) { ROMC_1C(cpustate, cL); ROMC_0F(cpustate); ROMC_13(cpustate); - } - if((op>=0x30)&&(op<=0x3f)) /* SKR - DS is a long cycle inst */ - ROMC_00(cpustate, cL); - else - ROMC_00(cpustate, cS); - break; + } + if((op>=0x30)&&(op<=0x3f)) /* SKR - DS is a long cycle inst */ + ROMC_00(cpustate, cL); + else + ROMC_00(cpustate, cS); + break; } - } while( cpustate->icount > 0 ); + } while( cpustate->icount > 0 ); } CPU_DISASSEMBLE( f8 ); @@ -1991,26 +1991,26 @@ static CPU_SET_INFO( f8 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_SP: cpustate->pc1 = info->i; break; + case CPUINFO_INT_SP: cpustate->pc1 = info->i; break; case CPUINFO_INT_PC: cpustate->pc0 = info->i; cpustate->dbus = cpustate->direct->read_decrypted_byte(cpustate->pc0); - cpustate->pc0 += 1; + cpustate->pc0 += 1; break; - case CPUINFO_INT_PREVIOUSPC: break; /* TODO? */ - case CPUINFO_INT_INPUT_STATE + F8_INPUT_LINE_INT_REQ: cpustate->irq_request = info->i; break; + case CPUINFO_INT_PREVIOUSPC: break; /* TODO? */ + case CPUINFO_INT_INPUT_STATE + F8_INPUT_LINE_INT_REQ: cpustate->irq_request = info->i; break; case CPUINFO_INT_REGISTER + F8_PC0: cpustate->pc0 = info->i; cpustate->dbus = cpustate->direct->read_decrypted_byte(cpustate->pc0); - cpustate->pc0 += 1; + cpustate->pc0 += 1; break; case CPUINFO_INT_REGISTER + F8_PC1: cpustate->pc1 = info->i; break; case CPUINFO_INT_REGISTER + F8_DC0: cpustate->dc0 = info->i; break; case CPUINFO_INT_REGISTER + F8_DC1: cpustate->dc1 = info->i; break; - case CPUINFO_INT_REGISTER + F8_W: cpustate->w = info->i; break; - case CPUINFO_INT_REGISTER + F8_A: cpustate->a = info->i; break; + case CPUINFO_INT_REGISTER + F8_W: cpustate->w = info->i; break; + case CPUINFO_INT_REGISTER + F8_A: cpustate->a = info->i; break; case CPUINFO_INT_REGISTER + F8_IS: cpustate->is = info->i & 0x3f; break; - case CPUINFO_INT_REGISTER + F8_J: cpustate->r[ 9] = info->i; break; + case CPUINFO_INT_REGISTER + F8_J: cpustate->r[ 9] = info->i; break; case CPUINFO_INT_REGISTER + F8_HU: cpustate->r[10] = info->i; break; case CPUINFO_INT_REGISTER + F8_HL: cpustate->r[11] = info->i; break; case CPUINFO_INT_REGISTER + F8_KU: cpustate->r[12] = info->i; break; @@ -2091,130 +2091,130 @@ CPU_GET_INFO( f8 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(f8_Regs); break; - case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 7; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_SP: info->i = cpustate->pc1; break; - case CPUINFO_INT_PC: info->i = (cpustate->pc0 - 1) & 0xffff; break; - case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* TODO??? */ break; - - case CPUINFO_INT_INPUT_STATE + F8_INPUT_LINE_INT_REQ: info->i = cpustate->irq_request; break; - - case CPUINFO_INT_REGISTER + F8_PC0: info->i = (cpustate->pc0 - 1) & 0xffff; break; - case CPUINFO_INT_REGISTER + F8_PC1: info->i = cpustate->pc1; break; - case CPUINFO_INT_REGISTER + F8_DC0: info->i = cpustate->dc0; break; - case CPUINFO_INT_REGISTER + F8_DC1: info->i = cpustate->dc1; break; - case CPUINFO_INT_REGISTER + F8_W: info->i = cpustate->w; break; - case CPUINFO_INT_REGISTER + F8_A: info->i = cpustate->a; break; - case CPUINFO_INT_REGISTER + F8_IS: info->i = cpustate->is; break; - case CPUINFO_INT_REGISTER + F8_J: info->i = cpustate->r[ 9]; break; - case CPUINFO_INT_REGISTER + F8_HU: info->i = cpustate->r[10]; break; - case CPUINFO_INT_REGISTER + F8_HL: info->i = cpustate->r[11]; break; - case CPUINFO_INT_REGISTER + F8_KU: info->i = cpustate->r[12]; break; - case CPUINFO_INT_REGISTER + F8_KL: info->i = cpustate->r[13]; break; - case CPUINFO_INT_REGISTER + F8_QU: info->i = cpustate->r[14]; break; - case CPUINFO_INT_REGISTER + F8_QL: info->i = cpustate->r[15]; break; - - case CPUINFO_INT_REGISTER + F8_R0: - case CPUINFO_INT_REGISTER + F8_R1: - case CPUINFO_INT_REGISTER + F8_R2: - case CPUINFO_INT_REGISTER + F8_R3: - case CPUINFO_INT_REGISTER + F8_R4: - case CPUINFO_INT_REGISTER + F8_R5: - case CPUINFO_INT_REGISTER + F8_R6: - case CPUINFO_INT_REGISTER + F8_R7: - case CPUINFO_INT_REGISTER + F8_R8: - info->i = cpustate->r[state - (CPUINFO_INT_REGISTER + F8_R0)]; break; - - - case CPUINFO_INT_REGISTER + F8_R16: - case CPUINFO_INT_REGISTER + F8_R17: - case CPUINFO_INT_REGISTER + F8_R18: - case CPUINFO_INT_REGISTER + F8_R19: - case CPUINFO_INT_REGISTER + F8_R20: - case CPUINFO_INT_REGISTER + F8_R21: - case CPUINFO_INT_REGISTER + F8_R22: - case CPUINFO_INT_REGISTER + F8_R23: - case CPUINFO_INT_REGISTER + F8_R24: - case CPUINFO_INT_REGISTER + F8_R25: - case CPUINFO_INT_REGISTER + F8_R26: - case CPUINFO_INT_REGISTER + F8_R27: - case CPUINFO_INT_REGISTER + F8_R28: - case CPUINFO_INT_REGISTER + F8_R29: - case CPUINFO_INT_REGISTER + F8_R30: - case CPUINFO_INT_REGISTER + F8_R31: - case CPUINFO_INT_REGISTER + F8_R32: - case CPUINFO_INT_REGISTER + F8_R33: - case CPUINFO_INT_REGISTER + F8_R34: - case CPUINFO_INT_REGISTER + F8_R35: - case CPUINFO_INT_REGISTER + F8_R36: - case CPUINFO_INT_REGISTER + F8_R37: - case CPUINFO_INT_REGISTER + F8_R38: - case CPUINFO_INT_REGISTER + F8_R39: - case CPUINFO_INT_REGISTER + F8_R40: - case CPUINFO_INT_REGISTER + F8_R41: - case CPUINFO_INT_REGISTER + F8_R42: - case CPUINFO_INT_REGISTER + F8_R43: - case CPUINFO_INT_REGISTER + F8_R44: - case CPUINFO_INT_REGISTER + F8_R45: - case CPUINFO_INT_REGISTER + F8_R46: - case CPUINFO_INT_REGISTER + F8_R47: - case CPUINFO_INT_REGISTER + F8_R48: - case CPUINFO_INT_REGISTER + F8_R49: - case CPUINFO_INT_REGISTER + F8_R50: - case CPUINFO_INT_REGISTER + F8_R51: - case CPUINFO_INT_REGISTER + F8_R52: - case CPUINFO_INT_REGISTER + F8_R53: - case CPUINFO_INT_REGISTER + F8_R54: - case CPUINFO_INT_REGISTER + F8_R55: - case CPUINFO_INT_REGISTER + F8_R56: - case CPUINFO_INT_REGISTER + F8_R57: - case CPUINFO_INT_REGISTER + F8_R58: - case CPUINFO_INT_REGISTER + F8_R59: - case CPUINFO_INT_REGISTER + F8_R60: - case CPUINFO_INT_REGISTER + F8_R61: - case CPUINFO_INT_REGISTER + F8_R62: - case CPUINFO_INT_REGISTER + F8_R63: - info->i = cpustate->r[state - (CPUINFO_INT_REGISTER + F8_R16) + 16]; break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(f8_Regs); break; + case CPUINFO_INT_INPUT_LINES: info->i = 1; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 7; break; + + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + + case CPUINFO_INT_SP: info->i = cpustate->pc1; break; + case CPUINFO_INT_PC: info->i = (cpustate->pc0 - 1) & 0xffff; break; + case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* TODO??? */ break; + + case CPUINFO_INT_INPUT_STATE + F8_INPUT_LINE_INT_REQ: info->i = cpustate->irq_request; break; + + case CPUINFO_INT_REGISTER + F8_PC0: info->i = (cpustate->pc0 - 1) & 0xffff; break; + case CPUINFO_INT_REGISTER + F8_PC1: info->i = cpustate->pc1; break; + case CPUINFO_INT_REGISTER + F8_DC0: info->i = cpustate->dc0; break; + case CPUINFO_INT_REGISTER + F8_DC1: info->i = cpustate->dc1; break; + case CPUINFO_INT_REGISTER + F8_W: info->i = cpustate->w; break; + case CPUINFO_INT_REGISTER + F8_A: info->i = cpustate->a; break; + case CPUINFO_INT_REGISTER + F8_IS: info->i = cpustate->is; break; + case CPUINFO_INT_REGISTER + F8_J: info->i = cpustate->r[ 9]; break; + case CPUINFO_INT_REGISTER + F8_HU: info->i = cpustate->r[10]; break; + case CPUINFO_INT_REGISTER + F8_HL: info->i = cpustate->r[11]; break; + case CPUINFO_INT_REGISTER + F8_KU: info->i = cpustate->r[12]; break; + case CPUINFO_INT_REGISTER + F8_KL: info->i = cpustate->r[13]; break; + case CPUINFO_INT_REGISTER + F8_QU: info->i = cpustate->r[14]; break; + case CPUINFO_INT_REGISTER + F8_QL: info->i = cpustate->r[15]; break; + + case CPUINFO_INT_REGISTER + F8_R0: + case CPUINFO_INT_REGISTER + F8_R1: + case CPUINFO_INT_REGISTER + F8_R2: + case CPUINFO_INT_REGISTER + F8_R3: + case CPUINFO_INT_REGISTER + F8_R4: + case CPUINFO_INT_REGISTER + F8_R5: + case CPUINFO_INT_REGISTER + F8_R6: + case CPUINFO_INT_REGISTER + F8_R7: + case CPUINFO_INT_REGISTER + F8_R8: + info->i = cpustate->r[state - (CPUINFO_INT_REGISTER + F8_R0)]; break; + + + case CPUINFO_INT_REGISTER + F8_R16: + case CPUINFO_INT_REGISTER + F8_R17: + case CPUINFO_INT_REGISTER + F8_R18: + case CPUINFO_INT_REGISTER + F8_R19: + case CPUINFO_INT_REGISTER + F8_R20: + case CPUINFO_INT_REGISTER + F8_R21: + case CPUINFO_INT_REGISTER + F8_R22: + case CPUINFO_INT_REGISTER + F8_R23: + case CPUINFO_INT_REGISTER + F8_R24: + case CPUINFO_INT_REGISTER + F8_R25: + case CPUINFO_INT_REGISTER + F8_R26: + case CPUINFO_INT_REGISTER + F8_R27: + case CPUINFO_INT_REGISTER + F8_R28: + case CPUINFO_INT_REGISTER + F8_R29: + case CPUINFO_INT_REGISTER + F8_R30: + case CPUINFO_INT_REGISTER + F8_R31: + case CPUINFO_INT_REGISTER + F8_R32: + case CPUINFO_INT_REGISTER + F8_R33: + case CPUINFO_INT_REGISTER + F8_R34: + case CPUINFO_INT_REGISTER + F8_R35: + case CPUINFO_INT_REGISTER + F8_R36: + case CPUINFO_INT_REGISTER + F8_R37: + case CPUINFO_INT_REGISTER + F8_R38: + case CPUINFO_INT_REGISTER + F8_R39: + case CPUINFO_INT_REGISTER + F8_R40: + case CPUINFO_INT_REGISTER + F8_R41: + case CPUINFO_INT_REGISTER + F8_R42: + case CPUINFO_INT_REGISTER + F8_R43: + case CPUINFO_INT_REGISTER + F8_R44: + case CPUINFO_INT_REGISTER + F8_R45: + case CPUINFO_INT_REGISTER + F8_R46: + case CPUINFO_INT_REGISTER + F8_R47: + case CPUINFO_INT_REGISTER + F8_R48: + case CPUINFO_INT_REGISTER + F8_R49: + case CPUINFO_INT_REGISTER + F8_R50: + case CPUINFO_INT_REGISTER + F8_R51: + case CPUINFO_INT_REGISTER + F8_R52: + case CPUINFO_INT_REGISTER + F8_R53: + case CPUINFO_INT_REGISTER + F8_R54: + case CPUINFO_INT_REGISTER + F8_R55: + case CPUINFO_INT_REGISTER + F8_R56: + case CPUINFO_INT_REGISTER + F8_R57: + case CPUINFO_INT_REGISTER + F8_R58: + case CPUINFO_INT_REGISTER + F8_R59: + case CPUINFO_INT_REGISTER + F8_R60: + case CPUINFO_INT_REGISTER + F8_R61: + case CPUINFO_INT_REGISTER + F8_R62: + case CPUINFO_INT_REGISTER + F8_R63: + info->i = cpustate->r[state - (CPUINFO_INT_REGISTER + F8_R16) + 16]; break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(f8); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(f8); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(f8); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(f8); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(f8); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(f8); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(f8); break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(f8); break; + case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(f8); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(f8); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "F8"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Fairchild F8"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, + case CPUINFO_STR_NAME: strcpy(info->s, "F8"); break; + case CPUINFO_STR_FAMILY: strcpy(info->s, "Fairchild F8"); break; + case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break; - case CPUINFO_STR_FLAGS: + case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c", cpustate->w & 0x10 ? 'I':'.', cpustate->w & 0x08 ? 'O':'.', diff --git a/src/emu/cpu/f8/f8.h b/src/emu/cpu/f8/f8.h index 51e2e6aeac1..865a45e74a0 100644 --- a/src/emu/cpu/f8/f8.h +++ b/src/emu/cpu/f8/f8.h @@ -32,18 +32,18 @@ extern "C" { enum { F8_PC0=1, F8_PC1, F8_DC0, F8_DC1, F8_W, F8_A, F8_IS, - F8_J, F8_HU, F8_HL, F8_KU, F8_KL, F8_QU, F8_QL, - - F8_R0, F8_R1, F8_R2, F8_R3, F8_R4, F8_R5, F8_R6, F8_R7, F8_R8, - F8_R16, F8_R17, F8_R18, F8_R19, F8_R20, F8_R21, F8_R22, F8_R23, - F8_R24, F8_R25, F8_R26, F8_R27, F8_R28, F8_R29, F8_R30, F8_R31, - F8_R32, F8_R33, F8_R34, F8_R35, F8_R36, F8_R37, F8_R38, F8_R39, - F8_R40, F8_R41, F8_R42, F8_R43, F8_R44, F8_R45, F8_R46, F8_R47, - F8_R48, F8_R49, F8_R50, F8_R51, F8_R52, F8_R53, F8_R54, F8_R55, - F8_R56, F8_R57, F8_R58, F8_R59, F8_R60, F8_R61, F8_R62, F8_R63 + F8_J, F8_HU, F8_HL, F8_KU, F8_KL, F8_QU, F8_QL, + + F8_R0, F8_R1, F8_R2, F8_R3, F8_R4, F8_R5, F8_R6, F8_R7, F8_R8, + F8_R16, F8_R17, F8_R18, F8_R19, F8_R20, F8_R21, F8_R22, F8_R23, + F8_R24, F8_R25, F8_R26, F8_R27, F8_R28, F8_R29, F8_R30, F8_R31, + F8_R32, F8_R33, F8_R34, F8_R35, F8_R36, F8_R37, F8_R38, F8_R39, + F8_R40, F8_R41, F8_R42, F8_R43, F8_R44, F8_R45, F8_R46, F8_R47, + F8_R48, F8_R49, F8_R50, F8_R51, F8_R52, F8_R53, F8_R54, F8_R55, + F8_R56, F8_R57, F8_R58, F8_R59, F8_R60, F8_R61, F8_R62, F8_R63 }; -#define F8_INPUT_LINE_INT_REQ 1 +#define F8_INPUT_LINE_INT_REQ 1 DECLARE_LEGACY_CPU_DEVICE(F8, f8); diff --git a/src/emu/cpu/f8/f8dasm.c b/src/emu/cpu/f8/f8dasm.c index 187dd53a1e6..a28a1b004c4 100644 --- a/src/emu/cpu/f8/f8dasm.c +++ b/src/emu/cpu/f8/f8dasm.c @@ -12,39 +12,39 @@ CPU_DISASSEMBLE( f8 ) unsigned size = 0; UINT8 op = oprom[size++]; - switch( op ) + switch( op ) { /* opcode bitmask */ case 0x00: /* 0000 0000 */ - sprintf(buffer, "LR A,KU"); + sprintf(buffer, "LR A,KU"); break; case 0x01: /* 0000 0001 */ - sprintf(buffer, "LR A,KL"); + sprintf(buffer, "LR A,KL"); break; case 0x02: /* 0000 0010 */ - sprintf(buffer, "LR A,QU"); + sprintf(buffer, "LR A,QU"); break; case 0x03: /* 0000 0011 */ - sprintf(buffer, "LR A,QL"); + sprintf(buffer, "LR A,QL"); break; case 0x04: /* 0000 0100 */ - sprintf(buffer, "LR KU,A"); + sprintf(buffer, "LR KU,A"); break; case 0x05: /* 0000 0101 */ - sprintf(buffer, "LR KL,A"); + sprintf(buffer, "LR KL,A"); break; case 0x06: /* 0000 0110 */ - sprintf(buffer, "LR QU,A"); + sprintf(buffer, "LR QU,A"); break; case 0x07: /* 0000 0111 */ - sprintf(buffer, "LR QL,A"); + sprintf(buffer, "LR QL,A"); break; - case 0x08: /* 0000 1000 */ - sprintf(buffer, "LR K,P"); + case 0x08: /* 0000 1000 */ + sprintf(buffer, "LR K,P"); break; case 0x09: /* 0000 1001 */ - sprintf(buffer, "LR P,K"); + sprintf(buffer, "LR P,K"); break; case 0x0a: /* 0000 1010 */ sprintf(buffer, "LR A,IS"); @@ -53,17 +53,17 @@ CPU_DISASSEMBLE( f8 ) sprintf(buffer, "LR IS,A"); break; - case 0x0c: /* 0000 1100 */ + case 0x0c: /* 0000 1100 */ sprintf(buffer, "PK") ; break; case 0x0d: /* 0000 1101 */ sprintf(buffer, "LR P0,Q"); - break; + break; case 0x0e: /* 0000 1110 */ - sprintf(buffer, "LR Q,DC"); + sprintf(buffer, "LR Q,DC"); break; case 0x0f: /* 0000 1111 */ - sprintf(buffer, "LR DC,Q"); + sprintf(buffer, "LR DC,Q"); break; case 0x10: /* 0001 0000 */ sprintf(buffer, "LR DC,H"); @@ -102,13 +102,13 @@ CPU_DISASSEMBLE( f8 ) sprintf(buffer, "EI"); break; case 0x1c: /* 0001 1100 */ - sprintf(buffer, "POP"); + sprintf(buffer, "POP"); break; case 0x1d: /* 0001 1101 */ - sprintf(buffer, "LR W,J"); + sprintf(buffer, "LR W,J"); break; case 0x1e: /* 0001 1110 */ - sprintf(buffer, "LR J,W"); + sprintf(buffer, "LR J,W"); break; case 0x1f: /* 0001 1111 */ sprintf(buffer, "INC"); @@ -118,37 +118,37 @@ CPU_DISASSEMBLE( f8 ) break; case 0x21: /* 0010 0001 */ sprintf(buffer, "NI $%02X", oprom[size++]); - break; - case 0x22: /* 0010 0010 */ + break; + case 0x22: /* 0010 0010 */ sprintf(buffer, "OI $%02X", oprom[size++]); - break; - case 0x23: /* 0010 0011 */ + break; + case 0x23: /* 0010 0011 */ sprintf(buffer, "XI $%02X", oprom[size++]); - break; + break; case 0x24: /* 0010 0100 */ sprintf(buffer, "AI $%02X", oprom[size++]); - break; + break; case 0x25: /* 0010 0101 */ sprintf(buffer, "CI $%02X", oprom[size++]); - break; + break; case 0x26: /* 0010 0110 */ sprintf(buffer, "IN $%02X", oprom[size++]); - break; + break; case 0x27: /* 0010 0111 */ sprintf(buffer, "OUT $%02X", oprom[size++]); - break; + break; case 0x28: /* 0010 1000 */ sprintf(buffer, "PI $%02X%02X", oprom[size + 0], oprom[size + 1]); size += 2; - break; + break; case 0x29: /* 0010 1001 */ sprintf(buffer, "JMP $%02X%02X", oprom[size + 0], oprom[size + 1]); size += 2; - break; + break; case 0x2a: /* 0010 1010 */ sprintf(buffer, "DCI $%02X%02X", oprom[size + 0], oprom[size + 1]); size += 2; - break; + break; case 0x2b: /* 0010 1011 */ sprintf(buffer, "NOP"); break; @@ -159,9 +159,9 @@ CPU_DISASSEMBLE( f8 ) case 0x2e: /* 0010 1110 */ case 0x2f: /* 0010 1111 */ sprintf(buffer, "??? $%02X",op); - break; + break; - case 0x30: /* 0011 0000 */ + case 0x30: /* 0011 0000 */ case 0x31: /* 0011 0001 */ case 0x32: /* 0011 0010 */ case 0x33: /* 0011 0011 */ @@ -173,23 +173,23 @@ CPU_DISASSEMBLE( f8 ) case 0x39: /* 0011 1001 */ case 0x3a: /* 0011 1010 */ case 0x3b: /* 0011 1011 */ - sprintf(buffer, "DS %s",rname[op & 15]); - break; - case 0x3c: /* 0011 1100 */ - sprintf(buffer, "DS (IS)"); - break; - case 0x3d: /* 0011 1101 */ - sprintf(buffer, "DS (IS++)"); - break; - case 0x3e: /* 0011 1110 */ - sprintf(buffer, "DS (IS--)"); - break; - case 0x3f: /* 0011 1111 */ + sprintf(buffer, "DS %s",rname[op & 15]); + break; + case 0x3c: /* 0011 1100 */ + sprintf(buffer, "DS (IS)"); + break; + case 0x3d: /* 0011 1101 */ + sprintf(buffer, "DS (IS++)"); + break; + case 0x3e: /* 0011 1110 */ + sprintf(buffer, "DS (IS--)"); + break; + case 0x3f: /* 0011 1111 */ sprintf(buffer, "??? $%02X",op); - break; + break; - case 0x40: /* 0100 0000 */ - case 0x41: /* 0100 0001 */ + case 0x40: /* 0100 0000 */ + case 0x41: /* 0100 0001 */ case 0x42: /* 0100 0010 */ case 0x43: /* 0100 0011 */ case 0x44: /* 0100 0100 */ @@ -200,22 +200,22 @@ CPU_DISASSEMBLE( f8 ) case 0x49: /* 0100 1001 */ case 0x4a: /* 0100 1010 */ case 0x4b: /* 0100 1011 */ - sprintf(buffer, "LR A,%s",rname[op & 15]); - break; - case 0x4c: /* 0100 1100 */ - sprintf(buffer, "LR A,(IS)"); - break; - case 0x4d: /* 0100 1101 */ - sprintf(buffer, "LR A,(IS++)"); - break; - case 0x4e: /* 0100 1110 */ - sprintf(buffer, "LR A,(IS--)"); - break; - case 0x4f: /* 0100 1111 */ + sprintf(buffer, "LR A,%s",rname[op & 15]); + break; + case 0x4c: /* 0100 1100 */ + sprintf(buffer, "LR A,(IS)"); + break; + case 0x4d: /* 0100 1101 */ + sprintf(buffer, "LR A,(IS++)"); + break; + case 0x4e: /* 0100 1110 */ + sprintf(buffer, "LR A,(IS--)"); + break; + case 0x4f: /* 0100 1111 */ sprintf(buffer, "??? $%02X",op); - break; + break; - case 0x50: /* 0101 0000 */ + case 0x50: /* 0101 0000 */ case 0x51: /* 0101 0001 */ case 0x52: /* 0101 0010 */ case 0x53: /* 0101 0011 */ @@ -227,23 +227,23 @@ CPU_DISASSEMBLE( f8 ) case 0x59: /* 0101 1001 */ case 0x5a: /* 0101 1010 */ case 0x5b: /* 0101 1011 */ - sprintf(buffer, "LR %s,A",rname[op & 15]); - break; - case 0x5c: /* 0101 1100 */ - sprintf(buffer, "LR (IS),A"); - break; - case 0x5d: /* 0101 1101 */ - sprintf(buffer, "LR (IS++),A"); - break; - case 0x5e: /* 0101 1110 */ - sprintf(buffer, "LR (IS--),A"); - break; - case 0x5f: /* 0101 1111 */ + sprintf(buffer, "LR %s,A",rname[op & 15]); + break; + case 0x5c: /* 0101 1100 */ + sprintf(buffer, "LR (IS),A"); + break; + case 0x5d: /* 0101 1101 */ + sprintf(buffer, "LR (IS++),A"); + break; + case 0x5e: /* 0101 1110 */ + sprintf(buffer, "LR (IS--),A"); + break; + case 0x5f: /* 0101 1111 */ sprintf(buffer, "??? $%02X",op); - break; + break; - case 0x60: /* 0110 0000 */ - case 0x61: /* 0110 0001 */ + case 0x60: /* 0110 0000 */ + case 0x61: /* 0110 0001 */ case 0x62: /* 0110 0010 */ case 0x63: /* 0110 0011 */ case 0x64: /* 0110 0100 */ @@ -252,7 +252,7 @@ CPU_DISASSEMBLE( f8 ) case 0x67: /* 0110 0111 */ sprintf(buffer, "LISU $%02X", op & 0x07); break; - case 0x68: /* 0110 1000 */ + case 0x68: /* 0110 1000 */ case 0x69: /* 0110 1001 */ case 0x6a: /* 0110 1010 */ case 0x6b: /* 0110 1011 */ @@ -261,9 +261,9 @@ CPU_DISASSEMBLE( f8 ) case 0x6e: /* 0110 1110 */ case 0x6f: /* 0110 1111 */ sprintf(buffer, "LISL $%02X", op & 0x07); - break; + break; - case 0x70: /* 0111 0000 */ + case 0x70: /* 0111 0000 */ case 0x71: /* 0111 0001 */ case 0x72: /* 0111 0010 */ case 0x73: /* 0111 0011 */ @@ -285,75 +285,75 @@ CPU_DISASSEMBLE( f8 ) case 0x81: /* 1000 0001 */ case 0x85: /* 1000 0101 */ sprintf(buffer, "BP $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; case 0x82: /* 1000 0010 */ sprintf(buffer, "BC $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; case 0x84: /* 1000 0100 */ sprintf(buffer, "BZ $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; case 0x80: /* 1000 0000 */ case 0x83: /* 1000 0011 */ case 0x86: /* 1000 0110 */ case 0x87: /* 1000 0111 */ sprintf(buffer, "BT $%02X,$%04X", op & 0x07, pc + (INT8)oprom[size++] + 1); - break; + break; - case 0x88: /* 1000 1000 */ + case 0x88: /* 1000 1000 */ sprintf(buffer, "AM"); break; - case 0x89: /* 1000 1001 */ + case 0x89: /* 1000 1001 */ sprintf(buffer, "AMD"); - break; + break; - case 0x8a: /* 1000 1010 */ + case 0x8a: /* 1000 1010 */ sprintf(buffer, "NM"); break; - case 0x8b: /* 1000 1011 */ + case 0x8b: /* 1000 1011 */ sprintf(buffer, "OM"); break; - case 0x8c: /* 1000 1100 */ + case 0x8c: /* 1000 1100 */ sprintf(buffer, "XM"); break; - case 0x8d: /* 1000 1101 */ + case 0x8d: /* 1000 1101 */ sprintf(buffer, "CM"); break; - case 0x8e: /* 1000 1110 */ + case 0x8e: /* 1000 1110 */ sprintf(buffer, "ADC"); - break; + break; - case 0x8f: /* 1000 1111 */ + case 0x8f: /* 1000 1111 */ sprintf(buffer, "BR7 $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; - case 0x90: /* 1001 0000 */ + case 0x90: /* 1001 0000 */ sprintf(buffer, "BR $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; case 0x91: /* 1001 0001 */ case 0x95: /* 1001 0101 */ sprintf(buffer, "BM $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; case 0x92: /* 1001 0010 */ sprintf(buffer, "BNC $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; case 0x94: /* 1001 0100 */ sprintf(buffer, "BNZ $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; case 0x98: /* 1001 1000 */ sprintf(buffer, "BNO $%04X", pc + (INT8)oprom[size++] + 1); - break; + break; case 0x93: /* 1001 0011 */ case 0x96: /* 1001 0110 */ @@ -366,19 +366,19 @@ CPU_DISASSEMBLE( f8 ) case 0x9e: /* 1001 1110 */ case 0x9f: /* 1001 1111 */ sprintf(buffer, "BF $%02X,$%04X", op & 0x0f, pc + (INT8)oprom[size++] + 1); - break; + break; - case 0xa0: /* 1010 0000 */ + case 0xa0: /* 1010 0000 */ case 0xa1: /* 1010 0001 */ sprintf(buffer, "INS $%02X", (unsigned) (INT8) (op & 0x0F)); - break; + break; - case 0xa2: /* 1010 0010 */ + case 0xa2: /* 1010 0010 */ case 0xa3: /* 1010 0011 */ sprintf(buffer, "??? $%02X\n", op); - break; + break; - case 0xa4: /* 1010 0100 */ + case 0xa4: /* 1010 0100 */ case 0xa5: /* 1010 0101 */ case 0xa6: /* 1010 0110 */ case 0xa7: /* 1010 0111 */ @@ -391,19 +391,19 @@ CPU_DISASSEMBLE( f8 ) case 0xae: /* 1010 1110 */ case 0xaf: /* 1010 1111 */ sprintf(buffer, "INS $%02X", (INT8) op & 0x0f); - break; + break; - case 0xb0: /* 1011 0000 */ + case 0xb0: /* 1011 0000 */ case 0xb1: /* 1011 0001 */ sprintf(buffer, "OUTS $%02X", (INT8) op & 0x0f); - break; + break; - case 0xb2: /* 1011 0010 */ + case 0xb2: /* 1011 0010 */ case 0xb3: /* 1011 0011 */ sprintf(buffer, "??? $%02X\n", op); - break; + break; - case 0xb4: /* 1011 0100 */ + case 0xb4: /* 1011 0100 */ case 0xb5: /* 1011 0101 */ case 0xb6: /* 1011 0110 */ case 0xb7: /* 1011 0111 */ @@ -416,9 +416,9 @@ CPU_DISASSEMBLE( f8 ) case 0xbe: /* 1011 1110 */ case 0xbf: /* 1011 1111 */ sprintf(buffer, "OUTS $%02X", (unsigned) (INT8) op & 0x0f); - break; + break; - case 0xc0: /* 1100 0000 */ + case 0xc0: /* 1100 0000 */ case 0xc1: /* 1100 0001 */ case 0xc2: /* 1100 0010 */ case 0xc3: /* 1100 0011 */ @@ -430,22 +430,22 @@ CPU_DISASSEMBLE( f8 ) case 0xc9: /* 1100 1001 */ case 0xca: /* 1100 1010 */ case 0xcb: /* 1100 1011 */ - sprintf(buffer, "AS %s", rname[op & 15]); - break; - case 0xcc: /* 1100 1100 */ + sprintf(buffer, "AS %s", rname[op & 15]); + break; + case 0xcc: /* 1100 1100 */ sprintf(buffer, "AS (IS)"); - break; - case 0xcd: /* 1100 1101 */ + break; + case 0xcd: /* 1100 1101 */ sprintf(buffer, "AS (IS++)"); - break; - case 0xce: /* 1100 1110 */ + break; + case 0xce: /* 1100 1110 */ sprintf(buffer, "AS (IS--)"); - break; - case 0xcf: /* 1100 1111 */ + break; + case 0xcf: /* 1100 1111 */ sprintf(buffer, "??? $%02X\n", op); break; - case 0xd0: /* 1101 0000 */ + case 0xd0: /* 1101 0000 */ case 0xd1: /* 1101 0001 */ case 0xd2: /* 1101 0010 */ case 0xd3: /* 1101 0011 */ @@ -459,20 +459,20 @@ CPU_DISASSEMBLE( f8 ) case 0xdb: /* 1101 1011 */ sprintf(buffer, "ASD %s", rname[op & 15]); break; - case 0xdc: /* 1101 1100 */ + case 0xdc: /* 1101 1100 */ sprintf(buffer, "ASD (IS)"); break; - case 0xdd: /* 1101 1101 */ + case 0xdd: /* 1101 1101 */ sprintf(buffer, "ASD (IS++)"); - break; - case 0xde: /* 1101 1110 */ + break; + case 0xde: /* 1101 1110 */ sprintf(buffer, "ASD (IS--)"); - break; - case 0xdf: /* 1101 1111 */ + break; + case 0xdf: /* 1101 1111 */ sprintf(buffer, "??? $%02X\n", op); - break; + break; - case 0xe0: /* 1110 0000 */ + case 0xe0: /* 1110 0000 */ case 0xe1: /* 1110 0001 */ case 0xe2: /* 1110 0010 */ case 0xe3: /* 1110 0011 */ @@ -485,22 +485,22 @@ CPU_DISASSEMBLE( f8 ) case 0xea: /* 1110 1010 */ case 0xeb: /* 1110 1011 */ sprintf(buffer, "XS %s", rname[op & 15]); - break; - case 0xec: /* 1110 1100 */ + break; + case 0xec: /* 1110 1100 */ sprintf(buffer, "XS (IS)"); - break; - case 0xed: /* 1110 1101 */ + break; + case 0xed: /* 1110 1101 */ sprintf(buffer, "XS (IS++)"); - break; - case 0xee: /* 1110 1110 */ + break; + case 0xee: /* 1110 1110 */ sprintf(buffer, "XS (IS--)"); - break; - case 0xef: /* 1110 1111 */ + break; + case 0xef: /* 1110 1111 */ sprintf(buffer, "??? $%02X\n", op); - break; + break; - case 0xf0: /* 1111 0000 */ + case 0xf0: /* 1111 0000 */ case 0xf1: /* 1111 0001 */ case 0xf2: /* 1111 0010 */ case 0xf3: /* 1111 0011 */ @@ -514,20 +514,19 @@ CPU_DISASSEMBLE( f8 ) case 0xfb: /* 1111 1011 */ sprintf(buffer, "NS %s", rname[op & 15]); break; - case 0xfc: /* 1111 1100 */ + case 0xfc: /* 1111 1100 */ sprintf(buffer, "NS (IS)"); - break; - case 0xfd: /* 1111 1101 */ + break; + case 0xfd: /* 1111 1101 */ sprintf(buffer, "NS (IS++)"); - break; - case 0xfe: /* 1111 1110 */ + break; + case 0xfe: /* 1111 1110 */ sprintf(buffer, "NS (IS--)"); - break; - case 0xff: /* 1111 1111 */ + break; + case 0xff: /* 1111 1111 */ sprintf(buffer, "??? $%02X\n", op); - break; - } + break; + } - return size; + return size; } - |