diff options
author | 2008-12-12 16:18:42 +0000 | |
---|---|---|
committer | 2008-12-12 16:18:42 +0000 | |
commit | e1f9347f0d1a4fb389f017ed90d0cb8a71b91beb (patch) | |
tree | 6c2a4937fac4150f955590d08cbb647a2d72be5d /src/emu/cpu/dsp56k | |
parent | fdce8d4d0c6a0fbd6fad2de92f5f9f3a4d5f8116 (diff) |
Pointer-ified the dsp56k cpu core. [Andrew Gardner]
(There are still a couple of global memory arrays that i've gotta' move into the cpu struct. Will do that soonish.)
Diffstat (limited to 'src/emu/cpu/dsp56k')
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56def.h | 420 | ||||
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56k.c | 409 | ||||
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56k.h | 206 | ||||
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56mem.c | 348 | ||||
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56ops.c | 1419 | ||||
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56pcu.c | 256 |
6 files changed, 1508 insertions, 1550 deletions
diff --git a/src/emu/cpu/dsp56k/dsp56def.h b/src/emu/cpu/dsp56k/dsp56def.h index 6ec50d6fc63..f3552449482 100644 --- a/src/emu/cpu/dsp56k/dsp56def.h +++ b/src/emu/cpu/dsp56k/dsp56def.h @@ -3,57 +3,65 @@ /////////////////////////////////////////// /*************************************************************************** + CURRENT CPU +***************************************************************************/ +//TODO: Just an idea. +//#define CCPU cpustate +//#define CCPUdef dsp56k_core* cpustate + + +/*************************************************************************** ALU ***************************************************************************/ -#define X core.ALU.x.d -#define X1 core.ALU.x.w.h -#define X0 core.ALU.x.w.l -#define Y core.ALU.y.d -#define Y1 core.ALU.y.w.h -#define Y0 core.ALU.y.w.l - -#define A core.ALU.a.q -#define A2 core.ALU.a.b.h4 -#define A1 core.ALU.a.w.h -#define A0 core.ALU.a.w.l -#define B core.ALU.b.q -#define B2 core.ALU.b.b.h4 -#define B1 core.ALU.b.w.h -#define B0 core.ALU.b.w.l +#define X cpustate->ALU.x.d +#define X1 cpustate->ALU.x.w.h +#define X0 cpustate->ALU.x.w.l +#define Y cpustate->ALU.y.d +#define Y1 cpustate->ALU.y.w.h +#define Y0 cpustate->ALU.y.w.l + +#define A cpustate->ALU.a.q +#define A2 cpustate->ALU.a.b.h4 +#define A1 cpustate->ALU.a.w.h +#define A0 cpustate->ALU.a.w.l +#define B cpustate->ALU.b.q +#define B2 cpustate->ALU.b.b.h4 +#define B1 cpustate->ALU.b.w.h +#define B0 cpustate->ALU.b.w.l /*************************************************************************** AGU ***************************************************************************/ -#define R0 core.AGU.r0 -#define R1 core.AGU.r1 -#define R2 core.AGU.r2 -#define R3 core.AGU.r3 +#define R0 cpustate->AGU.r0 +#define R1 cpustate->AGU.r1 +#define R2 cpustate->AGU.r2 +#define R3 cpustate->AGU.r3 -#define N0 core.AGU.n0 -#define N1 core.AGU.n1 -#define N2 core.AGU.n2 -#define N3 core.AGU.n3 +#define N0 cpustate->AGU.n0 +#define N1 cpustate->AGU.n1 +#define N2 cpustate->AGU.n2 +#define N3 cpustate->AGU.n3 -#define M0 core.AGU.m0 -#define M1 core.AGU.m1 -#define M2 core.AGU.m2 -#define M3 core.AGU.m3 +#define M0 cpustate->AGU.m0 +#define M1 cpustate->AGU.m1 +#define M2 cpustate->AGU.m2 +#define M3 cpustate->AGU.m3 -#define TEMP core.AGU.temp +#define TEMP cpustate->AGU.temp /*************************************************************************** PCU ***************************************************************************/ -static void pcu_reset(void); -#define PC (core.PCU.pc) -#define LA (core.PCU.la) -#define LC (core.PCU.lc) -#define SR (core.PCU.sr) -#define OMR (core.PCU.omr) -#define SP (core.PCU.sp) -#define SS (core.PCU.ss) +static void pcu_reset(dsp56k_core* cpustate); +#define PC (cpustate->PCU.pc) +#define LA (cpustate->PCU.la) +#define LC (cpustate->PCU.lc) +#define SR (cpustate->PCU.sr) +#define OMR (cpustate->PCU.omr) +#define SP (cpustate->PCU.sp) +#define SS (cpustate->PCU.ss) #define SSH (SS[SP].w.h) #define SSL (SS[SP].w.l) @@ -77,60 +85,60 @@ static void pcu_reset(void); /* 1-25 STATUS REGISTER (SR) BITS */ /* MR */ -static UINT8 LF_bit(void); -static UINT8 FV_bit(void); -//static UINT8 S_bits(void); #define s1BIT ((SR & 0x0800) != 0) #define s0BIT ((SR & 0x0400) != 0) -static UINT8 I_bits(void); +static UINT8 LF_bit(dsp56k_core* cpustate); +static UINT8 FV_bit(dsp56k_core* cpustate); +//static UINT8 S_bits(dsp56k_core* cpustate); #define s1BIT ((SR & 0x0800) != 0) #define s0BIT ((SR & 0x0400) != 0) +static UINT8 I_bits(dsp56k_core* cpustate); /* CCR */ -static UINT8 S_bit(void); -static UINT8 L_bit(void); -static UINT8 E_bit(void); -static UINT8 U_bit(void); -static UINT8 N_bit(void); -static UINT8 Z_bit(void); -static UINT8 V_bit(void); -static UINT8 C_bit(void); +static UINT8 S_bit(dsp56k_core* cpustate); +static UINT8 L_bit(dsp56k_core* cpustate); +static UINT8 E_bit(dsp56k_core* cpustate); +static UINT8 U_bit(dsp56k_core* cpustate); +static UINT8 N_bit(dsp56k_core* cpustate); +static UINT8 Z_bit(dsp56k_core* cpustate); +static UINT8 V_bit(dsp56k_core* cpustate); +static UINT8 C_bit(dsp56k_core* cpustate); /* MR */ -static void LF_bit_set(UINT8 value); -static void FV_bit_set(UINT8 value); -static void S_bits_set(UINT8 value); -static void I_bits_set(UINT8 value); +static void LF_bit_set(dsp56k_core* cpustate, UINT8 value); +static void FV_bit_set(dsp56k_core* cpustate, UINT8 value); +static void S_bits_set(dsp56k_core* cpustate, UINT8 value); +static void I_bits_set(dsp56k_core* cpustate, UINT8 value); /* CCR */ -static void S_bit_set(UINT8 value); -static void L_bit_set(UINT8 value); -static void E_bit_set(UINT8 value); -static void U_bit_set(UINT8 value); -static void N_bit_set(UINT8 value); -static void Z_bit_set(UINT8 value); -static void V_bit_set(UINT8 value); -static void C_bit_set(UINT8 value); +static void S_bit_set(dsp56k_core* cpustate, UINT8 value); +static void L_bit_set(dsp56k_core* cpustate, UINT8 value); +static void E_bit_set(dsp56k_core* cpustate, UINT8 value); +static void U_bit_set(dsp56k_core* cpustate, UINT8 value); +static void N_bit_set(dsp56k_core* cpustate, UINT8 value); +static void Z_bit_set(dsp56k_core* cpustate, UINT8 value); +static void V_bit_set(dsp56k_core* cpustate, UINT8 value); +static void C_bit_set(dsp56k_core* cpustate, UINT8 value); // TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here? /* 1-28 OPERATING MODE REGISTER (OMR) BITS */ -//static UINT8 CD_bit(void); #define cdBIT ((OMR & 0x0080) != 0) -//static UINT8 SD_bit(void); #define sdBIT ((OMR & 0x0040) != 0) -//static UINT8 R_bit(void); #define rBIT ((OMR & 0x0020) != 0) -//static UINT8 SA_bit(void); #define saBIT ((OMR & 0x0010) != 0) -//static UINT8 MC_bit(void); #define mcBIT ((OMR & 0x0004) != 0) -static UINT8 MB_bit(void); -static UINT8 MA_bit(void); - -static void CD_bit_set(UINT8 value); -static void SD_bit_set(UINT8 value); -static void R_bit_set(UINT8 value); -static void SA_bit_set(UINT8 value); -static void MC_bit_set(UINT8 value); -static void MB_bit_set(UINT8 value); -static void MA_bit_set(UINT8 value); +//static UINT8 CD_bit(dsp56k_core* cpustate); #define cdBIT ((OMR & 0x0080) != 0) +//static UINT8 SD_bit(dsp56k_core* cpustate); #define sdBIT ((OMR & 0x0040) != 0) +//static UINT8 R_bit(dsp56k_core* cpustate); #define rBIT ((OMR & 0x0020) != 0) +//static UINT8 SA_bit(dsp56k_core* cpustate); #define saBIT ((OMR & 0x0010) != 0) +//static UINT8 MC_bit(dsp56k_core* cpustate); #define mcBIT ((OMR & 0x0004) != 0) +static UINT8 MB_bit(dsp56k_core* cpustate); +static UINT8 MA_bit(dsp56k_core* cpustate); + +static void CD_bit_set(dsp56k_core* cpustate, UINT8 value); +static void SD_bit_set(dsp56k_core* cpustate, UINT8 value); +static void R_bit_set(dsp56k_core* cpustate, UINT8 value); +static void SA_bit_set(dsp56k_core* cpustate, UINT8 value); +static void MC_bit_set(dsp56k_core* cpustate, UINT8 value); +static void MB_bit_set(dsp56k_core* cpustate, UINT8 value); +static void MA_bit_set(dsp56k_core* cpustate, UINT8 value); /* 1-27 STACK POINTER (SP) BITS */ -static UINT8 UF_bit(void); -static UINT8 SE_bit(void); +static UINT8 UF_bit(dsp56k_core* cpustate); +static UINT8 SE_bit(dsp56k_core* cpustate); -//static void UF_bit_set(UINT8 value) {}; -//static void SE_bit_set(UINT8 value) {}; +//static void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {}; +//static void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {}; // HACK - Bootstrap modes @@ -141,18 +149,18 @@ static UINT8 SE_bit(void); /* PROTOTYPES */ /* PCU IRQ goodies */ -static void pcu_service_interrupts(void); +static void pcu_service_interrupts(dsp56k_core* cpustate); static void dsp56k_irq_table_init(void); static void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source); static int dsp56k_get_irq_index_by_tag(const char* tag); -static void dsp56k_add_pending_interrupt(const char* name); // Call me to add an interrupt to the queue +static void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name); // Call me to add an interrupt to the queue -static void dsp56k_clear_pending_interrupts(void); -static int dsp56k_count_pending_interrupts(void); -static void dsp56k_sort_pending_interrupts(int num); -static INT8 dsp56k_get_irq_priority(int index); +static void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate); +static int dsp56k_count_pending_interrupts(dsp56k_core* cpustate); +static void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num); +static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index); @@ -205,183 +213,183 @@ static INT8 dsp56k_get_irq_priority(int index); #define TSMB1 (dsp56k_peripheral_ram[A2O(0xfffd)]) /* Interrupt priority register (IPR) bits */ -static void IPR_set(UINT16 value); +static void IPR_set(dsp56k_core* cpustate, UINT16 value); /* A return value of -1 means disabled */ -static INT8 irqa_ipl(void); -static INT8 irqb_ipl(void); -static UINT8 irqa_trigger(void); -static UINT8 irqb_trigger(void); +static INT8 irqa_ipl(dsp56k_core* cpustate); +static INT8 irqb_ipl(dsp56k_core* cpustate); +static UINT8 irqa_trigger(dsp56k_core* cpustate); +static UINT8 irqb_trigger(dsp56k_core* cpustate); -static INT8 codec_ipl(void); -static INT8 host_ipl(void); -static INT8 ssi0_ipl(void); -static INT8 ssi1_ipl(void); -static INT8 tm_ipl(void); +static INT8 codec_ipl(dsp56k_core* cpustate); +static INT8 host_ipl(dsp56k_core* cpustate); +static INT8 ssi0_ipl(dsp56k_core* cpustate); +static INT8 ssi1_ipl(dsp56k_core* cpustate); +static INT8 tm_ipl(dsp56k_core* cpustate); /*************************************************************************** HOST INTERFACE ***************************************************************************/ -static void dsp56k_host_interface_reset(void); +static void dsp56k_host_interface_reset(dsp56k_core* cpustate); #define HTX (HTXHRX) #define HRX (HTXHRX) -#define ICR (core.HI.icr) -#define CVR (core.HI.cvr) -#define ISR (core.HI.isr) -#define IVR (core.HI.ivr) -#define TXH (core.HI.trxh) -#define TXL (core.HI.trxl) -#define RXH (core.HI.trxh) -#define RXL (core.HI.trxl) +#define ICR (cpustate->HI.icr) +#define CVR (cpustate->HI.cvr) +#define ISR (cpustate->HI.isr) +#define IVR (cpustate->HI.ivr) +#define TXH (cpustate->HI.trxh) +#define TXL (cpustate->HI.trxl) +#define RXH (cpustate->HI.trxh) +#define RXL (cpustate->HI.trxl) /***************/ /* DSP56k SIDE */ /***************/ /* Host Control Register (HCR) Bits */ -static void HCR_set(UINT16 value); +static void HCR_set(dsp56k_core* cpustate, UINT16 value); -//static UINT16 HF3_bit(void); #define hf3BIT ((HCR & 0x0010) != 0) -//static UINT16 HF2_bit(void); #define hf2BIT ((HCR & 0x0008) != 0) -static UINT16 HCIE_bit(void); -static UINT16 HTIE_bit(void); -static UINT16 HRIE_bit(void); +//static UINT16 HF3_bit(dsp56k_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0) +//static UINT16 HF2_bit(dsp56k_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0) +static UINT16 HCIE_bit(dsp56k_core* cpustate); +static UINT16 HTIE_bit(dsp56k_core* cpustate); +static UINT16 HRIE_bit(dsp56k_core* cpustate); -static void HF3_bit_set(UINT16 value); -static void HF2_bit_set(UINT16 value); -static void HCIE_bit_set(UINT16 value); -static void HTIE_bit_set(UINT16 value); -static void HRIE_bit_set(UINT16 value); +static void HF3_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HF2_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value); /* Host Status Register (HSR) Bits */ -//static void HSR_set(UINT16 value); - -//static UINT16 DMA_bit(void); #define dmaBIT ((HSR & 0x0080) != 0) -//static UINT16 HF1_bit(void); #define hf1BIT ((HSR & 0x0010) != 0) -//static UINT16 HF0_bit(void); #define hf0BIT ((HSR & 0x0008) != 0) -//static UINT16 HCP_bit(void); #define hcpBIT ((HSR & 0x0004) != 0) -static UINT16 HTDE_bit(void); -static UINT16 HRDF_bit(void); - -static void DMA_bit_set(UINT16 value); -static void HF1_bit_set(UINT16 value); -static void HF0_bit_set(UINT16 value); -static void HCP_bit_set(UINT16 value); -static void HTDE_bit_set(UINT16 value); -static void HRDF_bit_set(UINT16 value); +//static void HSR_set(dsp56k_core* cpustate, UINT16 value); + +//static UINT16 DMA_bit(dsp56k_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0) +//static UINT16 HF1_bit(dsp56k_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0) +//static UINT16 HF0_bit(dsp56k_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0) +//static UINT16 HCP_bit(dsp56k_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0) +static UINT16 HTDE_bit(dsp56k_core* cpustate); +static UINT16 HRDF_bit(dsp56k_core* cpustate); + +static void DMA_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HF1_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HF0_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HCP_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value); +static void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value); /*************/ /* HOST SIDE */ /*************/ /* Interrupt Control Register (ICR) Bits */ -static void ICR_set(UINT8 value); - -//static UINT8 INIT_bit(void); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0) -//static UINT8 HM1_bit(void); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0) -//static UINT8 HM0_bit(void); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0) -//static UINT8 HF1_bit_host(void); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0) -//static UINT8 HF0_bit_host(void); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0) -//static UINT8 TREQ_bit(void); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0) -//static UINT8 RREQ_bit(void); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0) - -//static void INIT_bit_set(UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080)) -//static void HM1_bit_set(UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040)) -//static void HM0_bit_set(UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020)) -static void HF1_bit_host_set(UINT8 value); -static void HF0_bit_host_set(UINT8 value); -static void TREQ_bit_set(UINT8 value); -static void RREQ_bit_set(UINT8 value); +static void ICR_set(dsp56k_core* cpustate, UINT8 value); + +//static UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0) +//static UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0) +//static UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0) +//static UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0) +//static UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0) +//static UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0) +//static UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0) + +//static void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080)) +//static void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040)) +//static void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020)) +static void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value); +static void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value); +static void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value); +static void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value); /* Command Vector Register (CVR) Bits */ -static void CVR_set(UINT8 value); +static void CVR_set(dsp56k_core* cpustate, UINT8 value); //static UINT8 HC_bit(); -static UINT8 HV_bits(void); +static UINT8 HV_bits(dsp56k_core* cpustate); -static void HC_bit_set(UINT8 value); -static void HV_bits_set(UINT8 value); +static void HC_bit_set(dsp56k_core* cpustate, UINT8 value); +static void HV_bits_set(dsp56k_core* cpustate, UINT8 value); /* Interrupt Status Register (ISR) Bits */ -// static void ISR_set(UINT8 value); - -//static UINT8 HREQ_bit(void); #define x_hreqBIT ((dsp56k.HI.ISR & 0x0080) != 0) -//static UINT8 DMA_bit(void); #define x_dmaBIT ((dsp56k.HI.ISR & 0x0040) != 0) -//static UINT8 HF3_bit_host(void); #define x_hf3BIT ((dsp56k.HI.ISR & 0x0010) != 0) -//static UINT8 HF2_bit_host(void); #define x_hf2BIT ((dsp56k.HI.ISR & 0x0008) != 0) -//static UINT8 TRDY_bit(void); #define x_trdyBIT ((dsp56k.HI.ISR & 0x0004) != 0) -static UINT8 TXDE_bit(void); -static UINT8 RXDF_bit(void); - -//static void HREQ_bit_set(UINT8 value); #define CLEAR_x_hreqBIT() (dsp56k.HI.ISR &= (~0x0080)) -//static void DMA_bit_set(UINT8 value); #define CLEAR_x_dmaBIT() (dsp56k.HI.ISR &= (~0x0040)) -static void HF3_bit_host_set(UINT8 value); -static void HF2_bit_host_set(UINT8 value); -//static void TRDY_bit_set(UINT8 value); #define CLEAR_x_trdyBIT() (dsp56k.HI.ISR &= (~0x0004)) -static void TXDE_bit_set(UINT8 value); -static void RXDF_bit_set(UINT8 value); +// static void ISR_set(dsp56k_core* cpustate, UINT8 value); + +//static UINT8 HREQ_bit(dsp56k_core* cpustate); #define x_hreqBIT ((dsp56k.HI.ISR & 0x0080) != 0) +//static UINT8 DMA_bit(dsp56k_core* cpustate); #define x_dmaBIT ((dsp56k.HI.ISR & 0x0040) != 0) +//static UINT8 HF3_bit_host(dsp56k_core* cpustate); #define x_hf3BIT ((dsp56k.HI.ISR & 0x0010) != 0) +//static UINT8 HF2_bit_host(dsp56k_core* cpustate); #define x_hf2BIT ((dsp56k.HI.ISR & 0x0008) != 0) +//static UINT8 TRDY_bit(dsp56k_core* cpustate); #define x_trdyBIT ((dsp56k.HI.ISR & 0x0004) != 0) +static UINT8 TXDE_bit(dsp56k_core* cpustate); +static UINT8 RXDF_bit(dsp56k_core* cpustate); + +//static void HREQ_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hreqBIT() (dsp56k.HI.ISR &= (~0x0080)) +//static void DMA_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_dmaBIT() (dsp56k.HI.ISR &= (~0x0040)) +static void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value); +static void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value); +//static void TRDY_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_trdyBIT() (dsp56k.HI.ISR &= (~0x0004)) +static void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value); +static void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value); /* Interrupt Vector Register (IVR) Bits */ -//static void IVR_set(UINT8 value); - -//static UINT8 IV7_bit(void); -//static UINT8 IV6_bit(void); -//static UINT8 IV5_bit(void); -//static UINT8 IV4_bit(void); -//static UINT8 IV3_bit(void); -//static UINT8 IV2_bit(void); -//static UINT8 IV1_bit(void); -//static UINT8 IV0_bit(void); - -//static void IV7_bit_set(UINT8 value); -//static void IV6_bit_set(UINT8 value); -//static void IV5_bit_set(UINT8 value); -//static void IV4_bit_set(UINT8 value); -//static void IV3_bit_set(UINT8 value); -//static void IV2_bit_set(UINT8 value); -//static void IV1_bit_set(UINT8 value); -//static void IV0_bit_set(UINT8 value); +//static void IVR_set(dsp56k_core* cpustate, UINT8 value); + +//static UINT8 IV7_bit(dsp56k_core* cpustate); +//static UINT8 IV6_bit(dsp56k_core* cpustate); +//static UINT8 IV5_bit(dsp56k_core* cpustate); +//static UINT8 IV4_bit(dsp56k_core* cpustate); +//static UINT8 IV3_bit(dsp56k_core* cpustate); +//static UINT8 IV2_bit(dsp56k_core* cpustate); +//static UINT8 IV1_bit(dsp56k_core* cpustate); +//static UINT8 IV0_bit(dsp56k_core* cpustate); + +//static void IV7_bit_set(dsp56k_core* cpustate, UINT8 value); +//static void IV6_bit_set(dsp56k_core* cpustate, UINT8 value); +//static void IV5_bit_set(dsp56k_core* cpustate, UINT8 value); +//static void IV4_bit_set(dsp56k_core* cpustate, UINT8 value); +//static void IV3_bit_set(dsp56k_core* cpustate, UINT8 value); +//static void IV2_bit_set(dsp56k_core* cpustate, UINT8 value); +//static void IV1_bit_set(dsp56k_core* cpustate, UINT8 value); +//static void IV0_bit_set(dsp56k_core* cpustate, UINT8 value); /* PROTOTYPES */ -static void dsp56k_host_interface_HTX_to_host(void); -static void dsp56k_host_interface_host_to_HTX(void); +static void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate); +static void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate); /*************************************************************************** I/O INTERFACE ***************************************************************************/ -static void dsp56k_io_reset(void); +static void dsp56k_io_reset(dsp56k_core* cpustate); /* Port A Bus Control Register (BCR) */ -static void BCR_set(UINT16 value); +static void BCR_set(dsp56k_core* cpustate, UINT16 value); -//static UINT16 RH_bit(void); -//static UINT16 BS_bit(void); -//static UINT16 external_x_wait_states(void); -//static UINT16 external_p_wait_states(void); +//static UINT16 RH_bit(dsp56k_core* cpustate); +//static UINT16 BS_bit(dsp56k_core* cpustate); +//static UINT16 external_x_wait_states(dsp56k_core* cpustate); +//static UINT16 external_p_wait_states(dsp56k_core* cpustate); -static void RH_bit_set(UINT16 value); -static void BS_bit_set(UINT16 value); -static void external_x_wait_states_set(UINT16 value); -static void external_p_wait_states_set(UINT16 value); +static void RH_bit_set(dsp56k_core* cpustate, UINT16 value); +static void BS_bit_set(dsp56k_core* cpustate, UINT16 value); +static void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value); +static void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value); /* Port B Control Register (PBC) */ -static void PBC_set(UINT16 value); -//static int host_interface_active(void); +static void PBC_set(dsp56k_core* cpustate, UINT16 value); +//static int host_interface_active(dsp56k_core* cpustate); /* Port B Data Direction Register (PBDDR) */ -static void PBDDR_set(UINT16 value); +static void PBDDR_set(dsp56k_core* cpustate, UINT16 value); /* Port B Data Register (PBD) */ -static void PBD_set(UINT16 value); +static void PBD_set(dsp56k_core* cpustate, UINT16 value); /* Port C Control Register (PCC) */ -static void PCC_set(UINT16 value); +static void PCC_set(dsp56k_core* cpustate, UINT16 value); /* Port C Data Direction Register (PCDDR) */ -static void PCDDR_set(UINT16 value); +static void PCDDR_set(dsp56k_core* cpustate, UINT16 value); /* Port C Dtaa Register (PCD) */ -static void PCD_set(UINT16 value); +static void PCD_set(dsp56k_core* cpustate, UINT16 value); diff --git a/src/emu/cpu/dsp56k/dsp56k.c b/src/emu/cpu/dsp56k/dsp56k.c index 01fb0efe43a..07338afdf78 100644 --- a/src/emu/cpu/dsp56k/dsp56k.c +++ b/src/emu/cpu/dsp56k/dsp56k.c @@ -35,183 +35,9 @@ #include "dsp56def.h" /*************************************************************************** - LOCAL DECLARATIONS + FUNCTION PROTOTYPES ***************************************************************************/ -static CPU_INIT( dsp56k ); static CPU_RESET( dsp56k ); -static CPU_EXIT( dsp56k ); - -/*************************************************************************** - MACROS -***************************************************************************/ - -/*************************************************************************** - STRUCTURES & TYPEDEFS -***************************************************************************/ -// 5-4 Host Interface -typedef struct -{ - // **** Dsp56k side **** // - // Host Control Register - UINT16* hcr; - - // Host Status Register - UINT16* hsr; - - // Host Transmit/Receive Data - UINT16* htrx; - - // **** Host CPU side **** // - // Interrupt Control Register - UINT8 icr; - - // Command Vector Register - UINT8 cvr; - - // Interrupt Status Register - UINT8 isr; - - // Interrupt Vector Register - UINT8 ivr; - - // Transmit / Receive Registers - UINT8 trxh; - UINT8 trxl; - - // HACK - Host interface bootstrap write offset - UINT16 bootstrap_offset; - -} dsp56k_host_interface; - -// 1-9 ALU -typedef struct -{ - // Four 16-bit input registers (can be accessed as 2 32-bit registers) - PAIR x; - PAIR y; - - // Two 32-bit accumulator registers + 8-bit accumulator extension registers - PAIR64 a; - PAIR64 b; - - // An accumulation shifter - // One data bus shifter/limiter - // A parallel, single cycle, non-pipelined Multiply-Accumulator (MAC) unit - // Basics -} dsp56k_data_alu; - -// 1-10 Address Generation Unit (AGU) -typedef struct -{ - // Four address registers - UINT16 r0; - UINT16 r1; - UINT16 r2; - UINT16 r3; - - // Four offset registers - UINT16 n0; - UINT16 n1; - UINT16 n2; - UINT16 n3; - - // Four modifier registers - UINT16 m0; - UINT16 m1; - UINT16 m2; - UINT16 m3; - - // Used in loop processing - UINT16 temp; - - // FM.4-5 - hmmm? - // UINT8 status; - - // Basics -} dsp56k_agu; - -// 1-11 Program Control Unit (PCU) -typedef struct -{ - // Program Counter - UINT16 pc; - - // Loop Address - UINT16 la; - - // Loop Counter - UINT16 lc; - - // Status Register - UINT16 sr; - - // Operating Mode Register - UINT16 omr; - - // Stack Pointer - UINT16 sp; - - // Stack (TODO: 15-level?) - PAIR ss[16]; - - // Controls IRQ processing - void (*service_interrupts)(void); - - // A list of pending interrupts (indices into dsp56k_interrupt_sources array) - INT8 pending_interrupts[32]; - - // Basics - - // Other PCU internals - UINT16 reset_vector; - -} dsp56k_pcu; - -// 1-8 The dsp56156 CORE -typedef struct -{ - // PROGRAM CONTROLLER - dsp56k_pcu PCU; - - // ADR ALU (AGU) - dsp56k_agu AGU; - - // CLOCK GEN - //static emu_timer *dsp56k_timer; // 1-5, 1-8 - Clock gen - - // DATA ALU - dsp56k_data_alu ALU; - - // OnCE - - // IBS and BITFIELD UNIT - - // Host Interface - dsp56k_host_interface HI; - - // IRQ line states - UINT8 modA_state; - UINT8 modB_state; - UINT8 modC_state; - UINT8 reset_state; - - // HACK - Bootstrap mode state variable. - UINT8 bootstrap_mode; - - UINT8 repFlag; // Knowing if we're in a 'repeat' state (dunno how the processor does this) - UINT32 repAddr; // The address of the instruction to repeat... - - - /* MAME internal stuff */ - UINT32 ppc; - UINT32 op; - int interrupt_cycles; - void (*output_pins_changed)(UINT32 pins); - const device_config *device; - const address_space *program; - const address_space *data; -} dsp56k_core; - /*************************************************************************** ONBOARD MEMORY ALLOCATION @@ -220,16 +46,6 @@ static UINT16 *dsp56k_peripheral_ram; static UINT16 *dsp56k_program_ram; /*************************************************************************** - FUNCTION PROTOTYPES -***************************************************************************/ - -/*************************************************************************** - PRIVATE GLOBAL VARIABLES -***************************************************************************/ -static dsp56k_core core; -static int dsp56k_icount; - -/*************************************************************************** COMPONENT FUNCTIONALITY ***************************************************************************/ // 1-9 ALU @@ -250,37 +66,13 @@ static int dsp56k_icount; /*************************************************************************** MEMORY ACCESSORS ***************************************************************************/ -#define ROPCODE(pc) memory_decrypted_read_word(core.program, pc) - - -/*************************************************************************** - EXECEPTION HANDLING -***************************************************************************/ - -#ifdef UNUSED_FUNCTION -INLINE void generate_exception(int exception) -{ -} -#endif - -#ifdef UNUSED_FUNCTION -INLINE void invalid_instruction(UINT32 op) -{ -} -#endif +#define ROPCODE(pc) memory_decrypted_read_word(cpustate->program, pc) /*************************************************************************** IRQ HANDLING ***************************************************************************/ -#ifdef UNUSED_FUNCTION -static void check_irqs(void) -{ - //logerror("Dsp56k check irqs\n"); -} -#endif - -static void set_irq_line(int irqline, int state) +static void set_irq_line(dsp56k_core* cpustate, int irqline, int state) { logerror("DSP56k set irq line %d %d\n", irqline, state); @@ -288,51 +80,51 @@ static void set_irq_line(int irqline, int state) { case DSP56K_IRQ_MODA: // TODO: 1-12 Get this triggering right - if (irqa_trigger()) + if (irqa_trigger(cpustate)) logerror("DSP56k IRQA is set to fire on the \"Negative Edge\".\n"); if (state != CLEAR_LINE) - core.modA_state = TRUE; + cpustate->modA_state = TRUE; else - core.modA_state = FALSE; + cpustate->modA_state = FALSE; - if (core.reset_state != TRUE) - dsp56k_add_pending_interrupt("IRQA"); + if (cpustate->reset_state != TRUE) + dsp56k_add_pending_interrupt(cpustate, "IRQA"); break; case DSP56K_IRQ_MODB: // TODO: 1-12 Get this triggering right - if (irqb_trigger()) + if (irqb_trigger(cpustate)) logerror("DSP56k IRQB is set to fire on the \"Negative Edge\".\n"); if (state != CLEAR_LINE) - core.modB_state = TRUE; + cpustate->modB_state = TRUE; else - core.modB_state = FALSE; + cpustate->modB_state = FALSE; - if (core.reset_state != TRUE) - dsp56k_add_pending_interrupt("IRQB"); + if (cpustate->reset_state != TRUE) + dsp56k_add_pending_interrupt(cpustate, "IRQB"); break; case DSP56K_IRQ_MODC: if (state != CLEAR_LINE) - core.modC_state = TRUE; + cpustate->modC_state = TRUE; else - core.modC_state = FALSE; + cpustate->modC_state = FALSE; // TODO : Set bus mode or whatever break; case DSP56K_IRQ_RESET: if (state != CLEAR_LINE) - core.reset_state = TRUE; + cpustate->reset_state = TRUE; else { /* If it changes state from asserted to cleared. Call the reset function. */ - if (core.reset_state == TRUE) - cpu_reset_dsp56k(core.device); + if (cpustate->reset_state == TRUE) + cpu_reset_dsp56k(cpustate->device); - core.reset_state = FALSE; + cpustate->reset_state = FALSE; } // dsp56k_add_pending_interrupt("Hardware RESET"); @@ -345,63 +137,44 @@ static void set_irq_line(int irqline, int state) // If the reset line isn't asserted, service interrupts // TODO: Is it right to immediately service interrupts? - //if (core.reset_state != TRUE) + //if (cpustate->reset_state != TRUE) // pcu_service_interrupts(); } /*************************************************************************** - CONTEXT SWITCHING -***************************************************************************/ -/* -static CPU_GET_CONTEXT( dsp56k ) -{ - if (dst) - *(dsp56k_core *)dst = core; -} - - -static CPU_SET_CONTEXT( dsp56k ) -{ - if (src) - core = *(dsp56k_core *)src; - - check_irqs(); -} -*/ - - -/*************************************************************************** INITIALIZATION AND SHUTDOWN ***************************************************************************/ static CPU_INIT( dsp56k ) { + dsp56k_core* cpustate = device->token; + // Call specific module inits - pcu_init(index); - // agu_init(index); - // alu_init(index); + pcu_init(cpustate, index); + // agu_init(cpustate, index); + // alu_init(cpustate, index); // HACK - You're not in bootstrap mode upon bootup - core.bootstrap_mode = BOOTSTRAP_OFF; + cpustate->bootstrap_mode = BOOTSTRAP_OFF; // Clear the irq states - core.modA_state = FALSE; - core.modB_state = FALSE; - core.modC_state = FALSE; - core.reset_state = FALSE; + cpustate->modA_state = FALSE; + cpustate->modB_state = FALSE; + cpustate->modC_state = FALSE; + cpustate->reset_state = FALSE; /* Save the core's state */ // state_save_register_device_item(device, 0, modA_state); // ... - //core.config = device->static_config; - //core.irq_callback = irqcallback; - core.device = device; - core.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); - core.data = memory_find_address_space(device, ADDRESS_SPACE_DATA); + //cpustate->config = device->static_config; + //cpustate->irq_callback = irqcallback; + cpustate->device = device; + cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + cpustate->data = memory_find_address_space(device, ADDRESS_SPACE_DATA); } -static void agu_reset(void) +static void agu_reset(dsp56k_core* cpustate) { // FM.4-3 R0 = 0x0000; @@ -422,7 +195,7 @@ static void agu_reset(void) TEMP = 0x0000; } -static void alu_reset(void) +static void alu_reset(dsp56k_core* cpustate) { X = 0x00000000; Y = 0x00000000; @@ -430,24 +203,24 @@ static void alu_reset(void) B = 0x0000000000; } - static CPU_RESET( dsp56k ) { + dsp56k_core* cpustate = device->token; logerror("Dsp56k reset\n"); - core.interrupt_cycles = 0; - core.ppc = 0x0000; + cpustate->interrupt_cycles = 0; + cpustate->ppc = 0x0000; - core.repFlag = 0; - core.repAddr = 0x0000; + cpustate->repFlag = 0; + cpustate->repAddr = 0x0000; - pcu_reset(); - mem_reset(); - agu_reset(); - alu_reset(); + pcu_reset(cpustate); + mem_reset(cpustate); + agu_reset(cpustate); + alu_reset(cpustate); /* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU put in MAME */ - memory_write_word_16le(core.program, 0x0000, 0x0124); + memory_write_word_16le(cpustate->program, 0x0000, 0x0124); } @@ -460,38 +233,40 @@ static CPU_EXIT( dsp56k ) /*************************************************************************** CORE INCLUDE ***************************************************************************/ - -#define OP (core.op) +#define OP (cpustate->op) #include "dsp56ops.c" + /*************************************************************************** CORE EXECUTION LOOP ***************************************************************************/ static CPU_EXECUTE( dsp56k ) { + dsp56k_core* cpustate = device->token; + /* If reset line is asserted, do nothing */ - if (core.reset_state) + if (cpustate->reset_state) return cycles; // HACK - if you're in bootstrap mode, simply pretend you ate up all your cycles waiting for data. - if (core.bootstrap_mode != BOOTSTRAP_OFF) + if (cpustate->bootstrap_mode != BOOTSTRAP_OFF) return cycles; - dsp56k_icount = cycles; - dsp56k_icount -= core.interrupt_cycles; - core.interrupt_cycles = 0; + cpustate->icount = cycles; + cpustate->icount -= cpustate->interrupt_cycles; + cpustate->interrupt_cycles = 0; - while(dsp56k_icount > 0) + while(cpustate->icount > 0) { - execute_one(); - pcu_service_interrupts(); /* TODO: There is definitely something un-right about this */ + execute_one(cpustate); + pcu_service_interrupts(cpustate); /* TODO: There is definitely something un-right about this */ } - dsp56k_icount -= core.interrupt_cycles; - core.interrupt_cycles = 0; + cpustate->icount -= cpustate->interrupt_cycles; + cpustate->interrupt_cycles = 0; - return cycles - dsp56k_icount; + return cycles - cpustate->icount; } @@ -522,12 +297,14 @@ ADDRESS_MAP_END static CPU_SET_INFO( dsp56k ) { + dsp56k_core* cpustate = device->token; + switch (state) { - case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODA: set_irq_line(DSP56K_IRQ_MODA, info->i); break; - case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODB: set_irq_line(DSP56K_IRQ_MODB, info->i); break; - case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODC: set_irq_line(DSP56K_IRQ_MODC, info->i); break; - case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_RESET: set_irq_line(DSP56K_IRQ_RESET, info->i); break; + case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODA: set_irq_line(cpustate, DSP56K_IRQ_MODA, info->i); break; + case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODB: set_irq_line(cpustate, DSP56K_IRQ_MODB, info->i); break; + case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODC: set_irq_line(cpustate, DSP56K_IRQ_MODC, info->i); break; + case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_RESET: set_irq_line(cpustate, DSP56K_IRQ_RESET, info->i); break; case CPUINFO_INT_PC: case CPUINFO_INT_REGISTER + DSP56K_PC: PC = info->i & 0xffff; break; @@ -588,13 +365,15 @@ static CPU_SET_INFO( dsp56k ) CPU_GET_INFO( dsp56k ) { + dsp56k_core* cpustate = (device != NULL) ? device->token : NULL; + switch (state) { // --- the following bits of info are returned as 64-bit signed integers --- - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(core); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(dsp56k_core); break; case CPUINFO_INT_INPUT_LINES: info->i = 4; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0x0000; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; case CPUINFO_INT_CLOCK_DIVIDER: info->i = 2; break; case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; @@ -618,7 +397,7 @@ CPU_GET_INFO( dsp56k ) case CPUINFO_INT_PC: case CPUINFO_INT_REGISTER + DSP56K_PC: info->i = PC; break; - case CPUINFO_INT_PREVIOUSPC: info->i = core.ppc; break; + case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc; break; case CPUINFO_INT_REGISTER + DSP56K_SR: info->i = SR; break; case CPUINFO_INT_REGISTER + DSP56K_LC: info->i = LC; break; @@ -672,23 +451,23 @@ CPU_GET_INFO( dsp56k ) case CPUINFO_INT_REGISTER + DSP56K_ST15: info->i = ST15; break; // --- the following bits of info are returned as pointers to data or functions --- - case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(dsp56k); break; - case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(dsp56k); break; + case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(dsp56k); break; + case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(dsp56k); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(dsp56k); break; - case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(dsp56k); break; + case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(dsp56k); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(dsp56k); break; - case CPUINFO_PTR_BURN: info->burn = NULL; break; - case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(dsp56k); break; + case CPUINFO_PTR_BURN: info->burn = NULL; break; + case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(dsp56k); break; case CPUINFO_PTR_DEBUG_INIT: info->debug_init = NULL; break; case CPUINFO_PTR_TRANSLATE: info->translate = NULL; break; case CPUINFO_PTR_READ: info->read = NULL; break; case CPUINFO_PTR_WRITE: info->write = NULL; break; case CPUINFO_PTR_READOP: info->readop = NULL; break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &dsp56k_icount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: - info->internal_map16 = ADDRESS_MAP_NAME(dsp56156_x_data_map); break; + info->internal_map16 = ADDRESS_MAP_NAME(dsp56156_x_data_map); break; case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: - info->internal_map16 = ADDRESS_MAP_NAME(dsp56156_program_map); break; + info->internal_map16 = ADDRESS_MAP_NAME(dsp56156_program_map); break; // --- the following bits of info are returned as NULL-terminated strings --- case CPUINFO_STR_NAME: strcpy(info->s, "DSP56156"); break; @@ -700,21 +479,21 @@ CPU_GET_INFO( dsp56k ) case CPUINFO_STR_FLAGS: sprintf(info->s, "%s%s %s%s%s%s%s%s%s%s %s%s", /* Status Register */ - LF_bit() ? "L" : ".", - FV_bit() ? "F" : ".", - - S_bit() ? "S" : ".", - L_bit() ? "L" : ".", - E_bit() ? "E" : ".", - U_bit() ? "U" : ".", - N_bit() ? "N" : ".", - Z_bit() ? "Z" : ".", - V_bit() ? "V" : ".", - C_bit() ? "C" : ".", + LF_bit(cpustate) ? "L" : ".", + FV_bit(cpustate) ? "F" : ".", + + S_bit(cpustate) ? "S" : ".", + L_bit(cpustate) ? "L" : ".", + E_bit(cpustate) ? "E" : ".", + U_bit(cpustate) ? "U" : ".", + N_bit(cpustate) ? "N" : ".", + Z_bit(cpustate) ? "Z" : ".", + V_bit(cpustate) ? "V" : ".", + C_bit(cpustate) ? "C" : ".", /* Stack Pointer */ - UF_bit() ? "U" : ".", - SE_bit() ? "S" : "."); + UF_bit(cpustate) ? "U" : ".", + SE_bit(cpustate) ? "S" : "."); break; case CPUINFO_STR_REGISTER + DSP56K_PC: sprintf(info->s, "PC : %04x", PC); break; diff --git a/src/emu/cpu/dsp56k/dsp56k.h b/src/emu/cpu/dsp56k/dsp56k.h index 86e5d1b4826..c2cb859cb1b 100644 --- a/src/emu/cpu/dsp56k/dsp56k.h +++ b/src/emu/cpu/dsp56k/dsp56k.h @@ -17,14 +17,6 @@ /*************************************************************************** REGISTER ENUMERATION ***************************************************************************/ - -// IRQ Lines -// MODA and MODB are also known as IRQA and IRQB -#define DSP56K_IRQ_MODA 0 -#define DSP56K_IRQ_MODB 1 -#define DSP56K_IRQ_MODC 2 -#define DSP56K_IRQ_RESET 3 /* Is this needed? */ - enum { // PCU @@ -65,22 +57,194 @@ enum DSP56K_ST15 }; -// For Debugger and opcodes -enum _parallel_move_type -{ - PARALLEL_TYPE_XMDM, - PARALLEL_TYPE_XMDM_SPECIAL, - PARALLEL_TYPE_NODM, - PARALLEL_TYPE_ARU, - PARALLEL_TYPE_RRDM -}; -typedef enum _parallelMoveType parallelMoveType; +// IRQ Lines +// MODA and MODB are also known as IRQA and IRQB +#define DSP56K_IRQ_MODA 0 +#define DSP56K_IRQ_MODB 1 +#define DSP56K_IRQ_MODC 2 +#define DSP56K_IRQ_RESET 3 /* Is this needed? */ +// Needed for MAME extern CPU_GET_INFO( dsp56k ); -void dsp56k_host_interface_write(UINT8 offset, UINT8 data); -UINT8 dsp56k_host_interface_read(UINT8 offset); -UINT16 dsp56k_get_peripheral_memory(UINT16 addr); +/*************************************************************************** + STRUCTURES & TYPEDEFS +***************************************************************************/ +// 5-4 Host Interface +typedef struct +{ + // **** Dsp56k side **** // + // Host Control Register + UINT16* hcr; + + // Host Status Register + UINT16* hsr; + + // Host Transmit/Receive Data + UINT16* htrx; + + // **** Host CPU side **** // + // Interrupt Control Register + UINT8 icr; + + // Command Vector Register + UINT8 cvr; + + // Interrupt Status Register + UINT8 isr; + + // Interrupt Vector Register + UINT8 ivr; + + // Transmit / Receive Registers + UINT8 trxh; + UINT8 trxl; + + // HACK - Host interface bootstrap write offset + UINT16 bootstrap_offset; + +} dsp56k_host_interface; + +// 1-9 ALU +typedef struct +{ + // Four 16-bit input registers (can be accessed as 2 32-bit registers) + PAIR x; + PAIR y; + + // Two 32-bit accumulator registers + 8-bit accumulator extension registers + PAIR64 a; + PAIR64 b; + + // An accumulation shifter + // One data bus shifter/limiter + // A parallel, single cycle, non-pipelined Multiply-Accumulator (MAC) unit + // Basics +} dsp56k_data_alu; + +// 1-10 Address Generation Unit (AGU) +typedef struct +{ + // Four address registers + UINT16 r0; + UINT16 r1; + UINT16 r2; + UINT16 r3; + + // Four offset registers + UINT16 n0; + UINT16 n1; + UINT16 n2; + UINT16 n3; + + // Four modifier registers + UINT16 m0; + UINT16 m1; + UINT16 m2; + UINT16 m3; + + // Used in loop processing + UINT16 temp; + + // FM.4-5 - hmmm? + // UINT8 status; + + // Basics +} dsp56k_agu; + +// 1-11 Program Control Unit (PCU) +typedef struct +{ + // Program Counter + UINT16 pc; + + // Loop Address + UINT16 la; + + // Loop Counter + UINT16 lc; + + // Status Register + UINT16 sr; + + // Operating Mode Register + UINT16 omr; + + // Stack Pointer + UINT16 sp; + + // Stack (TODO: 15-level?) + PAIR ss[16]; + + // Controls IRQ processing + void (*service_interrupts)(void); + + // A list of pending interrupts (indices into dsp56k_interrupt_sources array) + INT8 pending_interrupts[32]; + + // Basics + + // Other PCU internals + UINT16 reset_vector; + +} dsp56k_pcu; + +// 1-8 The dsp56156 CORE +typedef struct +{ + // PROGRAM CONTROLLER + dsp56k_pcu PCU; + + // ADR ALU (AGU) + dsp56k_agu AGU; + + // CLOCK GEN + //static emu_timer *dsp56k_timer; // 1-5, 1-8 - Clock gen + + // DATA ALU + dsp56k_data_alu ALU; + + // OnCE + + // IBS and BITFIELD UNIT + + // Host Interface + dsp56k_host_interface HI; + + // IRQ line states + UINT8 modA_state; + UINT8 modB_state; + UINT8 modC_state; + UINT8 reset_state; + + // HACK - Bootstrap mode state variable. + UINT8 bootstrap_mode; + + UINT8 repFlag; // Knowing if we're in a 'repeat' state (dunno how the processor does this) + UINT32 repAddr; // The address of the instruction to repeat... + + + /* MAME internal stuff */ + int icount; + + UINT32 ppc; + UINT32 op; + int interrupt_cycles; + void (*output_pins_changed)(UINT32 pins); + const device_config *device; + const address_space *program; + const address_space *data; +} dsp56k_core; + + +/*************************************************************************** + PUBLIC FUNCTIONS +***************************************************************************/ + +void dsp56k_host_interface_write(device_config* device, UINT8 offset, UINT8 data); +UINT8 dsp56k_host_interface_read(device_config* device, UINT8 offset); + +UINT16 dsp56k_get_peripheral_memory(device_config* device, UINT16 addr); #endif /* __DSP56K_H__ */ diff --git a/src/emu/cpu/dsp56k/dsp56mem.c b/src/emu/cpu/dsp56k/dsp56mem.c index 708bfba527c..695dc7149bb 100644 --- a/src/emu/cpu/dsp56k/dsp56mem.c +++ b/src/emu/cpu/dsp56k/dsp56mem.c @@ -3,34 +3,35 @@ /* IPR Accessor Implementations */ -static void IPR_set(UINT16 value) +static void IPR_set(dsp56k_core* cpustate, UINT16 value) { /* TODO: Is there anything else? */ IPR = value; } -static INT8 irqa_ipl(void) { return ((IPR & 0x0003) >> 0) - 1; } -static UINT8 irqa_trigger(void) { return (IPR & 0x0004) >> 2; } -static INT8 irqb_ipl(void) { return ((IPR & 0x0018) >> 3) - 1; } -static UINT8 irqb_trigger(void) { return (IPR & 0x0002) >> 5; } -static INT8 codec_ipl(void) { return ((IPR & 0x00c0) >> 6) - 1; } -static INT8 host_ipl(void) { return ((IPR & 0x0300) >> 8) - 1; } -static INT8 ssi0_ipl(void) { return ((IPR & 0x0c00) >> 10) - 1; } -static INT8 ssi1_ipl(void) { return ((IPR & 0x3000) >> 12) - 1; } -static INT8 tm_ipl(void) { return ((IPR & 0xc000) >> 14) - 1; } +static INT8 irqa_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0003) >> 0) - 1; } +static UINT8 irqa_trigger(dsp56k_core* cpustate){ return (IPR & 0x0004) >> 2; } +static INT8 irqb_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0018) >> 3) - 1; } +static UINT8 irqb_trigger(dsp56k_core* cpustate){ return (IPR & 0x0002) >> 5; } +static INT8 codec_ipl(dsp56k_core* cpustate) { return ((IPR & 0x00c0) >> 6) - 1; } +static INT8 host_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0300) >> 8) - 1; } +static INT8 ssi0_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0c00) >> 10) - 1; } +static INT8 ssi1_ipl(dsp56k_core* cpustate) { return ((IPR & 0x3000) >> 12) - 1; } +static INT8 tm_ipl(dsp56k_core* cpustate) { return ((IPR & 0xc000) >> 14) - 1; } -static void mem_reset(void) +static void mem_reset(dsp56k_core* cpustate) { // Reset the HI registers - dsp56k_host_interface_reset(); + dsp56k_host_interface_reset(cpustate); // Reset the IO registers - dsp56k_io_reset(); + dsp56k_io_reset(cpustate); } /* Work */ static READ16_HANDLER( peripheral_register_r ) { + dsp56k_core* cpustate = (dsp56k_core*)space->cpu->token; // (printf) logerror("Peripheral read 0x%04x\n", O2A(offset)); switch (O2A(offset)) @@ -92,12 +93,12 @@ static READ16_HANDLER( peripheral_register_r ) // HTX/HRX: Host TX/RX Register case 0xffe5: // 5-5 - if (!HRDF_bit()) + if (!HRDF_bit(cpustate)) return 0xbeef; else { UINT16 value = HRX; // TODO: Maybe not exactly right? Just being safe. - HRDF_bit_set(0); + HRDF_bit_set(cpustate, 0); return value; } break; @@ -165,6 +166,8 @@ static READ16_HANDLER( peripheral_register_r ) static WRITE16_HANDLER( peripheral_register_w ) { + dsp56k_core* cpustate = (dsp56k_core*)space->cpu->token; + // Its primary behavior is RAM // COMBINE_DATA(&dsp56k_peripheral_ram[offset]); @@ -175,27 +178,27 @@ static WRITE16_HANDLER( peripheral_register_w ) { // Port B Control Register (PBC) case 0xffc0: - PBC_set(data); + PBC_set(cpustate, data); break; // Port C Control Register (PCC) case 0xffc1: - PCC_set(data); + PCC_set(cpustate, data); break; // Port B Data Direction Register (PBDDR) case 0xffc2: - PBDDR_set(data); + PBDDR_set(cpustate, data); break; // Port C Data Direction Register (PCDDR) case 0xffc3: - PCDDR_set(data); + PCDDR_set(cpustate, data); break; // HCR: Host Control Register case 0xffc4: - HCR_set(data); + HCR_set(cpustate, data); break; // COCR @@ -228,22 +231,22 @@ static WRITE16_HANDLER( peripheral_register_w ) // BCR: Bus Control Register case 0xffde: - BCR_set(data); + BCR_set(cpustate, data); break; // IPR: Interrupt Priority Register case 0xffdf: - IPR_set(data); + IPR_set(cpustate, data); break; // Port B Data Register (PBD) case 0xffe2: - PBD_set(data); + PBD_set(cpustate, data); break; // Port C Data Register (PCD) case 0xffe3: - PCD_set(data); + PCD_set(cpustate, data); break; // HSR: Host Status Register @@ -252,7 +255,7 @@ static WRITE16_HANDLER( peripheral_register_w ) // HTX/HRX: Host TX/RX Register case 0xffe5: HTX = data; - HTDE_bit_set(0); // 5-5 + HTDE_bit_set(cpustate, 0); // 5-5 break; // COSR @@ -325,49 +328,49 @@ static WRITE16_HANDLER( peripheral_register_w ) /************************************/ /* Host Control Register (HCR) Bits */ /************************************/ -static void HCR_set(UINT16 value) +static void HCR_set(dsp56k_core* cpustate, UINT16 value) { - HF3_bit_set ((value & 0x0010) >> 4); - HF2_bit_set ((value & 0x0008) >> 3); - HCIE_bit_set((value & 0x0004) >> 2); - HTIE_bit_set((value & 0x0002) >> 1); - HRIE_bit_set((value & 0x0001) >> 0); + HF3_bit_set (cpustate, (value & 0x0010) >> 4); + HF2_bit_set (cpustate, (value & 0x0008) >> 3); + HCIE_bit_set(cpustate, (value & 0x0004) >> 2); + HTIE_bit_set(cpustate, (value & 0x0002) >> 1); + HRIE_bit_set(cpustate, (value & 0x0001) >> 0); } -//static UINT16 HF3_bit(void); #define hf3BIT ((HCR & 0x0010) != 0) -//static UINT16 HF2_bit(void); #define hf2BIT ((HCR & 0x0008) != 0) -static UINT16 HCIE_bit(void) { return ((HCR & 0x0004) != 0); } -static UINT16 HTIE_bit(void) { return ((HCR & 0x0002) != 0); } -static UINT16 HRIE_bit(void) { return ((HCR & 0x0001) != 0); } +//static UINT16 HF3_bit(dsp56k_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0) +//static UINT16 HF2_bit(dsp56k_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0) +static UINT16 HCIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0004) != 0); } +static UINT16 HTIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0002) != 0); } +static UINT16 HRIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0001) != 0); } -static void HF3_bit_set(UINT16 value) +static void HF3_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HCR &= ~(0x0010); HCR |= (value << 4); - HF3_bit_host_set(value); + HF3_bit_host_set(cpustate, value); } -static void HF2_bit_set(UINT16 value) +static void HF2_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HCR &= ~(0x0008); HCR |= (value << 3); - HF2_bit_host_set(value); + HF2_bit_host_set(cpustate, value); } -static void HCIE_bit_set(UINT16 value) +static void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HCR &= ~(0x0004); HCR |= (value << 2); } -static void HTIE_bit_set(UINT16 value) +static void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HCR &= ~(0x0002); HCR |= (value << 1); } -static void HRIE_bit_set(UINT16 value) +static void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HCR &= ~(0x0001); @@ -377,68 +380,68 @@ static void HRIE_bit_set(UINT16 value) /***********************************/ /* Host Status Register (HSR) Bits */ /***********************************/ -//static UINT16 DMA_bit(void); #define dmaBIT ((HSR & 0x0080) != 0) -//static UINT16 HF1_bit(void); #define hf1BIT ((HSR & 0x0010) != 0) -//static UINT16 HF0_bit(void); #define hf0BIT ((HSR & 0x0008) != 0) -//static UINT16 HCP_bit(void); #define hcpBIT ((HSR & 0x0004) != 0) -static UINT16 HTDE_bit(void) { return ((HSR & 0x0002) != 0); } -static UINT16 HRDF_bit(void) { return ((HSR & 0x0001) != 0); } +//static UINT16 DMA_bit(dsp56k_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0) +//static UINT16 HF1_bit(dsp56k_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0) +//static UINT16 HF0_bit(dsp56k_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0) +//static UINT16 HCP_bit(dsp56k_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0) +static UINT16 HTDE_bit(dsp56k_core* cpustate) { return ((HSR & 0x0002) != 0); } +static UINT16 HRDF_bit(dsp56k_core* cpustate) { return ((HSR & 0x0001) != 0); } -static void DMA_bit_set(UINT16 value) +static void DMA_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HSR &= ~(0x0080); HSR |= (value << 7); // TODO: 5-12 When the DMA bit is set, the DMA mode is enabled by the Host Mode bits HM0 & HM1 } -static void HF1_bit_set(UINT16 value) +static void HF1_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HSR &= ~(0x0010); HSR |= (value << 4); } -static void HF0_bit_set(UINT16 value) +static void HF0_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HSR &= ~(0x0008); HSR |= (value << 3); } -static void HCP_bit_set(UINT16 value) +static void HCP_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HSR &= ~(0x0004); HSR |= (value << 2); - if (value && HCIE_bit()) - dsp56k_add_pending_interrupt("Host Command"); + if (value && HCIE_bit(cpustate)) + dsp56k_add_pending_interrupt(cpustate, "Host Command"); } -static void HTDE_bit_set(UINT16 value) +static void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HSR &= ~(0x0002); HSR |= (value << 1); // 5-10 If HTIE bit is set, whip out a Host Transmit Data interrupt - if (value && HTIE_bit()) - dsp56k_add_pending_interrupt("Host Transmit Data"); + if (value && HTIE_bit(cpustate)) + dsp56k_add_pending_interrupt(cpustate, "Host Transmit Data"); // 5-5 If both me and RXDF are cleared, transmit data to the host - if (!value && !RXDF_bit()) - dsp56k_host_interface_HTX_to_host(); + if (!value && !RXDF_bit(cpustate)) + dsp56k_host_interface_HTX_to_host(cpustate); } -static void HRDF_bit_set(UINT16 value) +static void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x01; HSR &= ~(0x0001); HSR |= (value << 0); // 5-10 If HRIE is set, whip out a Host Receive Data interrupt - if (value && HRIE_bit()) - dsp56k_add_pending_interrupt("Host Receive Data"); + if (value && HRIE_bit(cpustate)) + dsp56k_add_pending_interrupt(cpustate, "Host Receive Data"); // 5-5 If both me and TXDE are cleared, transmit data to the dsp56k - if (!value && !TXDE_bit()) - dsp56k_host_interface_host_to_HTX(); + if (!value && !TXDE_bit(cpustate)) + dsp56k_host_interface_host_to_HTX(cpustate); } @@ -449,48 +452,48 @@ static void HRDF_bit_set(UINT16 value) /*****************************************/ /* Interrupt Control Register (ICR) Bits */ /*****************************************/ -static void ICR_set(UINT8 value) +static void ICR_set(dsp56k_core* cpustate, UINT8 value) { - HF1_bit_host_set((value & 0x10) >> 4); - HF0_bit_host_set((value & 0x08) >> 3); - TREQ_bit_set((value & 0x02) >> 1); - RREQ_bit_set((value & 0x01) >> 0); + HF1_bit_host_set(cpustate, (value & 0x10) >> 4); + HF0_bit_host_set(cpustate, (value & 0x08) >> 3); + TREQ_bit_set(cpustate, (value & 0x02) >> 1); + RREQ_bit_set(cpustate, (value & 0x01) >> 0); } -//static UINT8 INIT_bit(void); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0) -//static UINT8 HM1_bit(void); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0) -//static UINT8 HM0_bit(void); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0) -//static UINT8 HF1_bit_host(void); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0) -//static UINT8 HF0_bit_host(void); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0) -//static UINT8 TREQ_bit(void); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0) -//static UINT8 RREQ_bit(void); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0) +//static UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0) +//static UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0) +//static UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0) +//static UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0) +//static UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0) +//static UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0) +//static UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0) -//static void INIT_bit_set(UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080)) -//static void HM1_bit_set(UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040)) -//static void HM0_bit_set(UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020)) -static void HF1_bit_host_set(UINT8 value) +//static void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080)) +//static void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040)) +//static void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020)) +static void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; ICR &= ~(0x10); ICR |= (value << 4); - HF1_bit_set(value); // 5-14 + HF1_bit_set(cpustate, value); // 5-14 } -static void HF0_bit_host_set(UINT8 value) +static void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; ICR &= ~(0x08); ICR |= (value << 3); - HF0_bit_set(value); // 5-13 + HF0_bit_set(cpustate, value); // 5-13 } -static void TREQ_bit_set(UINT8 value) +static void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; ICR &= ~(0x02); ICR |= (value << 1); } -static void RREQ_bit_set(UINT8 value) +static void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; ICR &= ~(0x01); @@ -508,24 +511,24 @@ static void RREQ_bit_set(UINT8 value) /**************************************/ /* Command Vector Register (CVR) Bits */ /**************************************/ -static UINT8 HV_bits(void) { return (CVR & 0x1f); } +static UINT8 HV_bits(dsp56k_core* cpustate) { return (CVR & 0x1f); } -static void CVR_set(UINT8 value) +static void CVR_set(dsp56k_core* cpustate, UINT8 value) { /* A single, unified place to run all callbacks for each of the bits */ - HC_bit_set((value & 0x80) >> 7); - HV_bits_set((value & 0x1f)); + HC_bit_set(cpustate, (value & 0x80) >> 7); + HV_bits_set(cpustate, (value & 0x1f)); } -static void HC_bit_set(UINT8 value) +static void HC_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; CVR &= ~(0x80); CVR |= (value << 7); - HCP_bit_set(value); // 5-9 & 5-11 + HCP_bit_set(cpustate, value); // 5-9 & 5-11 } -static void HV_bits_set(UINT8 value) +static void HV_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x1f; CVR &= ~(0x1f); @@ -536,79 +539,81 @@ static void HV_bits_set(UINT8 value) /****************************************/ /* Interrupt Status Register (ISR) Bits */ /****************************************/ -static UINT8 TXDE_bit(void) { return ((ISR & 0x0002) != 0); } -static UINT8 RXDF_bit(void) { return ((ISR & 0x0001) != 0); } +static UINT8 TXDE_bit(dsp56k_core* cpustate) { return ((ISR & 0x0002) != 0); } +static UINT8 RXDF_bit(dsp56k_core* cpustate) { return ((ISR & 0x0001) != 0); } -static void HF3_bit_host_set(UINT8 value) +static void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; ISR &= ~(0x0010); ISR |= (value << 4); } -static void HF2_bit_host_set(UINT8 value) +static void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; ISR &= ~(0x0008); ISR |= (value << 3); } -static void TXDE_bit_set(UINT8 value) +static void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; ISR &= ~(0x0002); ISR |= (value << 1); // If both me and the HRDF are cleared, transmit data to the dsp56k - if (!value && !HRDF_bit()) - dsp56k_host_interface_host_to_HTX(); + if (!value && !HRDF_bit(cpustate)) + dsp56k_host_interface_host_to_HTX(cpustate); } -static void RXDF_bit_set(UINT8 value) +static void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; ISR &= ~(0x0001); ISR |= (value << 0); // If both me and HTDE are cleared, transmit data to the host - if (!value && !HTDE_bit()) - dsp56k_host_interface_HTX_to_host(); + if (!value && !HTDE_bit(cpustate)) + dsp56k_host_interface_HTX_to_host(cpustate); } // TODO: 5-11 What is the host processor Initialize function? -static void dsp56k_host_interface_reset(void) +static void dsp56k_host_interface_reset(dsp56k_core* cpustate) { // Hook up the CPU-side pointers properly. - core.HI.hcr = &dsp56k_peripheral_ram[A2O(0xffc4)]; - core.HI.hsr = &dsp56k_peripheral_ram[A2O(0xffe4)]; - core.HI.htrx = &dsp56k_peripheral_ram[A2O(0xffe5)]; + cpustate->HI.hcr = &dsp56k_peripheral_ram[A2O(0xffc4)]; + cpustate->HI.hsr = &dsp56k_peripheral_ram[A2O(0xffe4)]; + cpustate->HI.htrx = &dsp56k_peripheral_ram[A2O(0xffe5)]; // The Bootstrap hack is initialized to write to address 0x0000 - core.HI.bootstrap_offset = 0x0000; + cpustate->HI.bootstrap_offset = 0x0000; /* HCR */ - HCR_set(0x0000); // 5-10 + HCR_set(cpustate, 0x0000); // 5-10 /* HSR */ - HRDF_bit_set(0); // 5-11 - HTDE_bit_set(1); // 5-11 - HCP_bit_set(0); // 5-11 - HF0_bit_set(0); // 5-12 - HF1_bit_set(0); // 5-12 - DMA_bit_set(0); // 5-12 + HRDF_bit_set(cpustate, 0); // 5-11 + HTDE_bit_set(cpustate, 1); // 5-11 + HCP_bit_set(cpustate, 0); // 5-11 + HF0_bit_set(cpustate, 0); // 5-12 + HF1_bit_set(cpustate, 0); // 5-12 + DMA_bit_set(cpustate, 0); // 5-12 /* CVR*/ - HV_bits_set(0x16); // 5-7 - HC_bit_set(0); // 5-9 + HV_bits_set(cpustate, 0x16); // 5-7 + HC_bit_set(cpustate, 0); // 5-9 /* TODO: ISR (at least) */ } /* These two functions are exposed to the outside world */ /* They represent the host side of the dsp56k's host interface */ -void dsp56k_host_interface_write(UINT8 offset, UINT8 data) +void dsp56k_host_interface_write(device_config* device, UINT8 offset, UINT8 data) { + dsp56k_core* cpustate = device->token; + /* Not exactly correct since the bootstrap hack doesn't need this to be true */ /* if (!host_interface_active()) @@ -620,24 +625,24 @@ void dsp56k_host_interface_write(UINT8 offset, UINT8 data) // Interrupt Control Register (ICR) case 0x00: // HACK - if (core.bootstrap_mode == BOOTSTRAP_HI) + if (cpustate->bootstrap_mode == BOOTSTRAP_HI) { // A-4 If they set HF0 while in bootstrap mode, it stops the bootstrap short. if (data & 0x08) { - core.bootstrap_mode = BOOTSTRAP_OFF; + cpustate->bootstrap_mode = BOOTSTRAP_OFF; PC = 0x0000; // TODO: Do we set HF0 then, or let it slide? // TODO: Do I allow it to do an ICR_set(), or intercept it and throw everything away? break; } } - ICR_set(data); + ICR_set(cpustate, data); break; // Command Vector Register (CVR) case 0x01: - CVR_set(data); + CVR_set(cpustate, data); break; // Interrupt status register (ISR) - Read only! @@ -661,14 +666,14 @@ void dsp56k_host_interface_write(UINT8 offset, UINT8 data) // Transmit byte register - high byte (TXH) case 0x06: // HACK - if (core.bootstrap_mode == BOOTSTRAP_HI) + if (cpustate->bootstrap_mode == BOOTSTRAP_HI) { - dsp56k_program_ram[core.HI.bootstrap_offset] &= 0x00ff; - dsp56k_program_ram[core.HI.bootstrap_offset] |= (data << 8); + dsp56k_program_ram[cpustate->HI.bootstrap_offset] &= 0x00ff; + dsp56k_program_ram[cpustate->HI.bootstrap_offset] |= (data << 8); break; /* Probably the right thing to do, given this is a hack */ } - if (TXDE_bit()) // 5-5 + if (TXDE_bit(cpustate)) // 5-5 { TXH = data; } @@ -677,23 +682,23 @@ void dsp56k_host_interface_write(UINT8 offset, UINT8 data) // Transmit byte register - low byte (TXL) case 0x07: // HACK - if (core.bootstrap_mode == BOOTSTRAP_HI) + if (cpustate->bootstrap_mode == BOOTSTRAP_HI) { - dsp56k_program_ram[core.HI.bootstrap_offset] &= 0xff00; - dsp56k_program_ram[core.HI.bootstrap_offset] |= data; - core.HI.bootstrap_offset++; + dsp56k_program_ram[cpustate->HI.bootstrap_offset] &= 0xff00; + dsp56k_program_ram[cpustate->HI.bootstrap_offset] |= data; + cpustate->HI.bootstrap_offset++; - if (core.HI.bootstrap_offset == 0x800) + if (cpustate->HI.bootstrap_offset == 0x800) { - core.bootstrap_mode = BOOTSTRAP_OFF; + cpustate->bootstrap_mode = BOOTSTRAP_OFF; } break; /* Probably the right thing to do, given this is a hack */ } - if (TXDE_bit()) // 5-5 + if (TXDE_bit(cpustate)) // 5-5 { TXL = data; - TXDE_bit_set(0); + TXDE_bit_set(cpustate, 0); } break; @@ -701,8 +706,10 @@ void dsp56k_host_interface_write(UINT8 offset, UINT8 data) } } -UINT8 dsp56k_host_interface_read(UINT8 offset) +UINT8 dsp56k_host_interface_read(device_config* device, UINT8 offset) { + dsp56k_core* cpustate = device->token; + /* Not exactly correct since the bootstrap hack doesn't need this to be true */ /* if (!host_interface_active()) @@ -744,7 +751,7 @@ UINT8 dsp56k_host_interface_read(UINT8 offset) // Receive byte register - high byte (RXH) case 0x06: // 5-5 - if (!RXDF_bit()) + if (!RXDF_bit(cpustate)) return 0xbf; else return RXH; @@ -753,12 +760,12 @@ UINT8 dsp56k_host_interface_read(UINT8 offset) // Receive byte register - low byte (RXL) case 0x07: // 5-5 - if (!RXDF_bit()) + if (!RXDF_bit(cpustate)) return 0xbf; else { UINT8 value = RXL; // TODO: Maybe not exactly right? I'm just being safe. - RXDF_bit_set(0); + RXDF_bit_set(cpustate, 0); return value; } break; @@ -770,22 +777,22 @@ UINT8 dsp56k_host_interface_read(UINT8 offset) return 0xff; } -static void dsp56k_host_interface_HTX_to_host(void) +static void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate) { RXH = ((HTX & 0xff00) >> 8); RXL = ((HTX & 0x00ff)); - RXDF_bit_set(1); - HTDE_bit_set(1); + RXDF_bit_set(cpustate, 1); + HTDE_bit_set(cpustate, 1); } -static void dsp56k_host_interface_host_to_HTX(void) +static void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate) { HRX &= 0x00ff; HRX |= (TXH << 8); HRX &= 0xff00; HRX |= TXL; - TXDE_bit_set(1); - HRDF_bit_set(1); + TXDE_bit_set(cpustate, 1); + HRDF_bit_set(cpustate, 1); } @@ -793,20 +800,20 @@ static void dsp56k_host_interface_host_to_HTX(void) I/O INTERFACE ***************************************************************************/ /* BCR */ -static void BCR_set(UINT16 value) +static void BCR_set(dsp56k_core* cpustate, UINT16 value) { - RH_bit_set((value & 0x8000) >> 15); - BS_bit_set((value & 0x4000) >> 14); - external_x_wait_states_set((value & 0x03e0) >> 5); - external_p_wait_states_set((value & 0x001f) >> 0); + RH_bit_set(cpustate, (value & 0x8000) >> 15); + BS_bit_set(cpustate, (value & 0x4000) >> 14); + external_x_wait_states_set(cpustate, (value & 0x03e0) >> 5); + external_p_wait_states_set(cpustate, (value & 0x001f) >> 0); } -//static UINT16 RH_bit(void); -//static UINT16 BS_bit(void); -//static UINT16 external_x_wait_states(void); -//static UINT16 external_p_wait_states(void); +//static UINT16 RH_bit(dsp56k_core* cpustate); +//static UINT16 BS_bit(dsp56k_core* cpustate); +//static UINT16 external_x_wait_states(dsp56k_core* cpustate); +//static UINT16 external_p_wait_states(dsp56k_core* cpustate); -static void RH_bit_set(UINT16 value) +static void RH_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x0001; BCR &= ~(0x8000); @@ -814,7 +821,7 @@ static void RH_bit_set(UINT16 value) // TODO: 4-6 Assert BR pin? } -static void BS_bit_set(UINT16 value) +static void BS_bit_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x0001; BCR &= ~(0x4000); @@ -822,13 +829,13 @@ static void BS_bit_set(UINT16 value) // TODO: 4-6 Respond to BR pin? } -static void external_x_wait_states_set(UINT16 value) +static void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x001f; BCR &= ~(0x03e0); BCR |= (value << 5); } -static void external_p_wait_states_set(UINT16 value) +static void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value) { value = value & 0x001f; BCR &= ~(0x001f); @@ -837,7 +844,7 @@ static void external_p_wait_states_set(UINT16 value) /* Port B Control Register PBC */ -static void PBC_set(UINT16 value) +static void PBC_set(dsp56k_core* cpustate, UINT16 value) { if (value & 0xfffe) logerror("Dsp56k : Attempting to set reserved bits in the PBC. Ignoring.\n"); @@ -848,7 +855,7 @@ static void PBC_set(UINT16 value) } #ifdef UNUSED_FUNCTION -static int host_interface_active(void) +static int host_interface_active(dsp56k_core* cpustate) { /* The host interface is active if the 0th bit in the PBC is set */ return PBC & 0x0001; @@ -856,7 +863,7 @@ static int host_interface_active(void) #endif /* Port B Data Direction Register (PBDDR) */ -static void PBDDR_set(UINT16 value) +static void PBDDR_set(dsp56k_core* cpustate, UINT16 value) { if (value & 0x8000) logerror("Dsp56k : Attempting to set reserved bits in the PBDDR. Ignoring.\n"); @@ -869,7 +876,7 @@ static void PBDDR_set(UINT16 value) } /* Port B Data Register (PBD) */ -static void PBD_set(UINT16 value) +static void PBD_set(dsp56k_core* cpustate, UINT16 value) { if (value & 0x8000) logerror("Dsp56k : Attempting to set reserved bits in the PBD. Ignoring.\n"); @@ -882,7 +889,7 @@ static void PBD_set(UINT16 value) } /* Port C Control Register (PCC) */ -static void PCC_set(UINT16 value) +static void PCC_set(dsp56k_core* cpustate, UINT16 value) { if (value & 0xf000) logerror("Dsp56k : Attempting to set reserved bits in the PCC. Ignoring.\n"); @@ -895,7 +902,7 @@ static void PCC_set(UINT16 value) } /* Port C Data Direction Register (PCDDR) */ -static void PCDDR_set(UINT16 value) +static void PCDDR_set(dsp56k_core* cpustate, UINT16 value) { if (value & 0xf000) logerror("Dsp56k : Attempting to set reserved bits in the PCDDR. Ignoring.\n"); @@ -908,7 +915,7 @@ static void PCDDR_set(UINT16 value) } /* Port C Data Register (PCD) */ -static void PCD_set(UINT16 value) +static void PCD_set(dsp56k_core* cpustate, UINT16 value) { if (value & 0xf000) logerror("Dsp56k : Attempting to set reserved bits in the PCD. Ignoring.\n"); @@ -921,18 +928,19 @@ static void PCD_set(UINT16 value) PCD |= (value << 0); } -static void dsp56k_io_reset(void) +static void dsp56k_io_reset(dsp56k_core* cpustate) { /* The BCR = 0x43ff */ - RH_bit_set(0); - BS_bit_set(1); - external_x_wait_states_set(0x1f); - external_p_wait_states_set(0x1f); + RH_bit_set(cpustate, 0); + BS_bit_set(cpustate, 1); + external_x_wait_states_set(cpustate, 0x1f); + external_p_wait_states_set(cpustate, 0x1f); } /* MISC*/ -UINT16 dsp56k_get_peripheral_memory(UINT16 addr) +UINT16 dsp56k_get_peripheral_memory(device_config* device, UINT16 addr) { + // TODO // THIS COMES BACK dsp56k_core* cpustate = device->token; return dsp56k_peripheral_ram[A2O(addr)]; } diff --git a/src/emu/cpu/dsp56k/dsp56ops.c b/src/emu/cpu/dsp56k/dsp56ops.c index 4984c58568c..abc24a4edd5 100644 --- a/src/emu/cpu/dsp56k/dsp56ops.c +++ b/src/emu/cpu/dsp56k/dsp56ops.c @@ -38,172 +38,171 @@ typedef struct _typed_pointer typed_pointer; #define BITS(CUR,MASK) (Dsp56kOpMask(CUR,MASK)) - /*********************/ /* Opcode prototypes */ /*********************/ -static size_t dsp56k_op_addsub_2 (const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); -static size_t dsp56k_op_mac_1 (const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); -static size_t dsp56k_op_macr_1 (const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); -static size_t dsp56k_op_move_1 (const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); -static size_t dsp56k_op_mpy_1 (const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); -static size_t dsp56k_op_mpyr_1 (const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); -static size_t dsp56k_op_tfr_2 (const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); -static size_t dsp56k_op_mpy_2 (const UINT16 op_byte, UINT8* cycles); -static size_t dsp56k_op_mac_2 (const UINT16 op_byte, UINT8* cycles); -static size_t dsp56k_op_clr (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_add (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_move (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_tfr (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_rnd (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_tst (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_inc (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_inc24 (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_or (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_asr (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_asl (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_lsr (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_lsl (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_eor (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_subl (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_sub (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_clr24 (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_sbc (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_cmp (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_neg (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_not (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_dec (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_dec24 (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_and (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_abs (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_ror (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_rol (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_cmpm (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_mpy (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_mpyr (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_mac (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_macr (const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); -static size_t dsp56k_op_adc (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_andi (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_asl4 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_asr4 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_asr16 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_bfop (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_bfop_1 (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_bfop_2 (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_bcc (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_bcc_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_bcc_2 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_bra (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_bra_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_bra_2 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_brkcc (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_bscc (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_bscc_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_bsr (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_bsr_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_chkaau (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_debug (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_debugcc (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_div (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_dmac (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_do (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_do_1 (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_do_2 (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_doforever(const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_enddo (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_ext (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_illegal (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_imac (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_impy (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_jcc (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_jcc_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_jmp (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_jmp_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_jscc (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_jscc_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_jsr (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_jsr_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_jsr_2 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_lea (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_lea_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_macsuuu (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_move_2 (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_movec (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_movec_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_movec_2 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_movec_3 (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_movec_4 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_movec_5 (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_movei (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_movem (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_movem_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_movem_2 (const UINT16 op, const UINT16 op2, UINT8* cycles); -static size_t dsp56k_op_movep (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_movep_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_moves (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_mpysuuu (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_negc (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_nop (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_norm (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_ori (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_rep (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_rep_1 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_rep_2 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_repcc (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_reset (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_rti (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_rts (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_stop (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_swap (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_swi (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_tcc (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_tfr2 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_tfr3 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_tst2 (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_wait (const UINT16 op, UINT8* cycles); -static size_t dsp56k_op_zero (const UINT16 op, UINT8* cycles); - - -static void execute_register_to_register_data_move(const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value); -static void execute_address_register_update(const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value); -static void execute_x_memory_data_move (const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value); -static void execute_x_memory_data_move2(const UINT16 op, typed_pointer* d_register); -static void execute_dual_x_memory_data_read(const UINT16 op, typed_pointer* d_register); -static void execute_x_memory_data_move_with_short_displacement(const UINT16 op, const UINT16 op2); - -static UINT16 decode_BBB_bitmask(UINT16 BBB, UINT16 *iVal); -static int decode_cccc_table(UINT16 cccc); -static void decode_DDDDD_table(UINT16 DDDDD, typed_pointer* ret); -static void decode_DD_table(UINT16 DD, typed_pointer* ret); -static void decode_F_table(UINT16 F, typed_pointer* ret); -static void decode_h0hF_table(UINT16 h0h, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret); -static void decode_HH_table(UINT16 HH, typed_pointer* ret); -static void decode_HHH_table(UINT16 HHH, typed_pointer* ret); -static void decode_IIII_table(UINT16 IIII, typed_pointer* src_ret, typed_pointer* dst_ret, void* working); -static void decode_JJJF_table(UINT16 JJJ, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret); -static void decode_JJF_table(UINT16 JJ, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret); -static void decode_KKK_table(UINT16 KKK, typed_pointer* dst_ret1, typed_pointer* dst_ret2, void* working); -static void decode_QQF_table(UINT16 QQ, UINT16 F, void **S1, void **S2, void **D); -static void decode_QQF_special_table(UINT16 QQ, UINT16 F, void **S1, void **S2, void **D); -static void decode_QQQF_table(UINT16 QQQ, UINT16 F, void **S1, void **S2, void **D); -static void decode_RR_table(UINT16 RR, typed_pointer* ret); -static void decode_TT_table(UINT16 TT, typed_pointer* ret); -static void decode_uuuuF_table(UINT16 uuuu, UINT16 F, UINT8 add_sub_other, typed_pointer* src_ret, typed_pointer* dst_ret); -static void decode_Z_table(UINT16 Z, typed_pointer* ret); - -static void execute_m_table(int x, UINT16 m); -static void execute_mm_table(UINT16 rnum, UINT16 mm); -static void execute_MM_table(UINT16 rnum, UINT16 MM); -static UINT16 execute_q_table(int RR, UINT16 q); -static void execute_z_table(int RR, UINT16 z); - -static UINT16 assemble_address_from_Pppppp_table(UINT16 P, UINT16 ppppp); -static UINT16 assemble_address_from_IO_short_address(UINT16 pp); -static UINT16 assemble_address_from_6bit_signed_relative_short_address(UINT16 srs); - -static void dsp56k_process_loop(void); -static void dsp56k_process_rep(size_t repSize); +static size_t dsp56k_op_addsub_2 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); +static size_t dsp56k_op_mac_1 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); +static size_t dsp56k_op_macr_1 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); +static size_t dsp56k_op_move_1 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); +static size_t dsp56k_op_mpy_1 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); +static size_t dsp56k_op_mpyr_1 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); +static size_t dsp56k_op_tfr_2 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles); +static size_t dsp56k_op_mpy_2 (dsp56k_core* cpustate, const UINT16 op_byte, UINT8* cycles); +static size_t dsp56k_op_mac_2 (dsp56k_core* cpustate, const UINT16 op_byte, UINT8* cycles); +static size_t dsp56k_op_clr (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_add (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_move (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_tfr (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_rnd (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_tst (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_inc (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_inc24 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_or (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_asr (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_asl (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_lsr (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_lsl (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_eor (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_subl (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_sub (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_clr24 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_sbc (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_cmp (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_neg (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_not (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_dec (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_dec24 (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_and (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_abs (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_ror (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_rol (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_cmpm (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_mpy (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_mpyr (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_mac (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_macr (dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles); +static size_t dsp56k_op_adc (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_andi (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_asl4 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_asr4 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_asr16 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_bfop (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_bfop_1 (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_bfop_2 (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_bcc (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_bcc_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_bcc_2 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_bra (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_bra_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_bra_2 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_brkcc (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_bscc (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_bscc_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_bsr (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_bsr_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_chkaau (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_debug (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_debugcc (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_div (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_dmac (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_do (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_do_1 (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_do_2 (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_doforever(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_enddo (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_ext (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_illegal (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_imac (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_impy (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_jcc (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_jcc_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_jmp (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_jmp_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_jscc (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_jscc_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_jsr (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_jsr_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_jsr_2 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_lea (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_lea_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_macsuuu (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_move_2 (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_movec (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_movec_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_movec_2 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_movec_3 (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_movec_4 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_movec_5 (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_movei (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_movem (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_movem_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_movem_2 (dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles); +static size_t dsp56k_op_movep (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_movep_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_moves (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_mpysuuu (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_negc (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_nop (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_norm (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_ori (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_rep (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_rep_1 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_rep_2 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_repcc (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_reset (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_rti (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_rts (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_stop (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_swap (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_swi (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_tcc (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_tfr2 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_tfr3 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_tst2 (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_wait (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); +static size_t dsp56k_op_zero (dsp56k_core* cpustate, const UINT16 op, UINT8* cycles); + + +static void execute_register_to_register_data_move(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value); +static void execute_address_register_update(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value); +static void execute_x_memory_data_move (dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value); +static void execute_x_memory_data_move2(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register); +static void execute_dual_x_memory_data_read(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register); +static void execute_x_memory_data_move_with_short_displacement(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2); + +static UINT16 decode_BBB_bitmask(dsp56k_core* cpustate, UINT16 BBB, UINT16 *iVal); +static int decode_cccc_table(dsp56k_core* cpustate, UINT16 cccc); +static void decode_DDDDD_table(dsp56k_core* cpustate, UINT16 DDDDD, typed_pointer* ret); +static void decode_DD_table(dsp56k_core* cpustate, UINT16 DD, typed_pointer* ret); +static void decode_F_table(dsp56k_core* cpustate, UINT16 F, typed_pointer* ret); +static void decode_h0hF_table(dsp56k_core* cpustate, UINT16 h0h, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret); +static void decode_HH_table(dsp56k_core* cpustate, UINT16 HH, typed_pointer* ret); +static void decode_HHH_table(dsp56k_core* cpustate, UINT16 HHH, typed_pointer* ret); +static void decode_IIII_table(dsp56k_core* cpustate, UINT16 IIII, typed_pointer* src_ret, typed_pointer* dst_ret, void* working); +static void decode_JJJF_table(dsp56k_core* cpustate, UINT16 JJJ, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret); +static void decode_JJF_table(dsp56k_core* cpustate, UINT16 JJ, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret); +static void decode_KKK_table(dsp56k_core* cpustate, UINT16 KKK, typed_pointer* dst_ret1, typed_pointer* dst_ret2, void* working); +static void decode_QQF_table(dsp56k_core* cpustate, UINT16 QQ, UINT16 F, void **S1, void **S2, void **D); +static void decode_QQF_special_table(dsp56k_core* cpustate, UINT16 QQ, UINT16 F, void **S1, void **S2, void **D); +static void decode_QQQF_table(dsp56k_core* cpustate, UINT16 QQQ, UINT16 F, void **S1, void **S2, void **D); +static void decode_RR_table(dsp56k_core* cpustate, UINT16 RR, typed_pointer* ret); +static void decode_TT_table(dsp56k_core* cpustate, UINT16 TT, typed_pointer* ret); +static void decode_uuuuF_table(dsp56k_core* cpustate, UINT16 uuuu, UINT16 F, UINT8 add_sub_other, typed_pointer* src_ret, typed_pointer* dst_ret); +static void decode_Z_table(dsp56k_core* cpustate, UINT16 Z, typed_pointer* ret); + +static void execute_m_table(dsp56k_core* cpustate, int x, UINT16 m); +static void execute_mm_table(dsp56k_core* cpustate, UINT16 rnum, UINT16 mm); +static void execute_MM_table(dsp56k_core* cpustate, UINT16 rnum, UINT16 MM); +static UINT16 execute_q_table(dsp56k_core* cpustate, int RR, UINT16 q); +static void execute_z_table(dsp56k_core* cpustate, int RR, UINT16 z); + +static UINT16 assemble_address_from_Pppppp_table(dsp56k_core* cpustate, UINT16 P, UINT16 ppppp); +static UINT16 assemble_address_from_IO_short_address(dsp56k_core* cpustate, UINT16 pp); +static UINT16 assemble_address_from_6bit_signed_relative_short_address(dsp56k_core* cpustate, UINT16 srs); + +static void dsp56k_process_loop(dsp56k_core* cpustate); +static void dsp56k_process_rep(dsp56k_core* cpustate, size_t repSize); @@ -215,8 +214,8 @@ static UINT16 Dsp56kOpMask(UINT16 op, UINT16 mask); /* These arguments are written source->destination to fall in line with the processor's paradigm. */ static void SetDestinationValue(typed_pointer source, typed_pointer dest); -static void SetDataMemoryValue(typed_pointer source, UINT32 destinationAddr); -static void SetProgramMemoryValue(typed_pointer source, UINT32 destinationAddr); +static void SetDataMemoryValue(dsp56k_core* cpustate, typed_pointer source, UINT32 destinationAddr); +static void SetProgramMemoryValue(dsp56k_core* cpustate, typed_pointer source, UINT32 destinationAddr); @@ -224,7 +223,7 @@ static void SetProgramMemoryValue(typed_pointer source, UINT32 destinationAddr); IMPLEMENTATION ***************************************************************************/ -static void execute_one(void) +static void execute_one(dsp56k_core* cpustate) { UINT16 op; UINT16 op2; @@ -232,7 +231,7 @@ static void execute_one(void) UINT8 cycle_count = 0; /* For MAME */ - debugger_instruction_hook(core.device, PC); + debugger_instruction_hook(cpustate->device, PC); OP = ROPCODE(WORD(PC)); /* The words we're going to be working with */ @@ -253,41 +252,41 @@ static void execute_one(void) /* SUB : 011m mKKK 0rru Fuuu : A-202 */ if ((op & 0xe080) == 0x6000) { - size = dsp56k_op_addsub_2(op_byte, &d_register, &cycle_count); + size = dsp56k_op_addsub_2(cpustate, op_byte, &d_register, &cycle_count); } /* MAC : 011m mKKK 1xx0 F1QQ : A-122 */ else if ((op & 0xe094) == 0x6084) { - size = dsp56k_op_mac_1(op_byte, &d_register, &cycle_count); + size = dsp56k_op_mac_1(cpustate, op_byte, &d_register, &cycle_count); } /* MACR: 011m mKKK 1--1 F1QQ : A-124 */ else if ((op & 0xe094) == 0x6094) { - size = dsp56k_op_macr_1(op_byte, &d_register, &cycle_count); + size = dsp56k_op_macr_1(cpustate, op_byte, &d_register, &cycle_count); } /* MOVE : 011m mKKK 0rr1 0000 : A-128 */ else if ((op & 0xe09f) == 0x6010) { - size = dsp56k_op_move_1(op_byte, &d_register, &cycle_count); + size = dsp56k_op_move_1(cpustate, op_byte, &d_register, &cycle_count); } /* MPY : 011m mKKK 1xx0 F0QQ : A-160 */ else if ((op & 0xe094) == 0x6080) { - size = dsp56k_op_mpy_1(op_byte, &d_register, &cycle_count); + size = dsp56k_op_mpy_1(cpustate, op_byte, &d_register, &cycle_count); } /* MPYR : 011m mKKK 1--1 F0QQ : A-162 */ else if ((op & 0xe094) == 0x6090) { - size = dsp56k_op_mpyr_1(op_byte, &d_register, &cycle_count); + size = dsp56k_op_mpyr_1(cpustate, op_byte, &d_register, &cycle_count); } /* TFR : 011m mKKK 0rr1 F0DD : A-212 */ else if ((op & 0xe094) == 0x6010) { - size = dsp56k_op_tfr_2(op_byte, &d_register, &cycle_count); + size = dsp56k_op_tfr_2(cpustate, op_byte, &d_register, &cycle_count); } /* Now evaluate the parallel data move */ - execute_dual_x_memory_data_read(op, &d_register); + execute_dual_x_memory_data_read(cpustate, op, &d_register); } /* X Memory Data Write and Register Data Move : 0001 011k RRDD .... : A-140 */ else if ((op & 0xfe00) == 0x1600) @@ -298,12 +297,12 @@ static void execute_one(void) /* MPY : 0001 0110 RRDD FQQQ : A-160 */ if ((op & 0xff00) == 0x1600) { - size = dsp56k_op_mpy_2(op_byte, &cycle_count); + size = dsp56k_op_mpy_2(cpustate, op_byte, &cycle_count); } /* MAC : 0001 0111 RRDD FQQQ : A-122 */ else if ((op & 0xff00) == 0x1700) { - size = dsp56k_op_mac_2(op_byte, &cycle_count); + size = dsp56k_op_mac_2(cpustate, op_byte, &cycle_count); } /* Now evaluate the parallel data move */ @@ -389,178 +388,178 @@ static void execute_one(void) /* CLR : .... .... 0000 F001 : A-60 */ if ((op_byte & 0x00f7) == 0x0001) { - size = dsp56k_op_clr(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_clr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* ADD : .... .... 0000 FJJJ : A-22 */ else if ((op_byte & 0x00f0) == 0x0000) { - size = dsp56k_op_add(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_add(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* MOVE : .... .... 0001 0001 : A-128 */ else if ((op_byte & 0x00ff) == 0x0011) { - size = dsp56k_op_move(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_move(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* TFR : .... .... 0001 FJJJ : A-212 */ else if ((op_byte & 0x00f0) == 0x0010) { - size = dsp56k_op_tfr(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_tfr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* RND : .... .... 0010 F000 : A-188 */ else if ((op_byte & 0x00f7) == 0x0020) { - size = dsp56k_op_rnd(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_rnd(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* TST : .... .... 0010 F001 : A-218 */ else if ((op_byte & 0x00f7) == 0x0021) { - size = dsp56k_op_tst(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_tst(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* INC : .... .... 0010 F010 : A-104 */ else if ((op_byte & 0x00f7) == 0x0022) { - size = dsp56k_op_inc(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_inc(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* INC24 : .... .... 0010 F011 : A-106 */ else if ((op_byte & 0x00f7) == 0x0023) { - size = dsp56k_op_inc24(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_inc24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* OR : .... .... 0010 F1JJ : A-176 */ else if ((op_byte & 0x00f4) == 0x0024) { - size = dsp56k_op_or(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_or(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* ASR : .... .... 0011 F000 : A-32 */ else if ((op_byte & 0x00f7) == 0x0030) { - size = dsp56k_op_asr(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_asr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* ASL : .... .... 0011 F001 : A-28 */ else if ((op_byte & 0x00f7) == 0x0031) { - size = dsp56k_op_asl(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_asl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* LSR : .... .... 0011 F010 : A-120 */ else if ((op_byte & 0x00f7) == 0x0032) { - size = dsp56k_op_lsr(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_lsr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* LSL : .... .... 0011 F011 : A-118 */ else if ((op_byte & 0x00f7) == 0x0033) { - size = dsp56k_op_lsl(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_lsl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* EOR : .... .... 0011 F1JJ : A-94 */ else if ((op_byte & 0x00f4) == 0x0034) { - size = dsp56k_op_eor(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_eor(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* SUBL : .... .... 0100 F001 : A-204 */ else if ((op_byte & 0x00f7) == 0x0041) { - size = dsp56k_op_subl(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_subl(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* SUB : .... .... 0100 FJJJ : A-202 */ else if ((op_byte & 0x00f0) == 0x0040) { - size = dsp56k_op_sub(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_sub(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* CLR24 : .... .... 0101 F001 : A-62 */ else if ((op_byte & 0x00f7) == 0x0051) { - size = dsp56k_op_clr24(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_clr24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* SBC : .... .... 0101 F01J : A-198 */ else if ((op_byte & 0x00f6) == 0x0052) { - size = dsp56k_op_sbc(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_sbc(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* CMP : .... .... 0101 FJJJ : A-64 */ else if ((op_byte & 0x00f0) == 0x0050) { - size = dsp56k_op_cmp(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_cmp(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* NEG : .... .... 0110 F000 : A-166 */ else if ((op_byte & 0x00f7) == 0x0060) { - size = dsp56k_op_neg(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_neg(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* NOT : .... .... 0110 F001 : A-174 */ else if ((op_byte & 0x00f7) == 0x0061) { - size = dsp56k_op_not(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_not(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* DEC : .... .... 0110 F010 : A-72 */ else if ((op_byte & 0x00f7) == 0x0062) { - size = dsp56k_op_dec(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_dec(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* DEC24 : .... .... 0110 F011 : A-74 */ else if ((op_byte & 0x00f7) == 0x0063) { - size = dsp56k_op_dec24(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_dec24(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* AND : .... .... 0110 F1JJ : A-24 */ else if ((op_byte & 0x00f4) == 0x0064) { - size = dsp56k_op_and(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_and(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* ABS : .... .... 0111 F001 : A-18 */ if ((op_byte & 0x00f7) == 0x0071) { - size = dsp56k_op_abs(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_abs(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* ROR : .... .... 0111 F010 : A-192 */ else if ((op_byte & 0x00f7) == 0x0072) { - size = dsp56k_op_ror(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_ror(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* ROL : .... .... 0111 F011 : A-190 */ else if ((op_byte & 0x00f7) == 0x0073) { - size = dsp56k_op_rol(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_rol(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* CMPM : .... .... 0111 FJJJ : A-66 */ else if ((op_byte & 0x00f0) == 0x0070) { - size = dsp56k_op_cmpm(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_cmpm(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* MPY : .... .... 1k00 FQQQ : A-160 -- CONFIRMED TYPO IN DOCS (HHHH vs HHHW) */ else if ((op_byte & 0x00b0) == 0x0080) { - size = dsp56k_op_mpy(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_mpy(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* MPYR : .... .... 1k01 FQQQ : A-162 */ else if ((op_byte & 0x00b0) == 0x0090) { - size = dsp56k_op_mpyr(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_mpyr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* MAC : .... .... 1k10 FQQQ : A-122 */ else if ((op_byte & 0x00b0) == 0x00a0) { - size = dsp56k_op_mac(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_mac(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } /* MACR : .... .... 1k11 FQQQ : A-124 -- DRAMA - rr vs xx (805) */ else if ((op_byte & 0x00b0) == 0x00b0) { - size = dsp56k_op_macr(op_byte, &d_register, &prev_accum_value, &cycle_count); + size = dsp56k_op_macr(cpustate, op_byte, &d_register, &prev_accum_value, &cycle_count); } @@ -571,19 +570,19 @@ static void execute_one(void) /* DO NOTHING */ break; case kRegisterToRegister: - execute_register_to_register_data_move(op, &d_register, &prev_accum_value); + execute_register_to_register_data_move(cpustate, op, &d_register, &prev_accum_value); break; case kAddressRegister: - execute_address_register_update(op, &d_register, &prev_accum_value); + execute_address_register_update(cpustate, op, &d_register, &prev_accum_value); break; case kXMemoryDataMove: - execute_x_memory_data_move(op, &d_register, &prev_accum_value); + execute_x_memory_data_move(cpustate, op, &d_register, &prev_accum_value); break; case kXMemoryDataMove2: - execute_x_memory_data_move2(op, &d_register); + execute_x_memory_data_move2(cpustate, op, &d_register); break; case kXMemoryDataMoveWithDisp: - execute_x_memory_data_move_with_short_displacement(op, op2); + execute_x_memory_data_move_with_short_displacement(cpustate, op, op2); size = 2; break; } @@ -595,10 +594,10 @@ static void execute_one(void) { PC += size; - dsp56k_process_loop(); - dsp56k_process_rep(size); + dsp56k_process_loop(cpustate); + dsp56k_process_rep(cpustate, size); - dsp56k_icount -= 4; /* Temporarily hard-coded at 4 clocks per opcode */ /* cycle_count */ + cpustate->icount -= 4; /* Temporarily hard-coded at 4 clocks per opcode */ /* cycle_count */ return; } @@ -610,464 +609,464 @@ static void execute_one(void) /* ADC : 0001 0101 0000 F01J : A-20 */ if ((op & 0xfff6) == 0x1502) { - size = dsp56k_op_adc(op, &cycle_count); + size = dsp56k_op_adc(cpustate, op, &cycle_count); } /* ANDI : 0001 1EE0 iiii iiii : A-26 */ /* (MoveP sneaks in here if you don't check 0x0600) */ else if (((op & 0xf900) == 0x1800) & ((op & 0x0600) != 0x0000)) { - size = dsp56k_op_andi(op, &cycle_count); + size = dsp56k_op_andi(cpustate, op, &cycle_count); } /* ASL4 : 0001 0101 0011 F001 : A-30 */ else if ((op & 0xfff7) == 0x1531) { - size = dsp56k_op_asl4(op, &cycle_count); + size = dsp56k_op_asl4(cpustate, op, &cycle_count); } /* ASR4 : 0001 0101 0011 F000 : A-34 */ else if ((op & 0xfff7) == 0x1530) { - size = dsp56k_op_asr4(op, &cycle_count); + size = dsp56k_op_asr4(cpustate, op, &cycle_count); } /* ASR16 : 0001 0101 0111 F000 : A-36 */ else if ((op & 0xfff7) == 0x1570) { - size = dsp56k_op_asr16(op, &cycle_count); + size = dsp56k_op_asr16(cpustate, op, &cycle_count); } /* BFCHG : 0001 0100 11Pp pppp BBB1 0010 iiii iiii : A-38 */ else if (((op & 0xffc0) == 0x14c0) && ((op2 & 0x1f00) == 0x1200)) { - size = dsp56k_op_bfop(op, op2, &cycle_count); + size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count); } /* BFCHG : 0001 0100 101- --RR BBB1 0010 iiii iiii : A-38 */ else if (((op & 0xffe0) == 0x14a0) && ((op2 & 0x1f00) == 0x1200)) { - size = dsp56k_op_bfop_1(op, op2, &cycle_count); + size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count); } /* BFCHG : 0001 0100 100D DDDD BBB1 0010 iiii iiii : A-38 */ else if (((op & 0xffe0) == 0x1480) && ((op2 & 0x1f00) == 0x1200)) { - size = dsp56k_op_bfop_2(op, op2, &cycle_count); + size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count); } /* BFCLR : 0001 0100 11Pp pppp BBB0 0100 iiii iiii : A-40 */ else if (((op & 0xffc0) == 0x14c0) && ((op2 & 0x1f00) == 0x0400)) { - size = dsp56k_op_bfop(op, op2, &cycle_count); + size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count); } /* BFCLR : 0001 0100 101- --RR BBB0 0100 iiii iiii : A-40 */ else if (((op & 0xffe0) == 0x14a0) && ((op2 & 0x1f00) == 0x0400)) { - size = dsp56k_op_bfop_1(op, op2, &cycle_count); + size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count); } /* BFCLR : 0001 0100 100D DDDD BBB0 0100 iiii iiii : A-40 */ else if (((op & 0xffe0) == 0x1480) && ((op2 & 0x1f00) == 0x0400)) { - size = dsp56k_op_bfop_2(op, op2, &cycle_count); + size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count); } /* BFSET : 0001 0100 11Pp pppp BBB1 1000 iiii iiii : A-42 */ else if (((op & 0xffc0) == 0x14c0) && ((op2 & 0x1f00) == 0x1800)) { - size = dsp56k_op_bfop(op, op2, &cycle_count); + size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count); } /* BFSET : 0001 0100 101- --RR BBB1 1000 iiii iiii : A-42 */ else if (((op & 0xffe0) == 0x14a0) && ((op2 & 0x1f00) == 0x1800)) { - size = dsp56k_op_bfop_1(op, op2, &cycle_count); + size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count); } /* BFSET : 0001 0100 100D DDDD BBB1 1000 iiii iiii : A-42 */ else if (((op & 0xffe0) == 0x1480) && ((op2 & 0x1f00) == 0x1800)) { - size = dsp56k_op_bfop_2(op, op2, &cycle_count); + size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count); } /* BFTSTH : 0001 0100 01Pp pppp BBB1 0000 iiii iiii : A-44 */ else if (((op & 0xffc0) == 0x1440) && ((op2 & 0x1f00) == 0x1000)) { - size = dsp56k_op_bfop(op, op2, &cycle_count); + size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count); } /* BFTSTH : 0001 0100 001- --RR BBB1 0000 iiii iiii : A-44 */ else if (((op & 0xffe0) == 0x1420) && ((op2 & 0x1f00) == 0x1000)) { - size = dsp56k_op_bfop_1(op, op2, &cycle_count); + size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count); } /* BFTSTH : 0001 0100 000D DDDD BBB1 0000 iiii iiii : A-44 */ else if (((op & 0xffe0) == 0x1400) && ((op2 & 0x1f00) == 0x1000)) { - size = dsp56k_op_bfop_2(op, op2, &cycle_count); + size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count); } /* BFTSTL : 0001 0100 01Pp pppp BBB0 0000 iiii iiii : A-46 */ else if (((op & 0xffc0) == 0x1440) && ((op2 & 0x1f00) == 0x0000)) { - size = dsp56k_op_bfop(op, op2, &cycle_count); + size = dsp56k_op_bfop(cpustate, op, op2, &cycle_count); } /* BFTSTL : 0001 0100 001- --RR BBB0 0000 iiii iiii : A-46 */ else if (((op & 0xffe0) == 0x1420) && ((op2 & 0x1f00) == 0x0000)) { - size = dsp56k_op_bfop_1(op, op2, &cycle_count); + size = dsp56k_op_bfop_1(cpustate, op, op2, &cycle_count); } /* BFTSTL : 0001 0100 000D DDDD BBB0 0000 iiii iiii : A-46 */ else if (((op & 0xffe0) == 0x1400) && ((op2 & 0x1f00) == 0x0000)) { - size = dsp56k_op_bfop_2(op, op2, &cycle_count); + size = dsp56k_op_bfop_2(cpustate, op, op2, &cycle_count); } /* Bcc : 0000 0111 --11 cccc xxxx xxxx xxxx xxxx : A-48 */ else if (((op & 0xff30) == 0x0730) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_bcc(op, op2, &cycle_count); + size = dsp56k_op_bcc(cpustate, op, op2, &cycle_count); } /* Bcc : 0010 11cc ccee eeee : A-48 */ else if ((op & 0xfc00) == 0x2c00) { - size = dsp56k_op_bcc_1(op, &cycle_count); + size = dsp56k_op_bcc_1(cpustate, op, &cycle_count); } /* Bcc : 0000 0111 RR10 cccc : A-48 */ else if ((op & 0xff30) == 0x0720) { - size = dsp56k_op_bcc_2(op, &cycle_count); + size = dsp56k_op_bcc_2(cpustate, op, &cycle_count); } /* BRA : 0000 0001 0011 11-- xxxx xxxx xxxx xxxx : A-50 */ else if (((op & 0xfffc) == 0x013c) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_bra(op, op2, &cycle_count); + size = dsp56k_op_bra(cpustate, op, op2, &cycle_count); } /* BRA : 0000 1011 aaaa aaaa : A-50 */ else if ((op & 0xff00) == 0x0b00) { - size = dsp56k_op_bra_1(op, &cycle_count); + size = dsp56k_op_bra_1(cpustate, op, &cycle_count); } /* BRA : 0000 0001 0010 11RR : A-50 */ else if ((op & 0xfffc) == 0x012c) { - size = dsp56k_op_bra_2(op, &cycle_count); + size = dsp56k_op_bra_2(cpustate, op, &cycle_count); } /* BRKc : 0000 0001 0001 cccc : A-52 */ else if ((op & 0xfff0) == 0x0110) { - size = dsp56k_op_brkcc(op, &cycle_count); + size = dsp56k_op_brkcc(cpustate, op, &cycle_count); } /* BScc : 0000 0111 --01 cccc xxxx xxxx xxxx xxxx : A-54 */ else if (((op & 0xff30) == 0x0710) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_bscc(op, op2, &cycle_count); + size = dsp56k_op_bscc(cpustate, op, op2, &cycle_count); } /* BScc : 0000 0111 RR00 cccc : A-54 */ else if ((op & 0xff30) == 0x0700) { - size = dsp56k_op_bscc_1(op, &cycle_count); + size = dsp56k_op_bscc_1(cpustate, op, &cycle_count); } /* BSR : 0000 0001 0011 10-- xxxx xxxx xxxx xxxx : A-56 */ else if (((op & 0xfffc) == 0x0138) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_bsr(op, op2, &cycle_count); + size = dsp56k_op_bsr(cpustate, op, op2, &cycle_count); } /* BSR : 0000 0001 0010 10RR : A-56 */ else if ((op & 0xfffc) == 0x0128) { - size = dsp56k_op_bsr_1(op, &cycle_count); + size = dsp56k_op_bsr_1(cpustate, op, &cycle_count); } /* CHKAAU : 0000 0000 0000 0100 : A-58 */ else if ((op & 0xffff) == 0x0004) { - size = dsp56k_op_chkaau(op, &cycle_count); + size = dsp56k_op_chkaau(cpustate, op, &cycle_count); } /* DEBUG : 0000 0000 0000 0001 : A-68 */ else if ((op & 0xffff) == 0x0001) { - size = dsp56k_op_debug(op, &cycle_count); + size = dsp56k_op_debug(cpustate, op, &cycle_count); } /* DEBUGcc : 0000 0000 0101 cccc : A-70 */ else if ((op & 0xfff0) == 0x0050) { - size = dsp56k_op_debugcc(op, &cycle_count); + size = dsp56k_op_debugcc(cpustate, op, &cycle_count); } /* DIV : 0001 0101 0--0 F1DD : A-76 */ /* WARNING : DOCS SAY THERE IS A PARALLEL MOVE HERE !!! */ else if ((op & 0xff94) == 0x1504) { - size = dsp56k_op_div(op, &cycle_count); + size = dsp56k_op_div(cpustate, op, &cycle_count); } /* DMAC : 0001 0101 10s1 FsQQ : A-80 */ else if ((op & 0xffd0) == 0x1590) { - size = dsp56k_op_dmac(op, &cycle_count); + size = dsp56k_op_dmac(cpustate, op, &cycle_count); } /* DO : 0000 0000 110- --RR xxxx xxxx xxxx xxxx : A-82 */ else if (((op & 0xffe0) == 0x00c0) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_do(op, op2, &cycle_count); + size = dsp56k_op_do(cpustate, op, op2, &cycle_count); } /* DO : 0000 1110 iiii iiii xxxx xxxx xxxx xxxx : A-82 */ else if (((op & 0xff00) == 0x0e00) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_do_1(op, op2, &cycle_count); + size = dsp56k_op_do_1(cpustate, op, op2, &cycle_count); } /* DO : 0000 0100 000D DDDD xxxx xxxx xxxx xxxx : A-82 */ else if (((op & 0xffe0) == 0x0400) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_do_2(op, op2, &cycle_count); + size = dsp56k_op_do_2(cpustate, op, op2, &cycle_count); } /* DO FOREVER : 0000 0000 0000 0010 xxxx xxxx xxxx xxxx : A-88 */ else if (((op & 0xffff) == 0x0002) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_doforever(op, op2, &cycle_count); + size = dsp56k_op_doforever(cpustate, op, op2, &cycle_count); } /* ENDDO : 0000 0000 0000 1001 : A-92 */ else if ((op & 0xffff) == 0x0009) { - size = dsp56k_op_enddo(op, &cycle_count); + size = dsp56k_op_enddo(cpustate, op, &cycle_count); } /* EXT : 0001 0101 0101 F010 : A-96 */ else if ((op & 0xfff7) == 0x1552) { - size = dsp56k_op_ext(op, &cycle_count); + size = dsp56k_op_ext(cpustate, op, &cycle_count); } /* ILLEGAL : 0000 0000 0000 1111 : A-98 */ else if ((op & 0xffff) == 0x000f) { - size = dsp56k_op_illegal(op, &cycle_count); + size = dsp56k_op_illegal(cpustate, op, &cycle_count); } /* IMAC : 0001 0101 1010 FQQQ : A-100 */ else if ((op & 0xfff0) == 0x15a0) { - size = dsp56k_op_imac(op, &cycle_count); + size = dsp56k_op_imac(cpustate, op, &cycle_count); } /* IMPY : 0001 0101 1000 FQQQ : A-102 */ else if ((op & 0xfff0) == 0x1580) { - size = dsp56k_op_impy(op, &cycle_count); + size = dsp56k_op_impy(cpustate, op, &cycle_count); } /* Jcc : 0000 0110 --11 cccc xxxx xxxx xxxx xxxx : A-108 */ else if (((op & 0xff30) == 0x0630) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_jcc(op, op2, &cycle_count); + size = dsp56k_op_jcc(cpustate, op, op2, &cycle_count); } /* Jcc : 0000 0110 RR10 cccc : A-108 */ else if ((op & 0xff30) == 0x0620 ) { - size = dsp56k_op_jcc_1(op, &cycle_count); + size = dsp56k_op_jcc_1(cpustate, op, &cycle_count); } /* JMP : 0000 0001 0011 01-- xxxx xxxx xxxx xxxx : A-110 */ else if (((op & 0xfffc) == 0x0134) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_jmp(op, op2, &cycle_count); + size = dsp56k_op_jmp(cpustate, op, op2, &cycle_count); } /* JMP : 0000 0001 0010 01RR : A-110 */ else if ((op & 0xfffc) == 0x0124) { - size = dsp56k_op_jmp_1(op, &cycle_count); + size = dsp56k_op_jmp_1(cpustate, op, &cycle_count); } /* JScc : 0000 0110 --01 cccc xxxx xxxx xxxx xxxx : A-112 */ else if (((op & 0xff30) == 0x0610) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_jscc(op, op2, &cycle_count); + size = dsp56k_op_jscc(cpustate, op, op2, &cycle_count); } /* JScc : 0000 0110 RR00 cccc : A-112 */ else if ((op & 0xff30) == 0x0600) { - size = dsp56k_op_jscc_1(op, &cycle_count); + size = dsp56k_op_jscc_1(cpustate, op, &cycle_count); } /* JSR : 0000 0001 0011 00-- xxxx xxxx xxxx xxxx : A-114 */ else if (((op & 0xfffc) == 0x0130) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_jsr(op, op2, &cycle_count); + size = dsp56k_op_jsr(cpustate, op, op2, &cycle_count); } /* JSR : 0000 1010 AAAA AAAA : A-114 */ else if ((op & 0xff00) == 0x0a00) { - size = dsp56k_op_jsr_1(op, &cycle_count); + size = dsp56k_op_jsr_1(cpustate, op, &cycle_count); } /* JSR : 0000 0001 0010 00RR : A-114 */ else if ((op & 0xfffc) == 0x0120) { - size = dsp56k_op_jsr_2(op, &cycle_count); + size = dsp56k_op_jsr_2(cpustate, op, &cycle_count); } /* LEA : 0000 0001 11TT MMRR : A-116 */ else if ((op & 0xffc0) == 0x01c0) { - size = dsp56k_op_lea(op, &cycle_count); + size = dsp56k_op_lea(cpustate, op, &cycle_count); } /* LEA : 0000 0001 10NN MMRR : A-116 */ else if ((op & 0xffc0) == 0x0180) { - size = dsp56k_op_lea_1(op, &cycle_count); + size = dsp56k_op_lea_1(cpustate, op, &cycle_count); } /* MAC(su,uu) : 0001 0101 1110 FsQQ : A-126 */ else if ((op & 0xfff0) == 0x15e0) { - size = dsp56k_op_macsuuu(op, &cycle_count); + size = dsp56k_op_macsuuu(cpustate, op, &cycle_count); } /* MOVE : 0000 0101 BBBB BBBB ---- HHHW 0001 0001 : A-128 */ else if (((op & 0xff00) == 0x0500) && ((op2 & 0x00ff) == 0x0011)) { - size = dsp56k_op_move_2(op, op2, &cycle_count); + size = dsp56k_op_move_2(cpustate, op, op2, &cycle_count); } /* MOVE(C) : 0011 1WDD DDD0 MMRR : A-144 */ else if ((op & 0xf810) == 0x3800) { - size = dsp56k_op_movec(op, &cycle_count); + size = dsp56k_op_movec(cpustate, op, &cycle_count); } /* MOVE(C) : 0011 1WDD DDD1 q0RR : A-144 */ else if ((op & 0xf814) == 0x3810) { - size = dsp56k_op_movec_1(op, &cycle_count); + size = dsp56k_op_movec_1(cpustate, op, &cycle_count); } /* MOVE(C) : 0011 1WDD DDD1 Z11- : A-144 */ else if ((op & 0xf816) == 0x3816) { - size = dsp56k_op_movec_2(op, &cycle_count); + size = dsp56k_op_movec_2(cpustate, op, &cycle_count); } /* MOVE(C) : 0011 1WDD DDD1 t10- xxxx xxxx xxxx xxxx : A-144 */ else if (((op & 0xf816) == 0x3814) && ((op2 & 0x0000) == 0x0000)) { - size = dsp56k_op_movec_3(op, op2, &cycle_count); + size = dsp56k_op_movec_3(cpustate, op, op2, &cycle_count); } /* MOVE(C) : 0010 10dd dddD DDDD : A-144 */ else if ((op & 0xfc00) == 0x2800) { - size = dsp56k_op_movec_4(op, &cycle_count); + size = dsp56k_op_movec_4(cpustate, op, &cycle_count); } /* MOVE(C) : 0000 0101 BBBB BBBB 0011 1WDD DDD0 ---- : A-144 */ else if (((op & 0xff00) == 0x0500) && ((op2 & 0xf810) == 0x3800)) { - size = dsp56k_op_movec_5(op, op2, &cycle_count); + size = dsp56k_op_movec_5(cpustate, op, op2, &cycle_count); } /* MOVE(I) : 0010 00DD BBBB BBBB : A-150 */ else if ((op & 0xfc00) == 0x2000) { - size = dsp56k_op_movei(op, &cycle_count); + size = dsp56k_op_movei(cpustate, op, &cycle_count); } /* MOVE(M) : 0000 001W RR0M MHHH : A-152 */ else if ((op & 0xfe20) == 0x0200) { - size = dsp56k_op_movem(op, &cycle_count); + size = dsp56k_op_movem(cpustate, op, &cycle_count); } /* MOVE(M) : 0000 001W RR11 mmRR : A-152 */ else if ((op & 0xfe30) == 0x0230) { - size = dsp56k_op_movem_1(op, &cycle_count); + size = dsp56k_op_movem_1(cpustate, op, &cycle_count); } /* MOVE(M) : 0000 0101 BBBB BBBB 0000 001W --0- -HHH : A-152 */ else if (((op & 0xff00) == 0x0500) && ((op2 & 0xfe20) == 0x0200)) { - size = dsp56k_op_movem_2(op, op2, &cycle_count); + size = dsp56k_op_movem_2(cpustate, op, op2, &cycle_count); } /* MOVE(P) : 0001 100W HH1p pppp : A-156 */ else if ((op & 0xfe20) == 0x1820) { - size = dsp56k_op_movep(op, &cycle_count); + size = dsp56k_op_movep(cpustate, op, &cycle_count); } /* MOVE(P) : 0000 110W RRmp pppp : A-156 */ else if ((op & 0xfe00) == 0x0c00) { - size = dsp56k_op_movep_1(op, &cycle_count); + size = dsp56k_op_movep_1(cpustate, op, &cycle_count); } /* MOVE(S) : 0001 100W HH0a aaaa : A-158 */ else if ((op & 0xfe20) == 0x1800) { - size = dsp56k_op_moves(op, &cycle_count); + size = dsp56k_op_moves(cpustate, op, &cycle_count); } /* MPY(su,uu) : 0001 0101 1100 FsQQ : A-164 */ else if ((op & 0xfff0) == 0x15c0) { - size = dsp56k_op_mpysuuu(op, &cycle_count); + size = dsp56k_op_mpysuuu(cpustate, op, &cycle_count); } /* NEGC : 0001 0101 0110 F000 : A-168 */ else if ((op & 0xfff7) == 0x1560) { - size = dsp56k_op_negc(op, &cycle_count); + size = dsp56k_op_negc(cpustate, op, &cycle_count); } /* NOP : 0000 0000 0000 0000 : A-170 */ else if ((op & 0xffff) == 0x0000) { - size = dsp56k_op_nop(op, &cycle_count); + size = dsp56k_op_nop(cpustate, op, &cycle_count); } /* NORM : 0001 0101 0010 F0RR : A-172 */ else if ((op & 0xfff4) == 0x1520) { - size = dsp56k_op_norm(op, &cycle_count); + size = dsp56k_op_norm(cpustate, op, &cycle_count); } /* ORI : 0001 1EE1 iiii iiii : A-178 */ else if ((op & 0xf900) == 0x1900) { - size = dsp56k_op_ori(op, &cycle_count); + size = dsp56k_op_ori(cpustate, op, &cycle_count); } /* REP : 0000 0000 111- --RR : A-180 */ else if ((op & 0xffe0) == 0x00e0) { - size = dsp56k_op_rep(op, &cycle_count); + size = dsp56k_op_rep(cpustate, op, &cycle_count); } /* REP : 0000 1111 iiii iiii : A-180 */ else if ((op & 0xff00) == 0x0f00) { - size = dsp56k_op_rep_1(op, &cycle_count); + size = dsp56k_op_rep_1(cpustate, op, &cycle_count); } /* REP : 0000 0100 001D DDDD : A-180 */ else if ((op & 0xffe0) == 0x0420) { - size = dsp56k_op_rep_2(op, &cycle_count); + size = dsp56k_op_rep_2(cpustate, op, &cycle_count); } /* REPcc : 0000 0001 0101 cccc : A-184 */ else if ((op & 0xfff0) == 0x0150) { - size = dsp56k_op_repcc(op, &cycle_count); + size = dsp56k_op_repcc(cpustate, op, &cycle_count); } /* RESET : 0000 0000 0000 1000 : A-186 */ else if ((op & 0xffff) == 0x0008) { - size = dsp56k_op_reset(op, &cycle_count); + size = dsp56k_op_reset(cpustate, op, &cycle_count); } /* RTI : 0000 0000 0000 0111 : A-194 */ else if ((op & 0xffff) == 0x0007) { - size = dsp56k_op_rti(op, &cycle_count); + size = dsp56k_op_rti(cpustate, op, &cycle_count); } /* RTS : 0000 0000 0000 0110 : A-196 */ else if ((op & 0xffff) == 0x0006) { - size = dsp56k_op_rts(op, &cycle_count); + size = dsp56k_op_rts(cpustate, op, &cycle_count); } /* STOP : 0000 0000 0000 1010 : A-200 */ else if ((op & 0xffff) == 0x000a) { - size = dsp56k_op_stop(op, &cycle_count); + size = dsp56k_op_stop(cpustate, op, &cycle_count); } /* SWAP : 0001 0101 0111 F001 : A-206 */ else if ((op & 0xfff7) == 0x1571) { - size = dsp56k_op_swap(op, &cycle_count); + size = dsp56k_op_swap(cpustate, op, &cycle_count); } /* SWI : 0000 0000 0000 0101 : A-208 */ else if ((op & 0xffff) == 0x0005) { - size = dsp56k_op_swi(op, &cycle_count); + size = dsp56k_op_swi(cpustate, op, &cycle_count); } /* Tcc : 0001 00cc ccTT Fh0h : A-210 */ else if ((op & 0xfc02) == 0x1000) { - size = dsp56k_op_tcc(op, &cycle_count); + size = dsp56k_op_tcc(cpustate, op, &cycle_count); } /* TFR(2) : 0001 0101 0000 F00J : A-214 */ else if ((op & 0xfff6) == 0x1500) { - size = dsp56k_op_tfr2(op, &cycle_count); + size = dsp56k_op_tfr2(cpustate, op, &cycle_count); } /* TFR(3) : 0010 01mW RRDD FHHH : A-216 */ else if ((op & 0xfc00) == 0x2400) { - size = dsp56k_op_tfr3(op, &cycle_count); + size = dsp56k_op_tfr3(cpustate, op, &cycle_count); } /* TST(2) : 0001 0101 0001 -1DD : A-220 */ else if ((op & 0xfff4) == 0x1514) { - size = dsp56k_op_tst2(op, &cycle_count); + size = dsp56k_op_tst2(cpustate, op, &cycle_count); } /* WAIT : 0000 0000 0000 1011 : A-222 */ else if ((op & 0xffff) == 0x000b) { - size = dsp56k_op_wait(op, &cycle_count); + size = dsp56k_op_wait(cpustate, op, &cycle_count); } /* ZERO : 0001 0101 0101 F000 : A-224 */ else if ((op & 0xfff7) == 0x1550) { - size = dsp56k_op_zero(op, &cycle_count); + size = dsp56k_op_zero(cpustate, op, &cycle_count); } @@ -1081,10 +1080,10 @@ static void execute_one(void) /* Must have been a good opcode */ PC += size; - dsp56k_process_loop(); - dsp56k_process_rep(size); + dsp56k_process_loop(cpustate); + dsp56k_process_rep(cpustate, size); - dsp56k_icount -= 4; /* Temporarily hard-coded at 4 clocks per opcode */ /* cycle_count */ + cpustate->icount -= 4; /* Temporarily hard-coded at 4 clocks per opcode */ /* cycle_count */ } @@ -1100,14 +1099,14 @@ static void execute_one(void) /* ADD : 011m mKKK 0rru Fuuu : A-22 */ /* SUB : 011m mKKK 0rru Fuuu : A-202 */ -static size_t dsp56k_op_addsub_2(const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) +static size_t dsp56k_op_addsub_2(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) { UINT64 useVal = 0; UINT8 op_type = OP_OTHER; typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_uuuuF_table(BITS(op_byte,0x0017), BITS(op_byte,0x0008), op_type, &S, &D); + decode_uuuuF_table(cpustate, BITS(op_byte,0x0017), BITS(op_byte,0x0008), op_type, &S, &D); /* If you gave an invalid operation type, presume it's a nop and move on with the parallel move */ if (op_type == OP_OTHER) @@ -1142,15 +1141,15 @@ static size_t dsp56k_op_addsub_2(const UINT16 op_byte, typed_pointer* d_register /* S L E U N Z V C */ /* * * * * * * * * */ /* TODO S, L, E, U, V, C */ - if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); - if (*((UINT64*)D.addr) == 0) Z_bit_set(1); + if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if (*((UINT64*)D.addr) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: + mv oscillator cycles */ return 1; } /* MAC : 011m mKKK 1xx0 F1QQ : A-122 */ -static size_t dsp56k_op_mac_1(const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) +static size_t dsp56k_op_mac_1(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) { INT64 opD = 0; INT64 result = 0; @@ -1162,7 +1161,7 @@ static size_t dsp56k_op_mac_1(const UINT16 op_byte, typed_pointer* d_register, U void* S1 = NULL; void* S2 = NULL; - decode_QQF_table(BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S1, &S2, &D); + decode_QQF_table(cpustate, BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S1, &S2, &D); /* Cast both values as being signed */ s1 = *((INT16*)S1); @@ -1193,15 +1192,15 @@ static size_t dsp56k_op_mac_1(const UINT16 op_byte, typed_pointer* d_register, U /* S L E U N Z V C */ /* * * * * * * * - */ /* TODO: S, L, E, V */ - if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(1); + if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: +mv oscillator cycles */ return 1; } /* MACR: 011m mKKK 1--1 F1QQ : A-124 */ -static size_t dsp56k_op_macr_1(const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) +static size_t dsp56k_op_macr_1(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * - */ @@ -1209,7 +1208,7 @@ static size_t dsp56k_op_macr_1(const UINT16 op_byte, typed_pointer* d_register, } /* MOVE : 011m mKKK 0rr1 0000 : A-128 */ -static size_t dsp56k_op_move_1(const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) +static size_t dsp56k_op_move_1(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - - - - - */ @@ -1217,7 +1216,7 @@ static size_t dsp56k_op_move_1(const UINT16 op_byte, typed_pointer* d_register, } /* MPY : 011m mKKK 1xx0 F0QQ : A-160 */ -static size_t dsp56k_op_mpy_1(const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) +static size_t dsp56k_op_mpy_1(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) { INT64 result = 0; @@ -1228,7 +1227,7 @@ static size_t dsp56k_op_mpy_1(const UINT16 op_byte, typed_pointer* d_register, U void* S1 = NULL; void* S2 = NULL; - decode_QQF_table(BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S1, &S2, &D); + decode_QQF_table(cpustate, BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S1, &S2, &D); /* Cast both values as being signed */ s1 = *((INT16*)S1); @@ -1247,15 +1246,15 @@ static size_t dsp56k_op_mpy_1(const UINT16 op_byte, typed_pointer* d_register, U /* S L E U N Z V C */ /* * * * * * * * - */ /* TODO: S, L, E, V */ - if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(1); + if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: +mv oscillator cycles */ return 1; } /* MPYR : 011m mKKK 1--1 F0QQ : A-162 */ -static size_t dsp56k_op_mpyr_1(const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) +static size_t dsp56k_op_mpyr_1(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * - */ @@ -1263,7 +1262,7 @@ static size_t dsp56k_op_mpyr_1(const UINT16 op_byte, typed_pointer* d_register, } /* TFR : 011m mKKK 0rr1 F0DD : A-212 */ -static size_t dsp56k_op_tfr_2(const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) +static size_t dsp56k_op_tfr_2(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -1271,7 +1270,7 @@ static size_t dsp56k_op_tfr_2(const UINT16 op_byte, typed_pointer* d_register, U } /* MPY : 0001 0110 RRDD FQQQ : A-160 */ -static size_t dsp56k_op_mpy_2(const UINT16 op_byte, UINT8* cycles) +static size_t dsp56k_op_mpy_2(dsp56k_core* cpustate, const UINT16 op_byte, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * - */ @@ -1279,7 +1278,7 @@ static size_t dsp56k_op_mpy_2(const UINT16 op_byte, UINT8* cycles) } /* MAC : 0001 0111 RRDD FQQQ : A-122 */ -static size_t dsp56k_op_mac_2(const UINT16 op_byte, UINT8* cycles) +static size_t dsp56k_op_mac_2(dsp56k_core* cpustate, const UINT16 op_byte, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * - */ @@ -1287,13 +1286,13 @@ static size_t dsp56k_op_mac_2(const UINT16 op_byte, UINT8* cycles) } /* CLR : .... .... 0000 F001 : A-60 */ -static size_t dsp56k_op_clr(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_clr(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer D = {NULL, DT_LONG_WORD}; typed_pointer clear = {NULL, DT_LONG_WORD}; UINT64 clear_val = U64(0x0000000000000000); - decode_F_table(BITS(op_byte,0x0008), &D); + decode_F_table(cpustate, BITS(op_byte,0x0008), &D); *p_accum = *((UINT64*)D.addr); @@ -1307,24 +1306,24 @@ static size_t dsp56k_op_clr(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * * * * * 0 - */ /* TODO - S&L */ - E_bit_set(0); - U_bit_set(1); - N_bit_set(0); - Z_bit_set(1); - V_bit_set(0); + E_bit_set(cpustate, 0); + U_bit_set(cpustate, 1); + N_bit_set(cpustate, 0); + Z_bit_set(cpustate, 1); + V_bit_set(cpustate, 0); cycles += 2; /* TODO: + mv oscillator clock cycles */ return 1; } /* ADD : .... .... 0000 FJJJ : A-22 */ -static size_t dsp56k_op_add(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_add(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { UINT64 addVal = 0; typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_JJJF_table(BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D); + decode_JJJF_table(cpustate, BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D); *p_accum = *((UINT64*)D.addr); @@ -1348,15 +1347,15 @@ static size_t dsp56k_op_add(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * * * * * * * */ /* TODO S, L, E, U, V, C */ - if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); - if (*((UINT64*)D.addr) == 0) Z_bit_set(1); + if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if (*((UINT64*)D.addr) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: + mv oscillator cycles */ return 1; } /* MOVE : .... .... 0001 0001 : A-128 */ -static size_t dsp56k_op_move(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_move(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* Equivalent to a nop with a parallel move */ /* These can't be used later. Hopefully compilers would pick this up. */ @@ -1372,12 +1371,12 @@ static size_t dsp56k_op_move(const UINT16 op_byte, typed_pointer* d_register, UI } /* TFR : .... .... 0001 FJJJ : A-212 */ -static size_t dsp56k_op_tfr(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_tfr(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_JJJF_table(BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D); + decode_JJJF_table(cpustate, BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D); *p_accum = *((UINT64*)D.addr); @@ -1394,7 +1393,7 @@ static size_t dsp56k_op_tfr(const UINT16 op_byte, typed_pointer* d_register, UIN } /* RND : .... .... 0010 F000 : A-188 */ -static size_t dsp56k_op_rnd(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_rnd(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * - */ @@ -1402,11 +1401,11 @@ static size_t dsp56k_op_rnd(const UINT16 op_byte, typed_pointer* d_register, UIN } /* TST : .... .... 0010 F001 : A-218 */ -static size_t dsp56k_op_tst(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_tst(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer D = {NULL, DT_LONG_WORD}; - decode_F_table(BITS(op_byte,0x0008), &D); + decode_F_table(cpustate, BITS(op_byte,0x0008), &D); *p_accum = *((UINT64*)D.addr); @@ -1416,20 +1415,20 @@ static size_t dsp56k_op_tst(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* 0 * * * * * 0 0 */ /* TODO: S, L, E, U */ - if ((*((UINT64*)D.addr)) & U64(0x0000008000000000)) N_bit_set(1); else N_bit_set(0); - if ((*((UINT64*)D.addr)) == 0) Z_bit_set(1); else Z_bit_set(0); - V_bit_set(0); - C_bit_set(0); + if ((*((UINT64*)D.addr)) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); else N_bit_set(cpustate, 0); + if ((*((UINT64*)D.addr)) == 0) Z_bit_set(cpustate, 1); else Z_bit_set(cpustate, 0); + V_bit_set(cpustate, 0); + C_bit_set(cpustate, 0); cycles += 2; /* TODO: + mv oscillator clock cycles */ return 1; } /* INC : .... .... 0010 F010 : A-104 */ -static size_t dsp56k_op_inc(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_inc(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op_byte,0x0008), &D); + decode_F_table(cpustate, BITS(op_byte,0x0008), &D); /* Save some data for the parallel move */ *p_accum = *((UINT64*)D.addr); @@ -1446,20 +1445,20 @@ static size_t dsp56k_op_inc(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * * * * * * * */ /* TODO: S, L, E, U, V, C */ - if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_bit_set(1); + if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: +mv oscillator cycles */ return 1; } /* INC24 : .... .... 0010 F011 : A-106 */ -static size_t dsp56k_op_inc24(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_inc24(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { UINT32 workBits24; typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op_byte,0x0008), &D); + decode_F_table(cpustate, BITS(op_byte,0x0008), &D); /* Save some data for the parallel move */ *p_accum = *((UINT64*)D.addr); @@ -1479,20 +1478,20 @@ static size_t dsp56k_op_inc24(const UINT16 op_byte, typed_pointer* d_register, U /* S L E U N Z V C */ /* * * * * * ? * * */ /* TODO: S, L, E, U, V, C */ - if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_bit_set(1); + if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: + mv oscillator clock cycles */ return 1; } /* OR : .... .... 0010 F1JJ : A-176 */ -static size_t dsp56k_op_or(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_or(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_JJF_table(BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S, &D); + decode_JJF_table(cpustate, BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S, &D); /* Save some data for the parallel move */ *p_accum = *((UINT64*)D.addr); @@ -1506,19 +1505,19 @@ static size_t dsp56k_op_or(const UINT16 op_byte, typed_pointer* d_register, UINT /* S L E U N Z V C */ /* * * - - ? ? 0 - */ /* TODO: S, L */ - if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_bit_set(1); else N_bit_set(0); - if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_bit_set(1); else Z_bit_set(0); - V_bit_set(0); + if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_bit_set(cpustate, 1); else N_bit_set(cpustate, 0); + if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_bit_set(cpustate, 1); else Z_bit_set(cpustate, 0); + V_bit_set(cpustate, 0); cycles += 2; /* TODO: + mv oscillator cycles */ return 1; } /* ASR : .... .... 0011 F000 : A-32 */ -static size_t dsp56k_op_asr(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_asr(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op_byte,0x0008), &D); + decode_F_table(cpustate, BITS(op_byte,0x0008), &D); *p_accum = *((UINT64*)D.addr); @@ -1537,17 +1536,17 @@ static size_t dsp56k_op_asr(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * * * * * 0 ? */ /* TODO: S, L, E, U */ - if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); - if (*((UINT64*)D.addr) == 0) Z_bit_set(1); - V_bit_set(0); - if (*p_accum & U64(0x0000000000000001)) C_bit_set(1); + if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if (*((UINT64*)D.addr) == 0) Z_bit_set(cpustate, 1); + V_bit_set(cpustate, 0); + if (*p_accum & U64(0x0000000000000001)) C_bit_set(cpustate, 1); cycles += 2; /* TODO: + mv oscillator cycles */ return 1; } /* ASL : .... .... 0011 F001 : A-28 */ -static size_t dsp56k_op_asl(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_asl(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * ? ? */ @@ -1558,10 +1557,10 @@ static size_t dsp56k_op_asl(const UINT16 op_byte, typed_pointer* d_register, UIN } /* LSR : .... .... 0011 F010 : A-120 */ -static size_t dsp56k_op_lsr(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_lsr(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op_byte,0x0008), &D); + decode_F_table(cpustate, BITS(op_byte,0x0008), &D); *p_accum = *((UINT64*)D.addr); @@ -1577,17 +1576,17 @@ static size_t dsp56k_op_lsr(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * - - ? ? 0 ? */ /* TODO: S, L */ - N_bit_set(0); - if (((PAIR64*)D.addr)->w.h == 0) Z_bit_set(1); - V_bit_set(0); - if (*p_accum & U64(0x0000000000010000)) C_bit_set(1); + N_bit_set(cpustate, 0); + if (((PAIR64*)D.addr)->w.h == 0) Z_bit_set(cpustate, 1); + V_bit_set(cpustate, 0); + if (*p_accum & U64(0x0000000000010000)) C_bit_set(cpustate, 1); cycles += 2; /* TODO: + mv oscillator cycles */ return 1; } /* LSL : .... .... 0011 F011 : A-118 */ -static size_t dsp56k_op_lsl(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_lsl(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - ? ? 0 ? */ @@ -1598,7 +1597,7 @@ static size_t dsp56k_op_lsl(const UINT16 op_byte, typed_pointer* d_register, UIN } /* EOR : .... .... 0011 F1JJ : A-94 */ -static size_t dsp56k_op_eor(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_eor(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - ? ? 0 - */ @@ -1608,7 +1607,7 @@ static size_t dsp56k_op_eor(const UINT16 op_byte, typed_pointer* d_register, UIN } /* SUBL : .... .... 0100 F001 : A-204 */ -static size_t dsp56k_op_subl(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_subl(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * ? * */ @@ -1618,7 +1617,7 @@ static size_t dsp56k_op_subl(const UINT16 op_byte, typed_pointer* d_register, UI } /* SUB : .... .... 0100 FJJJ : A-202 */ -static size_t dsp56k_op_sub(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_sub(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * * */ @@ -1626,7 +1625,7 @@ static size_t dsp56k_op_sub(const UINT16 op_byte, typed_pointer* d_register, UIN } /* CLR24 : .... .... 0101 F001 : A-62 */ -static size_t dsp56k_op_clr24(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_clr24(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * ? 0 - */ @@ -1635,7 +1634,7 @@ static size_t dsp56k_op_clr24(const UINT16 op_byte, typed_pointer* d_register, U } /* SBC : .... .... 0101 F01J : A-198 */ -static size_t dsp56k_op_sbc(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_sbc(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * * */ @@ -1643,7 +1642,7 @@ static size_t dsp56k_op_sbc(const UINT16 op_byte, typed_pointer* d_register, UIN } /* CMP : .... .... 0101 FJJJ : A-64 */ -static size_t dsp56k_op_cmp(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_cmp(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { UINT64 cmpVal = 0; UINT64 result = 0; @@ -1651,7 +1650,7 @@ static size_t dsp56k_op_cmp(const UINT16 op_byte, typed_pointer* d_register, UIN typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_JJJF_table(BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D); + decode_JJJF_table(cpustate, BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D); *p_accum = *((UINT64*)D.addr); @@ -1670,7 +1669,7 @@ static size_t dsp56k_op_cmp(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * * * * * * * */ /* TODO: S, L, E, U, N, V, C */ - if (result == 0) Z_bit_set(1); /* TODO: Do you clear it if this isn't true? */ + if (result == 0) Z_bit_set(cpustate, 1); /* TODO: Do you clear it if this isn't true? */ cycles += 2; /* TODO: + mv oscillator clock cycles */ @@ -1678,7 +1677,7 @@ static size_t dsp56k_op_cmp(const UINT16 op_byte, typed_pointer* d_register, UIN } /* NEG : .... .... 0110 F000 : A-166 */ -static size_t dsp56k_op_neg(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_neg(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * * */ @@ -1686,10 +1685,10 @@ static size_t dsp56k_op_neg(const UINT16 op_byte, typed_pointer* d_register, UIN } /* NOT : .... .... 0110 F001 : A-174 */ -static size_t dsp56k_op_not(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_not(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op_byte,0x0008), &D); + decode_F_table(cpustate, BITS(op_byte,0x0008), &D); *p_accum = *((UINT64*)D.addr); @@ -1702,16 +1701,16 @@ static size_t dsp56k_op_not(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * - - ? ? 0 - */ /* TODO: S?, L */ - if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_bit_set(1); - if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_bit_set(1); - V_bit_set(0); + if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_bit_set(cpustate, 1); + V_bit_set(cpustate, 0); cycles += 2; /* TODO: + mv oscillator cycles */ return 1; } /* DEC : .... .... 0110 F010 : A-72 */ -static size_t dsp56k_op_dec(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_dec(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * * */ @@ -1719,12 +1718,12 @@ static size_t dsp56k_op_dec(const UINT16 op_byte, typed_pointer* d_register, UIN } /* DEC24 : .... .... 0110 F011 : A-74 */ -static size_t dsp56k_op_dec24(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_dec24(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { UINT32 workBits24; typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op_byte,0x0008), &D); + decode_F_table(cpustate, BITS(op_byte,0x0008), &D); /* Save some data for the parallel move */ *p_accum = *((UINT64*)D.addr); @@ -1744,20 +1743,20 @@ static size_t dsp56k_op_dec24(const UINT16 op_byte, typed_pointer* d_register, U /* S L E U N Z V C */ /* * * * * * ? * * */ /* TODO: S, L, E, U, V, C */ - if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_bit_set(1); + if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: + mv oscillator clock cycles */ return 1; } /* AND : .... .... 0110 F1JJ : A-24 */ -static size_t dsp56k_op_and(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_and(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_JJF_table(BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S, &D); + decode_JJF_table(cpustate, BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S, &D); /* Save some data for the parallel move */ *p_accum = *((UINT64*)D.addr); @@ -1771,16 +1770,16 @@ static size_t dsp56k_op_and(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * - - ? ? 0 - */ /* TODO: S, L */ - if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_bit_set(1); - if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_bit_set(1); - V_bit_set(0); + if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_bit_set(cpustate, 1); + V_bit_set(cpustate, 0); cycles += 2; /* TODO: + mv oscillator cycles */ return 1; } /* ABS : .... .... 0111 F001 : A-18 */ -static size_t dsp56k_op_abs(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_abs(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * - */ @@ -1788,7 +1787,7 @@ static size_t dsp56k_op_abs(const UINT16 op_byte, typed_pointer* d_register, UIN } /* ROR : .... .... 0111 F010 : A-192 */ -static size_t dsp56k_op_ror(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_ror(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - ? ? 0 ? */ @@ -1799,7 +1798,7 @@ static size_t dsp56k_op_ror(const UINT16 op_byte, typed_pointer* d_register, UIN } /* ROL : .... .... 0111 F011 : A-190 */ -static size_t dsp56k_op_rol(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_rol(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - ? ? 0 ? */ @@ -1810,7 +1809,7 @@ static size_t dsp56k_op_rol(const UINT16 op_byte, typed_pointer* d_register, UIN } /* CMPM : .... .... 0111 FJJJ : A-66 */ -static size_t dsp56k_op_cmpm(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_cmpm(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { INT64 absS; INT64 absD; @@ -1819,7 +1818,7 @@ static size_t dsp56k_op_cmpm(const UINT16 op_byte, typed_pointer* d_register, UI typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_JJJF_table(BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D); + decode_JJJF_table(cpustate, BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D); *p_accum = *((UINT64*)D.addr); @@ -1862,15 +1861,15 @@ static size_t dsp56k_op_cmpm(const UINT16 op_byte, typed_pointer* d_register, UI /* S L E U N Z V C */ /* * * * * * * * * */ /* TODO: S, L, E, U, V, C */ - if ( (absResult) & U64(0x0000008000000000)) N_bit_set(1); else N_bit_set(0); - if (((absResult) & U64(0x000000ffffffffff)) == 0) Z_bit_set(1); else Z_bit_set(0); + if ( (absResult) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); else N_bit_set(cpustate, 0); + if (((absResult) & U64(0x000000ffffffffff)) == 0) Z_bit_set(cpustate, 1); else Z_bit_set(cpustate, 0); cycles += 2; /* TODO: +mv oscillator cycles */ return 1; } /* MPY : .... .... 1k00 FQQQ : A-160 -- CONFIRMED TYPO IN DOCS (HHHH vs HHHW) */ -static size_t dsp56k_op_mpy(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_mpy(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { UINT16 k = 0; INT64 result = 0; @@ -1882,7 +1881,7 @@ static size_t dsp56k_op_mpy(const UINT16 op_byte, typed_pointer* d_register, UIN void* S1 = NULL; void* S2 = NULL; - decode_QQQF_table(BITS(op_byte,0x0007), BITS(op_byte,0x0008), &S1, &S2, &D); + decode_QQQF_table(cpustate, BITS(op_byte,0x0007), BITS(op_byte,0x0008), &S1, &S2, &D); k = BITS(op_byte,0x0040); @@ -1902,15 +1901,15 @@ static size_t dsp56k_op_mpy(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * * * * * * - */ /* TODO: S, L, E, V */ - if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(1); + if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: +mv oscillator cycles */ return 1; } /* MPYR : .... .... 1k01 FQQQ : A-162 */ -static size_t dsp56k_op_mpyr(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_mpyr(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { /* S L E U N Z V C */ /* * * * * * * * - */ @@ -1918,7 +1917,7 @@ static size_t dsp56k_op_mpyr(const UINT16 op_byte, typed_pointer* d_register, UI } /* MAC : .... .... 1k10 FQQQ : A-122 */ -static size_t dsp56k_op_mac(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_mac(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { UINT16 k = 0; INT64 opD = 0; @@ -1931,7 +1930,7 @@ static size_t dsp56k_op_mac(const UINT16 op_byte, typed_pointer* d_register, UIN void* S1 = NULL; void* S2 = NULL; - decode_QQQF_table(BITS(op_byte,0x0007), BITS(op_byte,0x0008), &S1, &S2, &D); + decode_QQQF_table(cpustate, BITS(op_byte,0x0007), BITS(op_byte,0x0008), &S1, &S2, &D); k = BITS(op_byte,0x0040); @@ -1968,15 +1967,15 @@ static size_t dsp56k_op_mac(const UINT16 op_byte, typed_pointer* d_register, UIN /* S L E U N Z V C */ /* * * * * * * * - */ /* TODO: S, L, E, V */ - if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(1); + if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: +mv oscillator cycles */ return 1; } /* MACR : .... .... 1k11 FQQQ : A-124 -- DRAMA - rr vs xx (805) */ -static size_t dsp56k_op_macr(const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) +static size_t dsp56k_op_macr(dsp56k_core* cpustate, const UINT16 op_byte, typed_pointer* d_register, UINT64* p_accum, UINT8* cycles) { UINT16 k = 0; INT64 opD = 0; @@ -1989,7 +1988,7 @@ static size_t dsp56k_op_macr(const UINT16 op_byte, typed_pointer* d_register, UI void* S1 = NULL; void* S2 = NULL; - decode_QQQF_table(BITS(op_byte,0x0007), BITS(op_byte,0x0008), &S1, &S2, &D); + decode_QQQF_table(cpustate, BITS(op_byte,0x0007), BITS(op_byte,0x0008), &S1, &S2, &D); k = BITS(op_byte,0x0040); @@ -2031,8 +2030,8 @@ static size_t dsp56k_op_macr(const UINT16 op_byte, typed_pointer* d_register, UI /* S L E U N Z V C */ /* * * * * * * * - */ /* TODO: S, L, E, V */ - if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(1); + if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(cpustate, 1); cycles += 2; /* TODO: +mv oscillator cycles */ return 1; @@ -2044,7 +2043,7 @@ static size_t dsp56k_op_macr(const UINT16 op_byte, typed_pointer* d_register, UI /******************************/ /* ADC : 0001 0101 0000 F01J : A-20 */ -static size_t dsp56k_op_adc(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_adc(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * * * * * * * */ @@ -2052,7 +2051,7 @@ static size_t dsp56k_op_adc(const UINT16 op, UINT8* cycles) } /* ANDI : 0001 1EE0 iiii iiii : A-26 */ -static size_t dsp56k_op_andi(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_andi(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT16 immediate = BITS(op,0x00ff); @@ -2084,11 +2083,11 @@ static size_t dsp56k_op_andi(const UINT16 op, UINT8* cycles) } /* ASL4 : 0001 0101 0011 F001 : A-30 */ -static size_t dsp56k_op_asl4(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_asl4(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT64 p_accum = 0; typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op,0x0008), &D); + decode_F_table(cpustate, BITS(op,0x0008), &D); p_accum = *((UINT64*)D.addr); @@ -2101,21 +2100,21 @@ static size_t dsp56k_op_asl4(const UINT16 op, UINT8* cycles) /* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if bit 35 through 39 are not the same. */ /* C - Set if bit 36 of source operand is set. Cleared otherwise. */ - if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); else N_bit_set(0); - if (*((UINT64*)D.addr) == 0) Z_bit_set(1); else Z_bit_set(0); - if ( (*((UINT64*)D.addr) & U64(0x000000ff00000000)) != (p_accum & U64(0x000000ff00000000)) ) V_bit_set(1); else V_bit_set(0); - if (p_accum & U64(0x0000001000000000)) C_bit_set(1); else C_bit_set(0); + if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); else N_bit_set(cpustate, 0); + if (*((UINT64*)D.addr) == 0) Z_bit_set(cpustate, 1); else Z_bit_set(cpustate, 0); + if ( (*((UINT64*)D.addr) & U64(0x000000ff00000000)) != (p_accum & U64(0x000000ff00000000)) ) V_bit_set(cpustate, 1); else V_bit_set(cpustate, 0); + if (p_accum & U64(0x0000001000000000)) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); cycles += 2; return 1; } /* ASR4 : 0001 0101 0011 F000 : A-34 */ -static size_t dsp56k_op_asr4(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_asr4(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT64 p_accum = 0; typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op,0x0008), &D); + decode_F_table(cpustate, BITS(op,0x0008), &D); p_accum = *((UINT64*)D.addr); @@ -2132,22 +2131,22 @@ static size_t dsp56k_op_asr4(const UINT16 op, UINT8* cycles) /* - * * * * * 0 ? */ /* TODO: E, U */ /* C - Set if bit 3 of source operand is set. Cleared otherwise. */ - if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); else N_bit_set(0); - if (*((UINT64*)D.addr) == 0) Z_bit_set(1); else Z_bit_set(0); - V_bit_set(0); - if (p_accum & U64(0x0000000000000008)) C_bit_set(1); else C_bit_set(0); + if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); else N_bit_set(cpustate, 0); + if (*((UINT64*)D.addr) == 0) Z_bit_set(cpustate, 1); else Z_bit_set(cpustate, 0); + V_bit_set(cpustate, 0); + if (p_accum & U64(0x0000000000000008)) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); cycles += 2; return 1; } /* ASR16 : 0001 0101 0111 F000 : A-36 */ -static size_t dsp56k_op_asr16(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_asr16(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT64 backupVal; typed_pointer D = {NULL, DT_BYTE}; - decode_F_table(BITS(op,0x0008), &D); + decode_F_table(cpustate, BITS(op,0x0008), &D); backupVal = *((UINT64*)D.addr); @@ -2161,10 +2160,10 @@ static size_t dsp56k_op_asr16(const UINT16 op, UINT8* cycles) /* S L E U N Z V C */ /* - * * * * * 0 ? */ /* TODO: E, U */ - if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(1); else N_bit_set(0); - if (*((UINT64*)D.addr) == 0) Z_bit_set(1); else Z_bit_set(0); - V_bit_set(0); - if (backupVal & U64(0x0000000000008000)) C_bit_set(1); else C_bit_set(0); + if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); else N_bit_set(cpustate, 0); + if (*((UINT64*)D.addr) == 0) Z_bit_set(cpustate, 1); else Z_bit_set(cpustate, 0); + V_bit_set(cpustate, 0); + if (backupVal & U64(0x0000000000008000)) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); cycles += 2; return 1; @@ -2175,7 +2174,7 @@ static size_t dsp56k_op_asr16(const UINT16 op, UINT8* cycles) /* BFSET : 0001 0100 11Pp pppp BBB1 1000 iiii iiii : A-42 */ /* BFTSTH : 0001 0100 01Pp pppp BBB1 0000 iiii iiii : A-44 */ /* BFTSTL : 0001 0100 01Pp pppp BBB0 0000 iiii iiii : A-46 */ -static size_t dsp56k_op_bfop(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_bfop(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { UINT16 workAddr = 0x0000; UINT16 workingWord = 0x0000; @@ -2183,10 +2182,10 @@ static size_t dsp56k_op_bfop(const UINT16 op, const UINT16 op2, UINT8* cycles) typed_pointer tempTP = { NULL, DT_BYTE }; UINT16 iVal = op2 & 0x00ff; - decode_BBB_bitmask(BITS(op2,0xe000), &iVal); + decode_BBB_bitmask(cpustate, BITS(op2,0xe000), &iVal); - workAddr = assemble_address_from_Pppppp_table(BITS(OP,0x0020), BITS(OP,0x001f)); - previousValue = memory_read_word_16le(core.data, WORD(workAddr)); + workAddr = assemble_address_from_Pppppp_table(cpustate, BITS(OP,0x0020), BITS(OP,0x001f)); + previousValue = memory_read_word_16le(cpustate->data, WORD(workAddr)); workingWord = previousValue; switch(BITS(op2, 0x1f00)) @@ -2210,7 +2209,7 @@ static size_t dsp56k_op_bfop(const UINT16 op, const UINT16 op2, UINT8* cycles) tempTP.addr = &workingWord; tempTP.data_type = DT_WORD; - SetDataMemoryValue(tempTP, WORD(workAddr)); + SetDataMemoryValue(cpustate, tempTP, WORD(workAddr)); /* S L E U N Z V C */ /* - * - - - - - ? */ @@ -2218,15 +2217,15 @@ static size_t dsp56k_op_bfop(const UINT16 op, const UINT16 op2, UINT8* cycles) switch(BITS(op2, 0x1f00)) { case 0x12: /* BFCHG */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x18: /* BFSET */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x10: /* BFTSTH */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x00: /* BFTSTL */ - if ((iVal & previousValue) == 0x0000) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == 0x0000) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; } cycles += 4; /* TODO: + mvb oscillator clock cycles */ @@ -2238,7 +2237,7 @@ static size_t dsp56k_op_bfop(const UINT16 op, const UINT16 op2, UINT8* cycles) /* BFSET : 0001 0100 101- --RR BBB1 1000 iiii iiii : A-42 */ /* BFTSTH : 0001 0100 001- --RR BBB1 0000 iiii iiii : A-44 */ /* BFTSTL : 0001 0100 001- --RR BBB0 0000 iiii iiii : A-46 */ -static size_t dsp56k_op_bfop_1(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_bfop_1(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { UINT16 workAddr = 0x0000; UINT16 workingWord = 0x0000; @@ -2247,12 +2246,12 @@ static size_t dsp56k_op_bfop_1(const UINT16 op, const UINT16 op2, UINT8* cycles) typed_pointer tempTP = { NULL, DT_BYTE }; UINT16 iVal = op2 & 0x00ff; - decode_BBB_bitmask(BITS(op2,0xe000), &iVal); + decode_BBB_bitmask(cpustate, BITS(op2,0xe000), &iVal); - decode_RR_table(BITS(op,0x0003), &R); + decode_RR_table(cpustate, BITS(op,0x0003), &R); workAddr = *((UINT16*)R.addr); - previousValue = memory_read_word_16le(core.data, WORD(workAddr)); + previousValue = memory_read_word_16le(cpustate->data, WORD(workAddr)); workingWord = previousValue; switch(BITS(op2, 0x1f00)) @@ -2276,7 +2275,7 @@ static size_t dsp56k_op_bfop_1(const UINT16 op, const UINT16 op2, UINT8* cycles) tempTP.addr = &workingWord; tempTP.data_type = DT_WORD; - SetDataMemoryValue(tempTP, WORD(workAddr)); + SetDataMemoryValue(cpustate, tempTP, WORD(workAddr)); /* S L E U N Z V C */ /* - * - - - - - ? */ @@ -2284,15 +2283,15 @@ static size_t dsp56k_op_bfop_1(const UINT16 op, const UINT16 op2, UINT8* cycles) switch(BITS(op2, 0x1f00)) { case 0x12: /* BFCHG */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x18: /* BFSET */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x10: /* BFTSTH */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x00: /* BFTSTL */ - if ((iVal & previousValue) == 0x0000) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == 0x0000) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; } cycles += 4; /* TODO: + mvb oscillator clock cycles */ @@ -2304,7 +2303,7 @@ static size_t dsp56k_op_bfop_1(const UINT16 op, const UINT16 op2, UINT8* cycles) /* BFSET : 0001 0100 100D DDDD BBB1 1000 iiii iiii : A-42 */ /* BFTSTH : 0001 0100 000D DDDD BBB1 0000 iiii iiii : A-44 */ /* BFTSTL : 0001 0100 000D DDDD BBB0 0000 iiii iiii : A-46 */ -static size_t dsp56k_op_bfop_2(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_bfop_2(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { UINT16 workingWord = 0x0000; UINT16 previousValue = 0x0000; @@ -2312,8 +2311,8 @@ static size_t dsp56k_op_bfop_2(const UINT16 op, const UINT16 op2, UINT8* cycles) UINT16 iVal = op2 & 0x00ff; typed_pointer S = { NULL, DT_BYTE }; - decode_BBB_bitmask(BITS(op2,0xe000), &iVal); - decode_DDDDD_table(BITS(op,0x001f), &S); + decode_BBB_bitmask(cpustate, BITS(op2,0xe000), &iVal); + decode_DDDDD_table(cpustate, BITS(op,0x001f), &S); /* A & B are special */ if (S.data_type == DT_LONG_WORD) @@ -2354,15 +2353,15 @@ static size_t dsp56k_op_bfop_2(const UINT16 op, const UINT16 op2, UINT8* cycles) switch(BITS(op2, 0x1f00)) { case 0x12: /* BFCHG */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x18: /* BFSET */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x10: /* BFTSTH */ - if ((iVal & previousValue) == iVal) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == iVal) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; case 0x00: /* BFTSTL */ - if ((iVal & previousValue) == 0x0000) C_bit_set(1); else C_bit_set(0); break; + if ((iVal & previousValue) == 0x0000) C_bit_set(cpustate, 1); else C_bit_set(cpustate, 0); break; } cycles += 4; /* TODO: + mvb oscillator clock cycles */ @@ -2370,9 +2369,9 @@ static size_t dsp56k_op_bfop_2(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* Bcc : 0000 0111 --11 cccc xxxx xxxx xxxx xxxx : A-48 */ -static size_t dsp56k_op_bcc(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_bcc(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { - int shouldBranch = decode_cccc_table(BITS(op,0x000f)); + int shouldBranch = decode_cccc_table(cpustate, BITS(op,0x000f)); if (shouldBranch) { @@ -2380,7 +2379,7 @@ static size_t dsp56k_op_bcc(const UINT16 op, const UINT16 op2, UINT8* cycles) PC += 2; - core.ppc = PC; + cpustate->ppc = PC; PC += offset; cycles += 4; @@ -2398,17 +2397,17 @@ static size_t dsp56k_op_bcc(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* Bcc : 0010 11cc ccee eeee : A-48 */ -static size_t dsp56k_op_bcc_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_bcc_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { - int shouldBranch = decode_cccc_table(BITS(op,0x03c0)); + int shouldBranch = decode_cccc_table(cpustate, BITS(op,0x03c0)); if (shouldBranch) { - INT16 offset = (INT16)assemble_address_from_6bit_signed_relative_short_address(BITS(op,0x003f)); + INT16 offset = (INT16)assemble_address_from_6bit_signed_relative_short_address(cpustate, BITS(op,0x003f)); PC += 1; - core.ppc = PC; + cpustate->ppc = PC; PC += offset; cycles += 4; @@ -2426,7 +2425,7 @@ static size_t dsp56k_op_bcc_1(const UINT16 op, UINT8* cycles) } /* Bcc : 0000 0111 RR10 cccc : A-48 */ -static size_t dsp56k_op_bcc_2(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_bcc_2(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2434,7 +2433,7 @@ static size_t dsp56k_op_bcc_2(const UINT16 op, UINT8* cycles) } /* BRA : 0000 0001 0011 11-- xxxx xxxx xxxx xxxx : A-50 */ -static size_t dsp56k_op_bra(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_bra(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2442,7 +2441,7 @@ static size_t dsp56k_op_bra(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* BRA : 0000 1011 aaaa aaaa : A-50 */ -static size_t dsp56k_op_bra_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_bra_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* 8 bit immediate, relative offset */ INT8 branchOffset = (INT8)BITS(op,0x00ff); @@ -2451,7 +2450,7 @@ static size_t dsp56k_op_bra_1(const UINT16 op, UINT8* cycles) PC += 1; /* Jump */ - core.ppc = PC; + cpustate->ppc = PC; PC += branchOffset; /* S L E U N Z V C */ @@ -2461,7 +2460,7 @@ static size_t dsp56k_op_bra_1(const UINT16 op, UINT8* cycles) } /* BRA : 0000 0001 0010 11RR : A-50 */ -static size_t dsp56k_op_bra_2(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_bra_2(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2469,14 +2468,14 @@ static size_t dsp56k_op_bra_2(const UINT16 op, UINT8* cycles) } /* BRKcc : 0000 0001 0001 cccc : A-52 */ -static size_t dsp56k_op_brkcc(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_brkcc(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { - int shouldBreak = decode_cccc_table(BITS(op,0x000f)); + int shouldBreak = decode_cccc_table(cpustate, BITS(op,0x000f)); if (shouldBreak) { /* TODO: I think this PC = LA thing is off-by-1, but it's working this way because its consistently so */ - core.ppc = PC; + cpustate->ppc = PC; PC = LA; SR = SSL; /* TODO: A-83. I believe only the Loop Flag and Forever Flag come back here. */ @@ -2501,9 +2500,9 @@ static size_t dsp56k_op_brkcc(const UINT16 op, UINT8* cycles) } /* BScc : 0000 0111 --01 cccc xxxx xxxx xxxx xxxx : A-54 */ -static size_t dsp56k_op_bscc(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_bscc(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { - int shouldBranch = decode_cccc_table(BITS(op,0x000f)); + int shouldBranch = decode_cccc_table(cpustate, BITS(op,0x000f)); if (shouldBranch) { @@ -2516,7 +2515,7 @@ static size_t dsp56k_op_bscc(const UINT16 op, const UINT16 op2, UINT8* cycles) SSL = SR; /* Change */ - core.ppc = PC; + cpustate->ppc = PC; PC = PC + (INT16)op2; } @@ -2527,7 +2526,7 @@ static size_t dsp56k_op_bscc(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* BScc : 0000 0111 RR00 cccc : A-54 */ -static size_t dsp56k_op_bscc_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_bscc_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2535,7 +2534,7 @@ static size_t dsp56k_op_bscc_1(const UINT16 op, UINT8* cycles) } /* BSR : 0000 0001 0011 10-- xxxx xxxx xxxx xxxx : A-56 */ -static size_t dsp56k_op_bsr(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_bsr(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { /* The PC Contains the address of the next instruction */ PC += 2; @@ -2546,7 +2545,7 @@ static size_t dsp56k_op_bsr(const UINT16 op, const UINT16 op2, UINT8* cycles) SSL = SR; /* Change */ - core.ppc = PC; + cpustate->ppc = PC; PC = PC + (INT16)op2; /* S L E U N Z V C */ @@ -2556,7 +2555,7 @@ static size_t dsp56k_op_bsr(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* BSR : 0000 0001 0010 10RR : A-56 */ -static size_t dsp56k_op_bsr_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_bsr_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2564,7 +2563,7 @@ static size_t dsp56k_op_bsr_1(const UINT16 op, UINT8* cycles) } /* CHKAAU : 0000 0000 0000 0100 : A-58 */ -static size_t dsp56k_op_chkaau(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_chkaau(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - ? ? ? - */ @@ -2578,7 +2577,7 @@ static size_t dsp56k_op_chkaau(const UINT16 op, UINT8* cycles) } /* DEBUG : 0000 0000 0000 0001 : A-68 */ -static size_t dsp56k_op_debug(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_debug(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2586,7 +2585,7 @@ static size_t dsp56k_op_debug(const UINT16 op, UINT8* cycles) } /* DEBUGcc : 0000 0000 0101 cccc : A-70 */ -static size_t dsp56k_op_debugcc(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_debugcc(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2595,7 +2594,7 @@ static size_t dsp56k_op_debugcc(const UINT16 op, UINT8* cycles) /* DIV : 0001 0101 0--0 F1DD : A-76 */ /* WARNING : DOCS SAY THERE IS A PARALLEL MOVE HERE !!! */ -static size_t dsp56k_op_div(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_div(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * - - - - ? ? */ @@ -2606,7 +2605,7 @@ static size_t dsp56k_op_div(const UINT16 op, UINT8* cycles) } /* DMAC : 0001 0101 10s1 FsQQ : A-80 */ -static size_t dsp56k_op_dmac(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_dmac(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * * * * * * - */ @@ -2614,7 +2613,7 @@ static size_t dsp56k_op_dmac(const UINT16 op, UINT8* cycles) } /* DO : 0000 0000 110- --RR xxxx xxxx xxxx xxxx : A-82 */ -static size_t dsp56k_op_do(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_do(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { /* S L E U N Z V C */ /* - * - - - - - - */ @@ -2622,7 +2621,7 @@ static size_t dsp56k_op_do(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* DO : 0000 1110 iiii iiii xxxx xxxx xxxx xxxx : A-82 */ -static size_t dsp56k_op_do_1(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_do_1(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { UINT8 iValue = BITS(op,0x00ff); @@ -2644,7 +2643,7 @@ static size_t dsp56k_op_do_1(const UINT16 op, const UINT16 op2, UINT8* cycles) /* Third instruction cycle */ - LF_bit_set(1); + LF_bit_set(cpustate, 1); /* S L E U N Z V C */ @@ -2662,11 +2661,11 @@ static size_t dsp56k_op_do_1(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* DO : 0000 0100 000D DDDD xxxx xxxx xxxx xxxx : A-82 */ -static size_t dsp56k_op_do_2(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_do_2(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { UINT16 lValue = 0x0000; typed_pointer S = {NULL, DT_BYTE}; - decode_DDDDD_table(BITS(op,0x001f), &S); + decode_DDDDD_table(cpustate, BITS(op,0x001f), &S); /* TODO: Does not work for sources A&B - Fix per the docs */ lValue = *((UINT16*)S.addr); @@ -2697,7 +2696,7 @@ static size_t dsp56k_op_do_2(const UINT16 op, const UINT16 op2, UINT8* cycles) /* Third instruction cycle */ - LF_bit_set(1); + LF_bit_set(cpustate, 1); /* S L E U N Z V C */ @@ -2715,7 +2714,7 @@ static size_t dsp56k_op_do_2(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* DO FOREVER : 0000 0000 0000 0010 xxxx xxxx xxxx xxxx : A-88 */ -static size_t dsp56k_op_doforever(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_doforever(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { /* First instruction cycle */ SP++; @@ -2729,8 +2728,8 @@ static size_t dsp56k_op_doforever(const UINT16 op, const UINT16 op2, UINT8* cycl LA = PC + 2 + op2; /* Third instruction cycle */ - LF_bit_set(1); - FV_bit_set(1); + LF_bit_set(cpustate, 1); + FV_bit_set(cpustate, 1); /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2739,7 +2738,7 @@ static size_t dsp56k_op_doforever(const UINT16 op, const UINT16 op2, UINT8* cycl } /* ENDDO : 0000 0000 0000 1001 : A-92 */ -static size_t dsp56k_op_enddo(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_enddo(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2747,7 +2746,7 @@ static size_t dsp56k_op_enddo(const UINT16 op, UINT8* cycles) } /* EXT : 0001 0101 0101 F010 : A-96 */ -static size_t dsp56k_op_ext(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_ext(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * * * * * * - */ @@ -2755,7 +2754,7 @@ static size_t dsp56k_op_ext(const UINT16 op, UINT8* cycles) } /* ILLEGAL : 0000 0000 0000 1111 : A-98 */ -static size_t dsp56k_op_illegal(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_illegal(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2763,7 +2762,7 @@ static size_t dsp56k_op_illegal(const UINT16 op, UINT8* cycles) } /* IMAC : 0001 0101 1010 FQQQ : A-100 */ -static size_t dsp56k_op_imac(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_imac(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * ? ? * ? ? - */ @@ -2774,7 +2773,7 @@ static size_t dsp56k_op_imac(const UINT16 op, UINT8* cycles) } /* IMPY : 0001 0101 1000 FQQQ : A-102 */ -static size_t dsp56k_op_impy(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_impy(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * ? ? * ? ? - */ @@ -2785,7 +2784,7 @@ static size_t dsp56k_op_impy(const UINT16 op, UINT8* cycles) } /* Jcc : 0000 0110 --11 cccc xxxx xxxx xxxx xxxx : A-108 */ -static size_t dsp56k_op_jcc(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_jcc(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2793,7 +2792,7 @@ static size_t dsp56k_op_jcc(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* Jcc : 0000 0110 RR10 cccc : A-108 */ -static size_t dsp56k_op_jcc_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_jcc_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2801,9 +2800,9 @@ static size_t dsp56k_op_jcc_1(const UINT16 op, UINT8* cycles) } /* JMP : 0000 0001 0011 01-- xxxx xxxx xxxx xxxx : A-110 */ -static size_t dsp56k_op_jmp(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_jmp(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { - core.ppc = PC; + cpustate->ppc = PC; PC = op2; /* S L E U N Z V C */ @@ -2814,12 +2813,12 @@ static size_t dsp56k_op_jmp(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* JMP : 0000 0001 0010 01RR : A-110 */ -static size_t dsp56k_op_jmp_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_jmp_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { typed_pointer R = { NULL, DT_BYTE }; - decode_RR_table(BITS(op,0x0003), &R); + decode_RR_table(cpustate, BITS(op,0x0003), &R); - core.ppc = PC; + cpustate->ppc = PC; PC = *((UINT16*)R.addr); /* S L E U N Z V C */ @@ -2830,9 +2829,9 @@ static size_t dsp56k_op_jmp_1(const UINT16 op, UINT8* cycles) } /* JScc : 0000 0110 --01 cccc xxxx xxxx xxxx xxxx : A-112 */ -static size_t dsp56k_op_jscc(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_jscc(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { - int shouldJump = decode_cccc_table(BITS(op,0x000f)); + int shouldJump = decode_cccc_table(cpustate, BITS(op,0x000f)); if(shouldJump) { @@ -2846,7 +2845,7 @@ static size_t dsp56k_op_jscc(const UINT16 op, const UINT16 op2, UINT8* cycles) SSH = PC; SSL = SR; - core.ppc = PC; + cpustate->ppc = PC; PC = branchOffset; cycles += 4; /* TODO: +jx oscillator clock cycles */ @@ -2864,7 +2863,7 @@ static size_t dsp56k_op_jscc(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* JScc : 0000 0110 RR00 cccc : A-112 */ -static size_t dsp56k_op_jscc_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_jscc_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2872,7 +2871,7 @@ static size_t dsp56k_op_jscc_1(const UINT16 op, UINT8* cycles) } /* JSR : 0000 0001 0011 00-- xxxx xxxx xxxx xxxx : A-114 */ -static size_t dsp56k_op_jsr(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_jsr(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { /* TODO: It says "signed" absolute offset. Weird. */ UINT16 branchOffset = op2; @@ -2884,7 +2883,7 @@ static size_t dsp56k_op_jsr(const UINT16 op, const UINT16 op2, UINT8* cycles) SSH = PC; SSL = SR; - core.ppc = PC; + cpustate->ppc = PC; PC = branchOffset; /* S L E U N Z V C */ @@ -2894,7 +2893,7 @@ static size_t dsp56k_op_jsr(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* JSR : 0000 1010 AAAA AAAA : A-114 */ -static size_t dsp56k_op_jsr_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_jsr_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2902,7 +2901,7 @@ static size_t dsp56k_op_jsr_1(const UINT16 op, UINT8* cycles) } /* JSR : 0000 0001 0010 00RR : A-114 */ -static size_t dsp56k_op_jsr_2(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_jsr_2(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2910,13 +2909,13 @@ static size_t dsp56k_op_jsr_2(const UINT16 op, UINT8* cycles) } /* LEA : 0000 0001 11TT MMRR : A-116 */ -static size_t dsp56k_op_lea(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_lea(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT16 ea = 0; UINT16 *rX = NULL; UINT16 *nX = NULL; typed_pointer D = {NULL, DT_BYTE}; - decode_TT_table(BITS(op,0x0030), &D); + decode_TT_table(cpustate, BITS(op,0x0030), &D); /* TODO: change the execute_mm_functions to return values. Maybe */ /* Because this calculation isn't applied, do everything locally */ @@ -2946,7 +2945,7 @@ static size_t dsp56k_op_lea(const UINT16 op, UINT8* cycles) } /* LEA : 0000 0001 10NN MMRR : A-116 */ -static size_t dsp56k_op_lea_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_lea_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -2954,7 +2953,7 @@ static size_t dsp56k_op_lea_1(const UINT16 op, UINT8* cycles) } /* MAC(su,uu) : 0001 0101 1110 FsQQ : A-126 */ -static size_t dsp56k_op_macsuuu(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_macsuuu(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT8 s = 0; INT64 result = 0; @@ -2963,7 +2962,7 @@ static size_t dsp56k_op_macsuuu(const UINT16 op, UINT8* cycles) void* S1 = NULL; void* S2 = NULL; - decode_QQF_special_table(BITS(op,0x0003), BITS(op,0x0008), &S1, &S2, &D); + decode_QQF_special_table(cpustate, BITS(op,0x0003), BITS(op,0x0008), &S1, &S2, &D); s = BITS(op,0x0004); @@ -2989,15 +2988,15 @@ static size_t dsp56k_op_macsuuu(const UINT16 op, UINT8* cycles) /* S L E U N Z V C */ /* - * * * * * * - */ /* TODO: L, E, U, V */ - if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(1); - if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(1); + if ( *((UINT64*)D) & U64(0x0000008000000000)) N_bit_set(cpustate, 1); + if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_bit_set(cpustate, 1); cycles += 2; return 1; } /* MOVE : 0000 0101 BBBB BBBB ---- HHHW 0001 0001 : A-128 */ -static size_t dsp56k_op_move_2(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_move_2(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - - - - - */ @@ -3005,20 +3004,20 @@ static size_t dsp56k_op_move_2(const UINT16 op, const UINT16 op2, UINT8* cycles) } /* MOVE(C) : 0011 1WDD DDD0 MMRR : A-144 */ -static size_t dsp56k_op_movec(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movec(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT8 W; typed_pointer R = { NULL, DT_BYTE }; typed_pointer SD = { NULL, DT_BYTE }; W = BITS(op,0x0400); - decode_DDDDD_table(BITS(op,0x03e0), &SD); - decode_RR_table(BITS(op,0x0003), &R); + decode_DDDDD_table(cpustate, BITS(op,0x03e0), &SD); + decode_RR_table(cpustate, BITS(op,0x0003), &R); if (W) { /* Write D */ - UINT16 value = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr))) ; + UINT16 value = memory_read_word_16le(cpustate->data, WORD(*((UINT16*)R.addr))) ; typed_pointer temp_src = { &value, DT_WORD }; SetDestinationValue(temp_src, SD); } @@ -3026,10 +3025,10 @@ static size_t dsp56k_op_movec(const UINT16 op, UINT8* cycles) { /* Read S */ UINT16 dataMemOffset = *((UINT16*)R.addr); - SetDataMemoryValue(SD, WORD(dataMemOffset)); + SetDataMemoryValue(cpustate, SD, WORD(dataMemOffset)); } - execute_MM_table(BITS(op,0x0003), BITS(op,0x000c)); + execute_MM_table(cpustate, BITS(op,0x0003), BITS(op,0x000c)); /* S L E U N Z V C */ /* * ? ? ? ? ? ? ? */ @@ -3047,20 +3046,20 @@ static size_t dsp56k_op_movec(const UINT16 op, UINT8* cycles) } /* MOVE(C) : 0011 1WDD DDD1 q0RR : A-144 */ -static size_t dsp56k_op_movec_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movec_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT8 W; UINT16 memOffset; typed_pointer SD = {NULL, DT_BYTE}; W = BITS(op,0x0400); - decode_DDDDD_table(BITS(op,0x03e0), &SD); - memOffset = execute_q_table(BITS(op,0x0003), BITS(op,0x0008)); + decode_DDDDD_table(cpustate, BITS(op,0x03e0), &SD); + memOffset = execute_q_table(cpustate, BITS(op,0x0003), BITS(op,0x0008)); if (W) { /* Write D */ - UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset)); + UINT16 tempData = memory_read_word_16le(cpustate->data, WORD(memOffset)); typed_pointer temp_src = { (void*)&tempData, DT_WORD }; SetDestinationValue(temp_src, SD); } @@ -3069,7 +3068,7 @@ static size_t dsp56k_op_movec_1(const UINT16 op, UINT8* cycles) /* Read S */ UINT16 tempData = *((UINT16*)SD.addr); typed_pointer temp_src = { (void*)&tempData, DT_WORD }; - SetDataMemoryValue(temp_src, WORD(memOffset)); + SetDataMemoryValue(cpustate, temp_src, WORD(memOffset)); } /* S L E U N Z V C */ @@ -3088,7 +3087,7 @@ static size_t dsp56k_op_movec_1(const UINT16 op, UINT8* cycles) } /* MOVE(C) : 0011 1WDD DDD1 Z11- : A-144 */ -static size_t dsp56k_op_movec_2(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movec_2(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT8 W; UINT16 memOffset; @@ -3096,15 +3095,15 @@ static size_t dsp56k_op_movec_2(const UINT16 op, UINT8* cycles) typed_pointer XMemOffset = {NULL, DT_BYTE}; W = BITS(op,0x0400); - decode_Z_table(BITS(op,0x0008), &XMemOffset); - decode_DDDDD_table(BITS(op,0x03e0), &SD); + decode_Z_table(cpustate, BITS(op,0x0008), &XMemOffset); + decode_DDDDD_table(cpustate, BITS(op,0x03e0), &SD); memOffset = *((UINT16*)XMemOffset.addr); if (W) { /* Write D */ - UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset)); + UINT16 tempData = memory_read_word_16le(cpustate->data, WORD(memOffset)); typed_pointer temp_src = { (void*)&tempData, DT_WORD }; SetDestinationValue(temp_src, SD); } @@ -3113,7 +3112,7 @@ static size_t dsp56k_op_movec_2(const UINT16 op, UINT8* cycles) /* Read S */ UINT16 tempData = *((UINT16*)SD.addr); typed_pointer temp_src = { (void*)&tempData, DT_WORD }; - SetDataMemoryValue(temp_src, WORD(memOffset)); + SetDataMemoryValue(cpustate, temp_src, WORD(memOffset)); } @@ -3133,7 +3132,7 @@ static size_t dsp56k_op_movec_2(const UINT16 op, UINT8* cycles) } /* MOVE(C) : 0011 1WDD DDD1 t10- xxxx xxxx xxxx xxxx : A-144 */ -static size_t dsp56k_op_movec_3(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_movec_3(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { UINT8 W; UINT8 t; @@ -3141,7 +3140,7 @@ static size_t dsp56k_op_movec_3(const UINT16 op, const UINT16 op2, UINT8* cycles W = BITS(op,0x0400); t = BITS(op,0x0008); - decode_DDDDD_table(BITS(op,0x03e0), &SD); + decode_DDDDD_table(cpustate, BITS(op,0x03e0), &SD); if (W) { @@ -3155,7 +3154,7 @@ static size_t dsp56k_op_movec_3(const UINT16 op, const UINT16 op2, UINT8* cycles else { /* 16-bit long address */ - UINT16 tempD = memory_read_word_16le(core.data, WORD(op2)); + UINT16 tempD = memory_read_word_16le(cpustate->data, WORD(op2)); typed_pointer tempTP = {&tempD, DT_WORD}; SetDestinationValue(tempTP, SD); } @@ -3171,7 +3170,7 @@ static size_t dsp56k_op_movec_3(const UINT16 op, const UINT16 op2, UINT8* cycles else { /* 16-bit long address */ - SetDataMemoryValue(SD, WORD(op2)); + SetDataMemoryValue(cpustate, SD, WORD(op2)); } } @@ -3191,13 +3190,13 @@ static size_t dsp56k_op_movec_3(const UINT16 op, const UINT16 op2, UINT8* cycles } /* MOVE(C) : 0010 10dd dddD DDDD : A-144 */ -static size_t dsp56k_op_movec_4(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movec_4(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_DDDDD_table(BITS(op,0x03e0), &S); - decode_DDDDD_table(BITS(op,0x001f), &D); + decode_DDDDD_table(cpustate, BITS(op,0x03e0), &S); + decode_DDDDD_table(cpustate, BITS(op,0x001f), &D); SetDestinationValue(S, D); @@ -3217,7 +3216,7 @@ static size_t dsp56k_op_movec_4(const UINT16 op, UINT8* cycles) } /* MOVE(C) : 0000 0101 BBBB BBBB 0011 1WDD DDD0 ---- : A-144 */ -static size_t dsp56k_op_movec_5(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_movec_5(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { INT8 xx; UINT8 W; @@ -3226,14 +3225,14 @@ static size_t dsp56k_op_movec_5(const UINT16 op, const UINT16 op2, UINT8* cycles xx = (INT8)(op & 0x00ff); W = BITS(op2,0x0400); - decode_DDDDD_table(BITS(op2,0x03e0), &SD); + decode_DDDDD_table(cpustate, BITS(op2,0x03e0), &SD); memOffset = R2 + (INT16)xx; if (W) { /* Write D */ - UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset)); + UINT16 tempData = memory_read_word_16le(cpustate->data, WORD(memOffset)); typed_pointer temp_src = { (void*)&tempData, DT_WORD }; SetDestinationValue(temp_src, SD); } @@ -3242,7 +3241,7 @@ static size_t dsp56k_op_movec_5(const UINT16 op, const UINT16 op2, UINT8* cycles /* Read S */ UINT16 tempData = *((UINT16*)SD.addr); typed_pointer temp_src = { (void*)&tempData, DT_WORD }; - SetDataMemoryValue(temp_src, WORD(memOffset)); + SetDataMemoryValue(cpustate, temp_src, WORD(memOffset)); } /* S L E U N Z V C */ @@ -3261,7 +3260,7 @@ static size_t dsp56k_op_movec_5(const UINT16 op, const UINT16 op2, UINT8* cycles } /* MOVE(I) : 0010 00DD BBBB BBBB : A-150 */ -static size_t dsp56k_op_movei(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movei(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { typed_pointer D = {NULL, DT_BYTE}; typed_pointer immTP = {NULL, DT_BYTE}; @@ -3271,7 +3270,7 @@ static size_t dsp56k_op_movei(const UINT16 op, UINT8* cycles) immTP.addr = &immediateSignExtended; immTP.data_type = DT_WORD; - decode_DD_table(BITS(op,0x0300), &D); + decode_DD_table(cpustate, BITS(op,0x0300), &D); SetDestinationValue(immTP, D); @@ -3282,21 +3281,21 @@ static size_t dsp56k_op_movei(const UINT16 op, UINT8* cycles) } /* MOVE(M) : 0000 001W RR0M MHHH : A-152 */ -static size_t dsp56k_op_movem(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movem(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT8 W; typed_pointer R = { NULL, DT_BYTE }; typed_pointer SD = { NULL, DT_BYTE }; W = BITS(op,0x0100); - decode_RR_table(BITS(op,0x00c0), &R); - decode_HHH_table(BITS(op,0x0007), &SD); + decode_RR_table(cpustate, BITS(op,0x00c0), &R); + decode_HHH_table(cpustate, BITS(op,0x0007), &SD); if (W) { /* Read from Program Memory */ typed_pointer data; - UINT16 ldata = memory_read_word_16le(core.program, WORD(*((UINT16*)R.addr))); + UINT16 ldata = memory_read_word_16le(cpustate->program, WORD(*((UINT16*)R.addr))); data.addr = &ldata; data.data_type = DT_WORD; @@ -3305,10 +3304,10 @@ static size_t dsp56k_op_movem(const UINT16 op, UINT8* cycles) else { /* Write to Program Memory */ - SetProgramMemoryValue(SD, WORD(*((UINT16*)R.addr))) ; + SetProgramMemoryValue(cpustate, SD, WORD(*((UINT16*)R.addr))) ; } - execute_MM_table(BITS(op,0x00c0), BITS(op,0x0018)); + execute_MM_table(cpustate, BITS(op,0x00c0), BITS(op,0x0018)); /* S L E U N Z V C */ /* * * - - - - - - */ @@ -3318,7 +3317,7 @@ static size_t dsp56k_op_movem(const UINT16 op, UINT8* cycles) } /* MOVE(M) : 0000 001W RR11 mmRR : A-152 */ -static size_t dsp56k_op_movem_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movem_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - - - - - */ @@ -3326,7 +3325,7 @@ static size_t dsp56k_op_movem_1(const UINT16 op, UINT8* cycles) } /* MOVE(M) : 0000 0101 BBBB BBBB 0000 001W --0- -HHH : A-152 */ -static size_t dsp56k_op_movem_2(const UINT16 op, const UINT16 op2, UINT8* cycles) +static size_t dsp56k_op_movem_2(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - - - - - */ @@ -3334,23 +3333,23 @@ static size_t dsp56k_op_movem_2(const UINT16 op, const UINT16 op2, UINT8* cycles } /* MOVE(P) : 0001 100W HH1p pppp : A-156 */ -static size_t dsp56k_op_movep(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movep(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { UINT16 W; UINT16 pp; typed_pointer SD = {NULL, DT_BYTE}; - decode_HH_table(BITS(op,0x00c0), &SD); + decode_HH_table(cpustate, BITS(op,0x00c0), &SD); /* TODO: Special cases for A & B */ pp = op & 0x001f; - pp = assemble_address_from_IO_short_address(pp); + pp = assemble_address_from_IO_short_address(cpustate, pp); W = BITS(op,0x0100); if (W) { - UINT16 data = memory_read_word_16le(core.data, WORD(pp)); + UINT16 data = memory_read_word_16le(cpustate->data, WORD(pp)); typed_pointer tempTP; tempTP.addr = &data; @@ -3360,7 +3359,7 @@ static size_t dsp56k_op_movep(const UINT16 op, UINT8* cycles) } else { - SetDataMemoryValue(SD, WORD(pp)); + SetDataMemoryValue(cpustate, SD, WORD(pp)); } /* S L E U N Z V C */ @@ -3372,30 +3371,30 @@ static size_t dsp56k_op_movep(const UINT16 op, UINT8* cycles) } /* MOVE(P) : 0000 110W RRmp pppp : A-156 */ -static size_t dsp56k_op_movep_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_movep_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { // X:<Rx> and X:<pp> UINT16 W; UINT16 pp; typed_pointer SD = {NULL, DT_BYTE}; - decode_RR_table(BITS(op,0x00c0), &SD); + decode_RR_table(cpustate, BITS(op,0x00c0), &SD); pp = op & 0x001f; - pp = assemble_address_from_IO_short_address(pp); + pp = assemble_address_from_IO_short_address(cpustate, pp); W = BITS(OP,0x0100); /* A little different than most W if's - opposite read and write */ if (W) { - UINT16 data = memory_read_word_16le(core.data, WORD(*((UINT16*)SD.addr))); + UINT16 data = memory_read_word_16le(cpustate->data, WORD(*((UINT16*)SD.addr))); typed_pointer tempTP; tempTP.addr = &data; tempTP.data_type = DT_WORD; - SetDataMemoryValue(tempTP, WORD(pp)); + SetDataMemoryValue(cpustate, tempTP, WORD(pp)); } else { @@ -3404,7 +3403,7 @@ static size_t dsp56k_op_movep_1(const UINT16 op, UINT8* cycles) } // Postincrement - execute_m_table(BITS(OP,0x00c0), BITS(OP,0x0020)); + execute_m_table(cpustate, BITS(OP,0x00c0), BITS(OP,0x0020)); /* S L E U N Z V C */ /* * * - - - - - - */ @@ -3414,7 +3413,7 @@ static size_t dsp56k_op_movep_1(const UINT16 op, UINT8* cycles) } /* MOVE(S) : 0001 100W HH0a aaaa : A-158 */ -static size_t dsp56k_op_moves(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_moves(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - - - - - */ @@ -3422,7 +3421,7 @@ static size_t dsp56k_op_moves(const UINT16 op, UINT8* cycles) } /* MPY(su,uu) : 0001 0101 1100 FsQQ : A-164 */ -static size_t dsp56k_op_mpysuuu(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_mpysuuu(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * * * * * * - */ @@ -3430,7 +3429,7 @@ static size_t dsp56k_op_mpysuuu(const UINT16 op, UINT8* cycles) } /* NEGC : 0001 0101 0110 F000 : A-168 */ -static size_t dsp56k_op_negc(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_negc(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * * * * * * * */ @@ -3438,7 +3437,7 @@ static size_t dsp56k_op_negc(const UINT16 op, UINT8* cycles) } /* NOP : 0000 0000 0000 0000 : A-170 */ -static size_t dsp56k_op_nop(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_nop(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -3446,7 +3445,7 @@ static size_t dsp56k_op_nop(const UINT16 op, UINT8* cycles) } /* NORM : 0001 0101 0010 F0RR : A-172 */ -static size_t dsp56k_op_norm(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_norm(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * * * * * ? - */ @@ -3456,7 +3455,7 @@ static size_t dsp56k_op_norm(const UINT16 op, UINT8* cycles) } /* ORI : 0001 1EE1 iiii iiii : A-178 */ -static size_t dsp56k_op_ori(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_ori(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - ? ? ? ? ? ? ? */ @@ -3466,7 +3465,7 @@ static size_t dsp56k_op_ori(const UINT16 op, UINT8* cycles) } /* REP : 0000 0000 111- --RR : A-180 */ -static size_t dsp56k_op_rep(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_rep(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * - - - - - - */ @@ -3474,7 +3473,7 @@ static size_t dsp56k_op_rep(const UINT16 op, UINT8* cycles) } /* REP : 0000 1111 iiii iiii : A-180 */ -static size_t dsp56k_op_rep_1(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_rep_1(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* TODO: This is non-interruptable, probably have to turn off interrupts here */ UINT16 iVal = op & 0x00ff; @@ -3484,8 +3483,8 @@ static size_t dsp56k_op_rep_1(const UINT16 op, UINT8* cycles) TEMP = LC; LC = iVal; - core.repFlag = 1; - core.repAddr = PC + WORD(1); + cpustate->repFlag = 1; + cpustate->repAddr = PC + WORD(1); cycles += 4; /* TODO: + mv oscillator clock cycles */ } @@ -3502,12 +3501,12 @@ static size_t dsp56k_op_rep_1(const UINT16 op, UINT8* cycles) } /* REP : 0000 0100 001D DDDD : A-180 */ -static size_t dsp56k_op_rep_2(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_rep_2(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* TODO: This is non-interruptable, probably have to turn off interrupts here */ UINT16 repValue; typed_pointer D = {NULL, DT_BYTE}; - decode_DDDDD_table(BITS(op,0x001f), &D); + decode_DDDDD_table(cpustate, BITS(op,0x001f), &D); /* TODO: handle special A&B source cases */ if (D.addr == &A || D.addr == &B) @@ -3520,8 +3519,8 @@ static size_t dsp56k_op_rep_2(const UINT16 op, UINT8* cycles) TEMP = LC; LC = repValue; - core.repFlag = 1; - core.repAddr = PC + WORD(1); + cpustate->repFlag = 1; + cpustate->repAddr = PC + WORD(1); cycles += 4; /* TODO: + mv oscillator clock cycles */ } @@ -3537,7 +3536,7 @@ static size_t dsp56k_op_rep_2(const UINT16 op, UINT8* cycles) } /* REPcc : 0000 0001 0101 cccc : A-184 */ -static size_t dsp56k_op_repcc(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_repcc(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -3545,7 +3544,7 @@ static size_t dsp56k_op_repcc(const UINT16 op, UINT8* cycles) } /* RESET : 0000 0000 0000 1000 : A-186 */ -static size_t dsp56k_op_reset(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_reset(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -3553,9 +3552,9 @@ static size_t dsp56k_op_reset(const UINT16 op, UINT8* cycles) } /* RTI : 0000 0000 0000 0111 : A-194 */ -static size_t dsp56k_op_rti(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_rti(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { - core.ppc = PC; + cpustate->ppc = PC; PC = SSH; SR = SSL; @@ -3569,10 +3568,10 @@ static size_t dsp56k_op_rti(const UINT16 op, UINT8* cycles) } /* RTS : 0000 0000 0000 0110 : A-196 */ -static size_t dsp56k_op_rts(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_rts(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* Pop */ - core.ppc = PC; + cpustate->ppc = PC; PC = SSH; /* SR = SSL; The status register is not affected. */ @@ -3586,7 +3585,7 @@ static size_t dsp56k_op_rts(const UINT16 op, UINT8* cycles) } /* STOP : 0000 0000 0000 1010 : A-200 */ -static size_t dsp56k_op_stop(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_stop(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -3594,7 +3593,7 @@ static size_t dsp56k_op_stop(const UINT16 op, UINT8* cycles) } /* SWAP : 0001 0101 0111 F001 : A-206 */ -static size_t dsp56k_op_swap(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_swap(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -3602,7 +3601,7 @@ static size_t dsp56k_op_swap(const UINT16 op, UINT8* cycles) } /* SWI : 0000 0000 0000 0101 : A-208 */ -static size_t dsp56k_op_swi(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_swi(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -3610,9 +3609,9 @@ static size_t dsp56k_op_swi(const UINT16 op, UINT8* cycles) } /* Tcc : 0001 00cc ccTT Fh0h : A-210 */ -static size_t dsp56k_op_tcc(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_tcc(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { - int shouldTransfer = decode_cccc_table(BITS(op,0x03c0)); + int shouldTransfer = decode_cccc_table(cpustate, BITS(op,0x03c0)); if (shouldTransfer) { @@ -3621,11 +3620,11 @@ static size_t dsp56k_op_tcc(const UINT16 op, UINT8* cycles) typed_pointer S2 = {&R0, DT_WORD}; typed_pointer D2 = {NULL, DT_BYTE}; - decode_h0hF_table(BITS(op,0x0007),BITS(op,0x0008), &S, &D); + decode_h0hF_table(cpustate, BITS(op,0x0007),BITS(op,0x0008), &S, &D); SetDestinationValue(S, D); /* TODO: What's up with that A,A* thing in the docs? Can you only ignore the R0->RX transfer if you do an A,A? */ - decode_RR_table(BITS(op,0x0030), &D2); /* TT is the same as RR */ + decode_RR_table(cpustate, BITS(op,0x0030), &D2); /* TT is the same as RR */ SetDestinationValue(S2, D2); } @@ -3636,7 +3635,7 @@ static size_t dsp56k_op_tcc(const UINT16 op, UINT8* cycles) } /* TFR(2) : 0001 0101 0000 F00J : A-214 */ -static size_t dsp56k_op_tfr2(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_tfr2(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * - - - - - - */ @@ -3644,7 +3643,7 @@ static size_t dsp56k_op_tfr2(const UINT16 op, UINT8* cycles) } /* TFR(3) : 0010 01mW RRDD FHHH : A-216 */ -static size_t dsp56k_op_tfr3(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_tfr3(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* * * - - - - - - */ @@ -3652,28 +3651,28 @@ static size_t dsp56k_op_tfr3(const UINT16 op, UINT8* cycles) } /* TST(2) : 0001 0101 0001 -1DD : A-220 */ -static size_t dsp56k_op_tst2(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_tst2(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { typed_pointer D = {NULL, DT_BYTE}; - decode_DD_table(BITS(op,0x0003), &D); + decode_DD_table(cpustate, BITS(op,0x0003), &D); /* S L E U N Z V C */ /* - * * * * * 0 0 */ /* (L,E,U should be set to 0) */ - L_bit_set(0); - E_bit_set(0); - // U_bit_set(0); /* TODO: Conflicting opinions? "Set if unnormalized." Documentation is weird (A&B?) */ - if ((*((UINT16*)D.addr)) & 0x8000) N_bit_set(1); else N_bit_set(0); - if ((*((UINT16*)D.addr)) == 0x0000) Z_bit_set(1); else Z_bit_set(0); - // V_bit_set(0); /* TODO: Verify as well! */ - C_bit_set(0); + L_bit_set(cpustate, 0); + E_bit_set(cpustate, 0); + // U_bit_set(cpustate, 0); /* TODO: Conflicting opinions? "Set if unnormalized." Documentation is weird (A&B?) */ + if ((*((UINT16*)D.addr)) & 0x8000) N_bit_set(cpustate, 1); else N_bit_set(cpustate, 0); + if ((*((UINT16*)D.addr)) == 0x0000) Z_bit_set(cpustate, 1); else Z_bit_set(cpustate, 0); + // V_bit_set(cpustate, 0); /* TODO: Verify as well! */ + C_bit_set(cpustate, 0); cycles += 2; return 1; } /* WAIT : 0000 0000 0000 1011 : A-222 */ -static size_t dsp56k_op_wait(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_wait(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - - - - - - - - */ @@ -3681,7 +3680,7 @@ static size_t dsp56k_op_wait(const UINT16 op, UINT8* cycles) } /* ZERO : 0001 0101 0101 F000 : A-224 */ -static size_t dsp56k_op_zero(const UINT16 op, UINT8* cycles) +static size_t dsp56k_op_zero(dsp56k_core* cpustate, const UINT16 op, UINT8* cycles) { /* S L E U N Z V C */ /* - * * * * * * - */ @@ -3693,7 +3692,7 @@ static size_t dsp56k_op_zero(const UINT16 op, UINT8* cycles) /*************************************************************************** Table decoding ***************************************************************************/ -static UINT16 decode_BBB_bitmask(UINT16 BBB, UINT16 *iVal) +static UINT16 decode_BBB_bitmask(dsp56k_core* cpustate, UINT16 BBB, UINT16 *iVal) { UINT16 retVal = 0x0000; @@ -3707,7 +3706,7 @@ static UINT16 decode_BBB_bitmask(UINT16 BBB, UINT16 *iVal) return retVal; } -static int decode_cccc_table(UINT16 cccc) +static int decode_cccc_table(dsp56k_core* cpustate, UINT16 cccc) { int retVal = 0; @@ -3715,28 +3714,28 @@ static int decode_cccc_table(UINT16 cccc) switch (cccc) { /* Arranged according to mnemonic table - not decoding table */ - case 0x0: if( C_bit() == 0) retVal = 1; break; // cc(hs) - case 0x8: if( C_bit() == 1) retVal = 1; break; // cs(lo) - case 0x5: if( E_bit() == 0) retVal = 1; break; // ec - case 0xa: if( Z_bit() == 1) retVal = 1; break; // eq - case 0xd: if( E_bit() == 1) retVal = 1; break; // es - case 0x1: if((N_bit() ^ V_bit()) == 0) retVal = 1; break; // ge - case 0x7: if((Z_bit() | (N_bit() ^ V_bit())) == 0) retVal = 1; break; // gt - case 0x6: if( L_bit() == 0) retVal = 1; break; // lc - case 0xf: if((Z_bit() | (N_bit() ^ V_bit())) == 1) retVal = 1; break; // le - case 0xe: if( L_bit() == 1) retVal = 1; break; // ls - case 0x9: if((N_bit() ^ V_bit()) == 1) retVal = 1; break; // lt - case 0xb: if( N_bit() == 1) retVal = 1; break; // mi - case 0x2: if( Z_bit() == 0) retVal = 1; break; // ne - case 0xc: if((Z_bit() | ((!U_bit()) & (!E_bit()))) == 1) retVal = 1; break; // nr - case 0x3: if( N_bit() == 0) retVal = 1; break; // pl - case 0x4: if((Z_bit() | ((!U_bit()) & (!E_bit()))) == 0) retVal = 1; break; // nn + case 0x0: if( C_bit(cpustate) == 0) retVal = 1; break; // cc(hs) + case 0x8: if( C_bit(cpustate) == 1) retVal = 1; break; // cs(lo) + case 0x5: if( E_bit(cpustate) == 0) retVal = 1; break; // ec + case 0xa: if( Z_bit(cpustate) == 1) retVal = 1; break; // eq + case 0xd: if( E_bit(cpustate) == 1) retVal = 1; break; // es + case 0x1: if((N_bit(cpustate) ^ V_bit(cpustate)) == 0) retVal = 1; break; // ge + case 0x7: if((Z_bit(cpustate) | (N_bit(cpustate) ^ V_bit(cpustate))) == 0) retVal = 1; break; // gt + case 0x6: if( L_bit(cpustate) == 0) retVal = 1; break; // lc + case 0xf: if((Z_bit(cpustate) | (N_bit(cpustate) ^ V_bit(cpustate))) == 1) retVal = 1; break; // le + case 0xe: if( L_bit(cpustate) == 1) retVal = 1; break; // ls + case 0x9: if((N_bit(cpustate) ^ V_bit(cpustate)) == 1) retVal = 1; break; // lt + case 0xb: if( N_bit(cpustate) == 1) retVal = 1; break; // mi + case 0x2: if( Z_bit(cpustate) == 0) retVal = 1; break; // ne + case 0xc: if((Z_bit(cpustate) | ((!U_bit(cpustate)) & (!E_bit(cpustate)))) == 1) retVal = 1; break; // nr + case 0x3: if( N_bit(cpustate) == 0) retVal = 1; break; // pl + case 0x4: if((Z_bit(cpustate) | ((!U_bit(cpustate)) & (!E_bit(cpustate)))) == 0) retVal = 1; break; // nn } return retVal; } -static void decode_DDDDD_table(UINT16 DDDDD, typed_pointer* ret) +static void decode_DDDDD_table(dsp56k_core* cpustate, UINT16 DDDDD, typed_pointer* ret) { switch(DDDDD) { @@ -3776,7 +3775,7 @@ static void decode_DDDDD_table(UINT16 DDDDD, typed_pointer* ret) } } -static void decode_DD_table(UINT16 DD, typed_pointer* ret) +static void decode_DD_table(dsp56k_core* cpustate, UINT16 DD, typed_pointer* ret) { switch(DD) { @@ -3787,7 +3786,7 @@ static void decode_DD_table(UINT16 DD, typed_pointer* ret) } } -static void decode_F_table(UINT16 F, typed_pointer* ret) +static void decode_F_table(dsp56k_core* cpustate, UINT16 F, typed_pointer* ret) { switch(F) { @@ -3796,7 +3795,7 @@ static void decode_F_table(UINT16 F, typed_pointer* ret) } } -static void decode_h0hF_table(UINT16 h0h, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret) +static void decode_h0hF_table(dsp56k_core* cpustate, UINT16 h0h, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret) { UINT16 switchVal = (h0h << 1) | F ; @@ -3813,7 +3812,7 @@ static void decode_h0hF_table(UINT16 h0h, UINT16 F, typed_pointer* src_ret, type } } -static void decode_HH_table(UINT16 HH, typed_pointer* ret) +static void decode_HH_table(dsp56k_core* cpustate, UINT16 HH, typed_pointer* ret) { switch(HH) { @@ -3824,7 +3823,7 @@ static void decode_HH_table(UINT16 HH, typed_pointer* ret) } } -static void decode_HHH_table(UINT16 HHH, typed_pointer* ret) +static void decode_HHH_table(dsp56k_core* cpustate, UINT16 HHH, typed_pointer* ret) { switch(HHH) { @@ -3839,7 +3838,7 @@ static void decode_HHH_table(UINT16 HHH, typed_pointer* ret) } } -static void decode_IIII_table(UINT16 IIII, typed_pointer* src_ret, typed_pointer* dst_ret, void *working) +static void decode_IIII_table(dsp56k_core* cpustate, UINT16 IIII, typed_pointer* src_ret, typed_pointer* dst_ret, void *working) { void *opposite = 0x00 ; @@ -3865,7 +3864,7 @@ static void decode_IIII_table(UINT16 IIII, typed_pointer* src_ret, typed_pointer } } -static void decode_JJJF_table(UINT16 JJJ, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret) +static void decode_JJJF_table(dsp56k_core* cpustate, UINT16 JJJ, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret) { UINT16 switchVal = (JJJ << 1) | F ; @@ -3888,7 +3887,7 @@ static void decode_JJJF_table(UINT16 JJJ, UINT16 F, typed_pointer* src_ret, type } } -static void decode_JJF_table(UINT16 JJ, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret) +static void decode_JJF_table(dsp56k_core* cpustate, UINT16 JJ, UINT16 F, typed_pointer* src_ret, typed_pointer* dst_ret) { UINT16 switchVal = (JJ << 1) | F ; @@ -3905,7 +3904,7 @@ static void decode_JJF_table(UINT16 JJ, UINT16 F, typed_pointer* src_ret, typed_ } } -static void decode_KKK_table(UINT16 KKK, typed_pointer* dst_ret1, typed_pointer* dst_ret2, void* working) +static void decode_KKK_table(dsp56k_core* cpustate, UINT16 KKK, typed_pointer* dst_ret1, typed_pointer* dst_ret2, void* working) { void *opposite = 0x00 ; @@ -3925,7 +3924,7 @@ static void decode_KKK_table(UINT16 KKK, typed_pointer* dst_ret1, typed_pointer* } } -static void decode_QQF_table(UINT16 QQ, UINT16 F, void **S1, void **S2, void **D) +static void decode_QQF_table(dsp56k_core* cpustate, UINT16 QQ, UINT16 F, void **S1, void **S2, void **D) { UINT16 switchVal = (QQ << 1) | F ; @@ -3942,7 +3941,7 @@ static void decode_QQF_table(UINT16 QQ, UINT16 F, void **S1, void **S2, void **D } } -static void decode_QQF_special_table(UINT16 QQ, UINT16 F, void **S1, void **S2, void **D) +static void decode_QQF_special_table(dsp56k_core* cpustate, UINT16 QQ, UINT16 F, void **S1, void **S2, void **D) { UINT16 switchVal = (QQ << 1) | F ; @@ -3959,7 +3958,7 @@ static void decode_QQF_special_table(UINT16 QQ, UINT16 F, void **S1, void **S2, } } -static void decode_QQQF_table(UINT16 QQQ, UINT16 F, void **S1, void **S2, void **D) +static void decode_QQQF_table(dsp56k_core* cpustate, UINT16 QQQ, UINT16 F, void **S1, void **S2, void **D) { UINT16 switchVal = (QQQ << 1) | F; @@ -3984,7 +3983,7 @@ static void decode_QQQF_table(UINT16 QQQ, UINT16 F, void **S1, void **S2, void * } } -static void decode_RR_table(UINT16 RR, typed_pointer* ret) +static void decode_RR_table(dsp56k_core* cpustate, UINT16 RR, typed_pointer* ret) { switch(RR) { @@ -3995,7 +3994,7 @@ static void decode_RR_table(UINT16 RR, typed_pointer* ret) } } -static void decode_TT_table(UINT16 TT, typed_pointer* ret) +static void decode_TT_table(dsp56k_core* cpustate, UINT16 TT, typed_pointer* ret) { switch(TT) { @@ -4007,7 +4006,7 @@ static void decode_TT_table(UINT16 TT, typed_pointer* ret) } -static void decode_uuuuF_table(UINT16 uuuu, UINT16 F, UINT8 add_sub_other, typed_pointer* src_ret, typed_pointer* dst_ret) +static void decode_uuuuF_table(dsp56k_core* cpustate, UINT16 uuuu, UINT16 F, UINT8 add_sub_other, typed_pointer* src_ret, typed_pointer* dst_ret) { UINT16 switchVal = (uuuu << 1) | F; @@ -4081,7 +4080,7 @@ static void decode_uuuuF_table(UINT16 uuuu, UINT16 F, UINT8 add_sub_other, typed } } -static void decode_Z_table(UINT16 Z, typed_pointer* ret) +static void decode_Z_table(dsp56k_core* cpustate, UINT16 Z, typed_pointer* ret) { switch(Z) { @@ -4091,7 +4090,7 @@ static void decode_Z_table(UINT16 Z, typed_pointer* ret) } } -static void execute_m_table(int x, UINT16 m) +static void execute_m_table(dsp56k_core* cpustate, int x, UINT16 m) { UINT16 *rX = 0x00 ; UINT16 *nX = 0x00 ; @@ -4111,7 +4110,7 @@ static void execute_m_table(int x, UINT16 m) } } -static void execute_mm_table(UINT16 rnum, UINT16 mm) +static void execute_mm_table(dsp56k_core* cpustate, UINT16 rnum, UINT16 mm) { UINT16 *rX = NULL; UINT16 *nX = NULL; @@ -4133,7 +4132,7 @@ static void execute_mm_table(UINT16 rnum, UINT16 mm) } } -static void execute_MM_table(UINT16 rnum, UINT16 MM) +static void execute_MM_table(dsp56k_core* cpustate, UINT16 rnum, UINT16 MM) { UINT16 *rX = 0x00 ; UINT16 *nX = 0x00 ; @@ -4156,7 +4155,7 @@ static void execute_MM_table(UINT16 rnum, UINT16 MM) } /* Returns R value */ -static UINT16 execute_q_table(int RR, UINT16 q) +static UINT16 execute_q_table(dsp56k_core* cpustate, int RR, UINT16 q) { UINT16 *rX = 0x0000; UINT16 *nX = 0x0000; @@ -4180,7 +4179,7 @@ static UINT16 execute_q_table(int RR, UINT16 q) return 0; } -static void execute_z_table(int RR, UINT16 z) +static void execute_z_table(dsp56k_core* cpustate, int RR, UINT16 z) { UINT16 *rX = 0x00; UINT16 *nX = 0x00; @@ -4200,27 +4199,27 @@ static void execute_z_table(int RR, UINT16 z) } } -static UINT16 assemble_address_from_Pppppp_table(UINT16 P, UINT16 ppppp) +static UINT16 assemble_address_from_Pppppp_table(dsp56k_core* cpustate, UINT16 P, UINT16 ppppp) { UINT16 destAddr = 0x00 ; switch (P) { case 0x0: destAddr = ppppp; break; /* TODO: Does this really only address up to 0x32? */ - case 0x1: destAddr = assemble_address_from_IO_short_address(ppppp); break; + case 0x1: destAddr = assemble_address_from_IO_short_address(cpustate, ppppp); break; } return destAddr ; } -static UINT16 assemble_address_from_IO_short_address(UINT16 pp) +static UINT16 assemble_address_from_IO_short_address(dsp56k_core* cpustate, UINT16 pp) { UINT16 fullAddy = 0xffe0; fullAddy |= pp; return fullAddy; } -static UINT16 assemble_address_from_6bit_signed_relative_short_address(UINT16 srs) +static UINT16 assemble_address_from_6bit_signed_relative_short_address(dsp56k_core* cpustate, UINT16 srs) { UINT16 fullAddy = srs ; if (fullAddy & 0x0020) @@ -4229,21 +4228,21 @@ static UINT16 assemble_address_from_6bit_signed_relative_short_address(UINT16 sr return fullAddy ; } -static void dsp56k_process_loop(void) +static void dsp56k_process_loop(dsp56k_core* cpustate) { /* TODO: This might not work for dos nested in doForevers */ - if (LF_bit() && FV_bit()) + if (LF_bit(cpustate) && FV_bit(cpustate)) { /* Do Forever*/ if (PC == LA) { LC--; - core.ppc = PC; + cpustate->ppc = PC; PC = SSH; } } - else if (LF_bit()) + else if (LF_bit(cpustate)) { /* Do */ if (PC == LA) @@ -4267,18 +4266,18 @@ static void dsp56k_process_loop(void) } } -static void dsp56k_process_rep(size_t repSize) +static void dsp56k_process_rep(dsp56k_core* cpustate, size_t repSize) { - if (core.repFlag) + if (cpustate->repFlag) { - if (PC == core.repAddr) + if (PC == cpustate->repAddr) { if (LC == 1) { /* End of rep processing */ LC = TEMP; - core.repFlag = 0; - core.repAddr = 0x0000; + cpustate->repFlag = 0; + cpustate->repAddr = 0x0000; } else { @@ -4294,12 +4293,12 @@ static void dsp56k_process_rep(size_t repSize) Parallel Memory Ops ***************************************************************************/ /* Register to Register Data Move : 0100 IIII .... .... : A-132 */ -static void execute_register_to_register_data_move(const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value) +static void execute_register_to_register_data_move(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value) { typed_pointer S = {NULL, DT_BYTE}; typed_pointer D = {NULL, DT_BYTE}; - decode_IIII_table(BITS(op,0x0f00), &S, &D, d_register->addr); + decode_IIII_table(cpustate, BITS(op,0x0f00), &S, &D, d_register->addr); /* If the source is the same as the ALU destination, use the previous accumulator value */ if (d_register->addr == S.addr) @@ -4316,26 +4315,26 @@ static void execute_register_to_register_data_move(const UINT16 op, typed_pointe } /* Address Register Update : 0011 0zRR .... .... : A-135 */ -static void execute_address_register_update(const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value) +static void execute_address_register_update(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value) { - execute_z_table(BITS(op,0x0300), BITS(op,0x0400)); + execute_z_table(cpustate, BITS(op,0x0300), BITS(op,0x0400)); } /* X Memory Data Move : 1mRR HHHW .... .... : A-137 */ -static void execute_x_memory_data_move(const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value) +static void execute_x_memory_data_move(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value) { UINT16 W; typed_pointer R = {NULL, DT_BYTE}; typed_pointer SD = {NULL, DT_BYTE}; W = BITS(op,0x0100); - decode_HHH_table(BITS(op,0x0e00), &SD); - decode_RR_table(BITS(op,0x3000),&R); + decode_HHH_table(cpustate, BITS(op,0x0e00), &SD); + decode_RR_table(cpustate, BITS(op,0x3000),&R); if (W) { /* From X:<ea> to SD */ - UINT16 data = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr))); + UINT16 data = memory_read_word_16le(cpustate->data, WORD(*((UINT16*)R.addr))); typed_pointer tempTP; tempTP.addr = &data; @@ -4353,27 +4352,27 @@ static void execute_x_memory_data_move(const UINT16 op, typed_pointer* d_registe tempTP.addr = prev_accum_value; tempTP.data_type = DT_LONG_WORD; - SetDataMemoryValue(tempTP, WORD(*((UINT16*)R.addr))) ; + SetDataMemoryValue(cpustate, tempTP, WORD(*((UINT16*)R.addr))) ; } else { - SetDataMemoryValue(SD, WORD(*((UINT16*)R.addr))) ; + SetDataMemoryValue(cpustate, SD, WORD(*((UINT16*)R.addr))) ; } } - execute_m_table(BITS(op,0x3000), BITS(op,0x4000)); + execute_m_table(cpustate, BITS(op,0x3000), BITS(op,0x4000)); } /* X Memory Data Move : 0101 HHHW .... .... : A-137 */ /* NOTE: previous accumulator value is not needed since ^F1 is always the opposite accumulator */ -static void execute_x_memory_data_move2(const UINT16 op, typed_pointer* d_register) +static void execute_x_memory_data_move2(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register) { UINT16 W; UINT16* mem_offset = NULL; typed_pointer SD = {NULL, DT_BYTE}; W = BITS(op,0x0100); - decode_HHH_table(BITS(op,0x0e000), &SD); + decode_HHH_table(cpustate, BITS(op,0x0e000), &SD); if (d_register->addr == &A) mem_offset = &B1; @@ -4383,19 +4382,19 @@ static void execute_x_memory_data_move2(const UINT16 op, typed_pointer* d_regist if (W) { /* Write D */ - UINT16 value = memory_read_word_16le(core.data, WORD(*mem_offset)); + UINT16 value = memory_read_word_16le(cpustate->data, WORD(*mem_offset)); typed_pointer tempV = {&value, DT_WORD}; SetDestinationValue(tempV, SD); } else { /* Read S */ - SetDataMemoryValue(SD, WORD(*mem_offset)); + SetDataMemoryValue(cpustate, SD, WORD(*mem_offset)); } } /* X Memory Data Move With Short Displacement : 0000 0101 BBBB BBBB ---- HHHW .... .... : A-139 */ -static void execute_x_memory_data_move_with_short_displacement(const UINT16 op, const UINT16 op2) +static void execute_x_memory_data_move_with_short_displacement(dsp56k_core* cpustate, const UINT16 op, const UINT16 op2) { INT8 xx; UINT8 W; @@ -4404,14 +4403,14 @@ static void execute_x_memory_data_move_with_short_displacement(const UINT16 op, xx = (INT8)(op & 0x00ff); W = BITS(op2,0x0100); - decode_HHH_table(BITS(op2,0x0e00), &SD); + decode_HHH_table(cpustate, BITS(op2,0x0e00), &SD); memOffset = R2 + (INT16)xx; if (W) { /* Write D */ - UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset)); + UINT16 tempData = memory_read_word_16le(cpustate->data, WORD(memOffset)); typed_pointer temp_src = { (void*)&tempData, DT_WORD }; SetDestinationValue(temp_src, SD); } @@ -4420,12 +4419,12 @@ static void execute_x_memory_data_move_with_short_displacement(const UINT16 op, /* Read S */ UINT16 tempData = *((UINT16*)SD.addr); typed_pointer temp_src = { (void*)&tempData, DT_WORD }; - SetDataMemoryValue(temp_src, WORD(memOffset)); + SetDataMemoryValue(cpustate, temp_src, WORD(memOffset)); } } /* Dual X Memory Data Read : 011m mKKK .rr. .... : A-142*/ -static void execute_dual_x_memory_data_read(const UINT16 op, typed_pointer* d_register) +static void execute_dual_x_memory_data_read(dsp56k_core* cpustate, const UINT16 op, typed_pointer* d_register) { typed_pointer tempV; UINT16 srcVal1 = 0x0000; @@ -4434,8 +4433,8 @@ static void execute_dual_x_memory_data_read(const UINT16 op, typed_pointer* d_re typed_pointer D1 = {NULL, DT_BYTE}; typed_pointer D2 = {NULL, DT_BYTE}; - decode_RR_table(BITS(op,0x0060), &R); - decode_KKK_table(BITS(op,0x0700), &D1, &D2, d_register->addr); + decode_RR_table(cpustate, BITS(op,0x0060), &R); + decode_KKK_table(cpustate, BITS(op,0x0700), &D1, &D2, d_register->addr); /* Can't do an R3 for S1 */ if (R.addr == &R3) @@ -4447,19 +4446,19 @@ static void execute_dual_x_memory_data_read(const UINT16 op, typed_pointer* d_re fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read."); /* First memmove */ - srcVal1 = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr))); + srcVal1 = memory_read_word_16le(cpustate->data, WORD(*((UINT16*)R.addr))); tempV.addr = &srcVal1; tempV.data_type = DT_WORD; SetDestinationValue(tempV, D1); /* Second memmove */ - srcVal2 = memory_read_word_16le(core.data, WORD(R3)); + srcVal2 = memory_read_word_16le(cpustate->data, WORD(R3)); tempV.addr = &srcVal2; tempV.data_type = DT_WORD; SetDestinationValue(tempV, D2); /* Touch up the R regs after all the moves */ - execute_mm_table(BITS(op,0x0060), BITS(op,0x1800)); + execute_mm_table(cpustate, BITS(op,0x0060), BITS(op,0x1800)); } /*************************************************************************** @@ -4544,32 +4543,32 @@ static void SetDestinationValue(typed_pointer source, typed_pointer dest) } /* TODO: Wait-state timings! */ -static void SetDataMemoryValue(typed_pointer source, UINT32 destinationAddr) +static void SetDataMemoryValue(dsp56k_core* cpustate, typed_pointer source, UINT32 destinationAddr) { switch(source.data_type) { - case DT_BYTE: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ; - case DT_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ; - case DT_DOUBLE_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ; + case DT_BYTE: memory_write_word_16le(cpustate->data, destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ; + case DT_WORD: memory_write_word_16le(cpustate->data, destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ; + case DT_DOUBLE_WORD: memory_write_word_16le(cpustate->data, destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ; // !!! Is this universal ??? // !!! Forget not, yon shift-limiter !!! - case DT_LONG_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ; + case DT_LONG_WORD: memory_write_word_16le(cpustate->data, destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ; } } /* TODO: Wait-state timings! */ -static void SetProgramMemoryValue(typed_pointer source, UINT32 destinationAddr) +static void SetProgramMemoryValue(dsp56k_core* cpustate, typed_pointer source, UINT32 destinationAddr) { switch(source.data_type) { - case DT_BYTE: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ; - case DT_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ; - case DT_DOUBLE_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ; + case DT_BYTE: memory_write_word_16le(cpustate->program, destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ; + case DT_WORD: memory_write_word_16le(cpustate->program, destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ; + case DT_DOUBLE_WORD: memory_write_word_16le(cpustate->program, destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ; // !!! Is this universal ??? // !!! Forget not, yon shift-limiter !!! - case DT_LONG_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ; + case DT_LONG_WORD: memory_write_word_16le(cpustate->program, destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ; } } diff --git a/src/emu/cpu/dsp56k/dsp56pcu.c b/src/emu/cpu/dsp56k/dsp56pcu.c index e7fe558c36a..e924f1b45d9 100644 --- a/src/emu/cpu/dsp56k/dsp56pcu.c +++ b/src/emu/cpu/dsp56k/dsp56pcu.c @@ -1,84 +1,84 @@ /* Status Register */ -static UINT8 LF_bit(void) { return (SR & 0x8000) >> 15; } -static UINT8 FV_bit(void) { return (SR & 0x4000) >> 14; } -//static UINT8 S_bits(void); #define s1BIT ((SR & 0x0800) != 0) #define s0BIT ((SR & 0x0400) != 0) -static UINT8 I_bits(void) { return (SR & 0x0300) >> 8; } -static UINT8 S_bit(void) { return (SR & 0x0080) >> 7; } -static UINT8 L_bit(void) { return (SR & 0x0040) >> 6; } -static UINT8 E_bit(void) { return (SR & 0x0020) >> 5; } -static UINT8 U_bit(void) { return (SR & 0x0010) >> 4; } -static UINT8 N_bit(void) { return (SR & 0x0008) >> 3; } -static UINT8 Z_bit(void) { return (SR & 0x0004) >> 2; } -static UINT8 V_bit(void) { return (SR & 0x0002) >> 1; } -static UINT8 C_bit(void) { return (SR & 0x0001) >> 0; } - -static void LF_bit_set(UINT8 value) +static UINT8 LF_bit(dsp56k_core* cpustate) { return (SR & 0x8000) >> 15; } +static UINT8 FV_bit(dsp56k_core* cpustate) { return (SR & 0x4000) >> 14; } +//static UINT8 S_bits(dsp56k_core* cpustate); #define s1BIT ((SR & 0x0800) != 0) #define s0BIT ((SR & 0x0400) != 0) +static UINT8 I_bits(dsp56k_core* cpustate) { return (SR & 0x0300) >> 8; } +static UINT8 S_bit(dsp56k_core* cpustate) { return (SR & 0x0080) >> 7; } +static UINT8 L_bit(dsp56k_core* cpustate) { return (SR & 0x0040) >> 6; } +static UINT8 E_bit(dsp56k_core* cpustate) { return (SR & 0x0020) >> 5; } +static UINT8 U_bit(dsp56k_core* cpustate) { return (SR & 0x0010) >> 4; } +static UINT8 N_bit(dsp56k_core* cpustate) { return (SR & 0x0008) >> 3; } +static UINT8 Z_bit(dsp56k_core* cpustate) { return (SR & 0x0004) >> 2; } +static UINT8 V_bit(dsp56k_core* cpustate) { return (SR & 0x0002) >> 1; } +static UINT8 C_bit(dsp56k_core* cpustate) { return (SR & 0x0001) >> 0; } + +static void LF_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x8000); SR |= (value << 15); } -static void FV_bit_set(UINT8 value) +static void FV_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x4000); SR |= (value << 14); } -static void S_bits_set(UINT8 value) +static void S_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0c00); SR |= (value << 10); } -static void I_bits_set(UINT8 value) +static void I_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0300); SR |= (value << 8); } -static void S_bit_set(UINT8 value) +static void S_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x0080); SR |= (value << 7); } -static void L_bit_set(UINT8 value) +static void L_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x0040); SR |= (value << 6); } -static void E_bit_set(UINT8 value) +static void E_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x0020); SR |= (value << 5); } -static void U_bit_set(UINT8 value) +static void U_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x0010); SR |= (value << 4); } -static void N_bit_set(UINT8 value) +static void N_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x0008); SR |= (value << 3); } -static void Z_bit_set(UINT8 value) +static void Z_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x0004); SR |= (value << 2); } -static void V_bit_set(UINT8 value) +static void V_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x0002); SR |= (value << 1); } -static void C_bit_set(UINT8 value) +static void C_bit_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x01; SR &= ~(0x0001); @@ -86,57 +86,57 @@ static void C_bit_set(UINT8 value) } /* Operating Mode Register */ -// static UINT8 MC_bit(void) { return ((OMR & 0x0004) != 0); } // #define mcBIT ((OMR & 0x0004) != 0) -static UINT8 MB_bit(void) { return ((OMR & 0x0002) != 0); } // #define mbBIT ((OMR & 0x0002) != 0) -static UINT8 MA_bit(void) { return ((OMR & 0x0001) != 0); } // #define maBIT ((OMR & 0x0001) != 0) +// static UINT8 MC_bit(dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); } // #define mcBIT ((OMR & 0x0004) != 0) +static UINT8 MB_bit(dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); } // #define mbBIT ((OMR & 0x0002) != 0) +static UINT8 MA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); } // #define maBIT ((OMR & 0x0001) != 0) -static void CD_bit_set(UINT8 value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); } -static void SD_bit_set(UINT8 value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); } -static void R_bit_set(UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); } -static void SA_bit_set(UINT8 value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); } -static void MC_bit_set(UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); } -static void MB_bit_set(UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); } -static void MA_bit_set(UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); } +static void CD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); } +static void SD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); } +static void R_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); } +static void SA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); } +static void MC_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); } +static void MB_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); } +static void MA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); } /* Stack Pointer */ -static UINT8 UF_bit() { return (SP & 0x0020) >> 5; } -static UINT8 SE_bit() { return (SP & 0x0010) >> 4; } +static UINT8 UF_bit(dsp56k_core* cpustate) { return (SP & 0x0020) >> 5; } +static UINT8 SE_bit(dsp56k_core* cpustate) { return (SP & 0x0010) >> 4; } -//static void UF_bit_set(UINT8 value) {}; -//static void SE_bit_set(UINT8 value) {}; +//static void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {}; +//static void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {}; -UINT8 dsp56k_operating_mode(void) +UINT8 dsp56k_operating_mode(dsp56k_core* cpustate) { - return ((MB_bit() << 1) | MA_bit()); + return ((MB_bit(cpustate) << 1) | MA_bit(cpustate)); } -static void pcu_init(int index) +static void pcu_init(dsp56k_core* cpustate, int index) { // Init the irq table dsp56k_irq_table_init(); } -static void pcu_reset(void) +static void pcu_reset(dsp56k_core* cpustate) { int i; // When reset is deasserted, set MA, MB, and MC from MODA, MODB, and MODC lines. - MA_bit_set(core.modA_state); - MB_bit_set(core.modB_state); - MC_bit_set(core.modC_state); + MA_bit_set(cpustate, cpustate->modA_state); + MB_bit_set(cpustate, cpustate->modB_state); + MC_bit_set(cpustate, cpustate->modC_state); // Reset based on the operating mode. - switch(dsp56k_operating_mode()) + switch(dsp56k_operating_mode(cpustate)) { case 0x00: logerror("Dsp56k in Special Bootstrap Mode 1\n"); // HACK - We don't need to put the bootstrap mode on here since // we'll simulate it entirely in this function - core.bootstrap_mode = BOOTSTRAP_OFF; + cpustate->bootstrap_mode = BOOTSTRAP_OFF; // HACK - Simply copy over 0x1000 bytes of data located at program memory 0xc000. // This, in actuality, is handled with the internal boot ROM. @@ -150,8 +150,8 @@ static void pcu_reset(void) // ... // P:$cffe -> Internal P:$07ff low byte // P:$cfff -> Internal P:$07ff high byte - UINT8 mem_value_low = memory_read_byte_16le(core.program, mem_offset); /* TODO: IS THIS READING RIGHT? */ - UINT8 mem_value_high = memory_read_byte_16be(core.program, mem_offset); + UINT8 mem_value_low = memory_read_byte_16le(cpustate->program, mem_offset); /* TODO: IS THIS READING RIGHT? */ + UINT8 mem_value_high = memory_read_byte_16be(cpustate->program, mem_offset); dsp56k_program_ram[i] = (mem_value_high << 8) || mem_value_low; } @@ -159,9 +159,9 @@ static void pcu_reset(void) PC = 0x0000; // HACK - All done! Set the Operating Mode to 2 as per the boot ROM. - MB_bit_set(1); - MA_bit_set(0); - core.PCU.reset_vector = 0xe000; + MB_bit_set(cpustate, 1); + MA_bit_set(cpustate, 0); + cpustate->PCU.reset_vector = 0xe000; break; case 0x01: @@ -172,14 +172,14 @@ static void pcu_reset(void) // they need. Once they've had their fill, they turn bootstrap mode off // and the CPU begins execution at 0x0000; // HACK - Read bit 15 at 0xc000 to see if we're working with the SSIO or host interface. - if (memory_read_word_16le(core.program, 0xc000<<1) & 0x8000) + if (memory_read_word_16le(cpustate->program, 0xc000<<1) & 0x8000) { - core.bootstrap_mode = BOOTSTRAP_SSIX; + cpustate->bootstrap_mode = BOOTSTRAP_SSIX; logerror("DSP56k : Currently in (hacked) bootstrap mode - reading from SSIx.\n"); } else { - core.bootstrap_mode = BOOTSTRAP_HI; + cpustate->bootstrap_mode = BOOTSTRAP_HI; logerror("DSP56k : Currently in (hacked) bootstrap mode - reading from Host Interface.\n"); } @@ -187,22 +187,22 @@ static void pcu_reset(void) PC = 0x0000; // HACK - Not done yet, but set the Operating Mode to 2 in preparation. - MB_bit_set(1); - MA_bit_set(0); - core.PCU.reset_vector = 0xe000; + MB_bit_set(cpustate, 1); + MA_bit_set(cpustate, 0); + cpustate->PCU.reset_vector = 0xe000; break; case 0x02: logerror("Dsp56k in Normal Expanded Mode\n"); PC = 0xe000; - core.PCU.reset_vector = 0xe000; + cpustate->PCU.reset_vector = 0xe000; break; case 0x03: logerror("Dsp56k in Development Expanded Mode\n"); // TODO: Disable internal ROM, etc. Likely a tricky thing for MAME? PC = 0x0000; - core.PCU.reset_vector = 0x0000; + cpustate->PCU.reset_vector = 0x0000; break; } @@ -211,32 +211,32 @@ static void pcu_reset(void) IPR = 0x0000; // FM.5-4 - I_bits_set(0x03); - S_bits_set(0); - L_bit_set(0); - S_bit_set(0); - FV_bit_set(0); + I_bits_set(cpustate, 0x03); + S_bits_set(cpustate, 0); + L_bit_set(cpustate, 0); + S_bit_set(cpustate, 0); + FV_bit_set(cpustate, 0); // FM.7-25 - E_bit_set(0); - U_bit_set(0); - N_bit_set(0); - V_bit_set(0); - Z_bit_set(0); + E_bit_set(cpustate, 0); + U_bit_set(cpustate, 0); + N_bit_set(cpustate, 0); + V_bit_set(cpustate, 0); + Z_bit_set(cpustate, 0); // FM.5-4+ - C_bit_set(0); - LF_bit_set(0); + C_bit_set(cpustate, 0); + LF_bit_set(cpustate, 0); SP = 0x0000; // FM.5-14 (OMR) - SA_bit_set(0); - R_bit_set(0); - SD_bit_set(0); - CD_bit_set(0); + SA_bit_set(cpustate, 0); + R_bit_set(cpustate, 0); + SD_bit_set(cpustate, 0); + CD_bit_set(cpustate, 0); // Clear out the pending interrupt list - dsp56k_clear_pending_interrupts(); + dsp56k_clear_pending_interrupts(cpustate); } /*************************************************************************** @@ -251,30 +251,30 @@ typedef struct static dsp56k_irq_data dsp56k_interrupt_sources[32]; // TODO: Figure out how to switch on level versus edge-triggered. -static void pcu_service_interrupts(void) +static void pcu_service_interrupts(dsp56k_core* cpustate) { int i; // Count list of pending interrupts - int num_servicable = dsp56k_count_pending_interrupts(); + int num_servicable = dsp56k_count_pending_interrupts(cpustate); if (num_servicable == 0) return; // Sort list according to priority - dsp56k_sort_pending_interrupts(num_servicable); + dsp56k_sort_pending_interrupts(cpustate, num_servicable); // Service each interrupt in order // TODO: This just *can't* be right :) for (i = 0; i < num_servicable; i++) { - const int interrupt_index = core.PCU.pending_interrupts[i]; + const int interrupt_index = cpustate->PCU.pending_interrupts[i]; // Get the priority of the interrupt - a return value of -1 means disabled! - INT8 priority = dsp56k_get_irq_priority(interrupt_index); + INT8 priority = dsp56k_get_irq_priority(cpustate, interrupt_index); // 1-12 Make sure you're not masked out against the Interrupt Mask Bits (disabled is handled for free here) - if (priority >= I_bits()) + if (priority >= I_bits(cpustate)) { // Are you anything but the Host Command interrupt? if (interrupt_index != 22) @@ -285,34 +285,34 @@ static void pcu_service_interrupts(void) else { // The host command input has a floating vector. - const UINT16 irq_vector = HV_bits() << 1; + const UINT16 irq_vector = HV_bits(cpustate) << 1; - core.ppc = PC; + cpustate->ppc = PC; PC = irq_vector; // TODO: 5-9 5-11 Gotta' Clear HC (HCP gets it too) when taking this exception! - HC_bit_set(0); + HC_bit_set(cpustate, 0); } } } - dsp56k_clear_pending_interrupts(); + dsp56k_clear_pending_interrupts(cpustate); } // // The function the CPU core will call to add an interrupt to the list // (The API as it were) // -static void dsp56k_add_pending_interrupt(const char* name) +static void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name) { int i; int irq_index = dsp56k_get_irq_index_by_tag(name); for (i = 0; i < 32; i++) { - if (core.PCU.pending_interrupts[i] == -1) + if (cpustate->PCU.pending_interrupts[i] == -1) { - core.PCU.pending_interrupts[i] = irq_index; + cpustate->PCU.pending_interrupts[i] = irq_index; break; } } @@ -363,19 +363,19 @@ static void dsp56k_irq_table_init(void) dsp56k_set_irq_source(31, 0x003e, "Host Command 8"); } -static void dsp56k_clear_pending_interrupts(void) +static void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate) { int i; for (i = 0; i < 32; i++) { - core.PCU.pending_interrupts[i] = -1; + cpustate->PCU.pending_interrupts[i] = -1; } } -static int dsp56k_count_pending_interrupts(void) +static int dsp56k_count_pending_interrupts(dsp56k_core* cpustate) { int numI = 0; - while (core.PCU.pending_interrupts[numI] != -1) + while (cpustate->PCU.pending_interrupts[numI] != -1) { numI++; } @@ -383,7 +383,7 @@ static int dsp56k_count_pending_interrupts(void) return numI; } -static void dsp56k_sort_pending_interrupts(int num) +static void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num) { int i, j; @@ -391,7 +391,7 @@ static void dsp56k_sort_pending_interrupts(int num) int priority_list[32]; for (i = 0; i < num; i++) { - priority_list[i] = dsp56k_get_irq_priority(core.PCU.pending_interrupts[i]); + priority_list[i] = dsp56k_get_irq_priority(cpustate, cpustate->PCU.pending_interrupts[i]); } // Bubble sort should be good enough for us @@ -409,9 +409,9 @@ static void dsp56k_sort_pending_interrupts(int num) priority_list[j] = holder; // Swap irq indices. - holder = core.PCU.pending_interrupts[j+1]; - core.PCU.pending_interrupts[j+1] = core.PCU.pending_interrupts[j]; - core.PCU.pending_interrupts[j] = holder; + holder = cpustate->PCU.pending_interrupts[j+1]; + cpustate->PCU.pending_interrupts[j+1] = cpustate->PCU.pending_interrupts[j]; + cpustate->PCU.pending_interrupts[j] = holder; } } } @@ -419,7 +419,7 @@ static void dsp56k_sort_pending_interrupts(int num) // TODO: 1-17 Now sort each of the priority levels within their categories. } -static INT8 dsp56k_get_irq_priority(int index) +static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index) { // 1-12 switch (index) @@ -432,33 +432,33 @@ static INT8 dsp56k_get_irq_priority(int index) case 4: return 3; // SWI // Poll the IPR for these guys. - case 5: return irqa_ipl(); // IRQA - case 6: return irqb_ipl(); // IRQB - case 7: return -1; // Reserved - case 8: return ssi0_ipl(); // SSI0 Receive Data with Exception - case 9: return ssi0_ipl(); // SSI0 Receive Data - case 10: return ssi0_ipl(); // SSI0 Transmit Data with Exception - case 11: return ssi0_ipl(); // SSI0 Transmit Data - case 12: return ssi1_ipl(); // SSI1 Receive Data with Exception - case 13: return ssi1_ipl(); // SSI1 Receive Data - case 14: return ssi1_ipl(); // SSI1 Transmit Data with Exception - case 15: return ssi1_ipl(); // SSI1 Transmit Data - case 16: return tm_ipl(); // Timer Overflow - case 17: return tm_ipl(); // Timer Compare - case 18: return host_ipl(); // Host DMA Receive Data - case 19: return host_ipl(); // Host DMA Transmit Data - case 20: return host_ipl(); // Host Receive Data - case 21: return host_ipl(); // Host Transmit Data - case 22: return host_ipl(); // Host Command 0 (Default) - case 23: return codec_ipl(); // Codec Receive/Transmit - case 24: return host_ipl(); // Host Command 1 // TODO: Are all host ipl's the same? - case 25: return host_ipl(); // Host Command 2 - case 26: return host_ipl(); // Host Command 3 - case 27: return host_ipl(); // Host Command 4 - case 28: return host_ipl(); // Host Command 5 - case 29: return host_ipl(); // Host Command 6 - case 30: return host_ipl(); // Host Command 7 - case 31: return host_ipl(); // Host Command 8 + case 5: return irqa_ipl(cpustate); // IRQA + case 6: return irqb_ipl(cpustate); // IRQB + case 7: return -1; // Reserved + case 8: return ssi0_ipl(cpustate); // SSI0 Receive Data with Exception + case 9: return ssi0_ipl(cpustate); // SSI0 Receive Data + case 10: return ssi0_ipl(cpustate); // SSI0 Transmit Data with Exception + case 11: return ssi0_ipl(cpustate); // SSI0 Transmit Data + case 12: return ssi1_ipl(cpustate); // SSI1 Receive Data with Exception + case 13: return ssi1_ipl(cpustate); // SSI1 Receive Data + case 14: return ssi1_ipl(cpustate); // SSI1 Transmit Data with Exception + case 15: return ssi1_ipl(cpustate); // SSI1 Transmit Data + case 16: return tm_ipl(cpustate); // Timer Overflow + case 17: return tm_ipl(cpustate); // Timer Compare + case 18: return host_ipl(cpustate); // Host DMA Receive Data + case 19: return host_ipl(cpustate); // Host DMA Transmit Data + case 20: return host_ipl(cpustate); // Host Receive Data + case 21: return host_ipl(cpustate); // Host Transmit Data + case 22: return host_ipl(cpustate); // Host Command 0 (Default) + case 23: return codec_ipl(cpustate); // Codec Receive/Transmit + case 24: return host_ipl(cpustate); // Host Command 1 // TODO: Are all host ipl's the same? + case 25: return host_ipl(cpustate); // Host Command 2 + case 26: return host_ipl(cpustate); // Host Command 3 + case 27: return host_ipl(cpustate); // Host Command 4 + case 28: return host_ipl(cpustate); // Host Command 5 + case 29: return host_ipl(cpustate); // Host Command 6 + case 30: return host_ipl(cpustate); // Host Command 7 + case 31: return host_ipl(cpustate); // Host Command 8 default: break; } |