summaryrefslogtreecommitdiffstatshomepage
path: root/src/emu/cpu/dsp56k
diff options
context:
space:
mode:
author Andrew Gardner <andrew-gardner@users.noreply.github.com>2008-10-01 04:24:46 +0000
committer Andrew Gardner <andrew-gardner@users.noreply.github.com>2008-10-01 04:24:46 +0000
commit8515504a7b8ccb6399c5ef51bd671059595ccb95 (patch)
treea11c0fec9bbc98da3dc335f9ca82d96832211060 /src/emu/cpu/dsp56k
parenta10dfb942dcd98e28e8cd5b74d0695af168185e3 (diff)
Added additional Motorola DSP56k reset behavior. (Andrew Gardner)
Diffstat (limited to 'src/emu/cpu/dsp56k')
-rw-r--r--src/emu/cpu/dsp56k/dsp56def.h27
-rw-r--r--src/emu/cpu/dsp56k/dsp56k.c37
-rw-r--r--src/emu/cpu/dsp56k/dsp56mem.c24
-rw-r--r--src/emu/cpu/dsp56k/dsp56ops.c9
-rw-r--r--src/emu/cpu/dsp56k/dsp56pcu.c79
5 files changed, 147 insertions, 29 deletions
diff --git a/src/emu/cpu/dsp56k/dsp56def.h b/src/emu/cpu/dsp56k/dsp56def.h
index a0ea85ad857..6ec50d6fc63 100644
--- a/src/emu/cpu/dsp56k/dsp56def.h
+++ b/src/emu/cpu/dsp56k/dsp56def.h
@@ -76,10 +76,12 @@ static void pcu_reset(void);
#define ST15 (SS[15].d)
/* 1-25 STATUS REGISTER (SR) BITS */
+/* MR */
static UINT8 LF_bit(void);
static UINT8 FV_bit(void);
//static UINT8 S_bits(void); #define s1BIT ((SR & 0x0800) != 0) #define s0BIT ((SR & 0x0400) != 0)
static UINT8 I_bits(void);
+/* CCR */
static UINT8 S_bit(void);
static UINT8 L_bit(void);
static UINT8 E_bit(void);
@@ -89,14 +91,16 @@ static UINT8 Z_bit(void);
static UINT8 V_bit(void);
static UINT8 C_bit(void);
+/* MR */
static void LF_bit_set(UINT8 value);
-//static void FV_bit_set(UINT8 value); #define fvBIT_CLEAR() (SR &= (~0x4000))
-//static void S_bits_set(UINT8 value); #define s1BIT_CLEAR() (SR &= (~0x0800)) #define s0BIT_CLEAR() (SR &= (~0x0400))
-//static void I_bits_set(UINT8 value);
-//static void S_bit_set(UINT8 value); #define sBIT_CLEAR() (SR &= (~0x0080))
-//static void L_bit_set(UINT8 value); #define lBIT_CLEAR() (SR &= (~0x0040))
-//static void E_bit_set(UINT8 value); #define eBIT_CLEAR() (SR &= (~0x0020))
-//static void U_bit_set(UINT8 value); #define uBIT_CLEAR() (SR &= (~0x0010))
+static void FV_bit_set(UINT8 value);
+static void S_bits_set(UINT8 value);
+static void I_bits_set(UINT8 value);
+/* CCR */
+static void S_bit_set(UINT8 value);
+static void L_bit_set(UINT8 value);
+static void E_bit_set(UINT8 value);
+static void U_bit_set(UINT8 value);
static void N_bit_set(UINT8 value);
static void Z_bit_set(UINT8 value);
static void V_bit_set(UINT8 value);
@@ -113,10 +117,10 @@ static void C_bit_set(UINT8 value);
static UINT8 MB_bit(void);
static UINT8 MA_bit(void);
-//static UINT8 CD_bit_set(UINT8 value); #define cdBIT_CLEAR() (OMR &= (~0x0080))
-//static UINT8 SD_bit_set(UINT8 value); #define sdBIT_CLEAR() (OMR &= (~0x0040))
-//static UINT8 R_bit_set(UINT8 value); #define rBIT_CLEAR() (OMR &= (~0x0020))
-//static UINT8 SA_bit_set(UINT8 value); #define saBIT_CLEAR() (OMR &= (~0x0010))
+static void CD_bit_set(UINT8 value);
+static void SD_bit_set(UINT8 value);
+static void R_bit_set(UINT8 value);
+static void SA_bit_set(UINT8 value);
static void MC_bit_set(UINT8 value);
static void MB_bit_set(UINT8 value);
static void MA_bit_set(UINT8 value);
@@ -380,3 +384,4 @@ static void PCDDR_set(UINT16 value);
/* Port C Dtaa Register (PCD) */
static void PCD_set(UINT16 value);
+
diff --git a/src/emu/cpu/dsp56k/dsp56k.c b/src/emu/cpu/dsp56k/dsp56k.c
index 80fdd022b3f..c685063b219 100644
--- a/src/emu/cpu/dsp56k/dsp56k.c
+++ b/src/emu/cpu/dsp56k/dsp56k.c
@@ -125,6 +125,9 @@ typedef struct
// Used in loop processing
UINT16 temp;
+ // FM.4-5 - hmmm?
+ // UINT8 status;
+
// Basics
} dsp56k_agu;
@@ -398,6 +401,36 @@ static void dsp56k_init(int index, int clock, const void *_config, int (*irqcall
//core.irq_callback = irqcallback;
}
+static void agu_reset(void)
+{
+ // FM.4-3
+ R0 = 0x0000;
+ R1 = 0x0000;
+ R2 = 0x0000;
+ R3 = 0x0000;
+
+ N0 = 0x0000;
+ N1 = 0x0000;
+ N2 = 0x0000;
+ N3 = 0x0000;
+
+ M0 = 0xffff;
+ M1 = 0xffff;
+ M2 = 0xffff;
+ M3 = 0xffff;
+
+ TEMP = 0x0000;
+}
+
+static void alu_reset(void)
+{
+ X = 0x00000000;
+ Y = 0x00000000;
+ A = 0x0000000000;
+ B = 0x0000000000;
+}
+
+
static void dsp56k_reset(void)
{
logerror("Dsp56k reset\n");
@@ -410,8 +443,8 @@ static void dsp56k_reset(void)
pcu_reset();
mem_reset();
- //agu_reset();
- //alu_reset();
+ agu_reset();
+ alu_reset();
/* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU put in MAME */
program_write_word_16le(0x0000, 0x0124);
diff --git a/src/emu/cpu/dsp56k/dsp56mem.c b/src/emu/cpu/dsp56k/dsp56mem.c
index 8c316f2967f..cb6303e9287 100644
--- a/src/emu/cpu/dsp56k/dsp56mem.c
+++ b/src/emu/cpu/dsp56k/dsp56mem.c
@@ -9,15 +9,15 @@ static void IPR_set(UINT16 value)
IPR = value;
}
-static INT8 irqa_ipl(void) { return ((IPR & 0x0003) >> 0) - 1; }
-static UINT8 irqa_trigger(void) { return (IPR & 0x0004) >> 2; }
-static INT8 irqb_ipl(void) { return ((IPR & 0x0018) >> 3) - 1; }
-static UINT8 irqb_trigger(void) { return (IPR & 0x0002) >> 5; }
-static INT8 codec_ipl(void) { return ((IPR & 0x00c0) >> 6) - 1; }
-static INT8 host_ipl(void) { return ((IPR & 0x0300) >> 8) - 1; }
-static INT8 ssi0_ipl(void) { return ((IPR & 0x0c00) >> 10) - 1; }
-static INT8 ssi1_ipl(void) { return ((IPR & 0x3000) >> 12) - 1; }
-static INT8 tm_ipl(void) { return ((IPR & 0xc000) >> 14) - 1; }
+static INT8 irqa_ipl(void) { return ((IPR & 0x0003) >> 0) - 1; }
+static UINT8 irqa_trigger(void) { return (IPR & 0x0004) >> 2; }
+static INT8 irqb_ipl(void) { return ((IPR & 0x0018) >> 3) - 1; }
+static UINT8 irqb_trigger(void) { return (IPR & 0x0002) >> 5; }
+static INT8 codec_ipl(void) { return ((IPR & 0x00c0) >> 6) - 1; }
+static INT8 host_ipl(void) { return ((IPR & 0x0300) >> 8) - 1; }
+static INT8 ssi0_ipl(void) { return ((IPR & 0x0c00) >> 10) - 1; }
+static INT8 ssi1_ipl(void) { return ((IPR & 0x3000) >> 12) - 1; }
+static INT8 tm_ipl(void) { return ((IPR & 0xc000) >> 14) - 1; }
static void mem_reset(void)
{
@@ -795,8 +795,8 @@ static void dsp56k_host_interface_host_to_HTX(void)
/* BCR */
static void BCR_set(UINT16 value)
{
- RH_bit_set((value & 0x0001) >> 15);
- BS_bit_set((value & 0x0001) >> 14);
+ RH_bit_set((value & 0x8000) >> 15);
+ BS_bit_set((value & 0x4000) >> 14);
external_x_wait_states_set((value & 0x03e0) >> 5);
external_p_wait_states_set((value & 0x001f) >> 0);
}
@@ -923,7 +923,7 @@ static void PCD_set(UINT16 value)
static void dsp56k_io_reset(void)
{
- /* The BCR */
+ /* The BCR = 0x43ff */
RH_bit_set(0);
BS_bit_set(1);
external_x_wait_states_set(0x1f);
diff --git a/src/emu/cpu/dsp56k/dsp56ops.c b/src/emu/cpu/dsp56k/dsp56ops.c
index c6fb2df29ac..8ee035e69d1 100644
--- a/src/emu/cpu/dsp56k/dsp56ops.c
+++ b/src/emu/cpu/dsp56k/dsp56ops.c
@@ -6,6 +6,15 @@
***************************************************************************/
+// NOTES For register setting:
+// FM.3-4 : When A2 or B2 is read, the register contents occupy the low-order portion
+// (bits 7-0) of the word; the high-order portion (bits 16-8) is sign-extended. When A2 or B2
+// is written, the register receives the low-order portion of the word; the high-order portion is not used
+// : ...much more!
+// : ...shifter/limiter/overflow notes too.
+//
+//
+
// Helper functions and macros
#define BITS(CUR,MASK) (Dsp56kOpMask(CUR,MASK))
static UINT16 Dsp56kOpMask(UINT16 op, UINT16 mask) ;
diff --git a/src/emu/cpu/dsp56k/dsp56pcu.c b/src/emu/cpu/dsp56k/dsp56pcu.c
index 85f1e3cd173..2e2ee206908 100644
--- a/src/emu/cpu/dsp56k/dsp56pcu.c
+++ b/src/emu/cpu/dsp56k/dsp56pcu.c
@@ -18,7 +18,48 @@ static void LF_bit_set(UINT8 value)
SR &= ~(0x8000);
SR |= (value << 15);
}
-//static UINT8 I_bits_set(void) { }
+static void FV_bit_set(UINT8 value)
+{
+ value = value & 0x01;
+ SR &= ~(0x4000);
+ SR |= (value << 14);
+}
+static void S_bits_set(UINT8 value)
+{
+ value = value & 0x03;
+ SR &= ~(0x0c00);
+ SR |= (value << 10);
+}
+static void I_bits_set(UINT8 value)
+{
+ value = value & 0x03;
+ SR &= ~(0x0300);
+ SR |= (value << 8);
+}
+static void S_bit_set(UINT8 value)
+{
+ value = value & 0x01;
+ SR &= ~(0x0080);
+ SR |= (value << 7);
+}
+static void L_bit_set(UINT8 value)
+{
+ value = value & 0x01;
+ SR &= ~(0x0040);
+ SR |= (value << 6);
+}
+static void E_bit_set(UINT8 value)
+{
+ value = value & 0x01;
+ SR &= ~(0x0020);
+ SR |= (value << 5);
+}
+static void U_bit_set(UINT8 value)
+{
+ value = value & 0x01;
+ SR &= ~(0x0010);
+ SR |= (value << 4);
+}
static void N_bit_set(UINT8 value)
{
value = value & 0x01;
@@ -49,9 +90,13 @@ static void C_bit_set(UINT8 value)
static UINT8 MB_bit(void) { return ((OMR & 0x0002) != 0); } // #define mbBIT ((OMR & 0x0002) != 0)
static UINT8 MA_bit(void) { return ((OMR & 0x0001) != 0); } // #define maBIT ((OMR & 0x0001) != 0)
-static void MC_bit_set(UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); } //#define mcBIT_CLEAR() (OMR &= (~0x0004)) //#define mcBIT_SET() (OMR |= 0x0004)
-static void MB_bit_set(UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); } //#define mbBIT_CLEAR() (OMR &= (~0x0002)) //#define mbBIT_SET() (OMR |= 0x0002)
-static void MA_bit_set(UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); } //#define maBIT_CLEAR() (OMR &= (~0x0001)) //#define maBIT_SET() (OMR |= 0x0001)
+static void CD_bit_set(UINT8 value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); }
+static void SD_bit_set(UINT8 value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); }
+static void R_bit_set(UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); }
+static void SA_bit_set(UINT8 value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); }
+static void MC_bit_set(UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); }
+static void MB_bit_set(UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); }
+static void MA_bit_set(UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); }
/* Stack Pointer */
@@ -165,6 +210,32 @@ static void pcu_reset(void)
// 1-17 Clear Interrupt Priority Register (IPR)
IPR = 0x0000;
+ // FM.5-4
+// I_bits_set(0x03); This is what the manual says, but i'm dubious! Polygonet's HI interrupt wouldn't happen with the I bits set.
+ I_bits_set(0x00);
+ S_bits_set(0);
+ L_bit_set(0);
+ S_bit_set(0);
+ FV_bit_set(0);
+
+ // FM.7-25
+ E_bit_set(0);
+ U_bit_set(0);
+ N_bit_set(0);
+ V_bit_set(0);
+ Z_bit_set(0);
+
+ // FM.5-4+
+ C_bit_set(0);
+ LF_bit_set(0);
+ SP = 0x0000;
+
+ // FM.5-14 (OMR)
+ SA_bit_set(0);
+ R_bit_set(0);
+ SD_bit_set(0);
+ CD_bit_set(0);
+
// Clear out the pending interrupt list
dsp56k_clear_pending_interrupts();
}