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authorGravatarGravatar David Haywood <28625134+DavidHaywood@users.noreply.github.com>2019-11-15 19:15:11 +0000
committerGravatarGravatar ajrhacker <ajrhacker@users.noreply.github.com>2019-11-15 14:15:11 -0500
commitc9a6c7ff4d7dceb7cdb67d50afc7f4b5f717c531 (patch)
tree9905210ed1e7e015f17bb5cdc0a59a914d788dac /src/devices
parenta0e2b82b634f796c186dec0db895028088a542e9 (diff)
new WORKING machines (ABL Pinball) + temp disable timer IRQ in rad_bb3 + significant nes_vt cleanups / state chop (#5900)
new WORKING machines -------------------- Pinball (P8002, ABL TV Game) [David Haywood, Morten Kirkegaard, Peter Wilhelmsen] * divided up large nes_vt.cpp class, and did some general tidy up, commented some known addresses etc. to stop code rot. * temporarily disabled timer on elan when running rad_bb3 until timer enable can be identified, made a few notes.
Diffstat (limited to 'src/devices')
-rw-r--r--src/devices/video/ppu2c0x_vt.cpp14
-rw-r--r--src/devices/video/ppu2c0x_vt.h9
2 files changed, 22 insertions, 1 deletions
diff --git a/src/devices/video/ppu2c0x_vt.cpp b/src/devices/video/ppu2c0x_vt.cpp
index 44cc2ea14fe..5e46f84ed0f 100644
--- a/src/devices/video/ppu2c0x_vt.cpp
+++ b/src/devices/video/ppu2c0x_vt.cpp
@@ -21,6 +21,8 @@ DEFINE_DEVICE_TYPE(PPU_VT03PAL, ppu_vt03pal_device, "ppu_vt03pal", "VT03 PPU (PA
ppu_vt03_device::ppu_vt03_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
ppu2c0x_device(mconfig, type, tag, owner, clock),
+ m_is_pal(false),
+ m_is_50hz(false),
m_read_bg(*this),
m_read_sp(*this)
{
@@ -39,6 +41,8 @@ ppu_vt03pal_device::ppu_vt03pal_device(const machine_config &mconfig, const char
{
m_scanlines_per_frame = PAL_SCANLINES_PER_FRAME;
m_vblank_first_scanline = VBLANK_FIRST_SCANLINE_PALC;
+ m_is_pal = true;
+ m_is_50hz = true;
}
@@ -54,6 +58,16 @@ READ8_MEMBER(ppu_vt03_device::palette_read)
}
}
+void ppu_vt03_device::set_201x_descramble(uint8_t reg0, uint8_t reg1, uint8_t reg2, uint8_t reg3, uint8_t reg4, uint8_t reg5)
+{
+ m_2012_2017_descramble[0] = reg0; // TOOD: name regs
+ m_2012_2017_descramble[1] = reg1;
+ m_2012_2017_descramble[2] = reg2;
+ m_2012_2017_descramble[3] = reg3;
+ m_2012_2017_descramble[4] = reg4;
+ m_2012_2017_descramble[5] = reg5;
+}
+
void ppu_vt03_device::set_new_pen(int i)
{
if((i < 0x20) && ((i & 0x3) == 0)) {
diff --git a/src/devices/video/ppu2c0x_vt.h b/src/devices/video/ppu2c0x_vt.h
index 7801ce44351..9514da73136 100644
--- a/src/devices/video/ppu2c0x_vt.h
+++ b/src/devices/video/ppu2c0x_vt.h
@@ -32,7 +32,7 @@ public:
auto read_sp() { return m_read_sp.bind(); }
void set_palette_mode(vtxx_pal_mode pmode) { m_pal_mode = pmode; }
- void set_201x_descramble(const uint8_t descramble[6]) { for (int i = 0; i < 6; i++) m_2012_2017_descramble[i] = descramble[i]; }
+ void set_201x_descramble(uint8_t reg0, uint8_t reg1, uint8_t reg2, uint8_t reg3, uint8_t reg4, uint8_t reg5);
virtual DECLARE_READ8_MEMBER(read) override;
virtual DECLARE_WRITE8_MEMBER(write) override;
@@ -62,6 +62,13 @@ public:
uint8_t get_m_read_bg4_bg3();
uint8_t get_speva2_speva0();
+ bool get_is_pal() { return m_is_pal; }
+ bool get_is_50hz() { return m_is_50hz; }
+
+protected:
+ bool m_is_pal;
+ bool m_is_50hz;
+
private:
devcb_read8 m_read_bg;
devcb_read8 m_read_sp;