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author hap <happppp@users.noreply.github.com>2021-02-23 16:46:05 +0100
committer hap <happppp@users.noreply.github.com>2021-02-23 21:36:21 +0100
commit3a20bc6fcef5c97def6fbdd2ecd0f0a0a5a3782e (patch)
tree5e66efd2d58dd0af791bed14e81c63c0c014b37e /src/devices
parent72cc27262212892f8159d77ab1167ee9938a3065 (diff)
hh_cops1: qkracerm ram is 8x12
Diffstat (limited to 'src/devices')
-rw-r--r--src/devices/cpu/cops1/cops1base.cpp2
-rw-r--r--src/devices/cpu/cops1/mm5799.cpp5
2 files changed, 6 insertions, 1 deletions
diff --git a/src/devices/cpu/cops1/cops1base.cpp b/src/devices/cpu/cops1/cops1base.cpp
index 08f882df59c..540724e61c2 100644
--- a/src/devices/cpu/cops1/cops1base.cpp
+++ b/src/devices/cpu/cops1/cops1base.cpp
@@ -25,6 +25,8 @@ TODO:
- documentation says that LB 10 is either 0 or 4, depending on RAM configuration,
but on qkracerm it's 5 (also confirmed in patent source code), so I assume
LB 10 is fully configurable as mask option
+- MM5799 RAM layout is derived from MCU decap, documentation suggests that the
+ secondary option is literally 6x16 but according to the decap it's 4x16 + 4x8
*/
diff --git a/src/devices/cpu/cops1/mm5799.cpp b/src/devices/cpu/cops1/mm5799.cpp
index bffb5e64a66..7ea0ce4a1ff 100644
--- a/src/devices/cpu/cops1/mm5799.cpp
+++ b/src/devices/cpu/cops1/mm5799.cpp
@@ -29,11 +29,14 @@ void mm5799_device::data_map(address_map &map)
// 8x12x4
for (int i = 0; i < 0x80; i += 0x10)
map(i | 0x04, i | 0x0f).ram();
+ map(0x00, 0x03).mirror(0x70).noprw();
}
else
{
// 6x16x4
- map(0x00, 0x5f).ram();
+ map(0x00, 0x3f).ram();
+ for (int i = 0x40; i < 0x80; i += 0x10)
+ map(i | 0x00, i | 0x07).ram().mirror(0x08);
}
}