diff options
author | 2019-06-01 13:16:13 +0200 | |
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committer | 2019-06-01 13:16:29 +0200 | |
commit | 22b7b3f4de27688543645390cf234f88dfb2332e (patch) | |
tree | 3ec741ecfbb8f9f3d849e2ebd6813b7aedc86b03 /src/devices | |
parent | a8bdd97c9611f8386a3a581c4b45c0c8e83a2180 (diff) |
added shared chessmachine device for Mephisto risc, chessmachine EC, chessmachine DR (nw)
Diffstat (limited to 'src/devices')
-rw-r--r-- | src/devices/bus/centronics/chessmec.cpp | 39 | ||||
-rw-r--r-- | src/devices/bus/centronics/chessmec.h | 42 | ||||
-rw-r--r-- | src/devices/bus/centronics/ctronics.cpp | 2 | ||||
-rw-r--r-- | src/devices/bus/isa/chessmdr.cpp | 124 | ||||
-rw-r--r-- | src/devices/bus/isa/chessmdr.h | 46 | ||||
-rw-r--r-- | src/devices/bus/isa/chessmsr.cpp (renamed from src/devices/bus/isa/chessm.cpp) | 53 | ||||
-rw-r--r-- | src/devices/bus/isa/chessmsr.h (renamed from src/devices/bus/isa/chessm.h) | 24 | ||||
-rw-r--r-- | src/devices/bus/isa/finalchs.cpp | 4 | ||||
-rw-r--r-- | src/devices/bus/isa/finalchs.h | 3 | ||||
-rw-r--r-- | src/devices/bus/isa/isa_cards.cpp | 9 | ||||
-rw-r--r-- | src/devices/machine/gen_latch.cpp | 9 |
11 files changed, 305 insertions, 50 deletions
diff --git a/src/devices/bus/centronics/chessmec.cpp b/src/devices/bus/centronics/chessmec.cpp new file mode 100644 index 00000000000..82a6c8e1c55 --- /dev/null +++ b/src/devices/bus/centronics/chessmec.cpp @@ -0,0 +1,39 @@ +// license:BSD-3-Clause +// copyright-holders:hap +/* + +The ChessMachine EC by Tasc +External module with ARM2 CPU, also sold under the Mephisto brand by H&G + +see chessmachine_device for technical notes + +*/ + +#include "emu.h" +#include "chessmec.h" + + +DEFINE_DEVICE_TYPE(CENTRONICS_CHESSMEC, centronics_chessmec_device, "centronics_chessmec", "The ChessMachine EC") + + +//------------------------------------------------- +// constructor +//------------------------------------------------- + +centronics_chessmec_device::centronics_chessmec_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + device_t(mconfig, CENTRONICS_CHESSMEC, tag, owner, clock), + device_centronics_peripheral_interface(mconfig, *this), + m_chessm(*this, "chessm") +{ } + + + +//------------------------------------------------- +// device_add_mconfig - add device configuration +//------------------------------------------------- + +void centronics_chessmec_device::device_add_mconfig(machine_config &config) +{ + CHESSMACHINE(config, m_chessm, 15'000'000); + m_chessm->data_out().set(FUNC(centronics_chessmec_device::output_busy)); +} diff --git a/src/devices/bus/centronics/chessmec.h b/src/devices/bus/centronics/chessmec.h new file mode 100644 index 00000000000..56da813f0b8 --- /dev/null +++ b/src/devices/bus/centronics/chessmec.h @@ -0,0 +1,42 @@ +// license:BSD-3-Clause +// copyright-holders:hap +/* + + The ChessMachine EC by Tasc + +*/ + +#ifndef MAME_BUS_CENTRONICS_CHESSMEC_H +#define MAME_BUS_CENTRONICS_CHESSMEC_H + +#pragma once + +#include "ctronics.h" +#include "machine/chessmachine.h" + + +class centronics_chessmec_device : public device_t, + public device_centronics_peripheral_interface +{ +public: + // construction/destruction + centronics_chessmec_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device-level overrides + virtual void device_start() override { } + virtual void device_add_mconfig(machine_config &config) override; + + virtual DECLARE_WRITE_LINE_MEMBER(input_data0) override { if (started()) m_chessm->data0_w(state); } + virtual DECLARE_WRITE_LINE_MEMBER(input_data1) override { if (started()) m_chessm->reset_w(state); } + virtual DECLARE_WRITE_LINE_MEMBER(input_data7) override { if (started()) m_chessm->data1_w(state); } + +private: + required_device<chessmachine_device> m_chessm; + +}; + + +DECLARE_DEVICE_TYPE(CENTRONICS_CHESSMEC, centronics_chessmec_device) + +#endif // MAME_BUS_CENTRONICS_CHESSMEC_H diff --git a/src/devices/bus/centronics/ctronics.cpp b/src/devices/bus/centronics/ctronics.cpp index 6a29a5b6a15..53d5ab7cb4a 100644 --- a/src/devices/bus/centronics/ctronics.cpp +++ b/src/devices/bus/centronics/ctronics.cpp @@ -133,6 +133,7 @@ device_centronics_peripheral_interface::~device_centronics_peripheral_interface( #include "nec_p72.h" #include "printer.h" #include "covox.h" +#include "chessmec.h" void centronics_devices(device_slot_interface &device) { @@ -145,4 +146,5 @@ void centronics_devices(device_slot_interface &device) device.option_add("printer", CENTRONICS_PRINTER); device.option_add("covox", CENTRONICS_COVOX); device.option_add("covox_stereo", CENTRONICS_COVOX_STEREO); + device.option_add("chessmec", CENTRONICS_CHESSMEC); } diff --git a/src/devices/bus/isa/chessmdr.cpp b/src/devices/bus/isa/chessmdr.cpp new file mode 100644 index 00000000000..02f73db82d2 --- /dev/null +++ b/src/devices/bus/isa/chessmdr.cpp @@ -0,0 +1,124 @@ +// license:BSD-3-Clause +// copyright-holders:hap +/* + +The ChessMachine DR by Tasc + +8-bit ISA card, 2nd version of The ChessMachine. +see chessmachine_device for technical notes + +*/ + +#include "emu.h" +#include "chessmdr.h" + + +DEFINE_DEVICE_TYPE(ISA8_CHESSMDR, isa8_chessmdr_device, "isa_chessmdr", "The ChessMachine DR") + +//------------------------------------------------- +// constructor +//------------------------------------------------- + +isa8_chessmdr_device::isa8_chessmdr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + device_t(mconfig, ISA8_CHESSMDR, tag, owner, clock), + device_isa8_card_interface(mconfig, *this), + m_chessm(*this, "chessm") +{ } + + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void isa8_chessmdr_device::device_start() +{ + set_isa_device(); + m_installed = false; +} + + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void isa8_chessmdr_device::device_reset() +{ + if (!m_installed) + { + // MAME doesn't allow reading ioport at device_start + u16 port = ioport("DSW")->read() * 0x40 + 0x10; + m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_chessmdr_device::chessmdr_r), this), write8_delegate(FUNC(isa8_chessmdr_device::chessmdr_w), this)); + + m_installed = true; + } +} + + + +//------------------------------------------------- +// input_ports - device-specific input ports +//------------------------------------------------- + +static INPUT_PORTS_START( chessmdr ) + PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x3D0 + PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CM_SW1:1,2,3,4") + PORT_DIPSETTING( 0x00, "0x010 (Invalid)" ) + PORT_DIPSETTING( 0x01, "0x050 (Invalid)" ) + PORT_DIPSETTING( 0x02, "0x090 (Invalid)" ) + PORT_DIPSETTING( 0x03, "0x0D0 (Invalid)" ) + PORT_DIPSETTING( 0x04, "0x110" ) + PORT_DIPSETTING( 0x05, "0x150" ) + PORT_DIPSETTING( 0x06, "0x190" ) + PORT_DIPSETTING( 0x07, "0x1D0" ) + PORT_DIPSETTING( 0x08, "0x210" ) + PORT_DIPSETTING( 0x09, "0x250" ) + PORT_DIPSETTING( 0x0a, "0x290" ) + PORT_DIPSETTING( 0x0b, "0x2D0" ) + PORT_DIPSETTING( 0x0c, "0x310" ) + PORT_DIPSETTING( 0x0d, "0x350" ) + PORT_DIPSETTING( 0x0e, "0x390" ) + PORT_DIPSETTING( 0x0f, "0x3D0" ) +INPUT_PORTS_END + +ioport_constructor isa8_chessmdr_device::device_input_ports() const +{ + return INPUT_PORTS_NAME(chessmdr); +} + + + +//------------------------------------------------- +// device_add_mconfig - add device configuration +//------------------------------------------------- + +void isa8_chessmdr_device::device_add_mconfig(machine_config &config) +{ + CHESSMACHINE(config, m_chessm, 15'000'000); +} + + + +/****************************************************************************** + I/O +******************************************************************************/ + +READ8_MEMBER(isa8_chessmdr_device::chessmdr_r) +{ + if (offset == 1) + return m_chessm->data_r() ? 0 : 0x80; + else + return 0xff; +} + +WRITE8_MEMBER(isa8_chessmdr_device::chessmdr_w) +{ + if (offset == 0) + { + m_chessm->data0_w(data & 1); + m_chessm->data1_w(data & 0x80); + m_chessm->reset_w(data & 2); + } +} + diff --git a/src/devices/bus/isa/chessmdr.h b/src/devices/bus/isa/chessmdr.h new file mode 100644 index 00000000000..8607dac26b0 --- /dev/null +++ b/src/devices/bus/isa/chessmdr.h @@ -0,0 +1,46 @@ +// license:BSD-3-Clause +// copyright-holders:hap +/* + + The ChessMachine DR by Tasc + +*/ + +#ifndef MAME_BUS_ISA_CHESSMDR_H +#define MAME_BUS_ISA_CHESSMDR_H + +#pragma once + +#include "isa.h" +#include "machine/chessmachine.h" + + +class isa8_chessmdr_device : + public device_t, + public device_isa8_card_interface +{ +public: + // construction/destruction + isa8_chessmdr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override; + + virtual ioport_constructor device_input_ports() const override; + +private: + required_device<chessmachine_device> m_chessm; + + bool m_installed; + + DECLARE_READ8_MEMBER(chessmdr_r); + DECLARE_WRITE8_MEMBER(chessmdr_w); +}; + + +DECLARE_DEVICE_TYPE(ISA8_CHESSMDR, isa8_chessmdr_device) + +#endif // MAME_BUS_ISA_CHESSMDR_H diff --git a/src/devices/bus/isa/chessm.cpp b/src/devices/bus/isa/chessmsr.cpp index 9ed0f37eaf3..137af674a0f 100644 --- a/src/devices/bus/isa/chessm.cpp +++ b/src/devices/bus/isa/chessmsr.cpp @@ -2,36 +2,33 @@ // copyright-holders:hap /* -The ChessMachine by Tasc +The ChessMachine SR by Tasc 8-bit ISA card, successor of The Final ChessCard. -No ROM on the card this time, the chess program is sent to RAM instead. + +I/O is similar to The Final ChessCard, with two 74374 latches, but no ROM. +There's a 74590 counter chip for writing the initial bootstrap. The rest +of the program is sent to RAM via the latches. VLSI VY86C010-12QC (ARM2), seen with 30MHz XTAL, but XTAL label usually scratched off. 128KB, 512KB, or 1MB RAM. 512KB version probably the most common. It looks like Gideon 2.1 only sees up to 512KB RAM, The King up to 2MB RAM. -Also seen with VY86C061PSTC (ARM6) @ 32MHz, very rare or prototype. - -3 models exist: SR, DR, EC. SR and DR are ISA cards, EC is an external module (serial port). -It was also released for the Amiga. - -TODO: -- add model DR (missing bootstrap ROM dump?) +Also seen with VY86C061PSTC (ARM6) @ 32MHz, very rare, aka "Madrid" version. */ #include "emu.h" -#include "chessm.h" +#include "chessmsr.h" -DEFINE_DEVICE_TYPE(ISA8_CHESSM, isa8_chessm_device, "isa_chessm", "ChessMachine") +DEFINE_DEVICE_TYPE(ISA8_CHESSMSR, isa8_chessmsr_device, "isa_chessmsr", "The ChessMachine SR") //------------------------------------------------- // constructor //------------------------------------------------- -isa8_chessm_device::isa8_chessm_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : - device_t(mconfig, ISA8_CHESSM, tag, owner, clock), +isa8_chessmsr_device::isa8_chessmsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + device_t(mconfig, ISA8_CHESSMSR, tag, owner, clock), device_isa8_card_interface(mconfig, *this), m_maincpu(*this, "maincpu"), m_mainlatch(*this, "mainlatch"), @@ -45,7 +42,7 @@ isa8_chessm_device::isa8_chessm_device(const machine_config &mconfig, const char // device_start - device-specific startup //------------------------------------------------- -void isa8_chessm_device::device_start() +void isa8_chessmsr_device::device_start() { set_isa_device(); m_installed = false; @@ -57,13 +54,13 @@ void isa8_chessm_device::device_start() // device_reset - device-specific reset //------------------------------------------------- -void isa8_chessm_device::device_reset() +void isa8_chessmsr_device::device_reset() { if (!m_installed) { // MAME doesn't allow reading ioport at device_start u16 port = ioport("DSW")->read() * 0x40 + 0x10; - m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_chessm_device::chessm_r), this), write8_delegate(FUNC(isa8_chessm_device::chessm_w), this)); + m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_chessmsr_device::chessmsr_r), this), write8_delegate(FUNC(isa8_chessmsr_device::chessmsr_w), this)); m_maincpu->set_unscaled_clock(ioport("CPU")->read() ? (32_MHz_XTAL) : (30_MHz_XTAL/2)); @@ -76,10 +73,10 @@ void isa8_chessm_device::device_reset() } } -void isa8_chessm_device::device_reset_after_children() +void isa8_chessmsr_device::device_reset_after_children() { // hold ARM CPU in reset state - chessm_w(machine().dummy_space(), 1, 0); + chessmsr_w(machine().dummy_space(), 1, 0); } @@ -88,8 +85,8 @@ void isa8_chessm_device::device_reset_after_children() // input_ports - device-specific input ports //------------------------------------------------- -static INPUT_PORTS_START( chessm ) - PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x390 +static INPUT_PORTS_START( chessmsr ) + PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x3D0 PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CM_SW1:1,2,3,4") PORT_DIPSETTING( 0x00, "0x010 (Invalid)" ) PORT_DIPSETTING( 0x01, "0x050 (Invalid)" ) @@ -106,7 +103,7 @@ static INPUT_PORTS_START( chessm ) PORT_DIPSETTING( 0x0c, "0x310" ) PORT_DIPSETTING( 0x0d, "0x350" ) PORT_DIPSETTING( 0x0e, "0x390" ) - PORT_DIPSETTING( 0x0f, "0x3D0 (Invalid)" ) + PORT_DIPSETTING( 0x0f, "0x3D0" ) PORT_START("CPU") PORT_CONFNAME( 0x01, 0x00, "CPU Type" ) @@ -121,9 +118,9 @@ static INPUT_PORTS_START( chessm ) PORT_CONFSETTING( 21, "2MB" ) // unofficial INPUT_PORTS_END -ioport_constructor isa8_chessm_device::device_input_ports() const +ioport_constructor isa8_chessmsr_device::device_input_ports() const { - return INPUT_PORTS_NAME(chessm); + return INPUT_PORTS_NAME(chessmsr); } @@ -132,10 +129,10 @@ ioport_constructor isa8_chessm_device::device_input_ports() const // device_add_mconfig - add device configuration //------------------------------------------------- -void isa8_chessm_device::device_add_mconfig(machine_config &config) +void isa8_chessmsr_device::device_add_mconfig(machine_config &config) { ARM(config, m_maincpu, 30_MHz_XTAL/2); - m_maincpu->set_addrmap(AS_PROGRAM, &isa8_chessm_device::chessm_mem); + m_maincpu->set_addrmap(AS_PROGRAM, &isa8_chessmsr_device::chessmsr_mem); m_maincpu->set_copro_type(arm_cpu_device::copro_type::VL86C020); GENERIC_LATCH_8(config, m_mainlatch); @@ -151,7 +148,7 @@ void isa8_chessm_device::device_add_mconfig(machine_config &config) // External handlers -READ8_MEMBER(isa8_chessm_device::chessm_r) +READ8_MEMBER(isa8_chessmsr_device::chessmsr_r) { if (offset == 0) return m_mainlatch->read(); @@ -159,7 +156,7 @@ READ8_MEMBER(isa8_chessm_device::chessm_r) return m_mainlatch->pending_r() ? 0 : 2; } -WRITE8_MEMBER(isa8_chessm_device::chessm_w) +WRITE8_MEMBER(isa8_chessmsr_device::chessmsr_w) { if (offset == 0) { @@ -181,7 +178,7 @@ WRITE8_MEMBER(isa8_chessm_device::chessm_w) // Internal (on-card CPU) -void isa8_chessm_device::chessm_mem(address_map &map) +void isa8_chessmsr_device::chessmsr_mem(address_map &map) { map(0x00380000, 0x00380000).mirror(0x00000008).r(m_sublatch, FUNC(generic_latch_8_device::read)).w(m_mainlatch, FUNC(generic_latch_8_device::write)); } diff --git a/src/devices/bus/isa/chessm.h b/src/devices/bus/isa/chessmsr.h index 8b7585ac838..2d79226d4ce 100644 --- a/src/devices/bus/isa/chessm.h +++ b/src/devices/bus/isa/chessmsr.h @@ -2,12 +2,12 @@ // copyright-holders:hap /* - The ChessMachine by Tasc + The ChessMachine SR by Tasc */ -#ifndef MAME_BUS_ISA_CHESSM_H -#define MAME_BUS_ISA_CHESSM_H +#ifndef MAME_BUS_ISA_CHESSMSR_H +#define MAME_BUS_ISA_CHESSMSR_H #pragma once @@ -16,22 +16,21 @@ #include "machine/gen_latch.h" -class isa8_chessm_device : +class isa8_chessmsr_device : public device_t, public device_isa8_card_interface { public: // construction/destruction - isa8_chessm_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + isa8_chessmsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); protected: // device-level overrides virtual void device_start() override; virtual void device_reset() override; virtual void device_reset_after_children() override; - - // optional information overrides virtual void device_add_mconfig(machine_config &config) override; + virtual ioport_constructor device_input_ports() const override; private: @@ -44,14 +43,13 @@ private: bool m_suspended; bool m_installed; - DECLARE_READ8_MEMBER(chessm_r); - DECLARE_WRITE8_MEMBER(chessm_w); + DECLARE_READ8_MEMBER(chessmsr_r); + DECLARE_WRITE8_MEMBER(chessmsr_w); - void chessm_mem(address_map &map); + void chessmsr_mem(address_map &map); }; -DECLARE_DEVICE_TYPE(ISA8_CHESSM, isa8_chessm_device) - +DECLARE_DEVICE_TYPE(ISA8_CHESSMSR, isa8_chessmsr_device) -#endif // MAME_BUS_ISA_CHESSM_H +#endif // MAME_BUS_ISA_CHESSMSR_H diff --git a/src/devices/bus/isa/finalchs.cpp b/src/devices/bus/isa/finalchs.cpp index c53ecd2b76d..84b81220c42 100644 --- a/src/devices/bus/isa/finalchs.cpp +++ b/src/devices/bus/isa/finalchs.cpp @@ -8,7 +8,7 @@ The Final ChessCard by Tasc It is similar to the C64 version, actually not as impressive since a PC from around 1989 should be able to run a good chess game by itself. -Tasc later released The ChessMachine ISA card, see chessm.cpp. +Tasc later released The ChessMachine ISA card, see chessm*.cpp. Multiple ROM revisions were made. Version 2.0 is compatible with the initial 1989 software version. Version 3.6 works with the newer software package, including the @@ -20,7 +20,7 @@ one that came with The ChessMachine. #include "finalchs.h" -DEFINE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device, "isa_finalchs", "Final ChessCard") +DEFINE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device, "isa_finalchs", "The Final ChessCard") //------------------------------------------------- // constructor diff --git a/src/devices/bus/isa/finalchs.h b/src/devices/bus/isa/finalchs.h index 607b311f3c4..d00573ebab6 100644 --- a/src/devices/bus/isa/finalchs.h +++ b/src/devices/bus/isa/finalchs.h @@ -28,9 +28,9 @@ protected: // device-level overrides virtual void device_start() override; virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override; // optional information overrides - virtual void device_add_mconfig(machine_config &config) override; virtual const tiny_rom_entry *device_rom_region() const override; virtual ioport_constructor device_input_ports() const override; @@ -50,5 +50,4 @@ private: DECLARE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device) - #endif // MAME_BUS_ISA_FINALCHS_H diff --git a/src/devices/bus/isa/isa_cards.cpp b/src/devices/bus/isa/isa_cards.cpp index d2eabd9d547..c97866bdf5e 100644 --- a/src/devices/bus/isa/isa_cards.cpp +++ b/src/devices/bus/isa/isa_cards.cpp @@ -73,7 +73,8 @@ #include "pds.h" // other -#include "chessm.h" +#include "chessmdr.h" +#include "chessmsr.h" #include "finalchs.h" @@ -122,7 +123,8 @@ void pc_isa8_cards(device_slot_interface &device) device.option_add("pds", ISA8_PDS); device.option_add("lba_enhancer", ISA8_LBA_ENHANCER); device.option_add("asc88", ASC88); - device.option_add("chessm", ISA8_CHESSM); + device.option_add("chessmdr", ISA8_CHESSMDR); + device.option_add("chessmsr", ISA8_CHESSMSR); device.option_add("finalchs", ISA8_FINALCHS); } @@ -161,7 +163,8 @@ void pc_isa16_cards(device_slot_interface &device) device.option_add("dectalk", ISA8_DECTALK); device.option_add("pds", ISA8_PDS); device.option_add("lba_enhancer", ISA8_LBA_ENHANCER); - device.option_add("chessm", ISA8_CHESSM); + device.option_add("chessmdr", ISA8_CHESSMDR); + device.option_add("chessmsr", ISA8_CHESSMSR); device.option_add("finalchs", ISA8_FINALCHS); // 16-bit device.option_add("ide", ISA16_IDE); diff --git a/src/devices/machine/gen_latch.cpp b/src/devices/machine/gen_latch.cpp index b96d39a14be..2e3929b108a 100644 --- a/src/devices/machine/gen_latch.cpp +++ b/src/devices/machine/gen_latch.cpp @@ -9,6 +9,11 @@ #include "emu.h" #include "gen_latch.h" +#define LOG_WARN (1U << 0) +#define VERBOSE (LOG_WARN) + +#include "logmacro.h" + //************************************************************************** // DEVICE TYPE DEFINITIONS @@ -154,7 +159,7 @@ void generic_latch_8_device::sync_callback(void *ptr, s32 param) // if the latch has been written and the value is changed, log a warning if (is_latch_written() && m_latched_value != value) - logerror("Warning: latch written before being read. Previous: %02x, new: %02x\n", m_latched_value, value); + LOGMASKED(LOG_WARN, "Warning: latch written before being read. Previous: %02x, new: %02x\n", m_latched_value, value); // store the new value and mark it not read m_latched_value = value; @@ -225,7 +230,7 @@ void generic_latch_16_device::sync_callback(void *ptr, s32 param) // if the latch has been written and the value is changed, log a warning if (is_latch_written() && m_latched_value != value) - logerror("Warning: latch written before being read. Previous: %02x, new: %02x\n", m_latched_value, value); + LOGMASKED(LOG_WARN, "Warning: latch written before being read. Previous: %02x, new: %02x\n", m_latched_value, value); // store the new value and mark it not read m_latched_value = value; |