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author Vas Crabb <vas@vastheman.com>2021-01-24 13:33:07 +1100
committer Vas Crabb <vas@vastheman.com>2021-01-24 13:33:07 +1100
commit78f6ff34a5d8839a88c8cf36703cf8afc67139a4 (patch)
treec58abf068ad2e6f2e5bb621f1cc0fe1d489b7f54 /src/devices/machine
parent051119c0914d40e086c42460650a34697d85edfd (diff)
srcclean in preparation for branching release
Diffstat (limited to 'src/devices/machine')
-rw-r--r--src/devices/machine/m950x0.cpp28
-rw-r--r--src/devices/machine/m950x0.h34
-rw-r--r--src/devices/machine/sa1110.cpp18
-rw-r--r--src/devices/machine/sa1110.h276
-rw-r--r--src/devices/machine/sa1111.cpp2
-rw-r--r--src/devices/machine/sa1111.h124
-rw-r--r--src/devices/machine/swim1.cpp2
-rw-r--r--src/devices/machine/swim2.cpp6
-rw-r--r--src/devices/machine/swim2.h4
9 files changed, 247 insertions, 247 deletions
diff --git a/src/devices/machine/m950x0.cpp b/src/devices/machine/m950x0.cpp
index ce85c48a9b6..9d42166804c 100644
--- a/src/devices/machine/m950x0.cpp
+++ b/src/devices/machine/m950x0.cpp
@@ -4,30 +4,30 @@
m950x0.cpp
- STmicro M95010/20/40 SPI-bus EEPROM
+ STmicro M95010/20/40 SPI-bus EEPROM
- Common characteristics:
- - 16-byte page size
- - Write protection selectable in quarter, half, or full sizes
+ Common characteristics:
+ - 16-byte page size
+ - Write protection selectable in quarter, half, or full sizes
- Part variants with a -DF designation have additional support for an
- identification page, which is not currently emulated.
+ Part variants with a -DF designation have additional support for an
+ identification page, which is not currently emulated.
- Sizes:
- M95010 - 1kbit
- M95020 - 2kbit
- M95040 - 4kbit, slightly altered instructions for 9th address bit
+ Sizes:
+ M95010 - 1kbit
+ M95020 - 2kbit
+ M95040 - 4kbit, slightly altered instructions for 9th address bit
- Current issues:
- - Implementation currently operates in a parallel manner, rather than
- serial.
+ Current issues:
+ - Implementation currently operates in a parallel manner, rather than
+ serial.
***************************************************************************/
#include "emu.h"
#include "m950x0.h"
-#define VERBOSE (0)
+#define VERBOSE (0)
#include "logmacro.h"
DEFINE_DEVICE_TYPE(M95010, m95010_device, "m95010", "STmicro M95010 1kbit SPI EEPROM")
diff --git a/src/devices/machine/m950x0.h b/src/devices/machine/m950x0.h
index c7becdbce74..0eceb6fab21 100644
--- a/src/devices/machine/m950x0.h
+++ b/src/devices/machine/m950x0.h
@@ -4,7 +4,7 @@
m950x0.h
- STmicro M95010/20/40 SPI-bus EEPROM
+ STmicro M95010/20/40 SPI-bus EEPROM
***************************************************************************/
@@ -46,21 +46,21 @@ protected:
enum : uint8_t
{
- INSN_WRSR0 = 0x01,
- INSN_WRITE0 = 0x02,
- INSN_READ0 = 0x03,
- INSN_WRDI0 = 0x04,
- INSN_RDSR0 = 0x05,
- INSN_WREN0 = 0x06,
-
- INSN_WRSR1 = 0x09,
- INSN_WRITE1 = 0x0a,
- INSN_READ1 = 0x0b,
- INSN_WRDI1 = 0x0c,
- INSN_RDSR1 = 0x0d,
- INSN_WREN1 = 0x0e,
-
- STATUS_WEL_BIT = 1
+ INSN_WRSR0 = 0x01,
+ INSN_WRITE0 = 0x02,
+ INSN_READ0 = 0x03,
+ INSN_WRDI0 = 0x04,
+ INSN_RDSR0 = 0x05,
+ INSN_WREN0 = 0x06,
+
+ INSN_WRSR1 = 0x09,
+ INSN_WRITE1 = 0x0a,
+ INSN_READ1 = 0x0b,
+ INSN_WRDI1 = 0x0c,
+ INSN_RDSR1 = 0x0d,
+ INSN_WREN1 = 0x0e,
+
+ STATUS_WEL_BIT = 1
};
const bool m_check_a8;
@@ -94,4 +94,4 @@ DECLARE_DEVICE_TYPE(M95010, m95010_device)
DECLARE_DEVICE_TYPE(M95020, m95020_device)
DECLARE_DEVICE_TYPE(M95040, m95040_device)
-#endif // MAME_MACHINE_M950X0_H \ No newline at end of file
+#endif // MAME_MACHINE_M950X0_H
diff --git a/src/devices/machine/sa1110.cpp b/src/devices/machine/sa1110.cpp
index 480f9998131..86e17a10d4f 100644
--- a/src/devices/machine/sa1110.cpp
+++ b/src/devices/machine/sa1110.cpp
@@ -10,7 +10,7 @@
#include "sa1110.h"
#define LOG_UNKNOWN (1 << 1)
-#define LOG_ICP (1 << 2)
+#define LOG_ICP (1 << 2)
#define LOG_UART3 (1 << 3)
#define LOG_UART3_HF (1 << 4)
#define LOG_MCP (1 << 5)
@@ -18,16 +18,16 @@
#define LOG_OSTIMER (1 << 7)
#define LOG_OSTIMER_HF (1 << 8)
#define LOG_RTC (1 << 9)
-#define LOG_RTC_HF (1 << 10)
+#define LOG_RTC_HF (1 << 10)
#define LOG_POWER (1 << 11)
-#define LOG_POWER_HF (1 << 12)
+#define LOG_POWER_HF (1 << 12)
#define LOG_RESET (1 << 13)
#define LOG_GPIO (1 << 14)
#define LOG_GPIO_HF (1 << 15)
#define LOG_INTC (1 << 16)
-#define LOG_PPC (1 << 17)
-#define LOG_DMA (1 << 18)
-#define LOG_UDC (1 << 19)
+#define LOG_PPC (1 << 17)
+#define LOG_DMA (1 << 18)
+#define LOG_UDC (1 << 19)
#define LOG_ALL (LOG_UNKNOWN | LOG_ICP | LOG_UART3 | LOG_MCP | LOG_OSTIMER | LOG_RTC | LOG_POWER | LOG_RESET | LOG_GPIO | LOG_INTC | LOG_PPC | LOG_DMA | LOG_UDC)
#define VERBOSE (0)
@@ -297,7 +297,7 @@ void sa1110_periphs_device::icp_w(offs_t offset, uint32_t data, uint32_t mem_mas
//parity_t parity = PARITY_NONE;
//if (BIT(data, 0))
//{
- // parity = (BIT(data, 1) ? PARITY_EVEN : PARITY_ODD);
+ // parity = (BIT(data, 1) ? PARITY_EVEN : PARITY_ODD);
//}
//set_data_frame(1, BIT(data, 3) ? 8 : 7, parity, stop_bits);
@@ -314,7 +314,7 @@ void sa1110_periphs_device::icp_w(offs_t offset, uint32_t data, uint32_t mem_mas
//const uint8_t old = m_uart_regs.utcr[1] & 0x0f;
COMBINE_DATA(&m_icp_regs.uart.utcr[1]);
//if ((m_uart_regs.utcr[1] & 0x0f) != old)
- // icp_uart_recalculate_divisor();
+ // icp_uart_recalculate_divisor();
break;
}
case REG_UTCR2:
@@ -324,7 +324,7 @@ void sa1110_periphs_device::icp_w(offs_t offset, uint32_t data, uint32_t mem_mas
//const uint8_t old = m_uart_regs.utcr[2] & 0xff;
COMBINE_DATA(&m_icp_regs.uart.utcr[2]);
//if ((m_uart_regs.utcr[2] & 0xff) != old)
- // icp_uart_recalculate_divisor();
+ // icp_uart_recalculate_divisor();
break;
}
case REG_UTCR3:
diff --git a/src/devices/machine/sa1110.h b/src/devices/machine/sa1110.h
index 7693e09dfa3..3ef8e79042b 100644
--- a/src/devices/machine/sa1110.h
+++ b/src/devices/machine/sa1110.h
@@ -156,26 +156,26 @@ protected:
// register offsets
enum
{
- UDC_BASE_ADDR = 0x80000000,
- REG_UDCCR = (0x00000000 >> 2),
- REG_UDCAR = (0x00000004 >> 2),
- REG_UDCOMP = (0x00000008 >> 2),
- REG_UDCIMP = (0x0000000c >> 2),
- REG_UDCCS0 = (0x00000010 >> 2),
- REG_UDCCS1 = (0x00000014 >> 2),
- REG_UDCCS2 = (0x00000018 >> 2),
- REG_UDCD0 = (0x0000001c >> 2),
- REG_UDCWC = (0x00000020 >> 2),
- REG_UDCDR = (0x00000028 >> 2),
- REG_UDCSR = (0x00000030 >> 2),
-
- ICP_BASE_ADDR = 0x80030000,
- REG_UTCR4 = (0x00000010 >> 2),
- REG_HSCR0 = (0x00000060 >> 2),
- REG_HSCR1 = (0x00000064 >> 2),
- REG_HSDR = (0x0000006c >> 2),
- REG_HSSR0 = (0x00000074 >> 2),
- REG_HSSR1 = (0x00000078 >> 2),
+ UDC_BASE_ADDR = 0x80000000,
+ REG_UDCCR = (0x00000000 >> 2),
+ REG_UDCAR = (0x00000004 >> 2),
+ REG_UDCOMP = (0x00000008 >> 2),
+ REG_UDCIMP = (0x0000000c >> 2),
+ REG_UDCCS0 = (0x00000010 >> 2),
+ REG_UDCCS1 = (0x00000014 >> 2),
+ REG_UDCCS2 = (0x00000018 >> 2),
+ REG_UDCD0 = (0x0000001c >> 2),
+ REG_UDCWC = (0x00000020 >> 2),
+ REG_UDCDR = (0x00000028 >> 2),
+ REG_UDCSR = (0x00000030 >> 2),
+
+ ICP_BASE_ADDR = 0x80030000,
+ REG_UTCR4 = (0x00000010 >> 2),
+ REG_HSCR0 = (0x00000060 >> 2),
+ REG_HSCR1 = (0x00000064 >> 2),
+ REG_HSDR = (0x0000006c >> 2),
+ REG_HSSR0 = (0x00000074 >> 2),
+ REG_HSSR1 = (0x00000078 >> 2),
UART_BASE_ADDR = 0x80050000,
REG_UTCR0 = (0x00000000 >> 2),
@@ -247,73 +247,73 @@ protected:
REG_ICFP = (0x00000010 >> 2),
REG_ICPR = (0x00000020 >> 2),
- PPC_BASE_ADDR = 0x90060000,
- REG_PPDR = (0x00000000 >> 2),
- REG_PPSR = (0x00000004 >> 2),
- REG_PPAR = (0x00000008 >> 2),
- REG_PSDR = (0x0000000c >> 2),
- REG_PPFR = (0x00000010 >> 2),
-
- DMA_BASE_ADDR = 0xb0000000,
- REG_DDAR = (0x00000000 >> 2),
- REG_DSSR = (0x00000004 >> 2),
- REG_DCSR = (0x00000008 >> 2),
- REG_DSR = (0x0000000c >> 2),
- REG_DBSA = (0x00000010 >> 2),
- REG_DBTA = (0x00000014 >> 2),
- REG_DBSB = (0x00000018 >> 2),
- REG_DBTB = (0x0000001c >> 2)
+ PPC_BASE_ADDR = 0x90060000,
+ REG_PPDR = (0x00000000 >> 2),
+ REG_PPSR = (0x00000004 >> 2),
+ REG_PPAR = (0x00000008 >> 2),
+ REG_PSDR = (0x0000000c >> 2),
+ REG_PPFR = (0x00000010 >> 2),
+
+ DMA_BASE_ADDR = 0xb0000000,
+ REG_DDAR = (0x00000000 >> 2),
+ REG_DSSR = (0x00000004 >> 2),
+ REG_DCSR = (0x00000008 >> 2),
+ REG_DSR = (0x0000000c >> 2),
+ REG_DBSA = (0x00000010 >> 2),
+ REG_DBTA = (0x00000014 >> 2),
+ REG_DBSB = (0x00000018 >> 2),
+ REG_DBTB = (0x0000001c >> 2)
};
// register contents
enum : uint32_t
{
- UDCCR_UDD_BIT = 0,
- UDCCR_UDA_BIT = 1,
- UDCCR_RESM_BIT = 2,
- UDCCR_EIM_BIT = 3,
- UDCCR_RIM_BIT = 4,
- UDCCR_TIM_BIT = 5,
- UDCCR_SUSM_BIT = 6,
- UDCCR_WRITE_MASK = 0x7d,
-
- UDCAR_WRITE_MASK = 0x7f,
-
- UDCOMP_WRITE_MASK = 0xff,
-
- UDCIMP_WRITE_MASK = 0xff,
-
- UDCCS0_OPR_BIT = 0,
- UDCCS0_IPR_BIT = 1,
- UDCCS0_SST_BIT = 2,
- UDCCS0_FST_BIT = 3,
- UDCCS0_DE_BIT = 4,
- UDCCS0_SE_BIT = 5,
- UDCCS0_SO_BIT = 6,
- UDCCS0_SSE_BIT = 7,
-
- UDCCS1_RFS_BIT = 0,
- UDCCS1_RPC_BIT = 1,
- UDCCS1_RPE_BIT = 2,
- UDCCS1_SST_BIT = 3,
- UDCCS1_FST_BIT = 4,
- UDCCS1_RNE_BIT = 5,
-
- UDCCS2_TFS_BIT = 0,
- UDCCS2_TPC_BIT = 1,
- UDCCS2_TPE_BIT = 2,
- UDCCS2_TUR_BIT = 3,
- UDCCS2_SST_BIT = 4,
- UDCCS2_FST_BIT = 5,
-
- UDCWC_WRITE_MASK = 0x0f,
-
- UDCSR_EIR_BIT = 0,
- UDCSR_RIR_BIT = 1,
- UDCSR_TIR_BIT = 2,
- UDCSR_SUSIR_BIT = 3,
- UDCSR_RESIR_BIT = 4,
- UDCSR_RSTIR_BIT = 5,
+ UDCCR_UDD_BIT = 0,
+ UDCCR_UDA_BIT = 1,
+ UDCCR_RESM_BIT = 2,
+ UDCCR_EIM_BIT = 3,
+ UDCCR_RIM_BIT = 4,
+ UDCCR_TIM_BIT = 5,
+ UDCCR_SUSM_BIT = 6,
+ UDCCR_WRITE_MASK = 0x7d,
+
+ UDCAR_WRITE_MASK = 0x7f,
+
+ UDCOMP_WRITE_MASK = 0xff,
+
+ UDCIMP_WRITE_MASK = 0xff,
+
+ UDCCS0_OPR_BIT = 0,
+ UDCCS0_IPR_BIT = 1,
+ UDCCS0_SST_BIT = 2,
+ UDCCS0_FST_BIT = 3,
+ UDCCS0_DE_BIT = 4,
+ UDCCS0_SE_BIT = 5,
+ UDCCS0_SO_BIT = 6,
+ UDCCS0_SSE_BIT = 7,
+
+ UDCCS1_RFS_BIT = 0,
+ UDCCS1_RPC_BIT = 1,
+ UDCCS1_RPE_BIT = 2,
+ UDCCS1_SST_BIT = 3,
+ UDCCS1_FST_BIT = 4,
+ UDCCS1_RNE_BIT = 5,
+
+ UDCCS2_TFS_BIT = 0,
+ UDCCS2_TPC_BIT = 1,
+ UDCCS2_TPE_BIT = 2,
+ UDCCS2_TUR_BIT = 3,
+ UDCCS2_SST_BIT = 4,
+ UDCCS2_FST_BIT = 5,
+
+ UDCWC_WRITE_MASK = 0x0f,
+
+ UDCSR_EIR_BIT = 0,
+ UDCSR_RIR_BIT = 1,
+ UDCSR_TIR_BIT = 2,
+ UDCSR_SUSIR_BIT = 3,
+ UDCSR_RESIR_BIT = 4,
+ UDCSR_RSTIR_BIT = 5,
UART3_FIFO_PRE = 8,
UART3_FIFO_FRE = 9,
@@ -326,8 +326,8 @@ protected:
UTCR3_TIE_BIT = 4,
UTCR3_LBM_BIT = 5,
- UTCR4_HSE_BIT = 0,
- UTCR4_LPM_BIT = 1,
+ UTCR4_HSE_BIT = 0,
+ UTCR4_LPM_BIT = 1,
UTSR0_TFS_BIT = 0,
UTSR0_RFS_BIT = 1,
@@ -343,36 +343,36 @@ protected:
UTSR1_FRE_BIT = 4,
UTSR1_ROR_BIT = 5,
- HSCR0_ITR_BIT = 0,
- HSCR0_LBM_BIT = 1,
- HSCR0_TUS_BIT = 2,
- HSCR0_TXE_BIT = 3,
- HSCR0_RXE_BIT = 4,
- HSCR0_RIE_BIT = 5,
- HSCR0_TIE_BIT = 6,
- HSCR0_AME_BIT = 7,
-
- HSCR2_TXP_BIT = 18,
- HSCR2_RXP_BIT = 19,
-
- HSDR_EOF_BIT = 8,
- HSDR_CRE_BIT = 9,
- HSDR_ROR_BIT = 10,
-
- HSSR0_EIF_BIT = 0,
- HSSR0_TUR_BIT = 1,
- HSSR0_RAB_BIT = 2,
- HSSR0_TFS_BIT = 3,
- HSSR0_RFS_BIT = 4,
- HSSR0_FRE_BIT = 5,
-
- HSSR1_RSY_BIT = 0,
- HSSR1_TBY_BIT = 1,
- HSSR1_RNE_BIT = 2,
- HSSR1_TNF_BIT = 3,
- HSSR1_EOF_BIT = 4,
- HSSR1_CRE_BIT = 5,
- HSSR1_ROR_BIT = 6,
+ HSCR0_ITR_BIT = 0,
+ HSCR0_LBM_BIT = 1,
+ HSCR0_TUS_BIT = 2,
+ HSCR0_TXE_BIT = 3,
+ HSCR0_RXE_BIT = 4,
+ HSCR0_RIE_BIT = 5,
+ HSCR0_TIE_BIT = 6,
+ HSCR0_AME_BIT = 7,
+
+ HSCR2_TXP_BIT = 18,
+ HSCR2_RXP_BIT = 19,
+
+ HSDR_EOF_BIT = 8,
+ HSDR_CRE_BIT = 9,
+ HSDR_ROR_BIT = 10,
+
+ HSSR0_EIF_BIT = 0,
+ HSSR0_TUR_BIT = 1,
+ HSSR0_RAB_BIT = 2,
+ HSSR0_TFS_BIT = 3,
+ HSSR0_RFS_BIT = 4,
+ HSSR0_FRE_BIT = 5,
+
+ HSSR1_RSY_BIT = 0,
+ HSSR1_TBY_BIT = 1,
+ HSSR1_RNE_BIT = 2,
+ HSSR1_TNF_BIT = 3,
+ HSSR1_EOF_BIT = 4,
+ HSSR1_CRE_BIT = 5,
+ HSSR1_ROR_BIT = 6,
MCCR0_ASD_BIT = 0,
MCCR0_ASD_MASK = 0x0000007f,
@@ -443,25 +443,25 @@ protected:
RTSR_HZE_BIT = 3,
RTSR_HZE_MASK = (1 << RTSR_HZE_BIT),
- DDAR_RW_BIT = 0,
- DDAR_E_BIT = 1,
- DDAR_BS_BIT = 2,
- DDAR_DW_BIT = 3,
- DDAR_DA0_BIT = 4,
- DDAR_DA0_MASK = 0x000000f0,
- DDAR_DA8_BIT = 8,
- DDAR_DA8_MASK = 0xffffff00,
-
- DSR_RUN_BIT = 0,
- DSR_IE_BIT = 1,
- DSR_ERROR_BIT = 2,
- DSR_DONEA_BIT = 3,
- DSR_STRTA_BIT = 4,
- DSR_DONEB_BIT = 5,
- DSR_STRTB_BIT = 6,
- DSR_BIU_BIT = 7,
-
- DBT_MASK = 0x00001fff
+ DDAR_RW_BIT = 0,
+ DDAR_E_BIT = 1,
+ DDAR_BS_BIT = 2,
+ DDAR_DW_BIT = 3,
+ DDAR_DA0_BIT = 4,
+ DDAR_DA0_MASK = 0x000000f0,
+ DDAR_DA8_BIT = 8,
+ DDAR_DA8_MASK = 0xffffff00,
+
+ DSR_RUN_BIT = 0,
+ DSR_IE_BIT = 1,
+ DSR_ERROR_BIT = 2,
+ DSR_DONEA_BIT = 3,
+ DSR_STRTA_BIT = 4,
+ DSR_DONEB_BIT = 5,
+ DSR_STRTB_BIT = 6,
+ DSR_BIU_BIT = 7,
+
+ DBT_MASK = 0x00001fff
};
// interrupt bits
@@ -715,9 +715,9 @@ protected:
uint32_t dbt[2];
};
- udc_regs m_udc_regs;
+ udc_regs m_udc_regs;
uart_regs m_uart_regs;
- icp_regs m_icp_regs;
+ icp_regs m_icp_regs;
mcp_regs m_mcp_regs;
ssp_regs m_ssp_regs;
ostimer_regs m_ostmr_regs;
@@ -726,9 +726,9 @@ protected:
uint32_t m_rcsr;
gpio_regs m_gpio_regs;
intc_regs m_intc_regs;
- ppc_regs m_ppc_regs;
- dma_regs m_dma_regs[6];
- uint8_t m_dma_active_mask;
+ ppc_regs m_ppc_regs;
+ dma_regs m_dma_regs[6];
+ uint8_t m_dma_active_mask;
required_device<sa1110_cpu_device> m_maincpu;
required_device<input_merger_device> m_uart3_irqs;
diff --git a/src/devices/machine/sa1111.cpp b/src/devices/machine/sa1111.cpp
index 4fbd5545355..e58d8250187 100644
--- a/src/devices/machine/sa1111.cpp
+++ b/src/devices/machine/sa1111.cpp
@@ -21,7 +21,7 @@
#define LOG_GPIO (1 << 10)
#define LOG_INTC (1 << 11)
#define LOG_CARD (1 << 12)
-#define LOG_AUDIO_DMA (1 << 13)
+#define LOG_AUDIO_DMA (1 << 13)
#define LOG_ALL (LOG_UNKNOWN | LOG_SBI | LOG_SK | LOG_USB | LOG_AUDIO | LOG_SSP | LOG_TRACK | LOG_MOUSE | LOG_GPIO | LOG_INTC | LOG_CARD)
#define VERBOSE (0)
diff --git a/src/devices/machine/sa1111.h b/src/devices/machine/sa1111.h
index 1524900be20..3804c06a30c 100644
--- a/src/devices/machine/sa1111.h
+++ b/src/devices/machine/sa1111.h
@@ -346,19 +346,19 @@ protected:
SASCR_RDD_BIT = 17,
SASCR_STO_BIT = 18,
- SASR_TNF_BIT = 0,
- SASR_RNE_BIT = 1,
- SASR_BSY_BIT = 2,
- SASR_TFS_BIT = 3,
- SASR_RFS_BIT = 4,
- SASR_TUR_BIT = 5,
- SASR_ROR_BIT = 6,
- SASR_TFL_BIT = 8,
+ SASR_TNF_BIT = 0,
+ SASR_RNE_BIT = 1,
+ SASR_BSY_BIT = 2,
+ SASR_TFS_BIT = 3,
+ SASR_RFS_BIT = 4,
+ SASR_TUR_BIT = 5,
+ SASR_ROR_BIT = 6,
+ SASR_TFL_BIT = 8,
SASR_TFL_MASK = 0x00000f00,
SASR_RFL_BIT = 12,
SASR_RFL_MASK = 0x0000f000,
- SASR_SEND_BIT = 16,
- SASR_RECV_BIT = 17,
+ SASR_SEND_BIT = 16,
+ SASR_RECV_BIT = 17,
SASR0_L3WD_BIT = 16,
SASR0_L3RD_BIT = 17,
@@ -376,14 +376,14 @@ protected:
SADTCS_TDSTA_BIT = 4,
SADTCS_TDBDB_BIT = 5,
SADTCS_TDSTB_BIT = 6,
- SADTCS_TBIU_BIT = 7,
+ SADTCS_TBIU_BIT = 7,
SADRCS_RDEN_BIT = 0,
SADRCS_RDBDA_BIT = 3,
SADRCS_RDSTA_BIT = 4,
SADRCS_RDBDB_BIT = 5,
SADRCS_RDSTB_BIT = 6,
- SADRCS_RBIU_BIT = 7,
+ SADRCS_RBIU_BIT = 7,
SAITR_TFS_BIT = 0,
SAITR_RFS_BIT = 1,
@@ -480,56 +480,56 @@ protected:
// interrupt lines
enum : uint32_t
{
- INT_GPA0 = 0,
- INT_GPA1 = 1,
- INT_GPA2 = 2,
- INT_GPA3 = 3,
- INT_GPB0 = 4,
- INT_GPB1 = 5,
- INT_GPB2 = 6,
- INT_GPB3 = 7,
- INT_GPB4 = 8,
- INT_GPB5 = 9,
- INT_GPC0 = 10,
- INT_GPC1 = 11,
- INT_GPC2 = 12,
- INT_GPC3 = 13,
- INT_GPC4 = 14,
- INT_GPC5 = 15,
- INT_GPC6 = 16,
- INT_GPC7 = 17,
- INT_MSTX = 18,
- INT_MSRX = 19,
- INT_MSERR = 20,
- INT_TPTX = 21,
- INT_TPRX = 22,
- INT_TPERR = 23,
- INT_SSPTX = 24,
- INT_SSPRX = 25,
- INT_SSPROR = 26,
- INT_AUDTXA = 32,
- INT_AUDRXA = 33,
- INT_AUDTXB = 34,
- INT_AUDRXB = 35,
- INT_AUDTFS = 36,
- INT_AUDRFS = 37,
- INT_AUDTUR = 38,
- INT_AUDROR = 39,
- INT_AUDDTS = 40,
- INT_AUDRDD = 41,
- INT_AUDSTO = 42,
- INT_USBPWR = 43,
- INT_USBHCIM = 44,
- INT_USBHCIBUF = 45,
- INT_USBHCIWAKE = 46,
- INT_USBHCIMFC = 47,
- INT_USBRESUME = 48,
- INT_S0RDY = 49,
- INT_S1RDY = 50,
- INT_S0CD = 51,
- INT_S1CD = 52,
- INT_S0BVD = 53,
- INT_S1BVD = 54
+ INT_GPA0 = 0,
+ INT_GPA1 = 1,
+ INT_GPA2 = 2,
+ INT_GPA3 = 3,
+ INT_GPB0 = 4,
+ INT_GPB1 = 5,
+ INT_GPB2 = 6,
+ INT_GPB3 = 7,
+ INT_GPB4 = 8,
+ INT_GPB5 = 9,
+ INT_GPC0 = 10,
+ INT_GPC1 = 11,
+ INT_GPC2 = 12,
+ INT_GPC3 = 13,
+ INT_GPC4 = 14,
+ INT_GPC5 = 15,
+ INT_GPC6 = 16,
+ INT_GPC7 = 17,
+ INT_MSTX = 18,
+ INT_MSRX = 19,
+ INT_MSERR = 20,
+ INT_TPTX = 21,
+ INT_TPRX = 22,
+ INT_TPERR = 23,
+ INT_SSPTX = 24,
+ INT_SSPRX = 25,
+ INT_SSPROR = 26,
+ INT_AUDTXA = 32,
+ INT_AUDRXA = 33,
+ INT_AUDTXB = 34,
+ INT_AUDRXB = 35,
+ INT_AUDTFS = 36,
+ INT_AUDRFS = 37,
+ INT_AUDTUR = 38,
+ INT_AUDROR = 39,
+ INT_AUDDTS = 40,
+ INT_AUDRDD = 41,
+ INT_AUDSTO = 42,
+ INT_USBPWR = 43,
+ INT_USBHCIM = 44,
+ INT_USBHCIBUF = 45,
+ INT_USBHCIWAKE = 46,
+ INT_USBHCIMFC = 47,
+ INT_USBRESUME = 48,
+ INT_S0RDY = 49,
+ INT_S1RDY = 50,
+ INT_S0CD = 51,
+ INT_S1CD = 52,
+ INT_S0BVD = 53,
+ INT_S1BVD = 54
};
struct sbi_regs
diff --git a/src/devices/machine/swim1.cpp b/src/devices/machine/swim1.cpp
index 331c25f62aa..9c49fd94dad 100644
--- a/src/devices/machine/swim1.cpp
+++ b/src/devices/machine/swim1.cpp
@@ -160,7 +160,7 @@ u8 swim1_device::ism_read(offs_t offset)
return m_ism_mode;
default:
- // logerror("read %s\n", names[offset & 7]);
+ // logerror("read %s\n", names[offset & 7]);
break;
}
return 0xff;
diff --git a/src/devices/machine/swim2.cpp b/src/devices/machine/swim2.cpp
index 582a97a58b2..9e504c0d7f9 100644
--- a/src/devices/machine/swim2.cpp
+++ b/src/devices/machine/swim2.cpp
@@ -231,7 +231,7 @@ void swim2_device::write(offs_t offset, u8 data)
if(fifo_push(M_CRC) && !m_error)
m_error |= 0x04;
break;
-
+
case 3: { // param
static const char *const pname[4] = {
"late", "time0", "early", "time1"
@@ -394,7 +394,7 @@ void swim2_device::sync()
cycles = 0;
break;
}
- }
+ }
if(m_tss_output & 0xc) {
bool bit;
@@ -525,7 +525,7 @@ void swim2_device::sync()
}
}
}
- }
+ }
}
}
diff --git a/src/devices/machine/swim2.h b/src/devices/machine/swim2.h
index bddcd7b49d1..20df1671131 100644
--- a/src/devices/machine/swim2.h
+++ b/src/devices/machine/swim2.h
@@ -51,7 +51,7 @@ private:
u16 m_fifo[2], m_sr;
u16 m_crc, m_mfm_sync_counter;
u32 m_half_cycles_before_change;
-
+
u64 m_last_sync;
u64 m_flux_write_start;
std::array<u64, 32> m_flux_write;
@@ -61,7 +61,7 @@ private:
u64 time_to_cycles(const attotime &tm) const;
attotime cycles_to_time(u64 cycles) const;
-
+
void fifo_clear();
bool fifo_push(u16 data);
u16 fifo_pop();