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author Sandro Ronco <sronco@users.noreply.github.com>2021-01-12 13:39:14 +0100
committer GitHub <noreply@github.com>2021-01-12 23:39:14 +1100
commit5a57d03cfe07bf47bc6862f403fb811bebbfa956 (patch)
tree21dbf21537b820694af31d6897f091838b08c280 /src/devices/machine
parentfad7c9e0beb50f6c96da9ea8f93082bc349a25c2 (diff)
-Acorn Archimedes code reorganization: (#7627)
* Separated Acorn IOC and MEMC into devices. * Emulated 8051-based serial keyboard. * acorn_machine/memc.cpp: Ensure only one logical page is mapped to a single physical page. * Fixed RISC OS POST IOC register test. * aa310.cpp: Added debug code to display RISC OS POST failures. -machine/archimedes_keyb.cpp: Dumped Acorn Archimedes keyboard microcontroller. [Phil Pemberton]
Diffstat (limited to 'src/devices/machine')
-rw-r--r--src/devices/machine/acorn_ioc.cpp411
-rw-r--r--src/devices/machine/acorn_ioc.h130
-rw-r--r--src/devices/machine/acorn_memc.cpp509
-rw-r--r--src/devices/machine/acorn_memc.h102
4 files changed, 1152 insertions, 0 deletions
diff --git a/src/devices/machine/acorn_ioc.cpp b/src/devices/machine/acorn_ioc.cpp
new file mode 100644
index 00000000000..1a879cb7a2d
--- /dev/null
+++ b/src/devices/machine/acorn_ioc.cpp
@@ -0,0 +1,411 @@
+// license:LGPL-2.1+
+// copyright-holders:Angelo Salese, R. Belmont, Juergen Buchmueller, Sandro Ronco
+/**************************************************************************************************
+
+ Acorn RISC Machine Input/Output Controller (IOC)
+
+ TODO:
+ - support IOEB used in the ARM250 (partially implemented in aristmk5.cpp)
+
+**************************************************************************************************/
+
+#include "emu.h"
+#include "acorn_ioc.h"
+
+//#define VERBOSE 1
+#include "logmacro.h"
+
+
+DEFINE_DEVICE_TYPE(ACORN_IOC, acorn_ioc_device, "ioc", "Acorn IOC")
+
+//**************************************************************************
+// LIVE DEVICE
+//**************************************************************************
+
+acorn_ioc_device::acorn_ioc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : device_t(mconfig, ACORN_IOC, tag, owner, clock)
+ , device_serial_interface(mconfig, *this)
+ , m_peripherals_r(*this)
+ , m_peripherals_w(*this)
+ , m_giop_r(*this)
+ , m_giop_w(*this)
+ , m_irq_w(*this)
+ , m_fiq_w(*this)
+ , m_kout_w(*this)
+ , m_baud_w(*this)
+{
+}
+
+void acorn_ioc_device::device_resolve_objects()
+{
+ m_peripherals_r.resolve_all_safe(0xffffffff);
+ m_peripherals_w.resolve_all_safe();
+ m_giop_r.resolve_all_safe(1);
+ m_giop_w.resolve_all_safe();
+ m_irq_w.resolve_safe();
+ m_fiq_w.resolve_safe();
+ m_kout_w.resolve_safe();
+ m_baud_w.resolve();
+}
+
+void acorn_ioc_device::device_start()
+{
+ for (int i=0; i <4; i++)
+ m_timers[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(acorn_ioc_device::timer_tick), this));
+
+ save_item(NAME(m_ir));
+ save_item(NAME(m_if));
+ save_item(NAME(m_baud));
+ save_item(NAME(m_timercnt));
+ save_item(NAME(m_timerout));
+ save_item(NAME(m_regs));
+}
+
+void acorn_ioc_device::device_reset()
+{
+ std::fill(std::begin(m_regs), std::end(m_regs), 0);
+ m_regs[IRQ_STATUS_A] = 0x10 | 0x80; // set up POR (Power On Reset) and Force IRQ at start-up
+ m_regs[IRQ_STATUS_B] = 0x40; // set up KART Tx empty
+ m_regs[FIQ_STATUS] = 0x80; // set up Force FIQ
+
+ m_ir = CLEAR_LINE;
+ m_if = CLEAR_LINE;
+ m_baud = CLEAR_LINE;
+
+ // KART interface
+ set_data_frame(1, 8, PARITY_NONE, STOP_BITS_2);
+ set_rate(31250);
+
+ for (int i = 0; i < 6; i++)
+ m_giop_w[i](1);
+
+ for (int i=0; i < 2; i++)
+ {
+ m_timercnt[i] = 0;
+ m_timerout[i] = 0;
+ set_timer(i);
+ }
+
+ transmit_register_reset();
+ receive_register_reset();
+}
+
+void acorn_ioc_device::map(address_map &map)
+{
+ // Typical configuration
+ // IOA[2:6] --> A[2:6] Internal registers address
+ // IOA[16:18] --> B[0:2] Peripherals select
+ // IOA[19:20] --> T[0:1] Peripherals access timing
+ // IOA[21] --> CS Chip select
+ map(0x00200000, 0x0020007f).mirror(0x0018ff80).rw(FUNC(acorn_ioc_device::registers_r), FUNC(acorn_ioc_device::registers_w));
+ map(0x00210000, 0x0021ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<1>), FUNC(acorn_ioc_device::periph_w<1>));
+ map(0x00220000, 0x0022ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<2>), FUNC(acorn_ioc_device::periph_w<2>));
+ map(0x00230000, 0x0023ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<3>), FUNC(acorn_ioc_device::periph_w<3>));
+ map(0x00240000, 0x0024ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<4>), FUNC(acorn_ioc_device::periph_w<4>));
+ map(0x00250000, 0x0025ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<5>), FUNC(acorn_ioc_device::periph_w<5>));
+ map(0x00260000, 0x0026ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<6>), FUNC(acorn_ioc_device::periph_w<6>));
+ map(0x00270000, 0x0027ffff).select(0x00180000).rw(FUNC(acorn_ioc_device::periph_r<7>), FUNC(acorn_ioc_device::periph_w<7>));
+}
+
+TIMER_CALLBACK_MEMBER(acorn_ioc_device::timer_tick)
+{
+ // all timers always run
+ set_timer(param);
+
+ // but only timers 0 and 1 generate IRQs
+ switch (param)
+ {
+ case 0:
+ change_interrupt(IRQ_STATUS_A, 0x20, ASSERT_LINE);
+ break;
+
+ case 1:
+ change_interrupt(IRQ_STATUS_A, 0x40, ASSERT_LINE);
+ break;
+
+ case 2:
+ m_baud ^= 1;
+ m_baud_w(m_baud ? ASSERT_LINE : CLEAR_LINE);
+ break;
+ }
+}
+
+void acorn_ioc_device::change_interrupt(int reg, uint8_t mask, int state)
+{
+ if (state)
+ m_regs[reg] |= mask;
+ else
+ m_regs[reg] &= ~mask;
+
+ update_interrups();
+}
+
+void acorn_ioc_device::tra_complete()
+{
+ change_interrupt(IRQ_STATUS_B, 0x40, ASSERT_LINE); // KART Rx empty
+}
+
+void acorn_ioc_device::rcv_complete()
+{
+ receive_register_extract();
+ m_regs[KART] = get_received_char();
+ change_interrupt(IRQ_STATUS_B, 0x80, ASSERT_LINE); // KART Rx full
+}
+
+void acorn_ioc_device::tra_callback()
+{
+ m_kout_w(transmit_register_get_data_bit());
+}
+
+void acorn_ioc_device::set_timer(int tmr)
+{
+ double freq = 0;
+
+ switch (tmr)
+ {
+ case 0: // Timers
+ case 1:
+ if (m_timercnt[tmr] == 0)
+ m_timers[tmr]->adjust(attotime::never, tmr);
+ else
+ m_timers[tmr]->adjust(attotime::from_usec(m_timercnt[tmr] / 2), tmr); // TODO: ARM timings are quite off there, it should be latch and not latch/2
+ break;
+
+ case 2: // Baud generator
+ freq = (double)clock() / 8 / (double)(m_timercnt[tmr] + 1);
+ if (!m_baud_w.isnull())
+ m_timers[tmr]->adjust(attotime::from_usec(freq), tmr);
+ break;
+
+ case 3: // KART clock
+ freq = (double)clock() / 8 / (double)((m_timercnt[tmr] + 1) * 16);
+ set_rate((int)freq);
+ break;
+ }
+}
+
+void acorn_ioc_device::latch_timer_cnt(int tmr)
+{
+ // find out how many 2 MHz ticks have gone by
+ m_timerout[tmr] = m_timercnt[tmr] - (uint32_t)m_timers[tmr]->elapsed().as_ticks(clock() / 4);
+}
+
+WRITE_LINE_MEMBER(acorn_ioc_device::if_w)
+{
+ // set on falling edge
+ if (m_if && !state)
+ change_interrupt(IRQ_STATUS_A, 0x04, ASSERT_LINE);
+
+ m_if = state;
+}
+
+WRITE_LINE_MEMBER(acorn_ioc_device::ir_w)
+{
+ // set on rising edge
+ if (!m_ir && state)
+ change_interrupt(IRQ_STATUS_A, 0x08, ASSERT_LINE);
+
+ m_ir = state;
+}
+
+void acorn_ioc_device::update_interrups()
+{
+ if ((m_regs[IRQ_STATUS_A] & m_regs[IRQ_MASK_A]) || (m_regs[IRQ_STATUS_B] & m_regs[IRQ_MASK_B]))
+ m_irq_w(ASSERT_LINE);
+ else
+ m_irq_w(CLEAR_LINE);
+
+ if (m_regs[FIQ_STATUS] & m_regs[FIQ_MASK])
+ m_fiq_w(ASSERT_LINE);
+ else
+ m_fiq_w(CLEAR_LINE);
+}
+
+uint32_t acorn_ioc_device::registers_r(offs_t offset, uint32_t mem_mask)
+{
+ LOG("%s: IOC R %02x = %02x\n", machine().describe_context(), offset, m_regs[offset]);
+
+ uint8_t data = 0;
+ switch (offset & 0x1f)
+ {
+ case CONTROL:
+ // x--- ---- IR line
+ // -x-- ---- IF line
+ // --xx xxxx GPIO (C0-C5)
+
+ for (int i = 0; i < 6; i++)
+ data |= m_giop_r[i]() << i;
+
+ data |= m_if << 6;
+ data |= m_ir << 7;
+ return data;
+
+ case KART:
+ change_interrupt(IRQ_STATUS_B, 0x80, CLEAR_LINE);
+ return m_regs[KART];
+
+ case IRQ_STATUS_A:
+ // x--- ---- Always 1 (force IRQ)
+ // -x-- ---- Timer 1
+ // --x- ---- Timer 0
+ // ---x ---- POR line
+ // ---- x-- IR line
+ // ---- -x-- IF line
+ // ---- --x- IL7 line
+ // ---- ---x IL6 line
+
+ return m_regs[IRQ_STATUS_A];
+
+ case IRQ_REQUEST_A:
+ return m_regs[IRQ_STATUS_A] & m_regs[IRQ_MASK_A];
+
+ case IRQ_MASK_A:
+ return m_regs[IRQ_MASK_A];
+
+ case IRQ_STATUS_B:
+ // x--- ---- KART Rx full
+ // -x-- ---- KART Tx empty
+ // --xx xxxx IL0-IL5 lines
+
+ return m_regs[IRQ_STATUS_B];
+
+ case IRQ_REQUEST_B:
+ return m_regs[IRQ_STATUS_B] & m_regs[IRQ_MASK_B];
+
+ case IRQ_MASK_B:
+ return m_regs[IRQ_MASK_B];
+
+ case FIQ_STATUS:
+ // x--- ---- Always 1 (force FIQ)
+ // -x-- ---- IL0 line
+ // --xx x--- C5, C4 and C3 lines
+ // ---- -x-- IF line
+ // ---- --xx FH0 and FH1 lines
+
+ return m_regs[FIQ_STATUS];
+
+ case FIQ_REQUEST:
+ return m_regs[FIQ_STATUS] & m_regs[FIQ_MASK];
+
+ case FIQ_MASK:
+ return m_regs[FIQ_MASK];
+
+ case T0_LATCH_LO:
+ return m_timerout[0] & 0xff;
+
+ case T0_LATCH_HI:
+ return (m_timerout[0] >> 8) & 0xff;
+
+ case T1_LATCH_LO:
+ return m_timerout[1] & 0xff;
+
+ case T1_LATCH_HI:
+ return (m_timerout[1] >> 8) & 0xff;
+
+ case T2_LATCH_LO:
+ return m_timerout[2] & 0xff;
+
+ case T2_LATCH_HI:
+ return (m_timerout[2] >> 8) & 0xff;
+
+ case T3_LATCH_LO:
+ return m_timerout[3] & 0xff;
+
+ case T3_LATCH_HI:
+ return (m_timerout[3] >> 8) & 0xff;
+
+ default:
+ return m_regs[offset & 0x1f];
+ }
+}
+
+void acorn_ioc_device::registers_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ LOG("%s: IOC W %02x = %02x\n", machine().describe_context(), offset, data);
+
+ // IOC uses the data bus lines D16-D23 as inputs, this also works with byte store (STRB)
+ // because the ARM CPU repeats the byte four times across the data bus.
+ if (ACCESSING_BITS_16_31)
+ data >>= 16;
+
+ switch (offset & 0x1f)
+ {
+ case CONTROL:
+ for (int i = 0; i < 6; i++)
+ m_giop_w[i](BIT(data, i));
+ break;
+
+ case KART:
+ change_interrupt(IRQ_STATUS_B, 0x40, CLEAR_LINE);
+ m_regs[KART] = data;
+ transmit_register_setup(data);
+ break;
+
+ case IRQ_REQUEST_A:
+ m_regs[IRQ_STATUS_A] &= ~(data & 0x7c);
+ update_interrups(); // check pending irqs
+ break;
+
+ case IRQ_MASK_A:
+ m_regs[IRQ_MASK_A] = data;
+ update_interrups();
+ break;
+
+ case IRQ_MASK_B:
+ m_regs[IRQ_MASK_B] = data;
+ update_interrups();
+ break;
+
+ case FIQ_MASK:
+ m_regs[FIQ_MASK] = data;
+ update_interrups();
+ break;
+
+ case T0_LATCH_LO: case T0_LATCH_HI:
+ case T1_LATCH_LO: case T1_LATCH_HI:
+ case T2_LATCH_LO: case T2_LATCH_HI:
+ case T3_LATCH_LO: case T3_LATCH_HI:
+ m_regs[offset] = data;
+ break;
+
+ case T0_LATCH: // Timer 0 latch
+ latch_timer_cnt(0);
+ break;
+
+ case T1_LATCH: // Timer 1 latch
+ latch_timer_cnt(1);
+ break;
+
+ case T2_LATCH: // Timer 2 latch
+ latch_timer_cnt(2);
+ break;
+
+ case T3_LATCH: // Timer 3 latch
+ latch_timer_cnt(3);
+ break;
+
+ case T0_GO: // Timer 0 start
+ m_timercnt[0] = m_regs[T0_LATCH_HI] << 8 | m_regs[T0_LATCH_LO];
+ set_timer(0);
+ break;
+
+ case T1_GO: // Timer 1 start
+ m_timercnt[1] = m_regs[T1_LATCH_HI] << 8 | m_regs[T1_LATCH_LO];
+ set_timer(1);
+ break;
+
+ case T2_GO: // Timer 2 start
+ m_timercnt[2] = m_regs[T2_LATCH_HI] << 8 | m_regs[T2_LATCH_LO];
+ set_timer(2);
+ break;
+
+ case T3_GO: // Timer 3 start
+ m_timercnt[3] = m_regs[T3_LATCH_HI] << 8 | m_regs[T3_LATCH_LO];
+ set_timer(3);
+ break;
+
+ default:
+ m_regs[offset & 0x1f] = data;
+ break;
+ }
+}
diff --git a/src/devices/machine/acorn_ioc.h b/src/devices/machine/acorn_ioc.h
new file mode 100644
index 00000000000..50477cf8b24
--- /dev/null
+++ b/src/devices/machine/acorn_ioc.h
@@ -0,0 +1,130 @@
+// license:LGPL-2.1+
+// copyright-holders:Angelo Salese, R. Belmont, Juergen Buchmueller, Sandro Ronco
+/**************************************************************************************************
+
+ Acorn RISC Machine Input/Output Controller (IOC)
+
+**************************************************************************************************/
+
+#ifndef MAME_MACHINE_ACORN_IOC_H
+#define MAME_MACHINE_ACORN_IOC_H
+
+#pragma once
+
+#include "diserial.h"
+
+//**************************************************************************
+// TYPE DEFINITIONS
+//**************************************************************************
+
+// ======================> acorn_ioc_device
+
+class acorn_ioc_device : public device_t, public device_serial_interface
+{
+public:
+ acorn_ioc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ template <unsigned N> auto peripheral_r() { static_assert(N >= 1 && N <= 7); return m_peripherals_r[N - 1].bind(); }
+ template <unsigned N> auto peripheral_w() { static_assert(N >= 1 && N <= 7); return m_peripherals_w[N - 1].bind(); }
+ template <unsigned N> auto gpio_r() { static_assert(N <= 5); return m_giop_r[N].bind(); }
+ template <unsigned N> auto gpio_w() { static_assert(N <= 5); return m_giop_w[N].bind(); }
+ auto irq_w() { return m_irq_w.bind(); }
+ auto fiq_w() { return m_fiq_w.bind(); }
+ auto baud_w() { return m_baud_w.bind(); }
+ auto kout_w() { return m_kout_w.bind(); }
+
+ void map(address_map &map);
+
+ uint32_t registers_r(offs_t offset, uint32_t mem_mask = ~0);
+ void registers_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ template<unsigned N> uint32_t periph_r(offs_t offset, uint32_t mem_mask = ~0) { return m_peripherals_r[N - 1](offset, mem_mask); }
+ template<unsigned N> void periph_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { m_peripherals_w[N - 1](offset, data, mem_mask); }
+
+ DECLARE_WRITE_LINE_MEMBER(il0_w) { change_interrupt(IRQ_STATUS_B, 0x01, state); change_interrupt(FIQ_STATUS, 0x40, state); }
+ DECLARE_WRITE_LINE_MEMBER(il1_w) { change_interrupt(IRQ_STATUS_B, 0x02, state); }
+ DECLARE_WRITE_LINE_MEMBER(il2_w) { change_interrupt(IRQ_STATUS_B, 0x04, state); }
+ DECLARE_WRITE_LINE_MEMBER(il3_w) { change_interrupt(IRQ_STATUS_B, 0x08, state); }
+ DECLARE_WRITE_LINE_MEMBER(il4_w) { change_interrupt(IRQ_STATUS_B, 0x10, state); }
+ DECLARE_WRITE_LINE_MEMBER(il5_w) { change_interrupt(IRQ_STATUS_B, 0x20, state); }
+ DECLARE_WRITE_LINE_MEMBER(il6_w) { change_interrupt(IRQ_STATUS_A, 0x01, state); }
+ DECLARE_WRITE_LINE_MEMBER(il7_w) { change_interrupt(IRQ_STATUS_A, 0x02, state); }
+ DECLARE_WRITE_LINE_MEMBER(fh0_w) { change_interrupt(FIQ_STATUS , 0x01, state); }
+ DECLARE_WRITE_LINE_MEMBER(fh1_w) { change_interrupt(FIQ_STATUS , 0x02, state); }
+ DECLARE_WRITE_LINE_MEMBER(fl_w) { change_interrupt(FIQ_STATUS , 0x04, !state); }
+ DECLARE_WRITE_LINE_MEMBER(por_w) { if (state) change_interrupt(IRQ_STATUS_A, 0x10, state); }
+ DECLARE_WRITE_LINE_MEMBER(kin_w) { rx_w(state); }
+ DECLARE_WRITE_LINE_MEMBER(if_w);
+ DECLARE_WRITE_LINE_MEMBER(ir_w);
+
+protected:
+ // device-level overrides
+ virtual void device_resolve_objects() override;
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ // device_serial_interface overrides
+ virtual void tra_callback() override;
+ virtual void tra_complete() override;
+ virtual void rcv_complete() override;
+
+private:
+ void update_interrups();
+ void change_interrupt(int reg, uint8_t mask, int state);
+ void set_timer(int tmr);
+ void latch_timer_cnt(int tmr);
+ TIMER_CALLBACK_MEMBER(timer_tick);
+
+ enum // registers
+ {
+ CONTROL = 0x00 / 4,
+ KART = 0x04 / 4,
+ IRQ_STATUS_A = 0x10 / 4,
+ IRQ_REQUEST_A = 0x14 / 4,
+ IRQ_MASK_A = 0x18 / 4,
+ IRQ_STATUS_B = 0x20 / 4,
+ IRQ_REQUEST_B = 0x24 / 4,
+ IRQ_MASK_B = 0x28 / 4,
+ FIQ_STATUS = 0x30 / 4,
+ FIQ_REQUEST = 0x34 / 4,
+ FIQ_MASK = 0x38 / 4,
+ T0_LATCH_LO = 0x40 / 4,
+ T0_LATCH_HI = 0x44 / 4,
+ T0_GO = 0x48 / 4,
+ T0_LATCH = 0x4c / 4,
+ T1_LATCH_LO = 0x50 / 4,
+ T1_LATCH_HI = 0x54 / 4,
+ T1_GO = 0x58 / 4,
+ T1_LATCH = 0x5c / 4,
+ T2_LATCH_LO = 0x60 / 4,
+ T2_LATCH_HI = 0x64 / 4,
+ T2_GO = 0x68 / 4,
+ T2_LATCH = 0x6c / 4,
+ T3_LATCH_LO = 0x70 / 4,
+ T3_LATCH_HI = 0x74 / 4,
+ T3_GO = 0x78 / 4,
+ T3_LATCH = 0x7c / 4,
+ };
+
+ devcb_read32::array<7> m_peripherals_r;
+ devcb_write32::array<7> m_peripherals_w;
+ devcb_read_line::array<6> m_giop_r;
+ devcb_write_line::array<6> m_giop_w;
+ devcb_write_line m_irq_w;
+ devcb_write_line m_fiq_w;
+ devcb_write_line m_kout_w;
+ devcb_write_line m_baud_w;
+ emu_timer * m_timers[4];
+
+ int m_ir;
+ int m_if;
+ int m_baud;
+ uint32_t m_timercnt[4];
+ uint32_t m_timerout[4];
+ uint8_t m_regs[0x20];
+};
+
+
+// device type definition
+DECLARE_DEVICE_TYPE(ACORN_IOC, acorn_ioc_device)
+
+#endif // MAME_MACHINE_ACORN_IOC_H
diff --git a/src/devices/machine/acorn_memc.cpp b/src/devices/machine/acorn_memc.cpp
new file mode 100644
index 00000000000..ebf13443e6e
--- /dev/null
+++ b/src/devices/machine/acorn_memc.cpp
@@ -0,0 +1,509 @@
+// license:LGPL-2.1+
+// copyright-holders:Angelo Salese, R. Belmont, Juergen Buchmueller, Sandro Ronco
+/**************************************************************************************************
+
+ Acorn RISC Machine Memory Controller (MEMC)
+
+ TODO:
+ - VIDC DMA interface needs to be cleaned up.
+ - Slave mode.
+
+**************************************************************************************************/
+
+#include "emu.h"
+#include "acorn_memc.h"
+
+#include "debug/debugcon.h"
+#include "debug/debugcmd.h"
+#include "debugger.h"
+
+#include <functional>
+
+//#define VERBOSE 1
+#include "logmacro.h"
+
+DEFINE_DEVICE_TYPE(ACORN_MEMC, acorn_memc_device, "memc", "Acorn MEMC")
+
+//**************************************************************************
+// LIVE DEVICE
+//**************************************************************************
+
+acorn_memc_device::acorn_memc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : device_t(mconfig, ACORN_MEMC, tag, owner, clock)
+ , device_memory_interface(mconfig, *this)
+ , m_vidc(*this, finder_base::DUMMY_TAG)
+ , m_space_config("MEMC", ENDIANNESS_LITTLE, 32, 26, 0)
+ , m_abort_w(*this)
+ , m_sirq_w(*this)
+ , m_output_dram_rowcol(false)
+{
+}
+
+//-------------------------------------------------
+// memory_space_config - return a description of
+// any address spaces owned by this device
+//-------------------------------------------------
+
+device_memory_interface::space_config_vector acorn_memc_device::memory_space_config() const
+{
+ return space_config_vector {
+ std::make_pair(0, &m_space_config)
+ };
+}
+
+void acorn_memc_device::memc_map_debug_commands(int ref, const std::vector<std::string> &params)
+{
+ uint64_t offset;
+ if (params.size() != 1 || !machine().debugger().commands().validate_number_parameter(params[0], offset))
+ return;
+
+ // figure out the page number and offset in the page
+ uint32_t pagesize = m_page_sizes[m_pagesize];
+ uint32_t page = offset / pagesize;
+ uint32_t poffs = offset % pagesize;
+
+ machine().debugger().console().printf("0x%08lx == ", offset);
+ if (offset >= 0x02000000)
+ machine().debugger().console().printf("physical\n");
+ else if (m_pages[page] == -1)
+ machine().debugger().console().printf("unmapped\n");
+ else
+ machine().debugger().console().printf("0x%08lx (PPL %x)\n", 0x02000000 | ((m_pages[page] * pagesize) + poffs), m_pages_ppl[page]);
+}
+
+void acorn_memc_device::device_resolve_objects()
+{
+ m_abort_w.resolve_safe();
+ m_sirq_w.resolve_safe();
+}
+
+void acorn_memc_device::device_start()
+{
+ m_space = &space();
+
+ save_item(NAME(m_spvmd));
+ save_item(NAME(m_pagesize));
+ save_item(NAME(m_latchrom));
+ save_item(NAME(m_video_dma_on));
+ save_item(NAME(m_sound_dma_on));
+ save_item(NAME(m_cursor_enabled));
+ save_item(NAME(m_os_mode));
+ save_item(NAME(m_vidinit));
+ save_item(NAME(m_vidstart));
+ save_item(NAME(m_vidend));
+ save_item(NAME(m_vidcur));
+ save_item(NAME(m_cinit));
+ save_item(NAME(m_sndstart));
+ save_item(NAME(m_sndend));
+ save_item(NAME(m_sndcur));
+ save_item(NAME(m_sndendcur));
+ save_item(NAME(m_pages));
+ save_item(NAME(m_pages_ppl));
+
+ if (machine().debug_flags & DEBUG_FLAG_ENABLED)
+ {
+ using namespace std::placeholders;
+ machine().debugger().console().register_command("memc_map", CMDFLAG_NONE, 0, 1, 1, std::bind(&acorn_memc_device::memc_map_debug_commands, this, _1, _2));
+ }
+}
+
+void acorn_memc_device::device_reset()
+{
+ m_latchrom = true; // map in the boot ROM
+ m_pagesize = 0;
+ m_video_dma_on = false;
+ m_sound_dma_on = false;
+ m_cursor_enabled = false;
+ m_os_mode = false;
+ m_vidinit = 0;
+ m_vidstart = 0;
+ m_vidend = 0;
+ m_vidcur = 0;
+ m_cinit = 0;
+ m_sndstart = 0;
+ m_sndend = 0;
+ m_sndcur = 0;
+ m_sndendcur = 0;
+ m_spvmd = ASSERT_LINE;
+
+ // kill all MEMC mappings
+ std::fill(std::begin(m_pages), std::end(m_pages), -1); // indicate unmapped
+ std::fill(std::begin(m_pages_ppl), std::end(m_pages_ppl), 0);
+}
+
+uint32_t acorn_memc_device::invalid_access(bool is_write, offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ if (!machine().side_effects_disabled())
+ {
+ if (is_write)
+ logerror("abort W 0x%08x 0x%08x (0x%08x)\n", offset << 2, data, mem_mask);
+ else
+ logerror("abort R 0x%08x (0x%08x)\n", offset << 2, mem_mask);
+
+ m_abort_w(ASSERT_LINE);
+ }
+
+ return 0xdeadbeef;
+}
+
+bool acorn_memc_device::is_valid_access(int page, bool write)
+{
+ if (m_pages[page] != -1)
+ {
+ if (m_spvmd || machine().side_effects_disabled())
+ return true;
+
+ switch (m_pages_ppl[page])
+ {
+ case 0: return true;
+ case 1: return m_os_mode || (write == false);
+ case 2: return m_os_mode && (write == false);
+ case 3: return m_os_mode && (write == false);
+ }
+ }
+
+ return false;
+}
+
+void acorn_memc_device::registers_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ // is it a register?
+ if ((data & 0x03e00000) != 0x03600000)
+ return;
+
+ LOG("%s: MEMC W %02x = %04x\n", machine().describe_context(), (data >> 17) & 7, data & 0xffff);
+
+ switch ((data >> 17) & 7)
+ {
+ case 0: // Video init
+ m_vidinit = ((data >> 2) & 0x7fff) * 16;
+ break;
+
+ case 1: // Video start
+ m_vidstart = ((data >> 2) & 0x7fff) * 16;
+ break;
+
+ case 2: // Video end
+ m_vidend = ((data >> 2) & 0x7fff) * 16;
+ break;
+
+ case 3: // Cursor init
+ m_cursor_enabled = true;
+ if (m_vidc.found())
+ m_vidc->set_cursor_enable(m_cursor_enabled);
+
+ m_cinit = ((data >> 2) & 0x7fff) * 16;
+ break;
+
+ case 4: // Sound start
+ m_sirq_w(CLEAR_LINE);
+ m_sndstart = ((data >> 2) & 0x7fff) * 16;
+ break;
+
+ case 5: // Sound end
+ // end buffer is actually +16 bytes wrt sound start
+ // TODO: it actually don't apply for ertictac and poizone?
+ m_sndend = ((data >> 2) & 0x7fff) * 16;
+ break;
+
+ case 6: // Sound pointer
+ m_sndcur = m_sndstart;
+ m_sndendcur = m_sndend;
+ m_sirq_w(ASSERT_LINE);
+ break;
+
+ case 7: // Control
+ // --x- ---- ---- ---- Test Mode
+ // ---x ---- ---- ---- OS Mode
+ // ---- x--- ---- ---- Sound DMA
+ // ---- -x-- ---- ---- Video DMA
+ // ---- --xx ---- ---- DRAM refresh config
+ // ---- ---- xx-- ---- High ROM access time
+ // ---- ---- --xx ---- Low ROM access time
+ // ---- ---- ---- xx-- Page size
+ // ---- ---- ---- --xx Not used
+
+ m_pagesize = BIT(data, 2, 2);
+ m_video_dma_on = BIT(data, 10);
+ m_sound_dma_on = BIT(data, 11);
+ m_os_mode = BIT(data, 12);
+
+ LOG("%s MEMC: %x to Control (page size %d, %s, %s)\n", machine().describe_context(), data & 0x1ffc, m_page_sizes[m_pagesize], m_video_dma_on ? "Video DMA on" : "Video DMA off", m_sound_dma_on ? "Sound DMA on" : "Sound DMA off");
+
+ if (m_video_dma_on)
+ {
+ m_vidcur = 0;
+ // TODO: update internally
+ }
+ else
+ {
+ m_cursor_enabled = false;
+ if (m_vidc.found())
+ m_vidc->set_cursor_enable(m_cursor_enabled);
+ }
+
+ if (m_vidc.found())
+ m_vidc->update_sound_mode(m_sound_dma_on);
+
+ if (m_sound_dma_on)
+ {
+ //logerror("MEMC: Starting audio DMA at %d uSec, buffer from %x to %x\n", ((m_regs[0xc0]&0xff)-2)*8, m_sndstart, m_sndend);
+ //logerror("MEMC: audio DMA start, sound freq %d, sndhz = %f\n", (m_regs[0xc0] & 0xff)-2, sndhz);
+
+ m_sndcur = m_sndstart;
+ m_sndendcur = m_sndend;
+ }
+ break;
+ default:
+ logerror("MEMC: %06x to unknown reg %d\n", data & 0x1ffff, (data >> 17) & 7);
+ break;
+ }
+}
+
+
+//**************************************************************************
+//
+// 22 2222 1111 1111 1100 0000 0000
+// 54 3210 9876 5432 1098 7654 3210
+// 4k page: 11 1LLL LLLL LLLL LLAA MPPP PPPP
+// 8k page: 11 1LLL LLLL LLLM LLAA MPPP PPPP
+// 16k page: 11 1LLL LLLL LLxM LLAA MPPP PPPP
+// 32k page: 11 1LLL LLLL LxxM LLAA MPPP PPPP
+// 3 8 2 9 0 f f
+//
+// L - logical page
+// P - physical page
+// A - access permissions
+// M - MEMC number (for machines with multiple MEMCs)
+//
+// The logical page is encoded with bits 11+10 being the most significant bits
+// (in that order), and the rest being bit 22 down.
+//
+// The physical page is encoded differently depending on the page size :
+//
+// 4k page: bits 6-0 being bits 6-0
+// 8k page: bits 6-1 being bits 5-0, bit 0 being bit 6
+// 16k page: bits 6-2 being bits 4-0, bits 1-0 being bits 6-5
+// 32k page: bits 6-3 being bits 4-0, bit 0 being bit 4, bit 2 being bit 5, bit 1 being bit 6
+//
+//**************************************************************************
+
+void acorn_memc_device::page_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ uint32_t logaddr = 0;
+ uint32_t phyaddr = 0;
+ uint32_t memc = 0;
+
+ switch (m_pagesize)
+ {
+ case 0:
+ phyaddr = BIT(data, 0, 7);
+ logaddr = BIT(data, 12, 11) | (BIT(data, 10, 2) << 11);
+ memc = BIT(data, 7);
+ break;
+
+ case 1:
+ phyaddr = BIT(data, 1, 6) | (BIT(data, 0) << 6);
+ logaddr = BIT(data, 13, 10) | (BIT(data, 10, 2) << 10);
+ memc = BIT(data, 7) | (BIT(data, 12) << 1);
+ break;
+
+ case 2:
+ phyaddr = BIT(data, 2, 5) | (BIT(data, 0, 2) << 5);
+ logaddr = BIT(data, 14, 9) | (BIT(data, 10, 2) << 9);
+ memc = BIT(data, 7) | (BIT(data, 12) << 1);
+ break;
+
+ case 3:
+ phyaddr = BIT(data, 3, 4) | (BIT(data, 0) << 4) | (BIT(data, 1) << 6) | (BIT(data, 2) << 5);
+ logaddr = BIT(data, 15, 8) | (BIT(data, 10, 2) << 8);
+ memc = BIT(data, 7) | (BIT(data, 12) << 1);
+ break;
+ }
+
+ // always make sure ROM mode is disconnected when this occurs
+ m_latchrom = false;
+
+ phyaddr += memc * 0x80;
+
+ // unmap all logical pages that resolve to the same physical address
+ for (int i=0; i < 0x2000; i++)
+ if (m_pages[i] == phyaddr)
+ m_pages[i] = -1;
+
+ // now go ahead and set the mapping in the page table
+ m_pages[logaddr] = phyaddr;
+ m_pages_ppl[logaddr] = BIT(data, 8, 2);
+
+ LOG("%s = MEMC_PAGE(%d): W %08x: logaddr %08x to phyaddr %08x, MEMC %d, perms %d\n", machine().describe_context(), m_pages[logaddr], data, logaddr * m_page_sizes[m_pagesize], phyaddr * m_page_sizes[m_pagesize], memc, m_pages_ppl[logaddr]);
+}
+
+
+// TODO: what type of DMA this is, burst or cycle steal? Docs doesn't explain it (4 usec is the DRAM refresh). */
+// TODO: Erotictac and Poizone sets up vidinit register AFTER vidend, for double buffering? (fixes Poizone "Eterna" logo display on attract)
+// TODO: understand how to make quazer to work (sets video DMA param in-flight)
+void acorn_memc_device::do_video_dma()
+{
+ uint32_t size = (m_vidend - m_vidstart + 0x10) & 0x1fffff;
+ uint32_t offset_ptr = m_vidinit;
+
+ if (offset_ptr >= m_vidend + 0x10) // TODO: correct?
+ offset_ptr = m_vidstart;
+
+ //popmessage("%08x %08x %08x",m_vidstart, m_vidinit, m_vidend);
+
+ if (m_vidc.found())
+ {
+ for (m_vidcur = 0; m_vidcur < size; m_vidcur++)
+ {
+ m_vidc->write_vram(m_vidcur, m_space->read_byte(dram_address((offset_ptr))));
+ offset_ptr++;
+ if (offset_ptr >= m_vidend + 0x10) // TODO: correct?
+ offset_ptr = m_vidstart;
+ }
+
+ if (m_cursor_enabled)
+ {
+ uint16_t ccur_size = m_vidc->get_cursor_size() & 0x1ff;
+
+ for (int ccur = 0; ccur < ccur_size; ccur++)
+ m_vidc->write_cram(ccur, m_space->read_byte(dram_address((m_cinit + ccur))));
+ }
+ }
+}
+
+void acorn_memc_device::do_sound_dma()
+{
+ if (m_vidc.found())
+ {
+ for (int ch = 0; ch < 8; ch++)
+ m_vidc->write_dac(ch, m_space->read_byte(dram_address(m_sndcur + ch)));
+ }
+
+ m_sndcur += 8;
+
+ if (m_sndcur >= m_sndendcur)
+ {
+ m_sirq_w(ASSERT_LINE);
+
+ // TODO: nuke this implementation detail, repeated below
+ if (m_vidc.found())
+ m_vidc->update_sound_mode(m_sound_dma_on);
+
+ if (m_sound_dma_on)
+ {
+ //logerror("Chaining to next: start %x end %x\n", m_sndstart, m_sndend);
+ m_sndcur = m_sndstart;
+ m_sndendcur = m_sndend;
+ }
+ else if (m_vidc.found())
+ {
+ for (int ch=0; ch<8; ch++)
+ m_vidc->clear_dac(ch);
+ }
+ }
+}
+
+WRITE_LINE_MEMBER(acorn_memc_device::spvmd_w)
+{
+ m_spvmd = state;
+ m_abort_w(CLEAR_LINE);
+}
+
+WRITE_LINE_MEMBER(acorn_memc_device::sndrq_w)
+{
+ if (state && m_sound_dma_on)
+ do_sound_dma();
+}
+
+
+WRITE_LINE_MEMBER(acorn_memc_device::vidrq_w)
+{
+ if (state && m_video_dma_on)
+ do_video_dma();
+}
+
+uint32_t acorn_memc_device::dram_address(uint32_t address)
+{
+ if (m_output_dram_rowcol)
+ {
+ // The correct DRAM row / column for every page size is shown in Appendix A of the Acorn MEMC datasheet
+ // xx-- ---- ---- ---- ---- ---- MEMC (for systems with multiple MEMC)
+ // --xx xxxx xxxx ---- ---- ---- DRAM row
+ // ---- ---- ---- xxxx xxxx xx-- DRAM column
+ // ---- ---- ---- ---- ---- --xx CAS
+
+ switch (m_pagesize)
+ {
+ // Page size MEMC Unused DRAM row Unused DRAM column CAS Mask unused
+ case 0: address = bitswap<24>(address, 23, 22, 21,20, 11,10,9,8,7,6,5,4, 19, 18,17,16,15,14,13,12,3,2, 1,0) & 0xcff7ff; break;
+ case 1: address = bitswap<24>(address, 23, 22, 21, 12,11,10,9,8,7,6,5,4, 20, 18,17,16,15,14,13,19,3,2, 1,0) & 0xdff7ff; break;
+ case 2: address = bitswap<24>(address, 23, 22, 21, 12,11,10,9,8,7,6,5,4, 20,18,17,16,15,14,13,19,3,2, 1,0) & 0xdfffff; break;
+ case 3: address = bitswap<24>(address, 23, 22, 13,12,11,10,9,8,7,6,5,4, 20,18,17,16,15,14,21,19,3,2, 1,0) & 0xffffff; break;
+ }
+ }
+
+ return 0x02000000 | address;
+}
+
+uint32_t acorn_memc_device::logical_r(offs_t offset, uint32_t mem_mask)
+{
+ // are we mapping in the boot ROM?
+ if (m_latchrom)
+ return m_space->read_dword(0x3800000 | ((offset & 0x1fffff) << 2), mem_mask);
+
+ // figure out the page number and offset in the page
+ uint32_t pagesize = m_page_sizes[m_pagesize];
+ uint32_t page = (offset << 2) / pagesize;
+ uint32_t poffs = (offset << 2) % pagesize;
+
+ if (is_valid_access(page, false))
+ return m_space->read_dword(dram_address(m_pages[page] * pagesize + poffs), mem_mask);
+ else
+ return invalid_access(false, offset, 0, mem_mask);
+}
+
+
+void acorn_memc_device::logical_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ // if the boot ROM is mapped, ignore writes
+ if (m_latchrom)
+ return;
+
+ // figure out the page number and offset in the page
+ uint32_t pagesize = m_page_sizes[m_pagesize];
+ uint32_t page = (offset << 2) / pagesize;
+ uint32_t poffs = (offset << 2) % pagesize;
+
+ if (is_valid_access(page, true))
+ m_space->write_dword(dram_address(m_pages[page] * pagesize + poffs), data, mem_mask);
+ else
+ invalid_access(true, offset, data, mem_mask);
+}
+
+
+uint32_t acorn_memc_device::high_mem_r(offs_t offset, uint32_t mem_mask)
+{
+ uint32_t addr = offset << 2;
+ m_latchrom = false;
+
+ if (!m_spvmd)
+ return invalid_access(false, addr, 0, mem_mask);
+ else if (addr < 0x1000000) // DRAM
+ return m_space->read_dword(dram_address(addr), mem_mask);
+ else
+ return m_space->read_dword(0x2000000 | addr, mem_mask);
+}
+
+void acorn_memc_device::high_mem_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ uint32_t addr = offset << 2;
+ m_latchrom = false;
+
+ if (!m_spvmd)
+ invalid_access(true, addr, data, mem_mask);
+ else if (addr < 0x1000000) // DRAM
+ m_space->write_dword(dram_address(addr), data, mem_mask);
+ else
+ m_space->write_dword(0x2000000 | addr, data, mem_mask);
+}
diff --git a/src/devices/machine/acorn_memc.h b/src/devices/machine/acorn_memc.h
new file mode 100644
index 00000000000..f0b687ac195
--- /dev/null
+++ b/src/devices/machine/acorn_memc.h
@@ -0,0 +1,102 @@
+// license:LGPL-2.1+
+// copyright-holders:Angelo Salese, R. Belmont, Juergen Buchmueller, Sandro Ronco
+/**************************************************************************************************
+
+ Acorn RISC Machine Memory Controller (MEMC)
+
+**************************************************************************************************/
+
+#ifndef MAME_MACHINE_ACORN_MEMC_H
+#define MAME_MACHINE_ACORN_MEMC_H
+
+#pragma once
+
+#include "machine/acorn_vidc.h"
+
+//**************************************************************************
+// TYPE DEFINITIONS
+//**************************************************************************
+
+// ======================> acorn_memc_device
+
+class acorn_memc_device : public device_t, public device_memory_interface
+{
+public:
+ acorn_memc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ template <typename T>
+ acorn_memc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&vidc_tag)
+ : acorn_memc_device(mconfig, tag, owner, clock)
+ {
+ m_vidc.set_tag(std::forward<T>(vidc_tag));
+ }
+
+ auto abort_w() { return m_abort_w.bind(); }
+ auto sirq_w() { return m_sirq_w.bind(); }
+
+ // enable/disable the output of the correct DRAM row and column for DRAM access.
+ // This allows to emulate the correct DRAM mirrors that are used by RISC OS to detect the installed RAM,
+ // but requires a bitswap on every access and is not required by machines with 2 or more MB of RAM.
+ void output_dram_rowcol(bool v) { m_output_dram_rowcol = v; }
+
+ uint32_t logical_r(offs_t offset, uint32_t mem_mask = ~0);
+ void logical_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void page_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void registers_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t high_mem_r(offs_t offset, uint32_t mem_mask = ~0);
+ void high_mem_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+
+ DECLARE_WRITE_LINE_MEMBER(spvmd_w);
+ DECLARE_WRITE_LINE_MEMBER(sndrq_w);
+ DECLARE_WRITE_LINE_MEMBER(vidrq_w);
+
+protected:
+ // device-level overrides
+ virtual void device_resolve_objects() override;
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ // device_memory_interface overrides
+ virtual space_config_vector memory_space_config() const override;
+
+private:
+ void memc_map_debug_commands(int ref, const std::vector<std::string> &params);
+ uint32_t dram_address(uint32_t address);
+ bool is_valid_access(int page, bool write);
+ uint32_t invalid_access(bool is_write, offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ void do_sound_dma();
+ void do_video_dma();
+
+ static constexpr const int m_page_sizes[4] = { 4096, 8192, 16384, 32768 };
+ optional_device<acorn_vidc10_device> m_vidc;
+ const address_space_config m_space_config;
+
+ address_space * m_space;
+ devcb_write_line m_abort_w;
+ devcb_write_line m_sirq_w;
+ bool m_output_dram_rowcol;
+ int m_spvmd;
+ uint8_t m_pagesize;
+ bool m_latchrom;
+ bool m_video_dma_on;
+ bool m_sound_dma_on;
+ bool m_cursor_enabled;
+ bool m_os_mode;
+ uint32_t m_vidinit;
+ uint32_t m_vidstart;
+ uint32_t m_vidend;
+ uint32_t m_vidcur;
+ uint32_t m_cinit;
+ uint32_t m_sndstart;
+ uint32_t m_sndend;
+ uint32_t m_sndcur;
+ uint32_t m_sndendcur;
+ int16_t m_pages[0x2000]; // the logical RAM area is 32 megs, and the smallest page size is 4k
+ uint8_t m_pages_ppl[0x2000];
+};
+
+
+// device type definition
+DECLARE_DEVICE_TYPE(ACORN_MEMC, acorn_memc_device)
+
+#endif // MAME_MACHINE_ACORN_MEMC_H