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author Miodrag Milanovic <mmicko@gmail.com>2016-07-27 09:26:22 +0200
committer Miodrag Milanovic <mmicko@gmail.com>2016-07-27 09:26:22 +0200
commit4887ce18443a51fd2a861da959082ad346ff4ee2 (patch)
treef21e5096b569bff399a6e03c09715502ef859c34 /src/devices/machine
parent385f433cf4f7c3a2fa6012536a479de6ddddc68a (diff)
Cleanups and version bump
Diffstat (limited to 'src/devices/machine')
-rw-r--r--src/devices/machine/68230pit.cpp148
-rw-r--r--src/devices/machine/68230pit.h46
-rw-r--r--src/devices/machine/fga002.cpp202
-rw-r--r--src/devices/machine/fga002.h231
-rw-r--r--src/devices/machine/hp_taco.cpp4
-rw-r--r--src/devices/machine/input_merger.cpp8
-rw-r--r--src/devices/machine/input_merger.h2
-rw-r--r--src/devices/machine/pdc.cpp1
-rw-r--r--src/devices/machine/scnxx562.cpp494
-rw-r--r--src/devices/machine/scnxx562.h90
-rw-r--r--src/devices/machine/z80scc.cpp48
11 files changed, 635 insertions, 639 deletions
diff --git a/src/devices/machine/68230pit.cpp b/src/devices/machine/68230pit.cpp
index 3354738f954..fa7142c2306 100644
--- a/src/devices/machine/68230pit.cpp
+++ b/src/devices/machine/68230pit.cpp
@@ -5,13 +5,13 @@
* Motorola MC68230 PI/T Parallell Interface and Timer
*
* PORT MODES INCLUDE :
-* - BIT I/O
+* - BIT I/O
* - UNIDIRECTIONAL 8 BIT AND 16 BIT
-* - BIDIRECTIONAL 8 BIT AND 16 BIT
-* PROGRAMMABLE HANDSHAKING OPTIONS
-* 24-BIT PROGRAMMABLE TIMER MODES
-* FIVE SEPARATE INTERRUPT VECTORS SEPARATE PORT AND TIMER INTERRUPT SERVICE REQUESTS
-* REGISTERS AREREAD/WRITEAND DIRECTLY ADDRESSABLE
+* - BIDIRECTIONAL 8 BIT AND 16 BIT
+* PROGRAMMABLE HANDSHAKING OPTIONS
+* 24-BIT PROGRAMMABLE TIMER MODES
+* FIVE SEPARATE INTERRUPT VECTORS SEPARATE PORT AND TIMER INTERRUPT SERVICE REQUESTS
+* REGISTERS AREREAD/WRITEAND DIRECTLY ADDRESSABLE
* REGISTERS ARE ADDRESSED FOR MOVEP (Move Peripheral) AND DMAC COMPATIBILITY
*
* Revisions: 2015-07-15 JLE initial
@@ -77,9 +77,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, device_type type
, m_tcr(0)
, m_tivr(0)
, m_cpr(0)
- // , m_cprh(0) // Collectivelly handled by m_cpr
- // , m_cprm(0) // Collectivelly handled by m_cpr
- // , m_cprl(0) // Collectivelly handled by m_cpr
+ // , m_cprh(0) // Collectivelly handled by m_cpr
+ // , m_cprm(0) // Collectivelly handled by m_cpr
+ // , m_cprl(0) // Collectivelly handled by m_cpr
, m_cntr(0)
, m_tsr(0)
{
@@ -113,9 +113,9 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
, m_tcr(0)
, m_tivr(0)
, m_cpr(0)
- // , m_cprh(0) // Collectivelly handled by m_cpr
- // , m_cprm(0) // Collectivelly handled by m_cpr
- // , m_cprl(0) // Collectivelly handled by m_cpr
+ // , m_cprh(0) // Collectivelly handled by m_cpr
+ // , m_cprm(0) // Collectivelly handled by m_cpr
+ // , m_cprl(0) // Collectivelly handled by m_cpr
, m_cntr(0)
, m_tsr(0)
{
@@ -193,9 +193,9 @@ void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32
{
switch(id)
{
- case TIMER_ID_PIT:
+ case TIMER_ID_PIT:
if (m_cntr-- == 0) // Zero detect
- {
+ {
/* TODO: Check mode and use preload value if required or just rollover 24 bit */
if ((m_tcr & REG_TCR_ZD) == 0)
m_cntr = m_cpr;
@@ -203,9 +203,9 @@ void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32
m_cntr &= 0xffffff;
}
break;
- default:
- LOG(("Unhandled Timer ID %d\n", id));
- break;
+ default:
+ LOG(("Unhandled Timer ID %d\n", id));
+ break;
}
}
@@ -400,21 +400,21 @@ void pit68230_device::wr_pitreg_tcr(UINT8 data)
switch (m_tcr & REG_TCR_TOUT_TIACK_MASK)
{
case REG_TCR_PC3_PC7:
- case REG_TCR_PC3_PC7_DC: LOG(("- PC3 and PC7 used as I/O pins\n")); break;
+ case REG_TCR_PC3_PC7_DC: LOG(("- PC3 and PC7 used as I/O pins\n")); break;
case REG_TCR_TOUT_PC7_SQ:
- case REG_TCR_TOUT_PC7_SQ_DC: LOG(("- PC3 used as SQuare wave TOUT and PC7 used as I/O pin - not supported yet\n")); sqr = 1; break;
- case REG_TCR_TOUT_TIACK: LOG(("- PC3 used as TOUT and PC7 used as TIACK - not supported yet\n")); tout = 1; tiack = 1; break;
- case REG_TCR_TOUT_TIACK_INT: LOG(("- PC3 used as TOUT and PC7 used as TIACK, Interrupts enabled - not supported yet\n")); tout = 1; tiack = 1; irq = 1; break;
- case REG_TCR_TOUT_PC7: LOG(("- PC3 used as TOUT and PC7 used as I/O pin - not supported yet\n")); break;
- case REG_TCR_TOUT_PC7_INT: LOG(("- PC3 used as TOUT and PC7 used as I/O pin, Interrupts enabled - not supported yet\n")); break;
+ case REG_TCR_TOUT_PC7_SQ_DC: LOG(("- PC3 used as SQuare wave TOUT and PC7 used as I/O pin - not supported yet\n")); sqr = 1; break;
+ case REG_TCR_TOUT_TIACK: LOG(("- PC3 used as TOUT and PC7 used as TIACK - not supported yet\n")); tout = 1; tiack = 1; break;
+ case REG_TCR_TOUT_TIACK_INT: LOG(("- PC3 used as TOUT and PC7 used as TIACK, Interrupts enabled - not supported yet\n")); tout = 1; tiack = 1; irq = 1; break;
+ case REG_TCR_TOUT_PC7: LOG(("- PC3 used as TOUT and PC7 used as I/O pin - not supported yet\n")); break;
+ case REG_TCR_TOUT_PC7_INT: LOG(("- PC3 used as TOUT and PC7 used as I/O pin, Interrupts enabled - not supported yet\n")); break;
}
switch (m_tcr & REG_TCR_CC_MASK)
{
- case REG_TCR_CC_PC2_CLK_PSC: LOG(("- PC2 used as I/O pin,CLK and x32 prescaler are used\n")); clk = 1; psc = 1; break;
- case REG_TCR_CC_TEN_CLK_PSC: LOG(("- PC2 used as Timer enable/disable, CLK and presacaler are used\n")); pen = 1; clk = 1; psc = 1; break;
- case REG_TCR_CC_TIN_PSC: LOG(("- PC2 used as Timer clock and the presacaler is used - not supported yet\n")); psc = 1; break;
- case REG_TCR_CC_TIN_RAW: LOG(("- PC2 used as Timer clock and the presacaler is NOT used - not supported yet\n")); break;
+ case REG_TCR_CC_PC2_CLK_PSC: LOG(("- PC2 used as I/O pin,CLK and x32 prescaler are used\n")); clk = 1; psc = 1; break;
+ case REG_TCR_CC_TEN_CLK_PSC: LOG(("- PC2 used as Timer enable/disable, CLK and presacaler are used\n")); pen = 1; clk = 1; psc = 1; break;
+ case REG_TCR_CC_TIN_PSC: LOG(("- PC2 used as Timer clock and the presacaler is used - not supported yet\n")); psc = 1; break;
+ case REG_TCR_CC_TIN_RAW: LOG(("- PC2 used as Timer clock and the presacaler is NOT used - not supported yet\n")); break;
}
LOG(("%s", m_tcr & REG_TCR_ZR ? "- Spec violation, should always be 0!\n" : ""));
LOG(("- Timer %s when reaching 0 (zero)\n", m_tcr & REG_TCR_ZD ? "rolls over" : "reload the preload values"));
@@ -475,29 +475,29 @@ WRITE8_MEMBER (pit68230_device::write)
{
LOG(("%s %s \n",tag(), FUNCNAME));
switch (offset) {
- case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
- case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
- case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
- case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
- case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
- case PIT_68230_PIVR: wr_pitreg_pivr(data); break;
- case PIT_68230_PACR: wr_pitreg_pacr(data); break;
- case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
- case PIT_68230_PADR: wr_pitreg_padr(data); break;
- case PIT_68230_PBDR: wr_pitreg_pbdr(data); break;
- case PIT_68230_PAAR: break; // Ignores write per spec, read only register
- case PIT_68230_PBAR: break; // Ignores write per spec, read only register
- case PIT_68230_PCDR: wr_pitreg_pcdr(data); break;
- case PIT_68230_PSR: wr_pitreg_psr(data); break;
- case PIT_68230_TCR: wr_pitreg_tcr(data); break;
- case PIT_68230_TIVR: wr_pitreg_tivr(data); break;
- case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
- case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
- case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
- case PIT_68230_CNTRH: break; // Ignores write per spec, read only register
- case PIT_68230_CNTRM: break; // Ignores write per spec, read only register
- case PIT_68230_CNTRL: break; // Ignores write per spec, read only register
- case PIT_68230_TSR: wr_pitreg_tsr(data); break;
+ case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
+ case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
+ case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
+ case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
+ case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
+ case PIT_68230_PIVR: wr_pitreg_pivr(data); break;
+ case PIT_68230_PACR: wr_pitreg_pacr(data); break;
+ case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
+ case PIT_68230_PADR: wr_pitreg_padr(data); break;
+ case PIT_68230_PBDR: wr_pitreg_pbdr(data); break;
+ case PIT_68230_PAAR: break; // Ignores write per spec, read only register
+ case PIT_68230_PBAR: break; // Ignores write per spec, read only register
+ case PIT_68230_PCDR: wr_pitreg_pcdr(data); break;
+ case PIT_68230_PSR: wr_pitreg_psr(data); break;
+ case PIT_68230_TCR: wr_pitreg_tcr(data); break;
+ case PIT_68230_TIVR: wr_pitreg_tivr(data); break;
+ case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
+ case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
+ case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
+ case PIT_68230_CNTRH: break; // Ignores write per spec, read only register
+ case PIT_68230_CNTRM: break; // Ignores write per spec, read only register
+ case PIT_68230_CNTRL: break; // Ignores write per spec, read only register
+ case PIT_68230_TSR: wr_pitreg_tsr(data); break;
default:
LOG (("Unhandled Write of %02x to register %02x", data, offset));
}
@@ -601,7 +601,7 @@ UINT8 pit68230_device::rr_pitreg_pcdr()
return m_pcdr;
}
-/* The port A alternate register is an alternate register for reading the port A pins.
+/* The port A alternate register is an alternate register for reading the port A pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
the instantaneous pin level is read and no input latching is performed except at the
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
@@ -697,29 +697,29 @@ READ8_MEMBER (pit68230_device::read){
UINT8 data;
switch (offset) {
- case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
- case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
- case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
- case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
- case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
- case PIT_68230_PIVR: data = rr_pitreg_pivr(); break;
- case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
- case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
- case PIT_68230_PADR: data = rr_pitreg_padr(); break;
- case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
- case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
- case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
- case PIT_68230_PCDR: data = rr_pitreg_pcdr(); break;
- case PIT_68230_PSR: data = rr_pitreg_psr(); break;
- case PIT_68230_TCR: data = rr_pitreg_tcr(); break;
- case PIT_68230_TIVR: data = rr_pitreg_tivr(); break;
- case PIT_68230_CPRH: data = rr_pitreg_cprh(); break;
- case PIT_68230_CPRM: data = rr_pitreg_cprm(); break;
- case PIT_68230_CPRL: data = rr_pitreg_cprl(); break;
- case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
- case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
- case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
- case PIT_68230_TSR: data = rr_pitreg_tsr(); break;
+ case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
+ case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
+ case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
+ case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
+ case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
+ case PIT_68230_PIVR: data = rr_pitreg_pivr(); break;
+ case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
+ case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
+ case PIT_68230_PADR: data = rr_pitreg_padr(); break;
+ case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
+ case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
+ case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
+ case PIT_68230_PCDR: data = rr_pitreg_pcdr(); break;
+ case PIT_68230_PSR: data = rr_pitreg_psr(); break;
+ case PIT_68230_TCR: data = rr_pitreg_tcr(); break;
+ case PIT_68230_TIVR: data = rr_pitreg_tivr(); break;
+ case PIT_68230_CPRH: data = rr_pitreg_cprh(); break;
+ case PIT_68230_CPRM: data = rr_pitreg_cprm(); break;
+ case PIT_68230_CPRL: data = rr_pitreg_cprl(); break;
+ case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
+ case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
+ case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
+ case PIT_68230_TSR: data = rr_pitreg_tsr(); break;
default:
LOG (("Unhandled read register %02x\n", offset));
data = 0;
diff --git a/src/devices/machine/68230pit.h b/src/devices/machine/68230pit.h
index 0c304bd1970..06736741867 100644
--- a/src/devices/machine/68230pit.h
+++ b/src/devices/machine/68230pit.h
@@ -174,23 +174,23 @@ class pit68230_device : public device_t//, public device_execute_interface
protected:
enum {
- REG_TCR_ENABLE = 0x01,
- REG_TCR_CC_MASK = 0x06,
- REG_TCR_CC_PC2_CLK_PSC = 0x00,
- REG_TCR_CC_TEN_CLK_PSC = 0x02,
- REG_TCR_CC_TIN_PSC = 0x04,
- REG_TCR_CC_TIN_RAW = 0x06,
- REG_TCR_ZR = 0x08,
- REG_TCR_ZD = 0x10,
- REG_TCR_TOUT_TIACK_MASK = 0xe0, // 1 1 1
- REG_TCR_PC3_PC7 = 0x00, // 0 0 0
- REG_TCR_PC3_PC7_DC = 0x20, // 0 0 1
- REG_TCR_TOUT_PC7_SQ = 0x40, // 0 1 0
- REG_TCR_TOUT_PC7_SQ_DC = 0x60, // 0 1 1
- REG_TCR_TOUT_TIACK = 0x80, // 1 0 0
- REG_TCR_TOUT_TIACK_INT = 0xa0, // 1 0 1
- REG_TCR_TOUT_PC7 = 0xc0, // 1 1 0
- REG_TCR_TOUT_PC7_INT = 0xe0, // 1 1 1
+ REG_TCR_ENABLE = 0x01,
+ REG_TCR_CC_MASK = 0x06,
+ REG_TCR_CC_PC2_CLK_PSC = 0x00,
+ REG_TCR_CC_TEN_CLK_PSC = 0x02,
+ REG_TCR_CC_TIN_PSC = 0x04,
+ REG_TCR_CC_TIN_RAW = 0x06,
+ REG_TCR_ZR = 0x08,
+ REG_TCR_ZD = 0x10,
+ REG_TCR_TOUT_TIACK_MASK = 0xe0, // 1 1 1
+ REG_TCR_PC3_PC7 = 0x00, // 0 0 0
+ REG_TCR_PC3_PC7_DC = 0x20, // 0 0 1
+ REG_TCR_TOUT_PC7_SQ = 0x40, // 0 1 0
+ REG_TCR_TOUT_PC7_SQ_DC = 0x60, // 0 1 1
+ REG_TCR_TOUT_TIACK = 0x80, // 1 0 0
+ REG_TCR_TOUT_TIACK_INT = 0xa0, // 1 0 1
+ REG_TCR_TOUT_PC7 = 0xc0, // 1 1 0
+ REG_TCR_TOUT_PC7_INT = 0xe0, // 1 1 1
};
// device-level overrides
@@ -217,18 +217,18 @@ protected:
UINT8 m_paddr; // Port A Data Direction register
UINT8 m_pbddr; // Port B Data Direction register
UINT8 m_pcddr; // Port C Data Direction register
- UINT8 m_pivr; // Ports Interrupt vector
+ UINT8 m_pivr; // Ports Interrupt vector
UINT8 m_pacr; // Port A Control register
UINT8 m_pbcr; // Port B Control register
UINT8 m_padr; // Port A Data register
UINT8 m_pbdr; // Port B Data register
UINT8 m_pcdr; // Port C Data register
UINT8 m_psr; // Port Status Register
- UINT8 m_tcr; // Timer Control Register
- UINT8 m_tivr; // Timer Interrupt Vector register
- int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
- int m_cntr; // - The 24 bit Counter
- UINT8 m_tsr; // Timer Status Register
+ UINT8 m_tcr; // Timer Control Register
+ UINT8 m_tivr; // Timer Interrupt Vector register
+ int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
+ int m_cntr; // - The 24 bit Counter
+ UINT8 m_tsr; // Timer Status Register
// Timers
emu_timer *pit_timer;
diff --git a/src/devices/machine/fga002.cpp b/src/devices/machine/fga002.cpp
index 4cd77414612..ceb54043211 100644
--- a/src/devices/machine/fga002.cpp
+++ b/src/devices/machine/fga002.cpp
@@ -4,31 +4,31 @@
*
* Force Computer FGA-002 Force Gate Array
*
-* Documetation: http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/201559_FGA-002_Nov96.pdf
+* Documetation: http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/201559_FGA-002_Nov96.pdf
*
-* The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and containing 24,000 gates in a 281 pin PGA
-* package. It provides interfaces to the 68020/30 microprocessor as well as a VMEbus compatible interface.
-* The auxilary interface of the gate array is a high speed data channel used by the internal 32 bit DMA controller. The interface
-* allows data transfer rates of up to 6 MByte/second. The timing of the local I/O interface is programmable and provides
-* easy interfacing of local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly connected or
-* connected via buffers to the gate array allowing easy implementation and usage. The gate array registers are programmed by the local CPU.
+* The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and containing 24,000 gates in a 281 pin PGA
+* package. It provides interfaces to the 68020/30 microprocessor as well as a VMEbus compatible interface.
+* The auxilary interface of the gate array is a high speed data channel used by the internal 32 bit DMA controller. The interface
+* allows data transfer rates of up to 6 MByte/second. The timing of the local I/O interface is programmable and provides
+* easy interfacing of local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly connected or
+* connected via buffers to the gate array allowing easy implementation and usage. The gate array registers are programmed by the local CPU.
*
-* FEATURES:
-* - Programmable decoding for CPU and VME access to the local main memory
-* - Interrupt management for internal and external interrupt sources
-* - 32 bit multi-port DMA Controller
-* - FORCE Message Broadcast slave interface with 2 message channels
-* - 8 interrupt capable MAILBOXES
-* - 8 bit TIMER with 16 selectable internal source clocks
+* FEATURES:
+* - Programmable decoding for CPU and VME access to the local main memory
+* - Interrupt management for internal and external interrupt sources
+* - 32 bit multi-port DMA Controller
+* - FORCE Message Broadcast slave interface with 2 message channels
+* - 8 interrupt capable MAILBOXES
+* - 8 bit TIMER with 16 selectable internal source clocks
*
*
-* CAUTION (from the documentation - no unducumented registers are currently emulated )
-* The FGA-002 gate array contains registers, which are used to configure the gate array for special external hardware
-* requirements. These registers are reserved and will be setup by the boot software according to the hardware environment in which the gate array is
-* implemented. These registers must not be changed by the user. Some of these hardware configuration registers also contain user selectable bits.
-* Programming the contents of these registers has to be done carefully without changing the bits initialized by the boot software.
-* Registers not described must not be programmed. Unqualified changes of register bits may have unpredictable consequences for the gate array and
-* external hardware. It is expressly forbidden to change register bits, except those defined for the user.
+* CAUTION (from the documentation - no unducumented registers are currently emulated )
+* The FGA-002 gate array contains registers, which are used to configure the gate array for special external hardware
+* requirements. These registers are reserved and will be setup by the boot software according to the hardware environment in which the gate array is
+* implemented. These registers must not be changed by the user. Some of these hardware configuration registers also contain user selectable bits.
+* Programming the contents of these registers has to be done carefully without changing the bits initialized by the boot software.
+* Registers not described must not be programmed. Unqualified changes of register bits may have unpredictable consequences for the gate array and
+* external hardware. It is expressly forbidden to change register bits, except those defined for the user.
*
*/
#include "fga002.h"
@@ -112,14 +112,14 @@ void fga002_device::device_timer (emu_timer &timer, device_timer_id id, INT32 pa
{
switch(id)
{
- case TIMER_ID_FGA:
+ case TIMER_ID_FGA:
if (m_tim0count-- == 0) // Zero detect
- {
+ {
if ((m_fga002[FGA_TIM0CTL] & REG_TIM0CTL_ZERO_STOP) == 0)
{
fga_timer->adjust(attotime::never, TIMER_ID_FGA, attotime::never);
}
- else
+ else
{
if ((m_fga002[FGA_TIM0CTL] & REG_TIM0CTL_AUTOPRELOAD) == 0)
m_tim0count &= 0xff;
@@ -128,34 +128,34 @@ void fga002_device::device_timer (emu_timer &timer, device_timer_id id, INT32 pa
}
}
break;
- default:
- LOG(("Unhandled Timer ID %d\n", id));
- break;
+ default:
+ LOG(("Unhandled Timer ID %d\n", id));
+ break;
}
}
-/* The FGA002 Timer
+/* The FGA002 Timer
- FEATURES
- - 8 bit Synchronous Counter
- - 16 selectable clocks with frequencies from 1MHz to 0.5 Hz
- - Autopreload and Zerostop operating modes
- - Watchdog Timer operation
- - SYSFAIL and/or interrupt generation
- - Vectored interrupt
- - Interrupt levels selectable by software
+ FEATURES
+ - 8 bit Synchronous Counter
+ - 16 selectable clocks with frequencies from 1MHz to 0.5 Hz
+ - Autopreload and Zerostop operating modes
+ - Watchdog Timer operation
+ - SYSFAIL and/or interrupt generation
+ - Vectored interrupt
+ - Interrupt levels selectable by software
*/
-/* Timer Preload Register TIM0PRELOAD
- The Timer Preload Register TIM0PRELOAD contains the preset value which can be loaded into the counter circuit. The default
- value of this register after reset is $00. The TIM0PRELOAD register can be read at any time but must not be altered if the
- timer is running.
- [7:0] The Timer Preload register contains the 8 bit value that is loaded into the counter if the
- Autopreload option in the TIM0CTL register is selected and the counter reaches the value zero.
- Also, if a write access to the TIM0COUNT register is performed, the counter is loaded with the value
- stored in the Timer Preload Register.
+/* Timer Preload Register TIM0PRELOAD
+ The Timer Preload Register TIM0PRELOAD contains the preset value which can be loaded into the counter circuit. The default
+ value of this register after reset is $00. The TIM0PRELOAD register can be read at any time but must not be altered if the
+ timer is running.
+ [7:0] The Timer Preload register contains the 8 bit value that is loaded into the counter if the
+ Autopreload option in the TIM0CTL register is selected and the counter reaches the value zero.
+ Also, if a write access to the TIM0COUNT register is performed, the counter is loaded with the value
+ stored in the Timer Preload Register.
*/
void fga002_device::do_fga002reg_tim0preload_w(UINT8 data)
{
@@ -169,44 +169,44 @@ UINT8 fga002_device::do_fga002reg_tim0preload_r()
return m_fga002[FGA_TIM0PRELOAD];
}
-/* Timer Control Register TIM0CTL
- In the Timer Control Register TIM0CTL the operating mode and the clock source of the timer can be selected. The Timer
- Control Register is grouped into two major fields. Bits 7-4 define the operating mode of the timer and the sysfail option.
- Bits 3-0 select the source clock applied to the timer. The TIM0CTL register is cleared to $00 after any reset operation.
- [7] Zerostop This bit selects whether the counter stops when reaching zero count or continues counting down. The value the
- counter will decrement to next depends on the setting of bit 6 of this register, which is the Autopreload bit.
- 1 = The counter continues counting down.
- 0 = The counter stops on zero count.
- [6] Autopreload This bit selects whether the counter rolls over from $00 to the value $FF and continues counting down or is
- preset by the contents of the timer preload register after reaching the zero count. The Autopreload option may be
- ignored if the counter is programmed to stop on zero count.
- 1 The Autopreload option is enabled. When the counter has passed from $01 to $00, the value stored in the Preload
- register will be transferred to the counter on the first clock edge following the zero count clock. After
- that transfer the counter continues decrementing from the new value.
- 0 The Autopreload option is disabled. After the counter has reached zero it will roll over to the value $FF and
- continue counting down.
- [5] Sysfail This bit enables/disables the sysfail generation by the timer. If this option is enabled, the SFAILO output pin of the FGA-002
- gate array will be asserted low when the timer triggers the timer interrupt. The sysfail signal is negated when the timer
- interrupt is cleared. 1 = enabled 0 = disabled
- [4] Start/Stop: This bit controls the timer start and stop operation. 1 = start 0 = stop
- [3:0] Clock select This bitfield provides selection of the source clock for timer operation.
- 3..0 source clock period
- 0000 1 microsecond
- 0001 2 microseconds
- 0010 4 microseconds
- 0011 8 microseconds
- 0100 16 microseconds
- 0101 32 microseconds
- 0110 64 microseconds
- 0111 128 microseconds
- 1000 256 microseconds
- 1001 512 microseconds
- 1010 2 milliseconds
- 1011 8 milliseconds
- 1100 32 milliseconds
- 1101 125 milliseconds
- 1110 500 milliseconds
- 1111 2 seconds
+/* Timer Control Register TIM0CTL
+ In the Timer Control Register TIM0CTL the operating mode and the clock source of the timer can be selected. The Timer
+ Control Register is grouped into two major fields. Bits 7-4 define the operating mode of the timer and the sysfail option.
+ Bits 3-0 select the source clock applied to the timer. The TIM0CTL register is cleared to $00 after any reset operation.
+ [7] Zerostop This bit selects whether the counter stops when reaching zero count or continues counting down. The value the
+ counter will decrement to next depends on the setting of bit 6 of this register, which is the Autopreload bit.
+ 1 = The counter continues counting down.
+ 0 = The counter stops on zero count.
+ [6] Autopreload This bit selects whether the counter rolls over from $00 to the value $FF and continues counting down or is
+ preset by the contents of the timer preload register after reaching the zero count. The Autopreload option may be
+ ignored if the counter is programmed to stop on zero count.
+ 1 The Autopreload option is enabled. When the counter has passed from $01 to $00, the value stored in the Preload
+ register will be transferred to the counter on the first clock edge following the zero count clock. After
+ that transfer the counter continues decrementing from the new value.
+ 0 The Autopreload option is disabled. After the counter has reached zero it will roll over to the value $FF and
+ continue counting down.
+ [5] Sysfail This bit enables/disables the sysfail generation by the timer. If this option is enabled, the SFAILO output pin of the FGA-002
+ gate array will be asserted low when the timer triggers the timer interrupt. The sysfail signal is negated when the timer
+ interrupt is cleared. 1 = enabled 0 = disabled
+ [4] Start/Stop: This bit controls the timer start and stop operation. 1 = start 0 = stop
+ [3:0] Clock select This bitfield provides selection of the source clock for timer operation.
+ 3..0 source clock period
+ 0000 1 microsecond
+ 0001 2 microseconds
+ 0010 4 microseconds
+ 0011 8 microseconds
+ 0100 16 microseconds
+ 0101 32 microseconds
+ 0110 64 microseconds
+ 0111 128 microseconds
+ 1000 256 microseconds
+ 1001 512 microseconds
+ 1010 2 milliseconds
+ 1011 8 milliseconds
+ 1100 32 milliseconds
+ 1101 125 milliseconds
+ 1110 500 milliseconds
+ 1111 2 seconds
*/
void fga002_device::do_fga002reg_tim0ctl_w(UINT8 data)
@@ -250,12 +250,12 @@ UINT8 fga002_device::do_fga002reg_tim0ctl_r()
return m_fga002[FGA_TIM0CTL];
}
-/* Timer Count Register TIM0COUNT
- The Timer Count Register TIM0COUNT contains the current value of the timer/counter. A write access to this register will
- load the counter with the value stored in the Timer Preload Register. The written data will be ignored.
- It is permitted to perform read/write accesses to the Timer Count Register when the timer is running.
- The Timer Count Register is initialized to the value $FF after reset.
- [7:0] Timer Count Value
+/* Timer Count Register TIM0COUNT
+ The Timer Count Register TIM0COUNT contains the current value of the timer/counter. A write access to this register will
+ load the counter with the value stored in the Timer Preload Register. The written data will be ignored.
+ It is permitted to perform read/write accesses to the Timer Count Register when the timer is running.
+ The Timer Count Register is initialized to the value $FF after reset.
+ [7:0] Timer Count Value
*/
void fga002_device::do_fga002reg_tim0count_w(UINT8 data)
{
@@ -269,11 +269,11 @@ UINT8 fga002_device::do_fga002reg_tim0count_r()
return m_tim0count;
}
-/* Timer Interrupt Control Register ICRTIM0
- Timer Interrupt Control is performed by the Timer Interrupt Control Register ICRTIM0 which enables/disables the interrupt
- and selects the interrupt level.
- [3] IRQ enable, 1 = timer interrupt channel enabled, 0 = disabled
- [2:0] IRQ level 000 = interrupt disabled 001-111 = Level 1 to 7 interrupt
+/* Timer Interrupt Control Register ICRTIM0
+ Timer Interrupt Control is performed by the Timer Interrupt Control Register ICRTIM0 which enables/disables the interrupt
+ and selects the interrupt level.
+ [3] IRQ enable, 1 = timer interrupt channel enabled, 0 = disabled
+ [2:0] IRQ level 000 = interrupt disabled 001-111 = Level 1 to 7 interrupt
*/
void fga002_device::do_fga002reg_icrtim0_w(UINT8 data)
{
@@ -287,10 +287,10 @@ UINT8 fga002_device::do_fga002reg_icrtim0_r()
return m_fga002[FGA_ICRTIM0];
}
-/* Timer Interrupt Status Register ISTIM0
- ISTIM0 displays a pending timer interrupt. This bit is always readable and indicates 0 if the timer interrupt has been triggered. A write access to the
- ISTIM0 register clears the timer interrupt. The data written to this register will be ignored.
- [7] The IRQ Status register bit displays if a timer interrupt request is pending. 1 = no interrupt is pending. 0 = interrupt is pending
+/* Timer Interrupt Status Register ISTIM0
+ ISTIM0 displays a pending timer interrupt. This bit is always readable and indicates 0 if the timer interrupt has been triggered. A write access to the
+ ISTIM0 register clears the timer interrupt. The data written to this register will be ignored.
+ [7] The IRQ Status register bit displays if a timer interrupt request is pending. 1 = no interrupt is pending. 0 = interrupt is pending
[6:0] not used
*/
void fga002_device::do_fga002reg_istim0_w(UINT8 data)
@@ -390,7 +390,7 @@ WRITE8_MEMBER (fga002_device::write){
case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break;
case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break;
case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break;
- case FGA_ISTIM0 : do_fga002reg_istim0_w(data); break;
+ case FGA_ISTIM0 : do_fga002reg_istim0_w(data); break;
case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break;
case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break;
case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break;
@@ -401,7 +401,7 @@ WRITE8_MEMBER (fga002_device::write){
case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break;
case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break;
case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break;
- case FGA_TIM0COUNT : do_fga002reg_tim0count_w(data); break;
+ case FGA_TIM0COUNT : do_fga002reg_tim0count_w(data); break;
default:
LOG(("Unsupported register %04x\n", offset));
}
@@ -493,7 +493,7 @@ READ8_MEMBER (fga002_device::read){
case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break;
case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break;
case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break;
- case FGA_ISTIM0 : ret = do_fga002reg_istim0_r(); break;
+ case FGA_ISTIM0 : ret = do_fga002reg_istim0_r(); break;
case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break;
case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break;
case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break;
@@ -504,7 +504,7 @@ READ8_MEMBER (fga002_device::read){
case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break;
case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break;
case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break;
- case FGA_TIM0COUNT : ret = do_fga002reg_tim0count_r(); break;
+ case FGA_TIM0COUNT : ret = do_fga002reg_tim0count_r(); break;
default:
LOG(("Unsupported register %04x\n", offset));
}
diff --git a/src/devices/machine/fga002.h b/src/devices/machine/fga002.h
index 80401da5b84..86b7ffc7b4c 100644
--- a/src/devices/machine/fga002.h
+++ b/src/devices/machine/fga002.h
@@ -5,7 +5,7 @@
#include "emu.h"
-#define MCFG_FGA002_ADD(_tag, _clock) MCFG_DEVICE_ADD(_tag, FGA002, _clock)
+#define MCFG_FGA002_ADD(_tag, _clock) MCFG_DEVICE_ADD(_tag, FGA002, _clock)
//**************************************************************************
// TYPE DEFINITIONS
@@ -15,19 +15,19 @@
class fga002_device : public device_t
{
- public:
+ public:
// construction/destruction
fga002_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
fga002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_WRITE8_MEMBER (write);
DECLARE_READ8_MEMBER (read);
- protected:
+ protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr) override;
- private:
+ private:
UINT8 m_tim0count;
UINT8 m_fga002[0x500];
@@ -48,128 +48,128 @@ class fga002_device : public device_t
TIMER_ID_FGA
};
enum {
- REG_TIM0CTL_ZERO_STOP = 0x80,
- REG_TIM0CTL_AUTOPRELOAD = 0x40,
- REG_TIM0CTL_SYSFAIL = 0x20,
- REG_TIM0CTL_START_STOP = 0x10,
- REG_TIM0CTL_CLK_MSK = 0x0f,
- REG_TIM0CTL_CLK_1_MIC = 0x00,
- REG_TIM0CTL_CLK_2_MIC = 0x01,
- REG_TIM0CTL_CLK_4_MIC = 0x02,
- REG_TIM0CTL_CLK_8_MIC = 0x03,
- REG_TIM0CTL_CLK_16_MIC = 0x04,
- REG_TIM0CTL_CLK_32_MIC = 0x05,
- REG_TIM0CTL_CLK_64_MIC = 0x06,
- REG_TIM0CTL_CLK_128_MIC = 0x07,
- REG_TIM0CTL_CLK_256_MIC = 0x08,
- REG_TIM0CTL_CLK_512_MIC = 0x09,
- REG_TIM0CTL_CLK_2_MIL = 0x0a,
- REG_TIM0CTL_CLK_8_MIL = 0x0b,
- REG_TIM0CTL_CLK_32_MIL = 0x0c,
- REG_TIM0CTL_CLK_125_MIL = 0x0d,
- REG_TIM0CTL_CLK_500_MIL = 0x0e,
- REG_TIM0CTL_CLK_2_SEC = 0x0f,
+ REG_TIM0CTL_ZERO_STOP = 0x80,
+ REG_TIM0CTL_AUTOPRELOAD = 0x40,
+ REG_TIM0CTL_SYSFAIL = 0x20,
+ REG_TIM0CTL_START_STOP = 0x10,
+ REG_TIM0CTL_CLK_MSK = 0x0f,
+ REG_TIM0CTL_CLK_1_MIC = 0x00,
+ REG_TIM0CTL_CLK_2_MIC = 0x01,
+ REG_TIM0CTL_CLK_4_MIC = 0x02,
+ REG_TIM0CTL_CLK_8_MIC = 0x03,
+ REG_TIM0CTL_CLK_16_MIC = 0x04,
+ REG_TIM0CTL_CLK_32_MIC = 0x05,
+ REG_TIM0CTL_CLK_64_MIC = 0x06,
+ REG_TIM0CTL_CLK_128_MIC = 0x07,
+ REG_TIM0CTL_CLK_256_MIC = 0x08,
+ REG_TIM0CTL_CLK_512_MIC = 0x09,
+ REG_TIM0CTL_CLK_2_MIL = 0x0a,
+ REG_TIM0CTL_CLK_8_MIL = 0x0b,
+ REG_TIM0CTL_CLK_32_MIL = 0x0c,
+ REG_TIM0CTL_CLK_125_MIL = 0x0d,
+ REG_TIM0CTL_CLK_500_MIL = 0x0e,
+ REG_TIM0CTL_CLK_2_SEC = 0x0f,
};
enum {
- REG_ISTIM0_TIM_INT = 0x80,
+ REG_ISTIM0_TIM_INT = 0x80,
};
/* Register offsets */
enum {
- FGA_ICRMBOX0 = 0x0000,
- FGA_ICRMBOX1 = 0x0004,
- FGA_ICRMBOX2 = 0x0008,
- FGA_ICRMBOX3 = 0x000c,
- FGA_ICRMBOX4 = 0x0010,
- FGA_ICRMBOX5 = 0x0014,
- FGA_ICRMBOX6 = 0x0018,
- FGA_ICRMBOX7 = 0x001C,
- FGA_VMEPAGE = 0x0200,
- FGA_ICRVME1 = 0x0204,
- FGA_ICRVME2 = 0x0208,
- FGA_ICRVME3 = 0x020c,
- FGA_ICRVME4 = 0x0210,
- FGA_ICRVME5 = 0x0214,
- FGA_ICRVME6 = 0x0218,
- FGA_ICRVME7 = 0x021c,
- FGA_ICRTIM0 = 0x0220,
- FGA_ICRDMANORM = 0x0230,
- FGA_ICRDMAERR = 0x0234,
- FGA_CTL1 = 0x0238,
- FGA_CTL2 = 0x023c,
- FGA_ICRFMB0REF = 0x0240,
- FGA_ICRFMB1REF = 0x0244,
- FGA_ICRFMB0MES = 0x0248,
- FGA_ICRFMB1MES = 0x024c,
- FGA_CTL3 = 0x0250,
- FGA_CTL4 = 0x0254,
- FGA_ICRPARITY = 0x0258,
- FGA_AUXPINCTL = 0x0260,
- FGA_CTL5 = 0x0264,
- FGA_AUXFIFWEX = 0x0268,
- FGA_AUXFIFREX = 0x026c,
- FGA_CTL6 = 0x0270,
- FGA_CTL7 = 0x0274,
- FGA_CTL8 = 0x0278,
- FGA_CTL9 = 0x027c,
- FGA_ICRABORT = 0x0280,
- FGA_ICRACFAIL = 0x0284,
- FGA_ICRSYSFAIL = 0x0288,
- FGA_ICRLOCAL0 = 0x028c,
- FGA_ICRLOCAL1 = 0x0290,
- FGA_ICRLOCAL2 = 0x0294,
- FGA_ICRLOCAL3 = 0x0298,
- FGA_ICRLOCAL4 = 0x029c,
- FGA_ICRLOCAL5 = 0x02a0,
- FGA_ICRLOCAL6 = 0x02a4,
- FGA_ICRLOCAL7 = 0x02a8,
- FGA_ENAMCODE = 0x02b4,
- FGA_CTL10 = 0x02c0,
- FGA_CTL11 = 0x02c4,
- FGA_MAINUM = 0x02c8,
- FGA_MAINUU = 0x02cc,
+ FGA_ICRMBOX0 = 0x0000,
+ FGA_ICRMBOX1 = 0x0004,
+ FGA_ICRMBOX2 = 0x0008,
+ FGA_ICRMBOX3 = 0x000c,
+ FGA_ICRMBOX4 = 0x0010,
+ FGA_ICRMBOX5 = 0x0014,
+ FGA_ICRMBOX6 = 0x0018,
+ FGA_ICRMBOX7 = 0x001C,
+ FGA_VMEPAGE = 0x0200,
+ FGA_ICRVME1 = 0x0204,
+ FGA_ICRVME2 = 0x0208,
+ FGA_ICRVME3 = 0x020c,
+ FGA_ICRVME4 = 0x0210,
+ FGA_ICRVME5 = 0x0214,
+ FGA_ICRVME6 = 0x0218,
+ FGA_ICRVME7 = 0x021c,
+ FGA_ICRTIM0 = 0x0220,
+ FGA_ICRDMANORM = 0x0230,
+ FGA_ICRDMAERR = 0x0234,
+ FGA_CTL1 = 0x0238,
+ FGA_CTL2 = 0x023c,
+ FGA_ICRFMB0REF = 0x0240,
+ FGA_ICRFMB1REF = 0x0244,
+ FGA_ICRFMB0MES = 0x0248,
+ FGA_ICRFMB1MES = 0x024c,
+ FGA_CTL3 = 0x0250,
+ FGA_CTL4 = 0x0254,
+ FGA_ICRPARITY = 0x0258,
+ FGA_AUXPINCTL = 0x0260,
+ FGA_CTL5 = 0x0264,
+ FGA_AUXFIFWEX = 0x0268,
+ FGA_AUXFIFREX = 0x026c,
+ FGA_CTL6 = 0x0270,
+ FGA_CTL7 = 0x0274,
+ FGA_CTL8 = 0x0278,
+ FGA_CTL9 = 0x027c,
+ FGA_ICRABORT = 0x0280,
+ FGA_ICRACFAIL = 0x0284,
+ FGA_ICRSYSFAIL = 0x0288,
+ FGA_ICRLOCAL0 = 0x028c,
+ FGA_ICRLOCAL1 = 0x0290,
+ FGA_ICRLOCAL2 = 0x0294,
+ FGA_ICRLOCAL3 = 0x0298,
+ FGA_ICRLOCAL4 = 0x029c,
+ FGA_ICRLOCAL5 = 0x02a0,
+ FGA_ICRLOCAL6 = 0x02a4,
+ FGA_ICRLOCAL7 = 0x02a8,
+ FGA_ENAMCODE = 0x02b4,
+ FGA_CTL10 = 0x02c0,
+ FGA_CTL11 = 0x02c4,
+ FGA_MAINUM = 0x02c8,
+ FGA_MAINUU = 0x02cc,
FGA_BOTTOMPAGEU = 0x02d0,
FGA_BOTTOMPAGEL = 0x02d4,
- FGA_TOPPAGEU = 0x02d8,
- FGA_TOPPAGEL = 0x02dc,
- FGA_MYVMEPAGE = 0x02fc,
+ FGA_TOPPAGEU = 0x02d8,
+ FGA_TOPPAGEL = 0x02dc,
+ FGA_MYVMEPAGE = 0x02fc,
FGA_TIM0PRELOAD = 0x0300,
- FGA_TIM0CTL = 0x0310,
- FGA_DMASRCATT = 0x0320,
- FGA_DMADSTATT = 0x0324,
- FGA_DMA_GENERAL = 0x0328,
- FGA_CTL12 = 0x032c,
- FGA_LIOTIMING = 0x0330,
- FGA_LOCALIACK = 0x0334,
- FGA_FMBCTL = 0x0338,
- FGA_FMBAREA = 0x033c,
+ FGA_TIM0CTL = 0x0310,
+ FGA_DMASRCATT = 0x0320,
+ FGA_DMADSTATT = 0x0324,
+ FGA_DMA_GENERAL = 0x0328,
+ FGA_CTL12 = 0x032c,
+ FGA_LIOTIMING = 0x0330,
+ FGA_LOCALIACK = 0x0334,
+ FGA_FMBCTL = 0x0338,
+ FGA_FMBAREA = 0x033c,
FGA_AUXSRCSTART = 0x0340,
FGA_AUXDSTSTART = 0x0344,
- FGA_AUXSRCTERM = 0x0348,
- FGA_AUXDSTTERM = 0x034c,
- FGA_CTL13 = 0x0350,
- FGA_CTL14 = 0x0354,
- FGA_CTL15 = 0x0358,
- FGA_CTL16 = 0x035c,
- FGA_SPECIALENA = 0x0424,
- FGA_ISTIM0 = 0x04a0,
- FGA_ISDMANORM = 0x04b0,
- FGA_ISDMAERR = 0x04b4,
- FGA_ISFMB0REF = 0x04b8,
- FGA_ISFMB1REF = 0x04bc,
- FGA_ISPARITY = 0x04c0,
- FGA_DMARUNCTL = 0x04c4,
- FGA_ISABORT = 0x04c8,
- FGA_ISACFAIL = 0x04cc,
- FGA_ISFMB0MES = 0x04e0,
- FGA_ISFMB1MES = 0x04e4,
- FGA_ISSYSFAIL = 0x04d0,
- FGA_ABORTPIN = 0x04d4,
- FGA_RSVMECALL = 0x04f0,
- FGA_RSKEYRES = 0x04f4,
- FGA_RSCPUCALL = 0x04f8,
- FGA_RSLOCSW = 0x04fc,
- FGA_TIM0COUNT = 0x0c00,
+ FGA_AUXSRCTERM = 0x0348,
+ FGA_AUXDSTTERM = 0x034c,
+ FGA_CTL13 = 0x0350,
+ FGA_CTL14 = 0x0354,
+ FGA_CTL15 = 0x0358,
+ FGA_CTL16 = 0x035c,
+ FGA_SPECIALENA = 0x0424,
+ FGA_ISTIM0 = 0x04a0,
+ FGA_ISDMANORM = 0x04b0,
+ FGA_ISDMAERR = 0x04b4,
+ FGA_ISFMB0REF = 0x04b8,
+ FGA_ISFMB1REF = 0x04bc,
+ FGA_ISPARITY = 0x04c0,
+ FGA_DMARUNCTL = 0x04c4,
+ FGA_ISABORT = 0x04c8,
+ FGA_ISACFAIL = 0x04cc,
+ FGA_ISFMB0MES = 0x04e0,
+ FGA_ISFMB1MES = 0x04e4,
+ FGA_ISSYSFAIL = 0x04d0,
+ FGA_ABORTPIN = 0x04d4,
+ FGA_RSVMECALL = 0x04f0,
+ FGA_RSKEYRES = 0x04f4,
+ FGA_RSCPUCALL = 0x04f8,
+ FGA_RSLOCSW = 0x04fc,
+ FGA_TIM0COUNT = 0x0c00,
};
};
@@ -178,4 +178,3 @@ class fga002_device : public device_t
// device type definition
extern const device_type FGA002;
#endif // __FGA002_H__
-
diff --git a/src/devices/machine/hp_taco.cpp b/src/devices/machine/hp_taco.cpp
index 4938d2f4c4b..adb369c59f2 100644
--- a/src/devices/machine/hp_taco.cpp
+++ b/src/devices/machine/hp_taco.cpp
@@ -183,8 +183,8 @@ enum {
#define SHORT_GAP_LENGTH ((tape_pos_t)(0.066 * ONE_INCH_POS)) // Minimum length of short gaps: 0.066" ([1], pg 8-10)
#define LONG_GAP_LENGTH ((tape_pos_t)(1.5 * ONE_INCH_POS)) // Minimum length of long gaps: 1.5" ([1], pg 8-10)
#define NULL_TAPE_POS ((tape_pos_t)-1) // Special value for invalid/unknown tape position
-#define PREAMBLE_TIMEOUT ((tape_pos_t)(2.6 * ONE_INCH_POS)) // Min. length of gap making preamble search time out (totally made up)
-#define DATA_TIMEOUT ((tape_pos_t)(0.066 * ONE_INCH_POS)) // Min. length of gap that will cause data reading to time out (totally made up)
+#define PREAMBLE_TIMEOUT ((tape_pos_t)(2.6 * ONE_INCH_POS)) // Min. length of gap making preamble search time out (totally made up)
+#define DATA_TIMEOUT ((tape_pos_t)(0.066 * ONE_INCH_POS)) // Min. length of gap that will cause data reading to time out (totally made up)
#define FILE_MAGIC 0x4f434154 // Magic value at start of image file: "TACO"
// Parts of command register
diff --git a/src/devices/machine/input_merger.cpp b/src/devices/machine/input_merger.cpp
index d75a3f994d2..ceedca5d556 100644
--- a/src/devices/machine/input_merger.cpp
+++ b/src/devices/machine/input_merger.cpp
@@ -64,8 +64,8 @@ void input_merger_device::device_start()
// input_merger_active_high_device - constructor
//-------------------------------------------------
-input_merger_active_high_device::input_merger_active_high_device(machine_config const &mconfig, char const *tag, device_t *owner, UINT32 clock)
- : input_merger_device(mconfig, INPUT_MERGER_ACTIVE_HIGH, "Input Merger (Active High)", tag, owner, clock, "input_merger_hi", __FILE__)
+input_merger_active_high_device::input_merger_active_high_device(machine_config const &mconfig, char const *tag, device_t *owner, UINT32 clock)
+ : input_merger_device(mconfig, INPUT_MERGER_ACTIVE_HIGH, "Input Merger (Active High)", tag, owner, clock, "input_merger_hi", __FILE__)
{
}
@@ -97,8 +97,8 @@ void input_merger_active_high_device::update_state()
// input_merger_active_low_device - constructor
//-------------------------------------------------
-input_merger_active_low_device::input_merger_active_low_device(machine_config const &mconfig, char const *tag, device_t *owner, UINT32 clock)
- : input_merger_device(mconfig, INPUT_MERGER_ACTIVE_LOW, "Input Merger (Active Low)", tag, owner, clock, "input_merger_lo", __FILE__)
+input_merger_active_low_device::input_merger_active_low_device(machine_config const &mconfig, char const *tag, device_t *owner, UINT32 clock)
+ : input_merger_device(mconfig, INPUT_MERGER_ACTIVE_LOW, "Input Merger (Active Low)", tag, owner, clock, "input_merger_lo", __FILE__)
{
}
diff --git a/src/devices/machine/input_merger.h b/src/devices/machine/input_merger.h
index 9ede71f2ab8..c649d723b55 100644
--- a/src/devices/machine/input_merger.h
+++ b/src/devices/machine/input_merger.h
@@ -2,7 +2,7 @@
// copyright-holders:Dirk Best
/***************************************************************************
- Input Merger
+ Input Merger
Used to connect multiple lines to a single device input while
keeping it pulled high or low
diff --git a/src/devices/machine/pdc.cpp b/src/devices/machine/pdc.cpp
index b993531a14b..f5a75d87f72 100644
--- a/src/devices/machine/pdc.cpp
+++ b/src/devices/machine/pdc.cpp
@@ -324,7 +324,6 @@ pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t
void pdc_device::device_start()
{
-
/* Save States */
save_item(NAME(reg_p0));
save_item(NAME(reg_p1));
diff --git a/src/devices/machine/scnxx562.cpp b/src/devices/machine/scnxx562.cpp
index cbd3f67a861..491e00ccdca 100644
--- a/src/devices/machine/scnxx562.cpp
+++ b/src/devices/machine/scnxx562.cpp
@@ -37,12 +37,12 @@ DONE (x) (p=partly) NMOS CMOS
Synch data rates 4Mbps 10Mbps
----- asynchrounous features ------------------
x 5-8 bit per char Y Y
- p 1-2 stop bits Y Y TODO: 1/16 bit increments
- p odd/even parity Y Y TODO: parity generation on Tx
+ p 1-2 stop bits Y Y TODO: 1/16 bit increments
+ p odd/even parity Y Y TODO: parity generation on Tx
x1,x16 Y Y
break det/gen Y Y
- p parity, framing & Y Y TODO: parity check on Rx
- overrun error det
+ p parity, framing & Y Y TODO: parity check on Rx
+ overrun error det
-- byte oriented synchrounous features --
Int/ext char sync Y Y
1/2 synch chars ? ?
@@ -58,7 +58,7 @@ DONE (x) (p=partly) NMOS CMOS
--
x Receiver FIFO 4 16
x Transmitter FIFO 4 16
- NRZ, NRZI, FM1 or Y Y
+ NRZ, NRZI, FM1 or Y Y
FM2 enc/dec
Manchester dec Y Y
x Baud gen per chan Y Y
@@ -88,7 +88,7 @@ DONE (x) (p=partly) NMOS CMOS
#define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#define LOGR(x)
+#define LOGR(x)
#if VERBOSE > 1
#define logerror printf
#endif
@@ -276,13 +276,13 @@ void duscc_device::device_reset()
Each of the above conditions occupies a bit in the General Status Register (GSR). If ICR[2] is set, the eight conditions are encoded
into three bits which are inserted into bits [2:0] or [4:2] of the interrupt vector register. This forms the content of the IVRM during
an interrupt acknowledge cycle. Unmodified and modified vectors can read directly through specified registers. Two of the conditions
- are the inclusive OR of several other maskable conditions:
+ are the inclusive OR of several other maskable conditions:
- Extemal or CIT special condition: Delta DCD, Delta CTS or CIT zero count (ICTSR[6:4j).
- Rxrrx error or special condition: any condition in the Receiver Status Register (RSR[7:0J) or a transmitter or DPLL condition in
the Transmitter and Receiver Status Register (TRSR[7:3J).
The TxRDY and RxRDY conditions are defined by OMR[4] and OMR[3], respectively. Also associated with the interrupt system are
the Interrupt Enable Register (IER), one bit in the Countermmer Control Register (CTCR), and the Interrupt Control Register (lCR).
-
+
The IER is programmed to enable specified conditions or groups of conditions to cause an interrupt by asserting the corresponding bit.
A negated bit prevents an interrupt from occurring when the condition is active and hence masks the interrupt. In addition to the
IER, CTCR[?] could be programmed to enable or disable an interrupt upon the CfT zero count condition. The interrupt priorities
@@ -292,7 +292,7 @@ void duscc_device::device_reset()
is to cause an interrupt. The CPU vector mode is specified by ICR[5:4] which selects either vectored or non-vectored operation. If
vectored mode is selected, the content of the IVR or IVRM is placed on the data bus when lACK is activated. If ICR[2] is set, the content
of IVRM is output which contains the content of IVR and the encoded status of the interrupting condition.
- Upon receiving an interrupt acknowledge, the DUSCC locks its current interrupt status until the end of the acknowledge cycle.
+ Upon receiving an interrupt acknowledge, the DUSCC locks its current interrupt status until the end of the acknowledge cycle.
If it has an active interrupt pending, it responds with the appropriate vector and then asserts DTACKN. If it does not have an interrupt, it
propagates the acknowledge through its X2/1DCN output if this function is programmed in PCRA[7]; otherwise, the IACKN is
ignored. Locking the interrupt status at the leading edge of IACKN prevents a device at a High position in the interrupt daisy chain from
@@ -306,8 +306,8 @@ int duscc_device::z80daisy_irq_state()
int state = 0;
LOG(("%s %s A:[%02x][%02x][%02x][%02x] B:[%02x][%02x][%02x][%02x] ",tag(), FUNCNAME,
- m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3],
- m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7]));
+ m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3],
+ m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7]));
// loop over all interrupt sources
for (auto & elem : m_int_state)
@@ -333,7 +333,6 @@ int duscc_device::z80daisy_irq_state()
int duscc_device::z80daisy_irq_ack()
{
-
LOG(("%s %s()\n",tag(), FUNCNAME));
// loop over all interrupt sources
@@ -360,7 +359,6 @@ int duscc_device::z80daisy_irq_ack()
void duscc_device::z80daisy_irq_reti()
{
-
LOG(("%s %s \n",tag(), FUNCNAME));
// loop over all interrupt sources
@@ -381,7 +379,7 @@ void duscc_device::z80daisy_irq_reti()
void duscc_device::check_interrupts()
{
LOG(("%s %s()\n",tag(), FUNCNAME));
- int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE;
+ int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE;
// "If no interrupt is pending, an H'FF' is output when reading the IVRM."
if (state == 0)
@@ -431,8 +429,8 @@ UINT8 duscc_device::modify_vector(UINT8 vec, int i, UINT8 src)
if ((m_icr & REG_ICR_VEC_MOD) != 0) // Affect vector?
{
// Modify vector according to "Vector Include Status" bit (REG_ICR_V2V4_MOD)
- if ((m_icr & REG_ICR_V2V4_MOD) != 0)
- { // Affect V2-V4
+ if ((m_icr & REG_ICR_V2V4_MOD) != 0)
+ { // Affect V2-V4
vec &= 0x07 << 3;
vec |= src << 3;
}
@@ -447,7 +445,7 @@ UINT8 duscc_device::modify_vector(UINT8 vec, int i, UINT8 src)
/* Interrupt Control and Status Registers
- This group of registers define mechanisms for communications between the DUSCC and the processor and contain the device status
+ This group of registers define mechanisms for communications between the DUSCC and the processor and contain the device status
information. Four registers, available for each channel, and four common device registers comprise this group which consists of
the following:
1. Interrupt Enable Register (IERA/B).
@@ -538,11 +536,11 @@ duscc_channel::duscc_channel(const machine_config &mconfig, const char *tag, dev
LOG(("%s\n",FUNCNAME));
// Reset all registers
- m_cmr1 = m_cmr2 = m_s1r = m_s2r = m_tpr = m_ttr = m_rpr = m_rtr
- = /* m_ctprh = m_ctprl = */ m_ctpr = m_ctcr = m_omr
- = /* m_cth = m_ctl = */ m_ct = m_pcr
+ m_cmr1 = m_cmr2 = m_s1r = m_s2r = m_tpr = m_ttr = m_rpr = m_rtr
+ = /* m_ctprh = m_ctprl = */ m_ctpr = m_ctcr = m_omr
+ = /* m_cth = m_ctl = */ m_ct = m_pcr
= m_ccr = m_rsr = m_trsr = m_ictsr /*= m_gsr*/ = m_ier /*= m_rea*/
- = m_cid = /*m_ivr = m_icr = m_sea = m_ivrm = */ m_mrr = m_ier1
+ = m_cid = /*m_ivr = m_icr = m_sea = m_ivrm = */ m_mrr = m_ier1
= m_ier2 = m_ier3 = m_trcr = m_rflr = m_ftlr = m_trmsr = m_telr = 0;
// Reset all states
@@ -591,13 +589,13 @@ void duscc_channel::device_start()
save_item(NAME(m_ttr));
save_item(NAME(m_rpr));
save_item(NAME(m_rtr));
- // save_item(NAME(m_ctprh));
- // save_item(NAME(m_ctprl));
+ // save_item(NAME(m_ctprh));
+ // save_item(NAME(m_ctprl));
save_item(NAME(m_ctpr));
save_item(NAME(m_ctcr));
save_item(NAME(m_omr));
- // save_item(NAME(m_cth));
- // save_item(NAME(m_ctl));
+ // save_item(NAME(m_cth));
+ // save_item(NAME(m_ctl));
save_item(NAME(m_ct));
save_item(NAME(m_pcr));
save_item(NAME(m_ccr));
@@ -606,14 +604,14 @@ void duscc_channel::device_start()
save_item(NAME(m_rsr));
save_item(NAME(m_trsr));
save_item(NAME(m_ictsr));
- // save_item(NAME(m_gsr)); // Moved this to the device instead, it is a global register
+ // save_item(NAME(m_gsr)); // Moved this to the device instead, it is a global register
save_item(NAME(m_ier));
- // save_item(NAME(m_rea));
+ // save_item(NAME(m_rea));
save_item(NAME(m_cid));
- // save_item(NAME(m_ivr)); // Moved this to the device instead, it is a global register
- // save_item(NAME(m_icr)); // Moved this to the device instead, it is a global register
- // save_item(NAME(m_sea));
- // save_item(NAME(m_ivrm)); // Moved this to the device instead, it is a global register
+ // save_item(NAME(m_ivr)); // Moved this to the device instead, it is a global register
+ // save_item(NAME(m_icr)); // Moved this to the device instead, it is a global register
+ // save_item(NAME(m_sea));
+ // save_item(NAME(m_ivrm)); // Moved this to the device instead, it is a global register
save_item(NAME(m_mrr));
save_item(NAME(m_ier1));
save_item(NAME(m_ier2));
@@ -642,7 +640,7 @@ void duscc_channel::device_start()
save_item(NAME(m_rts));
save_item(NAME(m_sync));
- // device_serial_interface::register_save_state(machine().save(), this);
+ // device_serial_interface::register_save_state(machine().save(), this);
}
@@ -659,39 +657,39 @@ void duscc_channel::device_reset()
transmit_register_reset();
// Soft/Channel Reset values according to DUSCC users guide
- m_cmr1 =0x00;
- m_cmr2 =0x00;
- m_s1r =0x00;
- m_s2r =0x00;
- m_tpr =0x00;
- m_ttr =0x00;
- m_rpr =0x00;
- m_rtr =0x00;
- m_ctcr =0x00;
- m_omr =0x00;
- m_pcr =0x00;
- m_ccr =0x00;
- m_rsr =0x00;
- m_trsr =0x00;
- m_ictsr =0x00;
- // m_gsr =0x00;
- m_ier =0x00;
- // m_rea =0x00;
- // m_ivr =0x0f;
- // m_icr =0x00;
- // m_sea =0x00;
- // m_ivrm =0x00;
- m_mrr =0x00; // TODO: Need a read after reset to enable CMOS features
- m_ier1 =0x00;
- m_ier2 =0x00;
- m_ier3 =0x00;
- m_trcr =0x00;
- m_rflr =0x00;
- m_ftlr =0x33;
- m_trmsr =0x00;
- m_telr =0x10;
- m_rtxc =0x00;
- m_trxc =0x00;
+ m_cmr1 =0x00;
+ m_cmr2 =0x00;
+ m_s1r =0x00;
+ m_s2r =0x00;
+ m_tpr =0x00;
+ m_ttr =0x00;
+ m_rpr =0x00;
+ m_rtr =0x00;
+ m_ctcr =0x00;
+ m_omr =0x00;
+ m_pcr =0x00;
+ m_ccr =0x00;
+ m_rsr =0x00;
+ m_trsr =0x00;
+ m_ictsr =0x00;
+ // m_gsr =0x00;
+ m_ier =0x00;
+ // m_rea =0x00;
+ // m_ivr =0x0f;
+ // m_icr =0x00;
+ // m_sea =0x00;
+ // m_ivrm =0x00;
+ m_mrr =0x00; // TODO: Need a read after reset to enable CMOS features
+ m_ier1 =0x00;
+ m_ier2 =0x00;
+ m_ier3 =0x00;
+ m_trcr =0x00;
+ m_rflr =0x00;
+ m_ftlr =0x33;
+ m_trmsr =0x00;
+ m_telr =0x10;
+ m_rtxc =0x00;
+ m_trxc =0x00;
// reset external lines TODO: check relation to control bits and reset
@@ -711,14 +709,14 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
{
switch(id)
{
- case TIMER_ID:
- if (m_ct-- == 0) // Zero detect
- {
+ case TIMER_ID:
+ if (m_ct-- == 0) // Zero detect
+ {
m_ictsr |= REG_ICTSR_ZERO_DET; // set zero detection bit
// Generate interrupt?
- if ( ( (m_ctcr & REG_CTCR_ZERO_DET_INT) == 1 ) &&
- ( (m_uart->m_icr & (m_index == duscc_device::CHANNEL_A ? duscc_device::REG_ICR_CHA : duscc_device::REG_ICR_CHB) ) != 0) )
+ if ( ( (m_ctcr & REG_CTCR_ZERO_DET_INT) == 1 ) &&
+ ( (m_uart->m_icr & (m_index == duscc_device::CHANNEL_A ? duscc_device::REG_ICR_CHA : duscc_device::REG_ICR_CHB) ) != 0) )
{
//trigger_interrupt();
}
@@ -728,7 +726,7 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
{
m_ct = m_ctpr;
}
- else
+ else
{
m_ct = 0xffff;
}
@@ -774,7 +772,7 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
m_ictsr &= ~REG_ICTSR_ZERO_DET;
}
break;
- case TIMER_ID_RTXC: // Terminate zero detection pulse
+ case TIMER_ID_RTXC: // Terminate zero detection pulse
m_rtxc = 0;
rtxc_timer->adjust(attotime::never);
if (m_index == duscc_device::CHANNEL_A)
@@ -782,7 +780,7 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
else
m_uart->m_out_rtxcb_cb(m_rtxc);
break;
- case TIMER_ID_TRXC: // Terminate zero detection pulse
+ case TIMER_ID_TRXC: // Terminate zero detection pulse
m_trxc = 0;
trxc_timer->adjust(attotime::never);
if (m_index == duscc_device::CHANNEL_A)
@@ -790,53 +788,53 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
else
m_uart->m_out_trxcb_cb(m_trxc);
break;
- default:
- LOGR(("Unhandled Timer ID %d\n", id));
- break;
+ default:
+ LOGR(("Unhandled Timer ID %d\n", id));
+ break;
}
// LOG(("%s %d\n", FUNCNAME, id));
device_serial_interface::device_timer(timer, id, param, ptr);
}
-/* The DUSCC 16 bit Timer
- Counter/Timer Control and Value Registers
- There are five registers in this set consisting of the following:
- 1. Counterltimer control register (CTCRAlB).
- 2. Counterltimer preset Highland Low registers (CTPRHAlB, CTPRLAlB).
- 3. Counter/bmer (current value) High and Low registers (CTHAlB, CTLAlB)
- The control register contains the operational information for the counterltimer. The preset registers contain the count which is
- loaded into the counterltimer circuits. The third group contains the current value of the counterltimer as it operates.
+/* The DUSCC 16 bit Timer
+ Counter/Timer Control and Value Registers
+ There are five registers in this set consisting of the following:
+ 1. Counterltimer control register (CTCRAlB).
+ 2. Counterltimer preset Highland Low registers (CTPRHAlB, CTPRLAlB).
+ 3. Counter/bmer (current value) High and Low registers (CTHAlB, CTLAlB)
+ The control register contains the operational information for the counterltimer. The preset registers contain the count which is
+ loaded into the counterltimer circuits. The third group contains the current value of the counterltimer as it operates.
*/
/* Counter/Timer Control Register (CTCRA/CTCRB)
- [7] Zero Detect Interrupt - This bit determines whether the assertion of the CIT ZERO COUNT status bit (ICTSR[6)) causes an
- interrupt to be generated if set to 1 and the Master interrupt control bit (ICR[0:1]) is set
- [6] Zero Detect Control - his bit determines the action of the counter upon reaching zero count
- 0 - The counter/timer is preset to the value contained in the counterltimer preset registers (CTPRL, CTPRH) at the next clock edge.
- 1 - The counterltimer continues counting without preset. The value at the next clock edge will be H'FFFF'.
- [5] CounterlTimer Output Control - This bit selects the output waveform when the counterltimer is selected to be output on TRxC or RTxC.
- 0 - The output toggles each time the CIT reaches zero count. The output is cleared to Low by either of the preset counterltimer commands.
- 1 - The output is a single clock positive width pulse each time the CIT reaches zero count. (The duration of this pulse is one clock period.)
- [4:3] Clock Select - This field selects whether the clock selected by [2:0J is prescaled prior to being applied to the input of the CIT.
- 0 0 No prescaling.
- 0 1 Divide clock by 16.
- 1 0 Divide clock by 32.
- 1 1 Divide clock by 64.
- [2:0] Clock Source - This field selects the clock source for the counterltimer.
- 000 RTxC pin. Pin must be programmed as input.
- 001 TRxC pin. Pin must be programmed as input.
- 010 Source is the crystal oscillator or system clock input divided by four.
- 011 This selects a special mode of operation. In this mode the counter, after receiving the 'start CIT' command, delays the
- start of counting until the RxD input goes Low. It continues counting until the RxD input goes High, then stops and sets
- the CIT zero count status bit. The CPU can use the value in the CIT to determine the bit rate of the incoming data.
- The clock is the crystal oscillator or system clock input divided by four.
- 100 Source is the 32X BRG output selected by RTR[3:0J of own channel.
- 101 Source is the 32X BRG output selected by TTR[3:0J of own channel.
- 110 Source is the internal signal which loads received characters from the receive shift register into the receiver
- FIFO. When operating in this mode, the FIFOed EOM status bit (RSR[7)) shall be set when the character which
- causes the count to go to zero is loaded into the receive FIFO.
- 111 Source is the internal signal which transfers characters from the data bus into the transmit FIFO. When operating in this
- mode, and if the TEOM on zero count or done control bit (TPR[4)) is asserted, the FIFOed send EOM command will
- be automatically asserted when the character which causes the count to go to zero is loaded into the transmit FIFO.
+ [7] Zero Detect Interrupt - This bit determines whether the assertion of the CIT ZERO COUNT status bit (ICTSR[6)) causes an
+ interrupt to be generated if set to 1 and the Master interrupt control bit (ICR[0:1]) is set
+ [6] Zero Detect Control - his bit determines the action of the counter upon reaching zero count
+ 0 - The counter/timer is preset to the value contained in the counterltimer preset registers (CTPRL, CTPRH) at the next clock edge.
+ 1 - The counterltimer continues counting without preset. The value at the next clock edge will be H'FFFF'.
+ [5] CounterlTimer Output Control - This bit selects the output waveform when the counterltimer is selected to be output on TRxC or RTxC.
+ 0 - The output toggles each time the CIT reaches zero count. The output is cleared to Low by either of the preset counterltimer commands.
+ 1 - The output is a single clock positive width pulse each time the CIT reaches zero count. (The duration of this pulse is one clock period.)
+ [4:3] Clock Select - This field selects whether the clock selected by [2:0J is prescaled prior to being applied to the input of the CIT.
+ 0 0 No prescaling.
+ 0 1 Divide clock by 16.
+ 1 0 Divide clock by 32.
+ 1 1 Divide clock by 64.
+ [2:0] Clock Source - This field selects the clock source for the counterltimer.
+ 000 RTxC pin. Pin must be programmed as input.
+ 001 TRxC pin. Pin must be programmed as input.
+ 010 Source is the crystal oscillator or system clock input divided by four.
+ 011 This selects a special mode of operation. In this mode the counter, after receiving the 'start CIT' command, delays the
+ start of counting until the RxD input goes Low. It continues counting until the RxD input goes High, then stops and sets
+ the CIT zero count status bit. The CPU can use the value in the CIT to determine the bit rate of the incoming data.
+ The clock is the crystal oscillator or system clock input divided by four.
+ 100 Source is the 32X BRG output selected by RTR[3:0J of own channel.
+ 101 Source is the 32X BRG output selected by TTR[3:0J of own channel.
+ 110 Source is the internal signal which loads received characters from the receive shift register into the receiver
+ FIFO. When operating in this mode, the FIFOed EOM status bit (RSR[7)) shall be set when the character which
+ causes the count to go to zero is loaded into the receive FIFO.
+ 111 Source is the internal signal which transfers characters from the data bus into the transmit FIFO. When operating in this
+ mode, and if the TEOM on zero count or done control bit (TPR[4)) is asserted, the FIFOed send EOM command will
+ be automatically asserted when the character which causes the count to go to zero is loaded into the transmit FIFO.
*/
UINT8 duscc_channel::do_dusccreg_ctcr_r()
{
@@ -852,54 +850,54 @@ void duscc_channel::do_dusccreg_ctcr_w(UINT8 data)
}
/* Counterrrimer Preset High Register (CTPRHA, CTPRHB)
- [7:0) MSB - This register contains the eight most significant bits of the value loaded into the counter/timer upon receipt of the load CIT
- from preset regsiter command or when.the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated.
- The minimum 16-bit counter/timer preset value is H'0002'.
+ [7:0) MSB - This register contains the eight most significant bits of the value loaded into the counter/timer upon receipt of the load CIT
+ from preset regsiter command or when.the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated.
+ The minimum 16-bit counter/timer preset value is H'0002'.
*/
UINT8 duscc_channel::do_dusccreg_ctprh_r()
{
UINT8 ret = ((m_ctpr >> 8) & 0xff );
LOG(("%s(%02x)\n", FUNCNAME, ret));
- // return m_ctprh;
+ // return m_ctprh;
return ret;
}
void duscc_channel::do_dusccreg_ctprh_w(UINT8 data)
-{
+{
LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data));
- // m_ctprh = data;
+ // m_ctprh = data;
m_ctpr &= ~0x0000ff00;
m_ctpr |= ((data << 8) & 0x0000ff00);
- return;
+ return;
}
/* CounterfTimer Preset Low Register (CTPRLA, CTPRLB)
- [7:0) lSB - This register contains the eight least significant bits of the value loaded into the counter/timer upon receipt of the load CIT
- from preset register command or when the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated.
- The minimum 16-bit counter/timer preset value is H'0002'.
+ [7:0) lSB - This register contains the eight least significant bits of the value loaded into the counter/timer upon receipt of the load CIT
+ from preset register command or when the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated.
+ The minimum 16-bit counter/timer preset value is H'0002'.
*/
UINT8 duscc_channel::do_dusccreg_ctprl_r()
{
UINT8 ret = (m_ctpr & 0xff);
LOG(("%s(%02x)\n", FUNCNAME, ret));
- // return m_ctprl;
+ // return m_ctprl;
return ret;
}
void duscc_channel::do_dusccreg_ctprl_w(UINT8 data)
-{
+{
LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data));
- // m_ctprl = data;
+ // m_ctprl = data;
m_ctpr &= ~0x000000ff;
m_ctpr |= (data & 0x000000ff);
- return;
+ return;
}
/* Counter/Timer High Register (CTHA, CTHB) Read only
- [7:0] MSB - A read of this 'register' provides the eight most significant bits of the current value of the counter/timer. it is
- recommended that the CIT be stopped via a stop counter command before it is read in order to prevent errors which may occur due to
- the read being performed while the CIT is changing. This count may be continued after the register is read.
+ [7:0] MSB - A read of this 'register' provides the eight most significant bits of the current value of the counter/timer. it is
+ recommended that the CIT be stopped via a stop counter command before it is read in order to prevent errors which may occur due to
+ the read being performed while the CIT is changing. This count may be continued after the register is read.
*/
UINT8 duscc_channel::do_dusccreg_cth_r()
@@ -912,15 +910,15 @@ UINT8 duscc_channel::do_dusccreg_cth_r()
/* Counter/Timer Low Register (CTLA, CTLB) Read only
- [7:0] lSB - A read of this 'register' provides the eight least significant bits of the current value of the counter/timer. It is
- recommended that the CIT be stopped via a stop counter command before it is read, in order to prevent errors which may occur due to
- the read being performed while the CIT is changing. This count may be continued after the register is read.
+ [7:0] lSB - A read of this 'register' provides the eight least significant bits of the current value of the counter/timer. It is
+ recommended that the CIT be stopped via a stop counter command before it is read, in order to prevent errors which may occur due to
+ the read being performed while the CIT is changing. This count may be continued after the register is read.
*/
UINT8 duscc_channel::do_dusccreg_ctl_r()
{
UINT8 ret = (m_ct & 0xff);
LOG(("%s(%02x)\n", FUNCNAME, ret));
- // return m_ctl;
+ // return m_ctl;
return ret;
}
@@ -1134,31 +1132,31 @@ int duscc_channel::get_tx_word_length()
// register read methods - see correspondning write method for details on each register
UINT8 duscc_channel::do_dusccreg_cmr1_r()
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, m_cmr1));
- return m_cmr1;
+ return m_cmr1;
}
UINT8 duscc_channel::do_dusccreg_cmr2_r()
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, m_cmr2));
- return m_cmr2;
+ return m_cmr2;
}
UINT8 duscc_channel::do_dusccreg_s1r_r()
{
LOG(("%s(%02x)\n", FUNCNAME, m_s1r));
- return m_s1r;
+ return m_s1r;
}
UINT8 duscc_channel::do_dusccreg_s2r_r()
{
LOG(("%s(%02x)\n", FUNCNAME, m_s2r));
- return m_s2r;
+ return m_s2r;
}
UINT8 duscc_channel::do_dusccreg_tpr_r()
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, m_tpr));
return m_tpr;
}
@@ -1227,9 +1225,9 @@ UINT8 duscc_channel::do_dusccreg_rxfifo_r()
}
UINT8 duscc_channel::do_dusccreg_rsr_r()
-{
+{
LOG(("%s: %02x\n", FUNCNAME, m_rsr));
- return (UINT8) m_rsr;
+ return (UINT8) m_rsr;
}
UINT8 duscc_channel::do_dusccreg_trsr_r()
@@ -1239,9 +1237,9 @@ UINT8 duscc_channel::do_dusccreg_trsr_r()
}
UINT8 duscc_channel::do_dusccreg_ictsr_r()
-{
- logerror("%s is not implemented yet\n", FUNCNAME);
- return (UINT8) m_ictsr;
+{
+ logerror("%s is not implemented yet\n", FUNCNAME);
+ return (UINT8) m_ictsr;
}
/* General Status Register (GSR)
@@ -1266,15 +1264,15 @@ UINT8 duscc_channel::do_dusccreg_ictsr_r()
receiver' command is invoked.
*/
UINT8 duscc_channel::do_dusccreg_gsr_r()
-{
+{
LOGR(("%s <- %02x\n", FUNCNAME, m_uart->m_gsr));
- return (UINT8) m_uart->m_gsr;
+ return (UINT8) m_uart->m_gsr;
}
UINT8 duscc_channel::do_dusccreg_ier_r()
-{
+{
LOGR(("%s <- %02x\n", FUNCNAME, m_uart->m_ier));
- return (UINT8) 0;
+ return (UINT8) 0;
}
UINT8 duscc_channel::do_dusccreg_cid_r()
@@ -1310,7 +1308,7 @@ UINT8 duscc_channel::do_dusccreg_ivr_ivrm_r()
}
UINT8 duscc_channel::do_dusccreg_icr_r()
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, m_uart->m_icr));
return m_uart->m_icr;
}
@@ -1376,9 +1374,9 @@ UINT8 duscc_channel::do_dusccreg_telr_r()
primary function of these registers is to define configuration of the channels and the function of the programmable pins. A channel
cannot be dynamically reconfigured. Do not write to CMRI or CMR2 if the receiver or transmitter is enabled.
*/
-/* CMR1 register -
- [7:6] Data Encoding - These bits select the data encoding for the received and transmitted data:
- 00 If the DPLL is set to NRZI mode (see DPLL commands), it selects positive logic (1 = high, 0 = low).
+/* CMR1 register -
+ [7:6] Data Encoding - These bits select the data encoding for the received and transmitted data:
+ 00 If the DPLL is set to NRZI mode (see DPLL commands), it selects positive logic (1 = high, 0 = low).
If the DPLL is set to FM mode (see DPLL commands), Manchester (bi-phase level) encoding is selected.
01 NRZI. Non-return-to-zero inverted.
10 FMO. Bi-phase space.
@@ -1514,7 +1512,7 @@ void duscc_channel::do_dusccreg_cmr2_w(UINT8 data)
}
/* SYN1/Secondary Address 1 Register (S1RA, S1RB)
- [7:O} Character Compare
+ [7:O} Character Compare
- In ASYNC mode this register holds a 5 to 8-bit long bit pattern which is ocmpared with received
characters. if a match occurs, the character compare status bit (RSR[7]) is set. This field is ignored if the receivEII is in a break
condition.
@@ -1526,10 +1524,10 @@ void duscc_channel::do_dusccreg_cmr2_w(UINT8 data)
TODO: Add check in receive_data and set status bits accordingly
*/
void duscc_channel::do_dusccreg_s1r_w(UINT8 data)
-{
+{
LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data));
m_s1r = data;
- return;
+ return;
}
/* SYN2ISecondary Address 2 Register (S2RA, S2RB)
@@ -1540,10 +1538,10 @@ void duscc_channel::do_dusccreg_s1r_w(UINT8 data)
match. If parity Is specified, then any unused bits in this register must be programmed to zeros. In BOP secondary mode using two
address octets, it contains the partial address used to compare the second received address octet.*/
void duscc_channel::do_dusccreg_s2r_w(UINT8 data)
-{
+{
LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data));
m_s2r = data;
- return;
+ return;
}
/* Transmitter Parameter Register (TPRA, TPRB)
@@ -1907,7 +1905,7 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
default: LOG(("Wrong programming\n")); break; // Should never happen
}
- return;
+ return;
}
/*
@@ -1941,7 +1939,7 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
/* Enable transmitter. Enables transmitter operation, conditioned by the state of
the CTS ENABLE Tx bit, TPR[2]. Has no effect if invoked when the transmitter has
previously been enabled.*/
- case REG_CCR_ENABLE_TX: LOG(("- Enable Tx\n"));
+ case REG_CCR_ENABLE_TX: LOG(("- Enable Tx\n"));
m_uart->m_gsr |= (m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_TXREADY : REG_GSR_CHAN_B_TXREADY);
m_tra = 1;
set_tra_rate(m_brg_tx_rate);
@@ -1995,7 +1993,7 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
duscc_timer->adjust(attotime::from_hz(rate), TIMER_ID_RTXC, attotime::from_hz(rate));
break;
- /* Stop. Stops the counter/timer and prescaler. Since the command may be asynchronous with the selected clock source,
+ /* Stop. Stops the counter/timer and prescaler. Since the command may be asynchronous with the selected clock source,
the counter/timer and/or prescaler may count one or more additional cycles before stopping.. */
case REG_CCR_STOP_TIMER: LOG(("- Stop Counter/Timer\n"));
duscc_timer->adjust(attotime::never);
@@ -2073,21 +2071,21 @@ void duscc_channel::do_dusccreg_txfifo_w(UINT8 data)
before reading the character data from RxFIFO. For block status, the status register is initially cleared and then read after the
message is received. Asserted status bits can be programmed to generate an interrupt (see Interrupt Enable Register).*/
void duscc_channel::do_dusccreg_rsr_w(UINT8 data)
-{
+{
LOG(("%s: %02x\n", FUNCNAME, data));
m_rsr &= ~data; // Clear only bits which are 1:s
- return;
+ return;
}
void duscc_channel::do_dusccreg_trsr_w(UINT8 data)
-{
+{
LOG(("%s: %02x - not supported yet\n", FUNCNAME, data));
m_trsr = data;
return;
}
void duscc_channel::do_dusccreg_ictsr_w(UINT8 data)
-{
+{
LOG(("%s: %02x - not supported yet\n", FUNCNAME, data));
m_ictsr = data;
return;
@@ -2095,57 +2093,57 @@ void duscc_channel::do_dusccreg_ictsr_w(UINT8 data)
/* This register provides a 'quick look' at the overall status of both channels of the DUSCC. A write to this register with ls at the
corresponding bit pOSitions causes TxRDY (bits 5 and 1) and/or RxRDY (bits 4 and 0) to be reset. The other status bits can be reset
- only by resetting the individual status bits that they point to.
+ only by resetting the individual status bits that they point to.
[7] Channel 8 External or Coutnerrrimer Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4].
[6] Channel B Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: RSRB[7:0], TRSRB[7:3].
- [5] Channel 8 Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B
+ [5] Channel 8 Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B
transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4j. This bit can be asserted only
- when the transmitter is enabled. Reselling the transmitter negates TxRDY.
+ when the transmitter is enabled. Reselling the transmitter negates TxRDY.
[4] Channel 8 Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel B receiver
FIFO to be read by the CPU. See deSCription of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel B
- receiver' command is invoked.
+ receiver' command is invoked.
[3] Channel A External or Countermmer Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
[2] Channel A Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: RSRA(7:0], TRSRA(7:3].
- [1) Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
+ [1) Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4]. This bit can be asserted only
when the transmitter is enabled. Resetting the transmitter negates TxRDY.
[0) Channel A Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel A receiver
FIFO to be read by the CPU. See description of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel A
- receiver' command is invoked.*/
+ receiver' command is invoked.*/
void duscc_channel::do_dusccreg_gsr_w(UINT8 data)
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, data));
m_uart->m_gsr &= (data & REG_GSR_XXREADY_MASK); // Reset only XXREADY bits, the rest needs to be reset by the source
- return; // TODO: Check of the XXREADY source bits should be reset too
+ return; // TODO: Check of the XXREADY source bits should be reset too
}
/* Interrupt Enable Register (IERA, IERB)
This register controls whether the assertion of bits in the channel's status registers causes an interrupt to be generated. An additional
condition for an interrupt to be generated is that the channel's master interrupt enabled bit, ICR[O] or ICR[1], be asserted.*/
void duscc_channel::do_dusccreg_ier_w(UINT8 data)
-{
+{
m_ier = data;
LOG(("%s(%02x)\n", FUNCNAME, data));
m_uart->check_interrupts();
- return;
+ return;
}
void duscc_channel::do_dusccreg_ivr_w(UINT8 data)
-{
+{
m_uart->m_ivr = data;
LOG(("%s(%02x)\n", FUNCNAME, data));
return;
}
void duscc_channel::do_dusccreg_icr_w(UINT8 data)
-{
+{
m_uart->m_icr = data;
LOG(("%s(%02x)\n", FUNCNAME, data));
return;
}
void duscc_channel::do_dusccreg_sea_rea_w(UINT8 data)
-{
+{
LOG(("%s(%02x)\n", FUNCNAME, data));
if ( m_uart->m_variant != SET_CMOS )
{
@@ -2157,7 +2155,7 @@ void duscc_channel::do_dusccreg_sea_rea_w(UINT8 data)
m_a7 = (m_index == duscc_device::CHANNEL_A ? 0x40 : 0); // Set or Reset depending in channel
}
- return;
+ return;
}
void duscc_channel::do_dusccreg_mrr_w(UINT8 data){ logerror("%s is not implemented yet\n", FUNCNAME); return; }
@@ -2178,36 +2176,36 @@ UINT8 duscc_channel::read(offs_t &offset)
switch (reg)
{
- case REG_CMR1: data = do_dusccreg_cmr1_r(); break;
- case REG_CMR2: data = do_dusccreg_cmr2_r(); break;
- case REG_S1R: data = do_dusccreg_s1r_r(); break;
- case REG_S2R: data = do_dusccreg_s2r_r(); break;
- case REG_TPR: data = do_dusccreg_tpr_r(); break;
- case REG_TTR: data = do_dusccreg_ttr_r(); break;
- case REG_RPR: data = do_dusccreg_rpr_r(); break;
- case REG_RTR: data = do_dusccreg_rtr_r(); break;
- case REG_CTPRH: data = do_dusccreg_ctprh_r(); break;
- case REG_CTPRL: data = do_dusccreg_ctprl_r(); break;
- case REG_CTCR: data = do_dusccreg_ctcr_r(); break;
- case REG_OMR: data = do_dusccreg_omr_r(); break;
- case REG_CTH: data = do_dusccreg_cth_r(); break;
- case REG_CTL: data = do_dusccreg_ctl_r(); break;
- case REG_PCR: data = do_dusccreg_pcr_r(); break;
- case REG_CCR: data = do_dusccreg_ccr_r(); break;
- case REG_RXFIFO_0: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_1: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_2: data = do_dusccreg_rxfifo_r(); break;
- case REG_RXFIFO_3: data = do_dusccreg_rxfifo_r(); break;
- case REG_RSR: data = do_dusccreg_rsr_r(); break;
- case REG_TRSR: data = do_dusccreg_trsr_r(); break;
- case REG_ICTSR: data = do_dusccreg_ictsr_r(); break;
- case REG_GSR: data = do_dusccreg_gsr_r(); break;
- case REG_IER: data = do_dusccreg_ier_r(); break;
- // case REG_IVR: data = do_dusccreg_ivr_r(); break; // Chan A = IVR, B = IVRM
- case REG_IVRM: data = do_dusccreg_ivr_ivrm_r(); break;
- case REG_ICR: data = do_dusccreg_icr_r(); break;
+ case REG_CMR1: data = do_dusccreg_cmr1_r(); break;
+ case REG_CMR2: data = do_dusccreg_cmr2_r(); break;
+ case REG_S1R: data = do_dusccreg_s1r_r(); break;
+ case REG_S2R: data = do_dusccreg_s2r_r(); break;
+ case REG_TPR: data = do_dusccreg_tpr_r(); break;
+ case REG_TTR: data = do_dusccreg_ttr_r(); break;
+ case REG_RPR: data = do_dusccreg_rpr_r(); break;
+ case REG_RTR: data = do_dusccreg_rtr_r(); break;
+ case REG_CTPRH: data = do_dusccreg_ctprh_r(); break;
+ case REG_CTPRL: data = do_dusccreg_ctprl_r(); break;
+ case REG_CTCR: data = do_dusccreg_ctcr_r(); break;
+ case REG_OMR: data = do_dusccreg_omr_r(); break;
+ case REG_CTH: data = do_dusccreg_cth_r(); break;
+ case REG_CTL: data = do_dusccreg_ctl_r(); break;
+ case REG_PCR: data = do_dusccreg_pcr_r(); break;
+ case REG_CCR: data = do_dusccreg_ccr_r(); break;
+ case REG_RXFIFO_0: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_1: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_2: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RXFIFO_3: data = do_dusccreg_rxfifo_r(); break;
+ case REG_RSR: data = do_dusccreg_rsr_r(); break;
+ case REG_TRSR: data = do_dusccreg_trsr_r(); break;
+ case REG_ICTSR: data = do_dusccreg_ictsr_r(); break;
+ case REG_GSR: data = do_dusccreg_gsr_r(); break;
+ case REG_IER: data = do_dusccreg_ier_r(); break;
+ // case REG_IVR: data = do_dusccreg_ivr_r(); break; // Chan A = IVR, B = IVRM
+ case REG_IVRM: data = do_dusccreg_ivr_ivrm_r(); break;
+ case REG_ICR: data = do_dusccreg_icr_r(); break;
// CDUSCC Extended registers - requires A7 to be set through REG_SEA
- case REG_CID: data = do_dusccreg_cid_r(); break;
+ case REG_CID: data = do_dusccreg_cid_r(); break;
default:
logerror(" \"%s\" %s: %c : Unsupported RRx register:%02x\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg);
}
@@ -2228,44 +2226,44 @@ void duscc_channel::write(UINT8 data, offs_t &offset)
LOG(("\"%s\" %s: %c : Register write '%02x' -> [%02x]", m_owner->tag(), FUNCNAME, 'A' + m_index, data, reg ));
switch (reg)
{
- case REG_CMR1: do_dusccreg_cmr1_w(data); break;
- case REG_CMR2: do_dusccreg_cmr2_w(data); break;
- case REG_S1R: do_dusccreg_s1r_w(data); break;
- case REG_S2R: do_dusccreg_s2r_w(data); break;
- case REG_TPR: do_dusccreg_tpr_w(data); break;
- case REG_TTR: do_dusccreg_ttr_w(data); break;
- case REG_RPR: do_dusccreg_rpr_w(data); break;
- case REG_RTR: do_dusccreg_rtr_w(data); break;
- case REG_CTPRH: do_dusccreg_ctprh_w(data); break;
- case REG_CTPRL: do_dusccreg_ctprl_w(data); break;
- case REG_CTCR: do_dusccreg_ctcr_w(data); break;
- case REG_OMR: do_dusccreg_omr_w(data); break;
-// case REG_CTH: LOG(("REG_CTH \n")); break; // Read only register
-// case REG_CTL: LOG(("REG_CTL \n")); break; // Read only register
- case REG_PCR: do_dusccreg_pcr_w(data); break;
- case REG_CCR: do_dusccreg_ccr_w(data); break;
- case REG_TXFIFO_0: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_1: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_2: do_dusccreg_txfifo_w(data); break;
- case REG_TXFIFO_3: do_dusccreg_txfifo_w(data); break;
- case REG_RSR: do_dusccreg_rsr_w(data); break;
- case REG_TRSR: do_dusccreg_trsr_w(data); break;
- case REG_ICTSR: do_dusccreg_ictsr_w(data); break;
- case REG_GSR: do_dusccreg_gsr_w(data); break;
- case REG_IER: do_dusccreg_ier_w(data); break;
- case REG_IVR: do_dusccreg_ivr_w(data); break;
- case REG_ICR: do_dusccreg_icr_w(data); break;
+ case REG_CMR1: do_dusccreg_cmr1_w(data); break;
+ case REG_CMR2: do_dusccreg_cmr2_w(data); break;
+ case REG_S1R: do_dusccreg_s1r_w(data); break;
+ case REG_S2R: do_dusccreg_s2r_w(data); break;
+ case REG_TPR: do_dusccreg_tpr_w(data); break;
+ case REG_TTR: do_dusccreg_ttr_w(data); break;
+ case REG_RPR: do_dusccreg_rpr_w(data); break;
+ case REG_RTR: do_dusccreg_rtr_w(data); break;
+ case REG_CTPRH: do_dusccreg_ctprh_w(data); break;
+ case REG_CTPRL: do_dusccreg_ctprl_w(data); break;
+ case REG_CTCR: do_dusccreg_ctcr_w(data); break;
+ case REG_OMR: do_dusccreg_omr_w(data); break;
+// case REG_CTH: LOG(("REG_CTH \n")); break; // Read only register
+// case REG_CTL: LOG(("REG_CTL \n")); break; // Read only register
+ case REG_PCR: do_dusccreg_pcr_w(data); break;
+ case REG_CCR: do_dusccreg_ccr_w(data); break;
+ case REG_TXFIFO_0: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_1: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_2: do_dusccreg_txfifo_w(data); break;
+ case REG_TXFIFO_3: do_dusccreg_txfifo_w(data); break;
+ case REG_RSR: do_dusccreg_rsr_w(data); break;
+ case REG_TRSR: do_dusccreg_trsr_w(data); break;
+ case REG_ICTSR: do_dusccreg_ictsr_w(data); break;
+ case REG_GSR: do_dusccreg_gsr_w(data); break;
+ case REG_IER: do_dusccreg_ier_w(data); break;
+ case REG_IVR: do_dusccreg_ivr_w(data); break;
+ case REG_ICR: do_dusccreg_icr_w(data); break;
// CDUSCC Extended registers - requires A7 to be set through REG_SEA
-// case REG_MRR: LOG(("REG_MRR \n")); break;
- case REG_SEA: do_dusccreg_sea_rea_w(data); break; /* Also supports REG_REA depending on which channel is written to */
- case REG_IER1: LOG(("REG_IER1\n")); break;
- case REG_IER2: LOG(("REG_IER2\n")); break;
- case REG_IER3: LOG(("REG_IER3\n")); break;
- case REG_TRCR: LOG(("REG_TRCR\n")); break;
- case REG_RFLR: LOG(("REG_RFLR\n")); break;
- case REG_FTLR: LOG(("REG_FTLR\n")); break;
- case REG_TRMSR: LOG(("REG_TRMSR\n")); break;
- case REG_TELR: LOG(("REG_TELR\n")); break;
+// case REG_MRR: LOG(("REG_MRR \n")); break;
+ case REG_SEA: do_dusccreg_sea_rea_w(data); break; /* Also supports REG_REA depending on which channel is written to */
+ case REG_IER1: LOG(("REG_IER1\n")); break;
+ case REG_IER2: LOG(("REG_IER2\n")); break;
+ case REG_IER3: LOG(("REG_IER3\n")); break;
+ case REG_TRCR: LOG(("REG_TRCR\n")); break;
+ case REG_RFLR: LOG(("REG_RFLR\n")); break;
+ case REG_FTLR: LOG(("REG_FTLR\n")); break;
+ case REG_TRMSR: LOG(("REG_TRMSR\n")); break;
+ case REG_TELR: LOG(("REG_TELR\n")); break;
default:
logerror(" \"%s\" %s: %c : Unsupported WRx register:%02x(%02x)\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg, data);
@@ -2323,7 +2321,7 @@ void duscc_channel::receive_data(UINT8 data)
{
// receive overrun error detected
m_rsr |= REG_RSR_OVERRUN_ERROR;
- // m_rx_error_fifo[m_rx_fifo_wp] &= ~REG_RSR_OVERRUN_ERROR; // The overrun error is NOT fifoed obviously...
+ // m_rx_error_fifo[m_rx_fifo_wp] &= ~REG_RSR_OVERRUN_ERROR; // The overrun error is NOT fifoed obviously...
logerror("Receive_data() Error %02x\n", m_rsr);
}
else
@@ -2338,7 +2336,7 @@ void duscc_channel::receive_data(UINT8 data)
m_rx_fifo_wp = 0;
}
- // if (m_eir & REG_IER_)
+ // if (m_eir & REG_IER_)
}
}
diff --git a/src/devices/machine/scnxx562.h b/src/devices/machine/scnxx562.h
index ee07df1b124..5365f5f70ac 100644
--- a/src/devices/machine/scnxx562.h
+++ b/src/devices/machine/scnxx562.h
@@ -241,13 +241,13 @@ public:
UINT8 m_ttr;
UINT8 m_rpr;
UINT8 m_rtr;
- // UINT8 m_ctprh;
- // UINT8 m_ctprl;
+ // UINT8 m_ctprh;
+ // UINT8 m_ctprl;
unsigned int m_ctpr;
UINT8 m_ctcr;
UINT8 m_omr;
- // UINT8 m_cth;
- // UINT8 m_ctl;
+ // UINT8 m_cth;
+ // UINT8 m_ctl;
unsigned int m_ct;
UINT8 m_pcr;
UINT8 m_ccr;
@@ -256,13 +256,13 @@ public:
UINT8 m_rsr;
UINT8 m_trsr;
UINT8 m_ictsr;
- // UINT8 m_gsr; // moved to the device since it is global
+ // UINT8 m_gsr; // moved to the device since it is global
UINT8 m_ier;
// UINT8 m_rea;
UINT8 m_cid;
//UINT8 m_ivr;
//UINT8 m_icr;
- // UINT8 m_sea;
+ // UINT8 m_sea;
//UINT8 m_ivrm;
UINT8 m_mrr;
UINT8 m_ier1;
@@ -275,12 +275,12 @@ public:
UINT8 m_telr;
protected:
- enum // Needs to be 0-3 in unmodified prio level
+ enum // Needs to be 0-3 in unmodified prio level
{
- INT_RXREADY = 0,
- INT_TXREADY = 1,
- INT_RXTXSTAT = 2,
- INT_EXTCTSTAT = 3
+ INT_RXREADY = 0,
+ INT_TXREADY = 1,
+ INT_RXTXSTAT = 2,
+ INT_EXTCTSTAT = 3
};
enum
@@ -292,9 +292,9 @@ protected:
REG_CCR_ENABLE_RX = 0x42,
REG_CCR_DISABLE_RX = 0x43,
REG_CCR_START_TIMER = 0x80,
- REG_CCR_STOP_TIMER = 0x81,
- REG_CCR_PRST_FFFF = 0x82,
- REG_CCR_PRST_CTPR = 0x83,
+ REG_CCR_STOP_TIMER = 0x81,
+ REG_CCR_PRST_FFFF = 0x82,
+ REG_CCR_PRST_CTPR = 0x83,
};
enum
@@ -403,24 +403,24 @@ protected:
enum
{
- REG_RSR_CHAR_COMPARE = 0x80,
- REG_RSR_OVERRUN_ERROR = 0x20,
- REG_RSR_FRAMING_ERROR = 0x02,
- REG_RSR_PARITY_ERROR = 0x01,
+ REG_RSR_CHAR_COMPARE = 0x80,
+ REG_RSR_OVERRUN_ERROR = 0x20,
+ REG_RSR_FRAMING_ERROR = 0x02,
+ REG_RSR_PARITY_ERROR = 0x01,
};
enum
{
- REG_GSR_CHAN_A_RXREADY = 0x01,
- REG_GSR_CHAN_B_RXREADY = 0x10,
- REG_GSR_CHAN_A_TXREADY = 0x02,
- REG_GSR_CHAN_B_TXREADY = 0x20,
- REG_GSR_XXREADY_MASK = 0x33
+ REG_GSR_CHAN_A_RXREADY = 0x01,
+ REG_GSR_CHAN_B_RXREADY = 0x10,
+ REG_GSR_CHAN_A_TXREADY = 0x02,
+ REG_GSR_CHAN_B_TXREADY = 0x20,
+ REG_GSR_XXREADY_MASK = 0x33
};
enum
{
- REG_ICTSR_ZERO_DET = 0x40,
+ REG_ICTSR_ZERO_DET = 0x40,
REG_ICTSR_DELTA_CTS = 0x10,
REG_ICTSR_DCD = 0x08,
REG_ICTSR_CTS = 0x04,
@@ -428,14 +428,14 @@ protected:
enum
{
- REG_IER_DCD_CTS = 0x80,
- REG_IER_TXRDY = 0x40,
- REG_IER_TRSR73 = 0x20,
- REG_IER_RXRDY = 0x10,
- REG_IER_RSR76 = 0x08,
- REG_IER_RSR54 = 0x04,
- REG_IER_RSR32 = 0x02,
- REG_IER_RSR10 = 0x01,
+ REG_IER_DCD_CTS = 0x80,
+ REG_IER_TXRDY = 0x40,
+ REG_IER_TRSR73 = 0x20,
+ REG_IER_RXRDY = 0x10,
+ REG_IER_RSR76 = 0x08,
+ REG_IER_RSR54 = 0x04,
+ REG_IER_RSR32 = 0x02,
+ REG_IER_RSR10 = 0x01,
};
// Register offsets, stripped from channel bit 0x20 but including A7 bit
@@ -494,13 +494,13 @@ protected:
UINT8 m_rtxc;
UINT8 m_trxc;
-
+
enum
{
- REG_CTCR_ZERO_DET_INT = 0x80,
- REG_CTCR_ZERO_DET_CTL = 0x40,
- REG_CTCR_TIM_OC = 0x20,
+ REG_CTCR_ZERO_DET_INT = 0x80,
+ REG_CTCR_ZERO_DET_CTL = 0x40,
+ REG_CTCR_TIM_OC = 0x20,
};
enum
@@ -731,15 +731,15 @@ protected:
enum
{
- REG_ICR_CHB = 0x01,
- REG_ICR_CHA = 0x02,
- REG_ICR_VEC_MOD = 0x04,
- REG_ICR_V2V4_MOD = 0x08,
- REG_ICR_PRIO_MASK = 0xC0,
- REG_ICR_PRIO_AHI = 0x00,
- REG_ICR_PRIO_BHI = 0x40,
- REG_ICR_PRIO_AINT = 0x80,
- REG_ICR_PRIO_BINT = 0xC0,
+ REG_ICR_CHB = 0x01,
+ REG_ICR_CHA = 0x02,
+ REG_ICR_VEC_MOD = 0x04,
+ REG_ICR_V2V4_MOD = 0x08,
+ REG_ICR_PRIO_MASK = 0xC0,
+ REG_ICR_PRIO_AHI = 0x00,
+ REG_ICR_PRIO_BHI = 0x40,
+ REG_ICR_PRIO_AINT = 0x80,
+ REG_ICR_PRIO_BINT = 0xC0,
};
};
diff --git a/src/devices/machine/z80scc.cpp b/src/devices/machine/z80scc.cpp
index 5e1e7f984f9..04a197d0e1a 100644
--- a/src/devices/machine/z80scc.cpp
+++ b/src/devices/machine/z80scc.cpp
@@ -79,7 +79,7 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
// printf("TAG %lld %s%s Data:%d\n", machine().firstcpu->total_cycles(), __PRETTY_FUNCTION__, m_owner->tag(), data);
#define VERBOSE 0
-#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
+#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
#define LOG(x) LOGPRINT(x)
#define LOGR(x)
#define LOGSETUP(x) LOGPRINT(x)
@@ -1602,7 +1602,7 @@ void z80scc_channel::do_sccreg_wr4(UINT8 data)
if (data == m_wr4)
{
logerror("- supressing reinit of Tx as write to wr4 is identical to previous value\n");
- }
+ }
else
{
m_wr4 = data;
@@ -1622,7 +1622,7 @@ void z80scc_channel::do_sccreg_wr5(UINT8 data)
if (data == m_wr5)
{
logerror("- supressing reinit of Tx as write to wr5 is identical to previous value\n");
- }
+ }
else
{
m_wr5 = data;
@@ -1962,22 +1962,22 @@ void z80scc_channel::control_write(UINT8 data)
/* TODO. Sort out 80X30 & other SCC variants limitations in register access */
switch (reg)
{
- case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); break;
- case REG_WR1_INT_DMA_ENABLE: do_sccreg_wr1(data); m_uart->check_interrupts(); break;
- case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break;
- case REG_WR3_RX_CONTROL: do_sccreg_wr3(data); break;
- case REG_WR4_RX_TX_MODES: do_sccreg_wr4(data); break;
- case REG_WR5_TX_CONTROL: do_sccreg_wr5(data); break;
- case REG_WR6_SYNC_OR_SDLC_A: do_sccreg_wr6(data); break;
- case REG_WR7_SYNC_OR_SDLC_F: do_sccreg_wr7(data); break;
- case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break;
- case REG_WR9_MASTER_INT_CTRL: do_sccreg_wr9(data); break;
- case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break;
- case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break;
- case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break;
- case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break;
- case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break;
- case REG_WR15_EXT_ST_INT_CTRL: do_sccreg_wr15(data); break;
+ case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); break;
+ case REG_WR1_INT_DMA_ENABLE: do_sccreg_wr1(data); m_uart->check_interrupts(); break;
+ case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break;
+ case REG_WR3_RX_CONTROL: do_sccreg_wr3(data); break;
+ case REG_WR4_RX_TX_MODES: do_sccreg_wr4(data); break;
+ case REG_WR5_TX_CONTROL: do_sccreg_wr5(data); break;
+ case REG_WR6_SYNC_OR_SDLC_A: do_sccreg_wr6(data); break;
+ case REG_WR7_SYNC_OR_SDLC_F: do_sccreg_wr7(data); break;
+ case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break;
+ case REG_WR9_MASTER_INT_CTRL: do_sccreg_wr9(data); break;
+ case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break;
+ case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break;
+ case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break;
+ case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break;
+ case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break;
+ case REG_WR15_EXT_ST_INT_CTRL: do_sccreg_wr15(data); break;
default:
logerror("\"%s\": %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
}
@@ -2361,14 +2361,14 @@ WRITE_LINE_MEMBER( z80scc_channel::txc_w )
}
//--------------------------------------------------------------------------------------------------------
-// safe_transmit_register_reset - wait for the transmitter shift register to be
-// emptied before apply the new value of wr5 and/or wr4. In the case of a Tx FIFO
+// safe_transmit_register_reset - wait for the transmitter shift register to be
+// emptied before apply the new value of wr5 and/or wr4. In the case of a Tx FIFO
// the change will occur before next character is started. From the specification:
//
// "The character length may be changed on the fly, but the desired length must be selected before the
// character is loaded into the Transmit Shift register from the transmit data FIFO. The easiest way to
// ensure this is to write to WR5 to change the character length before writing the data to the transmit
-// buffer."
+// buffer."
//
// Right now we only detect the problem and log an error
//---------------------------------------------------------------------------------------------------------
@@ -2424,11 +2424,11 @@ void z80scc_channel::update_serial()
if (m_brg_rate != 0 || m_wr14 & WR14_BRG_ENABLE)
{
- if (m_brg_rate == 1)
+ if (m_brg_rate == 1)
{
m_brg_rate = 0; // BRG beeing disabled
}
- else // or enabled
+ else // or enabled
{
m_brg_const = 2 + (m_wr13 << 8 | m_wr12);
int rate = m_owner->clock() / (m_brg_const == 0 ? 1 : m_brg_const);