diff options
author | Vas Crabb <vas@vastheman.com> | 2020-12-27 05:35:56 +1100 |
---|---|---|
committer | Vas Crabb <vas@vastheman.com> | 2020-12-27 05:35:56 +1100 |
commit | 43f569e58f26d23032b950ebcbd02f352532ba95 (patch) | |
tree | 6dfcb34f89f539c2a5d177e9970debf841189727 /src/devices/machine | |
parent | a5e6f4ea8d468f8f8e50ad5199a9f8aa9a81e9f1 (diff) |
srcclean for 0.227
Diffstat (limited to 'src/devices/machine')
-rw-r--r-- | src/devices/machine/f4702.cpp | 2 | ||||
-rw-r--r-- | src/devices/machine/ie15.cpp | 4 | ||||
-rw-r--r-- | src/devices/machine/locomo.cpp | 6 | ||||
-rw-r--r-- | src/devices/machine/locomo.h | 2 | ||||
-rw-r--r-- | src/devices/machine/sa1110.cpp | 18 | ||||
-rw-r--r-- | src/devices/machine/sa1110.h | 338 | ||||
-rw-r--r-- | src/devices/machine/sa1111.cpp | 24 | ||||
-rw-r--r-- | src/devices/machine/sa1111.h | 486 | ||||
-rw-r--r-- | src/devices/machine/scoop.cpp | 6 | ||||
-rw-r--r-- | src/devices/machine/scoop.h | 2 | ||||
-rw-r--r-- | src/devices/machine/ucb1200.cpp | 6 | ||||
-rw-r--r-- | src/devices/machine/ucb1200.h | 152 |
12 files changed, 523 insertions, 523 deletions
diff --git a/src/devices/machine/f4702.cpp b/src/devices/machine/f4702.cpp index 40a1d0be517..2a6bf7218c8 100644 --- a/src/devices/machine/f4702.cpp +++ b/src/devices/machine/f4702.cpp @@ -4,7 +4,7 @@ Fairchild 4702B Programmable Bit Rate Generator - Originally numbered 34702 in Fairchild's isoplanar CMOS series (whose + Originally numbered 34702 in Fairchild's isoplanar CMOS series (whose lower-numbered products were logical equivalents of RCA CD4000 and Motorola MC14500 series devices), this BRG incorporates some unusually sophisticated features into its 16-pin package, which may be why diff --git a/src/devices/machine/ie15.cpp b/src/devices/machine/ie15.cpp index 1555e1cb645..4d9d17a3afc 100644 --- a/src/devices/machine/ie15.cpp +++ b/src/devices/machine/ie15.cpp @@ -616,8 +616,8 @@ void ie15_device::update_leds() /* VBlank is active for 3 topmost on-screen rows and 1 at the bottom. - However, control flag 3 overrides VBlank, allowing status line - to be switched on and off. + However, control flag 3 overrides VBlank, allowing status line + to be switched on and off. */ void ie15_device::scanline_callback() { diff --git a/src/devices/machine/locomo.cpp b/src/devices/machine/locomo.cpp index 4eb6c54008d..01cae8787ce 100644 --- a/src/devices/machine/locomo.cpp +++ b/src/devices/machine/locomo.cpp @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Sharp LoCoMo peripheral chip emulation skeleton + Sharp LoCoMo peripheral chip emulation skeleton ***************************************************************************/ @@ -10,8 +10,8 @@ #include "locomo.h" #define LOG_UNKNOWN (1 << 1) -#define LOG_READS (1 << 2) -#define LOG_WRITES (1 << 3) +#define LOG_READS (1 << 2) +#define LOG_WRITES (1 << 3) #define LOG_ALL (LOG_UNKNOWN | LOG_READS | LOG_WRITES) #define VERBOSE (LOG_ALL) diff --git a/src/devices/machine/locomo.h b/src/devices/machine/locomo.h index 7f870b8f778..ac240959d9f 100644 --- a/src/devices/machine/locomo.h +++ b/src/devices/machine/locomo.h @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Sharp LoCoMo peripheral chip emulation skeleton + Sharp LoCoMo peripheral chip emulation skeleton ***************************************************************************/ diff --git a/src/devices/machine/sa1110.cpp b/src/devices/machine/sa1110.cpp index 7d13102c86a..8b9047dcc48 100644 --- a/src/devices/machine/sa1110.cpp +++ b/src/devices/machine/sa1110.cpp @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Intel XScale SA1110 peripheral emulation + Intel XScale SA1110 peripheral emulation ***************************************************************************/ @@ -11,16 +11,16 @@ #define LOG_UNKNOWN (1 << 1) #define LOG_UART (1 << 2) -#define LOG_UART_HF (1 << 3) -#define LOG_MCP (1 << 4) -#define LOG_SSP (1 << 5) -#define LOG_OSTIMER (1 << 6) -#define LOG_OSTIMER_HF (1 << 7) -#define LOG_RTC (1 << 8) +#define LOG_UART_HF (1 << 3) +#define LOG_MCP (1 << 4) +#define LOG_SSP (1 << 5) +#define LOG_OSTIMER (1 << 6) +#define LOG_OSTIMER_HF (1 << 7) +#define LOG_RTC (1 << 8) #define LOG_POWER (1 << 9) #define LOG_RESET (1 << 10) -#define LOG_GPIO (1 << 11) -#define LOG_GPIO_HF (1 << 12) +#define LOG_GPIO (1 << 11) +#define LOG_GPIO_HF (1 << 12) #define LOG_INTC (1 << 13) #define LOG_ALL (LOG_UNKNOWN | LOG_UART | LOG_MCP | LOG_SSP | LOG_OSTIMER | LOG_RTC | LOG_POWER | LOG_RESET | LOG_GPIO | LOG_INTC) diff --git a/src/devices/machine/sa1110.h b/src/devices/machine/sa1110.h index 167d7f47862..3069e7006ab 100644 --- a/src/devices/machine/sa1110.h +++ b/src/devices/machine/sa1110.h @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Intel XScale SA1110 peripheral emulation + Intel XScale SA1110 peripheral emulation ***************************************************************************/ @@ -137,20 +137,20 @@ protected: REG_UTSR0 = (0x0000001c >> 2), REG_UTSR1 = (0x00000020 >> 2), - MCP_BASE_ADDR = 0x80060000, + MCP_BASE_ADDR = 0x80060000, REG_MCCR0 = (0x00000000 >> 2), REG_MCDR0 = (0x00000008 >> 2), REG_MCDR1 = (0x0000000c >> 2), REG_MCDR2 = (0x00000010 >> 2), REG_MCSR = (0x00000018 >> 2), - SSP_BASE_ADDR = 0x80070000, - REG_SSCR0 = (0x00000060 >> 2), - REG_SSCR1 = (0x00000064 >> 2), - REG_SSDR = (0x0000006c >> 2), - REG_SSSR = (0x00000074 >> 2), + SSP_BASE_ADDR = 0x80070000, + REG_SSCR0 = (0x00000060 >> 2), + REG_SSCR1 = (0x00000064 >> 2), + REG_SSDR = (0x0000006c >> 2), + REG_SSSR = (0x00000074 >> 2), - OSTMR_BASE_ADDR = 0x90000000, + OSTMR_BASE_ADDR = 0x90000000, REG_OSMR0 = (0x00000000 >> 2), REG_OSMR1 = (0x00000004 >> 2), REG_OSMR2 = (0x00000008 >> 2), @@ -160,7 +160,7 @@ protected: REG_OWER = (0x00000018 >> 2), REG_OIER = (0x0000001c >> 2), - RTC_BASE_ADDR = 0x90010000, + RTC_BASE_ADDR = 0x90010000, REG_RTAR = (0x00000000 >> 2), REG_RCNR = (0x00000004 >> 2), REG_RTTR = (0x00000008 >> 2), @@ -176,19 +176,19 @@ protected: REG_PGSR = (0x00000018 >> 2), REG_POSR = (0x0000001c >> 2), - RESET_BASE_ADDR = 0x90030000, - REG_RSRR = (0x00000000 >> 2), - REG_RCSR = (0x00000004 >> 2), + RESET_BASE_ADDR = 0x90030000, + REG_RSRR = (0x00000000 >> 2), + REG_RCSR = (0x00000004 >> 2), - GPIO_BASE_ADDR = 0x90040000, - REG_GPLR = (0x00000000 >> 2), - REG_GPDR = (0x00000004 >> 2), - REG_GPSR = (0x00000008 >> 2), - REG_GPCR = (0x0000000c >> 2), - REG_GRER = (0x00000010 >> 2), - REG_GFER = (0x00000014 >> 2), - REG_GEDR = (0x00000018 >> 2), - REG_GAFR = (0x0000001c >> 2), + GPIO_BASE_ADDR = 0x90040000, + REG_GPLR = (0x00000000 >> 2), + REG_GPDR = (0x00000004 >> 2), + REG_GPSR = (0x00000008 >> 2), + REG_GPCR = (0x0000000c >> 2), + REG_GRER = (0x00000010 >> 2), + REG_GFER = (0x00000014 >> 2), + REG_GEDR = (0x00000018 >> 2), + REG_GAFR = (0x0000001c >> 2), INTC_BASE_ADDR = 0x90050000, REG_ICIP = (0x00000000 >> 2), @@ -202,159 +202,159 @@ protected: // register contents enum : uint32_t { - UART3_FIFO_PRE = 8, - UART3_FIFO_FRE = 9, - UART3_FIFO_ROR = 10, - - UTCR3_RXE_BIT = 0, - UTCR3_TXE_BIT = 1, - UTCR3_BRK_BIT = 2, - UTCR3_RIE_BIT = 3, - UTCR3_TIE_BIT = 4, - UTCR3_LBM_BIT = 5, - - UTSR0_TFS_BIT = 0, - UTSR0_RFS_BIT = 1, - UTSR0_RID_BIT = 2, - UTSR0_RBB_BIT = 3, - UTSR0_REB_BIT = 4, - UTSR0_EIF_BIT = 5, - - UTSR1_TBY_BIT = 0, - UTSR1_RNE_BIT = 1, - UTSR1_TNF_BIT = 2, - UTSR1_PRE_BIT = 3, - UTSR1_FRE_BIT = 4, - UTSR1_ROR_BIT = 5, - - MCCR0_ASD_BIT = 0, - MCCR0_ASD_MASK = 0x0000007f, - MCCR0_TSD_BIT = 8, - MCCR0_TSD_MASK = 0x00007f00, - MCCR0_MCE_BIT = 16, - MCCR0_ECS_BIT = 17, - MCCR0_ADM_BIT = 18, - MCCR0_TTE_BIT = 19, - MCCR0_TRE_BIT = 20, - MCCR0_ATE_BIT = 21, - MCCR0_ARE_BIT = 22, - MCCR0_LBM_BIT = 23, - MCCR0_ECP_BIT = 24, - MCCR0_ECP_MASK = 0x03000000, - - MCCR1_CFS_BIT = 20, - - MCDR2_RW_BIT = 16, - MCDR2_ADDR_BIT = 17, - MCDR2_ADDR_MASK = 0x001e0000, - - MCSR_ATS_BIT = 0, - MCSR_ARS_BIT = 1, - MCSR_TTS_BIT = 2, - MCSR_TRS_BIT = 3, - MCSR_ATU_BIT = 4, - MCSR_ARO_BIT = 5, - MCSR_TTU_BIT = 6, - MCSR_TRO_BIT = 7, - MCSR_ANF_BIT = 8, - MCSR_ANE_BIT = 9, - MCSR_TNF_BIT = 10, - MCSR_TNE_BIT = 11, - MCSR_CWC_BIT = 12, - MCSR_CRC_BIT = 13, - MCSR_ACE_BIT = 14, - MCSR_TCE_BIT = 15, - - SSCR0_DSS_BIT = 0, - SSCR0_DSS_MASK = 0x0000000f, - SSCR0_FRF_BIT = 4, - SSCR0_FRF_MASK = 0x00000030, - SSCR0_SSE_BIT = 7, - SSCR0_SCR_BIT = 8, - SSCR0_SCR_MASK = 0x0000ff00, - - SSCR1_RIE_BIT = 0, - SSCR1_TIE_BIT = 1, - SSCR1_LBM_BIT = 2, - SSCR1_SPO_BIT = 3, - SSCR1_SPH_BIT = 4, - SSCR1_ECS_BIT = 5, - - SSSR_TNF_BIT = 1, - SSSR_RNE_BIT = 2, - SSSR_BSY_BIT = 3, - SSSR_TFS_BIT = 4, - SSSR_RFS_BIT = 5, - SSSR_ROR_BIT = 6, - - RTSR_AL_BIT = 0, - RTSR_AL_MASK = (1 << RTSR_AL_BIT), - RTSR_HZ_BIT = 1, - RTSR_HZ_MASK = (1 << RTSR_HZ_BIT), - RTSR_ALE_BIT = 2, - RTSR_ALE_MASK = (1 << RTSR_ALE_BIT), - RTSR_HZE_BIT = 3, - RTSR_HZE_MASK = (1 << RTSR_HZE_BIT) + UART3_FIFO_PRE = 8, + UART3_FIFO_FRE = 9, + UART3_FIFO_ROR = 10, + + UTCR3_RXE_BIT = 0, + UTCR3_TXE_BIT = 1, + UTCR3_BRK_BIT = 2, + UTCR3_RIE_BIT = 3, + UTCR3_TIE_BIT = 4, + UTCR3_LBM_BIT = 5, + + UTSR0_TFS_BIT = 0, + UTSR0_RFS_BIT = 1, + UTSR0_RID_BIT = 2, + UTSR0_RBB_BIT = 3, + UTSR0_REB_BIT = 4, + UTSR0_EIF_BIT = 5, + + UTSR1_TBY_BIT = 0, + UTSR1_RNE_BIT = 1, + UTSR1_TNF_BIT = 2, + UTSR1_PRE_BIT = 3, + UTSR1_FRE_BIT = 4, + UTSR1_ROR_BIT = 5, + + MCCR0_ASD_BIT = 0, + MCCR0_ASD_MASK = 0x0000007f, + MCCR0_TSD_BIT = 8, + MCCR0_TSD_MASK = 0x00007f00, + MCCR0_MCE_BIT = 16, + MCCR0_ECS_BIT = 17, + MCCR0_ADM_BIT = 18, + MCCR0_TTE_BIT = 19, + MCCR0_TRE_BIT = 20, + MCCR0_ATE_BIT = 21, + MCCR0_ARE_BIT = 22, + MCCR0_LBM_BIT = 23, + MCCR0_ECP_BIT = 24, + MCCR0_ECP_MASK = 0x03000000, + + MCCR1_CFS_BIT = 20, + + MCDR2_RW_BIT = 16, + MCDR2_ADDR_BIT = 17, + MCDR2_ADDR_MASK = 0x001e0000, + + MCSR_ATS_BIT = 0, + MCSR_ARS_BIT = 1, + MCSR_TTS_BIT = 2, + MCSR_TRS_BIT = 3, + MCSR_ATU_BIT = 4, + MCSR_ARO_BIT = 5, + MCSR_TTU_BIT = 6, + MCSR_TRO_BIT = 7, + MCSR_ANF_BIT = 8, + MCSR_ANE_BIT = 9, + MCSR_TNF_BIT = 10, + MCSR_TNE_BIT = 11, + MCSR_CWC_BIT = 12, + MCSR_CRC_BIT = 13, + MCSR_ACE_BIT = 14, + MCSR_TCE_BIT = 15, + + SSCR0_DSS_BIT = 0, + SSCR0_DSS_MASK = 0x0000000f, + SSCR0_FRF_BIT = 4, + SSCR0_FRF_MASK = 0x00000030, + SSCR0_SSE_BIT = 7, + SSCR0_SCR_BIT = 8, + SSCR0_SCR_MASK = 0x0000ff00, + + SSCR1_RIE_BIT = 0, + SSCR1_TIE_BIT = 1, + SSCR1_LBM_BIT = 2, + SSCR1_SPO_BIT = 3, + SSCR1_SPH_BIT = 4, + SSCR1_ECS_BIT = 5, + + SSSR_TNF_BIT = 1, + SSSR_RNE_BIT = 2, + SSSR_BSY_BIT = 3, + SSSR_TFS_BIT = 4, + SSSR_RFS_BIT = 5, + SSSR_ROR_BIT = 6, + + RTSR_AL_BIT = 0, + RTSR_AL_MASK = (1 << RTSR_AL_BIT), + RTSR_HZ_BIT = 1, + RTSR_HZ_MASK = (1 << RTSR_HZ_BIT), + RTSR_ALE_BIT = 2, + RTSR_ALE_MASK = (1 << RTSR_ALE_BIT), + RTSR_HZE_BIT = 3, + RTSR_HZE_MASK = (1 << RTSR_HZE_BIT) }; // interrupt bits enum : uint32_t { - INT_GPIO0 = 0, - INT_GPIO1 = 1, - INT_GPIO2 = 2, - INT_GPIO3 = 3, - INT_GPIO4 = 4, - INT_GPIO5 = 5, - INT_GPIO6 = 6, - INT_GPIO7 = 7, - INT_GPIO8 = 8, - INT_GPIO9 = 9, - INT_GPIO10 = 10, - INT_GPIOHI = 11, - INT_LCD = 12, - INT_UDC = 13, - INT_UART1 = 15, - INT_UART2 = 16, - INT_UART3 = 17, - INT_MCP = 18, - INT_SSP = 19, - INT_DMA0 = 20, - INT_DMA1 = 21, - INT_DMA2 = 22, - INT_DMA3 = 23, - INT_DMA4 = 24, - INT_DMA5 = 25, - INT_OSTIMER0 = 26, - INT_OSTIMER1 = 27, - INT_OSTIMER2 = 28, - INT_OSTIMER3 = 29, - INT_RTC_TICK = 30, - INT_RTC_ALARM = 31 + INT_GPIO0 = 0, + INT_GPIO1 = 1, + INT_GPIO2 = 2, + INT_GPIO3 = 3, + INT_GPIO4 = 4, + INT_GPIO5 = 5, + INT_GPIO6 = 6, + INT_GPIO7 = 7, + INT_GPIO8 = 8, + INT_GPIO9 = 9, + INT_GPIO10 = 10, + INT_GPIOHI = 11, + INT_LCD = 12, + INT_UDC = 13, + INT_UART1 = 15, + INT_UART2 = 16, + INT_UART3 = 17, + INT_MCP = 18, + INT_SSP = 19, + INT_DMA0 = 20, + INT_DMA1 = 21, + INT_DMA2 = 22, + INT_DMA3 = 23, + INT_DMA4 = 24, + INT_DMA5 = 25, + INT_OSTIMER0 = 26, + INT_OSTIMER1 = 27, + INT_OSTIMER2 = 28, + INT_OSTIMER3 = 29, + INT_RTC_TICK = 30, + INT_RTC_ALARM = 31 }; // UART3 interrupt sources enum : unsigned { - UART3_TFS = 0, - UART3_RFS = 1, - UART3_RID = 2, - UART3_RBB = 3, - UART3_REB = 4, - UART3_EIF = 5, + UART3_TFS = 0, + UART3_RFS = 1, + UART3_RID = 2, + UART3_RBB = 3, + UART3_REB = 4, + UART3_EIF = 5, }; // MCP interrupt sources enum : unsigned { - MCP_AUDIO_TX = 0, - MCP_AUDIO_RX = 1, - MCP_TELECOM_TX = 2, - MCP_TELECOM_RX = 3, - MCP_AUDIO_UNDERRUN = 4, - MCP_AUDIO_OVERRUN = 5, - MCP_TELECOM_UNDERRUN = 6, - MCP_TELECOM_OVERRUN = 7 + MCP_AUDIO_TX = 0, + MCP_AUDIO_RX = 1, + MCP_TELECOM_TX = 2, + MCP_TELECOM_RX = 3, + MCP_AUDIO_UNDERRUN = 4, + MCP_AUDIO_OVERRUN = 5, + MCP_TELECOM_UNDERRUN = 6, + MCP_TELECOM_OVERRUN = 7 }; struct uart_regs @@ -373,7 +373,7 @@ protected: int tx_fifo_write_idx; int tx_fifo_count; - bool rx_break_interlock; + bool rx_break_interlock; }; struct mcp_regs @@ -486,15 +486,15 @@ protected: uint32_t icpr; }; - uart_regs m_uart_regs; - mcp_regs m_mcp_regs; - ssp_regs m_ssp_regs; - ostimer_regs m_ostmr_regs; - rtc_regs m_rtc_regs; - power_regs m_power_regs; - uint32_t m_rcsr; - gpio_regs m_gpio_regs; - intc_regs m_intc_regs; + uart_regs m_uart_regs; + mcp_regs m_mcp_regs; + ssp_regs m_ssp_regs; + ostimer_regs m_ostmr_regs; + rtc_regs m_rtc_regs; + power_regs m_power_regs; + uint32_t m_rcsr; + gpio_regs m_gpio_regs; + intc_regs m_intc_regs; required_device<cpu_device> m_maincpu; required_device<input_merger_device> m_uart3_irqs; diff --git a/src/devices/machine/sa1111.cpp b/src/devices/machine/sa1111.cpp index 3569349be14..2871576e701 100644 --- a/src/devices/machine/sa1111.cpp +++ b/src/devices/machine/sa1111.cpp @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Intel SA1111 Microprocessor Companion Chip skeleton + Intel SA1111 Microprocessor Companion Chip skeleton ***************************************************************************/ @@ -10,17 +10,17 @@ #include "sa1111.h" #define LOG_UNKNOWN (1 << 1) -#define LOG_SBI (1 << 2) -#define LOG_SK (1 << 3) -#define LOG_USB (1 << 4) -#define LOG_AUDIO (1 << 5) -#define LOG_SSP (1 << 6) -#define LOG_SSP_HF (1 << 7) -#define LOG_TRACK (1 << 8) -#define LOG_MOUSE (1 << 9) -#define LOG_GPIO (1 << 10) -#define LOG_INTC (1 << 11) -#define LOG_CARD (1 << 12) +#define LOG_SBI (1 << 2) +#define LOG_SK (1 << 3) +#define LOG_USB (1 << 4) +#define LOG_AUDIO (1 << 5) +#define LOG_SSP (1 << 6) +#define LOG_SSP_HF (1 << 7) +#define LOG_TRACK (1 << 8) +#define LOG_MOUSE (1 << 9) +#define LOG_GPIO (1 << 10) +#define LOG_INTC (1 << 11) +#define LOG_CARD (1 << 12) #define LOG_ALL (LOG_UNKNOWN | LOG_SBI | LOG_SK | LOG_USB | LOG_AUDIO | LOG_SSP | LOG_TRACK | LOG_MOUSE | LOG_GPIO | LOG_INTC | LOG_CARD) #define VERBOSE (0) // (LOG_ALL) diff --git a/src/devices/machine/sa1111.h b/src/devices/machine/sa1111.h index dc3d04d760a..03bebf06c1d 100644 --- a/src/devices/machine/sa1111.h +++ b/src/devices/machine/sa1111.h @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Intel SA1111 Microprocessor Companion Chip skeleton + Intel SA1111 Microprocessor Companion Chip skeleton ***************************************************************************/ @@ -201,248 +201,248 @@ protected: // register contents enum : uint32_t { - SKCR_PLLB_BIT = 0, - SKCR_RCLK_BIT = 1, - SKCR_SLEEP_BIT = 2, - SKCR_DOZE_BIT = 3, - SKCR_VCO_BIT = 4, - SKCR_SCANTST_BIT = 5, - SKCR_CLKTST_BIT = 6, - SKCR_RDY_BIT = 7, - SKCR_SLAC_BIT = 8, - SKCR_OPPC_BIT = 9, - SKCR_PII_BIT = 10, - SKCR_UIOTEN_BIT = 11, - SKCR_OEEN_BIT = 12, - - SMCR_DTIM_BIT = 0, - SMCR_MBGE_BIT = 1, - SMCR_DRAC_BIT = 2, - SMCR_DRAC_MASK = 0x0000001c, - SMCR_CLAT_BIT = 5, - - SKPCR_UCLKE_BIT = 0, - SKPCR_ACCLKE_BIT = 1, - SKPCR_ISCLKE_BIT = 2, - SKPCR_L3CLKE_BIT = 3, - SKPCR_SCLKE_BIT = 4, - SKPCR_PMCLKE_BIT = 5, - SKPCR_PTCLKE_BIT = 6, - SKPCR_DCLKE_BIT = 7, - SKPCR_PWMCLKE_BIT = 8, - - SKCDR_FBD_BIT = 0, - SKCDR_FBD_MASK = 0x0000007f, - SKCDR_IPD_BIT = 7, - SKCDR_IPD_MASK = 0x00000f80, - SKCDR_OPD_BIT = 12, - SKCDR_OPD_MASK = 0x00003000, - SKCDR_OPS_BIT = 14, - - SKAUD_ACD_BIT = 0, - SKAUD_ACD_MASK = 0x0000007f, - - SKPMC_PMCD_BIT = 0, - SKPMC_PMCD_MASK = 0x000000ff, - - SKPTC_PTCD_BIT = 0, - SKPTC_PTCD_MASK = 0x000000ff, - - SKPEN0_PWM0EN_BIT = 0, - - SKPWM0_PWM0CK_BIT = 0, - SKPWM0_PWM0CK_MASK = 0x000000ff, - - SKPEN1_PWM1EN_BIT = 0, - - SKPWM1_PWM1CK_BIT = 0, - SKPWM1_PWM1CK_MASK = 0x000000ff, - - USBSTAT_IHRW_BIT = 7, - USBSTAT_IHBA_BIT = 8, - USBSTAT_NHT_BIT = 9, - USBSTAT_NHFCT_BIT = 10, - USBSTAT_UPRT_BIT = 11, - - USBRST_FIR_BIT = 0, - USBRST_FHR_BIT = 1, - USBRST_CGR_BIT = 2, - USBRST_SSDC_BIT = 3, - USBRST_UIT_BIT = 4, - USBRST_SSE_BIT = 5, - USBRST_PSPL_BIT = 6, - USBRST_PCPL_BIT = 7, - - USBINT_IHRWT_BIT = 7, - USBINT_IHBAT_BIT = 8, - USBINT_NHT_BIT = 9, - USBINT_NHFCT_BIT = 10, - USBINT_UPRT_BIT = 11, - - SACR0_ENB_BIT = 0, - SACR0_BCKD_BIT = 2, - SACR0_RST_BIT = 3, - SACR0_TFTH_BIT = 8, - SACR0_TFTH_MASK = 0x00000f00, - SACR0_RFTH_BIT = 12, - SACR0_RFTH_MASK = 0x0000f000, - - SACR1_AMSL_BIT = 0, - SACR1_L3EN_BIT = 1, - SACR1_L3MB_BIT = 2, - SACR1_DREC_BIT = 3, - SACR1_DRPL_BIT = 4, - SACR1_ENLBF_BIT = 5, - - SACR2_TS3V_BIT = 0, - SACR2_TS4V_BIT = 1, - SACR2_WKUP_BIT = 2, - SACR2_DREC_BIT = 3, - SACR2_DRPL_BIT = 4, - SACR2_ENLBF_BIT = 5, - SACR2_RESET_BIT = 6, - - SASCR_TUR_BIT = 5, - SASCR_ROR_BIT = 6, - SASCR_DTS_BIT = 16, - SASCR_RDD_BIT = 17, - SASCR_STO_BIT = 18, - - SASR0_TNF_BIT = 0, - SASR0_RNE_BIT = 1, - SASR0_BSY_BIT = 2, - SASR0_TFS_BIT = 3, - SASR0_RFS_BIT = 4, - SASR0_TUR_BIT = 5, - SASR0_ROR_BIT = 6, - SASR0_TFL_BIT = 7, - SASR0_TFL_MASK = 0x00000f00, - SASR0_RFL_BIT = 12, - SASR0_RFL_MASK = 0x0000f000, - SASR0_L3WD_BIT = 16, - SASR0_L3RD_BIT = 17, - - SASR1_TNF_BIT = 0, - SASR1_RNE_BIT = 1, - SASR1_BSY_BIT = 2, - SASR1_TFS_BIT = 3, - SASR1_RFS_BIT = 4, - SASR1_TUR_BIT = 5, - SASR1_ROR_BIT = 6, - SASR1_TFL_BIT = 8, - SASR1_TFL_MASK = 0x00000f00, - SASR1_RFL_BIT = 12, - SASR1_RFL_MASK = 0x0000f000, - SASR1_CADT_BIT = 16, - SASR1_SADR_BIT = 17, - SASR1_RSTO_BIT = 18, - SASR1_CLPM_BIT = 19, - SASR1_CRDY_BIT = 20, - SASR1_RS3V_BIT = 21, - SASR1_RS4V_BIT = 22, - - SADTCS_TDEN_BIT = 0, - SADTCS_TDBDA_BIT = 3, - SADTCS_TDSTA_BIT = 4, - SADTCS_TDBDB_BIT = 5, - SADTCS_TDSTB_BIT = 6, - - SADRCS_RDEN_BIT = 0, - SADRCS_RDBDA_BIT = 3, - SADRCS_RDSTA_BIT = 4, - SADRCS_RDBDB_BIT = 5, - SADRCS_RDSTB_BIT = 6, - - SAITR_TFS_BIT = 0, - SAITR_RFS_BIT = 1, - SAITR_TUR_BIT = 2, - SAITR_ROR_BIT = 3, - SAITR_CADT_BIT = 4, - SAITR_SADR_BIT = 5, - SAITR_RSTO_BIT = 6, - SAITR_TDBDA_BIT = 8, - SAITR_TDBDB_BIT = 9, - SAITR_RDBDA_BIT = 10, - SAITR_RDBDB_BIT = 11, - - SSPCR0_DSS_BIT = 0, - SSPCR0_DSS_MASK = 0x0000000f, - SSPCR0_FRF_BIT = 4, - SSPCR0_FRF_MASK = 0x00000030, - SSPCR0_FRF_SPI = 0, - SSPCR0_FRF_SSP = 1, - SSPCR0_FRF_MWIRE = 2, - SSPCR0_FRF_RESV = 3, - SSPCR0_SSPEN_BIT = 7, - SSPCR0_SCR_BIT = 8, - SSPCR0_SCR_MASK = 0x0000ff00, - - SSPCR1_LBM_BIT = 2, - SSPCR1_SPO_BIT = 3, - SSPCR1_SPH_BIT = 4, - SSPCR1_TFT_BIT = 7, - SSPCR1_TFT_MASK = 0x00000780, - SSPCR1_RFT_BIT = 11, - SSPCR1_RFT_MASK = 0x00007800, - - SSPSR_TNF_BIT = 2, - SSPSR_RNE_BIT = 3, - SSPSR_BSY_BIT = 4, - SSPSR_TFS_BIT = 5, - SSPSR_RFS_BIT = 6, - SSPSR_ROR_BIT = 7, - SSPSR_TFL_BIT = 8, - SSPSR_TFL_MASK = 0x00000f00, - SSPSR_RFL_BIT = 12, - SSPSR_RFL_MASK = 0x0000f000, - - SSPITR_TFS_BIT = 2, - SSPITR_RFS_BIT = 3, - SSPITR_ROR_BIT = 4, - - KBDCR_FKC_BIT = 0, - KBDCR_FKD_BIT = 1, - KBDCR_ENA_BIT = 3, - - KBDSTAT_KBC_BIT = 0, - KBDSTAT_KBD_BIT = 1, - KBDSTAT_RXP_BIT = 2, - KBDSTAT_ENA_BIT = 3, - KBDSTAT_RXB_BIT = 4, - KBDSTAT_RXF_BIT = 5, - KBDSTAT_TXB_BIT = 6, - KBDSTAT_TXE_BIT = 7, - KBDSTAT_STP_BIT = 8, - - KBDCLKDIV_DV_BIT = 0, - KBDCLKDIV_DV_MASK = 0x00000003, - - PCSR_S0R_BIT = 0, - PCSR_S1R_BIT = 1, - PCSR_S0CD_BIT = 2, - PCSR_S1CD_BIT = 3, - PCSR_S0VS1_BIT = 4, - PCSR_S0VS2_BIT = 5, - PCSR_S1VS1_BIT = 6, - PCSR_S1VS2_BIT = 7, - PCSR_S0WP_BIT = 8, - PCSR_S1WP_BIT = 9, - PCSR_S0BVD1_BIT = 10, - PCSR_S0BVD2_BIT = 11, - PCSR_S1BVD1_BIT = 12, - PCSR_S1BVD2_BIT = 13, - - PCCR_S0RST_BIT = 0, - PCCR_S1RST_BIT = 1, - PCCR_S0FLT_BIT = 2, - PCCR_S1FLT_BIT = 3, - PCCR_S0PWEN_BIT = 4, - PCCR_S1PWEN_BIT = 5, - PCCR_S0PSE_BIT = 6, - PCCR_S1PSE_BIT = 7, - - PCSSR_S0SLP_BIT = 0, - PCSSR_S1SLP_BIT = 1 + SKCR_PLLB_BIT = 0, + SKCR_RCLK_BIT = 1, + SKCR_SLEEP_BIT = 2, + SKCR_DOZE_BIT = 3, + SKCR_VCO_BIT = 4, + SKCR_SCANTST_BIT = 5, + SKCR_CLKTST_BIT = 6, + SKCR_RDY_BIT = 7, + SKCR_SLAC_BIT = 8, + SKCR_OPPC_BIT = 9, + SKCR_PII_BIT = 10, + SKCR_UIOTEN_BIT = 11, + SKCR_OEEN_BIT = 12, + + SMCR_DTIM_BIT = 0, + SMCR_MBGE_BIT = 1, + SMCR_DRAC_BIT = 2, + SMCR_DRAC_MASK = 0x0000001c, + SMCR_CLAT_BIT = 5, + + SKPCR_UCLKE_BIT = 0, + SKPCR_ACCLKE_BIT = 1, + SKPCR_ISCLKE_BIT = 2, + SKPCR_L3CLKE_BIT = 3, + SKPCR_SCLKE_BIT = 4, + SKPCR_PMCLKE_BIT = 5, + SKPCR_PTCLKE_BIT = 6, + SKPCR_DCLKE_BIT = 7, + SKPCR_PWMCLKE_BIT = 8, + + SKCDR_FBD_BIT = 0, + SKCDR_FBD_MASK = 0x0000007f, + SKCDR_IPD_BIT = 7, + SKCDR_IPD_MASK = 0x00000f80, + SKCDR_OPD_BIT = 12, + SKCDR_OPD_MASK = 0x00003000, + SKCDR_OPS_BIT = 14, + + SKAUD_ACD_BIT = 0, + SKAUD_ACD_MASK = 0x0000007f, + + SKPMC_PMCD_BIT = 0, + SKPMC_PMCD_MASK = 0x000000ff, + + SKPTC_PTCD_BIT = 0, + SKPTC_PTCD_MASK = 0x000000ff, + + SKPEN0_PWM0EN_BIT = 0, + + SKPWM0_PWM0CK_BIT = 0, + SKPWM0_PWM0CK_MASK = 0x000000ff, + + SKPEN1_PWM1EN_BIT = 0, + + SKPWM1_PWM1CK_BIT = 0, + SKPWM1_PWM1CK_MASK = 0x000000ff, + + USBSTAT_IHRW_BIT = 7, + USBSTAT_IHBA_BIT = 8, + USBSTAT_NHT_BIT = 9, + USBSTAT_NHFCT_BIT = 10, + USBSTAT_UPRT_BIT = 11, + + USBRST_FIR_BIT = 0, + USBRST_FHR_BIT = 1, + USBRST_CGR_BIT = 2, + USBRST_SSDC_BIT = 3, + USBRST_UIT_BIT = 4, + USBRST_SSE_BIT = 5, + USBRST_PSPL_BIT = 6, + USBRST_PCPL_BIT = 7, + + USBINT_IHRWT_BIT = 7, + USBINT_IHBAT_BIT = 8, + USBINT_NHT_BIT = 9, + USBINT_NHFCT_BIT = 10, + USBINT_UPRT_BIT = 11, + + SACR0_ENB_BIT = 0, + SACR0_BCKD_BIT = 2, + SACR0_RST_BIT = 3, + SACR0_TFTH_BIT = 8, + SACR0_TFTH_MASK = 0x00000f00, + SACR0_RFTH_BIT = 12, + SACR0_RFTH_MASK = 0x0000f000, + + SACR1_AMSL_BIT = 0, + SACR1_L3EN_BIT = 1, + SACR1_L3MB_BIT = 2, + SACR1_DREC_BIT = 3, + SACR1_DRPL_BIT = 4, + SACR1_ENLBF_BIT = 5, + + SACR2_TS3V_BIT = 0, + SACR2_TS4V_BIT = 1, + SACR2_WKUP_BIT = 2, + SACR2_DREC_BIT = 3, + SACR2_DRPL_BIT = 4, + SACR2_ENLBF_BIT = 5, + SACR2_RESET_BIT = 6, + + SASCR_TUR_BIT = 5, + SASCR_ROR_BIT = 6, + SASCR_DTS_BIT = 16, + SASCR_RDD_BIT = 17, + SASCR_STO_BIT = 18, + + SASR0_TNF_BIT = 0, + SASR0_RNE_BIT = 1, + SASR0_BSY_BIT = 2, + SASR0_TFS_BIT = 3, + SASR0_RFS_BIT = 4, + SASR0_TUR_BIT = 5, + SASR0_ROR_BIT = 6, + SASR0_TFL_BIT = 7, + SASR0_TFL_MASK = 0x00000f00, + SASR0_RFL_BIT = 12, + SASR0_RFL_MASK = 0x0000f000, + SASR0_L3WD_BIT = 16, + SASR0_L3RD_BIT = 17, + + SASR1_TNF_BIT = 0, + SASR1_RNE_BIT = 1, + SASR1_BSY_BIT = 2, + SASR1_TFS_BIT = 3, + SASR1_RFS_BIT = 4, + SASR1_TUR_BIT = 5, + SASR1_ROR_BIT = 6, + SASR1_TFL_BIT = 8, + SASR1_TFL_MASK = 0x00000f00, + SASR1_RFL_BIT = 12, + SASR1_RFL_MASK = 0x0000f000, + SASR1_CADT_BIT = 16, + SASR1_SADR_BIT = 17, + SASR1_RSTO_BIT = 18, + SASR1_CLPM_BIT = 19, + SASR1_CRDY_BIT = 20, + SASR1_RS3V_BIT = 21, + SASR1_RS4V_BIT = 22, + + SADTCS_TDEN_BIT = 0, + SADTCS_TDBDA_BIT = 3, + SADTCS_TDSTA_BIT = 4, + SADTCS_TDBDB_BIT = 5, + SADTCS_TDSTB_BIT = 6, + + SADRCS_RDEN_BIT = 0, + SADRCS_RDBDA_BIT = 3, + SADRCS_RDSTA_BIT = 4, + SADRCS_RDBDB_BIT = 5, + SADRCS_RDSTB_BIT = 6, + + SAITR_TFS_BIT = 0, + SAITR_RFS_BIT = 1, + SAITR_TUR_BIT = 2, + SAITR_ROR_BIT = 3, + SAITR_CADT_BIT = 4, + SAITR_SADR_BIT = 5, + SAITR_RSTO_BIT = 6, + SAITR_TDBDA_BIT = 8, + SAITR_TDBDB_BIT = 9, + SAITR_RDBDA_BIT = 10, + SAITR_RDBDB_BIT = 11, + + SSPCR0_DSS_BIT = 0, + SSPCR0_DSS_MASK = 0x0000000f, + SSPCR0_FRF_BIT = 4, + SSPCR0_FRF_MASK = 0x00000030, + SSPCR0_FRF_SPI = 0, + SSPCR0_FRF_SSP = 1, + SSPCR0_FRF_MWIRE = 2, + SSPCR0_FRF_RESV = 3, + SSPCR0_SSPEN_BIT = 7, + SSPCR0_SCR_BIT = 8, + SSPCR0_SCR_MASK = 0x0000ff00, + + SSPCR1_LBM_BIT = 2, + SSPCR1_SPO_BIT = 3, + SSPCR1_SPH_BIT = 4, + SSPCR1_TFT_BIT = 7, + SSPCR1_TFT_MASK = 0x00000780, + SSPCR1_RFT_BIT = 11, + SSPCR1_RFT_MASK = 0x00007800, + + SSPSR_TNF_BIT = 2, + SSPSR_RNE_BIT = 3, + SSPSR_BSY_BIT = 4, + SSPSR_TFS_BIT = 5, + SSPSR_RFS_BIT = 6, + SSPSR_ROR_BIT = 7, + SSPSR_TFL_BIT = 8, + SSPSR_TFL_MASK = 0x00000f00, + SSPSR_RFL_BIT = 12, + SSPSR_RFL_MASK = 0x0000f000, + + SSPITR_TFS_BIT = 2, + SSPITR_RFS_BIT = 3, + SSPITR_ROR_BIT = 4, + + KBDCR_FKC_BIT = 0, + KBDCR_FKD_BIT = 1, + KBDCR_ENA_BIT = 3, + + KBDSTAT_KBC_BIT = 0, + KBDSTAT_KBD_BIT = 1, + KBDSTAT_RXP_BIT = 2, + KBDSTAT_ENA_BIT = 3, + KBDSTAT_RXB_BIT = 4, + KBDSTAT_RXF_BIT = 5, + KBDSTAT_TXB_BIT = 6, + KBDSTAT_TXE_BIT = 7, + KBDSTAT_STP_BIT = 8, + + KBDCLKDIV_DV_BIT = 0, + KBDCLKDIV_DV_MASK = 0x00000003, + + PCSR_S0R_BIT = 0, + PCSR_S1R_BIT = 1, + PCSR_S0CD_BIT = 2, + PCSR_S1CD_BIT = 3, + PCSR_S0VS1_BIT = 4, + PCSR_S0VS2_BIT = 5, + PCSR_S1VS1_BIT = 6, + PCSR_S1VS2_BIT = 7, + PCSR_S0WP_BIT = 8, + PCSR_S1WP_BIT = 9, + PCSR_S0BVD1_BIT = 10, + PCSR_S0BVD2_BIT = 11, + PCSR_S1BVD1_BIT = 12, + PCSR_S1BVD2_BIT = 13, + + PCCR_S0RST_BIT = 0, + PCCR_S1RST_BIT = 1, + PCCR_S0FLT_BIT = 2, + PCCR_S1FLT_BIT = 3, + PCCR_S0PWEN_BIT = 4, + PCCR_S1PWEN_BIT = 5, + PCCR_S0PSE_BIT = 6, + PCCR_S1PSE_BIT = 7, + + PCSSR_S0SLP_BIT = 0, + PCSSR_S1SLP_BIT = 1 }; struct sbi_regs diff --git a/src/devices/machine/scoop.cpp b/src/devices/machine/scoop.cpp index ace4ee78b81..1a254169f93 100644 --- a/src/devices/machine/scoop.cpp +++ b/src/devices/machine/scoop.cpp @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Sharp Scoop peripheral chip emulation skeleton + Sharp Scoop peripheral chip emulation skeleton ***************************************************************************/ @@ -10,8 +10,8 @@ #include "scoop.h" #define LOG_UNKNOWN (1 << 1) -#define LOG_READS (1 << 2) -#define LOG_WRITES (1 << 3) +#define LOG_READS (1 << 2) +#define LOG_WRITES (1 << 3) #define LOG_ALL (LOG_UNKNOWN | LOG_READS | LOG_WRITES) #define VERBOSE (LOG_ALL) diff --git a/src/devices/machine/scoop.h b/src/devices/machine/scoop.h index 48aae34361d..1fb0edaae66 100644 --- a/src/devices/machine/scoop.h +++ b/src/devices/machine/scoop.h @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Sharp Scoop peripheral chip emulation skeleton + Sharp Scoop peripheral chip emulation skeleton ***************************************************************************/ diff --git a/src/devices/machine/ucb1200.cpp b/src/devices/machine/ucb1200.cpp index ae88612f23b..54e68321523 100644 --- a/src/devices/machine/ucb1200.cpp +++ b/src/devices/machine/ucb1200.cpp @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Philips UCB1200 Advanced modem/audio analog front-end skeleton + Philips UCB1200 Advanced modem/audio analog front-end skeleton ***************************************************************************/ @@ -10,8 +10,8 @@ #include "ucb1200.h" #define LOG_UNKNOWN (1 << 1) -#define LOG_READS (1 << 2) -#define LOG_WRITES (1 << 3) +#define LOG_READS (1 << 2) +#define LOG_WRITES (1 << 3) #define LOG_ALL (LOG_UNKNOWN | LOG_READS | LOG_WRITES) #define VERBOSE (LOG_ALL) diff --git a/src/devices/machine/ucb1200.h b/src/devices/machine/ucb1200.h index a17104e4e96..19cf474917b 100644 --- a/src/devices/machine/ucb1200.h +++ b/src/devices/machine/ucb1200.h @@ -2,7 +2,7 @@ // copyright-holders:Ryan Holtz /*************************************************************************** - Philips UCB1200 Advanced modem/audio analog front-end skeleton + Philips UCB1200 Advanced modem/audio analog front-end skeleton ***************************************************************************/ @@ -42,81 +42,81 @@ protected: // register contents enum : uint16_t { - SIB_ZERO_BIT = 15, - - IO_INT0_BIT = 0, - ADC_INT_BIT = 11, - TSPX_INT_BIT = 12, - TSMX_INT_BIT = 13, - TCLIP_INT_BIT = 14, - ACLIP_INT_BIT = 15, - - TEL_DIV_BIT = 0, - TEL_DIV_MASK = 0x007f, - TEL_LOOP_BIT = 7, - - TEL_VOICE_ENA_BIT = 3, - TEL_CLIP_BIT = 4, - TEL_ATT_BIT = 6, - TEL_SIDE_ENA_BIT = 11, - TEL_MUTE_BIT = 13, - TEL_IN_ENA_BIT = 14, - TEL_OUT_ENA_BIT = 15, - - AUD_DIV_BIT = 0, - AUD_DIV_MASK = 0x007f, - AUD_GAIN_BIT = 7, - AUD_GAIN_MASK = 0x0f80, - - AUD_ATT_BIT = 0, - AUD_ATT_MASK = 0x001f, - AUD_CLIP_BIT = 6, - AUD_LOOP_BIT = 8, - AUD_MUTE_BIT = 13, - AUD_IN_ENA_BIT = 14, - AUD_OUT_ENA_BIT = 15, - - TSMX_POW_BIT = 0, - TSPX_POW_BIT = 1, - TSMY_POW_BIT = 2, - TSPY_POW_BIT = 3, - TSMX_GND_BIT = 4, - TSPX_GND_BIT = 5, - TSMY_GND_BIT = 6, - TSPY_GND_BIT = 7, - TSC_MODE_BIT = 8, - TSC_MODE_MASK = 0x0300, - TSC_BIAS_ENA_BIT = 11, - TSPX_LOW_BIT = 12, - TSMX_LOW_BIT = 13, - TOUCH_WRITE_MASK = 0x0fff, - - ADC_SYNC_ENA_BIT = 0, - VREFBYP_CON_BIT = 1, - ADC_INPUT_BIT = 2, - ADC_INPUT_MASK = 0x001c, - ADC_INPUT_TSPX = 0, - ADC_INPUT_TSMX = 1, - ADC_INPUT_TSPY = 2, - ADC_INPUT_TSMY = 3, - ADC_INPUT_AD0 = 4, - ADC_INPUT_AD1 = 5, - ADC_INPUT_AD2 = 6, - ADC_INPUT_AD3 = 7, - EXT_REF_ENA_BIT = 5, - ADC_START_BIT = 7, - ADC_ENA_BIT = 15, - - ADC_DATA_BIT = 5, - ADC_DATA_MASK = 0x7fe0, - ADC_DAT_VAL_BIT = 15, - - AUD_TEST_BIT = 0, - TEL_TEST_BIT = 1, - PROD_TEST_MODE_BIT = 2, - PROD_TEST_MODE_MASK = 0x003c, - DYN_VFLAG_ENA_BIT = 12, - AUD_OFF_CAN_BIT = 13 + SIB_ZERO_BIT = 15, + + IO_INT0_BIT = 0, + ADC_INT_BIT = 11, + TSPX_INT_BIT = 12, + TSMX_INT_BIT = 13, + TCLIP_INT_BIT = 14, + ACLIP_INT_BIT = 15, + + TEL_DIV_BIT = 0, + TEL_DIV_MASK = 0x007f, + TEL_LOOP_BIT = 7, + + TEL_VOICE_ENA_BIT = 3, + TEL_CLIP_BIT = 4, + TEL_ATT_BIT = 6, + TEL_SIDE_ENA_BIT = 11, + TEL_MUTE_BIT = 13, + TEL_IN_ENA_BIT = 14, + TEL_OUT_ENA_BIT = 15, + + AUD_DIV_BIT = 0, + AUD_DIV_MASK = 0x007f, + AUD_GAIN_BIT = 7, + AUD_GAIN_MASK = 0x0f80, + + AUD_ATT_BIT = 0, + AUD_ATT_MASK = 0x001f, + AUD_CLIP_BIT = 6, + AUD_LOOP_BIT = 8, + AUD_MUTE_BIT = 13, + AUD_IN_ENA_BIT = 14, + AUD_OUT_ENA_BIT = 15, + + TSMX_POW_BIT = 0, + TSPX_POW_BIT = 1, + TSMY_POW_BIT = 2, + TSPY_POW_BIT = 3, + TSMX_GND_BIT = 4, + TSPX_GND_BIT = 5, + TSMY_GND_BIT = 6, + TSPY_GND_BIT = 7, + TSC_MODE_BIT = 8, + TSC_MODE_MASK = 0x0300, + TSC_BIAS_ENA_BIT = 11, + TSPX_LOW_BIT = 12, + TSMX_LOW_BIT = 13, + TOUCH_WRITE_MASK = 0x0fff, + + ADC_SYNC_ENA_BIT = 0, + VREFBYP_CON_BIT = 1, + ADC_INPUT_BIT = 2, + ADC_INPUT_MASK = 0x001c, + ADC_INPUT_TSPX = 0, + ADC_INPUT_TSMX = 1, + ADC_INPUT_TSPY = 2, + ADC_INPUT_TSMY = 3, + ADC_INPUT_AD0 = 4, + ADC_INPUT_AD1 = 5, + ADC_INPUT_AD2 = 6, + ADC_INPUT_AD3 = 7, + EXT_REF_ENA_BIT = 5, + ADC_START_BIT = 7, + ADC_ENA_BIT = 15, + + ADC_DATA_BIT = 5, + ADC_DATA_MASK = 0x7fe0, + ADC_DAT_VAL_BIT = 15, + + AUD_TEST_BIT = 0, + TEL_TEST_BIT = 1, + PROD_TEST_MODE_BIT = 2, + PROD_TEST_MODE_MASK = 0x003c, + DYN_VFLAG_ENA_BIT = 12, + AUD_OFF_CAN_BIT = 13 }; uint16_t m_gpio_out_latch; |