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author MooglyGuy <MooglyGuy@users.noreply.github.com>2021-11-02 05:41:13 +0100
committer GitHub <noreply@github.com>2021-11-02 15:41:13 +1100
commit33e55b1ca764dd0ccda4a4da293e263a0de0ae13 (patch)
treef8feb897c2330005c021ef80fa2fc1c223964fc0 /src/devices/machine
parent6cbfe66e52cb68299e73014ec6a57aba5688ad49 (diff)
mc68328: Moved #define macros into enums within the class. (#8781) [Ryan Holtz]
Diffstat (limited to 'src/devices/machine')
-rw-r--r--src/devices/machine/mc68328.cpp338
-rw-r--r--src/devices/machine/mc68328.h330
2 files changed, 330 insertions, 338 deletions
diff --git a/src/devices/machine/mc68328.cpp b/src/devices/machine/mc68328.cpp
index c4b9d37b374..9ecce201f66 100644
--- a/src/devices/machine/mc68328.cpp
+++ b/src/devices/machine/mc68328.cpp
@@ -41,327 +41,9 @@
#define VERBOSE (0)
#include "logmacro.h"
-#define SCR_BETO 0x80
-#define SCR_WPV 0x40
-#define SCR_PRV 0x20
-#define SCR_BETEN 0x10
-#define SCR_SO 0x08
-#define SCR_DMAP 0x04
-#define SCR_WDTH8 0x01
-
-#define ICR_POL6 0x0100
-#define ICR_POL3 0x0200
-#define ICR_POL2 0x0400
-#define ICR_POL1 0x0800
-#define ICR_ET6 0x1000
-#define ICR_ET3 0x2000
-#define ICR_ET2 0x4000
-#define ICR_ET1 0x8000
-
-#define INT_SPIM 0x000001
-#define INT_TIMER2 0x000002
-#define INT_UART 0x000004
-#define INT_WDT 0x000008
-#define INT_RTC 0x000010
-#define INT_RESERVED 0x000020
-#define INT_KB 0x000040
-#define INT_PWM 0x000080
-#define INT_INT0 0x000100
-#define INT_INT1 0x000200
-#define INT_INT2 0x000400
-#define INT_INT3 0x000800
-#define INT_INT4 0x001000
-#define INT_INT5 0x002000
-#define INT_INT6 0x004000
-#define INT_INT7 0x008000
-#define INT_KBDINTS 0x00ff00
-#define INT_IRQ1 0x010000
-#define INT_IRQ2 0x020000
-#define INT_IRQ3 0x040000
-#define INT_IRQ6 0x080000
-#define INT_PEN 0x100000
-#define INT_SPIS 0x200000
-#define INT_TIMER1 0x400000
-#define INT_IRQ7 0x800000
-
-#define INT_M68K_LINE1 (INT_IRQ1)
-#define INT_M68K_LINE2 (INT_IRQ2)
-#define INT_M68K_LINE3 (INT_IRQ3)
-#define INT_M68K_LINE4 (INT_INT0 | INT_INT1 | INT_INT2 | INT_INT3 | INT_INT4 | INT_INT5 | INT_INT6 | INT_INT7 | \
- INT_PWM | INT_KB | INT_RTC | INT_WDT | INT_UART | INT_TIMER2 | INT_SPIM)
-#define INT_M68K_LINE5 (INT_PEN)
-#define INT_M68K_LINE6 (INT_IRQ6 | INT_TIMER1 | INT_SPIS)
-#define INT_M68K_LINE7 (INT_IRQ7)
-#define INT_M68K_LINE67 (INT_M68K_LINE6 | INT_M68K_LINE7)
-#define INT_M68K_LINE567 (INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7)
-#define INT_M68K_LINE4567 (INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7)
-#define INT_M68K_LINE34567 (INT_M68K_LINE3 | INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7)
-#define INT_M68K_LINE234567 (INT_M68K_LINE2 | INT_M68K_LINE3 | INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7)
-
-#define INT_IRQ1_SHIFT 0x000001
-#define INT_IRQ2_SHIFT 0x000002
-#define INT_IRQ3_SHIFT 0x000004
-#define INT_IRQ6_SHIFT 0x000008
-#define INT_PEN_SHIFT 0x000010
-#define INT_SPIS_SHIFT 0x000020
-#define INT_TIMER1_SHIFT 0x000040
-#define INT_IRQ7_SHIFT 0x000080
-
-#define INT_ACTIVE 1
-#define INT_INACTIVE 0
-
-#define GRPBASE_BASE_ADDR 0xfff0
-#define GRPBASE_VALID 0x0001
-
-#define GRPMASK_BASE_MASK 0xfff0
-
-#define CSAB_COMPARE 0xff000000
-#define CSAB_BSW 0x00010000
-#define CSAB_MASK 0x0000ff00
-#define CSAB_RO 0x00000008
-#define CSAB_WAIT 0x00000007
-
-#define CSCD_COMPARE 0xfff00000
-#define CSCD_BSW 0x00010000
-#define CSCD_MASK 0x0000fff0
-#define CSCD_RO 0x00000008
-#define CSCD_WAIT 0x00000007
-
-#define PLLCR_PIXCLK_SEL 0x3800
-#define PLLCR_PIXCLK_SEL_DIV2 0x0000
-#define PLLCR_PIXCLK_SEL_DIV4 0x0800
-#define PLLCR_PIXCLK_SEL_DIV8 0x1000
-#define PLLCR_PIXCLK_SEL_DIV16 0x1800
-#define PLLCR_PIXCLK_SEL_DIV1_0 0x2000
-#define PLLCR_PIXCLK_SEL_DIV1_1 0x2800
-#define PLLCR_PIXCLK_SEL_DIV1_2 0x3000
-#define PLLCR_PIXCLK_SEL_DIV1_3 0x3800
-#define PLLCR_SYSCLK_SEL 0x0700
-#define PLLCR_SYSCLK_SEL_DIV2 0x0000
-#define PLLCR_SYSCLK_SEL_DIV4 0x0100
-#define PLLCR_SYSCLK_SEL_DIV8 0x0200
-#define PLLCR_SYSCLK_SEL_DIV16 0x0300
-#define PLLCR_SYSCLK_SEL_DIV1_0 0x0400
-#define PLLCR_SYSCLK_SEL_DIV1_1 0x0500
-#define PLLCR_SYSCLK_SEL_DIV1_2 0x0600
-#define PLLCR_SYSCLK_SEL_DIV1_3 0x0700
-#define PLLCR_CLKEN 0x0010
-#define PLLCR_DISPLL 0x0008
-
-#define PLLFSR_CLK32 0x8000
-#define PLLFSR_PROT 0x4000
-#define PLLFSR_QCNT 0x0f00
-#define PLLFSR_PCNT 0x00ff
-
-#define PCTLR_PC_EN 0x80
-#define PCTLR_STOP 0x40
-#define PCTLR_WIDTH 0x1f
-
-#define CXP_CC 0xc000
-#define CXP_CC_XLU 0x0000
-#define CXP_CC_BLACK 0x4000
-#define CXP_CC_INVERSE 0x8000
-#define CXP_CC_INVALID 0xc000
-#define CXP_MASK 0x03ff
-
-#define CYP_MASK 0x01ff
-
-#define CWCH_CW 0x1f00
-#define CWCH_CH 0x001f
-
-#define BLKC_BKEN 0x80
-#define BLKC_BD 0x7f
-
-#define LPICF_PBSIZ 0x06
-#define LPICF_PBSIZ_1 0x00
-#define LPICF_PBSIZ_2 0x02
-#define LPICF_PBSIZ_4 0x04
-#define LPICF_PBSIZ_INVALID 0x06
-
-#define LPOLCF_LCKPOL 0x08
-#define LPOLCF_FLMPOL 0x04
-#define LPOLCF_LPPOL 0x02
-#define LPOLCF_PIXPOL 0x01
-
-#define LACDRC_MASK 0x0f
-
-#define LPXCD_MASK 0x3f
-
-#define LCKCON_LCDC_EN 0x80
-#define LCKCON_LCDON 0x80
-#define LCKCON_DMA16 0x40
-#define LCKCON_WS 0x30
-#define LCKCON_WS_1 0x00
-#define LCKCON_WS_2 0x10
-#define LCKCON_WS_3 0x20
-#define LCKCON_WS_4 0x30
-#define LCKCON_DWIDTH 0x02
-#define LCKCON_PCDS 0x01
-
-#define LBAR_MASK 0x7f
-
-#define LPOSR_BOS 0x08
-#define LPOSR_POS 0x07
-
-#define LFRCM_XMOD 0xf0
-#define LFRCM_YMOD 0x0f
-
-#define LGPMR_PAL1 0x7000
-#define LGPMR_PAL0 0x0700
-#define LGPMR_PAL3 0x0070
-#define LGPMR_PAL2 0x0007
-
-#define RTCHMSR_HOURS 0x1f000000
-#define RTCHMSR_MINUTES 0x003f0000
-#define RTCHMSR_SECONDS 0x0000003f
-
-#define RTCCTL_38_4 0x0020
-#define RTCCTL_ENABLE 0x0080
-
-#define RTCINT_STOPWATCH 0x0001
-#define RTCINT_MINUTE 0x0002
-#define RTCINT_ALARM 0x0004
-#define RTCINT_DAY 0x0008
-#define RTCINT_SECOND 0x0010
-
-#define RTCSTPWTCH_MASK 0x003f
-
-#define TCTL_TEN 0x0001
-#define TCTL_TEN_ENABLE 0x0001
-#define TCTL_CLKSOURCE 0x000e
-#define TCTL_CLKSOURCE_STOP 0x0000
-#define TCTL_CLKSOURCE_SYSCLK 0x0002
-#define TCTL_CLKSOURCE_SYSCLK16 0x0004
-#define TCTL_CLKSOURCE_TIN 0x0006
-#define TCTL_CLKSOURCE_32KHZ4 0x0008
-#define TCTL_CLKSOURCE_32KHZ5 0x000a
-#define TCTL_CLKSOURCE_32KHZ6 0x000c
-#define TCTL_CLKSOURCE_32KHZ7 0x000e
-#define TCTL_IRQEN 0x0010
-#define TCTL_IRQEN_ENABLE 0x0010
-#define TCTL_OM 0x0020
-#define TCTL_OM_ACTIVELOW 0x0000
-#define TCTL_OM_TOGGLE 0x0020
-#define TCTL_CAPTURE 0x00c0
-#define TCTL_CAPTURE_NOINT 0x0000
-#define TCTL_CAPTURE_RISING 0x0040
-#define TCTL_CAPTURE_FALLING 0x0080
-#define TCTL_CAPTURE_BOTH 0x00c0
-#define TCTL_FRR 0x0100
-#define TCTL_FRR_RESTART 0x0000
-#define TCTL_FRR_FREERUN 0x0100
-
-#define TSTAT_COMP 0x0001
-#define TSTAT_CAPT 0x0002
-
-#define WCTLR_WDRST 0x0008
-#define WCTLR_LOCK 0x0004
-#define WCTLR_FI 0x0002
-#define WCTLR_WDEN 0x0001
-
-#define USTCNT_UART_EN 0x8000
-#define USTCNT_RX_EN 0x4000
-#define USTCNT_TX_EN 0x2000
-#define USTCNT_RX_CLK_CONT 0x1000
-#define USTCNT_PARITY_EN 0x0800
-#define USTCNT_ODD_EVEN 0x0400
-#define USTCNT_STOP_BITS 0x0200
-#define USTCNT_8_7 0x0100
-#define USTCNT_GPIO_DELTA_EN 0x0080
-#define USTCNT_CTS_DELTA_EN 0x0040
-#define USTCNT_RX_FULL_EN 0x0020
-#define USTCNT_RX_HALF_EN 0x0010
-#define USTCNT_RX_RDY_EN 0x0008
-#define USTCNT_TX_EMPTY_EN 0x0004
-#define USTCNT_TX_HALF_EN 0x0002
-#define USTCNT_TX_AVAIL_EN 0x0001
-
-#define UBAUD_GPIO_DELTA 0x8000
-#define UBAUD_GPIO 0x4000
-#define UBAUD_GPIO_DIR 0x2000
-#define UBAUD_GPIO_SRC 0x1000
-#define UBAUD_BAUD_SRC 0x0800
-#define UBAUD_DIVIDE 0x0700
-#define UBAUD_DIVIDE_1 0x0000
-#define UBAUD_DIVIDE_2 0x0100
-#define UBAUD_DIVIDE_4 0x0200
-#define UBAUD_DIVIDE_8 0x0300
-#define UBAUD_DIVIDE_16 0x0400
-#define UBAUD_DIVIDE_32 0x0500
-#define UBAUD_DIVIDE_64 0x0600
-#define UBAUD_DIVIDE_128 0x0700
-#define UBAUD_PRESCALER 0x00ff
-
-#define URX_FIFO_FULL 0x8000
-#define URX_FIFO_HALF 0x4000
-#define URX_DATA_READY 0x2000
-#define URX_OVRUN 0x0800
-#define URX_FRAME_ERROR 0x0400
-#define URX_BREAK 0x0200
-#define URX_PARITY_ERROR 0x0100
-
-#define UTX_FIFO_EMPTY 0x8000
-#define UTX_FIFO_HALF 0x4000
-#define UTX_TX_AVAIL 0x2000
-#define UTX_SEND_BREAK 0x1000
-#define UTX_IGNORE_CTS 0x0800
-#define UTX_CTS_STATUS 0x0200
-#define UTX_CTS_DELTA 0x0100
-
-#define UMISC_CLK_SRC 0x4000
-#define UMISC_FORCE_PERR 0x2000
-#define UMISC_LOOP 0x1000
-#define UMISC_RTS_CONT 0x0080
-#define UMISC_RTS 0x0040
-#define UMISC_IRDA_ENABLE 0x0020
-#define UMISC_IRDA_LOOP 0x0010
-
-#define SPIS_SPIS_IRQ 0x8000
-#define SPIS_IRQEN 0x4000
-#define SPIS_ENPOL 0x2000
-#define SPIS_DATA_RDY 0x1000
-#define SPIS_OVRWR 0x0800
-#define SPIS_PHA 0x0400
-#define SPIS_POL 0x0200
-#define SPIS_SPISEN 0x0100
-
-#define SPIM_CLOCK_COUNT 0x000f
-#define SPIM_POL 0x0010
-#define SPIM_POL_HIGH 0x0000
-#define SPIM_POL_LOW 0x0010
-#define SPIM_PHA 0x0020
-#define SPIM_PHA_NORMAL 0x0000
-#define SPIM_PHA_OPPOSITE 0x0020
-#define SPIM_IRQEN 0x0040
-#define SPIM_SPIMIRQ 0x0080
-#define SPIM_XCH 0x0100
-#define SPIM_XCH_IDLE 0x0000
-#define SPIM_XCH_INIT 0x0100
-#define SPIM_SPMEN 0x0200
-#define SPIM_SPMEN_DISABLE 0x0000
-#define SPIM_SPMEN_ENABLE 0x0200
-#define SPIM_RATE 0xe000
-#define SPIM_RATE_4 0x0000
-#define SPIM_RATE_8 0x2000
-#define SPIM_RATE_16 0x4000
-#define SPIM_RATE_32 0x6000
-#define SPIM_RATE_64 0x8000
-#define SPIM_RATE_128 0xa000
-#define SPIM_RATE_256 0xc000
-#define SPIM_RATE_512 0xe000
-
-#define PWMC_PWMIRQ 0x8000
-#define PWMC_IRQEN 0x4000
-#define PWMC_LOAD 0x0100
-#define PWMC_PIN 0x0080
-#define PWMC_POL 0x0040
-#define PWMC_PWMEN 0x0010
-#define PWMC_CLKSEL 0x0007
-
DEFINE_DEVICE_TYPE(MC68328, mc68328_device, "mc68328", "MC68328 DragonBall Integrated Processor")
-
void mc68328_device::internal_map(address_map &map)
{
map(0xfff000, 0xfff000).rw(FUNC(mc68328_device::scr_r), FUNC(mc68328_device::scr_w));
@@ -607,10 +289,10 @@ void mc68328_device::device_start()
{
m68000_device::device_start();
- m_gptimer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::timer1_hit),this));
- m_gptimer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::timer2_hit),this));
+ m_gptimer[0] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::timer_tick<0>),this));
+ m_gptimer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::timer_tick<1>),this));
m_rtc = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::rtc_tick),this));
- m_pwm = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::pwm_transition),this));
+ m_pwm = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mc68328_device::pwm_tick),this));
register_state_save();
}
@@ -931,7 +613,7 @@ void mc68328_device::maybe_start_timer(uint32_t new_enable)
}
template <int Timer>
-void mc68328_device::timer_compare_event()
+TIMER_CALLBACK_MEMBER( mc68328_device::timer_tick )
{
m_tcn[Timer] = m_tcmp[Timer];
m_tstat[Timer] |= TSTAT_COMP;
@@ -974,17 +656,7 @@ void mc68328_device::timer_compare_event()
}
}
-TIMER_CALLBACK_MEMBER( mc68328_device::timer1_hit )
-{
- timer_compare_event<0>();
-}
-
-TIMER_CALLBACK_MEMBER( mc68328_device::timer2_hit )
-{
- timer_compare_event<1>();
-}
-
-TIMER_CALLBACK_MEMBER( mc68328_device::pwm_transition )
+TIMER_CALLBACK_MEMBER( mc68328_device::pwm_tick )
{
if (m_pwmw >= m_pwmp || m_pwmw == 0 || m_pwmp == 0)
{
diff --git a/src/devices/machine/mc68328.h b/src/devices/machine/mc68328.h
index df0e1aa77eb..da28189db18 100644
--- a/src/devices/machine/mc68328.h
+++ b/src/devices/machine/mc68328.h
@@ -131,7 +131,329 @@ protected:
virtual void device_start() override;
virtual void device_reset() override;
-private:
+ enum : uint8_t
+ {
+ SCR_WDTH8 = 0x01,
+ SCR_DMAP = 0x04,
+ SCR_SO = 0x08,
+ SCR_BETEN = 0x10,
+ SCR_PRV = 0x20,
+ SCR_WPV = 0x40,
+ SCR_BETO = 0x80,
+
+ PCTLR_WIDTH = 0x1f,
+ PCTLR_STOP = 0x40,
+ PCTLR_PC_EN = 0x80,
+
+ BLKC_BD = 0x7f,
+ BLKC_BKEN = 0x80,
+
+ LPICF_PBSIZ = 0x06,
+ LPICF_PBSIZ_1 = 0x00,
+ LPICF_PBSIZ_2 = 0x02,
+ LPICF_PBSIZ_4 = 0x04,
+ LPICF_PBSIZ_INVALID = 0x06,
+
+ LPOLCF_PIXPOL = 0x01,
+ LPOLCF_LPPOL = 0x02,
+ LPOLCF_FLMPOL = 0x04,
+ LPOLCF_LCKPOL = 0x08,
+
+ LACDRC_MASK = 0x0f,
+
+ LPXCD_MASK = 0x3f,
+
+ LCKCON_PCDS = 0x01,
+ LCKCON_DWIDTH = 0x02,
+ LCKCON_WS = 0x30,
+ LCKCON_WS_1 = 0x00,
+ LCKCON_WS_2 = 0x10,
+ LCKCON_WS_3 = 0x20,
+ LCKCON_WS_4 = 0x30,
+ LCKCON_DMA16 = 0x40,
+ LCKCON_LCDON = 0x80,
+ LCKCON_LCDC_EN = 0x80,
+
+ LBAR_MASK = 0x7f,
+
+ LPOSR_POS = 0x07,
+ LPOSR_BOS = 0x08,
+
+ LFRCM_YMOD = 0x0f,
+ LFRCM_XMOD = 0xf0,
+ };
+
+ enum : uint16_t
+ {
+ GRPBASE_VALID = 0x0001,
+ GRPBASE_BASE_ADDR = 0xfff0,
+
+ GRPMASK_BASE_MASK = 0xfff0,
+
+ PLLCR_DISPLL = 0x0008,
+ PLLCR_CLKEN = 0x0010,
+ PLLCR_SYSCLK_SEL_DIV2 = 0x0000,
+ PLLCR_SYSCLK_SEL_DIV4 = 0x0100,
+ PLLCR_SYSCLK_SEL_DIV8 = 0x0200,
+ PLLCR_SYSCLK_SEL_DIV16 = 0x0300,
+ PLLCR_SYSCLK_SEL_DIV1_0 = 0x0400,
+ PLLCR_SYSCLK_SEL_DIV1_1 = 0x0500,
+ PLLCR_SYSCLK_SEL_DIV1_2 = 0x0600,
+ PLLCR_SYSCLK_SEL_DIV1_3 = 0x0700,
+ PLLCR_SYSCLK_SEL = 0x0700,
+ PLLCR_PIXCLK_SEL_DIV2 = 0x0000,
+ PLLCR_PIXCLK_SEL_DIV4 = 0x0800,
+ PLLCR_PIXCLK_SEL_DIV8 = 0x1000,
+ PLLCR_PIXCLK_SEL_DIV16 = 0x1800,
+ PLLCR_PIXCLK_SEL_DIV1_0 = 0x2000,
+ PLLCR_PIXCLK_SEL_DIV1_1 = 0x2800,
+ PLLCR_PIXCLK_SEL_DIV1_2 = 0x3000,
+ PLLCR_PIXCLK_SEL_DIV1_3 = 0x3800,
+ PLLCR_PIXCLK_SEL = 0x3800,
+
+ PLLFSR_PCNT = 0x00ff,
+ PLLFSR_QCNT = 0x0f00,
+ PLLFSR_PROT = 0x4000,
+ PLLFSR_CLK32 = 0x8000,
+
+ ICR_POL6 = 0x0100,
+ ICR_POL3 = 0x0200,
+ ICR_POL2 = 0x0400,
+ ICR_POL1 = 0x0800,
+ ICR_ET6 = 0x1000,
+ ICR_ET3 = 0x2000,
+ ICR_ET2 = 0x4000,
+ ICR_ET1 = 0x8000,
+
+ PWMC_CLKSEL = 0x0007,
+ PWMC_PWMEN = 0x0010,
+ PWMC_POL = 0x0040,
+ PWMC_PIN = 0x0080,
+ PWMC_LOAD = 0x0100,
+ PWMC_IRQEN = 0x4000,
+ PWMC_PWMIRQ = 0x8000,
+
+ TCTL_TEN = 0x0001,
+ TCTL_TEN_ENABLE = 0x0001,
+ TCTL_CLKSOURCE = 0x000e,
+ TCTL_CLKSOURCE_STOP = 0x0000,
+ TCTL_CLKSOURCE_SYSCLK = 0x0002,
+ TCTL_CLKSOURCE_SYSCLK16 = 0x0004,
+ TCTL_CLKSOURCE_TIN = 0x0006,
+ TCTL_CLKSOURCE_32KHZ4 = 0x0008,
+ TCTL_CLKSOURCE_32KHZ5 = 0x000a,
+ TCTL_CLKSOURCE_32KHZ6 = 0x000c,
+ TCTL_CLKSOURCE_32KHZ7 = 0x000e,
+ TCTL_IRQEN = 0x0010,
+ TCTL_IRQEN_ENABLE = 0x0010,
+ TCTL_OM = 0x0020,
+ TCTL_OM_ACTIVELOW = 0x0000,
+ TCTL_OM_TOGGLE = 0x0020,
+ TCTL_CAPTURE = 0x00c0,
+ TCTL_CAPTURE_NOINT = 0x0000,
+ TCTL_CAPTURE_RISING = 0x0040,
+ TCTL_CAPTURE_FALLING = 0x0080,
+ TCTL_CAPTURE_BOTH = 0x00c0,
+ TCTL_FRR = 0x0100,
+ TCTL_FRR_RESTART = 0x0000,
+ TCTL_FRR_FREERUN = 0x0100,
+
+ TSTAT_COMP = 0x0001,
+ TSTAT_CAPT = 0x0002,
+
+ WCTLR_WDRST = 0x0008,
+ WCTLR_LOCK = 0x0004,
+ WCTLR_FI = 0x0002,
+ WCTLR_WDEN = 0x0001,
+
+ SPIS_SPISEN = 0x0100,
+ SPIS_POL = 0x0200,
+ SPIS_PHA = 0x0400,
+ SPIS_OVRWR = 0x0800,
+ SPIS_DATA_RDY = 0x1000,
+ SPIS_ENPOL = 0x2000,
+ SPIS_IRQEN = 0x4000,
+ SPIS_SPIS_IRQ = 0x8000,
+
+ SPIM_CLOCK_COUNT = 0x000f,
+ SPIM_POL = 0x0010,
+ SPIM_POL_HIGH = 0x0000,
+ SPIM_POL_LOW = 0x0010,
+ SPIM_PHA = 0x0020,
+ SPIM_PHA_NORMAL = 0x0000,
+ SPIM_PHA_OPPOSITE = 0x0020,
+ SPIM_IRQEN = 0x0040,
+ SPIM_SPIMIRQ = 0x0080,
+ SPIM_XCH = 0x0100,
+ SPIM_XCH_IDLE = 0x0000,
+ SPIM_XCH_INIT = 0x0100,
+ SPIM_SPMEN = 0x0200,
+ SPIM_SPMEN_DISABLE = 0x0000,
+ SPIM_SPMEN_ENABLE = 0x0200,
+ SPIM_RATE = 0xe000,
+ SPIM_RATE_4 = 0x0000,
+ SPIM_RATE_8 = 0x2000,
+ SPIM_RATE_16 = 0x4000,
+ SPIM_RATE_32 = 0x6000,
+ SPIM_RATE_64 = 0x8000,
+ SPIM_RATE_128 = 0xa000,
+ SPIM_RATE_256 = 0xc000,
+ SPIM_RATE_512 = 0xe000,
+
+ USTCNT_TX_AVAIL_EN = 0x0001,
+ USTCNT_TX_HALF_EN = 0x0002,
+ USTCNT_TX_EMPTY_EN = 0x0004,
+ USTCNT_RX_RDY_EN = 0x0008,
+ USTCNT_RX_HALF_EN = 0x0010,
+ USTCNT_RX_FULL_EN = 0x0020,
+ USTCNT_CTS_DELTA_EN = 0x0040,
+ USTCNT_GPIO_DELTA_EN = 0x0080,
+ USTCNT_8_7 = 0x0100,
+ USTCNT_STOP_BITS = 0x0200,
+ USTCNT_ODD_EVEN = 0x0400,
+ USTCNT_PARITY_EN = 0x0800,
+ USTCNT_RX_CLK_CONT = 0x1000,
+ USTCNT_TX_EN = 0x2000,
+ USTCNT_RX_EN = 0x4000,
+ USTCNT_UART_EN = 0x8000,
+
+ UBAUD_PRESCALER = 0x00ff,
+ UBAUD_DIVIDE = 0x0700,
+ UBAUD_DIVIDE_1 = 0x0000,
+ UBAUD_DIVIDE_2 = 0x0100,
+ UBAUD_DIVIDE_4 = 0x0200,
+ UBAUD_DIVIDE_8 = 0x0300,
+ UBAUD_DIVIDE_16 = 0x0400,
+ UBAUD_DIVIDE_32 = 0x0500,
+ UBAUD_DIVIDE_64 = 0x0600,
+ UBAUD_DIVIDE_128 = 0x0700,
+ UBAUD_BAUD_SRC = 0x0800,
+ UBAUD_GPIO_SRC = 0x1000,
+ UBAUD_GPIO_DIR = 0x2000,
+ UBAUD_GPIO = 0x4000,
+ UBAUD_GPIO_DELTA = 0x8000,
+
+ URX_PARITY_ERROR = 0x0100,
+ URX_BREAK = 0x0200,
+ URX_FRAME_ERROR = 0x0400,
+ URX_OVRUN = 0x0800,
+ URX_DATA_READY = 0x2000,
+ URX_FIFO_HALF = 0x4000,
+ URX_FIFO_FULL = 0x8000,
+
+ UTX_CTS_DELTA = 0x0100,
+ UTX_CTS_STATUS = 0x0200,
+ UTX_IGNORE_CTS = 0x0800,
+ UTX_SEND_BREAK = 0x1000,
+ UTX_TX_AVAIL = 0x2000,
+ UTX_FIFO_HALF = 0x4000,
+ UTX_FIFO_EMPTY = 0x8000,
+
+ UMISC_IRDA_LOOP = 0x0010,
+ UMISC_IRDA_ENABLE = 0x0020,
+ UMISC_RTS = 0x0040,
+ UMISC_RTS_CONT = 0x0080,
+ UMISC_LOOP = 0x1000,
+ UMISC_FORCE_PERR = 0x2000,
+ UMISC_CLK_SRC = 0x4000,
+
+ CXP_MASK = 0x03ff,
+ CXP_CC = 0xc000,
+ CXP_CC_XLU = 0x0000,
+ CXP_CC_BLACK = 0x4000,
+ CXP_CC_INVERSE = 0x8000,
+ CXP_CC_INVALID = 0xc000,
+
+ CYP_MASK = 0x01ff,
+
+ CWCH_CH = 0x001f,
+ CWCH_CW = 0x1f00,
+
+ LGPMR_PAL2 = 0x0007,
+ LGPMR_PAL3 = 0x0070,
+ LGPMR_PAL0 = 0x0700,
+ LGPMR_PAL1 = 0x7000,
+
+ RTCCTL_38_4 = 0x0020,
+ RTCCTL_ENABLE = 0x0080,
+
+ RTCINT_STOPWATCH = 0x0001,
+ RTCINT_MINUTE = 0x0002,
+ RTCINT_ALARM = 0x0004,
+ RTCINT_DAY = 0x0008,
+ RTCINT_SECOND = 0x0010,
+
+ RTCSTPWTCH_MASK = 0x003f,
+ };
+
+ enum : uint32_t
+ {
+ CSAB_WAIT = 0x00000007,
+ CSAB_RO = 0x00000008,
+ CSAB_MASK = 0x0000ff00,
+ CSAB_BSW = 0x00010000,
+ CSAB_COMPARE = 0xff000000,
+
+ CSCD_WAIT = 0x00000007,
+ CSCD_RO = 0x00000008,
+ CSCD_MASK = 0x0000fff0,
+ CSCD_BSW = 0x00010000,
+ CSCD_COMPARE = 0xfff00000,
+
+ INT_SPIM = 0x00000001,
+ INT_TIMER2 = 0x00000002,
+ INT_UART = 0x00000004,
+ INT_WDT = 0x00000008,
+ INT_RTC = 0x00000010,
+ INT_RESERVED = 0x00000020,
+ INT_KB = 0x00000040,
+ INT_PWM = 0x00000080,
+ INT_INT0 = 0x00000100,
+ INT_INT1 = 0x00000200,
+ INT_INT2 = 0x00000400,
+ INT_INT3 = 0x00000800,
+ INT_INT4 = 0x00001000,
+ INT_INT5 = 0x00002000,
+ INT_INT6 = 0x00004000,
+ INT_INT7 = 0x00008000,
+ INT_KBDINTS = 0x0000ff00,
+ INT_IRQ1 = 0x00010000,
+ INT_IRQ2 = 0x00020000,
+ INT_IRQ3 = 0x00040000,
+ INT_IRQ6 = 0x00080000,
+ INT_PEN = 0x00100000,
+ INT_SPIS = 0x00200000,
+ INT_TIMER1 = 0x00400000,
+ INT_IRQ7 = 0x00800000,
+
+ INT_M68K_LINE1 = INT_IRQ1,
+ INT_M68K_LINE2 = INT_IRQ2,
+ INT_M68K_LINE3 = INT_IRQ3,
+ INT_M68K_LINE4 = INT_INT0 | INT_INT1 | INT_INT2 | INT_INT3 | INT_INT4 | INT_INT5 | INT_INT6 | INT_INT7 |
+ INT_PWM | INT_KB | INT_RTC | INT_WDT | INT_UART | INT_TIMER2 | INT_SPIM,
+ INT_M68K_LINE5 = INT_PEN,
+ INT_M68K_LINE6 = INT_IRQ6 | INT_TIMER1 | INT_SPIS,
+ INT_M68K_LINE7 = INT_IRQ7,
+ INT_M68K_LINE67 = INT_M68K_LINE6 | INT_M68K_LINE7,
+ INT_M68K_LINE567 = INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7,
+ INT_M68K_LINE4567 = INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7,
+ INT_M68K_LINE34567 = INT_M68K_LINE3 | INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7,
+ INT_M68K_LINE234567 = INT_M68K_LINE2 | INT_M68K_LINE3 | INT_M68K_LINE4 | INT_M68K_LINE5 | INT_M68K_LINE6 | INT_M68K_LINE7,
+
+ INT_IRQ1_SHIFT = 0x00000001,
+ INT_IRQ2_SHIFT = 0x00000002,
+ INT_IRQ3_SHIFT = 0x00000004,
+ INT_IRQ6_SHIFT = 0x00000008,
+ INT_PEN_SHIFT = 0x00000010,
+ INT_SPIS_SHIFT = 0x00000020,
+ INT_TIMER1_SHIFT = 0x00000040,
+ INT_IRQ7_SHIFT = 0x00000080,
+
+ RTCHMSR_SECONDS = 0x0000003f,
+ RTCHMSR_MINUTES = 0x003f0000,
+ RTCHMSR_HOURS = 0x1f000000,
+ };
+
void scr_w(uint8_t data); // 0x000
void grpbasea_w(uint16_t data); // 0x100
@@ -537,13 +859,11 @@ private:
template<int Timer> uint32_t get_timer_frequency();
template<int Timer> void maybe_start_timer(uint32_t new_enable);
- template<int Timer> void timer_compare_event();
void register_state_save();
- TIMER_CALLBACK_MEMBER(timer1_hit);
- TIMER_CALLBACK_MEMBER(timer2_hit);
- TIMER_CALLBACK_MEMBER(pwm_transition);
+ template<int Timer> TIMER_CALLBACK_MEMBER(timer_tick);
+ TIMER_CALLBACK_MEMBER(pwm_tick);
TIMER_CALLBACK_MEMBER(rtc_tick);
emu_timer *m_gptimer[2];