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author Olivier Galibert <galibert@pobox.com>2017-12-15 12:45:49 +0100
committer Olivier Galibert <galibert@pobox.com>2017-12-16 13:22:21 +0100
commit77829f86719aa73ec3eddf08a9c7dfa71c89f5f3 (patch)
treefadd5f17e77cbe4c01646dcc326e665bb21df4ff /src/devices/machine/pci-ide.cpp
parent00c799de12624a06d243ba9c36efdfbb33c36315 (diff)
ide: deambiguate cs access between 16 and 32 bits [O. Galibert]
Diffstat (limited to 'src/devices/machine/pci-ide.cpp')
-rw-r--r--src/devices/machine/pci-ide.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/devices/machine/pci-ide.cpp b/src/devices/machine/pci-ide.cpp
index 216f67ac5fa..4ff36f856d1 100644
--- a/src/devices/machine/pci-ide.cpp
+++ b/src/devices/machine/pci-ide.cpp
@@ -27,7 +27,7 @@ DEVICE_ADDRESS_MAP_START(config_map, 32, ide_pci_device)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(chan1_data_command_map, 32, ide_pci_device)
- AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read_cs0, write_cs0)
+ AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read32_cs0, write32_cs0)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(chan1_control_map, 32, ide_pci_device)
@@ -35,7 +35,7 @@ DEVICE_ADDRESS_MAP_START(chan1_control_map, 32, ide_pci_device)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(chan2_data_command_map, 32, ide_pci_device)
- AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide2", bus_master_ide_controller_device, read_cs0, write_cs0)
+ AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide2", bus_master_ide_controller_device, read32_cs0, write32_cs0)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(chan2_control_map, 32, ide_pci_device)
@@ -117,7 +117,7 @@ READ32_MEMBER(ide_pci_device::ide_read_cs1)
{
// PCI offset starts at 0x3f4, idectrl expects 0x3f0
uint32_t data;
- data = m_ide->read_cs1(space, 1, mem_mask);
+ data = m_ide->read32_cs1(space, 1, mem_mask);
if (0)
logerror("%s:ide_read_cs1 offset=%08X data=%08X mask=%08X\n", machine().describe_context(), offset, data, mem_mask);
return data;
@@ -126,21 +126,21 @@ READ32_MEMBER(ide_pci_device::ide_read_cs1)
WRITE32_MEMBER(ide_pci_device::ide_write_cs1)
{
// PCI offset starts at 0x3f4, idectrl expects 0x3f0
- m_ide->write_cs1(space, 1, data, mem_mask);
+ m_ide->write32_cs1(space, 1, data, mem_mask);
}
READ32_MEMBER(ide_pci_device::ide2_read_cs1)
{
// PCI offset starts at 0x374, idectrl expects 0x370
uint32_t data;
- data = m_ide2->read_cs1(space, 1, mem_mask);
+ data = m_ide2->read32_cs1(space, 1, mem_mask);
return data;
}
WRITE32_MEMBER(ide_pci_device::ide2_write_cs1)
{
// PCI offset starts at 0x374, idectrl expects 0x370
- m_ide2->write_cs1(space, 1, data, mem_mask);
+ m_ide2->write32_cs1(space, 1, data, mem_mask);
}
WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)