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author Olivier Galibert <galibert@pobox.com>2022-12-14 22:03:56 +0100
committer Olivier Galibert <galibert@pobox.com>2023-02-22 11:29:45 +0100
commit74971c2f530c0996dbb8112f227f4cfcaf4b0045 (patch)
treeed1af70fedce7bdae59d2364415db53dc7d4f5f1 /src/devices/machine/68307sim.cpp
parentb733fd4b4324ab269ad603d8a12d17bacf7fcd93 (diff)
m68000: New implementation, generated from the micro/nanocode
Diffstat (limited to 'src/devices/machine/68307sim.cpp')
-rw-r--r--src/devices/machine/68307sim.cpp20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/devices/machine/68307sim.cpp b/src/devices/machine/68307sim.cpp
index a62a2911ab4..0f592662d50 100644
--- a/src/devices/machine/68307sim.cpp
+++ b/src/devices/machine/68307sim.cpp
@@ -54,7 +54,7 @@ uint16_t m68307_cpu_device::m68307_internal_sim_r(address_space &space, offs_t o
case m68307SIM_OR3: return sim.m_or[3];
default:
- logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", m_ppc, offset*2, mem_mask);
+ logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", m_ipc, offset*2, mem_mask);
return 0xff;
}
@@ -70,12 +70,12 @@ void m68307_cpu_device::m68307_internal_sim_w(address_space &space, offs_t offse
switch (offset<<1)
{
case m68307SIM_PACNT:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", m_ipc, offset*2,data,mem_mask);
sim.write_pacnt(data,mem_mask);
break;
case m68307SIM_PADDR:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", m_ipc, offset*2,data,mem_mask);
sim.write_paddr(data,mem_mask);
break;
@@ -84,12 +84,12 @@ void m68307_cpu_device::m68307_internal_sim_w(address_space &space, offs_t offse
break;
case m68307SIM_PBCNT:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", m_ipc, offset*2,data,mem_mask);
sim.write_pbcnt(data,mem_mask);
break;
case m68307SIM_PBDDR:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", m_ipc, offset*2,data,mem_mask);
sim.write_pbddr(data,mem_mask);
break;
@@ -99,22 +99,22 @@ void m68307_cpu_device::m68307_internal_sim_w(address_space &space, offs_t offse
case m68307SIM_LICR1:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", m_ipc, offset*2,data,mem_mask);
sim.write_licr1(this,data,mem_mask);
break;
case m68307SIM_LICR2:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", m_ipc, offset*2,data,mem_mask);
sim.write_licr2(this,data,mem_mask);
break;
case m68307SIM_PICR:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", m_ipc, offset*2,data,mem_mask);
sim.write_picr(this,data,mem_mask);
break;
case m68307SIM_PIVR:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", m_ipc, offset*2,data,mem_mask);
sim.write_pivr(this,data,mem_mask);
break;
@@ -146,7 +146,7 @@ void m68307_cpu_device::m68307_internal_sim_w(address_space &space, offs_t offse
default :
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", m_ppc, offset*2,data,mem_mask);
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", m_ipc, offset*2,data,mem_mask);
break;
}
}