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author Vas Crabb <vas@vastheman.com>2020-06-25 11:17:10 +1000
committer Vas Crabb <vas@vastheman.com>2020-06-25 11:17:10 +1000
commitdc789c4d9db00884232398be87ef86b4a99feab5 (patch)
tree3efac218fc89065c72d8d14324fe7ba0d9cd31a8 /src/devices/cpu
parent586144f23299760753937f5ec61074909458b1cd (diff)
parentf172d7065a7b1ac98760b68fddebfa17598d3383 (diff)
Merge branch 'release0222' into mainline-master
Diffstat (limited to 'src/devices/cpu')
-rw-r--r--src/devices/cpu/i960/i960.cpp11
1 files changed, 8 insertions, 3 deletions
diff --git a/src/devices/cpu/i960/i960.cpp b/src/devices/cpu/i960/i960.cpp
index 9db9d6ab095..ae17f211aba 100644
--- a/src/devices/cpu/i960/i960.cpp
+++ b/src/devices/cpu/i960/i960.cpp
@@ -92,10 +92,11 @@ void i960_cpu_device::send_iac(uint32_t adr)
switch(iac[0]>>24) {
case 0x40: // generate irq
+ logerror("I960: %x: IAC %08x %08x %08x %08x (generate IRQ)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
break;
case 0x41: // test for pending interrupts
- // check_irqs() seems to take care of this
- // though it may not be entirely accurate
+ logerror("I960: %x: IAC %08x %08x %08x %08x (test for pending interrupts)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
+ // check_irqs() seems to take care of this though it may not be entirely accurate
check_irqs();
break;
case 0x80: // store SAT & PRCB in memory
@@ -103,14 +104,18 @@ void i960_cpu_device::send_iac(uint32_t adr)
m_program.write_dword(iac[1]+4, m_PRCB);
break;
case 0x89: // invalidate internal instruction cache
+ logerror("I960: %x: IAC %08x %08x %08x %08x (invalidate internal instruction cache)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
// we do not emulate the instruction cache, so this is safe to ignore
break;
- case 0x8F: // enable/disable breakpoints
+ case 0x8f: // enable/disable breakpoints
+ logerror("I960: %x: IAC %08x %08x %08x %08x (enable/disable breakpoints)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
// processor breakpoints are not emulated, safe to ignore
break;
case 0x91: // stop processor
+ logerror("I960: %x: IAC %08x %08x %08x %08x (stop processor)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
break;
case 0x92: // continue initialization
+ logerror("I960: %x: IAC %08x %08x %08x %08x (continue initialization)\n", m_PIP, iac[0], iac[1], iac[2], iac[3]);
break;
case 0x93: // reinit
m_SAT = iac[1];