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author Vas Crabb <vas@vastheman.com>2018-06-24 19:04:53 +1000
committer Vas Crabb <vas@vastheman.com>2018-06-24 19:04:53 +1000
commit90d7b40e62b695a8f74158a64c69db15dcc94d37 (patch)
tree81ccafe933878fa3ef7389f91d1e6f0d00296d37 /src/devices/cpu
parent2578a9ddcb8dbcf6b05e01cf7b5fb7d32cd14d54 (diff)
srcclean and other cleanup (nw)
Diffstat (limited to 'src/devices/cpu')
-rw-r--r--src/devices/cpu/mips/mips3.cpp46
-rw-r--r--src/devices/cpu/mips/mips3.h104
-rw-r--r--src/devices/cpu/mips/mips3dsm.cpp30
3 files changed, 90 insertions, 90 deletions
diff --git a/src/devices/cpu/mips/mips3.cpp b/src/devices/cpu/mips/mips3.cpp
index e78fc478a33..f48682fd20a 100644
--- a/src/devices/cpu/mips/mips3.cpp
+++ b/src/devices/cpu/mips/mips3.cpp
@@ -2516,20 +2516,20 @@ void mips3_device::handle_cop2(uint32_t op)
switch (RSREG)
{
- case 0x00: /* MFCz */ if (RTREG) RTVAL64 = (int32_t)get_cop2_reg(RDREG); break;
- case 0x01: /* DMFCz */ if (RTREG) RTVAL64 = get_cop2_reg(RDREG); break;
- case 0x02: /* CFCz */ if (RTREG) RTVAL64 = (int32_t)get_cop2_creg(RDREG); break;
- case 0x04: /* MTCz */ set_cop2_reg(RDREG, RTVAL32); break;
- case 0x05: /* DMTCz */ set_cop2_reg(RDREG, RTVAL64); break;
- case 0x06: /* CTCz */ set_cop2_creg(RDREG, RTVAL32); break;
+ case 0x00: /* MFCz */ if (RTREG) RTVAL64 = (int32_t)get_cop2_reg(RDREG); break;
+ case 0x01: /* DMFCz */ if (RTREG) RTVAL64 = get_cop2_reg(RDREG); break;
+ case 0x02: /* CFCz */ if (RTREG) RTVAL64 = (int32_t)get_cop2_creg(RDREG); break;
+ case 0x04: /* MTCz */ set_cop2_reg(RDREG, RTVAL32); break;
+ case 0x05: /* DMTCz */ set_cop2_reg(RDREG, RTVAL64); break;
+ case 0x06: /* CTCz */ set_cop2_creg(RDREG, RTVAL32); break;
case 0x08: /* BC */
switch (RTREG)
{
- case 0x00: /* BCzF */ if (!m_cf[2]) ADDPC(SIMMVAL); break;
- case 0x01: /* BCzF */ if (m_cf[2]) ADDPC(SIMMVAL); break;
- case 0x02: /* BCzFL */ invalid_instruction(op); break;
- case 0x03: /* BCzTL */ invalid_instruction(op); break;
- default: invalid_instruction(op); break;
+ case 0x00: /* BCzF */ if (!m_cf[2]) ADDPC(SIMMVAL); break;
+ case 0x01: /* BCzF */ if (m_cf[2]) ADDPC(SIMMVAL); break;
+ case 0x02: /* BCzFL */ invalid_instruction(op); break;
+ case 0x03: /* BCzTL */ invalid_instruction(op); break;
+ default: invalid_instruction(op); break;
}
break;
default: handle_extra_cop2(op); break;
@@ -2559,21 +2559,21 @@ void mips3_device::handle_regimm(uint32_t op)
{
switch (RTREG)
{
- case 0x00: /* BLTZ */ if ((int64_t)RSVAL64 < 0) ADDPC(SIMMVAL); break;
- case 0x01: /* BGEZ */ if ((int64_t)RSVAL64 >= 0) ADDPC(SIMMVAL); break;
- case 0x02: /* BLTZL */ if ((int64_t)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
- case 0x03: /* BGEZL */ if ((int64_t)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
- case 0x08: /* TGEI */ if ((int64_t)RSVAL64 >= SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
- case 0x09: /* TGEIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
- case 0x0a: /* TLTI */ if ((int64_t)RSVAL64 < SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
- case 0x0b: /* TLTIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
- case 0x0c: /* TEQI */ if (RSVAL64 == UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
- case 0x0e: /* TNEI */ if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
+ case 0x00: /* BLTZ */ if ((int64_t)RSVAL64 < 0) ADDPC(SIMMVAL); break;
+ case 0x01: /* BGEZ */ if ((int64_t)RSVAL64 >= 0) ADDPC(SIMMVAL); break;
+ case 0x02: /* BLTZL */ if ((int64_t)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
+ case 0x03: /* BGEZL */ if ((int64_t)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
+ case 0x08: /* TGEI */ if ((int64_t)RSVAL64 >= SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
+ case 0x09: /* TGEIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
+ case 0x0a: /* TLTI */ if ((int64_t)RSVAL64 < SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
+ case 0x0b: /* TLTIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
+ case 0x0c: /* TEQI */ if (RSVAL64 == UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
+ case 0x0e: /* TNEI */ if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x10: /* BLTZAL */ m_core->r[31] = (int32_t)(m_core->pc + 4); if ((int64_t)RSVAL64 < 0) ADDPC(SIMMVAL); break;
case 0x11: /* BGEZAL */ m_core->r[31] = (int32_t)(m_core->pc + 4); if ((int64_t)RSVAL64 >= 0) ADDPC(SIMMVAL); break;
case 0x12: /* BLTZALL */ m_core->r[31] = (int32_t)(m_core->pc + 4); if ((int64_t)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
case 0x13: /* BGEZALL */ m_core->r[31] = (int32_t)(m_core->pc + 4); if ((int64_t)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
- default: /* ??? */ handle_extra_regimm(op); break;
+ default: /* ??? */ handle_extra_regimm(op); break;
}
}
@@ -2696,7 +2696,7 @@ void mips3_device::handle_special(uint32_t op)
case 0x25: /* OR */ if (RDREG) RDVAL64 = RSVAL64 | RTVAL64; break;
case 0x26: /* XOR */ if (RDREG) RDVAL64 = RSVAL64 ^ RTVAL64; break;
case 0x27: /* NOR */ if (RDREG) RDVAL64 = ~(RSVAL64 | RTVAL64); break;
- case 0x2a: /* SLT */ if (RDREG) RDVAL64 = (int64_t)RSVAL64 < (int64_t)RTVAL64; break;
+ case 0x2a: /* SLT */ if (RDREG) RDVAL64 = (int64_t)RSVAL64 < (int64_t)RTVAL64; break;
case 0x2b: /* SLTU */ if (RDREG) RDVAL64 = (uint64_t)RSVAL64 < (uint64_t)RTVAL64; break;
case 0x2c: /* DADD */
if (ENABLE_OVERFLOWS && RSVAL64 > ~RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
diff --git a/src/devices/cpu/mips/mips3.h b/src/devices/cpu/mips/mips3.h
index c0251c31890..1e55cd81478 100644
--- a/src/devices/cpu/mips/mips3.h
+++ b/src/devices/cpu/mips/mips3.h
@@ -312,77 +312,77 @@ private:
struct internal_mips3_state
{
/* core registers */
- uint32_t pc;
- int icount;
- uint64_t r[35];
+ uint32_t pc;
+ int icount;
+ uint64_t r[35];
/* upper 64 bits of 128-bit GPRs (R5900 only) */
- uint64_t rh[35];
+ uint64_t rh[35];
/* COP registers */
- uint64_t cpr[3][32];
- uint64_t ccr[3][32];
- uint32_t llbit;
+ uint64_t cpr[3][32];
+ uint64_t ccr[3][32];
+ uint32_t llbit;
/* VU0 registers (R5900 only) */
- float vfr[32][4];
- uint32_t vcr[32];
+ float vfr[32][4];
+ uint32_t vcr[32];
- uint32_t mode; /* current global mode */
+ uint32_t mode; /* current global mode */
/* parameters for subroutines */
- uint64_t numcycles; /* return value from gettotalcycles */
- const char * format; /* format string for print_debug */
- uint32_t arg0; /* print_debug argument 1 */
- uint32_t arg1; /* print_debug argument 2 */
-
- uint64_t count_zero_time;
- uint32_t compare_armed;
- uint32_t jmpdest; /* destination jump target */
+ uint64_t numcycles; /* return value from gettotalcycles */
+ const char * format; /* format string for print_debug */
+ uint32_t arg0; /* print_debug argument 1 */
+ uint32_t arg1; /* print_debug argument 2 */
+
+ uint64_t count_zero_time;
+ uint32_t compare_armed;
+ uint32_t jmpdest; /* destination jump target */
};
address_space_config m_program_config;
- mips3_flavor m_flavor;
+ mips3_flavor m_flavor;
/* core state */
internal_mips3_state *m_core;
/* internal stuff */
- uint32_t m_ppc;
- uint32_t m_nextpc;
- uint32_t m_pcbase;
- uint8_t m_cf[4][8];
- bool m_delayslot;
- int m_op;
- int m_interrupt_cycles;
- uint32_t m_ll_value;
- uint64_t m_lld_value;
- uint32_t m_badcop_value;
+ uint32_t m_ppc;
+ uint32_t m_nextpc;
+ uint32_t m_pcbase;
+ uint8_t m_cf[4][8];
+ bool m_delayslot;
+ int m_op;
+ int m_interrupt_cycles;
+ uint32_t m_ll_value;
+ uint64_t m_lld_value;
+ uint32_t m_badcop_value;
/* endian-dependent load/store */
typedef void (mips3_device::*loadstore_func)(uint32_t op);
- loadstore_func m_lwl;
- loadstore_func m_lwr;
- loadstore_func m_swl;
- loadstore_func m_swr;
- loadstore_func m_ldl;
- loadstore_func m_ldr;
- loadstore_func m_sdl;
- loadstore_func m_sdr;
-
- address_space * m_program;
+ loadstore_func m_lwl;
+ loadstore_func m_lwr;
+ loadstore_func m_swl;
+ loadstore_func m_swr;
+ loadstore_func m_ldl;
+ loadstore_func m_ldr;
+ loadstore_func m_sdl;
+ loadstore_func m_sdr;
+
+ address_space * m_program;
std::function<u32 (offs_t)> m_pr32;
std::function<const void * (offs_t)> m_prptr;
- uint32_t c_system_clock;
- uint32_t m_cpu_clock;
+ uint32_t c_system_clock;
+ uint32_t m_cpu_clock;
emu_timer * m_compare_int_timer;
/* derived info based on flavor */
- uint32_t m_pfnmask;
- uint8_t m_tlbentries;
+ uint32_t m_pfnmask;
+ uint8_t m_tlbentries;
/* memory accesses */
- bool m_bigendian;
+ bool m_bigendian;
uint32_t m_byte_xor;
uint32_t m_word_xor;
data_accessors m_memory;
@@ -398,16 +398,16 @@ private:
uint32_t m_fastram_select;
struct
{
- offs_t start; /* start of the RAM block */
- offs_t end; /* end of the RAM block */
- bool readonly; /* true if read-only */
- void * base; /* base in memory where the RAM lives */
- uint8_t * offset_base8; /* base in memory where the RAM lives, 8-bit pointer, with the start offset pre-applied */
- uint16_t * offset_base16; /* base in memory where the RAM lives, 16-bit pointer, with the start offset pre-applied */
- uint32_t * offset_base32; /* base in memory where the RAM lives, 32-bit pointer, with the start offset pre-applied */
+ offs_t start; /* start of the RAM block */
+ offs_t end; /* end of the RAM block */
+ bool readonly; /* true if read-only */
+ void * base; /* base in memory where the RAM lives */
+ uint8_t * offset_base8; /* base in memory where the RAM lives, 8-bit pointer, with the start offset pre-applied */
+ uint16_t * offset_base16; /* base in memory where the RAM lives, 16-bit pointer, with the start offset pre-applied */
+ uint32_t * offset_base32; /* base in memory where the RAM lives, 32-bit pointer, with the start offset pre-applied */
} m_fastram[MIPS3_MAX_FASTRAM];
- uint32_t m_debugger_temp;
+ uint32_t m_debugger_temp;
/* core state */
drc_cache m_cache; /* pointer to the DRC code cache */
diff --git a/src/devices/cpu/mips/mips3dsm.cpp b/src/devices/cpu/mips/mips3dsm.cpp
index eba85fa25ad..0ee0bd36058 100644
--- a/src/devices/cpu/mips/mips3dsm.cpp
+++ b/src/devices/cpu/mips/mips3dsm.cpp
@@ -428,19 +428,19 @@ uint32_t ee_disassembler::dasm_extra_cop2(uint32_t pc, uint32_t op, std::ostream
" ", "w ", "z ", "zw ", "y ", "yw ", "yz ", "yzw ",
"x ", "xw ", "xz ", "xzw ", "xy ", "xyw ", "xyz ", "xyzw"
};
- const char* dest_strings_with_comma[16] =
- {
- ",", "w,", "z,", "zw,", "y,", "yw,", "yz,", "yzw,",
- "x,", "xw,", "xz,", "xzw,", "xy,", "xyw,", "xyz,", "xyzw,"
- };
- const char* bc_strings[4] = { "x", "y", "z", "w" };
- const char* bc_strings_with_comma[4] = { "x,", "y,", "z,", "w," };
+ const char* dest_strings_with_comma[16] =
+ {
+ ",", "w,", "z,", "zw,", "y,", "yw,", "yz,", "yzw,",
+ "x,", "xw,", "xz,", "xzw,", "xy,", "xyw,", "xyz,", "xyzw,"
+ };
+ const char* bc_strings[4] = { "x", "y", "z", "w" };
+ const char* bc_strings_with_comma[4] = { "x,", "y,", "z,", "w," };
const char* dest = dest_strings[(op >> 21) & 15];
- const char* destc = dest_strings_with_comma[(op >> 21) & 15];
+ const char* destc = dest_strings_with_comma[(op >> 21) & 15];
const char* bc = bc_strings[op & 3];
const char* ftf = bc_strings[(op >> 23) & 3];
const char* fsf = bc_strings[(op >> 21) & 3];
- const char* fsfc = bc_strings_with_comma[(op >> 21) & 3];
+ const char* fsfc = bc_strings_with_comma[(op >> 21) & 3];
switch (op & 0x3f)
{
@@ -790,7 +790,7 @@ uint32_t ee_disassembler::dasm_extra_base(uint32_t pc, uint32_t op, std::ostream
{
case 0x1e: util::stream_format(stream, "lq %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x1f: util::stream_format(stream, "sq %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
- default: util::stream_format(stream, "dc.l $%08x [invalid]", op); break;
+ default: util::stream_format(stream, "dc.l $%08x [invalid]", op); break;
}
return 0;
@@ -802,8 +802,8 @@ uint32_t ee_disassembler::dasm_extra_special(uint32_t pc, uint32_t op, std::ostr
switch (op & 63)
{
- case 0x29: util::stream_format(stream, "mtsa %s", reg[rs]); break;
- default: util::stream_format(stream, "dc.l $%08x [invalid]", op); break;
+ case 0x29: util::stream_format(stream, "mtsa %s", reg[rs]); break;
+ default: util::stream_format(stream, "dc.l $%08x [invalid]", op); break;
}
return 0;
}
@@ -903,7 +903,7 @@ offs_t mips3_disassembler::dasm_one(std::ostream &stream, offs_t pc, u32 op)
case 0x3c: util::stream_format(stream, "dsll %s,%s,%d", reg[rd], reg[rt], shift+32); break;
case 0x3e: util::stream_format(stream, "dsrl %s,%s,%d", reg[rd], reg[rt], shift+32); break;
case 0x3f: util::stream_format(stream, "dsra %s,%s,%d", reg[rd], reg[rt], shift+32); break;
- default: flags = dasm_extra_special(pc, op, stream); break;
+ default: flags = dasm_extra_special(pc, op, stream); break;
}
break;
@@ -958,7 +958,7 @@ offs_t mips3_disassembler::dasm_one(std::ostream &stream, offs_t pc, u32 op)
case 0x19: util::stream_format(stream, "daddiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x1a: util::stream_format(stream, "ldl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x1b: util::stream_format(stream, "ldr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
- case 0x1c: flags = dasm_idt(pc, op, stream); break;
+ case 0x1c: flags = dasm_idt(pc, op, stream); break;
case 0x20: util::stream_format(stream, "lb %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x21: util::stream_format(stream, "lh %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x22: util::stream_format(stream, "lwl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
@@ -990,7 +990,7 @@ offs_t mips3_disassembler::dasm_one(std::ostream &stream, offs_t pc, u32 op)
case 0x3d: util::stream_format(stream, "sdc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x3e: util::stream_format(stream, "sdc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x3f: util::stream_format(stream, "sd %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
- default: flags = dasm_extra_base(pc, op, stream); break;
+ default: flags = dasm_extra_base(pc, op, stream); break;
}
return 4 | flags | SUPPORTED;
}