diff options
author | Miodrag Milanovic <mmicko@gmail.com> | 2016-06-29 08:34:30 +0200 |
---|---|---|
committer | Miodrag Milanovic <mmicko@gmail.com> | 2016-06-29 08:34:30 +0200 |
commit | 63f9a01f8c5d43b9cfe68c2d401a84647d19c10e (patch) | |
tree | a1f1874aa84850bddbebd2b0e0bfc3e1c77ce8c4 /src/devices/cpu | |
parent | 1f6f1bfd6cfb748d9c5e159d6bd014bab8d30944 (diff) |
Cleanup and version bumpmame0175
Diffstat (limited to 'src/devices/cpu')
-rw-r--r-- | src/devices/cpu/asap/asapdasm.cpp | 2 | ||||
-rw-r--r-- | src/devices/cpu/avr8/avr8.cpp | 2 | ||||
-rw-r--r-- | src/devices/cpu/drcbex64.cpp | 1 | ||||
-rw-r--r-- | src/devices/cpu/drcbex64.h | 1 | ||||
-rw-r--r-- | src/devices/cpu/m6502/odeco16.lst | 2 | ||||
-rw-r--r-- | src/devices/cpu/mb86235/mb86235d.cpp | 58 | ||||
-rw-r--r-- | src/devices/cpu/nec/v25.h | 4 | ||||
-rw-r--r-- | src/devices/cpu/patinhofeio/patinho_feio.cpp | 36 | ||||
-rw-r--r-- | src/devices/cpu/patinhofeio/patinhofeio_cpu.h | 38 | ||||
-rw-r--r-- | src/devices/cpu/sharc/sharc.cpp | 8 | ||||
-rw-r--r-- | src/devices/cpu/sharc/sharc.h | 38 | ||||
-rw-r--r-- | src/devices/cpu/sharc/sharcdrc.cpp | 2098 | ||||
-rw-r--r-- | src/devices/cpu/sharc/sharcfe.cpp | 802 | ||||
-rw-r--r-- | src/devices/cpu/sparc/mb86901.cpp | 1175 | ||||
-rw-r--r-- | src/devices/cpu/sparc/sparc.h | 102 | ||||
-rw-r--r-- | src/devices/cpu/sparc/sparcdefs.h | 738 | ||||
-rw-r--r-- | src/devices/cpu/tms32010/tms32010.h | 4 | ||||
-rw-r--r-- | src/devices/cpu/tms32025/tms32025.h | 6 |
18 files changed, 2556 insertions, 2559 deletions
diff --git a/src/devices/cpu/asap/asapdasm.cpp b/src/devices/cpu/asap/asapdasm.cpp index fd204c68a94..ded3a24e17b 100644 --- a/src/devices/cpu/asap/asapdasm.cpp +++ b/src/devices/cpu/asap/asapdasm.cpp @@ -91,7 +91,7 @@ CPU_DISASSEMBLE( asap ) sprintf(buffer, "mov%s %s,%s", setcond[cond], reg[rsrc1], reg[rdst]); else sprintf(buffer, "add%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); - break; + break; case 0x09: sprintf(buffer, "sub%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break; case 0x0a: sprintf(buffer, "addc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break; case 0x0b: sprintf(buffer, "subc%s %s,%s,%s", setcond[cond], reg[rsrc1], src2(op,0), reg[rdst]); break; diff --git a/src/devices/cpu/avr8/avr8.cpp b/src/devices/cpu/avr8/avr8.cpp index 2d2dd04824d..f0e790083f7 100644 --- a/src/devices/cpu/avr8/avr8.cpp +++ b/src/devices/cpu/avr8/avr8.cpp @@ -2915,7 +2915,7 @@ READ8_MEMBER( avr8_device::regs_r ) default: printf("[%08X] AVR8: Unknown Register Read: 0x%03X\n", m_shifted_pc, offset); -// machine().debug_break(); +// machine().debug_break(); return 0; } } diff --git a/src/devices/cpu/drcbex64.cpp b/src/devices/cpu/drcbex64.cpp index e1d41783a25..df5fc335599 100644 --- a/src/devices/cpu/drcbex64.cpp +++ b/src/devices/cpu/drcbex64.cpp @@ -175,7 +175,6 @@ // This is a trick to make it build on Android where the ARM SDK declares ::REG_Rn namespace drc { - using namespace uml; using namespace x64emit; diff --git a/src/devices/cpu/drcbex64.h b/src/devices/cpu/drcbex64.h index 2dcca934ddd..fc8b3cae1af 100644 --- a/src/devices/cpu/drcbex64.h +++ b/src/devices/cpu/drcbex64.h @@ -22,7 +22,6 @@ namespace drc { - //************************************************************************** // TYPE DEFINITIONS //************************************************************************** diff --git a/src/devices/cpu/m6502/odeco16.lst b/src/devices/cpu/m6502/odeco16.lst index 3fbc2409789..367f1c00704 100644 --- a/src/devices/cpu/m6502/odeco16.lst +++ b/src/devices/cpu/m6502/odeco16.lst @@ -92,7 +92,7 @@ vbl_zpg TMP2 = read_pc(); A = io->read_byte(0); //if(DECO16_VERBOSE) - // logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2); + // logerror("%s: VBL %02x (%04x)\n", tag(), NPC, TMP2); prefetch(); # exceptions diff --git a/src/devices/cpu/mb86235/mb86235d.cpp b/src/devices/cpu/mb86235/mb86235d.cpp index 34771cd346e..58dcfc047b6 100644 --- a/src/devices/cpu/mb86235/mb86235d.cpp +++ b/src/devices/cpu/mb86235/mb86235d.cpp @@ -6,14 +6,14 @@ static const char *regname[128] = { - "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", - "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", - "EB", "EBU", "EBL", "EO", "SP", "ST", "MOD", "LRPC", - "AR0", "AR1", "AR2", "AR3", "AR4", "AR5", "AR6", "AR7", - "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7", - "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7", - "PR", "FI", "FO0", "FO1", "PDR", "DDR", "PRP", "PWP", - "???", "???", "???", "???", "???", "???", "???", "???" + "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", + "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", + "EB", "EBU", "EBL", "EO", "SP", "ST", "MOD", "LRPC", + "AR0", "AR1", "AR2", "AR3", "AR4", "AR5", "AR6", "AR7", + "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7", + "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7", + "PR", "FI", "FO0", "FO1", "PDR", "DDR", "PRP", "PWP", + "???", "???", "???", "???", "???", "???", "???", "???" }; static const char *db_mnemonic[64] = @@ -69,22 +69,22 @@ static const char *mi1_field[16] = static const char *mi2_field[32] = { "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7", - "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" }; + "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" }; -static const char *mo_field[32] = +static const char *mo_field[32] = { "MA0", "MA1", "MA2", "MA3", "MA4", "MA5", "MA6", "MA7", "MB0", "MB1", "MB2", "MB3", "MB4", "MB5", "MB6", "MB7", - "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" }; + "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" }; -static const char *ai1_field[16] = +static const char *ai1_field[16] = { "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7" }; static const char *ai2_field[32] = { "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7", - "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "0", "1", "-1", "???", "???", "???", "???", "???" }; + "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "0", "1", "-1", "???", "???", "???", "???", "???" }; static const char *ai2f_field[32] = { "AA0", "AA1", "AA2", "AA3", "AA4", "AA5", "AA6", "AA7", "AB0", "AB1", "AB2", "AB3", "AB4", "AB5", "AB6", "AB7", - "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" }; + "PR", "PR++", "PR--", "PR#0", "???", "???", "???", "???", "-1.0E+0", "0.0E+0", "0.5E+0", "1.0E+0", "1.5E+0", "2.0E+0", "3.0E+0", "5.0E+0" }; static char* get_ea(int md, int arx, int ary, int disp) { @@ -196,7 +196,7 @@ static char* dasm_alu_mul(UINT64 opcode, bool twoop) break; } } - + // multiplication if (twoop) { @@ -211,7 +211,7 @@ static char* dasm_alu_mul(UINT64 opcode, bool twoop) else { if (ma == 0) - { + { if (opcode & ((UINT64)(1) << 56)) p += sprintf(p, "FMUL %s, %s, %s", mi1_field[i1], mi2_field[i2], mo_field[o]); else @@ -296,12 +296,12 @@ static char* dasm_control(UINT32 pc, UINT64 opcode) p += sprintf(p, "DRET"); break; - case 0x10: // DBcc - case 0x11: // DBNcc - case 0x18: // DCcc - case 0x19: // DCNcc - case 0x1a: // DCALL - case 0x12: // DJMP + case 0x10: // DBcc + case 0x11: // DBNcc + case 0x18: // DCcc + case 0x19: // DCNcc + case 0x1a: // DCALL + case 0x12: // DJMP { if (cop == 0x10) p += sprintf(p, "%s ", db_mnemonic[ef1]); @@ -798,25 +798,25 @@ static unsigned dasm_mb86235(char *buffer, UINT32 pc, UINT64 opcode) switch ((opcode >> 61) & 7) { - case 0: // ALU / MUL / double transfer (type 1) + case 0: // ALU / MUL / double transfer (type 1) p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_double_xfer1(opcode)); break; - case 1: // ALU / MYL / transfer (type 1) + case 1: // ALU / MYL / transfer (type 1) p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_xfer1(opcode)); break; - case 2: // ALU / MUL / control + case 2: // ALU / MUL / control p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, true), dasm_control(pc, opcode)); break; - case 4: // ALU or MUL / double transfer (type 2) + case 4: // ALU or MUL / double transfer (type 2) p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_double_xfer2(opcode)); break; - case 5: // ALU or MUL / transfer (type 2) + case 5: // ALU or MUL / transfer (type 2) p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_xfer2(opcode)); break; - case 6: // ALU or MUL / control + case 6: // ALU or MUL / control p += sprintf(p, "%s : %s", dasm_alu_mul(opcode, false), dasm_control(pc, opcode)); break; - case 7: // transfer (type 3) + case 7: // transfer (type 3) p += sprintf(p, "%s", dasm_xfer3(opcode)); break; diff --git a/src/devices/cpu/nec/v25.h b/src/devices/cpu/nec/v25.h index 6f0fa25eeb6..f170ad03b8f 100644 --- a/src/devices/cpu/nec/v25.h +++ b/src/devices/cpu/nec/v25.h @@ -31,7 +31,7 @@ enum #define MCFG_V25_PORT_P1_READ_CB(_devcb) \ devcb = &v25_common_device::set_p1_in_cb(*device, DEVCB_##_devcb); - + #define MCFG_V25_PORT_P2_READ_CB(_devcb) \ devcb = &v25_common_device::set_p2_in_cb(*device, DEVCB_##_devcb); @@ -53,7 +53,7 @@ public: // static configuration helpers static void set_decryption_table(device_t &device, const UINT8 *decryption_table) { downcast<v25_common_device &>(device).m_v25v35_decryptiontable = decryption_table; } - + template<class _Object> static devcb_base & set_pt_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_pt_in.set_callback(object); } template<class _Object> static devcb_base & set_p0_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_p0_in.set_callback(object); } template<class _Object> static devcb_base & set_p1_in_cb(device_t &device, _Object object) { return downcast<v25_common_device &>(device).m_p1_in.set_callback(object); } diff --git a/src/devices/cpu/patinhofeio/patinho_feio.cpp b/src/devices/cpu/patinhofeio/patinho_feio.cpp index 8482db59c41..a040d243916 100644 --- a/src/devices/cpu/patinhofeio/patinho_feio.cpp +++ b/src/devices/cpu/patinhofeio/patinho_feio.cpp @@ -1,7 +1,7 @@ // license:GPL-2.0+ // copyright-holders:Felipe Sanches /* - CPU emulation for Patinho Feio, the first computer designed and manufactured in Brazil + CPU emulation for Patinho Feio, the first computer designed and manufactured in Brazil */ #include "emu.h" @@ -91,11 +91,11 @@ void patinho_feio_cpu_device::device_start() //TODO: implement handling of these special purpose registers // which are also mapped to the first few main memory positions: // -// ERI: "Endereço de Retorno de Interrupção" +// ERI: "Endereco de Retorno de Interrupcao" // "Interrupt Return Address" // stored at addresses 002 and 003 // -// ETI: "início de uma rotina de tratamento de interrupção (se houver)" +// ETI: "inicio de uma rotina de tratamento de interrupcao (se houver)" // "start of an interrupt service routine (if any)" // stored at address 004 (and 005 as well?) // @@ -333,7 +333,7 @@ void patinho_feio_cpu_device::execute_instruction() case 0x90: //ST 0 = "Se T=0, Pula" // If T is zero, skip the next instruction - if ((FLAGS & T) == 0) + if ((FLAGS & T) == 0) INCREMENT_PC_4K; //skip return; case 0x91: @@ -348,7 +348,7 @@ void patinho_feio_cpu_device::execute_instruction() case 0x92: //ST 1 = "Se T=1, Pula" // If T is one, skip the next instruction - if ((FLAGS & T) == 1) + if ((FLAGS & T) == 1) INCREMENT_PC_4K; //skip return; case 0x93: @@ -363,7 +363,7 @@ void patinho_feio_cpu_device::execute_instruction() case 0x94: //SV 0 = "Se V=0, Pula" // If V is zero, skip the next instruction - if ((FLAGS & V) == 0) + if ((FLAGS & V) == 0) INCREMENT_PC_4K; //skip return; case 0x95: @@ -378,7 +378,7 @@ void patinho_feio_cpu_device::execute_instruction() case 0x96: //SV 1 = "Se V=1, Pula" // If V is one, skip the next instruction - if ((FLAGS & V) == 1) + if ((FLAGS & V) == 1) INCREMENT_PC_4K; //skip return; case 0x97: @@ -391,17 +391,17 @@ void patinho_feio_cpu_device::execute_instruction() } return; case 0x98: - //PUL="Pula para /002 a limpa estado de interrupção" + //PUL="Pula para /002 a limpa estado de interrupcao" // Jump to address /002 and disables interrupts - PC = 0x002; + PC = 0x002; m_interrupts_enabled = false; return; case 0x99: - //TRE="Troca conteúdos de ACC e EXT" + //TRE="Troca conteudos de ACC e EXT" // Exchange the value of the accumulator with the ACC extension register - value = ACC; - ACC = READ_ACC_EXTENSION_REG(); - WRITE_ACC_EXTENSION_REG(value); + value = ACC; + ACC = READ_ACC_EXTENSION_REG(); + WRITE_ACC_EXTENSION_REG(value); return; case 0x9A: //INIB="Inibe" @@ -621,7 +621,7 @@ void patinho_feio_cpu_device::execute_instruction() { case 0: // FNC /n0: Desliga flip-flop PERMITE/IMPEDE para - // o dispositivo n (isto é, impede inter- + // o dispositivo n (isto e, impede inter- // -rupcao do dispositivo n). // // Turns off the interrupt ENABLE/DISABLE @@ -654,7 +654,7 @@ void patinho_feio_cpu_device::execute_instruction() break; case 5: // FNC /n5: Liga flip-flop PERMITE/IMPEDE para o - // dispositivo n (isto é, permite inter- + // dispositivo n (isto e, permite inter- // -rupcao do dispositivo n). // // Turns on the interrupt ENABLE/DISABLE @@ -681,7 +681,7 @@ void patinho_feio_cpu_device::execute_instruction() m_iodev_control[channel] = NO_REQUEST; break; case 8: - // FNC /n8: Só funciona na leitora de fita, ca- + // FNC /n8: So funciona na leitora de fita, ca- // nal /E. Ignora todos os "feed-fra- // -mes" ("bytes" nulos) da fita, ate' a // proxima perfuracao (1o "byte" nao @@ -695,7 +695,7 @@ void patinho_feio_cpu_device::execute_instruction() //TODO: Implement-me! } else { printf("Function 8 of the /FNC instruction can only be used with"\ - "the papertape reader device at channel /E.\n"); + "the papertape reader device at channel /E.\n"); } break; default: @@ -705,7 +705,7 @@ void patinho_feio_cpu_device::execute_instruction() case 0x20: //SAL="Salta" // Skips a couple bytes if a condition is met - skip = false; + skip = false; switch(function) { case 1: diff --git a/src/devices/cpu/patinhofeio/patinhofeio_cpu.h b/src/devices/cpu/patinhofeio/patinhofeio_cpu.h index b8e6919273d..5d3a1745f53 100644 --- a/src/devices/cpu/patinhofeio/patinhofeio_cpu.h +++ b/src/devices/cpu/patinhofeio/patinhofeio_cpu.h @@ -35,18 +35,18 @@ enum #define REQUEST true #define NO_REQUEST false -#define BUTTON_NORMAL (1 << 0) /* normal CPU execution */ -#define BUTTON_CICLO_UNICO (1 << 1) /* single-cycle step */ -#define BUTTON_INSTRUCAO_UNICA (1 << 2) /* single-instruction step */ -#define BUTTON_ENDERECAMENTO (1 << 3) /* addressing action */ -#define BUTTON_ARMAZENAMENTO (1 << 4) /* storage action */ -#define BUTTON_EXPOSICAO (1 << 5) /* memory viewing action */ -#define BUTTON_ESPERA (1 << 6) /* wait */ -#define BUTTON_INTERRUPCAO (1 << 7) /* interrupt */ -#define BUTTON_PARTIDA (1 << 8) /* startup */ -#define BUTTON_PREPARACAO (1 << 9) /* reset */ -#define BUTTON_TIPO_DE_ENDERECAMENTO (1 << 10) /* Addressing mode (0: Fixed / 1: Sequential) */ -#define BUTTON_PROTECAO_DE_MEMORIA (1 << 11) /* Memory protection (in the address range 0xF80-0xFFF (1: write-only / 0: read-write) */ +#define BUTTON_NORMAL (1 << 0) /* normal CPU execution */ +#define BUTTON_CICLO_UNICO (1 << 1) /* single-cycle step */ +#define BUTTON_INSTRUCAO_UNICA (1 << 2) /* single-instruction step */ +#define BUTTON_ENDERECAMENTO (1 << 3) /* addressing action */ +#define BUTTON_ARMAZENAMENTO (1 << 4) /* storage action */ +#define BUTTON_EXPOSICAO (1 << 5) /* memory viewing action */ +#define BUTTON_ESPERA (1 << 6) /* wait */ +#define BUTTON_INTERRUPCAO (1 << 7) /* interrupt */ +#define BUTTON_PARTIDA (1 << 8) /* startup */ +#define BUTTON_PREPARACAO (1 << 9) /* reset */ +#define BUTTON_TIPO_DE_ENDERECAMENTO (1 << 10) /* Addressing mode (0: Fixed / 1: Sequential) */ +#define BUTTON_PROTECAO_DE_MEMORIA (1 << 11) /* Memory protection (in the address range 0xF80-0xFFF (1: write-only / 0: read-write) */ class patinho_feio_cpu_device : public cpu_device { public: @@ -76,14 +76,14 @@ protected: /* processor registers */ unsigned char m_acc; /* accumulator (8 bits) */ unsigned int m_pc; /* program counter (12 bits) - * Actual register name is CI, which - * stands for "Contador de Instrucao" - * or "instructions counter". - */ + * Actual register name is CI, which + * stands for "Contador de Instrucao" + * or "instructions counter". + */ unsigned int m_rc; /* RC = "Registrador de Chaves" (Keys Register) - * It represents the 12 bits of input data - * from toggle switches in the computer panel - */ + * It represents the 12 bits of input data + * from toggle switches in the computer panel + */ unsigned char m_idx; /* IDX = Index Register */ unsigned char m_ext; /* EXT = Accumulator Extension Register */ diff --git a/src/devices/cpu/sharc/sharc.cpp b/src/devices/cpu/sharc/sharc.cpp index 4123da67594..44a7c650d7d 100644 --- a/src/devices/cpu/sharc/sharc.cpp +++ b/src/devices/cpu/sharc/sharc.cpp @@ -11,7 +11,7 @@ #include "sharcfe.h" -#define DISABLE_FAST_REGISTERS 1 +#define DISABLE_FAST_REGISTERS 1 @@ -336,7 +336,7 @@ void adsp21062_device::external_dma_write(UINT32 address, UINT64 data) void adsp21062_device::device_start() { int saveindex; - + m_core = (sharc_internal_state *)m_cache.alloc_near(sizeof(sharc_internal_state)); memset(m_core, 0, sizeof(sharc_internal_state)); @@ -356,7 +356,7 @@ void adsp21062_device::device_start() // add UML symbols m_drcuml->symbol_add(&m_core->pc, sizeof(m_core->pc), "pc"); m_drcuml->symbol_add(&m_core->icount, sizeof(m_core->icount), "icount"); - + for (int i=0; i < 16; i++) { char buf[10]; @@ -412,7 +412,7 @@ void adsp21062_device::device_start() m_drcuml->symbol_add(&m_core->astat_drc.sz, sizeof(m_core->astat_drc.sz), "astat_sz"); m_drcuml->symbol_add(&m_core->astat_drc.sv, sizeof(m_core->astat_drc.sv), "astat_sv"); m_drcuml->symbol_add(&m_core->astat_drc.ss, sizeof(m_core->astat_drc.ss), "astat_ss"); - + m_drcuml->symbol_add(&m_core->arg0, sizeof(m_core->arg0), "arg0"); m_drcuml->symbol_add(&m_core->arg1, sizeof(m_core->arg1), "arg1"); m_drcuml->symbol_add(&m_core->arg2, sizeof(m_core->arg2), "arg2"); diff --git a/src/devices/cpu/sharc/sharc.h b/src/devices/cpu/sharc/sharc.h index 215135390e0..1eb2dc8972b 100644 --- a/src/devices/cpu/sharc/sharc.h +++ b/src/devices/cpu/sharc/sharc.h @@ -111,25 +111,25 @@ struct SHARC_DMA_OP #define MODE2_CAFRZ 0x80000 /* Cache freeze */ -#define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x)) -#define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x)) +#define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x)) +#define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x)) #define MAKE_EXTRACT_MASK(start_bit, length) ((0xffffffff << start_bit) & (((UINT32)0xffffffff) >> (32 - (start_bit + length)))) -#define OP_USERFLAG_COUNTER_LOOP 0x00000001 -#define OP_USERFLAG_COND_LOOP 0x00000002 -#define OP_USERFLAG_COND_FIELD 0x000003fc -#define OP_USERFLAG_COND_FIELD_SHIFT 2 -#define OP_USERFLAG_ASTAT_DELAY_COPY_AZ 0x00001000 -#define OP_USERFLAG_ASTAT_DELAY_COPY_AN 0x00002000 -#define OP_USERFLAG_ASTAT_DELAY_COPY_AC 0x00004000 -#define OP_USERFLAG_ASTAT_DELAY_COPY_AV 0x00008000 -#define OP_USERFLAG_ASTAT_DELAY_COPY_MV 0x00010000 -#define OP_USERFLAG_ASTAT_DELAY_COPY_MN 0x00020000 -#define OP_USERFLAG_ASTAT_DELAY_COPY_SV 0x00040000 -#define OP_USERFLAG_ASTAT_DELAY_COPY_SZ 0x00080000 -#define OP_USERFLAG_ASTAT_DELAY_COPY_BTF 0x00100000 -#define OP_USERFLAG_ASTAT_DELAY_COPY 0x001ff000 -#define OP_USERFLAG_CALL 0x10000000 +#define OP_USERFLAG_COUNTER_LOOP 0x00000001 +#define OP_USERFLAG_COND_LOOP 0x00000002 +#define OP_USERFLAG_COND_FIELD 0x000003fc +#define OP_USERFLAG_COND_FIELD_SHIFT 2 +#define OP_USERFLAG_ASTAT_DELAY_COPY_AZ 0x00001000 +#define OP_USERFLAG_ASTAT_DELAY_COPY_AN 0x00002000 +#define OP_USERFLAG_ASTAT_DELAY_COPY_AC 0x00004000 +#define OP_USERFLAG_ASTAT_DELAY_COPY_AV 0x00008000 +#define OP_USERFLAG_ASTAT_DELAY_COPY_MV 0x00010000 +#define OP_USERFLAG_ASTAT_DELAY_COPY_MN 0x00020000 +#define OP_USERFLAG_ASTAT_DELAY_COPY_SV 0x00040000 +#define OP_USERFLAG_ASTAT_DELAY_COPY_SZ 0x00080000 +#define OP_USERFLAG_ASTAT_DELAY_COPY_BTF 0x00100000 +#define OP_USERFLAG_ASTAT_DELAY_COPY 0x001ff000 +#define OP_USERFLAG_CALL 0x10000000 #define MCFG_SHARC_BOOT_MODE(boot_mode) \ @@ -439,7 +439,7 @@ private: uml::code_handle *m_pop_loop; uml::code_handle *m_push_status; uml::code_handle *m_pop_status; - uml::code_handle *m_exception[EXCEPTION_COUNT]; // exception handlers + uml::code_handle *m_exception[EXCEPTION_COUNT]; // exception handlers uml::code_handle *m_swap_dag1_0_3; uml::code_handle *m_swap_dag1_4_7; uml::code_handle *m_swap_dag2_0_3; @@ -596,7 +596,7 @@ private: { UINT32 cycles; /* accumulated cycles */ UINT8 checkints; /* need to check interrupts before next instruction */ - uml::code_label labelnum; /* index for local labels */ + uml::code_label labelnum; /* index for local labels */ struct { int counter; diff --git a/src/devices/cpu/sharc/sharcdrc.cpp b/src/devices/cpu/sharc/sharcdrc.cpp index 2850f91da67..a40586cac23 100644 --- a/src/devices/cpu/sharc/sharcdrc.cpp +++ b/src/devices/cpu/sharc/sharcdrc.cpp @@ -17,7 +17,7 @@ using namespace uml; -#define USE_SWAPDQ 0 +#define USE_SWAPDQ 0 #define WRITE_SNOOP 0 @@ -25,85 +25,85 @@ using namespace uml; #define MAPVAR_PC M0 #define MAPVAR_CYCLES M1 -// exit codes +// exit codes #define EXECUTE_OUT_OF_CYCLES 0 #define EXECUTE_MISSING_CODE 1 #define EXECUTE_UNMAPPED_CODE 2 #define EXECUTE_RESET_CACHE 3 -#define REG(reg) m_regmap[reg] -#define DM_I(reg) mem(&m_core->dag1.i[reg]) -#define DM_M(reg) mem(&m_core->dag1.m[reg]) -#define DM_L(reg) mem(&m_core->dag1.l[reg]) -#define DM_B(reg) mem(&m_core->dag1.b[reg]) -#define PM_I(reg) mem(&m_core->dag2.i[reg]) -#define PM_M(reg) mem(&m_core->dag2.m[reg]) -#define PM_L(reg) mem(&m_core->dag2.l[reg]) -#define PM_B(reg) mem(&m_core->dag2.b[reg]) -#define ASTAT_AZ mem(&m_core->astat_drc.az) -#define ASTAT_AV mem(&m_core->astat_drc.av) -#define ASTAT_AN mem(&m_core->astat_drc.an) -#define ASTAT_AC mem(&m_core->astat_drc.ac) -#define ASTAT_AS mem(&m_core->astat_drc.as) -#define ASTAT_AI mem(&m_core->astat_drc.ai) -#define ASTAT_AF mem(&m_core->astat_drc.af) -#define ASTAT_MN mem(&m_core->astat_drc.mn) -#define ASTAT_MV mem(&m_core->astat_drc.mv) -#define ASTAT_MU mem(&m_core->astat_drc.mu) -#define ASTAT_MI mem(&m_core->astat_drc.mi) -#define ASTAT_SV mem(&m_core->astat_drc.sv) -#define ASTAT_SZ mem(&m_core->astat_drc.sz) -#define ASTAT_SS mem(&m_core->astat_drc.ss) -#define ASTAT_BTF mem(&m_core->astat_drc.btf) -#define FLAG0 mem(&m_core->flag[0]) -#define FLAG1 mem(&m_core->flag[1]) -#define FLAG2 mem(&m_core->flag[2]) -#define FLAG3 mem(&m_core->flag[3]) -#define CURLCNTR mem(&m_core->curlcntr) -#define LCNTR mem(&m_core->lcntr) -#define PCSTK mem(&m_core->pcstk) -#define PCSTKP mem(&m_core->pcstkp) -#define STKY mem(&m_core->stky) -#define LSTKP mem(&m_core->lstkp) -#define USTAT1 mem(&m_core->ustat1) -#define USTAT2 mem(&m_core->ustat2) -#define IRPTL mem(&m_core->irptl) -#define MODE1 mem(&m_core->mode1) -#define MODE2 mem(&m_core->mode2) -#define IMASK mem(&m_core->imask) -#define IMASKP mem(&m_core->imaskp) -#define MRF mem(&m_core->mrf) -#define MRB mem(&m_core->mrb) - -#define AZ_CALC_REQUIRED ((desc->regreq[0] & 0x00010000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define AV_CALC_REQUIRED ((desc->regreq[0] & 0x00020000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define AN_CALC_REQUIRED ((desc->regreq[0] & 0x00040000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define AC_CALC_REQUIRED ((desc->regreq[0] & 0x00080000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define AS_CALC_REQUIRED ((desc->regreq[0] & 0x00100000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define AI_CALC_REQUIRED ((desc->regreq[0] & 0x00200000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define MN_CALC_REQUIRED ((desc->regreq[0] & 0x00400000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define MV_CALC_REQUIRED ((desc->regreq[0] & 0x00800000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define MU_CALC_REQUIRED ((desc->regreq[0] & 0x01000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define MI_CALC_REQUIRED ((desc->regreq[0] & 0x02000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define SV_CALC_REQUIRED ((desc->regreq[0] & 0x04000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define SZ_CALC_REQUIRED ((desc->regreq[0] & 0x08000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define SS_CALC_REQUIRED ((desc->regreq[0] & 0x10000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define BTF_CALC_REQUIRED ((desc->regreq[0] & 0x20000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) -#define AF_CALC_REQUIRED ((desc->regreq[0] & 0x40000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) - - -#define IRAM_BLOCK0_START 0x20000 -#define IRAM_BLOCK0_END 0x27fff -#define IRAM_BLOCK1_START 0x28000 -#define IRAM_BLOCK1_END 0x3ffff -#define IRAM_SHORT_BLOCK0_START 0x40000 -#define IRAM_SHORT_BLOCK0_END 0x4ffff -#define IRAM_SHORT_BLOCK1_START 0x50000 -#define IRAM_SHORT_BLOCK1_END 0x7ffff -#define IOP_REGISTER_START 0x00000 -#define IOP_REGISTER_END 0x000ff -#define IRAM_END 0x7ffff +#define REG(reg) m_regmap[reg] +#define DM_I(reg) mem(&m_core->dag1.i[reg]) +#define DM_M(reg) mem(&m_core->dag1.m[reg]) +#define DM_L(reg) mem(&m_core->dag1.l[reg]) +#define DM_B(reg) mem(&m_core->dag1.b[reg]) +#define PM_I(reg) mem(&m_core->dag2.i[reg]) +#define PM_M(reg) mem(&m_core->dag2.m[reg]) +#define PM_L(reg) mem(&m_core->dag2.l[reg]) +#define PM_B(reg) mem(&m_core->dag2.b[reg]) +#define ASTAT_AZ mem(&m_core->astat_drc.az) +#define ASTAT_AV mem(&m_core->astat_drc.av) +#define ASTAT_AN mem(&m_core->astat_drc.an) +#define ASTAT_AC mem(&m_core->astat_drc.ac) +#define ASTAT_AS mem(&m_core->astat_drc.as) +#define ASTAT_AI mem(&m_core->astat_drc.ai) +#define ASTAT_AF mem(&m_core->astat_drc.af) +#define ASTAT_MN mem(&m_core->astat_drc.mn) +#define ASTAT_MV mem(&m_core->astat_drc.mv) +#define ASTAT_MU mem(&m_core->astat_drc.mu) +#define ASTAT_MI mem(&m_core->astat_drc.mi) +#define ASTAT_SV mem(&m_core->astat_drc.sv) +#define ASTAT_SZ mem(&m_core->astat_drc.sz) +#define ASTAT_SS mem(&m_core->astat_drc.ss) +#define ASTAT_BTF mem(&m_core->astat_drc.btf) +#define FLAG0 mem(&m_core->flag[0]) +#define FLAG1 mem(&m_core->flag[1]) +#define FLAG2 mem(&m_core->flag[2]) +#define FLAG3 mem(&m_core->flag[3]) +#define CURLCNTR mem(&m_core->curlcntr) +#define LCNTR mem(&m_core->lcntr) +#define PCSTK mem(&m_core->pcstk) +#define PCSTKP mem(&m_core->pcstkp) +#define STKY mem(&m_core->stky) +#define LSTKP mem(&m_core->lstkp) +#define USTAT1 mem(&m_core->ustat1) +#define USTAT2 mem(&m_core->ustat2) +#define IRPTL mem(&m_core->irptl) +#define MODE1 mem(&m_core->mode1) +#define MODE2 mem(&m_core->mode2) +#define IMASK mem(&m_core->imask) +#define IMASKP mem(&m_core->imaskp) +#define MRF mem(&m_core->mrf) +#define MRB mem(&m_core->mrb) + +#define AZ_CALC_REQUIRED ((desc->regreq[0] & 0x00010000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define AV_CALC_REQUIRED ((desc->regreq[0] & 0x00020000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define AN_CALC_REQUIRED ((desc->regreq[0] & 0x00040000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define AC_CALC_REQUIRED ((desc->regreq[0] & 0x00080000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define AS_CALC_REQUIRED ((desc->regreq[0] & 0x00100000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define AI_CALC_REQUIRED ((desc->regreq[0] & 0x00200000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define MN_CALC_REQUIRED ((desc->regreq[0] & 0x00400000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define MV_CALC_REQUIRED ((desc->regreq[0] & 0x00800000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define MU_CALC_REQUIRED ((desc->regreq[0] & 0x01000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define MI_CALC_REQUIRED ((desc->regreq[0] & 0x02000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define SV_CALC_REQUIRED ((desc->regreq[0] & 0x04000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define SZ_CALC_REQUIRED ((desc->regreq[0] & 0x08000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define SS_CALC_REQUIRED ((desc->regreq[0] & 0x10000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define BTF_CALC_REQUIRED ((desc->regreq[0] & 0x20000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) +#define AF_CALC_REQUIRED ((desc->regreq[0] & 0x40000000) || desc->flags & OPFLAG_IN_DELAY_SLOT) + + +#define IRAM_BLOCK0_START 0x20000 +#define IRAM_BLOCK0_END 0x27fff +#define IRAM_BLOCK1_START 0x28000 +#define IRAM_BLOCK1_END 0x3ffff +#define IRAM_SHORT_BLOCK0_START 0x40000 +#define IRAM_SHORT_BLOCK0_END 0x4ffff +#define IRAM_SHORT_BLOCK1_START 0x50000 +#define IRAM_SHORT_BLOCK1_END 0x7ffff +#define IOP_REGISTER_START 0x00000 +#define IOP_REGISTER_END 0x000ff +#define IRAM_END 0x7ffff inline void adsp21062_device::alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name) @@ -267,26 +267,26 @@ UINT32 adsp21062_device::do_condition_astat_bits(int condition) UINT32 r = 0; switch (condition) { - case 0x00: r = AZ; break; // EQ - case 0x01: r = AZ | AN; break; // LT - case 0x02: r = AZ | AN; break; // LE - case 0x03: r = AC; break; // AC - case 0x04: r = AV; break; // AV - case 0x05: r = MV; break; // MV - case 0x06: r = MN; break; // MS - case 0x07: r = SV; break; // SV - case 0x08: r = SZ; break; // SZ - case 0x0d: r = BTF; break; // TF - case 0x10: r = AZ; break; // NOT EQUAL - case 0x11: r = AZ | AN; break; // GE - case 0x12: r = AZ | AN; break; // GT - case 0x13: r = AC; break; // NOT AC - case 0x14: r = AV; break; // NOT AV - case 0x15: r = MV; break; // NOT MV - case 0x16: r = MN; break; // NOT MS - case 0x17: r = SV; break; // NOT SV - case 0x18: r = SZ; break; // NOT SZ - case 0x1d: r = BTF; break; // NOT TF + case 0x00: r = AZ; break; // EQ + case 0x01: r = AZ | AN; break; // LT + case 0x02: r = AZ | AN; break; // LE + case 0x03: r = AC; break; // AC + case 0x04: r = AV; break; // AV + case 0x05: r = MV; break; // MV + case 0x06: r = MN; break; // MS + case 0x07: r = SV; break; // SV + case 0x08: r = SZ; break; // SZ + case 0x0d: r = BTF; break; // TF + case 0x10: r = AZ; break; // NOT EQUAL + case 0x11: r = AZ | AN; break; // GE + case 0x12: r = AZ | AN; break; // GT + case 0x13: r = AC; break; // NOT AC + case 0x14: r = AV; break; // NOT AV + case 0x15: r = MV; break; // NOT MV + case 0x16: r = MN; break; // NOT MS + case 0x17: r = SV; break; // NOT SV + case 0x18: r = SZ; break; // NOT SZ + case 0x1d: r = BTF; break; // NOT TF } return r; @@ -354,220 +354,220 @@ void adsp21062_device::static_generate_memory_accessor(MEM_ACCESSOR_TYPE type, c switch (type) { case MEM_ACCESSOR_PM_READ48: - UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START - UML_JMPc(block, COND_B, label); // jb label1 - UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END - UML_JMPc(block, COND_A, label); // ja label1 - + UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START + UML_JMPc(block, COND_B, label); // jb label1 + UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END + UML_JMPc(block, COND_A, label); // ja label1 + // 0x20000 ... 0x27fff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff - UML_MULS(block, I1, I1, I1, 3); // muls i1,3 - UML_DLOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // dload i0,[block0],i1,word,scale_x2 - UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32 - UML_DLOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_1],i1,word,scale_x2 - UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16 - UML_DOR(block, I0, I0, I2); // dor i0,i0,i2 - UML_DLOAD(block, I2, block0_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_2],i1,word,scale_x2 - UML_DOR(block, I0, I0, I2); // dor i0,i0,i2 - UML_RET(block); // ret - - UML_LABEL(block, label++); // label1: - UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START - UML_JMPc(block, COND_B, label); // jb label2 - UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END - UML_JMPc(block, COND_A, label); // ja label2 + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff + UML_MULS(block, I1, I1, I1, 3); // muls i1,3 + UML_DLOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // dload i0,[block0],i1,word,scale_x2 + UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32 + UML_DLOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_1],i1,word,scale_x2 + UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16 + UML_DOR(block, I0, I0, I2); // dor i0,i0,i2 + UML_DLOAD(block, I2, block0_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block0_2],i1,word,scale_x2 + UML_DOR(block, I0, I0, I2); // dor i0,i0,i2 + UML_RET(block); // ret + + UML_LABEL(block, label++); // label1: + UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START + UML_JMPc(block, COND_B, label); // jb label2 + UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END + UML_JMPc(block, COND_A, label); // ja label2 // 0x28000 ... 0x3ffff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff) - UML_MULS(block, I1, I1, I1, 3); // muls i1,3 - UML_DLOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // dload i0,[block1],i1,word,scale_x2 - UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32 - UML_DLOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_1],i1,word,scale_x2 - UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16 - UML_DOR(block, I0, I0, I2); // dor i0,i0,i2 - UML_DLOAD(block, I2, block1_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_2],i1,word,scale_x2 - UML_DOR(block, I0, I0, I2); // dor i0,i0,i2 - UML_RET(block); // ret - - UML_LABEL(block, label++); // label2: + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff) + UML_MULS(block, I1, I1, I1, 3); // muls i1,3 + UML_DLOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // dload i0,[block1],i1,word,scale_x2 + UML_DSHL(block, I0, I0, 32); // dshl i0,i0,32 + UML_DLOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_1],i1,word,scale_x2 + UML_DSHL(block, I2, I2, 16); // dshl i2,i2,16 + UML_DOR(block, I0, I0, I2); // dor i0,i0,i2 + UML_DLOAD(block, I2, block1_2, I1, SIZE_WORD, SCALE_x2); // dload i2,[block1_2],i1,word,scale_x2 + UML_DOR(block, I0, I0, I2); // dor i0,i0,i2 + UML_RET(block); // ret + + UML_LABEL(block, label++); // label2: break; case MEM_ACCESSOR_PM_WRITE48: - UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START - UML_JMPc(block, COND_B, label); // jb label1 - UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END - UML_JMPc(block, COND_A, label); // ja label1 + UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START + UML_JMPc(block, COND_B, label); // jb label1 + UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END + UML_JMPc(block, COND_A, label); // ja label1 // 0x20000 ... 0x27fff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff - UML_MULS(block, I1, I1, I1, 3); // muls i1,3 - UML_DSTORE(block, block0_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_2],i1,i0,word,scale_x2 - UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16 - UML_DSTORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_1],i1,i0,word,scale_x2 - UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16 - UML_DSTORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0],i1,i0,word,scale_x2 + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff + UML_MULS(block, I1, I1, I1, 3); // muls i1,3 + UML_DSTORE(block, block0_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_2],i1,i0,word,scale_x2 + UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16 + UML_DSTORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0_1],i1,i0,word,scale_x2 + UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16 + UML_DSTORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block0],i1,i0,word,scale_x2 UML_MOV(block, mem(&m_core->force_recompile), 1); - UML_RET(block); // ret + UML_RET(block); // ret - UML_LABEL(block, label++); // label1: - UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START - UML_JMPc(block, COND_B, label); // jb label2 - UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END - UML_JMPc(block, COND_A, label); // ja label2 + UML_LABEL(block, label++); // label1: + UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START + UML_JMPc(block, COND_B, label); // jb label2 + UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END + UML_JMPc(block, COND_A, label); // ja label2 // 0x28000 ... 0x3ffff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff) - UML_MULS(block, I1, I1, I1, 3); // muls i1,3 - UML_DSTORE(block, block1_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_2],i1,i0,word,scale_x2 - UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16 - UML_DSTORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_1],i1,i0,word,scale_x2 - UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16 - UML_DSTORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1],i1,i0,word,scale_x2 - UML_RET(block); // ret - - UML_LABEL(block, label++); // label2: + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff) + UML_MULS(block, I1, I1, I1, 3); // muls i1,3 + UML_DSTORE(block, block1_2, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_2],i1,i0,word,scale_x2 + UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16 + UML_DSTORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1_1],i1,i0,word,scale_x2 + UML_DSHR(block, I0, I0, 16); // dshr i0,i0,16 + UML_DSTORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // dstore [block1],i1,i0,word,scale_x2 + UML_RET(block); // ret + + UML_LABEL(block, label++); // label2: break; case MEM_ACCESSOR_PM_READ32: - UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START - UML_JMPc(block, COND_B, label); // jb label1 - UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END - UML_JMPc(block, COND_A, label); // ja label1 - + UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START + UML_JMPc(block, COND_B, label); // jb label1 + UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END + UML_JMPc(block, COND_A, label); // ja label1 + // 0x20000 ... 0x27fff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff - UML_MULS(block, I1, I1, I1, 3); // muls i1,3 - UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2 - UML_SHL(block, I0, I0, 16); // shl i0,i0,16 - UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block0_1],i1,word,scale_x2 - UML_OR(block, I0, I0, I2); // or i0,i0,i2 - UML_RET(block); // ret - - UML_LABEL(block, label++); // label1: - UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START - UML_JMPc(block, COND_B, label); // jb label2 - UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END - UML_JMPc(block, COND_A, label); // ja label2 + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff + UML_MULS(block, I1, I1, I1, 3); // muls i1,3 + UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2 + UML_SHL(block, I0, I0, 16); // shl i0,i0,16 + UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block0_1],i1,word,scale_x2 + UML_OR(block, I0, I0, I2); // or i0,i0,i2 + UML_RET(block); // ret + + UML_LABEL(block, label++); // label1: + UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START + UML_JMPc(block, COND_B, label); // jb label2 + UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END + UML_JMPc(block, COND_A, label); // ja label2 // 0x28000 ... 0x3ffff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff) - UML_MULS(block, I1, I1, I1, 3); // muls i1,3 - UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2 - UML_SHL(block, I0, I0, 16); // shl i0,i0,16 - UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block1_1],i1,word,scale_x2 - UML_OR(block, I0, I0, I2); // or i0,i0,i2 - UML_RET(block); // ret - - UML_LABEL(block, label++); // label2: + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff) + UML_MULS(block, I1, I1, I1, 3); // muls i1,3 + UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2 + UML_SHL(block, I0, I0, 16); // shl i0,i0,16 + UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x2); // load i2,[block1_1],i1,word,scale_x2 + UML_OR(block, I0, I0, I2); // or i0,i0,i2 + UML_RET(block); // ret + + UML_LABEL(block, label++); // label2: break; case MEM_ACCESSOR_PM_WRITE32: - UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START - UML_JMPc(block, COND_B, label); // jb label1 - UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END - UML_JMPc(block, COND_A, label); // ja label1 + UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START + UML_JMPc(block, COND_B, label); // jb label1 + UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END + UML_JMPc(block, COND_A, label); // ja label1 // 0x20000 ... 0x27fff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff - UML_MULS(block, I1, I1, I1, 3); // muls i1,3 - UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block0_1],i1,i0,word,scale_x2 - UML_SHR(block, I0, I0, 16); // shr i0,i0,16 - UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2 - UML_RET(block); // ret - - UML_LABEL(block, label++); // label1: - UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START - UML_JMPc(block, COND_B, label); // jb label2 - UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END - UML_JMPc(block, COND_A, label); // ja label2 + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff + UML_MULS(block, I1, I1, I1, 3); // muls i1,3 + UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block0_1],i1,i0,word,scale_x2 + UML_SHR(block, I0, I0, 16); // shr i0,i0,16 + UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2 + UML_RET(block); // ret + + UML_LABEL(block, label++); // label1: + UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START + UML_JMPc(block, COND_B, label); // jb label2 + UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END + UML_JMPc(block, COND_A, label); // ja label2 // 0x28000 ... 0x3ffff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff) - UML_MULS(block, I1, I1, I1, 3); // muls i1,3 - UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1_1],i1,i0,word,scale_x2 - UML_SHR(block, I0, I0, 16); // shr i0,i0,16 - UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2 - UML_RET(block); // ret - - UML_LABEL(block, label++); // label2: + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff (block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff) + UML_MULS(block, I1, I1, I1, 3); // muls i1,3 + UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1_1],i1,i0,word,scale_x2 + UML_SHR(block, I0, I0, 16); // shr i0,i0,16 + UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2 + UML_RET(block); // ret + + UML_LABEL(block, label++); // label2: break; case MEM_ACCESSOR_DM_READ32: - UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END - UML_JMPc(block, COND_BE, label); // jbe label1 + UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END + UML_JMPc(block, COND_BE, label); // jbe label1 // 0x80000 ... - UML_SHL(block, I1, I1, 2); // shl i1,i1,2 - UML_READ(block, I0, I1, SIZE_DWORD, SPACE_DATA); // read i0,i1,dword,SPACE_DATA + UML_SHL(block, I1, I1, 2); // shl i1,i1,2 + UML_READ(block, I0, I1, SIZE_DWORD, SPACE_DATA); // read i0,i1,dword,SPACE_DATA UML_RET(block); - UML_LABEL(block, label++); // label1: - UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START - UML_JMPc(block, COND_B, label); // jb label2 - UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END - UML_JMPc(block, COND_A, label); // ja label2 + UML_LABEL(block, label++); // label1: + UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START + UML_JMPc(block, COND_B, label); // jb label2 + UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END + UML_JMPc(block, COND_A, label); // ja label2 // 0x20000 ... 0x27fff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff - UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x4); // load i0,[block0],i1,word,scale_x4 - UML_SHL(block, I0, I0, 16); // shl i0,i0,16 - UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block0_1],i1,word,scale_x4 - UML_OR(block, I0, I0, I2); // or i0,i0,i2 + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff + UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x4); // load i0,[block0],i1,word,scale_x4 + UML_SHL(block, I0, I0, 16); // shl i0,i0,16 + UML_LOAD(block, I2, block0_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block0_1],i1,word,scale_x4 + UML_OR(block, I0, I0, I2); // or i0,i0,i2 UML_RET(block); - UML_LABEL(block, label++); // label2: - UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START - UML_JMPc(block, COND_B, label); // jb label3 - UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END - UML_JMPc(block, COND_A, label); // ja label3 + UML_LABEL(block, label++); // label2: + UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START + UML_JMPc(block, COND_B, label); // jb label3 + UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END + UML_JMPc(block, COND_A, label); // ja label3 // 0x28000 ... 0x3ffff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff - UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x4); // load i0,[block1],i1,word,scale_x4 - UML_SHL(block, I0, I0, 16); // shl i0,i0,16 - UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block1_1],i1,word,scale_x4 - UML_OR(block, I0, I0, I2); // or i0,i0,i2 + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff + UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x4); // load i0,[block1],i1,word,scale_x4 + UML_SHL(block, I0, I0, 16); // shl i0,i0,16 + UML_LOAD(block, I2, block1_1, I1, SIZE_WORD, SCALE_x4); // load i2,[block1_1],i1,word,scale_x4 + UML_OR(block, I0, I0, I2); // or i0,i0,i2 UML_RET(block); - UML_LABEL(block, label++); // Label3: - UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END - UML_JMPc(block, COND_A, label); // ja label4 + UML_LABEL(block, label++); // Label3: + UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END + UML_JMPc(block, COND_A, label); // ja label4 // IOP registers - UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1 - UML_CALLC(block, cfunc_read_iop, this); // callc cfunc_read_iop - UML_MOV(block, I0, mem(&m_core->arg1)); // mov i0,[m_core->arg1] + UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1 + UML_CALLC(block, cfunc_read_iop, this); // callc cfunc_read_iop + UML_MOV(block, I0, mem(&m_core->arg1)); // mov i0,[m_core->arg1] UML_RET(block); - UML_LABEL(block, label++); // label4: - UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START - UML_JMPc(block, COND_B, label+1); // jb label6 - UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END - UML_JMPc(block, COND_A, label+1); // ja label6 + UML_LABEL(block, label++); // label4: + UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START + UML_JMPc(block, COND_B, label+1); // jb label6 + UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END + UML_JMPc(block, COND_A, label+1); // ja label6 // 0x40000 ... 0x4ffff - UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff - UML_XOR(block, I1, I1, 1); // xor i1,i1,1 - UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000 - UML_JMPc(block, COND_Z, label); // jz label5 - UML_LOADS(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // loads i0,[block0],i1,word,scale_x2 + UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff + UML_XOR(block, I1, I1, 1); // xor i1,i1,1 + UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000 + UML_JMPc(block, COND_Z, label); // jz label5 + UML_LOADS(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // loads i0,[block0],i1,word,scale_x2 UML_RET(block); - UML_LABEL(block, label++); // label5: - UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2 + UML_LABEL(block, label++); // label5: + UML_LOAD(block, I0, block0, I1, SIZE_WORD, SCALE_x2); // load i0,[block0],i1,word,scale_x2 UML_RET(block); - UML_LABEL(block, label++); // label6: - UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START - UML_JMPc(block, COND_B, label+1); // jb label8 - UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END - UML_JMPc(block, COND_A, label+1); // ja label8 + UML_LABEL(block, label++); // label6: + UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START + UML_JMPc(block, COND_B, label+1); // jb label8 + UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END + UML_JMPc(block, COND_A, label+1); // ja label8 // 0x50000 ... 0x7ffff - UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff - UML_XOR(block, I1, I1, 1); // xor i1,i1,1 - UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000 - UML_JMPc(block, COND_Z, label); // jz label7 - UML_LOADS(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // loads i0,[block1],i1,word,scale_x2 + UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff + UML_XOR(block, I1, I1, 1); // xor i1,i1,1 + UML_TEST(block, mem(&m_core->mode1), 0x4000); // test [m_core->mode1],0x4000 + UML_JMPc(block, COND_Z, label); // jz label7 + UML_LOADS(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // loads i0,[block1],i1,word,scale_x2 UML_RET(block); - UML_LABEL(block, label++); // label7: - UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2 + UML_LABEL(block, label++); // label7: + UML_LOAD(block, I0, block1, I1, SIZE_WORD, SCALE_x2); // load i0,[block1],i1,word,scale_x2 UML_RET(block); - UML_LABEL(block, label++); // label8: + UML_LABEL(block, label++); // label8: break; case MEM_ACCESSOR_DM_WRITE32: @@ -583,69 +583,69 @@ void adsp21062_device::static_generate_memory_accessor(MEM_ACCESSOR_TYPE type, c #endif - UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END - UML_JMPc(block, COND_BE, label); // jbe label1 + UML_CMP(block, I1, IRAM_END); // cmp i1,IRAM_END + UML_JMPc(block, COND_BE, label); // jbe label1 // 0x80000 ... - UML_SHL(block, I1, I1, 2); // shl i1,i1,2 - UML_WRITE(block, I1, I0, SIZE_DWORD, SPACE_DATA); // write i1,i0,dword,SPACE_DATA + UML_SHL(block, I1, I1, 2); // shl i1,i1,2 + UML_WRITE(block, I1, I0, SIZE_DWORD, SPACE_DATA); // write i1,i0,dword,SPACE_DATA UML_RET(block); - UML_LABEL(block, label++); // label1: - UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START - UML_JMPc(block, COND_B, label); // jb label2 - UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END - UML_JMPc(block, COND_A, label); // ja label2 + UML_LABEL(block, label++); // label1: + UML_CMP(block, I1, IRAM_BLOCK0_START); // cmp i1,IRAM_BLOCK0_START + UML_JMPc(block, COND_B, label); // jb label2 + UML_CMP(block, I1, IRAM_BLOCK0_END); // cmp i1,IRAM_BLOCK0_END + UML_JMPc(block, COND_A, label); // ja label2 // 0x20000 ... 0x27fff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff - UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block0_1],i1,i0,word,scale_x4 - UML_SHR(block, I0, I0, 16); // shr i0,i0,16 - UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x4); // store [block0],i1,i0,word,scale_x4 + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff + UML_STORE(block, block0_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block0_1],i1,i0,word,scale_x4 + UML_SHR(block, I0, I0, 16); // shr i0,i0,16 + UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x4); // store [block0],i1,i0,word,scale_x4 UML_RET(block); - UML_LABEL(block, label++); // label2: - UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START - UML_JMPc(block, COND_B, label); // jb label3 - UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END - UML_JMPc(block, COND_A, label); // ja label3 + UML_LABEL(block, label++); // label2: + UML_CMP(block, I1, IRAM_BLOCK1_START); // cmp i1,IRAM_BLOCK1_START + UML_JMPc(block, COND_B, label); // jb label3 + UML_CMP(block, I1, IRAM_BLOCK1_END); // cmp i1,IRAM_BLOCK1_END + UML_JMPc(block, COND_A, label); // ja label3 // 0x28000 ... 0x3ffff - UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff - UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1_1],i1,i0,word,scale_x4 - UML_SHR(block, I0, I0, 16); // shr i0,i0,16 - UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1],i1,i0,word,scale_x4 + UML_AND(block, I1, I1, 0x7fff); // and i1,i1,0x7fff + UML_STORE(block, block1_1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1_1],i1,i0,word,scale_x4 + UML_SHR(block, I0, I0, 16); // shr i0,i0,16 + UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x4); // store [block1],i1,i0,word,scale_x4 UML_RET(block); - UML_LABEL(block, label++); // Label3: - UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END - UML_JMPc(block, COND_A, label); // ja label4 + UML_LABEL(block, label++); // Label3: + UML_CMP(block, I1, IOP_REGISTER_END); // cmp i1,IOP_REGISTER_END + UML_JMPc(block, COND_A, label); // ja label4 // IOP registers - UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1 - UML_MOV(block, mem(&m_core->arg1), I0); // mov [m_core->arg1],i0 - UML_CALLC(block, cfunc_write_iop, this); // callc cfunc_write_iop + UML_MOV(block, mem(&m_core->arg0), I1); // mov [m_core->arg0],i1 + UML_MOV(block, mem(&m_core->arg1), I0); // mov [m_core->arg1],i0 + UML_CALLC(block, cfunc_write_iop, this); // callc cfunc_write_iop UML_RET(block); - UML_LABEL(block, label++); // label4: - UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START - UML_JMPc(block, COND_B, label); // jb label5 - UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END - UML_JMPc(block, COND_A, label); // ja label5 + UML_LABEL(block, label++); // label4: + UML_CMP(block, I1, IRAM_SHORT_BLOCK0_START); // cmp i1,IRAM_SHORT_BLOCK0_START + UML_JMPc(block, COND_B, label); // jb label5 + UML_CMP(block, I1, IRAM_SHORT_BLOCK0_END); // cmp i1,IRAM_SHORT_BLOCK0_END + UML_JMPc(block, COND_A, label); // ja label5 // 0x40000 ... 0x4ffff - UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff - UML_XOR(block, I1, I1, 1); // xor i1,i1,1 - UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2 + UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff + UML_XOR(block, I1, I1, 1); // xor i1,i1,1 + UML_STORE(block, block0, I1, I0, SIZE_WORD, SCALE_x2); // store [block0],i1,i0,word,scale_x2 UML_RET(block); - UML_LABEL(block, label++); // label5: - UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START - UML_JMPc(block, COND_B, label); // jb label6 - UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END - UML_JMPc(block, COND_A, label); // ja label6 + UML_LABEL(block, label++); // label5: + UML_CMP(block, I1, IRAM_SHORT_BLOCK1_START); // cmp i1,IRAM_SHORT_BLOCK1_START + UML_JMPc(block, COND_B, label); // jb label6 + UML_CMP(block, I1, IRAM_SHORT_BLOCK1_END); // cmp i1,IRAM_SHORT_BLOCK1_END + UML_JMPc(block, COND_A, label); // ja label6 // 0x50000 ... 0x7ffff - UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff - UML_XOR(block, I1, I1, 1); // xor i1,i1,1 - UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2 + UML_AND(block, I1, I1, 0xffff); // and i1,i1,0xffff + UML_XOR(block, I1, I1, 1); // xor i1,i1,1 + UML_STORE(block, block1, I1, I0, SIZE_WORD, SCALE_x2); // store [block1],i1,i0,word,scale_x2 UML_RET(block); - UML_LABEL(block, label++); // label6: + UML_LABEL(block, label++); // label6: break; } @@ -664,26 +664,26 @@ void adsp21062_device::static_generate_push_pc() // add a global entry for this alloc_handle(m_drcuml.get(), &m_push_pc, "push_pc"); - UML_HANDLE(block, *m_push_pc); // handle *m_push_pc - - UML_MOV(block, I1, PCSTKP); // mov i1,PCSTKP - UML_ADD(block, I1, I1, 1); // add i1,i1,1 - UML_CMP(block, I1, 32); // cmp i1,32 - UML_JMPc(block, COND_L,label); // jl label1 - UML_CALLC(block, cfunc_pcstack_overflow, this); // callc cfunc_pcstack_overflow - - UML_LABEL(block, label++); // label1: - UML_CMP(block, I1, 0); // cmp i1,0 - UML_JMPc(block, COND_E, label); // je label2 - UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000 - UML_JMP(block, label + 1); // jmp label3 - UML_LABEL(block, label++); // label2: - UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000 - - UML_LABEL(block, label++); // label3: - UML_MOV(block, PCSTK, I0); // mov PCSTK,pc - UML_STORE(block, &m_core->pcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store [m_core->pcstack],i1,i0,dword,scale_x4 - UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1 + UML_HANDLE(block, *m_push_pc); // handle *m_push_pc + + UML_MOV(block, I1, PCSTKP); // mov i1,PCSTKP + UML_ADD(block, I1, I1, 1); // add i1,i1,1 + UML_CMP(block, I1, 32); // cmp i1,32 + UML_JMPc(block, COND_L,label); // jl label1 + UML_CALLC(block, cfunc_pcstack_overflow, this); // callc cfunc_pcstack_overflow + + UML_LABEL(block, label++); // label1: + UML_CMP(block, I1, 0); // cmp i1,0 + UML_JMPc(block, COND_E, label); // je label2 + UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000 + UML_JMP(block, label + 1); // jmp label3 + UML_LABEL(block, label++); // label2: + UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000 + + UML_LABEL(block, label++); // label3: + UML_MOV(block, PCSTK, I0); // mov PCSTK,pc + UML_STORE(block, &m_core->pcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store [m_core->pcstack],i1,i0,dword,scale_x4 + UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1 UML_RET(block); @@ -700,26 +700,26 @@ void adsp21062_device::static_generate_pop_pc() // add a global entry for this alloc_handle(m_drcuml.get(), &m_pop_pc, "pop_pc"); - UML_HANDLE(block, *m_pop_pc); // handle *m_pop_pc - - UML_MOV(block, I1, PCSTKP); // mov i0,PCSTKP - UML_LOAD(block, I0, &m_core->pcstack, I1, SIZE_DWORD, SCALE_x4); // load i1,[m_core->pcstack],i0,dword,scale_x4 - UML_CMP(block, I1, 0); // cmp i1,0 - UML_JMPc(block, COND_NE, label); // jne label1 - UML_CALLC(block, cfunc_pcstack_underflow, this); // callc cfunc_pcstack_underflow - - UML_LABEL(block, label++); // label1: - UML_SUB(block, I1, I1, 1); // sub i1,i1,1 - UML_CMP(block, I1, 0); // cmp i1,0 - UML_JMPc(block, COND_E, label); // je label2 - UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000 - UML_JMP(block, label + 1); // jmp label3 - UML_LABEL(block, label++); // label2: - UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000 - - UML_LABEL(block, label++); // label3: - UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1 - UML_MOV(block, PCSTK, I0); // mov PCSTK,i0 + UML_HANDLE(block, *m_pop_pc); // handle *m_pop_pc + + UML_MOV(block, I1, PCSTKP); // mov i0,PCSTKP + UML_LOAD(block, I0, &m_core->pcstack, I1, SIZE_DWORD, SCALE_x4); // load i1,[m_core->pcstack],i0,dword,scale_x4 + UML_CMP(block, I1, 0); // cmp i1,0 + UML_JMPc(block, COND_NE, label); // jne label1 + UML_CALLC(block, cfunc_pcstack_underflow, this); // callc cfunc_pcstack_underflow + + UML_LABEL(block, label++); // label1: + UML_SUB(block, I1, I1, 1); // sub i1,i1,1 + UML_CMP(block, I1, 0); // cmp i1,0 + UML_JMPc(block, COND_E, label); // je label2 + UML_AND(block, STKY, STKY, ~0x400000); // and STKY,~0x400000 + UML_JMP(block, label + 1); // jmp label3 + UML_LABEL(block, label++); // label2: + UML_OR(block, STKY, STKY, 0x400000); // or STKY,0x400000 + + UML_LABEL(block, label++); // label3: + UML_MOV(block, PCSTKP, I1); // mov PCSTKP,i1 + UML_MOV(block, PCSTK, I0); // mov PCSTK,i0 UML_RET(block); @@ -737,28 +737,28 @@ void adsp21062_device::static_generate_push_loop() // add a global entry for this alloc_handle(m_drcuml.get(), &m_push_loop, "push_loop"); - UML_HANDLE(block, *m_push_loop); // handle *m_push_loop + UML_HANDLE(block, *m_push_loop); // handle *m_push_loop - UML_MOV(block, I2, LSTKP); // mov i2,LSTKP - UML_ADD(block, I2, I2, 1); // add i2,1 - UML_CMP(block, I2, 6); // cmp i2,6 - UML_JMPc(block, COND_L, label); // jl label1 - UML_CALLC(block, cfunc_loopstack_overflow, this); // callc cfunc_loopstack_overflow + UML_MOV(block, I2, LSTKP); // mov i2,LSTKP + UML_ADD(block, I2, I2, 1); // add i2,1 + UML_CMP(block, I2, 6); // cmp i2,6 + UML_JMPc(block, COND_L, label); // jl label1 + UML_CALLC(block, cfunc_loopstack_overflow, this); // callc cfunc_loopstack_overflow - UML_LABEL(block, label++); // label1: - UML_CMP(block, I2, 0); // cmp i2,0 - UML_JMPc(block, COND_E, label); // je label2 - UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000 - UML_JMP(block, label + 1); // jmp label3 - UML_LABEL(block, label++); // label2: - UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000 + UML_LABEL(block, label++); // label1: + UML_CMP(block, I2, 0); // cmp i2,0 + UML_JMPc(block, COND_E, label); // je label2 + UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000 + UML_JMP(block, label + 1); // jmp label3 + UML_LABEL(block, label++); // label2: + UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000 - UML_LABEL(block, label++); // label3: + UML_LABEL(block, label++); // label3: - UML_STORE(block, m_core->lcstack, I2, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i2,i0,dword,scale_x4 - UML_STORE(block, m_core->lastack, I2, I1, SIZE_DWORD, SCALE_x4); // store m_core->lastack,i2,i1,dword,scale_x4 - UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0 - UML_MOV(block, LSTKP, I2); // mov LSTKP,i2 + UML_STORE(block, m_core->lcstack, I2, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i2,i0,dword,scale_x4 + UML_STORE(block, m_core->lastack, I2, I1, SIZE_DWORD, SCALE_x4); // store m_core->lastack,i2,i1,dword,scale_x4 + UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0 + UML_MOV(block, LSTKP, I2); // mov LSTKP,i2 UML_RET(block); @@ -774,26 +774,26 @@ void adsp21062_device::static_generate_pop_loop() // add a global entry for this alloc_handle(m_drcuml.get(), &m_pop_loop, "pop_loop"); - UML_HANDLE(block, *m_pop_loop); // handle *m_pop_loop - - UML_MOV(block, I2, LSTKP); // mov i2,LSTKP - UML_CMP(block, I2, 0); // cmp i2,0 - UML_JMPc(block, COND_NE, label); // jne label1 - UML_CALLC(block, cfunc_loopstack_underflow, this); // callc cfunc_loopstack_underflow - - UML_LABEL(block, label++); // label1: - UML_SUB(block, I2, I2, 1); // sub i2,i2,1 - UML_CMP(block, I2, 0); // cmp i2,0 - UML_JMPc(block, COND_E, label); // je label2 - UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000 - UML_JMP(block, label + 1); // jmp label3 - UML_LABEL(block, label++); // label2: - UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000 - - UML_LABEL(block, label++); // label3: - UML_LOAD(block, I0, m_core->lcstack, I2, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i2,dword,scale_x4 - UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0 - UML_MOV(block, LSTKP, I2); // mov LSTKP,i2 + UML_HANDLE(block, *m_pop_loop); // handle *m_pop_loop + + UML_MOV(block, I2, LSTKP); // mov i2,LSTKP + UML_CMP(block, I2, 0); // cmp i2,0 + UML_JMPc(block, COND_NE, label); // jne label1 + UML_CALLC(block, cfunc_loopstack_underflow, this); // callc cfunc_loopstack_underflow + + UML_LABEL(block, label++); // label1: + UML_SUB(block, I2, I2, 1); // sub i2,i2,1 + UML_CMP(block, I2, 0); // cmp i2,0 + UML_JMPc(block, COND_E, label); // je label2 + UML_AND(block, STKY, STKY, ~0x4000000); // and STKY,~0x4000000 + UML_JMP(block, label + 1); // jmp label3 + UML_LABEL(block, label++); // label2: + UML_OR(block, STKY, STKY, 0x4000000); // or STKY,0x4000000 + + UML_LABEL(block, label++); // label3: + UML_LOAD(block, I0, m_core->lcstack, I2, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i2,dword,scale_x4 + UML_MOV(block, CURLCNTR, I0); // mov CURLCNTR,i0 + UML_MOV(block, LSTKP, I2); // mov LSTKP,i2 UML_RET(block); @@ -809,24 +809,24 @@ void adsp21062_device::static_generate_push_status() // add a global entry for this alloc_handle(m_drcuml.get(), &m_push_status, "push_status"); - UML_HANDLE(block, *m_push_status); // handle *m_push_status + UML_HANDLE(block, *m_push_status); // handle *m_push_status - UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp] - UML_ADD(block, I2, I2, 1); // add i2,1 - UML_CMP(block, I2, 5); // cmp i2,5 - UML_JMPc(block, COND_L, label); // jl label1 - UML_CALLC(block, cfunc_statusstack_overflow, this); // callc cfunc_statusstack_overflow + UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp] + UML_ADD(block, I2, I2, 1); // add i2,1 + UML_CMP(block, I2, 5); // cmp i2,5 + UML_JMPc(block, COND_L, label); // jl label1 + UML_CALLC(block, cfunc_statusstack_overflow, this); // callc cfunc_statusstack_overflow - UML_LABEL(block, label++); // label1: - UML_CMP(block, I2, 0); // cmp i2,0 - UML_JMPc(block, COND_E, label); // je label2 - UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000 - UML_JMP(block, label + 1); // jmp label3 - UML_LABEL(block, label++); // label2: - UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000 + UML_LABEL(block, label++); // label1: + UML_CMP(block, I2, 0); // cmp i2,0 + UML_JMPc(block, COND_E, label); // je label2 + UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000 + UML_JMP(block, label + 1); // jmp label3 + UML_LABEL(block, label++); // label2: + UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000 - UML_LABEL(block, label++); // label3: - UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2 + UML_LABEL(block, label++); // label3: + UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2 //TODO: load MODE1 //TODO: load ASTAT @@ -845,27 +845,27 @@ void adsp21062_device::static_generate_pop_status() // add a global entry for this alloc_handle(m_drcuml.get(), &m_pop_status, "pop_status"); - UML_HANDLE(block, *m_pop_status); // handle *m_pop_status + UML_HANDLE(block, *m_pop_status); // handle *m_pop_status //TODO: store MODE1 //TODO: store ASTAT - - UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp] - UML_CMP(block, I2, 0); // cmp i2,0 - UML_JMPc(block, COND_NE, label); // jl label1 - UML_CALLC(block, cfunc_statusstack_underflow, this); // callc cfunc_statusstack_underflow - - UML_LABEL(block, label++); // label1: - UML_SUB(block, I2, I2, 1); // sub i2,1 - UML_CMP(block, I2, 0); // cmp i2,0 - UML_JMPc(block, COND_E, label); // je label2 - UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000 - UML_JMP(block, label + 1); // jmp label3 - UML_LABEL(block, label++); // label2: - UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000 - - UML_LABEL(block, label++); // label3: - UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2 + + UML_MOV(block, I2, mem(&m_core->status_stkp)); // mov i2,[status_stkp] + UML_CMP(block, I2, 0); // cmp i2,0 + UML_JMPc(block, COND_NE, label); // jl label1 + UML_CALLC(block, cfunc_statusstack_underflow, this); // callc cfunc_statusstack_underflow + + UML_LABEL(block, label++); // label1: + UML_SUB(block, I2, I2, 1); // sub i2,1 + UML_CMP(block, I2, 0); // cmp i2,0 + UML_JMPc(block, COND_E, label); // je label2 + UML_AND(block, STKY, STKY, ~0x1000000); // and STKY,~0x1000000 + UML_JMP(block, label + 1); // jmp label3 + UML_LABEL(block, label++); // label2: + UML_OR(block, STKY, STKY, 0x1000000); // or STKY,0x1000000 + + UML_LABEL(block, label++); // label3: + UML_MOV(block, mem(&m_core->status_stkp), I2); // mov [status_stkp],i2 UML_RET(block); @@ -886,30 +886,30 @@ void adsp21062_device::static_generate_exception(UINT8 exception, const char *na /* add a global entry for this */ alloc_handle(m_drcuml.get(), &exception_handle, name); - UML_HANDLE(block, *exception_handle); // handle name + UML_HANDLE(block, *exception_handle); // handle name - UML_AND(block, I3, mem(&m_core->irq_pending), IMASK); // and i3,[irq_pending],IMASK - UML_TZCNT(block, I3, I3); // tzcnt i3,i3 + UML_AND(block, I3, mem(&m_core->irq_pending), IMASK); // and i3,[irq_pending],IMASK + UML_TZCNT(block, I3, I3); // tzcnt i3,i3 - UML_MOV(block, I2, 1); // mov i2,1 - UML_SHL(block, I2, I2, I3); // shl i2,i2,i3 - UML_OR(block, IRPTL, IRPTL, I2); // or IRPTL,i2 + UML_MOV(block, I2, 1); // mov i2,1 + UML_SHL(block, I2, I2, I3); // shl i2,i2,i3 + UML_OR(block, IRPTL, IRPTL, I2); // or IRPTL,i2 UML_XOR(block, mem(&m_core->irq_pending), mem(&m_core->irq_pending), I2); // xor [irq_pending],i2 - UML_MOV(block, mem(&m_core->active_irq_num), I3); // mov [active_irq_num],i3 - UML_MOV(block, mem(&m_core->interrupt_active), 1); // mov [interrupt_active],1 + UML_MOV(block, mem(&m_core->active_irq_num), I3); // mov [active_irq_num],i3 + UML_MOV(block, mem(&m_core->interrupt_active), 1); // mov [interrupt_active],1 - UML_CALLH(block, *m_push_pc); // callh m_push_pc + UML_CALLH(block, *m_push_pc); // callh m_push_pc - UML_CMP(block, I3, 6); // cmp i3,6 - UML_JMPc(block, COND_L, label_nopush); // jl label_nopush - UML_CMP(block, I3, 8); // cmp i3,8 - UML_JMPc(block, COND_G, label_nopush); // jg label_nopush - UML_CALLH(block, *m_push_status); // callh m_push_status + UML_CMP(block, I3, 6); // cmp i3,6 + UML_JMPc(block, COND_L, label_nopush); // jl label_nopush + UML_CMP(block, I3, 8); // cmp i3,8 + UML_JMPc(block, COND_G, label_nopush); // jg label_nopush + UML_CALLH(block, *m_push_status); // callh m_push_status - UML_LABEL(block, label_nopush); // label_nopush: - UML_SHL(block, I0, I3, 2); // shl i0,i3,2 - UML_ADD(block, I0, I0, 0x20000); // add i0,0x20000 - UML_HASHJMP(block, 0, I0, *m_nocode); // hashjmp i0,m_nocode + UML_LABEL(block, label_nopush); // label_nopush: + UML_SHL(block, I0, I3, 2); // shl i0,i3,2 + UML_ADD(block, I0, I0, 0x20000); // add i0,0x20000 + UML_HASHJMP(block, 0, I0, *m_nocode); // hashjmp i0,m_nocode block->end(); } @@ -924,7 +924,7 @@ void adsp21062_device::static_generate_mode1_ops() block = m_drcuml->begin_block(128); alloc_handle(m_drcuml.get(), &m_swap_dag1_0_3, "swap_dag1_0_3"); - UML_HANDLE(block, *m_swap_dag1_0_3); // handle name + UML_HANDLE(block, *m_swap_dag1_0_3); // handle name #if !USE_SWAPDQ for (int i = 0; i < 4; i++) { @@ -956,7 +956,7 @@ void adsp21062_device::static_generate_mode1_ops() block = m_drcuml->begin_block(128); alloc_handle(m_drcuml.get(), &m_swap_dag1_4_7, "swap_dag1_4_7"); - UML_HANDLE(block, *m_swap_dag1_4_7); // handle name + UML_HANDLE(block, *m_swap_dag1_4_7); // handle name #if !USE_SWAPDQ for (int i = 4; i < 8; i++) { @@ -988,7 +988,7 @@ void adsp21062_device::static_generate_mode1_ops() block = m_drcuml->begin_block(128); alloc_handle(m_drcuml.get(), &m_swap_dag2_0_3, "swap_dag2_0_3"); - UML_HANDLE(block, *m_swap_dag2_0_3); // handle name + UML_HANDLE(block, *m_swap_dag2_0_3); // handle name #if !USE_SWAPDQ for (int i = 0; i < 4; i++) { @@ -1020,7 +1020,7 @@ void adsp21062_device::static_generate_mode1_ops() block = m_drcuml->begin_block(128); alloc_handle(m_drcuml.get(), &m_swap_dag2_4_7, "swap_dag2_4_7"); - UML_HANDLE(block, *m_swap_dag2_4_7); // handle name + UML_HANDLE(block, *m_swap_dag2_4_7); // handle name #if !USE_SWAPDQ for (int i = 4; i < 8; i++) { @@ -1052,7 +1052,7 @@ void adsp21062_device::static_generate_mode1_ops() block = m_drcuml->begin_block(64); alloc_handle(m_drcuml.get(), &m_swap_r0_7, "swap_r0_7"); - UML_HANDLE(block, *m_swap_r0_7); // handle name + UML_HANDLE(block, *m_swap_r0_7); // handle name #if !USE_SWAPDQ for (int i = 0; i < 8; i++) { @@ -1070,7 +1070,7 @@ void adsp21062_device::static_generate_mode1_ops() block = m_drcuml->begin_block(64); alloc_handle(m_drcuml.get(), &m_swap_r8_15, "swap_r8_15"); - UML_HANDLE(block, *m_swap_r8_15); // handle name + UML_HANDLE(block, *m_swap_r8_15); // handle name #if !USE_SWAPDQ for (int i = 8; i < 16; i++) { @@ -1095,8 +1095,8 @@ void adsp21062_device::execute_run_drc() drcuml_state *drcuml = m_drcuml.get(); int execute_result; -// if (m_cache_dirty) -// printf("SHARC cache reset\n"); +// if (m_cache_dirty) +// printf("SHARC cache reset\n"); /* reset the cache if dirty */ if (m_cache_dirty) @@ -1173,7 +1173,7 @@ void adsp21062_device::compile_block(offs_t pc) else { UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc - UML_HASHJMP(block, 0, seqhead->pc, *m_nocode); // hashjmp <0>,seqhead->pc,nocode + UML_HASHJMP(block, 0, seqhead->pc, *m_nocode); // hashjmp <0>,seqhead->pc,nocode continue; } @@ -1202,10 +1202,10 @@ void adsp21062_device::compile_block(offs_t pc) /* count off cycles and go there */ - generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles> + generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles> if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc) - UML_HASHJMP(block, 0, nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode + UML_HASHJMP(block, 0, nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode } block->end(); @@ -1271,23 +1271,23 @@ void adsp21062_device::static_generate_entry_point() alloc_handle(m_drcuml.get(), &m_exception[EXCEPTION_INTERRUPT], "exception_interrupt"); alloc_handle(m_drcuml.get(), &m_entry, "entry"); - UML_HANDLE(block, *m_entry); // handle entry + UML_HANDLE(block, *m_entry); // handle entry - load_fast_iregs(block); // <load fastregs> + load_fast_iregs(block); // <load fastregs> - /* check for interrupts */ - UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0 - UML_JMPc(block, COND_E, skip); // je skip - UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0 - UML_JMPc(block, COND_NE, skip); // jne skip - UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK - UML_JMPc(block, COND_Z, skip); // jz skip - UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN - UML_JMPc(block, COND_Z, skip); // jz skip + /* check for interrupts */ + UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0 + UML_JMPc(block, COND_E, skip); // je skip + UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0 + UML_JMPc(block, COND_NE, skip); // jne skip + UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK + UML_JMPc(block, COND_Z, skip); // jz skip + UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN + UML_JMPc(block, COND_Z, skip); // jz skip - UML_MOV(block, I0, mem(&m_core->pc)); // mov i0,nextpc - UML_MOV(block, I1, 0); // mov i1,0 - UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT] + UML_MOV(block, I0, mem(&m_core->pc)); // mov i0,nextpc + UML_MOV(block, I1, 0); // mov i1,0 + UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT] UML_LABEL(block, skip); @@ -1307,11 +1307,11 @@ void adsp21062_device::static_generate_nocode_handler() /* generate a hash jump via the current mode and PC */ alloc_handle(m_drcuml.get(), &m_nocode, "nocode"); - UML_HANDLE(block, *m_nocode); // handle nocode - UML_GETEXP(block, I0); // getexp i0 - UML_MOV(block, mem(&m_core->pc), I0); // mov [pc],i0 - save_fast_iregs(block); // <save fastregs> - UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE + UML_HANDLE(block, *m_nocode); // handle nocode + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&m_core->pc), I0); // mov [pc],i0 + save_fast_iregs(block); // <save fastregs> + UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); } @@ -1325,11 +1325,11 @@ void adsp21062_device::static_generate_out_of_cycles() /* generate a hash jump via the current mode and PC */ alloc_handle(m_drcuml.get(), &m_out_of_cycles, "out_of_cycles"); - UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles - UML_GETEXP(block, I0); // getexp i0 - UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0 - save_fast_iregs(block); // <save fastregs> - UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES + UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles + UML_GETEXP(block, I0); // getexp i0 + UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0 + save_fast_iregs(block); // <save fastregs> + UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES block->end(); } @@ -1338,8 +1338,8 @@ void adsp21062_device::static_generate_out_of_cycles() void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool last_delayslot) { /* add an entry for the log */ -// if (m_drcuml->logging() && !(desc->flags & OPFLAG_VIRTUAL_NOOP)) -// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]); +// if (m_drcuml->logging() && !(desc->flags & OPFLAG_VIRTUAL_NOOP)) +// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]); /* set the PC map variable */ UML_MAPVAR(block, MAPVAR_PC, desc->pc); // mapvar PC,desc->pc @@ -1353,17 +1353,17 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil /* if we are debugging, call the debugger */ if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) { - UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc - save_fast_iregs(block); // <save fastregs> - UML_DEBUG(block, desc->pc); // debug desc->pc + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + save_fast_iregs(block); // <save fastregs> + UML_DEBUG(block, desc->pc); // debug desc->pc } /* if we hit an unmapped address, fatal error */ if (desc->flags & OPFLAG_COMPILER_UNMAPPED) { - UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc - save_fast_iregs(block); // <save fastregs> - UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + save_fast_iregs(block); // <save fastregs> + UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE } // handle a special case where call is used as the last operation in a loop @@ -1377,19 +1377,19 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil UML_JMPc(block, COND_NE, end); code_label label_expire = compiler->labelnum++; - UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp] - UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4 - UML_SUB(block, I0, I0, 1); // sub i0,1 - UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4 - UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1 - UML_JMPc(block, COND_E, label_expire); // jne label_expire + UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp] + UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4 + UML_SUB(block, I0, I0, 1); // sub i0,1 + UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4 + UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1 + UML_JMPc(block, COND_E, label_expire); // jne label_expire UML_MOV(block, mem(&m_core->temp_return), desc->userdata0); UML_JMP(block, end); - UML_LABEL(block, label_expire); // label_expire: - UML_CALLH(block, *m_pop_pc); // callh m_pop_pc - UML_CALLH(block, *m_pop_loop); // callh m_pop_loop + UML_LABEL(block, label_expire); // label_expire: + UML_CALLH(block, *m_pop_pc); // callh m_pop_pc + UML_CALLH(block, *m_pop_loop); // callh m_pop_loop UML_MOV(block, mem(&m_core->temp_return), desc->pc + 1); UML_LABEL(block, end); @@ -1418,8 +1418,8 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil } /* if this is an invalid opcode, generate the exception now */ -// if (desc->flags & OPFLAG_INVALID_OPCODE) -// UML_EXH(block, *m_exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000 +// if (desc->flags & OPFLAG_INVALID_OPCODE) +// UML_EXH(block, *m_exception[EXCEPTION_PROGRAM], 0x80000); // exh exception_program,0x80000 /* unless this is a virtual no-op, it's a regular instruction */ if (!(desc->flags & OPFLAG_VIRTUAL_NOOP)) @@ -1427,9 +1427,9 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil /* compile the instruction */ if (!generate_opcode(block, compiler, desc)) { - UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc - UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]); // dmov [arg64],*desc->opptr.q - UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]); // dmov [arg64],*desc->opptr.q + UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented,ppc } } @@ -1438,7 +1438,7 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil if (compiler->mode1_delay.counter > 0) { compiler->mode1_delay.counter--; - + // delayed operation in the last delay slot needs to be done before the branch is taken if (last_delayslot) compiler->mode1_delay.counter = 0; @@ -1467,7 +1467,7 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil } - // insert loop check at this instruction if needed + // insert loop check at this instruction if needed if (desc->userflags & OP_USERFLAG_COUNTER_LOOP) { code_label label_skip_loop = compiler->labelnum++; @@ -1476,18 +1476,18 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil UML_JMPc(block, COND_NE, label_skip_loop); code_label label_expire = compiler->labelnum++; - UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp] - UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4 - UML_SUB(block, I0, I0, 1); // sub i0,1 - UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4 - UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1 - UML_JMPc(block, COND_E, label_expire); // jne label_expire + UML_MOV(block, I1, mem(&m_core->lstkp)); // mov i1,[m_core->lstkp] + UML_LOAD(block, I0, m_core->lcstack, I1, SIZE_DWORD, SCALE_x4); // load i0,m_core->lcstack,i1,dword,scale_x4 + UML_SUB(block, I0, I0, 1); // sub i0,1 + UML_STORE(block, m_core->lcstack, I1, I0, SIZE_DWORD, SCALE_x4); // store m_core->lcstack,i1,i0,dword,scale_x4 + UML_SUB(block, CURLCNTR, CURLCNTR, 1); // sub CURLCNTR,1 + UML_JMPc(block, COND_E, label_expire); // jne label_expire generate_loop_jump(block, compiler, desc); - UML_LABEL(block, label_expire); // label_expire: - UML_CALLH(block, *m_pop_pc); // callh m_pop_pc - UML_CALLH(block, *m_pop_loop); // callh m_pop_loop + UML_LABEL(block, label_expire); // label_expire: + UML_CALLH(block, *m_pop_pc); // callh m_pop_pc + UML_CALLH(block, *m_pop_loop); // callh m_pop_loop UML_LABEL(block, label_skip_loop); } @@ -1544,18 +1544,18 @@ void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_stat code_label skip = compiler->labelnum++; compiler->checkints = FALSE; - UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0 - UML_JMPc(block, COND_E, skip); // je skip - UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0 - UML_JMPc(block, COND_NE, skip); // jne skip - UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK - UML_JMPc(block, COND_Z, skip); // jz skip - UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN - UML_JMPc(block, COND_Z, skip); // jz skip + UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0 + UML_JMPc(block, COND_E, skip); // je skip + UML_CMP(block, mem(&m_core->interrupt_active), 0); // cmp [interrupt_active],0 + UML_JMPc(block, COND_NE, skip); // jne skip + UML_TEST(block, mem(&m_core->irq_pending), IMASK); // test [irq_pending],IMASK + UML_JMPc(block, COND_Z, skip); // jz skip + UML_TEST(block, mem(&m_core->mode1), MODE1_IRPTEN); // test MODE1,MODE1_IRPTEN + UML_JMPc(block, COND_Z, skip); // jz skip - UML_MOV(block, I0, param); // mov i0,nextpc - UML_MOV(block, I1, compiler->cycles); // mov i1,cycles - UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT] + UML_MOV(block, I0, param); // mov i0,nextpc + UML_MOV(block, I1, compiler->cycles); // mov i1,cycles + UML_CALLH(block, *m_exception[EXCEPTION_INTERRUPT]); // callh m_exception[EXCEPTION_INTERRUPT] UML_LABEL(block, skip); } @@ -1563,10 +1563,10 @@ void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_stat /* account for cycles */ if (compiler->cycles > 0) { - UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES); // sub icount,icount,cycles - UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 + UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES); // sub icount,icount,cycles + UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 if (allow_exception) - UML_EXHc(block, COND_S, *m_out_of_cycles, param); // exh out_of_cycles,nextpc + UML_EXHc(block, COND_S, *m_out_of_cycles, param); // exh out_of_cycles,nextpc } compiler->cycles = 0; } @@ -1586,42 +1586,42 @@ void adsp21062_device::generate_write_mode1_imm(drcuml_block *block, compiler_st // DAG1 regs 4-7 skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x8); - UML_JMPc(block, (data & 0x8) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same + UML_JMPc(block, (data & 0x8) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same UML_CALLH(block, *m_swap_dag1_4_7); UML_LABEL(block, skip); // DAG1 regs 0-3 skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x10); - UML_JMPc(block, (data & 0x10) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same + UML_JMPc(block, (data & 0x10) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same UML_CALLH(block, *m_swap_dag1_0_3); UML_LABEL(block, skip); // DAG2 regs 4-7 skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x20); - UML_JMPc(block, (data & 0x20) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same + UML_JMPc(block, (data & 0x20) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same UML_CALLH(block, *m_swap_dag2_4_7); UML_LABEL(block, skip); // DAG2 regs 0-3 skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x40); - UML_JMPc(block, (data & 0x40) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same + UML_JMPc(block, (data & 0x40) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same UML_CALLH(block, *m_swap_dag2_0_3); UML_LABEL(block, skip); // REG 8-15 skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x80); - UML_JMPc(block, (data & 0x80) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same + UML_JMPc(block, (data & 0x80) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same UML_CALLH(block, *m_swap_r8_15); UML_LABEL(block, skip); // REG 0-7 skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x400); - UML_JMPc(block, (data & 0x400) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same + UML_JMPc(block, (data & 0x400) ? COND_NZ : COND_Z, skip); // don't swap if the bits are same UML_CALLH(block, *m_swap_r0_7); UML_LABEL(block, skip); @@ -1636,51 +1636,51 @@ void adsp21062_device::generate_set_mode1_imm(drcuml_block *block, compiler_stat fatalerror("generate_set_mode1_imm: tried to enable I0 bit reversing"); if (data & 0x4) fatalerror("generate_set_mode1_imm: tried to enable MR alternate"); - if (data & 0x8) // DAG1 regs 4-7 + if (data & 0x8) // DAG1 regs 4-7 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x8); - UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 + UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 UML_CALLH(block, *m_swap_dag1_4_7); UML_LABEL(block, skip); } - if (data & 0x10) // DAG1 regs 0-3 + if (data & 0x10) // DAG1 regs 0-3 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x10); - UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 + UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 UML_CALLH(block, *m_swap_dag1_0_3); UML_LABEL(block, skip); } - if (data & 0x20) // DAG2 regs 4-7 + if (data & 0x20) // DAG2 regs 4-7 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x20); - UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 + UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 UML_CALLH(block, *m_swap_dag2_4_7); UML_LABEL(block, skip); } - if (data & 0x40) // DAG1 regs 0-3 + if (data & 0x40) // DAG1 regs 0-3 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x40); - UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 + UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 UML_CALLH(block, *m_swap_dag2_0_3); UML_LABEL(block, skip); } - if (data & 0x80) // REG 8-15 + if (data & 0x80) // REG 8-15 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x80); - UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 + UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 UML_CALLH(block, *m_swap_r8_15); UML_LABEL(block, skip); } - if (data & 0x400) // REG 0-7 + if (data & 0x400) // REG 0-7 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x400); - UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 + UML_JMPc(block, COND_NZ, skip); // don't swap if the bit is already 1 UML_CALLH(block, *m_swap_r0_7); UML_LABEL(block, skip); } @@ -1696,51 +1696,51 @@ void adsp21062_device::generate_clear_mode1_imm(drcuml_block *block, compiler_st fatalerror("generate_clear_mode1_imm: tried to disable I0 bit reversing"); if (data & 0x4) fatalerror("generate_clear_mode1_imm: tried to disable MR alternate"); - if (data & 0x8) // DAG1 regs 4-7 + if (data & 0x8) // DAG1 regs 4-7 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x8); - UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 + UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 UML_CALLH(block, *m_swap_dag1_4_7); UML_LABEL(block, skip); } - if (data & 0x10) // DAG1 regs 0-3 + if (data & 0x10) // DAG1 regs 0-3 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x10); - UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 + UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 UML_CALLH(block, *m_swap_dag1_0_3); UML_LABEL(block, skip); } - if (data & 0x20) // DAG2 regs 4-7 + if (data & 0x20) // DAG2 regs 4-7 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x20); - UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 + UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 UML_CALLH(block, *m_swap_dag2_4_7); UML_LABEL(block, skip); } - if (data & 0x40) // DAG1 regs 0-3 + if (data & 0x40) // DAG1 regs 0-3 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x40); - UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 + UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 UML_CALLH(block, *m_swap_dag2_0_3); UML_LABEL(block, skip); } - if (data & 0x80) // REG 8-15 + if (data & 0x80) // REG 8-15 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x80); - UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 + UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 UML_CALLH(block, *m_swap_r8_15); UML_LABEL(block, skip); } - if (data & 0x400) // REG 0-7 + if (data & 0x400) // REG 0-7 { code_label skip = compiler->labelnum++; UML_TEST(block, MODE1, 0x400); - UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 + UML_JMPc(block, COND_Z, skip); // don't swap if the bit is already 0 UML_CALLH(block, *m_swap_r0_7); UML_LABEL(block, skip); } @@ -1827,7 +1827,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil // save branch target if (desc->targetpc == BRANCH_TARGET_DYNAMIC) { - UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0 + UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0 } // compile delay slots if needed @@ -1847,7 +1847,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil if (delayslot) UML_MOV(block, I0, desc->pc + 3); else - UML_MOV(block, I0, desc->pc + 1); + UML_MOV(block, I0, desc->pc + 1); } UML_CALLH(block, *m_push_pc); @@ -1856,14 +1856,14 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil { generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) - UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000 + UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000 else - UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode + UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode } else { generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE); - UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode + UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode } // update compiler label @@ -1871,7 +1871,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil /* reset the mapvar to the current cycles and account for skipped slots */ compiler->cycles += desc->skipslots; - UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles + UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles } void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool delayslot, bool loopabort, bool clearint) @@ -1883,7 +1883,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil // save branch target if (desc->targetpc == BRANCH_TARGET_DYNAMIC) { - UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0 + UML_MOV(block, mem(&m_core->jmpdest), I0); // mov [jmpdest],i0 } // compile delay slots if needed @@ -1898,13 +1898,13 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil { code_label skip_pop = compiler_temp.labelnum++; - UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0 - UML_SHL(block, I1, 1, mem(&m_core->active_irq_num)); // shl i1,1,[active_irq_num] - UML_XOR(block, IRPTL, IRPTL, I1); // xor IRPTL,i1 - UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0 - UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop - UML_CALLH(block, *m_pop_status); // callh m_pop_status - UML_LABEL(block, skip_pop); // skip_pop: + UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0 + UML_SHL(block, I1, 1, mem(&m_core->active_irq_num)); // shl i1,1,[active_irq_num] + UML_XOR(block, IRPTL, IRPTL, I1); // xor IRPTL,i1 + UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0 + UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop + UML_CALLH(block, *m_pop_status); // callh m_pop_status + UML_LABEL(block, skip_pop); // skip_pop: } // loop abort @@ -1919,14 +1919,14 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil { generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) - UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000 + UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000 else - UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode + UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode } else { generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE); - UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode + UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode } // update compiler label @@ -1934,7 +1934,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil /* reset the mapvar to the current cycles and account for skipped slots */ compiler->cycles += desc->skipslots; - UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles + UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles } void adsp21062_device::generate_loop_jump(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) @@ -1943,15 +1943,15 @@ void adsp21062_device::generate_loop_jump(drcuml_block *block, compiler_state *c generate_update_cycles(block, compiler, desc->userdata0, TRUE); /* if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) - UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000 + UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000 else - UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode - */ + UML_HASHJMP(block, 0, desc->targetpc, *m_nocode); // hashjmp 0,targetpc,nocode + */ UML_HASHJMP(block, 0, desc->userdata0, *m_nocode); /* reset the mapvar to the current cycles and account for skipped slots */ compiler->cycles += desc->skipslots; - UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles + UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles } /*------------------------------------------------- @@ -2002,25 +2002,25 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c UML_MOV(block, I0, mem(&m_core->dag2.b[ureg & 7])); break; - case 0x64: // PCSTK + case 0x64: // PCSTK UML_LOAD(block, I0, &m_core->pcstack, PCSTKP, SIZE_DWORD, SCALE_x4); break; - case 0x70: // USTAT1 + case 0x70: // USTAT1 UML_MOV(block, I0, mem(&m_core->ustat1)); break; - case 0x71: // USTAT2 + case 0x71: // USTAT2 UML_MOV(block, I0, mem(&m_core->ustat2)); break; - case 0x79: // IRPTL + case 0x79: // IRPTL UML_MOV(block, I0, mem(&m_core->irptl)); break; - case 0x7a: // MODE2 + case 0x7a: // MODE2 UML_MOV(block, I0, mem(&m_core->mode2)); break; - case 0x7b: // MODE1 + case 0x7b: // MODE1 UML_MOV(block, I0, mem(&m_core->mode1)); break; - case 0x7c: // ASTAT + case 0x7c: // ASTAT // construct from bits if (!has_compute) { @@ -2111,20 +2111,20 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c UML_OR(block, I0, I0, I1); } break; - case 0x7d: // IMASK + case 0x7d: // IMASK UML_MOV(block, I0, mem(&m_core->imask)); break; - case 0x7e: // STKY + case 0x7e: // STKY UML_MOV(block, I0, mem(&m_core->stky)); break; - case 0xdb: // PX - UML_DMOV(block, I0, mem(&m_core->px)); // NOTE: this returns 64 bits + case 0xdb: // PX + UML_DMOV(block, I0, mem(&m_core->px)); // NOTE: this returns 64 bits break; - case 0xdc: // PX1 (bits 0-15 of PX) + case 0xdc: // PX1 (bits 0-15 of PX) UML_MOV(block, I0, mem(&m_core->px)); UML_AND(block, I0, I0, 0xffff); break; - case 0xdd: // PX2 (bits 16-47 of PX) + case 0xdd: // PX2 (bits 16-47 of PX) UML_DMOV(block, I0, mem(&m_core->px)); UML_DSHR(block, I0, I0, 16); UML_DAND(block, I0, I0, 0xffffffff); @@ -2138,7 +2138,7 @@ void adsp21062_device::generate_read_ureg(drcuml_block *block, compiler_state *c /*------------------------------------------------- - generate_write_ureg - contents of register I0 or 32-bit immediate data are written into UREG + generate_write_ureg - contents of register I0 or 32-bit immediate data are written into UREG -------------------------------------------------*/ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int ureg, bool imm, UINT32 data) @@ -2187,31 +2187,31 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state * UML_MOV(block, PM_B(ureg & 7), imm ? data : I0); break; - case 0x64: // PCSTK + case 0x64: // PCSTK fatalerror("generate_write_ureg: PCSTK"); break; - case 0x65: // PCSTKP + case 0x65: // PCSTKP UML_MOV(block, PCSTKP, imm ? data : I0); break; - case 0x67: // CURLCNTR + case 0x67: // CURLCNTR UML_MOV(block, CURLCNTR, imm ? data : I0); break; - case 0x68: // LCNTR + case 0x68: // LCNTR UML_MOV(block, LCNTR, imm ? data : I0); break; - case 0x70: // USTAT1 + case 0x70: // USTAT1 UML_MOV(block, mem(&m_core->ustat1), imm ? data : I0); break; - case 0x71: // USTAT2 + case 0x71: // USTAT2 UML_MOV(block, mem(&m_core->ustat2), imm ? data : I0); break; - case 0x79: // IRPTL + case 0x79: // IRPTL UML_MOV(block, mem(&m_core->irptl), imm ? data : I0); break; - case 0x7a: // MODE2 + case 0x7a: // MODE2 UML_MOV(block, mem(&m_core->mode2), imm ? data : I0); break; - case 0x7b: // MODE1 + case 0x7b: // MODE1 // MODE1 needs to be written delayed if (imm) { @@ -2226,17 +2226,17 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state * UML_MOV(block, mem(&m_core->mode1_delay_data), I0); } break; - case 0x7c: // ASTAT + case 0x7c: // ASTAT // TODO: needs bit break up fatalerror("generate_write_ureg: ASTAT"); break; - case 0x7d: // IMASK + case 0x7d: // IMASK UML_MOV(block, mem(&m_core->imask), imm ? data : I0); break; - case 0x7e: // STKY + case 0x7e: // STKY UML_MOV(block, mem(&m_core->stky), imm ? data : I0); break; - case 0xdb: // PX + case 0xdb: // PX if (imm) { fatalerror("generate_write_ureg %02X with immediate!", ureg); @@ -2246,7 +2246,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state * UML_DMOV(block, mem(&m_core->px), I0); } break; - case 0xdc: // PX1 (bits 0-15 of PX) + case 0xdc: // PX1 (bits 0-15 of PX) if (imm) { UML_DAND(block, mem(&m_core->px), mem(&m_core->px), ~0xffff); @@ -2260,7 +2260,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state * UML_DOR(block, mem(&m_core->px), mem(&m_core->px), I1); } break; - case 0xdd: // PX2 (bits 16-47 of PX) + case 0xdd: // PX2 (bits 16-47 of PX) if (imm) { UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff); @@ -2268,7 +2268,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state * } else { - UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff); + UML_DAND(block, mem(&m_core->px), mem(&m_core->px), 0xffff); UML_DSHL(block, I0, I0, 16); UML_DOR(block, mem(&m_core->px), mem(&m_core->px), I0); } @@ -2286,12 +2286,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi switch ((opcode >> 45) & 7) { - case 0: // subops + case 0: // subops { UINT32 subop = (opcode >> 40) & 0x1f; switch (subop) { - case 0x00: // NOP / idle |000|00000| + case 0x00: // NOP / idle |000|00000| if (opcode & U64(0x008000000000)) { // IDLE @@ -2306,7 +2306,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi } break; - case 0x01: // compute |000|00001| + case 0x01: // compute |000|00001| { int cond = (opcode >> 33) & 0x1f; @@ -2326,7 +2326,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x02: // immediate shift |000|00010| + case 0x02: // immediate shift |000|00010| { int shiftop = (opcode >> 16) & 0x3f; int rn = (opcode >> 4) & 0xf; @@ -2342,15 +2342,15 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi skip_label = compiler->labelnum++; generate_if_condition(block, compiler, desc, cond, skip_label); } - + generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx); - - if (has_condition) - UML_LABEL(block, skip_label); + + if (has_condition) + UML_LABEL(block, skip_label); return TRUE; } - case 0x04: // compute / modify |000|00100| + case 0x04: // compute / modify |000|00100| { int cond = (opcode >> 33) & 0x1f; int g = (opcode >> 38) & 0x1; @@ -2387,7 +2387,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x06: // direct jump|call |000|00110| + case 0x06: // direct jump|call |000|00110| { int b = (opcode >> 39) & 0x1; int j = (opcode >> 26) & 0x1; @@ -2405,7 +2405,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi } if (b) // call { - generate_call(block, compiler, desc, j != 0); + generate_call(block, compiler, desc, j != 0); } else // jump { @@ -2416,7 +2416,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x07: // direct jump|call |000|00111| + case 0x07: // direct jump|call |000|00111| { int b = (opcode >> 39) & 0x1; int j = (opcode >> 26) & 0x1; @@ -2445,7 +2445,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x08: // indirect jump|call / compute |000|01000| + case 0x08: // indirect jump|call / compute |000|01000| { int la = (opcode >> 38) & 0x1; int ci = (opcode >> 24) & 0x1; @@ -2508,7 +2508,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x09: // indirect jump|call / compute |000|01001| + case 0x09: // indirect jump|call / compute |000|01001| { int la = (opcode >> 38) & 0x1; int ci = (opcode >> 24) & 0x1; @@ -2532,7 +2532,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi { generate_jump(block, compiler, desc, j != 0, la != 0, ci != 0); } - + UML_LABEL(block, label_else); generate_compute(block, compiler, desc); } @@ -2565,12 +2565,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x0a: // return from subroutine / compute |000|01010| + case 0x0a: // return from subroutine / compute |000|01010| { int cond = (opcode >> 33) & 0x1f; int j = (opcode >> 26) & 0x1; int e = (opcode >> 25) & 0x1; - //int lr = (opcode >> 24) & 0x1; + //int lr = (opcode >> 24) & 0x1; // TODO: loop re-entry @@ -2583,7 +2583,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi UML_CALLH(block, *m_pop_pc); generate_jump(block, compiler, desc, j != 0, false, false); - + UML_LABEL(block, label_else); generate_compute(block, compiler, desc); } @@ -2610,7 +2610,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x0b: // return from interrupt / compute |000|01011| + case 0x0b: // return from interrupt / compute |000|01011| { int cond = (opcode >> 33) & 0x1f; int j = (opcode >> 26) & 0x1; @@ -2619,15 +2619,15 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi code_label skip_pop = compiler->labelnum++; - UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0 - UML_MOV(block, I0, 1); // mov i0,1 - UML_SHL(block, I0, I0, mem(&m_core->active_irq_num)); // shl i0,[active_irq_num] - UML_XOR(block, IRPTL, IRPTL, I0); // xor IRPTL,i0 - UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0 - UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop - UML_CALLH(block, *m_pop_status); // callh m_pop_status + UML_MOV(block, mem(&m_core->interrupt_active), 0); // mov [interrupt_active],0 + UML_MOV(block, I0, 1); // mov i0,1 + UML_SHL(block, I0, I0, mem(&m_core->active_irq_num)); // shl i0,[active_irq_num] + UML_XOR(block, IRPTL, IRPTL, I0); // xor IRPTL,i0 + UML_CMP(block, mem(&m_core->status_stkp), 0); // cmp [status_stkp],0 + UML_JMPc(block, COND_Z, skip_pop); // jz skip_pop + UML_CALLH(block, *m_pop_status); // callh m_pop_status - UML_LABEL(block, skip_pop); // skip_pop: + UML_LABEL(block, skip_pop); // skip_pop: // TODO: check interrupts @@ -2667,7 +2667,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x0c: // do until counter expired |000|01100| + case 0x0c: // do until counter expired |000|01100| { UINT16 data = (UINT16)(opcode >> 24); int offset = SIGN_EXTEND24(opcode & 0xffffff); @@ -2680,7 +2680,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi UML_MOV(block, I0, desc->pc + 1); UML_CALLH(block, *m_push_pc); - // push loop + // push loop UML_MOV(block, I0, data); UML_MOV(block, I1, address); UML_CALLH(block, *m_push_loop); @@ -2688,7 +2688,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x0d: // do until counter expired |000|01101| + case 0x0d: // do until counter expired |000|01101| { int ureg = (opcode >> 32) & 0xff; int offset = SIGN_EXTEND24(opcode & 0xffffff); @@ -2703,14 +2703,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi UML_MOV(block, I0, desc->pc + 1); UML_CALLH(block, *m_push_pc); - // push loop + // push loop UML_MOV(block, I0, I3); UML_MOV(block, I1, address); UML_CALLH(block, *m_push_loop); return TRUE; } - case 0x0e: // do until |000|01110| + case 0x0e: // do until |000|01110| { int offset = SIGN_EXTEND24(opcode & 0xffffff); UINT32 address = desc->pc + offset; @@ -2726,7 +2726,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x0f: // immediate data -> ureg |000|01111| + case 0x0f: // immediate data -> ureg |000|01111| { int ureg = (opcode >> 32) & 0xff; UINT32 data = (UINT32)opcode; @@ -2735,7 +2735,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D| + case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D| case 0x11: case 0x12: case 0x13: @@ -2754,7 +2754,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi if (g) { // PM - if (ureg == 0xdb) // PX is 48-bit + if (ureg == 0xdb) // PX is 48-bit UML_CALLH(block, *m_pm_write48); else UML_CALLH(block, *m_pm_write32); @@ -2771,7 +2771,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi if (g) { // PM - if (ureg == 0xdb) // PX is 48-bit + if (ureg == 0xdb) // PX is 48-bit UML_CALLH(block, *m_pm_read48); else UML_CALLH(block, *m_pm_read32); @@ -2787,7 +2787,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x14: // system register bit manipulation |000|10100| + case 0x14: // system register bit manipulation |000|10100| { int bop = (opcode >> 37) & 0x7; int sreg = (opcode >> 32) & 0xf; @@ -2795,7 +2795,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi switch (bop) { - case 0: // SET + case 0: // SET { switch (sreg) { @@ -2816,7 +2816,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi compiler->mode1_delay.data = data; compiler->mode1_delay.mode = MODE1_SET; break; - case 0xc: // ASTAT + case 0xc: // ASTAT // TODO: does this need delay? if (data & ASTAT_FLAGS::AZ) UML_MOV(block, ASTAT_AZ, 1); @@ -2876,7 +2876,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi } return TRUE; } - case 1: // CLEAR + case 1: // CLEAR { switch (sreg) { @@ -2957,7 +2957,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi } return TRUE; } - case 2: // TOGGLE + case 2: // TOGGLE { switch (sreg) { @@ -2995,7 +2995,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi } return TRUE; } - case 4: // TEST + case 4: // TEST { switch (sreg) { @@ -3047,7 +3047,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi } return TRUE; } - case 5: // XOR + case 5: // XOR { return FALSE; } @@ -3058,13 +3058,13 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x16: // I register modify / bit-reverse |000|10110| + case 0x16: // I register modify / bit-reverse |000|10110| { - if (opcode & U64(0x008000000000)) // bit reverse + if (opcode & U64(0x008000000000)) // bit reverse { return FALSE; } - else // modify + else // modify { int g = (opcode >> 38) & 0x1; int i = (opcode >> 32) & 0x7; @@ -3085,7 +3085,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi } } - case 0x17: // push|pop stacks / flush cache |000|10111| + case 0x17: // push|pop stacks / flush cache |000|10111| { if (opcode & U64(0x008000000000)) { @@ -3115,10 +3115,10 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 0x18: // cjump |000|11000| + case 0x18: // cjump |000|11000| return FALSE; - case 0x19: // rframe |000|11001| + case 0x19: // rframe |000|11001| return FALSE; default: @@ -3127,7 +3127,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi break; } - case 1: // compute / dreg <-> DM / dreg <-> PM |001| + case 1: // compute / dreg <-> DM / dreg <-> PM |001| { int pm_dreg = (opcode >> 23) & 0xf; int pmm = (opcode >> 27) & 0x7; @@ -3202,7 +3202,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 2: // compute / ureg <-> DM|PM, register modify |010| + case 2: // compute / ureg <-> DM|PM, register modify |010| { int u = (opcode >> 44) & 0x1; int i = (opcode >> 41) & 0x7; @@ -3245,18 +3245,18 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi generate_compute(block, compiler, desc); // transfer - UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] - if (u == 0) // pre-modify without update - UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m] + UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] + if (u == 0) // pre-modify without update + UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m] if (temp_ureg) - UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp] + UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp] else generate_read_ureg(block, compiler, desc, ureg, ureg_is_astat); - if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM - UML_CALLH(block, *m_pm_write48); // callh pm_write48 + if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM + UML_CALLH(block, *m_pm_write48); // callh pm_write48 else - UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32 + UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32 } else { @@ -3266,23 +3266,23 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi generate_compute(block, compiler, desc); // transfer - UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] - if (u == 0) // pre-modify without update - UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m] + UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] + if (u == 0) // pre-modify without update + UML_ADD(block, I1, I1, (g) ? PM_M(m) : DM_M(m)); // add i1,i1,dm|pm[m] - if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM - UML_CALLH(block, *m_pm_read48); // callh pm_read48 + if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM + UML_CALLH(block, *m_pm_read48); // callh pm_read48 else - UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32 + UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32 generate_write_ureg(block, compiler, desc, ureg, false, 0); } - if (u != 0) // post-modify with update + if (u != 0) // post-modify with update { if (g) - UML_ADD(block, PM_I(i), PM_I(i), PM_M(m)); // add pm[i],pm[m] + UML_ADD(block, PM_I(i), PM_I(i), PM_M(m)); // add pm[i],pm[m] else - UML_ADD(block, DM_I(i), DM_I(i), DM_M(m)); // add dm[i],dm[m] + UML_ADD(block, DM_I(i), DM_I(i), DM_M(m)); // add dm[i],dm[m] generate_update_circular_buffer(block, compiler, desc, g, i); } @@ -3295,7 +3295,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi case 3: { - if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1| + if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1| { int src_ureg = (opcode >> 36) & 0xff; int dst_ureg = (opcode >> 23) & 0xff; @@ -3343,7 +3343,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - else // compute / dreg <-> DM|PM, immediate modify |011|0| + else // compute / dreg <-> DM|PM, immediate modify |011|0| { int cond = (opcode >> 33) & 0x1f; int u = (opcode >> 38) & 0x1; @@ -3362,7 +3362,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi skip_label = compiler->labelnum++; generate_if_condition(block, compiler, desc, cond, skip_label); } - if (d) + if (d) { // DREG -> DM|PM bool temp_dreg = false; @@ -3377,14 +3377,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi generate_compute(block, compiler, desc); // transfer - UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] - if (u == 0) // pre-modify without update - UML_ADD(block, I1, I1, mod); // add i1,i1,mod + UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] + if (u == 0) // pre-modify without update + UML_ADD(block, I1, I1, mod); // add i1,i1,mod if (temp_dreg) - UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp] + UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp] else - UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg] - UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32 + UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg] + UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32 } else { @@ -3394,19 +3394,19 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi generate_compute(block, compiler, desc); // transfer - UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] - if (u == 0) // pre-modify without update - UML_ADD(block, I1, I1, mod); // add i1,i1,mod - UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32 - UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0 + UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] + if (u == 0) // pre-modify without update + UML_ADD(block, I1, I1, mod); // add i1,i1,mod + UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32 + UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0 } - if (u != 0) // post-modify with update + if (u != 0) // post-modify with update { if (g) - UML_ADD(block, PM_I(i), PM_I(i), mod); // add pm[i],mod + UML_ADD(block, PM_I(i), PM_I(i), mod); // add pm[i],mod else - UML_ADD(block, DM_I(i), DM_I(i), mod); // add dm[i],mod + UML_ADD(block, DM_I(i), DM_I(i), mod); // add dm[i],mod generate_update_circular_buffer(block, compiler, desc, g, i); } @@ -3420,7 +3420,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi case 4: { - if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1| + if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1| { int i = (opcode >> 41) & 0x7; int m = (opcode >> 38) & 0x7; @@ -3441,14 +3441,14 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi UML_MOV(block, I0, data); UML_MOV(block, I1, DM_I(i)); UML_CALLH(block, *m_dm_write32); - UML_ADD(block, DM_I(i), DM_I(i), DM_M(m)); + UML_ADD(block, DM_I(i), DM_I(i), DM_M(m)); } generate_update_circular_buffer(block, compiler, desc, g, i); return TRUE; } - else // immediate shift / dreg <-> DM|PM |100|0| + else // immediate shift / dreg <-> DM|PM |100|0| { int i = (opcode >> 41) & 0x7; int m = (opcode >> 38) & 0x7; @@ -3484,12 +3484,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx); // transfer - UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] + UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] if (temp_dreg) - UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp] + UML_MOV(block, I0, mem(&m_core->dreg_temp)); // mov i0,[m_core->dreg_temp] else - UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg] - UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32 + UML_MOV(block, I0, REG(dreg)); // mov i0,reg[dreg] + UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32 } else { @@ -3499,9 +3499,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi generate_shift_imm(block, compiler, desc, data, shiftop, rn, rx); // transfer - UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] - UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32 - UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0 + UML_MOV(block, I1, (g) ? PM_I(i) : DM_I(i)); // mov i1,dm|pm[i] + UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32 + UML_MOV(block, REG(dreg), I0); // mov reg[dreg],i0 } // update I @@ -3520,42 +3520,42 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi break; } - case 5: // ureg <-> DM|PM (indirect) |101| + case 5: // ureg <-> DM|PM (indirect) |101| { int g = (opcode >> 44) & 1; int d = (opcode >> 40) & 1; int i = (opcode >> 41) & 0x7; int ureg = (opcode >> 32) & 0xff; UINT32 offset = (UINT32)opcode; - + if (d) { // UREG -> DM|PM - UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset + UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset generate_read_ureg(block, compiler, desc, ureg, false); - if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM - UML_CALLH(block, *m_pm_write48); // callh pm_write48 + if (ureg == 0xdb && (g)) // PX is 48-bit when writing to PM + UML_CALLH(block, *m_pm_write48); // callh pm_write48 else - UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32 + UML_CALLH(block, (g) ? *m_pm_write32 : *m_dm_write32); // callh dm|pm_write32 } else { // DM|PM -> UREG - UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset + UML_ADD(block, I1, (g) ? PM_I(i) : DM_I(i), offset); // add i1,dm|pm[i],offset - if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM - UML_CALLH(block, *m_pm_read48); // callh pm_read48 + if (ureg == 0xdb && (g)) // PX is 48-bit when reading from PM + UML_CALLH(block, *m_pm_read48); // callh pm_read48 else - UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32 + UML_CALLH(block, (g) ? *m_pm_read32 : *m_dm_read32); // callh dm|pm_read32 generate_write_ureg(block, compiler, desc, ureg, false, 0); } return TRUE; } - case 6: // indirect jump / compute / dreg <-> DM |110| + case 6: // indirect jump / compute / dreg <-> DM |110| { int d = (opcode >> 44) & 0x1; int dmi = (opcode >> 41) & 0x7; @@ -3616,7 +3616,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi return TRUE; } - case 7: // indirect jump / compute / dreg <-> DM |111| + case 7: // indirect jump / compute / dreg <-> DM |111| { int d = (opcode >> 44) & 0x1; int dmi = (opcode >> 41) & 0x7; @@ -3698,7 +3698,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com int ry = (opcode >> 0) & 0xf; int ps = (opcode >> 16) & 0xf; - if (opcode & 0x400000) // multi-function operation + if (opcode & 0x400000) // multi-function operation { UINT32 multiop = (opcode >> 16) & 0x3f; int fm = rs; @@ -3710,65 +3710,65 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com switch (multiop) { - case 0x00: // Rn = MRxx - { + case 0x00: // Rn = MRxx + { generate_unimplemented_compute(block, compiler, desc); return; } - case 0x01: // MRxx = Rn + case 0x01: // MRxx = Rn { int ai = rs; switch (ai) { - case 0x00: // MR0F + case 0x00: // MR0F UML_DAND(block, MRF, MRF, U64(0xffffffff00000000)); UML_AND(block, I0, REG(rn), 0xffffffff); UML_DOR(block, MRF, MRF, I0); break; - case 0x01: // MR1F + case 0x01: // MR1F UML_DAND(block, MRF, MRF, U64(0x00000000ffffffff)); UML_DSHL(block, I0, REG(rn), 32); UML_DOR(block, MRF, MRF, I0); - break; - case 0x04: // MR0B + break; + case 0x04: // MR0B UML_DAND(block, MRB, MRB, U64(0xffffffff00000000)); UML_AND(block, I0, REG(rn), 0xffffffff); UML_DOR(block, MRB, MRB, I0); break; - case 0x05: // MR1B + case 0x05: // MR1B UML_DAND(block, MRB, MRB, U64(0x00000000ffffffff)); UML_DSHL(block, I0, REG(rn), 32); UML_DOR(block, MRB, MRB, I0); break; - case 0x02: // MR2F - case 0x06: // MR2B + case 0x02: // MR2F + case 0x06: // MR2B generate_unimplemented_compute(block, compiler, desc); return; } return; } - case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry - case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy - case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 - case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12 - case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12 - case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2 - case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 - case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 - case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 - case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12 - case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12 - case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2 - case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 - case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 - case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 + case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry + case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy + case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 + case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12 + case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12 + case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2 + case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 + case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 + case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 + case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12 + case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12 + case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2 + case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 + case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 + case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 generate_unimplemented_compute(block, compiler, desc); return; - case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2 + case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2 generate_unimplemented_compute(block, compiler, desc); return; @@ -3802,10 +3802,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AZ_CALC_REQUIRED) UML_OR(block, ASTAT_AZ, ASTAT_AZ, I0); if (AN_CALC_REQUIRED) UML_OR(block, ASTAT_AN, ASTAT_AN, I1); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO if (MN_CALC_REQUIRED) UML_FSCMP(block, F0, mem(&m_core->fp0)); @@ -3817,7 +3817,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_ICOPYFS(block, REG(ps), F5); return; - case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 + case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 UML_DSEXT(block, I0, REG(fxm), SIZE_DWORD); UML_DSEXT(block, I1, REG(fym), SIZE_DWORD); UML_DMULS(block, I0, I0, I0, I1); @@ -3837,7 +3837,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_MOV(block, REG(fa), I2); return; - case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 + case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 UML_DSEXT(block, I0, REG(fxm), SIZE_DWORD); UML_DSEXT(block, I1, REG(fym), SIZE_DWORD); UML_DMULS(block, I0, I0, I0, I1); @@ -3857,7 +3857,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_MOV(block, REG(fa), I2); return; - case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12 + case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12 // TODO: denormals UML_FSCOPYI(block, F0, REG(fxm)); UML_FSCOPYI(block, F1, REG(fym)); @@ -3870,11 +3870,11 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_FSCMP(block, F2, mem(&m_core->fp0)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO - + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (MN_CALC_REQUIRED) UML_FSCMP(block, F0, mem(&m_core->fp0)); if (MN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_MN); @@ -3884,7 +3884,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_ICOPYFS(block, REG(fa), F2); return; - case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12 + case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12 // TODO: denormals UML_FSCOPYI(block, F0, REG(fxm)); UML_FSCOPYI(block, F1, REG(fym)); @@ -3897,10 +3897,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_FSCMP(block, F2, mem(&m_core->fp0)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO if (MN_CALC_REQUIRED) UML_FSCMP(block, F0, mem(&m_core->fp0)); @@ -3911,7 +3911,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_ICOPYFS(block, REG(fa), F2); return; - case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12 + case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12 { code_label denormal = compiler->labelnum++; code_label end = compiler->labelnum++; @@ -3937,7 +3937,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_OR(block, I0, I0, I1); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); @@ -3947,7 +3947,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_AND(block, I0, I1, 0x80000000); if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1); if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); @@ -3964,7 +3964,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12 + case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12 { code_label denormal = compiler->labelnum++; code_label end = compiler->labelnum++; @@ -3989,7 +3989,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_OR(block, I0, I0, I1); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); @@ -3999,7 +3999,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_AND(block, I0, I1, 0x80000000); if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1); if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); @@ -4025,18 +4025,18 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8 + case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8 UML_FSCOPYI(block, F0, REG(fxm)); UML_FSCOPYI(block, F1, REG(fym)); UML_AND(block, I0, REG(fxa), 0x7fffffff); UML_FSMUL(block, F0, F0, F1); - if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO + if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0); if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); - if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO if (MN_CALC_REQUIRED) UML_FSCMP(block, F0, mem(&m_core->fp0)); @@ -4047,7 +4047,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_MOV(block, REG(fa), I0); return; - case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12) + case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12) // TODO: denormals UML_FSCOPYI(block, F0, REG(fxm)); UML_FSCOPYI(block, F1, REG(fym)); @@ -4063,10 +4063,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_FSCMP(block, F4, mem(&m_core->fp0)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO if (MN_CALC_REQUIRED) UML_FSCMP(block, F0, mem(&m_core->fp0)); @@ -4077,7 +4077,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_ICOPYFS(block, REG(fa), F4); return; - case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12) + case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12) // TODO: denormals UML_FSCOPYI(block, F0, REG(fxm)); UML_FSCOPYI(block, F1, REG(fym)); @@ -4093,10 +4093,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_FSCMP(block, F4, mem(&m_core->fp0)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO if (MN_CALC_REQUIRED) UML_FSCMP(block, F0, mem(&m_core->fp0)); @@ -4112,35 +4112,35 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } } - else // single-function operation + else // single-function operation { UINT32 operation = (opcode >> 12) & 0xff; switch ((opcode >> 20) & 3) { - case 0: // ALU operations + case 0: // ALU operations { switch (operation) { - case 0x09: // Rn = (Rx + Ry) / 2 - case 0x63: // Rn = CLIP Rx BY Ry - case 0x92: // Fn = ABS(Fx - Fy) - case 0x89: // Fn = (Fx + Fy) / 2 - case 0xdd: // Rn = TRUNC Fx BY Ry - case 0xe0: // Fn = Fx COPYSIGN Fy - case 0x05: // Rn = Rx + Ry + CI - case 0x06: // Rn = Rx - Ry + CI - 1 - case 0x25: // Rn = Rx + CI - case 0x26: // Rn = Rx + CI - 1 - case 0x30: // Rn = ABS Rx - case 0x43: // Rn = NOT Rx - case 0xa5: // Fn = RND Fx - case 0xad: // Rn = MANT Fx - case 0xcd: // Rn = TRUNC Fx + case 0x09: // Rn = (Rx + Ry) / 2 + case 0x63: // Rn = CLIP Rx BY Ry + case 0x92: // Fn = ABS(Fx - Fy) + case 0x89: // Fn = (Fx + Fy) / 2 + case 0xdd: // Rn = TRUNC Fx BY Ry + case 0xe0: // Fn = Fx COPYSIGN Fy + case 0x05: // Rn = Rx + Ry + CI + case 0x06: // Rn = Rx - Ry + CI - 1 + case 0x25: // Rn = Rx + CI + case 0x26: // Rn = Rx + CI - 1 + case 0x30: // Rn = ABS Rx + case 0x43: // Rn = NOT Rx + case 0xa5: // Fn = RND Fx + case 0xad: // Rn = MANT Fx + case 0xcd: // Rn = TRUNC Fx generate_unimplemented_compute(block, compiler, desc); return; - case 0x01: // Rn = Rx + Ry + case 0x01: // Rn = Rx + Ry UML_ADD(block, REG(rn), REG(rx), REG(ry)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); @@ -4150,7 +4150,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x02: // Rn = Rx - Ry + case 0x02: // Rn = Rx - Ry UML_SUB(block, REG(rn), REG(rx), REG(ry)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); @@ -4160,7 +4160,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x0a: // COMP(Rx, Ry) + case 0x0a: // COMP(Rx, Ry) UML_CMP(block, REG(rx), REG(ry)); UML_SETc(block, COND_Z, I0); UML_SETc(block, COND_L, I1); @@ -4182,7 +4182,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x21: // Rn = PASS Rx + case 0x21: // Rn = PASS Rx UML_MOV(block, REG(rn), REG(rx)); if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED) UML_CMP(block, REG(rn), 0); @@ -4194,7 +4194,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x22: // Rn = -Rx + case 0x22: // Rn = -Rx UML_SUB(block, REG(rn), 0, REG(rx)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); @@ -4204,7 +4204,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x29: // Rn = Rx + 1 + case 0x29: // Rn = Rx + 1 UML_ADD(block, REG(rn), REG(rx), 1); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); @@ -4214,7 +4214,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x2a: // Rn = Rx - 1 + case 0x2a: // Rn = Rx - 1 UML_SUB(block, REG(rn), REG(rx), 1); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); @@ -4224,7 +4224,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x40: // Rn = Rx AND Ry + case 0x40: // Rn = Rx AND Ry UML_AND(block, REG(rn), REG(rx), REG(ry)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); @@ -4234,7 +4234,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x41: // Rn = Rx OR Ry + case 0x41: // Rn = Rx OR Ry UML_OR(block, REG(rn), REG(rx), REG(ry)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); @@ -4244,7 +4244,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x42: // Rn = Rx XOR Ry + case 0x42: // Rn = Rx XOR Ry UML_XOR(block, REG(rn), REG(rx), REG(ry)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); @@ -4254,7 +4254,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x61: // Rn = MIN(Rx, Ry) + case 0x61: // Rn = MIN(Rx, Ry) UML_MOV(block, REG(rn), REG(rx)); UML_CMP(block, REG(rx), REG(ry)); UML_MOVc(block, COND_G, REG(rn), REG(ry)); @@ -4268,7 +4268,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0x62: // Rn = MAX(Rx, Ry) + case 0x62: // Rn = MAX(Rx, Ry) UML_MOV(block, REG(rn), REG(rx)); UML_CMP(block, REG(rx), REG(ry)); UML_MOVc(block, COND_L, REG(rn), REG(ry)); @@ -4286,7 +4286,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: { /* Fixed-point Dual Add/Subtract */ - UML_ADD(block, I0, REG(rx), REG(ry)); + UML_ADD(block, I0, REG(rx), REG(ry)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); if (AV_CALC_REQUIRED) UML_SETc(block, COND_V, ASTAT_AV); @@ -4307,7 +4307,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0x81: // Fn = Fx + Fy + case 0x81: // Fn = Fx + Fy // TODO: denormals UML_FSCOPYI(block, F0, REG(rx)); UML_FSCOPYI(block, F1, REG(ry)); @@ -4316,14 +4316,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_FSCMP(block, F0, mem(&m_core->fp0)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_ICOPYFS(block, REG(rn), F0); return; - case 0x82: // Fn = Fx - Fy + case 0x82: // Fn = Fx - Fy // TODO: denormals UML_FSCOPYI(block, F0, REG(rx)); UML_FSCOPYI(block, F1, REG(ry)); @@ -4332,14 +4332,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_FSCMP(block, F0, mem(&m_core->fp0)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_ICOPYFS(block, REG(rn), F0); return; - case 0x8a: // COMP(Fx, Fy) + case 0x8a: // COMP(Fx, Fy) UML_FSCOPYI(block, F0, REG(rx)); UML_FSCOPYI(block, F1, REG(ry)); UML_FSCMP(block, F0, F1); @@ -4356,29 +4356,29 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_SHR(block, I2, I2, 1); UML_OR(block, I2, I2, I0); UML_MOV(block, mem(&m_core->astat_drc.cacc), I2); - + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO return; - case 0x91: // Fn = ABS(Fx + Fy) + case 0x91: // Fn = ABS(Fx + Fy) // TODO: denormals UML_FSCOPYI(block, F0, REG(rx)); UML_FSCOPYI(block, F1, REG(ry)); UML_FSADD(block, F0, F0, F1); UML_FSABS(block, F0, F0); UML_ICOPYFS(block, REG(rn), F0); - if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO + if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO return; - case 0xa1: // Fn = PASS Fx + case 0xa1: // Fn = PASS Fx UML_MOV(block, REG(rn), REG(rx)); if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED) { @@ -4390,10 +4390,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO return; - case 0xa2: // Fn = -Fx + case 0xa2: // Fn = -Fx UML_FSCOPYI(block, F0, REG(rx)); UML_FSNEG(block, F0, F0); UML_ICOPYFS(block, REG(rn), F0); @@ -4404,23 +4404,23 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO return; - case 0xb0: // Fn = ABS(Fx) + case 0xb0: // Fn = ABS(Fx) UML_FSCOPYI(block, F0, REG(rx)); UML_FSABS(block, F0, F0); UML_ICOPYFS(block, REG(rn), F0); - if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO + if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 0); // TODO if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0); if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); - if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO return; - case 0xbd: // Fn = SCALB Fx BY Ry + case 0xbd: // Fn = SCALB Fx BY Ry // TODO: source = nan, result = denormal UML_MOV(block, I1, REG(rx)); UML_AND(block, I0, I1, 0x7f800000); @@ -4434,26 +4434,26 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_OR(block, REG(rn), I0, I1); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO return; - case 0xc1: // Rn = LOGB Fx + case 0xc1: // Rn = LOGB Fx // TODO: source = zero, infinity, nan UML_SHR(block, I0, REG(rx), 23); UML_AND(block, I0, I0, 0xff); UML_SUB(block, REG(rn), I0, 127); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0xc4: // Fn = RECIPS Fx + case 0xc4: // Fn = RECIPS Fx // TODO: denormals // TODO: use the bit accurate method from interpreter? UML_FSCOPYI(block, F0, REG(rx)); @@ -4470,11 +4470,11 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_ICOPYFS(block, REG(rn), F0); return; - case 0xc5: // Fn = RSQRTS Fx + case 0xc5: // Fn = RSQRTS Fx // TODO: denormals // TODO: use the bit accurate method from interpreter? UML_FSCOPYI(block, F0, REG(rx)); @@ -4488,7 +4488,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); return; - case 0xca: // Fn = FLOAT Rx + case 0xca: // Fn = FLOAT Rx UML_FSFRINT(block, F0, REG(rx), SIZE_DWORD); UML_ICOPYFS(block, REG(rn), F0); if (AZ_CALC_REQUIRED) @@ -4500,7 +4500,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); return; - case 0xc9: // Rn = FIX Fx + case 0xc9: // Rn = FIX Fx UML_FSCOPYI(block, F0, REG(rx)); UML_TEST(block, MODE1, MODE1_TRUNCATE); UML_JMPc(block, COND_Z, compiler->labelnum); @@ -4514,14 +4514,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_CMP(block, I0, 0); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_MOV(block, REG(rn), I0); - return; + return; - case 0xd9: // Rn = FIX Fx BY Ry + case 0xd9: // Rn = FIX Fx BY Ry { code_label denormal = compiler->labelnum++; code_label end = compiler->labelnum++; @@ -4553,10 +4553,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_CMP(block, I0, 0); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_MOV(block, REG(rn), I0); UML_JMP(block, end); @@ -4564,7 +4564,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_AND(block, I0, I1, 0x80000000); if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1); if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); @@ -4574,7 +4574,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0xda: // Fn = FLOAT Rx BY Ry + case 0xda: // Fn = FLOAT Rx BY Ry { code_label denormal = compiler->labelnum++; code_label end = compiler->labelnum++; @@ -4594,27 +4594,27 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_OR(block, REG(rn), I0, I1); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); UML_JMP(block, end); - + UML_LABEL(block, denormal); UML_AND(block, I0, I1, 0x80000000); if (AZ_CALC_REQUIRED) UML_MOV(block, ASTAT_AZ, 1); if (AN_CALC_REQUIRED) UML_MOV(block, ASTAT_AN, 0); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); UML_MOV(block, REG(rn), I0); - + UML_LABEL(block, end); return; } - case 0xe1: // Fn = MIN(Fx, Fy) + case 0xe1: // Fn = MIN(Fx, Fy) UML_FSCOPYI(block, F2, REG(rx)); UML_FSCOPYI(block, F3, REG(ry)); UML_FSMOV(block, F4, F2); @@ -4625,14 +4625,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_FSCMP(block, F4, mem(&m_core->fp0)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_ICOPYFS(block, REG(rn), F4); return; - case 0xe2: // Fn = MAX(Fx, Fy) + case 0xe2: // Fn = MAX(Fx, Fy) UML_FSCOPYI(block, F2, REG(rx)); UML_FSCOPYI(block, F3, REG(ry)); UML_FSMOV(block, F4, F2); @@ -4643,14 +4643,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com UML_FSCMP(block, F4, mem(&m_core->fp0)); if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ); if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AN); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_ICOPYFS(block, REG(rn), F4); return; - case 0xe3: // Fn = CLIP Fx BY Fy + case 0xe3: // Fn = CLIP Fx BY Fy { code_label label_1 = compiler->labelnum++; code_label label_2 = compiler->labelnum++; @@ -4675,7 +4675,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_ICOPYFS(block, REG(rn), F0); return; } @@ -4698,10 +4698,10 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (AN_CALC_REQUIRED) UML_SETc(block, COND_C, I1); if (AZ_CALC_REQUIRED) UML_OR(block, ASTAT_AZ, ASTAT_AZ, I0); if (AN_CALC_REQUIRED) UML_OR(block, ASTAT_AN, ASTAT_AN, I1); - if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO + if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0); // TODO if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0); if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0); - if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO + if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0); // TODO UML_ICOPYFS(block, REG(ra), F2); UML_ICOPYFS(block, REG(rs), F3); return; @@ -4714,166 +4714,166 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com break; } - case 1: // multiplier operations + case 1: // multiplier operations { switch (operation) { - case 0x48: // Rn = Rx * Ry (UUF) - case 0x49: // Rn = Rx * Ry (UUFR) - case 0x50: // Rn = Rx * Ry (SUI) - case 0x58: // Rn = Rx * Ry (SUF) - case 0x59: // Rn = Rx * Ry (SUFR) - case 0x60: // Rn = Rx * Ry (USI) - case 0x68: // Rn = Rx * Ry (USF) - case 0x69: // Rn = Rx * Ry (USFR) - case 0x78: // Rn = Rx * Ry (SSF) - case 0x79: // Rn = Rx * Ry (SSFR) - case 0x44: // MRF = Rx * Ry (UUI) - case 0x4c: // MRF = Rx * Ry (UUF) - case 0x4d: // MRF = Rx * Ry (UUFR) - case 0x54: // MRF = Rx * Ry (SUI) - case 0x5c: // MRF = Rx * Ry (SUF) - case 0x5d: // MRF = Rx * Ry (SUFR) - case 0x64: // MRF = Rx * Ry (USI) - case 0x6c: // MRF = Rx * Ry (USF) - case 0x6d: // MRF = Rx * Ry (USFR) - case 0x74: // MRF = Rx * Ry (SSI) - case 0x7c: // MRF = Rx * Ry (SSF) - case 0x7d: // MRF = Rx * Ry (SSFR) - case 0x46: // MRB = Rx * Ry (UUI) - case 0x4e: // MRB = Rx * Ry (UUF) - case 0x4f: // MRB = Rx * Ry (UUFR) - case 0x56: // MRB = Rx * Ry (SUI) - case 0x5e: // MRB = Rx * Ry (SUF) - case 0x5f: // MRB = Rx * Ry (SUFR) - case 0x66: // MRB = Rx * Ry (USI) - case 0x6e: // MRB = Rx * Ry (USF) - case 0x6f: // MRB = Rx * Ry (USFR) - case 0x76: // MRB = Rx * Ry (SSI) - case 0x7e: // MRB = Rx * Ry (SSF) - case 0x7f: // MRB = Rx * Ry (SSFR) - case 0x80: // Rn = MRF + Rx * Ry (UUI) - case 0x88: // Rn = MRF + Rx * Ry (UUF) - case 0x89: // Rn = MRF + Rx * Ry (UUFR) - case 0x90: // Rn = MRF + Rx * Ry (SUI) - case 0x98: // Rn = MRF + Rx * Ry (SUF) - case 0x99: // Rn = MRF + Rx * Ry (SUFR) - case 0xa0: // Rn = MRF + Rx * Ry (USI) - case 0xa8: // Rn = MRF + Rx * Ry (USF) - case 0xa9: // Rn = MRF + Rx * Ry (USFR) - case 0xb8: // Rn = MRF + Rx * Ry (SSF) - case 0xb9: // Rn = MRF + Rx * Ry (SSFR) - case 0x82: // Rn = MRB + Rx * Ry (UUI) - case 0x8a: // Rn = MRB + Rx * Ry (UUF) - case 0x8b: // Rn = MRB + Rx * Ry (UUFR) - case 0x92: // Rn = MRB + Rx * Ry (SUI) - case 0x9a: // Rn = MRB + Rx * Ry (SUF) - case 0x9b: // Rn = MRB + Rx * Ry (SUFR) - case 0xa2: // Rn = MRB + Rx * Ry (USI) - case 0xaa: // Rn = MRB + Rx * Ry (USF) - case 0xab: // Rn = MRB + Rx * Ry (USFR) - case 0xba: // Rn = MRB + Rx * Ry (SSF) - case 0xbb: // Rn = MRB + Rx * Ry (SSFR) - case 0x84: // MRF = MRF + Rx * Ry (UUI) - case 0x8c: // MRF = MRF + Rx * Ry (UUF) - case 0x8d: // MRF = MRF + Rx * Ry (UUFR) - case 0x94: // MRF = MRF + Rx * Ry (SUI) - case 0x9c: // MRF = MRF + Rx * Ry (SUF) - case 0x9d: // MRF = MRF + Rx * Ry (SUFR) - case 0xa4: // MRF = MRF + Rx * Ry (USI) - case 0xac: // MRF = MRF + Rx * Ry (USF) - case 0xad: // MRF = MRF + Rx * Ry (USFR) - case 0xb4: // MRF = MRF + Rx * Ry (SSI) - case 0xbc: // MRF = MRF + Rx * Ry (SSF) - case 0xbd: // MRF = MRF + Rx * Ry (SSFR) - case 0x86: // MRB = MRB + Rx * Ry (UUI) - case 0x8e: // MRB = MRB + Rx * Ry (UUF) - case 0x8f: // MRB = MRB + Rx * Ry (UUFR) - case 0x96: // MRB = MRB + Rx * Ry (SUI) - case 0x9e: // MRB = MRB + Rx * Ry (SUF) - case 0x9f: // MRB = MRB + Rx * Ry (SUFR) - case 0xa6: // MRB = MRB + Rx * Ry (USI) - case 0xae: // MRB = MRB + Rx * Ry (USF) - case 0xaf: // MRB = MRB + Rx * Ry (USFR) - case 0xb6: // MRB = MRB + Rx * Ry (SSI) - case 0xbe: // MRB = MRB + Rx * Ry (SSF) - case 0xbf: // MRB = MRB + Rx * Ry (SSFR) - case 0xc0: // Rn = MRF - Rx * Ry (UUI) - case 0xc8: // Rn = MRF - Rx * Ry (UUF) - case 0xc9: // Rn = MRF - Rx * Ry (UUFR) - case 0xd0: // Rn = MRF - Rx * Ry (SUI) - case 0xd8: // Rn = MRF - Rx * Ry (SUF) - case 0xd9: // Rn = MRF - Rx * Ry (SUFR) - case 0xe0: // Rn = MRF - Rx * Ry (USI) - case 0xe8: // Rn = MRF - Rx * Ry (USF) - case 0xe9: // Rn = MRF - Rx * Ry (USFR) - case 0xf0: // Rn = MRF - Rx * Ry (SSI) - case 0xf8: // Rn = MRF - Rx * Ry (SSF) - case 0xf9: // Rn = MRF - Rx * Ry (SSFR) - case 0xc2: // Rn = MRB - Rx * Ry (UUI) - case 0xca: // Rn = MRB - Rx * Ry (UUF) - case 0xcb: // Rn = MRB - Rx * Ry (UUFR) - case 0xd2: // Rn = MRB - Rx * Ry (SUI) - case 0xda: // Rn = MRB - Rx * Ry (SUF) - case 0xdb: // Rn = MRB - Rx * Ry (SUFR) - case 0xe2: // Rn = MRB - Rx * Ry (USI) - case 0xea: // Rn = MRB - Rx * Ry (USF) - case 0xeb: // Rn = MRB - Rx * Ry (USFR) - case 0xf2: // Rn = MRB - Rx * Ry (SSI) - case 0xfa: // Rn = MRB - Rx * Ry (SSF) - case 0xfb: // Rn = MRB - Rx * Ry (SSFR) - case 0xc4: // MRF = MRF - Rx * Ry (UUI) - case 0xcc: // MRF = MRF - Rx * Ry (UUF) - case 0xcd: // MRF = MRF - Rx * Ry (UUFR) - case 0xd4: // MRF = MRF - Rx * Ry (SUI) - case 0xdc: // MRF = MRF - Rx * Ry (SUF) - case 0xdd: // MRF = MRF - Rx * Ry (SUFR) - case 0xe4: // MRF = MRF - Rx * Ry (USI) - case 0xec: // MRF = MRF - Rx * Ry (USF) - case 0xed: // MRF = MRF - Rx * Ry (USFR) - case 0xf4: // MRF = MRF - Rx * Ry (SSI) - case 0xfc: // MRF = MRF - Rx * Ry (SSF) - case 0xfd: // MRF = MRF - Rx * Ry (SSFR) - case 0xc6: // MRB = MRB - Rx * Ry (UUI) - case 0xce: // MRB = MRB - Rx * Ry (UUF) - case 0xcf: // MRB = MRB - Rx * Ry (UUFR) - case 0xd6: // MRB = MRB - Rx * Ry (SUI) - case 0xde: // MRB = MRB - Rx * Ry (SUF) - case 0xdf: // MRB = MRB - Rx * Ry (SUFR) - case 0xe6: // MRB = MRB - Rx * Ry (USI) - case 0xee: // MRB = MRB - Rx * Ry (USF) - case 0xef: // MRB = MRB - Rx * Ry (USFR) - case 0xf6: // MRB = MRB - Rx * Ry (SSI) - case 0xfe: // MRB = MRB - Rx * Ry (SSF) - case 0xff: // MRB = MRB - Rx * Ry (SSFR) - case 0x00: // Rn = SAT MRF (UI) - case 0x01: // Rn = SAT MRF (SI) - case 0x08: // Rn = SAT MRF (UF) - case 0x09: // Rn = SAT MRF (SF) - case 0x02: // Rn = SAT MRB (UI) - case 0x03: // Rn = SAT MRB (SI) - case 0x0a: // Rn = SAT MRB (UF) - case 0x0b: // Rn = SAT MRB (SF) - case 0x04: // MRF = SAT MRF (UI) - case 0x05: // MRF = SAT MRF (SI) - case 0x0c: // MRF = SAT MRF (UF) - case 0x0d: // MRF = SAT MRF (SF) - case 0x06: // MRB = SAT MRB (UI) - case 0x07: // MRB = SAT MRB (SI) - case 0x0e: // MRB = SAT MRB (UF) - case 0x0f: // MRB = SAT MRB (SF) - case 0x18: // Rn = RND MRF (U) - case 0x19: // Rn = RND MRF (S) - case 0x1a: // Rn = RND MRB (U) - case 0x1b: // Rn = RND MRB (S) - case 0x1c: // MRF = RND MRF (U) - case 0x1d: // MRF = RND MRF (S) - case 0x1e: // MRB = RND MRB (U) - case 0x1f: // MRB = RND MRB (S) + case 0x48: // Rn = Rx * Ry (UUF) + case 0x49: // Rn = Rx * Ry (UUFR) + case 0x50: // Rn = Rx * Ry (SUI) + case 0x58: // Rn = Rx * Ry (SUF) + case 0x59: // Rn = Rx * Ry (SUFR) + case 0x60: // Rn = Rx * Ry (USI) + case 0x68: // Rn = Rx * Ry (USF) + case 0x69: // Rn = Rx * Ry (USFR) + case 0x78: // Rn = Rx * Ry (SSF) + case 0x79: // Rn = Rx * Ry (SSFR) + case 0x44: // MRF = Rx * Ry (UUI) + case 0x4c: // MRF = Rx * Ry (UUF) + case 0x4d: // MRF = Rx * Ry (UUFR) + case 0x54: // MRF = Rx * Ry (SUI) + case 0x5c: // MRF = Rx * Ry (SUF) + case 0x5d: // MRF = Rx * Ry (SUFR) + case 0x64: // MRF = Rx * Ry (USI) + case 0x6c: // MRF = Rx * Ry (USF) + case 0x6d: // MRF = Rx * Ry (USFR) + case 0x74: // MRF = Rx * Ry (SSI) + case 0x7c: // MRF = Rx * Ry (SSF) + case 0x7d: // MRF = Rx * Ry (SSFR) + case 0x46: // MRB = Rx * Ry (UUI) + case 0x4e: // MRB = Rx * Ry (UUF) + case 0x4f: // MRB = Rx * Ry (UUFR) + case 0x56: // MRB = Rx * Ry (SUI) + case 0x5e: // MRB = Rx * Ry (SUF) + case 0x5f: // MRB = Rx * Ry (SUFR) + case 0x66: // MRB = Rx * Ry (USI) + case 0x6e: // MRB = Rx * Ry (USF) + case 0x6f: // MRB = Rx * Ry (USFR) + case 0x76: // MRB = Rx * Ry (SSI) + case 0x7e: // MRB = Rx * Ry (SSF) + case 0x7f: // MRB = Rx * Ry (SSFR) + case 0x80: // Rn = MRF + Rx * Ry (UUI) + case 0x88: // Rn = MRF + Rx * Ry (UUF) + case 0x89: // Rn = MRF + Rx * Ry (UUFR) + case 0x90: // Rn = MRF + Rx * Ry (SUI) + case 0x98: // Rn = MRF + Rx * Ry (SUF) + case 0x99: // Rn = MRF + Rx * Ry (SUFR) + case 0xa0: // Rn = MRF + Rx * Ry (USI) + case 0xa8: // Rn = MRF + Rx * Ry (USF) + case 0xa9: // Rn = MRF + Rx * Ry (USFR) + case 0xb8: // Rn = MRF + Rx * Ry (SSF) + case 0xb9: // Rn = MRF + Rx * Ry (SSFR) + case 0x82: // Rn = MRB + Rx * Ry (UUI) + case 0x8a: // Rn = MRB + Rx * Ry (UUF) + case 0x8b: // Rn = MRB + Rx * Ry (UUFR) + case 0x92: // Rn = MRB + Rx * Ry (SUI) + case 0x9a: // Rn = MRB + Rx * Ry (SUF) + case 0x9b: // Rn = MRB + Rx * Ry (SUFR) + case 0xa2: // Rn = MRB + Rx * Ry (USI) + case 0xaa: // Rn = MRB + Rx * Ry (USF) + case 0xab: // Rn = MRB + Rx * Ry (USFR) + case 0xba: // Rn = MRB + Rx * Ry (SSF) + case 0xbb: // Rn = MRB + Rx * Ry (SSFR) + case 0x84: // MRF = MRF + Rx * Ry (UUI) + case 0x8c: // MRF = MRF + Rx * Ry (UUF) + case 0x8d: // MRF = MRF + Rx * Ry (UUFR) + case 0x94: // MRF = MRF + Rx * Ry (SUI) + case 0x9c: // MRF = MRF + Rx * Ry (SUF) + case 0x9d: // MRF = MRF + Rx * Ry (SUFR) + case 0xa4: // MRF = MRF + Rx * Ry (USI) + case 0xac: // MRF = MRF + Rx * Ry (USF) + case 0xad: // MRF = MRF + Rx * Ry (USFR) + case 0xb4: // MRF = MRF + Rx * Ry (SSI) + case 0xbc: // MRF = MRF + Rx * Ry (SSF) + case 0xbd: // MRF = MRF + Rx * Ry (SSFR) + case 0x86: // MRB = MRB + Rx * Ry (UUI) + case 0x8e: // MRB = MRB + Rx * Ry (UUF) + case 0x8f: // MRB = MRB + Rx * Ry (UUFR) + case 0x96: // MRB = MRB + Rx * Ry (SUI) + case 0x9e: // MRB = MRB + Rx * Ry (SUF) + case 0x9f: // MRB = MRB + Rx * Ry (SUFR) + case 0xa6: // MRB = MRB + Rx * Ry (USI) + case 0xae: // MRB = MRB + Rx * Ry (USF) + case 0xaf: // MRB = MRB + Rx * Ry (USFR) + case 0xb6: // MRB = MRB + Rx * Ry (SSI) + case 0xbe: // MRB = MRB + Rx * Ry (SSF) + case 0xbf: // MRB = MRB + Rx * Ry (SSFR) + case 0xc0: // Rn = MRF - Rx * Ry (UUI) + case 0xc8: // Rn = MRF - Rx * Ry (UUF) + case 0xc9: // Rn = MRF - Rx * Ry (UUFR) + case 0xd0: // Rn = MRF - Rx * Ry (SUI) + case 0xd8: // Rn = MRF - Rx * Ry (SUF) + case 0xd9: // Rn = MRF - Rx * Ry (SUFR) + case 0xe0: // Rn = MRF - Rx * Ry (USI) + case 0xe8: // Rn = MRF - Rx * Ry (USF) + case 0xe9: // Rn = MRF - Rx * Ry (USFR) + case 0xf0: // Rn = MRF - Rx * Ry (SSI) + case 0xf8: // Rn = MRF - Rx * Ry (SSF) + case 0xf9: // Rn = MRF - Rx * Ry (SSFR) + case 0xc2: // Rn = MRB - Rx * Ry (UUI) + case 0xca: // Rn = MRB - Rx * Ry (UUF) + case 0xcb: // Rn = MRB - Rx * Ry (UUFR) + case 0xd2: // Rn = MRB - Rx * Ry (SUI) + case 0xda: // Rn = MRB - Rx * Ry (SUF) + case 0xdb: // Rn = MRB - Rx * Ry (SUFR) + case 0xe2: // Rn = MRB - Rx * Ry (USI) + case 0xea: // Rn = MRB - Rx * Ry (USF) + case 0xeb: // Rn = MRB - Rx * Ry (USFR) + case 0xf2: // Rn = MRB - Rx * Ry (SSI) + case 0xfa: // Rn = MRB - Rx * Ry (SSF) + case 0xfb: // Rn = MRB - Rx * Ry (SSFR) + case 0xc4: // MRF = MRF - Rx * Ry (UUI) + case 0xcc: // MRF = MRF - Rx * Ry (UUF) + case 0xcd: // MRF = MRF - Rx * Ry (UUFR) + case 0xd4: // MRF = MRF - Rx * Ry (SUI) + case 0xdc: // MRF = MRF - Rx * Ry (SUF) + case 0xdd: // MRF = MRF - Rx * Ry (SUFR) + case 0xe4: // MRF = MRF - Rx * Ry (USI) + case 0xec: // MRF = MRF - Rx * Ry (USF) + case 0xed: // MRF = MRF - Rx * Ry (USFR) + case 0xf4: // MRF = MRF - Rx * Ry (SSI) + case 0xfc: // MRF = MRF - Rx * Ry (SSF) + case 0xfd: // MRF = MRF - Rx * Ry (SSFR) + case 0xc6: // MRB = MRB - Rx * Ry (UUI) + case 0xce: // MRB = MRB - Rx * Ry (UUF) + case 0xcf: // MRB = MRB - Rx * Ry (UUFR) + case 0xd6: // MRB = MRB - Rx * Ry (SUI) + case 0xde: // MRB = MRB - Rx * Ry (SUF) + case 0xdf: // MRB = MRB - Rx * Ry (SUFR) + case 0xe6: // MRB = MRB - Rx * Ry (USI) + case 0xee: // MRB = MRB - Rx * Ry (USF) + case 0xef: // MRB = MRB - Rx * Ry (USFR) + case 0xf6: // MRB = MRB - Rx * Ry (SSI) + case 0xfe: // MRB = MRB - Rx * Ry (SSF) + case 0xff: // MRB = MRB - Rx * Ry (SSFR) + case 0x00: // Rn = SAT MRF (UI) + case 0x01: // Rn = SAT MRF (SI) + case 0x08: // Rn = SAT MRF (UF) + case 0x09: // Rn = SAT MRF (SF) + case 0x02: // Rn = SAT MRB (UI) + case 0x03: // Rn = SAT MRB (SI) + case 0x0a: // Rn = SAT MRB (UF) + case 0x0b: // Rn = SAT MRB (SF) + case 0x04: // MRF = SAT MRF (UI) + case 0x05: // MRF = SAT MRF (SI) + case 0x0c: // MRF = SAT MRF (UF) + case 0x0d: // MRF = SAT MRF (SF) + case 0x06: // MRB = SAT MRB (UI) + case 0x07: // MRB = SAT MRB (SI) + case 0x0e: // MRB = SAT MRB (UF) + case 0x0f: // MRB = SAT MRB (SF) + case 0x18: // Rn = RND MRF (U) + case 0x19: // Rn = RND MRF (S) + case 0x1a: // Rn = RND MRB (U) + case 0x1b: // Rn = RND MRB (S) + case 0x1c: // MRF = RND MRF (U) + case 0x1d: // MRF = RND MRF (S) + case 0x1e: // MRB = RND MRB (U) + case 0x1f: // MRB = RND MRB (S) generate_unimplemented_compute(block, compiler, desc); return; - case 0x14: // MRF = 0 + case 0x14: // MRF = 0 UML_DMOV(block, mem(&m_core->mrf), 0); if (MN_CALC_REQUIRED) UML_MOV(block, ASTAT_MN, 0); if (MV_CALC_REQUIRED) UML_MOV(block, ASTAT_MV, 0); @@ -4881,7 +4881,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (MI_CALC_REQUIRED) UML_MOV(block, ASTAT_MI, 0); return; - case 0x16: // MRB = 0 + case 0x16: // MRB = 0 UML_DMOV(block, mem(&m_core->mrb), 0); if (MN_CALC_REQUIRED) UML_MOV(block, ASTAT_MN, 0); if (MV_CALC_REQUIRED) UML_MOV(block, ASTAT_MV, 0); @@ -4889,7 +4889,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (MI_CALC_REQUIRED) UML_MOV(block, ASTAT_MI, 0); return; - case 0x30: // Fn = Fx * Fy + case 0x30: // Fn = Fx * Fy UML_FSCOPYI(block, F0, REG(rx)); UML_FSCOPYI(block, F1, REG(ry)); UML_FSMUL(block, F0, F0, F1); @@ -4900,19 +4900,19 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com // TODO: MV, MU, MI flags return; - case 0x40: // Rn = Rx * Ry (UUI) + case 0x40: // Rn = Rx * Ry (UUI) UML_MULU(block, I0, I0, REG(rx), REG(ry)); UML_MOV(block, REG(rn), I0); // TODO: flags return; - case 0x70: // Rn = Rx * Ry (SSI) + case 0x70: // Rn = Rx * Ry (SSI) UML_MULS(block, I0, I0, REG(rx), REG(ry)); UML_MOV(block, REG(rn), I0); // TODO: flags return; - case 0xb0: // Rn = MRF + Rx * Ry (SSI) + case 0xb0: // Rn = MRF + Rx * Ry (SSI) UML_DSEXT(block, I0, REG(rx), SIZE_DWORD); UML_DSEXT(block, I1, REG(ry), SIZE_DWORD); UML_DMULS(block, I0, I0, I0, I1); @@ -4921,7 +4921,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com // TODO: flags! return; - case 0xb2: // Rn = MRB + Rx * Ry (SSI) + case 0xb2: // Rn = MRB + Rx * Ry (SSI) UML_DSEXT(block, I0, REG(rx), SIZE_DWORD); UML_DSEXT(block, I1, REG(ry), SIZE_DWORD); UML_DMULS(block, I0, I0, I0, I1); @@ -4937,25 +4937,25 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com break; } - case 2: // shifter operations + case 2: // shifter operations { switch (operation) { - case 0x04: // Rn = ASHIFT Rx BY Ry | <data8> - case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6> - case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE) - case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8> - case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE) - case 0x80: // Rn = EXP Rx - case 0x84: // Rn = EXP Rx (EX) - case 0x88: // Rn = LEFTZ Rx - case 0x8c: // Rn = LEFTO Rx - case 0x90: // Rn = FPACK Fx - case 0x94: // Fn = FUNPACK Rx + case 0x04: // Rn = ASHIFT Rx BY Ry | <data8> + case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6> + case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE) + case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8> + case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE) + case 0x80: // Rn = EXP Rx + case 0x84: // Rn = EXP Rx (EX) + case 0x88: // Rn = LEFTZ Rx + case 0x8c: // Rn = LEFTO Rx + case 0x90: // Rn = FPACK Fx + case 0x94: // Fn = FUNPACK Rx generate_unimplemented_compute(block, compiler, desc); return; - case 0x00: // Rn = LSHIFT Rx BY Ry | <data8> + case 0x00: // Rn = LSHIFT Rx BY Ry | <data8> { code_label shift_neg = compiler->labelnum++; code_label shift_end = compiler->labelnum++; @@ -4980,7 +4980,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0x08: // Rn = ROT Rx BY Ry | <data8> + case 0x08: // Rn = ROT Rx BY Ry | <data8> { code_label shift_neg = compiler->labelnum++; code_label shift_end = compiler->labelnum++; @@ -5001,7 +5001,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8> + case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8> { code_label shift_neg = compiler->labelnum++; code_label shift_end = compiler->labelnum++; @@ -5027,12 +5027,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6> + case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6> // extraction mask UML_MOV(block, I0, REG(ry)); UML_SHR(block, I1, I0, 6); - UML_AND(block, I1, I1, 0x3f); // i1 = len6 - UML_AND(block, I0, I0, 0x3f); // i0 = bit6 + UML_AND(block, I1, I1, 0x3f); // i1 = len6 + UML_AND(block, I0, I0, 0x3f); // i0 = bit6 UML_MOV(block, I3, 0xffffffff); UML_SUB(block, I2, 32, I1); UML_SHR(block, I3, I3, I2); @@ -5050,12 +5050,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE) + case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE) // extraction mask UML_MOV(block, I0, REG(ry)); UML_SHR(block, I1, I0, 6); - UML_AND(block, I1, I1, 0x3f); // i1 = len6 - UML_AND(block, I0, I0, 0x3f); // i0 = bit6 + UML_AND(block, I1, I1, 0x3f); // i1 = len6 + UML_AND(block, I0, I0, 0x3f); // i0 = bit6 UML_MOV(block, I3, 0xffffffff); UML_SUB(block, I2, 32, I1); UML_SHR(block, I3, I3, I2); @@ -5079,12 +5079,12 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> + case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> // extraction mask UML_MOV(block, I0, REG(ry)); UML_SHR(block, I1, I0, 6); - UML_AND(block, I1, I1, 0x3f); // i1 = len6 - UML_AND(block, I0, I0, 0x3f); // i0 = bit6 + UML_AND(block, I1, I1, 0x3f); // i1 = len6 + UML_AND(block, I0, I0, 0x3f); // i0 = bit6 UML_MOV(block, I3, 0xffffffff); UML_SUB(block, I2, 32, I1); UML_SHR(block, I3, I3, I2); @@ -5102,7 +5102,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0xc0: // Rn = BSET Rx BY Ry | <data8> + case 0xc0: // Rn = BSET Rx BY Ry | <data8> { UML_MOV(block, I0, REG(ry)); UML_SHL(block, I1, 1, I0); @@ -5117,7 +5117,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0xc4: // Rn = BCLR Rx BY Ry | <data8> + case 0xc4: // Rn = BCLR Rx BY Ry | <data8> { UML_MOV(block, I0, REG(ry)); UML_SHL(block, I1, 1, I0); @@ -5133,14 +5133,14 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com return; } - case 0xcc: // BTST Rx BY Ry | <data8> + case 0xcc: // BTST Rx BY Ry | <data8> { UML_MOV(block, I0, REG(ry)); UML_SHL(block, I1, 1, I0); UML_TEST(block, REG(rx), I1); if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ); - if (SV_CALC_REQUIRED) - UML_CMP(block, I0, 31); + if (SV_CALC_REQUIRED) + UML_CMP(block, I0, 31); if (SV_CALC_REQUIRED) UML_SETc(block, COND_G, ASTAT_SV); if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; @@ -5383,7 +5383,7 @@ void adsp21062_device::generate_do_condition(drcuml_block *block, compiler_state // infinite loop break; case 0x0f: /* LCE */ - fatalerror("generate_do_condition 0x0f"); // this should only be used with counter loops + fatalerror("generate_do_condition 0x0f"); // this should only be used with counter loops break; case 0x10: /* NOT EQUAL */ UML_TEST(block, mem(&m_core->astat_delay_copy.az), 1); @@ -5465,16 +5465,16 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c int len = (data >> 6) & 0x3f; switch (shiftop) - { - case 0x11: // FDEP Rx BY <bit6>:<len6> - case 0x13: // FDEP Rx BY <bit6>:<len6> (SE) - case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE) + { + case 0x11: // FDEP Rx BY <bit6>:<len6> + case 0x13: // FDEP Rx BY <bit6>:<len6> (SE) + case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE) UML_MOV(block, mem(&m_core->pc), desc->pc); UML_DMOV(block, mem(&m_core->arg64), desc->opptr.q[0]); UML_CALLC(block, cfunc_unimplemented_shiftimm, this); break; - case 0x00: // LSHIFT Rx BY <data8> + case 0x00: // LSHIFT Rx BY <data8> if (abs(shift) >= 32) { UML_MOV(block, REG(rn), 0); @@ -5495,7 +5495,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c } return; - case 0x01: // ASHIFT Rx BY <data8> + case 0x01: // ASHIFT Rx BY <data8> if (abs(shift) >= 32) { UML_MOV(block, REG(rn), 0); @@ -5518,7 +5518,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c } return; - case 0x02: // ROT Rx BY <data8> + case 0x02: // ROT Rx BY <data8> if (shift < 0) UML_ROR(block, REG(rn), REG(rx), (-shift) & 0x1f); else @@ -5528,7 +5528,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8> + case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8> if (abs(shift) >= 32) { UML_MOV(block, I0, 0); @@ -5551,7 +5551,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c } return; - case 0x10: // FEXT Rx BY <bit6>:<len6> + case 0x10: // FEXT Rx BY <bit6>:<len6> if (bit == 0) { UML_AND(block, REG(rn), REG(rx), MAKE_EXTRACT_MASK(bit, len)); @@ -5567,7 +5567,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x12: // FEXT Rx BY <bit6>:<len6> (SE) + case 0x12: // FEXT Rx BY <bit6>:<len6> (SE) UML_AND(block, I0, REG(rx), MAKE_EXTRACT_MASK(bit, len)); UML_SHL(block, I0, I0, 32 - (bit + len)); UML_SAR(block, REG(rn), I0, 32 - (bit + len) + bit); @@ -5577,7 +5577,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> + case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> UML_AND(block, I0, REG(rx), MAKE_EXTRACT_MASK(0, len)); if (bit > 0) UML_SHL(block, I0, I0, bit); @@ -5586,10 +5586,10 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ); if (SV_CALC_REQUIRED && (bit + len) > 32) UML_MOV(block, ASTAT_SV, 1); if (SV_CALC_REQUIRED && (bit + len) <= 32) UML_MOV(block, ASTAT_SV, 0); - if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); + if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x30: // BSET Rx BY <data8> + case 0x30: // BSET Rx BY <data8> UML_OR(block, REG(rn), REG(rx), 1 << data); if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ); if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1); @@ -5597,7 +5597,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x31: // BCLR Rx By <data8> + case 0x31: // BCLR Rx By <data8> UML_AND(block, REG(rn), REG(rx), ~(1 << data)); if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ); if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1); @@ -5605,7 +5605,7 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x32: // BTGL Rx BY <data8> + case 0x32: // BTGL Rx BY <data8> UML_XOR(block, REG(rn), REG(rx), 1 << data); if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ); if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1); @@ -5613,8 +5613,8 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0); return; - case 0x33: // BTST Rx BY <data8> - UML_TEST(block, REG(rx), 1 << data); + case 0x33: // BTST Rx BY <data8> + UML_TEST(block, REG(rx), 1 << data); if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ); if (SV_CALC_REQUIRED && data > 31) UML_MOV(block, ASTAT_SV, 1); if (SV_CALC_REQUIRED && data <= 31) UML_MOV(block, ASTAT_SV, 0); @@ -5627,4 +5627,4 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c UML_CALLC(block, cfunc_unimplemented_compute, this); return; } -}
\ No newline at end of file +} diff --git a/src/devices/cpu/sharc/sharcfe.cpp b/src/devices/cpu/sharc/sharcfe.cpp index bae9014ee33..105eea6c66c 100644 --- a/src/devices/cpu/sharc/sharcfe.cpp +++ b/src/devices/cpu/sharc/sharcfe.cpp @@ -10,62 +10,62 @@ #include "emu.h" #include "sharcfe.h" -#define REG_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0) -#define REG_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0) - -#define AZ_USED(desc) do { (desc).regin[0] |= 1 << 16; } while(0) -#define AZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 16; } while(0) -#define AV_USED(desc) do { (desc).regin[0] |= 1 << 17; } while(0) -#define AV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 17; } while(0) -#define AN_USED(desc) do { (desc).regin[0] |= 1 << 18; } while(0) -#define AN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 18; } while(0) -#define AC_USED(desc) do { (desc).regin[0] |= 1 << 19; } while(0) -#define AC_MODIFIED(desc) do { (desc).regout[0] |= 1 << 19; } while(0) -#define AS_USED(desc) do { (desc).regin[0] |= 1 << 20; } while(0) -#define AS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 20; } while(0) -#define AI_USED(desc) do { (desc).regin[0] |= 1 << 21; } while(0) -#define AI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 21; } while(0) -#define MN_USED(desc) do { (desc).regin[0] |= 1 << 22; } while(0) -#define MN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 22; } while(0) -#define MV_USED(desc) do { (desc).regin[0] |= 1 << 23; } while(0) -#define MV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 23; } while(0) -#define MU_USED(desc) do { (desc).regin[0] |= 1 << 24; } while(0) -#define MU_MODIFIED(desc) do { (desc).regout[0] |= 1 << 24; } while(0) -#define MI_USED(desc) do { (desc).regin[0] |= 1 << 25; } while(0) -#define MI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 25; } while(0) -#define SV_USED(desc) do { (desc).regin[0] |= 1 << 26; } while(0) -#define SV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 26; } while(0) -#define SZ_USED(desc) do { (desc).regin[0] |= 1 << 27; } while(0) -#define SZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 27; } while(0) -#define SS_USED(desc) do { (desc).regin[0] |= 1 << 28; } while(0) -#define SS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 28; } while(0) -#define BTF_USED(desc) do { (desc).regin[0] |= 1 << 29; } while(0) -#define BTF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 29; } while(0) -#define AF_USED(desc) do { (desc).regin[0] |= 1 << 30; } while(0) -#define AF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 30; } while(0) - -#define ALU_FLAGS_MODIFIED(desc) do { AZ_MODIFIED(desc);AN_MODIFIED(desc);AV_MODIFIED(desc);AC_MODIFIED(desc);AS_MODIFIED(desc);AI_MODIFIED(desc); } while(0) -#define MULT_FLAGS_MODIFIED(desc) do { MN_MODIFIED(desc);MV_MODIFIED(desc);MU_MODIFIED(desc);MI_MODIFIED(desc); } while(0) -#define SHIFT_FLAGS_MODIFIED(desc) do { SZ_MODIFIED(desc);SV_MODIFIED(desc);SS_MODIFIED(desc); } while(0) - - -#define PM_I_USED(desc,x) do { (desc).regin[1] |= 1 << (x); } while(0) -#define PM_I_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (x); } while(0) -#define PM_M_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 8); } while(0) -#define PM_M_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 8); } while(0) -#define PM_B_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 16); } while(0) -#define PM_B_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 16); } while(0) -#define PM_L_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 24); } while(0) -#define PM_L_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 24); } while(0) - -#define DM_I_USED(desc,x) do { (desc).regin[2] |= 1 << (x); } while(0) -#define DM_I_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << (x); } while(0) -#define DM_M_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 8); } while(0) -#define DM_M_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 8); } while(0) -#define DM_B_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 16); } while(0) -#define DM_B_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 16); } while(0) -#define DM_L_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 24); } while(0) -#define DM_L_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 24); } while(0) +#define REG_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0) +#define REG_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0) + +#define AZ_USED(desc) do { (desc).regin[0] |= 1 << 16; } while(0) +#define AZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 16; } while(0) +#define AV_USED(desc) do { (desc).regin[0] |= 1 << 17; } while(0) +#define AV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 17; } while(0) +#define AN_USED(desc) do { (desc).regin[0] |= 1 << 18; } while(0) +#define AN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 18; } while(0) +#define AC_USED(desc) do { (desc).regin[0] |= 1 << 19; } while(0) +#define AC_MODIFIED(desc) do { (desc).regout[0] |= 1 << 19; } while(0) +#define AS_USED(desc) do { (desc).regin[0] |= 1 << 20; } while(0) +#define AS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 20; } while(0) +#define AI_USED(desc) do { (desc).regin[0] |= 1 << 21; } while(0) +#define AI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 21; } while(0) +#define MN_USED(desc) do { (desc).regin[0] |= 1 << 22; } while(0) +#define MN_MODIFIED(desc) do { (desc).regout[0] |= 1 << 22; } while(0) +#define MV_USED(desc) do { (desc).regin[0] |= 1 << 23; } while(0) +#define MV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 23; } while(0) +#define MU_USED(desc) do { (desc).regin[0] |= 1 << 24; } while(0) +#define MU_MODIFIED(desc) do { (desc).regout[0] |= 1 << 24; } while(0) +#define MI_USED(desc) do { (desc).regin[0] |= 1 << 25; } while(0) +#define MI_MODIFIED(desc) do { (desc).regout[0] |= 1 << 25; } while(0) +#define SV_USED(desc) do { (desc).regin[0] |= 1 << 26; } while(0) +#define SV_MODIFIED(desc) do { (desc).regout[0] |= 1 << 26; } while(0) +#define SZ_USED(desc) do { (desc).regin[0] |= 1 << 27; } while(0) +#define SZ_MODIFIED(desc) do { (desc).regout[0] |= 1 << 27; } while(0) +#define SS_USED(desc) do { (desc).regin[0] |= 1 << 28; } while(0) +#define SS_MODIFIED(desc) do { (desc).regout[0] |= 1 << 28; } while(0) +#define BTF_USED(desc) do { (desc).regin[0] |= 1 << 29; } while(0) +#define BTF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 29; } while(0) +#define AF_USED(desc) do { (desc).regin[0] |= 1 << 30; } while(0) +#define AF_MODIFIED(desc) do { (desc).regout[0] |= 1 << 30; } while(0) + +#define ALU_FLAGS_MODIFIED(desc) do { AZ_MODIFIED(desc);AN_MODIFIED(desc);AV_MODIFIED(desc);AC_MODIFIED(desc);AS_MODIFIED(desc);AI_MODIFIED(desc); } while(0) +#define MULT_FLAGS_MODIFIED(desc) do { MN_MODIFIED(desc);MV_MODIFIED(desc);MU_MODIFIED(desc);MI_MODIFIED(desc); } while(0) +#define SHIFT_FLAGS_MODIFIED(desc) do { SZ_MODIFIED(desc);SV_MODIFIED(desc);SS_MODIFIED(desc); } while(0) + + +#define PM_I_USED(desc,x) do { (desc).regin[1] |= 1 << (x); } while(0) +#define PM_I_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (x); } while(0) +#define PM_M_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 8); } while(0) +#define PM_M_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 8); } while(0) +#define PM_B_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 16); } while(0) +#define PM_B_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 16); } while(0) +#define PM_L_USED(desc,x) do { (desc).regin[1] |= 1 << ((x) + 24); } while(0) +#define PM_L_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << ((x) + 24); } while(0) + +#define DM_I_USED(desc,x) do { (desc).regin[2] |= 1 << (x); } while(0) +#define DM_I_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << (x); } while(0) +#define DM_M_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 8); } while(0) +#define DM_M_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 8); } while(0) +#define DM_B_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 16); } while(0) +#define DM_B_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 16); } while(0) +#define DM_L_USED(desc,x) do { (desc).regin[2] |= 1 << ((x) + 24); } while(0) +#define DM_L_MODIFIED(desc,x) do { (desc).regout[2] |= 1 << ((x) + 24); } while(0) sharc_frontend::sharc_frontend(adsp21062_device *sharc, UINT32 window_start, UINT32 window_end, UINT32 max_sequence) @@ -221,12 +221,12 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) switch ((opcode >> 45) & 7) { - case 0: // subops + case 0: // subops { UINT32 subop = (opcode >> 40) & 0x1f; switch (subop) { - case 0x00: // NOP / idle |000|00000| + case 0x00: // NOP / idle |000|00000| if (opcode & U64(0x008000000000)) { // IDLE @@ -236,9 +236,9 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) { // NOP } - break; + break; - case 0x01: // compute |000|00001| + case 0x01: // compute |000|00001| { int cond = (opcode >> 33) & 0x1f; describe_if_condition(desc, cond); @@ -248,7 +248,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x02: // immediate shift |000|00010| + case 0x02: // immediate shift |000|00010| { int shiftop = (opcode >> 16) & 0x3f; int rn = (opcode >> 4) & 0xf; @@ -261,8 +261,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) return false; break; } - - case 0x04: // compute / modify |000|00100| + + case 0x04: // compute / modify |000|00100| { int g = (opcode >> 38) & 0x1; int m = (opcode >> 27) & 0x7; @@ -291,8 +291,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x06: // direct jump|call |000|00110| - { + case 0x06: // direct jump|call |000|00110| + { int j = (opcode >> 26) & 0x1; int b = (opcode >> 39) & 0x1; int cond = (opcode >> 33) & 0x1f; @@ -312,7 +312,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x07: // direct jump|call |000|00111| + case 0x07: // direct jump|call |000|00111| { int j = (opcode >> 26) & 0x1; int b = (opcode >> 39) & 0x1; @@ -333,8 +333,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x08: // indirect jump|call / compute |000|01000| - { + case 0x08: // indirect jump|call / compute |000|01000| + { int j = (opcode >> 26) & 0x1; int b = (opcode >> 39) & 0x1; int pmi = (opcode >> 30) & 0x7; @@ -361,12 +361,12 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x09: // indirect jump|call / compute |000|01001| + case 0x09: // indirect jump|call / compute |000|01001| { int j = (opcode >> 26) & 0x1; int b = (opcode >> 39) & 0x1; int cond = (opcode >> 33) & 0x1f; - + if (!describe_compute(desc, opcode)) return false; @@ -384,7 +384,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x0a: // return from subroutine / compute |000|01010| + case 0x0a: // return from subroutine / compute |000|01010| { int cond = (opcode >> 33) & 0x1f; int j = (opcode >> 26) & 0x1; @@ -404,7 +404,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x0b: // return from interrupt / compute |000|01011| + case 0x0b: // return from interrupt / compute |000|01011| { int cond = (opcode >> 33) & 0x1f; int j = (opcode >> 26) & 0x1; @@ -424,7 +424,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x0c: // do until counter expired |000|01100| + case 0x0c: // do until counter expired |000|01100| { int offset = SIGN_EXTEND24(opcode & 0xffffff); @@ -439,7 +439,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x0d: // do until counter expired |000|01101| + case 0x0d: // do until counter expired |000|01101| { int ureg = (opcode >> 32) & 0xff; if (!describe_ureg_access(desc, ureg, UREG_READ)) @@ -458,7 +458,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x0e: // do until |000|01110| + case 0x0e: // do until |000|01110| { int offset = SIGN_EXTEND24(opcode & 0xffffff); int cond = (opcode >> 33) & 0x1f; @@ -472,8 +472,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) /* loop.astat_check_pc = loop.end_pc - 2; if (loop.astat_check_pc < loop.start_pc) - fatalerror("describe_compute: conditional loop < 2 at %08X", desc.pc); - */ + fatalerror("describe_compute: conditional loop < 2 at %08X", desc.pc); + */ int jump_diff = loop.end_pc - loop.start_pc; if (jump_diff >= 2) @@ -488,7 +488,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x0f: // immediate data -> ureg |000|01111| + case 0x0f: // immediate data -> ureg |000|01111| { int ureg = (opcode >> 32) & 0xff; if (!describe_ureg_access(desc, ureg, UREG_WRITE)) @@ -496,7 +496,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D| + case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D| case 0x11: case 0x12: case 0x13: @@ -518,7 +518,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x14: // system register bit manipulation |000|10100| + case 0x14: // system register bit manipulation |000|10100| { int bop = (opcode >> 37) & 0x7; int sreg = (opcode >> 32) & 0xf; @@ -526,10 +526,10 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) switch (bop) { - case 0: // SET - case 1: // CLEAR - case 2: // TOGGLE - if (sreg == 0x7c) // ASTAT + case 0: // SET + case 1: // CLEAR + case 2: // TOGGLE + if (sreg == 0x7c) // ASTAT { if (data & adsp21062_device::AZ) { @@ -594,8 +594,8 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) } break; - case 4: // TEST - case 5: // XOR + case 4: // TEST + case 5: // XOR BTF_MODIFIED(desc); break; @@ -606,13 +606,13 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x16: // I register modify / bit-reverse |000|10110| + case 0x16: // I register modify / bit-reverse |000|10110| { - if (opcode & U64(0x008000000000)) // bit reverse + if (opcode & U64(0x008000000000)) // bit reverse { fatalerror("sharc_frontend::describe: bit reverse unimplemented"); } - else // modify + else // modify { int g = (opcode >> 38) & 0x1; int i = (opcode >> 32) & 0x7; @@ -625,17 +625,17 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 0x17: // push|pop stacks / flush cache |000|10111| + case 0x17: // push|pop stacks / flush cache |000|10111| break; - case 0x18: // cjump |000|11000| + case 0x18: // cjump |000|11000| fatalerror("sharc_frontend::describe: cjump unimplemented"); break; - case 0x19: // rframe |000|11001| + case 0x19: // rframe |000|11001| fatalerror("sharc_frontend::describe: rframe unimplemented"); break; - + default: fatalerror("sharc_frontend::describe: unknown subop %02X in opcode %04X%08X", subop, (UINT16)(opcode >> 32), (UINT32)(opcode)); return false; @@ -643,7 +643,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 1: // compute / dreg <-> DM / dreg <-> PM |001| + case 1: // compute / dreg <-> DM / dreg <-> PM |001| { if (!describe_compute(desc, opcode)) return false; @@ -689,7 +689,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 2: // compute / ureg <-> DM|PM, register modify |010| + case 2: // compute / ureg <-> DM|PM, register modify |010| { if (!describe_compute(desc, opcode)) return false; @@ -737,7 +737,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) if (!describe_compute(desc, opcode)) return false; - if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1| + if (opcode & U64(0x100000000000)) // compute / ureg <-> ureg |011|1| { int src_ureg = (opcode >> 36) & 0xff; int dst_ureg = (opcode >> 23) & 0xff; @@ -750,7 +750,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) if (!describe_ureg_access(desc, dst_ureg, UREG_WRITE)) return false; } - else // compute / dreg <-> DM|PM, immediate modify |011|0| + else // compute / dreg <-> DM|PM, immediate modify |011|0| { int u = (opcode >> 38) & 0x1; int d = (opcode >> 39) & 0x1; @@ -771,13 +771,13 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) REG_MODIFIED(desc, dreg); desc.flags |= OPFLAG_READS_MEMORY; } - + if (g) { // PM PM_I_USED(desc, i); - if (u) // post-modify with update + if (u) // post-modify with update { PM_I_MODIFIED(desc, i); } @@ -787,7 +787,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) // DM DM_I_USED(desc, i); - if (u) // post-modify with update + if (u) // post-modify with update { DM_I_MODIFIED(desc, i); } @@ -798,7 +798,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) case 4: { - if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1| + if (opcode & U64(0x100000000000)) // immediate data -> DM|PM |100|1| { int i = (opcode >> 41) & 0x7; int m = (opcode >> 38) & 0x7; @@ -821,7 +821,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) DM_M_USED(desc, m); } } - else // immediate shift / dreg <-> DM|PM |100|0| + else // immediate shift / dreg <-> DM|PM |100|0| { int i = (opcode >> 41) & 0x7; int m = (opcode >> 38) & 0x7; @@ -867,7 +867,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 5: // ureg <-> DM|PM (indirect) |101| + case 5: // ureg <-> DM|PM (indirect) |101| { int ureg = (opcode >> 32) & 0xff; int d = (opcode >> 40) & 1; @@ -890,11 +890,11 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) if (g) PM_I_USED(desc, i); else - DM_I_USED(desc, i); + DM_I_USED(desc, i); break; } - case 6: // indirect jump / compute / dreg <-> DM |110| + case 6: // indirect jump / compute / dreg <-> DM |110| { int d = (opcode >> 44) & 0x1; int dmi = (opcode >> 41) & 0x7; @@ -936,7 +936,7 @@ bool sharc_frontend::describe(opcode_desc &desc, const opcode_desc *prev) break; } - case 7: // indirect jump / compute / dreg <-> DM |111| + case 7: // indirect jump / compute / dreg <-> DM |111| { int d = (opcode >> 44) & 0x1; int dmi = (opcode >> 41) & 0x7; @@ -990,7 +990,7 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) int rx = (opcode >> 4) & 0xf; int ry = (opcode >> 0) & 0xf; - if (opcode & 0x400000) // multi-function operation + if (opcode & 0x400000) // multi-function operation { UINT32 multiop = (opcode >> 16) & 0x3f; int fm = rs; @@ -1002,15 +1002,15 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) switch (multiop) { - case 0x00: // Rn = MRxx + case 0x00: // Rn = MRxx REG_MODIFIED(desc, rn); break; - case 0x01: // MRxx = Rn + case 0x01: // MRxx = Rn REG_USED(desc, rn); break; - case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry - case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy + case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry + case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy REG_USED(desc, rx); REG_USED(desc, ry); REG_MODIFIED(desc, ra); @@ -1018,9 +1018,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) ALU_FLAGS_MODIFIED(desc); break; - case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 - case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 - case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 + case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 + case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 + case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 REG_USED(desc, fxm); REG_USED(desc, fym); REG_USED(desc, fxa); @@ -1031,9 +1031,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12 - case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12 - case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2 + case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12 + case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12 + case 0x0a: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2 REG_USED(desc, fxm); REG_USED(desc, fym); REG_USED(desc, fxa); @@ -1042,9 +1042,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 - case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 - case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 + case 0x0c: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 + case 0x0d: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 + case 0x0e: // Rm = MRF + R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 REG_USED(desc, fxm); REG_USED(desc, fym); REG_USED(desc, fxa); @@ -1055,9 +1055,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12 - case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12 - case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2 + case 0x10: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12 + case 0x11: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12 + case 0x12: // MRF = MRF - R3-0 * R7-4 (SSF), Ra = (R11-8 + R15-12) / 2 REG_USED(desc, fxm); REG_USED(desc, fym); REG_USED(desc, fxa); @@ -1066,9 +1066,9 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 - case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 - case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 + case 0x14: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12 + case 0x15: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12 + case 0x16: // Rm = MRF - R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2 REG_USED(desc, fxm); REG_USED(desc, fym); REG_USED(desc, fxa); @@ -1079,13 +1079,13 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12 - case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12 - case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12 - case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12 - case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2 - case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12) - case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12) + case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12 + case 0x19: // Fm = F3-0 * F7-4, Fa = F11-8 - F15-12 + case 0x1a: // Fm = F3-0 * F7-4, Fa = FLOAT F11-8 BY R15-12 + case 0x1b: // Fm = F3-0 * F7-4, Fa = FIX F11-8 BY R15-12 + case 0x1c: // Fm = F3-0 * F7-4, Fa = (F11-8 + F15-12) / 2 + case 0x1e: // Fm = F3-0 * F7-4, Fa = MAX(F11-8, F15-12) + case 0x1f: // Fm = F3-0 * F7-4, Fa = MIN(F11-8, F15-12) REG_USED(desc, fxm); REG_USED(desc, fym); REG_USED(desc, fxa); @@ -1096,7 +1096,7 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8 + case 0x1d: // Fm = F3-0 * F7-4, Fa = ABS F11-8 REG_USED(desc, fxm); REG_USED(desc, fym); REG_USED(desc, fxa); @@ -1139,48 +1139,48 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) return false; } } - else // single-function operation + else // single-function operation { UINT32 operation = (opcode >> 12) & 0xff; switch ((opcode >> 20) & 3) { - case 0: // ALU operations + case 0: // ALU operations { switch (operation) { - case 0x01: // Rn = Rx + Ry - case 0x02: // Rn = Rx - Ry - case 0x09: // Rn = (Rx + Ry) / 2 - case 0x40: // Rn = Rx AND Ry - case 0x41: // Rn = Rx OR Ry - case 0x42: // Rn = Rx XOR Ry - case 0x61: // Rn = MIN(Rx, Ry) - case 0x62: // Rn = MAX(Rx, Ry) - case 0x63: // Rn = CLIP Rx BY Ry - case 0x81: // Fn = Fx + Fy - case 0x82: // Fn = Fx - Fy - case 0x91: // Fn = ABS(Fx + Fy) - case 0x92: // Fn = ABS(Fx - Fy) - case 0x89: // Fn = (Fx + Fy) / 2 - case 0xbd: // Fn = SCALB Fx BY Ry - case 0xd9: // Rn = FIX Fx BY Ry - case 0xdd: // Rn = TRUNC Fx BY Ry - case 0xda: // Fn = FLOAT Rx BY Ry - case 0xe1: // Fn = MIN(Fx, Fy) - case 0xe2: // Fn = MAX(Fx, Fy) - case 0xe3: // Fn = CLIP Fx BY Fy - case 0xe0: // Fn = Fx COPYSIGN Fy + case 0x01: // Rn = Rx + Ry + case 0x02: // Rn = Rx - Ry + case 0x09: // Rn = (Rx + Ry) / 2 + case 0x40: // Rn = Rx AND Ry + case 0x41: // Rn = Rx OR Ry + case 0x42: // Rn = Rx XOR Ry + case 0x61: // Rn = MIN(Rx, Ry) + case 0x62: // Rn = MAX(Rx, Ry) + case 0x63: // Rn = CLIP Rx BY Ry + case 0x81: // Fn = Fx + Fy + case 0x82: // Fn = Fx - Fy + case 0x91: // Fn = ABS(Fx + Fy) + case 0x92: // Fn = ABS(Fx - Fy) + case 0x89: // Fn = (Fx + Fy) / 2 + case 0xbd: // Fn = SCALB Fx BY Ry + case 0xd9: // Rn = FIX Fx BY Ry + case 0xdd: // Rn = TRUNC Fx BY Ry + case 0xda: // Fn = FLOAT Rx BY Ry + case 0xe1: // Fn = MIN(Fx, Fy) + case 0xe2: // Fn = MAX(Fx, Fy) + case 0xe3: // Fn = CLIP Fx BY Fy + case 0xe0: // Fn = Fx COPYSIGN Fy REG_USED(desc, rx); REG_USED(desc, ry); REG_MODIFIED(desc, rn); ALU_FLAGS_MODIFIED(desc); break; - case 0x05: // Rn = Rx + Ry + CI - case 0x06: // Rn = Rx - Ry + CI - 1 - case 0x25: // Rn = Rx + CI - case 0x26: // Rn = Rx + CI - 1 + case 0x05: // Rn = Rx + Ry + CI + case 0x06: // Rn = Rx - Ry + CI - 1 + case 0x25: // Rn = Rx + CI + case 0x26: // Rn = Rx + CI - 1 REG_USED(desc, rx); REG_USED(desc, ry); REG_MODIFIED(desc, rn); @@ -1188,30 +1188,30 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) ALU_FLAGS_MODIFIED(desc); break; - case 0x0a: // COMP(Rx, Ry) - case 0x8a: // COMP(Fx, Fy) + case 0x0a: // COMP(Rx, Ry) + case 0x8a: // COMP(Fx, Fy) REG_USED(desc, rx); REG_USED(desc, ry); ALU_FLAGS_MODIFIED(desc); break; - case 0x29: // Rn = Rx + 1 - case 0x2a: // Rn = Rx - 1 - case 0x22: // Rn = -Rx - case 0x30: // Rn = ABS Rx - case 0x21: // Rn = PASS Rx - case 0x43: // Rn = NOT Rx - case 0xb0: // Fn = ABS(Fx) - case 0xa1: // Fn = PASS Fx - case 0xa2: // Fn = -Fx - case 0xa5: // Fn = RND Fx - case 0xad: // Rn = MANT Fx - case 0xc1: // Rn = LOGB Fx - case 0xc9: // Rn = FIX Fx - case 0xcd: // Rn = TRUNC Fx - case 0xca: // Fn = FLOAT Rx - case 0xc4: // Fn = RECIPS Fx - case 0xc5: // Fn = RSQRTS Fx + case 0x29: // Rn = Rx + 1 + case 0x2a: // Rn = Rx - 1 + case 0x22: // Rn = -Rx + case 0x30: // Rn = ABS Rx + case 0x21: // Rn = PASS Rx + case 0x43: // Rn = NOT Rx + case 0xb0: // Fn = ABS(Fx) + case 0xa1: // Fn = PASS Fx + case 0xa2: // Fn = -Fx + case 0xa5: // Fn = RND Fx + case 0xad: // Rn = MANT Fx + case 0xc1: // Rn = LOGB Fx + case 0xc9: // Rn = FIX Fx + case 0xcd: // Rn = TRUNC Fx + case 0xca: // Fn = FLOAT Rx + case 0xc4: // Fn = RECIPS Fx + case 0xc5: // Fn = RSQRTS Fx REG_USED(desc, rx); REG_MODIFIED(desc, rn); ALU_FLAGS_MODIFIED(desc); @@ -1248,76 +1248,76 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) break; } - case 1: // multiplier operations + case 1: // multiplier operations { switch (operation) { - case 0x40: // Rn = Rx * Ry (UUI) - case 0x48: // Rn = Rx * Ry (UUF) - case 0x49: // Rn = Rx * Ry (UUFR) - case 0x50: // Rn = Rx * Ry (SUI) - case 0x58: // Rn = Rx * Ry (SUF) - case 0x59: // Rn = Rx * Ry (SUFR) - case 0x60: // Rn = Rx * Ry (USI) - case 0x68: // Rn = Rx * Ry (USF) - case 0x69: // Rn = Rx * Ry (USFR) - case 0x70: // Rn = Rx * Ry (SSI) - case 0x78: // Rn = Rx * Ry (SSF) - case 0x79: // Rn = Rx * Ry (SSFR) + case 0x40: // Rn = Rx * Ry (UUI) + case 0x48: // Rn = Rx * Ry (UUF) + case 0x49: // Rn = Rx * Ry (UUFR) + case 0x50: // Rn = Rx * Ry (SUI) + case 0x58: // Rn = Rx * Ry (SUF) + case 0x59: // Rn = Rx * Ry (SUFR) + case 0x60: // Rn = Rx * Ry (USI) + case 0x68: // Rn = Rx * Ry (USF) + case 0x69: // Rn = Rx * Ry (USFR) + case 0x70: // Rn = Rx * Ry (SSI) + case 0x78: // Rn = Rx * Ry (SSF) + case 0x79: // Rn = Rx * Ry (SSFR) REG_USED(desc, rx); REG_USED(desc, ry); REG_MODIFIED(desc, rn); MULT_FLAGS_MODIFIED(desc); break; - case 0x44: // MRF = Rx * Ry (UUI) - case 0x4c: // MRF = Rx * Ry (UUF) - case 0x4d: // MRF = Rx * Ry (UUFR) - case 0x54: // MRF = Rx * Ry (SUI) - case 0x5c: // MRF = Rx * Ry (SUF) - case 0x5d: // MRF = Rx * Ry (SUFR) - case 0x64: // MRF = Rx * Ry (USI) - case 0x6c: // MRF = Rx * Ry (USF) - case 0x6d: // MRF = Rx * Ry (USFR) - case 0x74: // MRF = Rx * Ry (SSI) - case 0x7c: // MRF = Rx * Ry (SSF) - case 0x7d: // MRF = Rx * Ry (SSFR) + case 0x44: // MRF = Rx * Ry (UUI) + case 0x4c: // MRF = Rx * Ry (UUF) + case 0x4d: // MRF = Rx * Ry (UUFR) + case 0x54: // MRF = Rx * Ry (SUI) + case 0x5c: // MRF = Rx * Ry (SUF) + case 0x5d: // MRF = Rx * Ry (SUFR) + case 0x64: // MRF = Rx * Ry (USI) + case 0x6c: // MRF = Rx * Ry (USF) + case 0x6d: // MRF = Rx * Ry (USFR) + case 0x74: // MRF = Rx * Ry (SSI) + case 0x7c: // MRF = Rx * Ry (SSF) + case 0x7d: // MRF = Rx * Ry (SSFR) // TODO: track MRF? REG_USED(desc, rx); REG_USED(desc, ry); MULT_FLAGS_MODIFIED(desc); break; - case 0x46: // MRB = Rx * Ry (UUI) - case 0x4e: // MRB = Rx * Ry (UUF) - case 0x4f: // MRB = Rx * Ry (UUFR) - case 0x56: // MRB = Rx * Ry (SUI) - case 0x5e: // MRB = Rx * Ry (SUF) - case 0x5f: // MRB = Rx * Ry (SUFR) - case 0x66: // MRB = Rx * Ry (USI) - case 0x6e: // MRB = Rx * Ry (USF) - case 0x6f: // MRB = Rx * Ry (USFR) - case 0x76: // MRB = Rx * Ry (SSI) - case 0x7e: // MRB = Rx * Ry (SSF) - case 0x7f: // MRB = Rx * Ry (SSFR) + case 0x46: // MRB = Rx * Ry (UUI) + case 0x4e: // MRB = Rx * Ry (UUF) + case 0x4f: // MRB = Rx * Ry (UUFR) + case 0x56: // MRB = Rx * Ry (SUI) + case 0x5e: // MRB = Rx * Ry (SUF) + case 0x5f: // MRB = Rx * Ry (SUFR) + case 0x66: // MRB = Rx * Ry (USI) + case 0x6e: // MRB = Rx * Ry (USF) + case 0x6f: // MRB = Rx * Ry (USFR) + case 0x76: // MRB = Rx * Ry (SSI) + case 0x7e: // MRB = Rx * Ry (SSF) + case 0x7f: // MRB = Rx * Ry (SSFR) // TODO: track MRB? REG_USED(desc, rx); REG_USED(desc, ry); MULT_FLAGS_MODIFIED(desc); break; - case 0x80: // Rn = MRF + Rx * Ry (UUI) - case 0x88: // Rn = MRF + Rx * Ry (UUF) - case 0x89: // Rn = MRF + Rx * Ry (UUFR) - case 0x90: // Rn = MRF + Rx * Ry (SUI) - case 0x98: // Rn = MRF + Rx * Ry (SUF) - case 0x99: // Rn = MRF + Rx * Ry (SUFR) - case 0xa0: // Rn = MRF + Rx * Ry (USI) - case 0xa8: // Rn = MRF + Rx * Ry (USF) - case 0xa9: // Rn = MRF + Rx * Ry (USFR) - case 0xb0: // Rn = MRF + Rx * Ry (SSI) - case 0xb8: // Rn = MRF + Rx * Ry (SSF) - case 0xb9: // Rn = MRF + Rx * Ry (SSFR) + case 0x80: // Rn = MRF + Rx * Ry (UUI) + case 0x88: // Rn = MRF + Rx * Ry (UUF) + case 0x89: // Rn = MRF + Rx * Ry (UUFR) + case 0x90: // Rn = MRF + Rx * Ry (SUI) + case 0x98: // Rn = MRF + Rx * Ry (SUF) + case 0x99: // Rn = MRF + Rx * Ry (SUFR) + case 0xa0: // Rn = MRF + Rx * Ry (USI) + case 0xa8: // Rn = MRF + Rx * Ry (USF) + case 0xa9: // Rn = MRF + Rx * Ry (USFR) + case 0xb0: // Rn = MRF + Rx * Ry (SSI) + case 0xb8: // Rn = MRF + Rx * Ry (SSF) + case 0xb9: // Rn = MRF + Rx * Ry (SSFR) // TODO: track MRF? REG_USED(desc, rx); REG_USED(desc, ry); @@ -1325,18 +1325,18 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0x82: // Rn = MRB + Rx * Ry (UUI) - case 0x8a: // Rn = MRB + Rx * Ry (UUF) - case 0x8b: // Rn = MRB + Rx * Ry (UUFR) - case 0x92: // Rn = MRB + Rx * Ry (SUI) - case 0x9a: // Rn = MRB + Rx * Ry (SUF) - case 0x9b: // Rn = MRB + Rx * Ry (SUFR) - case 0xa2: // Rn = MRB + Rx * Ry (USI) - case 0xaa: // Rn = MRB + Rx * Ry (USF) - case 0xab: // Rn = MRB + Rx * Ry (USFR) - case 0xb2: // Rn = MRB + Rx * Ry (SSI) - case 0xba: // Rn = MRB + Rx * Ry (SSF) - case 0xbb: // Rn = MRB + Rx * Ry (SSFR) + case 0x82: // Rn = MRB + Rx * Ry (UUI) + case 0x8a: // Rn = MRB + Rx * Ry (UUF) + case 0x8b: // Rn = MRB + Rx * Ry (UUFR) + case 0x92: // Rn = MRB + Rx * Ry (SUI) + case 0x9a: // Rn = MRB + Rx * Ry (SUF) + case 0x9b: // Rn = MRB + Rx * Ry (SUFR) + case 0xa2: // Rn = MRB + Rx * Ry (USI) + case 0xaa: // Rn = MRB + Rx * Ry (USF) + case 0xab: // Rn = MRB + Rx * Ry (USFR) + case 0xb2: // Rn = MRB + Rx * Ry (SSI) + case 0xba: // Rn = MRB + Rx * Ry (SSF) + case 0xbb: // Rn = MRB + Rx * Ry (SSFR) // TODO: track MRB? REG_USED(desc, rx); REG_USED(desc, ry); @@ -1344,55 +1344,55 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0x84: // MRF = MRF + Rx * Ry (UUI) - case 0x8c: // MRF = MRF + Rx * Ry (UUF) - case 0x8d: // MRF = MRF + Rx * Ry (UUFR) - case 0x94: // MRF = MRF + Rx * Ry (SUI) - case 0x9c: // MRF = MRF + Rx * Ry (SUF) - case 0x9d: // MRF = MRF + Rx * Ry (SUFR) - case 0xa4: // MRF = MRF + Rx * Ry (USI) - case 0xac: // MRF = MRF + Rx * Ry (USF) - case 0xad: // MRF = MRF + Rx * Ry (USFR) - case 0xb4: // MRF = MRF + Rx * Ry (SSI) - case 0xbc: // MRF = MRF + Rx * Ry (SSF) - case 0xbd: // MRF = MRF + Rx * Ry (SSFR) + case 0x84: // MRF = MRF + Rx * Ry (UUI) + case 0x8c: // MRF = MRF + Rx * Ry (UUF) + case 0x8d: // MRF = MRF + Rx * Ry (UUFR) + case 0x94: // MRF = MRF + Rx * Ry (SUI) + case 0x9c: // MRF = MRF + Rx * Ry (SUF) + case 0x9d: // MRF = MRF + Rx * Ry (SUFR) + case 0xa4: // MRF = MRF + Rx * Ry (USI) + case 0xac: // MRF = MRF + Rx * Ry (USF) + case 0xad: // MRF = MRF + Rx * Ry (USFR) + case 0xb4: // MRF = MRF + Rx * Ry (SSI) + case 0xbc: // MRF = MRF + Rx * Ry (SSF) + case 0xbd: // MRF = MRF + Rx * Ry (SSFR) // TODO: track MRF? REG_USED(desc, rx); REG_USED(desc, ry); MULT_FLAGS_MODIFIED(desc); break; - case 0x86: // MRB = MRB + Rx * Ry (UUI) - case 0x8e: // MRB = MRB + Rx * Ry (UUF) - case 0x8f: // MRB = MRB + Rx * Ry (UUFR) - case 0x96: // MRB = MRB + Rx * Ry (SUI) - case 0x9e: // MRB = MRB + Rx * Ry (SUF) - case 0x9f: // MRB = MRB + Rx * Ry (SUFR) - case 0xa6: // MRB = MRB + Rx * Ry (USI) - case 0xae: // MRB = MRB + Rx * Ry (USF) - case 0xaf: // MRB = MRB + Rx * Ry (USFR) - case 0xb6: // MRB = MRB + Rx * Ry (SSI) - case 0xbe: // MRB = MRB + Rx * Ry (SSF) - case 0xbf: // MRB = MRB + Rx * Ry (SSFR) + case 0x86: // MRB = MRB + Rx * Ry (UUI) + case 0x8e: // MRB = MRB + Rx * Ry (UUF) + case 0x8f: // MRB = MRB + Rx * Ry (UUFR) + case 0x96: // MRB = MRB + Rx * Ry (SUI) + case 0x9e: // MRB = MRB + Rx * Ry (SUF) + case 0x9f: // MRB = MRB + Rx * Ry (SUFR) + case 0xa6: // MRB = MRB + Rx * Ry (USI) + case 0xae: // MRB = MRB + Rx * Ry (USF) + case 0xaf: // MRB = MRB + Rx * Ry (USFR) + case 0xb6: // MRB = MRB + Rx * Ry (SSI) + case 0xbe: // MRB = MRB + Rx * Ry (SSF) + case 0xbf: // MRB = MRB + Rx * Ry (SSFR) break; // TODO: track MRB? REG_USED(desc, rx); REG_USED(desc, ry); MULT_FLAGS_MODIFIED(desc); break; - - case 0xc0: // Rn = MRF - Rx * Ry (UUI) - case 0xc8: // Rn = MRF - Rx * Ry (UUF) - case 0xc9: // Rn = MRF - Rx * Ry (UUFR) - case 0xd0: // Rn = MRF - Rx * Ry (SUI) - case 0xd8: // Rn = MRF - Rx * Ry (SUF) - case 0xd9: // Rn = MRF - Rx * Ry (SUFR) - case 0xe0: // Rn = MRF - Rx * Ry (USI) - case 0xe8: // Rn = MRF - Rx * Ry (USF) - case 0xe9: // Rn = MRF - Rx * Ry (USFR) - case 0xf0: // Rn = MRF - Rx * Ry (SSI) - case 0xf8: // Rn = MRF - Rx * Ry (SSF) - case 0xf9: // Rn = MRF - Rx * Ry (SSFR) + + case 0xc0: // Rn = MRF - Rx * Ry (UUI) + case 0xc8: // Rn = MRF - Rx * Ry (UUF) + case 0xc9: // Rn = MRF - Rx * Ry (UUFR) + case 0xd0: // Rn = MRF - Rx * Ry (SUI) + case 0xd8: // Rn = MRF - Rx * Ry (SUF) + case 0xd9: // Rn = MRF - Rx * Ry (SUFR) + case 0xe0: // Rn = MRF - Rx * Ry (USI) + case 0xe8: // Rn = MRF - Rx * Ry (USF) + case 0xe9: // Rn = MRF - Rx * Ry (USFR) + case 0xf0: // Rn = MRF - Rx * Ry (SSI) + case 0xf8: // Rn = MRF - Rx * Ry (SSF) + case 0xf9: // Rn = MRF - Rx * Ry (SSFR) // TODO: track MRF? REG_USED(desc, rx); REG_USED(desc, ry); @@ -1400,18 +1400,18 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0xc2: // Rn = MRB - Rx * Ry (UUI) - case 0xca: // Rn = MRB - Rx * Ry (UUF) - case 0xcb: // Rn = MRB - Rx * Ry (UUFR) - case 0xd2: // Rn = MRB - Rx * Ry (SUI) - case 0xda: // Rn = MRB - Rx * Ry (SUF) - case 0xdb: // Rn = MRB - Rx * Ry (SUFR) - case 0xe2: // Rn = MRB - Rx * Ry (USI) - case 0xea: // Rn = MRB - Rx * Ry (USF) - case 0xeb: // Rn = MRB - Rx * Ry (USFR) - case 0xf2: // Rn = MRB - Rx * Ry (SSI) - case 0xfa: // Rn = MRB - Rx * Ry (SSF) - case 0xfb: // Rn = MRB - Rx * Ry (SSFR) + case 0xc2: // Rn = MRB - Rx * Ry (UUI) + case 0xca: // Rn = MRB - Rx * Ry (UUF) + case 0xcb: // Rn = MRB - Rx * Ry (UUFR) + case 0xd2: // Rn = MRB - Rx * Ry (SUI) + case 0xda: // Rn = MRB - Rx * Ry (SUF) + case 0xdb: // Rn = MRB - Rx * Ry (SUFR) + case 0xe2: // Rn = MRB - Rx * Ry (USI) + case 0xea: // Rn = MRB - Rx * Ry (USF) + case 0xeb: // Rn = MRB - Rx * Ry (USFR) + case 0xf2: // Rn = MRB - Rx * Ry (SSI) + case 0xfa: // Rn = MRB - Rx * Ry (SSF) + case 0xfb: // Rn = MRB - Rx * Ry (SSFR) // TODO: track MRB? REG_USED(desc, rx); REG_USED(desc, ry); @@ -1419,106 +1419,106 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) MULT_FLAGS_MODIFIED(desc); break; - case 0xc4: // MRF = MRF - Rx * Ry (UUI) - case 0xcc: // MRF = MRF - Rx * Ry (UUF) - case 0xcd: // MRF = MRF - Rx * Ry (UUFR) - case 0xd4: // MRF = MRF - Rx * Ry (SUI) - case 0xdc: // MRF = MRF - Rx * Ry (SUF) - case 0xdd: // MRF = MRF - Rx * Ry (SUFR) - case 0xe4: // MRF = MRF - Rx * Ry (USI) - case 0xec: // MRF = MRF - Rx * Ry (USF) - case 0xed: // MRF = MRF - Rx * Ry (USFR) - case 0xf4: // MRF = MRF - Rx * Ry (SSI) - case 0xfc: // MRF = MRF - Rx * Ry (SSF) - case 0xfd: // MRF = MRF - Rx * Ry (SSFR) + case 0xc4: // MRF = MRF - Rx * Ry (UUI) + case 0xcc: // MRF = MRF - Rx * Ry (UUF) + case 0xcd: // MRF = MRF - Rx * Ry (UUFR) + case 0xd4: // MRF = MRF - Rx * Ry (SUI) + case 0xdc: // MRF = MRF - Rx * Ry (SUF) + case 0xdd: // MRF = MRF - Rx * Ry (SUFR) + case 0xe4: // MRF = MRF - Rx * Ry (USI) + case 0xec: // MRF = MRF - Rx * Ry (USF) + case 0xed: // MRF = MRF - Rx * Ry (USFR) + case 0xf4: // MRF = MRF - Rx * Ry (SSI) + case 0xfc: // MRF = MRF - Rx * Ry (SSF) + case 0xfd: // MRF = MRF - Rx * Ry (SSFR) // TODO: track MRF? REG_USED(desc, rx); REG_USED(desc, ry); MULT_FLAGS_MODIFIED(desc); break; - case 0xc6: // MRB = MRB - Rx * Ry (UUI) - case 0xce: // MRB = MRB - Rx * Ry (UUF) - case 0xcf: // MRB = MRB - Rx * Ry (UUFR) - case 0xd6: // MRB = MRB - Rx * Ry (SUI) - case 0xde: // MRB = MRB - Rx * Ry (SUF) - case 0xdf: // MRB = MRB - Rx * Ry (SUFR) - case 0xe6: // MRB = MRB - Rx * Ry (USI) - case 0xee: // MRB = MRB - Rx * Ry (USF) - case 0xef: // MRB = MRB - Rx * Ry (USFR) - case 0xf6: // MRB = MRB - Rx * Ry (SSI) - case 0xfe: // MRB = MRB - Rx * Ry (SSF) - case 0xff: // MRB = MRB - Rx * Ry (SSFR) + case 0xc6: // MRB = MRB - Rx * Ry (UUI) + case 0xce: // MRB = MRB - Rx * Ry (UUF) + case 0xcf: // MRB = MRB - Rx * Ry (UUFR) + case 0xd6: // MRB = MRB - Rx * Ry (SUI) + case 0xde: // MRB = MRB - Rx * Ry (SUF) + case 0xdf: // MRB = MRB - Rx * Ry (SUFR) + case 0xe6: // MRB = MRB - Rx * Ry (USI) + case 0xee: // MRB = MRB - Rx * Ry (USF) + case 0xef: // MRB = MRB - Rx * Ry (USFR) + case 0xf6: // MRB = MRB - Rx * Ry (SSI) + case 0xfe: // MRB = MRB - Rx * Ry (SSF) + case 0xff: // MRB = MRB - Rx * Ry (SSFR) // TODO: track MRB? REG_USED(desc, rx); REG_USED(desc, ry); MULT_FLAGS_MODIFIED(desc); break; - - case 0x00: // Rn = SAT MRF (UI) - case 0x01: // Rn = SAT MRF (SI) - case 0x08: // Rn = SAT MRF (UF) - case 0x09: // Rn = SAT MRF (SF) + + case 0x00: // Rn = SAT MRF (UI) + case 0x01: // Rn = SAT MRF (SI) + case 0x08: // Rn = SAT MRF (UF) + case 0x09: // Rn = SAT MRF (SF) // TODO: track MRF? REG_MODIFIED(desc, rn); MULT_FLAGS_MODIFIED(desc); break; - case 0x02: // Rn = SAT MRB (UI) - case 0x03: // Rn = SAT MRB (SI) - case 0x0a: // Rn = SAT MRB (UF) - case 0x0b: // Rn = SAT MRB (SF) + case 0x02: // Rn = SAT MRB (UI) + case 0x03: // Rn = SAT MRB (SI) + case 0x0a: // Rn = SAT MRB (UF) + case 0x0b: // Rn = SAT MRB (SF) // TODO: track MRB? REG_MODIFIED(desc, rn); MULT_FLAGS_MODIFIED(desc); break; - case 0x04: // MRF = SAT MRF (UI) - case 0x05: // MRF = SAT MRF (SI) - case 0x0c: // MRF = SAT MRF (UF) - case 0x0d: // MRF = SAT MRF (SF) + case 0x04: // MRF = SAT MRF (UI) + case 0x05: // MRF = SAT MRF (SI) + case 0x0c: // MRF = SAT MRF (UF) + case 0x0d: // MRF = SAT MRF (SF) // TODO: track MRF? MULT_FLAGS_MODIFIED(desc); break; - case 0x06: // MRB = SAT MRB (UI) - case 0x07: // MRB = SAT MRB (SI) - case 0x0e: // MRB = SAT MRB (UF) - case 0x0f: // MRB = SAT MRB (SF) + case 0x06: // MRB = SAT MRB (UI) + case 0x07: // MRB = SAT MRB (SI) + case 0x0e: // MRB = SAT MRB (UF) + case 0x0f: // MRB = SAT MRB (SF) // TODO: track MRB? MULT_FLAGS_MODIFIED(desc); break; - case 0x18: // Rn = RND MRF (U) - case 0x19: // Rn = RND MRF (S) + case 0x18: // Rn = RND MRF (U) + case 0x19: // Rn = RND MRF (S) REG_MODIFIED(desc, rn); MULT_FLAGS_MODIFIED(desc); break; - case 0x1a: // Rn = RND MRB (U) - case 0x1b: // Rn = RND MRB (S) + case 0x1a: // Rn = RND MRB (U) + case 0x1b: // Rn = RND MRB (S) REG_MODIFIED(desc, rn); MULT_FLAGS_MODIFIED(desc); break; - case 0x1c: // MRF = RND MRF (U) - case 0x1d: // MRF = RND MRF (S) + case 0x1c: // MRF = RND MRF (U) + case 0x1d: // MRF = RND MRF (S) MULT_FLAGS_MODIFIED(desc); break; - case 0x1e: // MRB = RND MRB (U) - case 0x1f: // MRB = RND MRB (S) + case 0x1e: // MRB = RND MRB (U) + case 0x1f: // MRB = RND MRB (S) MULT_FLAGS_MODIFIED(desc); break; - case 0x14: // MRF = 0 + case 0x14: // MRF = 0 MULT_FLAGS_MODIFIED(desc); break; - case 0x16: // MRB = 0 + case 0x16: // MRB = 0 MULT_FLAGS_MODIFIED(desc); break; - case 0x30: // Fn = Fx * Fy + case 0x30: // Fn = Fx * Fy REG_USED(desc, rx); REG_USED(desc, ry); REG_MODIFIED(desc, rn); @@ -1531,48 +1531,48 @@ bool sharc_frontend::describe_compute(opcode_desc &desc, UINT64 opcode) break; } - case 2: // shifter operations + case 2: // shifter operations { switch (operation) { - case 0x00: // Rn = LSHIFT Rx BY Ry | <data8> - case 0x04: // Rn = ASHIFT Rx BY Ry | <data8> - case 0x08: // Rn = ROT Rx BY Ry | <data8> - case 0xc4: // Rn = BCLR Rx BY Ry | <data8> - case 0xc0: // Rn = BSET Rx BY Ry | <data8> - case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6> - case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE) - case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6> - case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE) + case 0x00: // Rn = LSHIFT Rx BY Ry | <data8> + case 0x04: // Rn = ASHIFT Rx BY Ry | <data8> + case 0x08: // Rn = ROT Rx BY Ry | <data8> + case 0xc4: // Rn = BCLR Rx BY Ry | <data8> + case 0xc0: // Rn = BSET Rx BY Ry | <data8> + case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6> + case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE) + case 0x40: // Rn = FEXT Rx BY Ry | <bit6>:<len6> + case 0x48: // Rn = FEXT Rx BY Ry | <bit6>:<len6> (SE) REG_USED(desc, rx); REG_USED(desc, ry); REG_MODIFIED(desc, rn); SHIFT_FLAGS_MODIFIED(desc); break; - case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8> - case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8> - case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> - case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE) + case 0x20: // Rn = Rn OR LSHIFT Rx BY Ry | <data8> + case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8> + case 0x64: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> + case 0x6c: // Rn = Rn OR FDEP Rx BY Ry | <bit6>:<len6> (SE) REG_USED(desc, rx); REG_USED(desc, ry); REG_USED(desc, rn); REG_MODIFIED(desc, rn); SHIFT_FLAGS_MODIFIED(desc); break; - - case 0xcc: // BTST Rx BY Ry | <data8> + + case 0xcc: // BTST Rx BY Ry | <data8> REG_USED(desc, rx); REG_USED(desc, ry); SHIFT_FLAGS_MODIFIED(desc); break; - - case 0x80: // Rn = EXP Rx - case 0x84: // Rn = EXP Rx (EX) - case 0x88: // Rn = LEFTZ Rx - case 0x8c: // Rn = LEFTO Rx - case 0x90: // Rn = FPACK Fx - case 0x94: // Fn = FUNPACK Rx + + case 0x80: // Rn = EXP Rx + case 0x84: // Rn = EXP Rx (EX) + case 0x88: // Rn = LEFTZ Rx + case 0x8c: // Rn = LEFTO Rx + case 0x90: // Rn = FPACK Fx + case 0x94: // Fn = FUNPACK Rx REG_USED(desc, rx); REG_MODIFIED(desc, rn); SHIFT_FLAGS_MODIFIED(desc); @@ -1657,34 +1657,34 @@ bool sharc_frontend::describe_ureg_access(opcode_desc &desc, int reg, UREG_ACCES PM_B_MODIFIED(desc, reg & 7); break; - case 0x60: // FADDR + case 0x60: // FADDR break; - case 0x61: // DADDR + case 0x61: // DADDR break; - case 0x63: // PC + case 0x63: // PC break; - case 0x64: // PCSTK + case 0x64: // PCSTK break; - case 0x65: // PCSTKP + case 0x65: // PCSTKP break; - case 0x66: // LADDR + case 0x66: // LADDR break; - case 0x67: // CURLCNTR + case 0x67: // CURLCNTR break; - case 0x68: // LCNTR + case 0x68: // LCNTR break; - case 0x70: // USTAT1 + case 0x70: // USTAT1 break; - case 0x71: // USTAT2 + case 0x71: // USTAT2 break; - case 0x79: // IRPTL + case 0x79: // IRPTL break; - case 0x7a: // MODE1 + case 0x7a: // MODE1 break; - case 0x7b: // MODE2 + case 0x7b: // MODE2 break; - case 0x7c: // ASTAT + case 0x7c: // ASTAT if (access == UREG_READ) { AZ_USED(desc); @@ -1713,17 +1713,17 @@ bool sharc_frontend::describe_ureg_access(opcode_desc &desc, int reg, UREG_ACCES } break; - case 0x7d: // IMASK + case 0x7d: // IMASK break; - case 0x7e: // STKY + case 0x7e: // STKY break; - case 0x7f: // IMASKP + case 0x7f: // IMASKP break; - case 0xdb: // PX + case 0xdb: // PX break; - case 0xdc: // PX1 + case 0xdc: // PX1 break; - case 0xdd: // PX2 + case 0xdd: // PX2 break; default: @@ -1738,31 +1738,31 @@ bool sharc_frontend::describe_shiftop_imm(opcode_desc &desc, int shiftop, int rn { switch (shiftop) { - case 0x00: // LSHIFT Rx BY <data8> - case 0x01: // ASHIFT Rx BY <data8> - case 0x02: // ROT Rx BY <data8> - case 0x10: // FEXT Rx BY <data8> - case 0x11: // FDEP Rx BY <data8> - case 0x12: // FEXT Rx BY <bit6>:<len6> (SE) - case 0x13: // FDEP Rx BY <bit6>:<len6> (SE) - case 0x30: // BSET Rx BY <data8> - case 0x31: // BCLR Rx By <data8> - case 0x32: // BTGL Rx BY <data8> + case 0x00: // LSHIFT Rx BY <data8> + case 0x01: // ASHIFT Rx BY <data8> + case 0x02: // ROT Rx BY <data8> + case 0x10: // FEXT Rx BY <data8> + case 0x11: // FDEP Rx BY <data8> + case 0x12: // FEXT Rx BY <bit6>:<len6> (SE) + case 0x13: // FDEP Rx BY <bit6>:<len6> (SE) + case 0x30: // BSET Rx BY <data8> + case 0x31: // BCLR Rx By <data8> + case 0x32: // BTGL Rx BY <data8> REG_USED(desc, rx); REG_MODIFIED(desc, rn); SHIFT_FLAGS_MODIFIED(desc); break; - case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8> - case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> - case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE) + case 0x08: // Rn = Rn OR LSHIFT Rx BY <data8> + case 0x19: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> + case 0x1b: // Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE) REG_USED(desc, rx); REG_USED(desc, rn); REG_MODIFIED(desc, rn); SHIFT_FLAGS_MODIFIED(desc); break; - case 0x33: // BTST Rx BY <data8> + case 0x33: // BTST Rx BY <data8> REG_USED(desc, rx); SHIFT_FLAGS_MODIFIED(desc); break; @@ -1800,4 +1800,4 @@ void sharc_frontend::describe_if_condition(opcode_desc &desc, int condition) case 0x18: SZ_USED(desc); break; /* NOT SZ */ case 0x1d: BTF_USED(desc); break; /* NOT TF */ } -}
\ No newline at end of file +} diff --git a/src/devices/cpu/sparc/mb86901.cpp b/src/devices/cpu/sparc/mb86901.cpp index 0a1bf03938b..2bf8e1ba284 100644 --- a/src/devices/cpu/sparc/mb86901.cpp +++ b/src/devices/cpu/sparc/mb86901.cpp @@ -10,8 +10,8 @@ // // To-Do: // - Ops: FBFcc, LDF, STF -// - Test: SPARCv8 ops are untested -// - Test: Traps are untested +// - Test: SPARCv8 ops are untested +// - Test: Traps are untested // - FPU support // - Coprocessor support // @@ -155,17 +155,17 @@ void mb86901_device::device_start() #endif // register our state for the debugger - state_add(STATE_GENPC, "GENPC", m_pc).noshow(); - state_add(STATE_GENFLAGS, "GENFLAGS", m_psr).callimport().callexport().formatstr("%6s").noshow(); - state_add(SPARC_PC, "PC", m_pc).formatstr("%08X"); - state_add(SPARC_NPC, "nPC", m_npc).formatstr("%08X"); - state_add(SPARC_PSR, "PSR", m_psr).formatstr("%08X"); - state_add(SPARC_WIM, "WIM", m_wim).formatstr("%08X"); - state_add(SPARC_TBR, "TBR", m_tbr).formatstr("%08X"); - state_add(SPARC_Y, "Y", m_y).formatstr("%08X"); - state_add(SPARC_ANNUL, "ANNUL", m_annul).formatstr("%01d"); - state_add(SPARC_ICC, "icc", m_icc).formatstr("%4s"); - state_add(SPARC_CWP, "CWP", m_cwp).formatstr("%2d"); + state_add(STATE_GENPC, "GENPC", m_pc).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_psr).callimport().callexport().formatstr("%6s").noshow(); + state_add(SPARC_PC, "PC", m_pc).formatstr("%08X"); + state_add(SPARC_NPC, "nPC", m_npc).formatstr("%08X"); + state_add(SPARC_PSR, "PSR", m_psr).formatstr("%08X"); + state_add(SPARC_WIM, "WIM", m_wim).formatstr("%08X"); + state_add(SPARC_TBR, "TBR", m_tbr).formatstr("%08X"); + state_add(SPARC_Y, "Y", m_y).formatstr("%08X"); + state_add(SPARC_ANNUL, "ANNUL", m_annul).formatstr("%01d"); + state_add(SPARC_ICC, "icc", m_icc).formatstr("%4s"); + state_add(SPARC_CWP, "CWP", m_cwp).formatstr("%2d"); char regname[3] = "g0"; for (int i = 0; i < 8; i++) { @@ -192,12 +192,12 @@ void mb86901_device::device_start() state_add(SPARC_I0 + i, regname, m_dbgregs[16+i]).formatstr("%08X"); } - state_add(SPARC_EC, "EC", m_ec).formatstr("%1d"); - state_add(SPARC_EF, "EF", m_ef).formatstr("%1d"); - state_add(SPARC_ET, "ET", m_et).formatstr("%1d"); - state_add(SPARC_PIL, "PIL", m_pil).formatstr("%2d"); - state_add(SPARC_S, "S", m_s).formatstr("%1d"); - state_add(SPARC_PS, "PS", m_ps).formatstr("%1d"); + state_add(SPARC_EC, "EC", m_ec).formatstr("%1d"); + state_add(SPARC_EF, "EF", m_ef).formatstr("%1d"); + state_add(SPARC_ET, "ET", m_et).formatstr("%1d"); + state_add(SPARC_PIL, "PIL", m_pil).formatstr("%2d"); + state_add(SPARC_S, "S", m_s).formatstr("%1d"); + state_add(SPARC_PS, "PS", m_ps).formatstr("%1d"); char rname[5]; for (int i = 0; i < 120; i++) @@ -415,13 +415,13 @@ void mb86901_device::state_string_export(const device_state_entry &entry, std::s case SPARC_ICC: str = string_format("%c%c%c%c", ICC_N_SET ? 'n' : ' ', ICC_Z_SET ? 'z' : ' ', ICC_V_SET ? 'v' : ' ', ICC_C_SET ? 'c' : ' '); break; - case SPARC_O0: case SPARC_O1: case SPARC_O2: case SPARC_O3: case SPARC_O4: case SPARC_O5: case SPARC_O6: case SPARC_O7: + case SPARC_O0: case SPARC_O1: case SPARC_O2: case SPARC_O3: case SPARC_O4: case SPARC_O5: case SPARC_O6: case SPARC_O7: str = string_format("%08X", m_dbgregs[entry.index() - SPARC_O0]); break; - case SPARC_L0: case SPARC_L1: case SPARC_L2: case SPARC_L3: case SPARC_L4: case SPARC_L5: case SPARC_L6: case SPARC_L7: + case SPARC_L0: case SPARC_L1: case SPARC_L2: case SPARC_L3: case SPARC_L4: case SPARC_L5: case SPARC_L6: case SPARC_L7: str = string_format("%08X", m_dbgregs[8 + (entry.index() - SPARC_L0)]); break; - case SPARC_I0: case SPARC_I1: case SPARC_I2: case SPARC_I3: case SPARC_I4: case SPARC_I5: case SPARC_I6: case SPARC_I7: + case SPARC_I0: case SPARC_I1: case SPARC_I2: case SPARC_I3: case SPARC_I4: case SPARC_I5: case SPARC_I6: case SPARC_I7: str = string_format("%08X", m_dbgregs[16 + (entry.index() - SPARC_I0)]); break; } @@ -524,21 +524,21 @@ void mb86901_device::execute_add(UINT32 op) operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); if (ADD or ADDcc) then - result <- r[rs1] + operand2; + result <- r[rs1] + operand2; else if (ADDX or ADDXcc) then - result <= r[rs1] + operand2 + C; + result <= r[rs1] + operand2 + C; next; if (rd != 0) then - r[rd] <- result; + r[rd] <- result; if (ADDcc or ADDXcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or - ((not r[rs1]<31>) and (not operand2<31>) and result<31>); - C <- (r[rs1]<31> and operand2<31>) or - ((not result<31>) and (r[rs1]<31> or operand2<31>)) + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or + ((not r[rs1]<31>) and (not operand2<31>) and result<31>); + C <- (r[rs1]<31> and operand2<31>) or + ((not result<31>) and (r[rs1]<31> or operand2<31>)) ); */ UINT32 operand2 = USEIMM ? SIMM13 : RS2REG; @@ -559,9 +559,9 @@ void mb86901_device::execute_add(UINT32 op) PSR |= (BIT31(result)) ? PSR_N_MASK : 0; PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= ((BIT31(RS1REG) && BIT31(operand2) && !BIT31(result)) || - (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; + (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; PSR |= ((BIT31(RS1REG) && BIT31(operand2)) || - (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; } } @@ -586,16 +586,16 @@ void mb86901_device::execute_taddcc(UINT32 op) next; if (TADDccTV and (temp_V = 1)) then ( - trap <- 1; - tag_overflow <- 1 + trap <- 1; + tag_overflow <- 1 ) else ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- temp_V; - C <- (r[rs1]<31> and operand2<31>) or - ((not result<31>) and (r[rs1]<31> or operand2<31>)); - if (rd != 0) then - r[rd] <- result; + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- temp_V; + C <- (r[rs1]<31> and operand2<31>) or + ((not result<31>) and (r[rs1]<31> or operand2<31>)); + if (rd != 0) then + r[rd] <- result; ); */ UINT32 operand2 = USEIMM ? SIMM13 : RS2REG; @@ -603,8 +603,8 @@ void mb86901_device::execute_taddcc(UINT32 op) UINT32 result = RS1REG + operand2; bool temp_v = (BIT31(RS1REG) && BIT31(operand2) && !BIT31(result)) || - (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result)) || - ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false; + (!BIT31(RS1REG) && !BIT31(operand2) && BIT31(result)) || + ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false; if (TADDCCTV && temp_v) { @@ -618,7 +618,7 @@ void mb86901_device::execute_taddcc(UINT32 op) PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= temp_v ? PSR_V_MASK : 0; PSR |= ((BIT31(RS1REG) && BIT31(operand2)) || - (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (!BIT31(result) && (BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; if (RD != 0) RDREG = result; @@ -638,21 +638,21 @@ void mb86901_device::execute_sub(UINT32 op) operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); if (SUB or SUBcc) then - result <- r[rs1] - operand2; + result <- r[rs1] - operand2; else if (SUBX or SUBXcc) then - result <= r[rs1] - operand2 - C; + result <= r[rs1] - operand2 - C; next; if (rd != 0) then - r[rd] <- result; + r[rd] <- result; if (SUBcc or SUBXcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or - ((not r[rs1]<31>) and operand2<31> and result<31>); - C <- ((not r[rs1]<31>) and operand2<31>) or - (result<31> and ((not r[rs1]<31>) or operand2<31>)) + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or + ((not r[rs1]<31>) and operand2<31> and result<31>); + C <- ((not r[rs1]<31>) and operand2<31>) or + (result<31> and ((not r[rs1]<31>) or operand2<31>)) ); */ UINT32 operand2 = USEIMM ? SIMM13 : RS2REG; @@ -672,9 +672,9 @@ void mb86901_device::execute_sub(UINT32 op) PSR |= (BIT31(result)) ? PSR_N_MASK : 0; PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= ((BIT31(RS1REG) && !BIT31(operand2) && !BIT31(result)) || - (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; + (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; PSR |= ((!BIT31(RS1REG) && BIT31(operand2)) || - (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; } } @@ -699,16 +699,16 @@ void mb86901_device::execute_tsubcc(UINT32 op) next; if (TSUBccTV and (temp_V = 1)) then ( - trap <- 1; - tag_overflow <- 1 + trap <- 1; + tag_overflow <- 1 ) else ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- temp_V; - C <- ((not r[rs1]<31>) and operand2<31>) or - (result<31> and ((not r[rs1]<31>) or operand2<31>)); - if (rd != 0) then - r[rd] <- result; + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- temp_V; + C <- ((not r[rs1]<31>) and operand2<31>) or + (result<31> and ((not r[rs1]<31>) or operand2<31>)); + if (rd != 0) then + r[rd] <- result; ); */ @@ -717,8 +717,8 @@ void mb86901_device::execute_tsubcc(UINT32 op) UINT32 result = RS1REG - operand2; bool temp_v = (BIT31(RS1REG) && !BIT31(operand2) && !BIT31(result)) || - (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result)) || - ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false; + (!BIT31(RS1REG) && BIT31(operand2) && BIT31(result)) || + ((RS1REG & 3) != 0 || (RS1REG & 3) != 0) ? true : false; if (TSUBCCTV && temp_v) { @@ -732,7 +732,7 @@ void mb86901_device::execute_tsubcc(UINT32 op) PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= temp_v ? PSR_V_MASK : 0; PSR |= ((!BIT31(RS1REG) && BIT31(operand2)) || - (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (BIT31(result) && (!BIT31(RS1REG) || BIT31(operand2)))) ? PSR_C_MASK : 0; if (RD != 0) RDREG = result; @@ -762,10 +762,10 @@ void mb86901_device::execute_logical(UINT32 op) if (rd != 0) then r[rd] <- result; if (ANDcccc or ANDNcc or ORcc or ORNcc or XORcc or XNORcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- 0 - C <- 0 + N <- result<31>; + Z <- if (result = 0) then 1 else 0; + V <- 0 + C <- 0 ); */ @@ -824,11 +824,11 @@ void mb86901_device::execute_shift(UINT32 op) shift_count := if (i = 0) then r[rs2]<4:0> else shcnt; if (SLL and (rd != 0) ) then - r[rd] <- shift_left_logical(r[rs1], shift_count) + r[rd] <- shift_left_logical(r[rs1], shift_count) else if (SRL and (rd != 0) ) then - r[rd] <- shift_right_logical(r[rs1], shift_count) + r[rd] <- shift_right_logical(r[rs1], shift_count) else if (SRA and (rd != 0) ) then - r[rd] <- shift_right_arithmetic(r[rs1], shift_count) + r[rd] <- shift_right_arithmetic(r[rs1], shift_count) */ UINT32 shift_count = USEIMM ? (SIMM13 & 31) : (RS2REG & 31); @@ -852,8 +852,8 @@ void mb86901_device::execute_mulscc(UINT32 op) operand1 := (N xor V) [] (r[rs1]<31:1>); operand2 := ( - if (Y<0> = 0) then 0 - else if (i = 0) then r[rs2] else sign_extend(simm13) + if (Y<0> = 0) then 0 + else if (i = 0) then r[rs2] else sign_extend(simm13) ); result <- operand1 + operand2; @@ -861,7 +861,7 @@ void mb86901_device::execute_mulscc(UINT32 op) next; if (rd != 0) then ( - r[rd] <- result; + r[rd] <- result; ) N <- result<31>; Z <- if (result = 0) then 1 else 0; @@ -884,9 +884,9 @@ void mb86901_device::execute_mulscc(UINT32 op) PSR |= (BIT31(result)) ? PSR_N_MASK : 0; PSR |= (result == 0) ? PSR_Z_MASK : 0; PSR |= ((BIT31(operand1) && BIT31(operand2) && !BIT31(result)) || - (!BIT31(operand1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; + (!BIT31(operand1) && !BIT31(operand2) && BIT31(result))) ? PSR_V_MASK : 0; PSR |= ((BIT31(operand1) && BIT31(operand2)) || - (!BIT31(result) && (BIT31(operand1) || BIT31(operand2)))) ? PSR_C_MASK : 0; + (!BIT31(result) && (BIT31(operand1) || BIT31(operand2)))) ? PSR_C_MASK : 0; } @@ -901,17 +901,17 @@ void mb86901_device::execute_rdsr(UINT32 op) if ((RDPSR or RDWIM or RDBTR or (RDASR and (privileged_ASR(rs1) = 1))) and (S = 0)) then ( - trap <- 1; - privileged_instruction <- 1; + trap <- 1; + privileged_instruction <- 1; else if (illegal_instruction_ASR(rs1) = 1) then ( - trap <- 1; - illegal_instruction <- 1 + trap <- 1; + illegal_instruction <- 1 else if (rd != 0) then ( - if (RDY) then r[rd] <- Y - else if (RDASR) then r[rd] <- ASR[rs1] - else if (RDPSR) then r[rd] <- PSR - else if (RDWIM) then r[rd] <- WIM - else if (RDTBR) then r[rd] <- TBR; + if (RDY) then r[rd] <- Y + else if (RDASR) then r[rd] <- ASR[rs1] + else if (RDPSR) then r[rd] <- PSR + else if (RDWIM) then r[rd] <- WIM + else if (RDTBR) then r[rd] <- TBR; ); */ @@ -957,41 +957,41 @@ void mb86901_device::execute_wrsr(UINT32 op) result := r[rs1] xor operand2; if (WRY) then ( - Y'''' <- result + Y'''' <- result ) else if (WRASR) then ( - if ( (privileged_ASR(rd) = 1) and (S = 0) ) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (illegal_instruction_ASR(rd) = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - ASR[rd]'''' <- result - ) + if ( (privileged_ASR(rd) = 1) and (S = 0) ) then ( + trap <- 1; + privileged_instruction <- 1 + ) else if (illegal_instruction_ASR(rd) = 1) then ( + trap <- 1; + illegal_instruction <- 1 + ) else ( + ASR[rd]'''' <- result + ) ) else if (WRPSR) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (result<4:0> >= NWINDOWS) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - PSR'''' <- result - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else if (result<4:0> >= NWINDOWS) then ( + trap <- 1; + illegal_instruction <- 1 + ) else ( + PSR'''' <- result + ) ) else if (WRWIM) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else ( - WIM'''' <- result - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else ( + WIM'''' <- result + ) ) else if (WRBTR) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else ( - WIM'''' <- result - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else ( + WIM'''' <- result + ) ); */ UINT32 operand2 = USEIMM ? SIMM13 : RS2REG; @@ -1009,8 +1009,8 @@ void mb86901_device::execute_wrsr(UINT32 op) m_trap = 1; m_privileged_instruction = 1; } - else if (m_illegal_instruction_asr[RD]) - { + else if (m_illegal_instruction_asr[RD]) + { m_trap = 1; m_illegal_instruction = 1; } @@ -1043,8 +1043,8 @@ void mb86901_device::execute_wrsr(UINT32 op) m_trap = 1; m_privileged_instruction = 1; } - else - { + else + { WIM = result & 0x7f; } } @@ -1055,8 +1055,8 @@ void mb86901_device::execute_wrsr(UINT32 op) m_trap = 1; m_privileged_instruction = 1; } - else - { + else + { TBR = result & 0xfffff000; } } @@ -1076,33 +1076,33 @@ void mb86901_device::execute_rett(UINT32 op) address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); next; if (ET = 1) then ( - trap <- 1; - if (S = 0) then privileged_instruction <- 1 - else if (S != 0) then illegal_instruction <- 1 + trap <- 1; + if (S = 0) then privileged_instruction <- 1 + else if (S != 0) then illegal_instruction <- 1 ) else if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - tt <- 00000011; { trap type for privileged_instruction } - execute_mode <- 0; - error_mode = 1 + trap <- 1; + privileged_instruction <- 1 + tt <- 00000011; { trap type for privileged_instruction } + execute_mode <- 0; + error_mode = 1 ) else if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_underflow <- 1; - tt <- 00000110; { trap type for window_underflow } - execute_mode = 0; - error_mode = 1 + trap <- 1; + window_underflow <- 1; + tt <- 00000110; { trap type for window_underflow } + execute_mode = 0; + error_mode = 1 ) else if (address<1:0> != 0) then ( - trap = 1; - mem_address_not_aligned = 1; - tt = 7; { trap type for mem_address_not_aligned } - execute_mode = 0; - error_mode = 1 + trap = 1; + mem_address_not_aligned = 1; + tt = 7; { trap type for mem_address_not_aligned } + execute_mode = 0; + error_mode = 1 ) else ( - ET <- 1; - PC <- nPC; - nPC <- address; - CWP <- new_cwp; - S <- PS + ET <- 1; + PC <- nPC; + nPC <- address; + CWP <- new_cwp; + S <- PS ) */ @@ -1166,29 +1166,29 @@ void mb86901_device::execute_saverestore(UINT32 op) operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); if (SAVE) then ( - new_cwp <- (CWP - 1) modulo NWINDOWS; - next; - if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_overflow <- 1 - ) else ( - result <- r[rs1] + operand2; { operands from old window } - CWP <- new_cwp - ) + new_cwp <- (CWP - 1) modulo NWINDOWS; + next; + if ((WIM and (1 << new_cwp)) != 0) then ( + trap <- 1; + window_overflow <- 1 + ) else ( + result <- r[rs1] + operand2; { operands from old window } + CWP <- new_cwp + ) ) else if (RESTORE) then ( - new_cwp <- (CWP + 1) modulo NWINDOWS; - next; - if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_overflow <- 1 - ) else ( - result <- r[rs1] + operand2; { operands from old window } - CWP <- new_cwp - ) + new_cwp <- (CWP + 1) modulo NWINDOWS; + next; + if ((WIM and (1 << new_cwp)) != 0) then ( + trap <- 1; + window_overflow <- 1 + ) else ( + result <- r[rs1] + operand2; { operands from old window } + CWP <- new_cwp + ) ); next; if ((trap = 0) and (rd != 0)) then - r[rd] <- result { destination in new window } + r[rd] <- result { destination in new window } */ UINT32 rs1 = RS1REG; @@ -1243,12 +1243,12 @@ void mb86901_device::execute_jmpl(UINT32 op) jump_address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); next; if (jump_address<1:0> != 0) then ( - trap <- 1; - mem_address_not_aligned <- 1 + trap <- 1; + mem_address_not_aligned <- 1 ) else ( - if (rd != 0) then r[rd] <- PC; - PC <- nPC; - nPC <- jump_address + if (rd != 0) then r[rd] <- PC; + PC <- nPC; + nPC <- jump_address ) */ @@ -1417,119 +1417,119 @@ void mb86901_device::execute_store(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 165, "Appendix C - ISP Descriptions - Store Instructions" (SPARCv8.pdf, pg. 162) if ( (S = 0) and (STDA or STA or STHA or STBA or STDFQ or STDCQ) ) then ( - trap <- 1; - privileged_instruction <- 1 + trap <- 1; + privileged_instruction <- 1 ) else if ((i = 1) and (STDA or STA or STHA or STBA)) then ( - trap <- 1; - illegal_instruction <- 1 + trap <- 1; + illegal_instruction <- 1 ); next; if (trap = 0) then ( - if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) - ) else if (STDA or STA or STHA or STBA) then ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ); - if ((STF or STDF or STFSR or STDFQ) and - ((EF = 0) or (bp_FPU_present = 0)) ) then ( - trap <- 1; - fp_disabled <- 1; - ); - if ((STC or STDC or STCSR or STDCQ) and - ((EC = 0) or (bp_CP_present = 0)) ) then ( - trap <- 1; - cp_disabled <- 1; - ) + if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then ( + address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); + addr_space <- (if (S = 0) then 10 else 11) + ) else if (STDA or STA or STHA or STBA) then ( + address <- r[rs1] + r[rs2]; + addr_space <- asi + ); + if ((STF or STDF or STFSR or STDFQ) and + ((EF = 0) or (bp_FPU_present = 0)) ) then ( + trap <- 1; + fp_disabled <- 1; + ); + if ((STC or STDC or STCSR or STDCQ) and + ((EC = 0) or (bp_CP_present = 0)) ) then ( + trap <- 1; + cp_disabled <- 1; + ) ); next; if (trap = 0) then ( - if ((STH or STHA) and (address<0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else ( - if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then ( - trap <- 1; - fp_exception <- 1; - ftt <- sequence_error; - ); - if (STDCQ and ((implementation has no coprocessor queue)) then ( - trap <- 1; - cp_exception <- 1; - { possibly additional implementation-dependent actions } - ); - if (STDF and (rd<0> != 0)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- invalid_fp_register; - ) - ) + if ((STH or STHA) and (address<0> != 0)) then ( + trap <- 1; + mem_address_not_aligned <- 1 + ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then ( + trap <- 1; + mem_address_not_aligned <- 1 + ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then ( + trap <- 1; + mem_address_not_aligned <- 1 + ) else ( + if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then ( + trap <- 1; + fp_exception <- 1; + ftt <- sequence_error; + ); + if (STDCQ and ((implementation has no coprocessor queue)) then ( + trap <- 1; + cp_exception <- 1; + { possibly additional implementation-dependent actions } + ); + if (STDF and (rd<0> != 0)) then ( + trap <- 1; + fp_exception <- 1; + ftt <- invalid_fp_register; + ) + ) ); next; if (trap = 0) then ( - if (STF) then ( byte_mask <- 1111; data0 <- f[rd] ) - else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] ) - else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] ) - else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STFSR) then ( - while ((FSR.qne = 1) and (trap = 0)) ( - // wait for pending floating-point instructions to complete - ) - next; - byte_mask <- 1111; data0 <- FSR - ) else if (STCSR) then ( - { implementation-dependent actions } - byte_mask <- 1111; data0 <- CSR - ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] ) - else if (STH or STHA) then ( - if (address<1:0> = 0) then ( - byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) ) - else if (address<1:0> = 2) then ( - byte_mask <- 0011; data0 <- r[rd] ) - ) else if (STB or STBA) then ( - if (address<1:0> = 0) then ( - byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) ) - ) else if (address<1:0> = 1) then ( - byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) ) - ) else if (address<1:0> = 2) then ( - byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) ) - ) else if (address<1:0> = 3) then ( - byte_mask <- 0001; data0 <- r[rd] ) - ) - ); + if (STF) then ( byte_mask <- 1111; data0 <- f[rd] ) + else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) + else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] ) + else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) + else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] ) + else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) + else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) + else if (STFSR) then ( + while ((FSR.qne = 1) and (trap = 0)) ( + // wait for pending floating-point instructions to complete + ) + next; + byte_mask <- 1111; data0 <- FSR + ) else if (STCSR) then ( + { implementation-dependent actions } + byte_mask <- 1111; data0 <- CSR + ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] ) + else if (STH or STHA) then ( + if (address<1:0> = 0) then ( + byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) ) + else if (address<1:0> = 2) then ( + byte_mask <- 0011; data0 <- r[rd] ) + ) else if (STB or STBA) then ( + if (address<1:0> = 0) then ( + byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) ) + ) else if (address<1:0> = 1) then ( + byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) ) + ) else if (address<1:0> = 2) then ( + byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) ) + ) else if (address<1:0> = 3) then ( + byte_mask <- 0001; data0 <- r[rd] ) + ) + ); ); next; if (trap = 0) then ( - MAE <- memory_write(addr_space, address, byte_mask, data1); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1 - ) + MAE <- memory_write(addr_space, address, byte_mask, data1); + next; + if (MAE = 1) then ( + trap <- 1; + data_access_exception <- 1 + ) ); if ((trap = 0) and (STD or STDA or STDF or STDC or STDFQ or STDCQ)) then ( - if (STD or STDA) then ( data1 <- r[rd or 00001] ) - else if (STDF) then ( data1 <- f[rd or 00001] ) - else if (STDC) then ( data1 <- implementation_dependent_value } - else if (STDFQ) then ( data1 <- implementation_dependent_value } - else if (STDCQ) then ( data1 <- implementation_dependent_value } - next; - MAE <- memory_write(addr_space, address + 4, 1111, data1); - next; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 - ) + if (STD or STDA) then ( data1 <- r[rd or 00001] ) + else if (STDF) then ( data1 <- f[rd or 00001] ) + else if (STDC) then ( data1 <- implementation_dependent_value } + else if (STDFQ) then ( data1 <- implementation_dependent_value } + else if (STDCQ) then ( data1 <- implementation_dependent_value } + next; + MAE <- memory_write(addr_space, address + 4, 1111, data1); + next; + if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } + trap <- 1; + data_access_exception <- 1 + ) ); */ @@ -1760,100 +1760,100 @@ void mb86901_device::execute_load(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 163, "Appendix C - ISP Descriptions - C.9. Instruction Defintions - Load Instructions" (SPARCv8.pdf, pg. 160) if (LDD or LD or LDSH or LDUH or LDSB or LDUB or LDDF or LDF or LDFSR or LDDC or LDC or LDCSR) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) + address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); + addr_space <- (if (S = 0) then 10 else 11) ) else if (LDDA or LDA or LDSHA or LDUHA or LDSBA or LDUBA) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (i = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else if (i = 1) then ( + trap <- 1; + illegal_instruction <- 1 + ) else ( + address <- r[rs1] + r[rs2]; + addr_space <- asi + ) ) next; if (trap = 0) then ( - if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then ( - trap <- 1; - fp_disabled <- 1 - ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then ( - trap <- 1; - cp_disabled <- 1 - ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or - ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or - ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if (LDDF and (rd<0> != 0)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- invalid_fpr_register - ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- sequence_error - ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then ( - trap <- 1; - cp_exception <- 1; - { possibly additional implementation-dependent actions } - ) + if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then ( + trap <- 1; + fp_disabled <- 1 + ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then ( + trap <- 1; + cp_disabled <- 1 + ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or + ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or + ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then ( + trap <- 1; + mem_address_not_aligned <- 1 + ) else if (LDDF and (rd<0> != 0)) then ( + trap <- 1; + fp_exception <- 1; + ftt <- invalid_fpr_register + ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then ( + trap <- 1; + fp_exception <- 1; + ftt <- sequence_error + ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then ( + trap <- 1; + cp_exception <- 1; + { possibly additional implementation-dependent actions } + ) ); next; if (trap = 0) then { - (data, MAE) <- memory_read(addr_space, address); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1; - ) else ( - if (LDSB or LDSBA or LDUB or LDUBA) then ( - if (address<1:0> = 0) then byte <- data<31:24> - else if (address<1:0> = 1) then byte <- data<23:16> - else if (address<1:0> = 2) then byte <- data<15: 8> - else if (address<1:0> = 3) then byte <- data< 7: 0> - next; - if (LDSB or LDSBA) then - word0 <- sign_extend_byte(byte) - else - word0 <- zero_extend_byte(byte) - ) else if (LDSH or LDSHA or LDUH or LDUHA) then ( - if (address<1:0> = 0) then halfword <- data<31:16> - else if (address<1:0> = 2) then halfword <- data<15: 0> - next; - if (LDSH or LDSHA) then - word0 <- sign_extend_halfword(halfword) - else - word0 <- zero_extend_halfword(halfword) - ) else - word0 <- data - ) + (data, MAE) <- memory_read(addr_space, address); + next; + if (MAE = 1) then ( + trap <- 1; + data_access_exception <- 1; + ) else ( + if (LDSB or LDSBA or LDUB or LDUBA) then ( + if (address<1:0> = 0) then byte <- data<31:24> + else if (address<1:0> = 1) then byte <- data<23:16> + else if (address<1:0> = 2) then byte <- data<15: 8> + else if (address<1:0> = 3) then byte <- data< 7: 0> + next; + if (LDSB or LDSBA) then + word0 <- sign_extend_byte(byte) + else + word0 <- zero_extend_byte(byte) + ) else if (LDSH or LDSHA or LDUH or LDUHA) then ( + if (address<1:0> = 0) then halfword <- data<31:16> + else if (address<1:0> = 2) then halfword <- data<15: 0> + next; + if (LDSH or LDSHA) then + word0 <- sign_extend_halfword(halfword) + else + word0 <- zero_extend_halfword(halfword) + ) else + word0 <- data + ) ); next; if (trap = 0) then ( - if ( (rd != 0) and (LD or LDA or LDSH or LDSHA - or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then - r[rd] <- word0 - else if (LDF) then f[rd] <- word0 - else if (LDC) then { implementation-dependent actions } - else if (LDFSR) then FSR <- word0 - else if (LDCSR) then CSR <- word0 - else if (LDD or LDDA) then r[rd and 11110] <- word0 - else if (LDDF) then f[rd and 11110] <- word0 - else if (LDDC) then { implementation-dependent actions } + if ( (rd != 0) and (LD or LDA or LDSH or LDSHA + or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then + r[rd] <- word0 + else if (LDF) then f[rd] <- word0 + else if (LDC) then { implementation-dependent actions } + else if (LDFSR) then FSR <- word0 + else if (LDCSR) then CSR <- word0 + else if (LDD or LDDA) then r[rd and 11110] <- word0 + else if (LDDF) then f[rd and 11110] <- word0 + else if (LDDC) then { implementation-dependent actions } ); next; if (((trap = 0) and (LDD or LDDA or LDDF or LDDC)) then ( - (word1, MAE) <- memory_read(addr_space, address + 4); - next; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 ) - else if (LDD or LDDA) then r[rd or 1] <- word1 - else if (LDDF) then f[rd or 1] <- word1 - else if (LDDC) then { implementation-dependent actions } + (word1, MAE) <- memory_read(addr_space, address + 4); + next; + if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } + trap <- 1; + data_access_exception <- 1 ) + else if (LDD or LDDA) then r[rd or 1] <- word1 + else if (LDDF) then f[rd or 1] <- word1 + else if (LDDC) then { implementation-dependent actions } ); */ @@ -2008,59 +2008,59 @@ void mb86901_device::execute_ldstub(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 169, "Appendix C - ISP Descriptions - Atomic Load-Store Unsigned Byte Instructions" (SPARCv8.pdf, pg. 166) if (LDSTUB) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) + address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); + addr_space <- (if (S = 0) then 10 else 11) } else if (LDSTUBA) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (i = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ) + if (S = 0) then ( + trap <- 1; + privileged_instruction <- 1 + ) else if (i = 1) then ( + trap <- 1; + illegal_instruction <- 1 + ) else ( + address <- r[rs1] + r[rs2]; + addr_space <- asi + ) ); next; if (trap = 0) then ( - while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then ( - { wait for lock(s) to be lifted } - { an implementation actually need only block when another LDSTUB or SWAP - is pending on the same byte in memory as the one addressed by this LDSTUB } - }; - next; - pb_block_ldst_byte <- 1; - next; - (data, MAE) <- memory_read(addr_space, address); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1 - ) + while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then ( + { wait for lock(s) to be lifted } + { an implementation actually need only block when another LDSTUB or SWAP + is pending on the same byte in memory as the one addressed by this LDSTUB } + }; + next; + pb_block_ldst_byte <- 1; + next; + (data, MAE) <- memory_read(addr_space, address); + next; + if (MAE = 1) then ( + trap <- 1; + data_access_exception <- 1 + ) ) next; if (trap = 0) then ( - if (address<1:0> = 0) then ( byte_mask <- 1000 ) - else if (address<1:0> = 1) then ( byte_mask <- 0100 ) - else if (address<1:0> = 2) then ( byte_mask <- 0010 ) - else if (address<1:0> = 3) then ( byte_mask <- 0001 ) - ; - next; - MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF); - next; - pb_block_ldst_byte <- 0; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 - ) else ( - if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>) - else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>) - else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>) - else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>) - next; - if (rd != 0) then r[rd] <- word - ) + if (address<1:0> = 0) then ( byte_mask <- 1000 ) + else if (address<1:0> = 1) then ( byte_mask <- 0100 ) + else if (address<1:0> = 2) then ( byte_mask <- 0010 ) + else if (address<1:0> = 3) then ( byte_mask <- 0001 ) + ; + next; + MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF); + next; + pb_block_ldst_byte <- 0; + if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } + trap <- 1; + data_access_exception <- 1 + ) else ( + if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>) + else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>) + else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>) + else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>) + next; + if (rd != 0) then r[rd] <- word + ) ); */ @@ -2258,16 +2258,16 @@ bool mb86901_device::evaluate_condition(UINT32 op) bool v = ICC_V_SET; bool c = ICC_C_SET; - switch(COND & 7) // COND & 8 - { // 0 8 - case 0: take = false; break; // bn ba - case 1: take = z; break; // bz bne - case 2: take = z | (n ^ z); break; // ble bg - case 3: take = n ^ v; break; // bl bge - case 4: take = c | z; break; // bleu bgu - case 5: take = c; break; // bcs bcc - case 6: take = n; break; // bneg bpos - case 7: take = v; break; // bvs bvc + switch(COND & 7) // COND & 8 + { // 0 8 + case 0: take = false; break; // bn ba + case 1: take = z; break; // bz bne + case 2: take = z | (n ^ z); break; // ble bg + case 3: take = n ^ v; break; // bl bge + case 4: take = c | z; break; // bleu bgu + case 5: take = c; break; // bcs bcc + case 6: take = n; break; // bneg bpos + case 7: take = v; break; // bvs bvc } if (COND & 8) @@ -2286,32 +2286,32 @@ void mb86901_device::execute_bicc(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 178, "Appendix C - ISP Descriptions - Branch on Integer Condition Instructions" (SPARCv8.pdf, pg. 175) eval_icc := ( - if (BNE) then (if (Z = 0) then 1 else 0); - if (BE) then (if (Z = 1) then 1 else 0); - if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0); - if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); - if (BGE) then (if ((N xor V) = 0) then 1 else 0); - if (BL) then (if ((N xor V) = 1) then 1 else 0); - if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); - if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); - if (BCC) then (if (C = 0) then 1 else 0); - if (BCS) then (if (C = 1) then 1 else 0); - if (BPOS) then (if (N = 0) then 1 else 0); - if (BNEG) then (if (N = 1) then 1 else 0); - if (BVC) then (if (V = 0) then 1 else 0); - if (BVS) then (if (V = 1) then 1 else 0); - if (BA) then 1; - if (BN) then 0; + if (BNE) then (if (Z = 0) then 1 else 0); + if (BE) then (if (Z = 1) then 1 else 0); + if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0); + if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); + if (BGE) then (if ((N xor V) = 0) then 1 else 0); + if (BL) then (if ((N xor V) = 1) then 1 else 0); + if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); + if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); + if (BCC) then (if (C = 0) then 1 else 0); + if (BCS) then (if (C = 1) then 1 else 0); + if (BPOS) then (if (N = 0) then 1 else 0); + if (BNEG) then (if (N = 1) then 1 else 0); + if (BVC) then (if (V = 0) then 1 else 0); + if (BVS) then (if (V = 1) then 1 else 0); + if (BA) then 1; + if (BN) then 0; ) PC <- nPC; if (eval_icc = 1) then ( - nPC <- PC + sign_extend(disp22[]00); - if (BA and (a = 1)) then - annul <- 1 { only for annulling Branch-Always } + nPC <- PC + sign_extend(disp22[]00); + if (BA and (a = 1)) then + annul <- 1 { only for annulling Branch-Always } ) else ( - nPC <- nPC + 4; - if (a = 1) then - annul <- 1 { only for annulling branches other than BA } + nPC <- nPC + 4; + if (a = 1) then + annul <- 1 { only for annulling branches other than BA } ) */ @@ -2342,35 +2342,35 @@ void mb86901_device::execute_ticc(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 182, "Appendix C - ISP Descriptions - Trap on Integer Condition Instructions" (SPARCv8.pdf, pg. 179) trap_eval_icc := ( - if (TNE) then (if (Z = 0) then 1 else 0); - if (TE) then (if (Z = 1) then 1 else 0); - if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0); - if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); - if (TGE) then (if ((N xor V) = 0) then 1 else 0); - if (TL) then (if ((N xor V) = 1) then 1 else 0); - if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); - if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); - if (TCC) then (if (C = 0) then 1 else 0); - if (TCS) then (if (C = 1) then 1 else 0); - if (TPOS) then (if (N = 0) then 1 else 0); - if (TNEG) then (if (N = 1) then 1 else 0); - if (TVC) then (if (V = 0) then 1 else 0); - if (TVS) then (if (V = 1) then 1 else 0); - if (TA) then 1; - if (TN) then 0; + if (TNE) then (if (Z = 0) then 1 else 0); + if (TE) then (if (Z = 1) then 1 else 0); + if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0); + if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); + if (TGE) then (if ((N xor V) = 0) then 1 else 0); + if (TL) then (if ((N xor V) = 1) then 1 else 0); + if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); + if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); + if (TCC) then (if (C = 0) then 1 else 0); + if (TCS) then (if (C = 1) then 1 else 0); + if (TPOS) then (if (N = 0) then 1 else 0); + if (TNEG) then (if (N = 1) then 1 else 0); + if (TVC) then (if (V = 0) then 1 else 0); + if (TVS) then (if (V = 1) then 1 else 0); + if (TA) then 1; + if (TN) then 0; ) trap_number := r[rs1] + (if (i = 0) then r[rs2] else sign_extend(software_trap#)); if (Ticc) then ( - if (trap_eval_icc = 1) then ( - trap <- 1; - trap_instruction <- 1; - ticc_trap_type <- trap_number<6:0> - ) else ( - PC <- nPC; - nPC <- nPC + 4; - ) + if (trap_eval_icc = 1) then ( + trap <- 1; + trap_instruction <- 1; + ticc_trap_type <- trap_number<6:0> + ) else ( + PC <- nPC; + nPC <- nPC + 4; + ) ); */ @@ -2489,76 +2489,76 @@ void mb86901_device::execute_trap() next; if (error_mode = 0) then ( - ET <- 0; - PS <- S; - CWP <- (CWP - 1) modulo NWINDOWS; - - next; - if (annul = 0) then ( - r[17] <- PC; - r[18] <- nPC; - ) else { annul != 0) } ( - r[17] <- nPC; - r[18] <- nPC + 4; - annul <- 0; - ) - - next; - S <- 1; - if (reset_trap = 0) then ( - PC <- TBR; - nPC <- TBR + 4; - ) else { reset_trap = 1 } ( - PC <- 0; - nPC <- 4; - reset_trap <- 0; - ) + ET <- 0; + PS <- S; + CWP <- (CWP - 1) modulo NWINDOWS; + + next; + if (annul = 0) then ( + r[17] <- PC; + r[18] <- nPC; + ) else { annul != 0) } ( + r[17] <- nPC; + r[18] <- nPC + 4; + annul <- 0; + ) + + next; + S <- 1; + if (reset_trap = 0) then ( + PC <- TBR; + nPC <- TBR + 4; + ) else { reset_trap = 1 } ( + PC <- 0; + nPC <- 4; + reset_trap <- 0; + ) ); select_trap := ( - if (reset_trap = 1) then { ignore ET, and leave tt unchanged } - else if (ET = 0) then ( - execute_mode <- 0; - error_mode <- 1 ) - else if (data_store_error = 1) then tt <- 00101011 - else if (instruction_access_error = 1) then tt <- 00100001 - else if (r_register_access_error = 1) then tt <- 00100000 - else if (instruction_access_exception = 1) then tt <- 00000001 - else if (privileged_instruction = 1) then tt <- 00000011 - else if (illegal_instruction = 1) then tt <- 00000010 - else if (fp_disabled = 1) then tt <- 00000100 - else if (cp_disabled = 1) then tt <- 00100100 - else if (unimplemented_FLUSH = 1) then tt <- 00100101 - else if (window_overflow = 1) then tt <- 00000101 - else if (window_underflow = 1) then tt <- 00000110 - else if (mem_address_not_aligned = 1) then tt <- 00000111 - else if (fp_exception = 1) then tt <- 00001000 - else if (cp_exception = 1) then tt <- 00101000 - else if (data_access_error = 1) then tt <- 00101001 - else if (data_access_exception = 1) then tt <- 00001001 - else if (tag_overflow = 1) then tt <- 00001010 - else if (division_by_zero = 1) then tt <- 00101010 - else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type - else if (interrupt_level > 0) then tt <- 0001[]interrupt_level; - - next; - - trap <- 0; - instruction_access_exception <- 0; - illegal_instruction <- 0; - privileged_instruction <- 0; - fp_disabled <- 0; - cp_disabled <- 0; - window_overflow <- 0; - window_underflow <- 0; - mem_address_not_aligned <- 0; - fp_exception <- 0; - cp_exception <- 0; - data_access_exception <- 0; - tag_overflow <- 0; - division_by_zero <- 0; - trap_instruction <- 0; - interrupt_level <- 0; + if (reset_trap = 1) then { ignore ET, and leave tt unchanged } + else if (ET = 0) then ( + execute_mode <- 0; + error_mode <- 1 ) + else if (data_store_error = 1) then tt <- 00101011 + else if (instruction_access_error = 1) then tt <- 00100001 + else if (r_register_access_error = 1) then tt <- 00100000 + else if (instruction_access_exception = 1) then tt <- 00000001 + else if (privileged_instruction = 1) then tt <- 00000011 + else if (illegal_instruction = 1) then tt <- 00000010 + else if (fp_disabled = 1) then tt <- 00000100 + else if (cp_disabled = 1) then tt <- 00100100 + else if (unimplemented_FLUSH = 1) then tt <- 00100101 + else if (window_overflow = 1) then tt <- 00000101 + else if (window_underflow = 1) then tt <- 00000110 + else if (mem_address_not_aligned = 1) then tt <- 00000111 + else if (fp_exception = 1) then tt <- 00001000 + else if (cp_exception = 1) then tt <- 00101000 + else if (data_access_error = 1) then tt <- 00101001 + else if (data_access_exception = 1) then tt <- 00001001 + else if (tag_overflow = 1) then tt <- 00001010 + else if (division_by_zero = 1) then tt <- 00101010 + else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type + else if (interrupt_level > 0) then tt <- 0001[]interrupt_level; + + next; + + trap <- 0; + instruction_access_exception <- 0; + illegal_instruction <- 0; + privileged_instruction <- 0; + fp_disabled <- 0; + cp_disabled <- 0; + window_overflow <- 0; + window_underflow <- 0; + mem_address_not_aligned <- 0; + fp_exception <- 0; + cp_exception <- 0; + data_access_exception <- 0; + tag_overflow <- 0; + division_by_zero <- 0; + trap_instruction <- 0; + interrupt_level <- 0; ); */ @@ -2615,7 +2615,7 @@ void mb86901_device::complete_instruction_execution(UINT32 op) { switch (OP) { - case OP_TYPE0: // Bicc, SETHI, FBfcc + case OP_TYPE0: // Bicc, SETHI, FBfcc switch (OP2) { case OP2_UNIMP: // unimp @@ -2624,7 +2624,7 @@ void mb86901_device::complete_instruction_execution(UINT32 op) case OP2_BICC: // branch on integer condition codes execute_bicc(op); break; - case OP2_SETHI: // sethi + case OP2_SETHI: // sethi SET_RDREG(IMM22); break; case OP2_FBFCC: // branch on floating-point condition codes @@ -2674,26 +2674,26 @@ void mb86901_device::dispatch_instruction(UINT32 op) /* The SPARC Instruction Manual: Version 8, page 159, "Appendix C - ISP Descriptions - C.6. Instruction Dispatch" (SPARCv8.pdf, pg. 156) illegal_IU_instr :- ( - if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction } - or + if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction } + or ( ((op=11) or (op=10)) and (op3=unassigned) ) - then 1 else 0 + then 1 else 0 if (illegal_IU_instr = 1) then ( - trap <- 1 - illegal_instruction <- 1 + trap <- 1 + illegal_instruction <- 1 ); if ((FPop1 or FPop2 or FBfcc) and ((EF = 0) or (bp_FPU_present = 0))) then ( - trap <- 1; - fp_disabled <- 1 + trap <- 1; + fp_disabled <- 1 ); if (CPop1 or CPop2 or CBccc) and ((EC = 0) or (bp_CP_present = 0))) then ( - trap <- 1; - cp_disabled <- 1 + trap <- 1; + cp_disabled <- 1 ); next; if (trap = 0) then ( - { code for specific instruction, defined below } + { code for specific instruction, defined below } ); */ bool illegal_IU_instr = (OP == 0 && OP2 == 0) || ((OP == 3 && !m_ldst_op3_assigned[OP3]) || (OP == 2 && !m_alu_op3_assigned[OP3])); @@ -2742,12 +2742,12 @@ void mb86901_device::execute_step() /* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153) if (bp_reset_in = 1) then ( - execute_mode <- 0; - reset_mode <- 1; - break { out of while (execute_mode = 1) loop } + execute_mode <- 0; + reset_mode <- 1; + break { out of while (execute_mode = 1) loop } ) else if ((ET = 1) and ((bp_IRL = 15) or (bp_IRL > PIL))) then ( - trap <- 1; - interrupt_level <- bp_IRL + trap <- 1; + interrupt_level <- bp_IRL ); next; @@ -2755,40 +2755,40 @@ void mb86901_device::execute_step() if (execute_mode = 1) then ( { execute_trap may have set execute_mode to 0 } - { the following code emulates the delayed nature of the write-state-register instructions. - PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR''''; - ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR''''; - TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR''''; - WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM''''; - Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y''''; - next; - - addr_space := (if (S = 0) then 8 else 9); - (instruction, MAE) <- memory_read(addr_space, PC); - next; - - if ( (MAE = 1) and (annul = 0) ) then ( - trap <- 1; - instruction_access_exception <- 1 - ) else ( - if (annul = 0) then ( - dispatch_instruction ; { See Section C.6 } - next; - if (FPop1 or FPop2) then ( - complete_fp_execution { See Section C.7 } - ) - next; - if ( (trap = 0) and - not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then ( - PC <- nPC; - nPC <- nPC + 4 - ) - ) else { annul != 0 } ( - annul <- 0; - PC <- nPC; - nPC <- nPC + 4 - ) - ) + { the following code emulates the delayed nature of the write-state-register instructions. + PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR''''; + ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR''''; + TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR''''; + WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM''''; + Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y''''; + next; + + addr_space := (if (S = 0) then 8 else 9); + (instruction, MAE) <- memory_read(addr_space, PC); + next; + + if ( (MAE = 1) and (annul = 0) ) then ( + trap <- 1; + instruction_access_exception <- 1 + ) else ( + if (annul = 0) then ( + dispatch_instruction ; { See Section C.6 } + next; + if (FPop1 or FPop2) then ( + complete_fp_execution { See Section C.7 } + ) + next; + if ( (trap = 0) and + not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then ( + PC <- nPC; + nPC <- nPC + 4 + ) + ) else { annul != 0 } ( + annul <- 0; + PC <- nPC; + nPC <- nPC + 4 + ) + ) ) */ if (m_bp_reset_in) @@ -2898,7 +2898,7 @@ void mb86901_device::execute_step() printf("Opcode at %08x: %04x, handler is at %08x // add 32-bit word (%08x) from handler table to result (%08x + %08x = %08x)\n", REG(5), opcode, handler_offset, value, REG(4), value, REG(4) + value); } else if (opcode == 0x003f || opcode == 0x0066 || opcode == 0x0099 || opcode == 0x0121 || opcode == 0x0136 || opcode == 0x014f || opcode == 0x0155 || opcode == 0x01c7 || opcode == 0x01cd || - opcode == 0x0217 || opcode == 0x0289 || opcode == 0x0296 || opcode == 0x029d || opcode == 0x02f2 || opcode == 0x0334 || opcode == 0x0381 || opcode == 0x3d38) + opcode == 0x0217 || opcode == 0x0289 || opcode == 0x0296 || opcode == 0x029d || opcode == 0x02f2 || opcode == 0x0334 || opcode == 0x0381 || opcode == 0x3d38) { switch(opcode) { @@ -3093,7 +3093,6 @@ void mb86901_device::execute_step() } else { - m_annul = 0; PC = nPC; nPC = nPC + 4; @@ -3112,12 +3111,12 @@ void mb86901_device::reset_step() /* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153) while (reset_mode = 1) ( - if (bp_reset_in = 0) then ( - reset_mode <- 0; - execute_mode <- 1; - trap <- 1; - reset_trap <- 1; - ) + if (bp_reset_in = 0) then ( + reset_mode <- 0; + execute_mode <- 1; + trap <- 1; + reset_trap <- 1; + ) ); */ @@ -3140,11 +3139,11 @@ void mb86901_device::error_step() /* The SPARC Instruction Manual: Version 8, page 157, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 154) while (error_mode = 1) ( - if (bp_reset_in = 1) then ( - error_mode <- 0; - reset_mode <- 1; - pb_error <- 0 - ) + if (bp_reset_in = 1) then ( + error_mode <- 0; + reset_mode <- 1; + pb_error <- 0 + ) ); */ @@ -3193,9 +3192,9 @@ void mb86901_device::execute_run() { for (int i = 0; i < 8; i++) { - m_dbgregs[i] = *m_regs[8 + i]; - m_dbgregs[8 + i] = *m_regs[16 + i]; - m_dbgregs[16 + i] = *m_regs[24 + i]; + m_dbgregs[i] = *m_regs[8 + i]; + m_dbgregs[8 + i] = *m_regs[16 + i]; + m_dbgregs[16 + i] = *m_regs[24 + i]; } } --m_icount; diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h index da2d0bc7c82..1acc2263854 100644 --- a/src/devices/cpu/sparc/sparc.h +++ b/src/devices/cpu/sparc/sparc.h @@ -11,36 +11,36 @@ #include "sparcdasm.h" -#define SPARCV8 (0) - -#define SPARC_NO_TRAP 256 -#define SPARC_RESET 0 -#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1 -#define SPARC_ILLEGAL_INSTRUCTION 2 -#define SPARC_PRIVILEGED_INSTRUCTION 3 -#define SPARC_FP_DISABLED 4 -#define SPARC_WINDOW_OVERFLOW 5 -#define SPARC_WINDOW_UNDERFLOW 6 -#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7 -#define SPARC_FLOATING_POINT_EXCEPTION 8 -#define SPARC_DATA_ACCESS_EXCEPTION 9 -#define SPARC_TAG_OVERFLOW 10 -#define SPARC_INT1 17 -#define SPARC_INT2 18 -#define SPARC_INT3 19 -#define SPARC_INT4 20 -#define SPARC_INT5 21 -#define SPARC_INT6 22 -#define SPARC_INT7 23 -#define SPARC_INT8 24 -#define SPARC_INT9 25 -#define SPARC_INT10 26 -#define SPARC_INT11 27 -#define SPARC_INT12 28 -#define SPARC_INT13 29 -#define SPARC_INT14 30 -#define SPARC_INT15 31 -#define SPARC_TRAP_INSTRUCTION 128 +#define SPARCV8 (0) + +#define SPARC_NO_TRAP 256 +#define SPARC_RESET 0 +#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1 +#define SPARC_ILLEGAL_INSTRUCTION 2 +#define SPARC_PRIVILEGED_INSTRUCTION 3 +#define SPARC_FP_DISABLED 4 +#define SPARC_WINDOW_OVERFLOW 5 +#define SPARC_WINDOW_UNDERFLOW 6 +#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7 +#define SPARC_FLOATING_POINT_EXCEPTION 8 +#define SPARC_DATA_ACCESS_EXCEPTION 9 +#define SPARC_TAG_OVERFLOW 10 +#define SPARC_INT1 17 +#define SPARC_INT2 18 +#define SPARC_INT3 19 +#define SPARC_INT4 20 +#define SPARC_INT5 21 +#define SPARC_INT6 22 +#define SPARC_INT7 23 +#define SPARC_INT8 24 +#define SPARC_INT9 25 +#define SPARC_INT10 26 +#define SPARC_INT11 27 +#define SPARC_INT12 28 +#define SPARC_INT13 29 +#define SPARC_INT14 30 +#define SPARC_INT15 31 +#define SPARC_TRAP_INSTRUCTION 128 #define SPARC_FPU_SEQUENCE_ERROR // TODO: when there are more SPARC CPUs, move setter to a base class @@ -200,16 +200,16 @@ protected: UINT8 m_cp_sequence_err; // fields separated out from PSR (Processor State Register) - UINT8 m_impl; // implementation (always 0 in MB86901) - UINT8 m_ver; // version (always 0 in MB86901) - UINT8 m_icc; // integer condition codes - bool m_ec; // enable coprocessor - bool m_ef; // enable FPU - UINT8 m_pil; // processor interrupt level - bool m_s; // supervisor mode - bool m_ps; // prior S state - bool m_et; // enable traps - UINT8 m_cwp; // current window pointer + UINT8 m_impl; // implementation (always 0 in MB86901) + UINT8 m_ver; // version (always 0 in MB86901) + UINT8 m_icc; // integer condition codes + bool m_ec; // enable coprocessor + bool m_ef; // enable FPU + UINT8 m_pil; // processor interrupt level + bool m_s; // supervisor mode + bool m_ps; // prior S state + bool m_et; // enable traps + UINT8 m_cwp; // current window pointer bool m_alu_op3_assigned[64]; bool m_ldst_op3_assigned[64]; @@ -259,10 +259,10 @@ enum SPARC_ICC, SPARC_CWP, - SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7, - SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7, - SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7, - SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7, + SPARC_G0, SPARC_G1, SPARC_G2, SPARC_G3, SPARC_G4, SPARC_G5, SPARC_G6, SPARC_G7, + SPARC_O0, SPARC_O1, SPARC_O2, SPARC_O3, SPARC_O4, SPARC_O5, SPARC_O6, SPARC_O7, + SPARC_L0, SPARC_L1, SPARC_L2, SPARC_L3, SPARC_L4, SPARC_L5, SPARC_L6, SPARC_L7, + SPARC_I0, SPARC_I1, SPARC_I2, SPARC_I3, SPARC_I4, SPARC_I5, SPARC_I6, SPARC_I7, SPARC_EC, SPARC_EF, @@ -271,13 +271,13 @@ enum SPARC_S, SPARC_PS, - SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15, - SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31, - SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47, - SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63, - SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79, - SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95, - SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111 + SPARC_R0, SPARC_R1, SPARC_R2, SPARC_R3, SPARC_R4, SPARC_R5, SPARC_R6, SPARC_R7, SPARC_R8, SPARC_R9, SPARC_R10, SPARC_R11, SPARC_R12, SPARC_R13, SPARC_R14, SPARC_R15, + SPARC_R16, SPARC_R17, SPARC_R18, SPARC_R19, SPARC_R20, SPARC_R21, SPARC_R22, SPARC_R23, SPARC_R24, SPARC_R25, SPARC_R26, SPARC_R27, SPARC_R28, SPARC_R29, SPARC_R30, SPARC_R31, + SPARC_R32, SPARC_R33, SPARC_R34, SPARC_R35, SPARC_R36, SPARC_R37, SPARC_R38, SPARC_R39, SPARC_R40, SPARC_R41, SPARC_R42, SPARC_R43, SPARC_R44, SPARC_R45, SPARC_R46, SPARC_R47, + SPARC_R48, SPARC_R49, SPARC_R50, SPARC_R51, SPARC_R52, SPARC_R53, SPARC_R54, SPARC_R55, SPARC_R56, SPARC_R57, SPARC_R58, SPARC_R59, SPARC_R60, SPARC_R61, SPARC_R62, SPARC_R63, + SPARC_R64, SPARC_R65, SPARC_R66, SPARC_R67, SPARC_R68, SPARC_R69, SPARC_R70, SPARC_R71, SPARC_R72, SPARC_R73, SPARC_R74, SPARC_R75, SPARC_R76, SPARC_R77, SPARC_R78, SPARC_R79, + SPARC_R80, SPARC_R81, SPARC_R82, SPARC_R83, SPARC_R84, SPARC_R85, SPARC_R86, SPARC_R87, SPARC_R88, SPARC_R89, SPARC_R90, SPARC_R91, SPARC_R92, SPARC_R93, SPARC_R94, SPARC_R95, + SPARC_R96, SPARC_R97, SPARC_R98, SPARC_R99, SPARC_R100, SPARC_R101, SPARC_R102, SPARC_R103, SPARC_R104, SPARC_R105, SPARC_R106, SPARC_R107, SPARC_R108, SPARC_R109, SPARC_R110, SPARC_R111 }; #endif /* __SPARC_H__ */ diff --git a/src/devices/cpu/sparc/sparcdefs.h b/src/devices/cpu/sparc/sparcdefs.h index 7fab760e06b..c59282ffa85 100644 --- a/src/devices/cpu/sparc/sparcdefs.h +++ b/src/devices/cpu/sparc/sparcdefs.h @@ -12,375 +12,375 @@ #ifndef __MB86901_DEFS_H__ #define __MB86901_DEFS_H__ -#define PSR_CWP_MASK 0x0000001f -#define PSR_ET_SHIFT 5 -#define PSR_ET_MASK 0x00000020 -#define PSR_PS_SHIFT 6 -#define PSR_PS_MASK 0x00000040 -#define PSR_S_SHIFT 7 -#define PSR_S_MASK 0x00000080 -#define PSR_PIL_SHIFT 8 -#define PSR_PIL_MASK 0x00000f00 -#define PSR_EF_SHIFT 12 -#define PSR_EF_MASK 0x00001000 -#define PSR_EC_SHIFT 13 -#define PSR_EC_MASK 0x00002000 -#define PSR_ICC_SHIFT 20 -#define PSR_RES_MASK 0x000fc000 -#define PSR_ICC_MASK 0x00f00000 -#define PSR_N_MASK 0x00800000 -#define PSR_Z_MASK 0x00400000 -#define PSR_V_MASK 0x00200000 -#define PSR_C_MASK 0x00100000 -#define PSR_VER_SHIFT 24 -#define PSR_VER_MASK 0x0f000000 -#define PSR_VER 0 -#define PSR_IMPL_SHIFT 28 -#define PSR_IMPL_MASK 0xf0000000 -#define PSR_IMPL 0 -#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK) - -#define ICC_N_SET (m_psr & PSR_N_MASK) -#define ICC_N (ICC_N_SET ? 1 : 0) -#define ICC_N_CLEAR (!ICC_N_SET) -#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0) -#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0) - -#define ICC_Z_SET (m_psr & PSR_Z_MASK) -#define ICC_Z (ICC_Z_SET ? 1 : 0) -#define ICC_Z_CLEAR (!ICC_Z_SET) -#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0) -#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0) - -#define ICC_V_SET (m_psr & PSR_V_MASK) -#define ICC_V (ICC_V_SET ? 1 : 0) -#define ICC_V_CLEAR (!ICC_V_SET) -#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0) -#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0) - -#define ICC_C_SET (m_psr & PSR_C_MASK) -#define ICC_C (ICC_C_SET ? 1 : 0) -#define ICC_C_CLEAR (!ICC_C_SET) -#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0) -#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0) - -#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0) - -#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0) - -#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0) -#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0) -#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0) - -#define CWP m_cwp -#define S m_s -#define PS m_ps - -#define IS_SUPERVISOR (m_psr & PSR_S_MASK) -#define IS_USER (!IS_SUPERVISOR) - -#define TRAPS_ENABLED (m_psr & PSR_ET_MASK) -#define TRAPS_DISABLED (!TRAPS_ENABLED) - -#define PSR m_psr -#define WIM m_wim -#define TBR m_tbr - -#define OP (op >> 30) // gangnam style -#define OP2 ((op >> 22) & 7) -#define OP3 ((op >> 19) & 63) -#define OPF ((op >> 5) & 0x1ff) -#define OPC ((op >> 5) & 0x1ff) -#define OPFLOW ((op >> 5) & 0x3f) - -#define DISP30 (INT32(op << 2)) -#define DISP22 (INT32(op << 10) >> 8) -#define DISP19 (INT32(op << 13) >> 11) -#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14) -#define IMM22 (op << 10) +#define PSR_CWP_MASK 0x0000001f +#define PSR_ET_SHIFT 5 +#define PSR_ET_MASK 0x00000020 +#define PSR_PS_SHIFT 6 +#define PSR_PS_MASK 0x00000040 +#define PSR_S_SHIFT 7 +#define PSR_S_MASK 0x00000080 +#define PSR_PIL_SHIFT 8 +#define PSR_PIL_MASK 0x00000f00 +#define PSR_EF_SHIFT 12 +#define PSR_EF_MASK 0x00001000 +#define PSR_EC_SHIFT 13 +#define PSR_EC_MASK 0x00002000 +#define PSR_ICC_SHIFT 20 +#define PSR_RES_MASK 0x000fc000 +#define PSR_ICC_MASK 0x00f00000 +#define PSR_N_MASK 0x00800000 +#define PSR_Z_MASK 0x00400000 +#define PSR_V_MASK 0x00200000 +#define PSR_C_MASK 0x00100000 +#define PSR_VER_SHIFT 24 +#define PSR_VER_MASK 0x0f000000 +#define PSR_VER 0 +#define PSR_IMPL_SHIFT 28 +#define PSR_IMPL_MASK 0xf0000000 +#define PSR_IMPL 0 +#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK) + +#define ICC_N_SET (m_psr & PSR_N_MASK) +#define ICC_N (ICC_N_SET ? 1 : 0) +#define ICC_N_CLEAR (!ICC_N_SET) +#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0) +#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0) + +#define ICC_Z_SET (m_psr & PSR_Z_MASK) +#define ICC_Z (ICC_Z_SET ? 1 : 0) +#define ICC_Z_CLEAR (!ICC_Z_SET) +#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0) +#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0) + +#define ICC_V_SET (m_psr & PSR_V_MASK) +#define ICC_V (ICC_V_SET ? 1 : 0) +#define ICC_V_CLEAR (!ICC_V_SET) +#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0) +#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0) + +#define ICC_C_SET (m_psr & PSR_C_MASK) +#define ICC_C (ICC_C_SET ? 1 : 0) +#define ICC_C_CLEAR (!ICC_C_SET) +#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0) +#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0) + +#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0) + +#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0) + +#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0) +#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0) +#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0) + +#define CWP m_cwp +#define S m_s +#define PS m_ps + +#define IS_SUPERVISOR (m_psr & PSR_S_MASK) +#define IS_USER (!IS_SUPERVISOR) + +#define TRAPS_ENABLED (m_psr & PSR_ET_MASK) +#define TRAPS_DISABLED (!TRAPS_ENABLED) + +#define PSR m_psr +#define WIM m_wim +#define TBR m_tbr + +#define OP (op >> 30) // gangnam style +#define OP2 ((op >> 22) & 7) +#define OP3 ((op >> 19) & 63) +#define OPF ((op >> 5) & 0x1ff) +#define OPC ((op >> 5) & 0x1ff) +#define OPFLOW ((op >> 5) & 0x3f) + +#define DISP30 (INT32(op << 2)) +#define DISP22 (INT32(op << 10) >> 8) +#define DISP19 (INT32(op << 13) >> 11) +#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14) +#define IMM22 (op << 10) #define CONST22 (op & 0x3fffff) -#define SIMM13 (INT32(op << 19) >> 19) -#define SIMM11 (INT32(op << 21) >> 21) -#define SIMM10 (INT32(op << 22) >> 22) -#define SIMM8 (INT32(op << 24) >> 24) -#define IMM7 (op & 0x7f) -#define SIMM7 (INT32(op << 25) >> 25) -#define SHCNT32 (op & 31) +#define SIMM13 (INT32(op << 19) >> 19) +#define SIMM11 (INT32(op << 21) >> 21) +#define SIMM10 (INT32(op << 22) >> 22) +#define SIMM8 (INT32(op << 24) >> 24) +#define IMM7 (op & 0x7f) +#define SIMM7 (INT32(op << 25) >> 25) +#define SHCNT32 (op & 31) #define SHCNT64 (op & 63) #define IAMODE (op & 0x7) -#define USEIMM ((op >> 13) & 1) -#define USEEXT ((op >> 12) & 1) - - -#define COND ((op >> 25) & 15) -#define RCOND ((op >> 10) & 7) -#define MOVCOND ((op >> 14) & 15) -#define PRED ((op >> 19) & 1) -#define ANNUL ((op >> 29) & 1) -#define BRCC ((op >> 20) & 3) -#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4)) -#define OPFCC ((op >> 11) & 7) -#define TCCCC ((op >> 11) & 3) -#define ASI ((op >> 5) & 255) -#define MMASK (op & 15) -#define CMASK ((op >> 4) & 7) - -#define RD ((op >> 25) & 31) -#define RS1 ((op >> 14) & 31) -#define RS2 (op & 31) - -#define FREG(x) m_fpr[(x)] -#define FDREG m_fpr[RD] -#define FSR m_fsr - -#define REG(x) *m_regs[(x)] -#define RDREG *m_regs[RD] -#define RS1REG *m_regs[RS1] -#define RS2REG *m_regs[RS2] -#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0) -#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG)) - -#define PC m_pc -#define nPC m_npc - -#define Y m_y - -#define ET m_et -#define EF m_ef -#define EC m_ec -#define PIL m_pil - -#define MAE m_mae -#define HOLD_BUS m_hold_bus - -#define BIT31(x) ((x) & 0x80000000) - -#define UPDATE_PC true -#define PC_UPDATED false - -#define OP_TYPE0 0 -#define OP_CALL 1 -#define OP_ALU 2 -#define OP_LDST 3 - -#define OP2_UNIMP 0 -#define OP2_BICC 2 -#define OP2_SETHI 4 -#define OP2_FBFCC 6 -#define OP2_CBCCC 7 - -#define OP3_ADD 0 -#define OP3_AND 1 -#define OP3_OR 2 -#define OP3_XOR 3 -#define OP3_SUB 4 -#define OP3_ANDN 5 -#define OP3_ORN 6 -#define OP3_XNOR 7 -#define OP3_ADDX 8 -#define OP3_UMUL 10 -#define OP3_SMUL 11 -#define OP3_SUBX 12 -#define OP3_UDIV 14 -#define OP3_SDIV 15 -#define OP3_ADDCC 16 -#define OP3_ANDCC 17 -#define OP3_ORCC 18 -#define OP3_XORCC 19 -#define OP3_SUBCC 20 -#define OP3_ANDNCC 21 -#define OP3_ORNCC 22 -#define OP3_XNORCC 23 -#define OP3_ADDXCC 24 -#define OP3_UMULCC 26 -#define OP3_SMULCC 27 -#define OP3_SUBXCC 28 -#define OP3_UDIVCC 30 -#define OP3_SDIVCC 31 -#define OP3_TADDCC 32 -#define OP3_TSUBCC 33 -#define OP3_TADDCCTV 34 -#define OP3_TSUBCCTV 35 -#define OP3_MULSCC 36 -#define OP3_SLL 37 -#define OP3_SRL 38 -#define OP3_SRA 39 -#define OP3_RDASR 40 -#define OP3_RDPSR 41 -#define OP3_RDWIM 42 -#define OP3_RDTBR 43 -#define OP3_WRASR 48 -#define OP3_WRPSR 49 -#define OP3_WRWIM 50 -#define OP3_WRTBR 51 -#define OP3_FPOP1 52 -#define OP3_FPOP2 53 -#define OP3_JMPL 56 -#define OP3_RETT 57 -#define OP3_TICC 58 -#define OP3_SAVE 60 -#define OP3_RESTORE 61 - -#define OP3_LD 0 -#define OP3_LDUB 1 -#define OP3_LDUH 2 -#define OP3_LDD 3 -#define OP3_ST 4 -#define OP3_STB 5 -#define OP3_STH 6 -#define OP3_STD 7 -#define OP3_LDSB 9 -#define OP3_LDSH 10 -#define OP3_LDSTUB 13 -#define OP3_SWAP 15 -#define OP3_LDA 16 -#define OP3_LDUBA 17 -#define OP3_LDUHA 18 -#define OP3_LDDA 19 -#define OP3_STA 20 -#define OP3_STBA 21 -#define OP3_STHA 22 -#define OP3_STDA 23 -#define OP3_LDSBA 25 -#define OP3_LDSHA 26 -#define OP3_LDSTUBA 29 -#define OP3_SWAPA 31 -#define OP3_LDFPR 32 -#define OP3_LDFSR 33 -#define OP3_LDDFPR 35 -#define OP3_STFPR 36 -#define OP3_STFSR 37 -#define OP3_STDFQ 38 -#define OP3_STDFPR 39 -#define OP3_LDCPR 40 -#define OP3_LDCSR 41 -#define OP3_LDDCPR 43 -#define OP3_STCPR 44 -#define OP3_STCSR 45 -#define OP3_STDCQ 46 -#define OP3_STDCPR 47 -#define OP3_CPOP1 54 -#define OP3_CPOP2 55 - -#define COND_BN 0 -#define COND_BE 1 -#define COND_BLE 2 -#define COND_BL 3 -#define COND_BLEU 4 -#define COND_BCS 5 -#define COND_BNEG 6 -#define COND_BVS 7 -#define COND_BA 8 -#define COND_BNE 9 -#define COND_BG 10 -#define COND_BGE 11 -#define COND_BGU 12 -#define COND_BCC 13 -#define COND_BPOS 14 -#define COND_BVC 15 - -#define LDD (OP3 == OP3_LDD) -#define LD (OP3 == OP3_LD) -#define LDSH (OP3 == OP3_LDSH) -#define LDUH (OP3 == OP3_LDUH) -#define LDSB (OP3 == OP3_LDSB) -#define LDUB (OP3 == OP3_LDUB) -#define LDDF (OP3 == OP3_LDDFPR) -#define LDF (OP3 == OP3_LDFPR) -#define LDFSR (OP3 == OP3_LDFSR) -#define LDDC (OP3 == OP3_LDDCPR) -#define LDC (OP3 == OP3_LDCPR) -#define LDCSR (OP3 == OP3_LDCSR) -#define LDDA (OP3 == OP3_LDDA) -#define LDA (OP3 == OP3_LDA) -#define LDSHA (OP3 == OP3_LDSHA) -#define LDUHA (OP3 == OP3_LDUHA) -#define LDSBA (OP3 == OP3_LDSBA) -#define LDUBA (OP3 == OP3_LDUBA) - -#define STD (OP3 == OP3_STD) -#define ST (OP3 == OP3_ST) -#define STH (OP3 == OP3_STH) -#define STB (OP3 == OP3_STB) -#define STDA (OP3 == OP3_STDA) -#define STA (OP3 == OP3_STA) -#define STHA (OP3 == OP3_STHA) -#define STBA (OP3 == OP3_STBA) -#define STF (OP3 == OP3_STFPR) -#define STFSR (OP3 == OP3_STFSR) -#define STDFQ (OP3 == OP3_STDFQ) -#define STDF (OP3 == OP3_STDFPR) -#define STC (OP3 == OP3_STCPR) -#define STCSR (OP3 == OP3_STCSR) -#define STDCQ (OP3 == OP3_STDCQ) -#define STDC (OP3 == OP3_STDCPR) - -#define JMPL (OP3 == OP3_JMPL) -#define TICC (OP3 == OP3_TICC) -#define RETT (OP3 == OP3_RETT) - -#define SWAP (OP3 == OP3_SWAP) -#define SWAPA (OP3 == OP3_SWAPA) - -#define FPOP1 (OP3 == OP3_FPOP1) -#define FPOP2 (OP3 == OP3_FPOP2) -#define CPOP1 (OP3 == OP3_CPOP1) -#define CPOP2 (OP3 == OP3_CPOP2) - -#define LDSTUB (OP3 == OP3_LDSTUB) -#define LDSTUBA (OP3 == OP3_LDSTUBA) - -#define ADD (OP3 == OP3_ADD) -#define ADDX (OP3 == OP3_ADDX) -#define ADDCC (OP3 == OP3_ADDCC) -#define ADDXCC (OP3 == OP3_ADDXCC) - -#define SUB (OP3 == OP3_SUB) -#define SUBX (OP3 == OP3_SUBX) -#define SUBCC (OP3 == OP3_SUBCC) -#define SUBXCC (OP3 == OP3_SUBXCC) - -#define TADDCCTV (OP3 == OP3_TADDCCTV) -#define TSUBCCTV (OP3 == OP3_TSUBCCTV) - -#define AND (OP3 == OP3_AND) -#define OR (OP3 == OP3_OR) -#define XOR (OP3 == OP3_XOR) -#define ANDN (OP3 == OP3_ANDN) -#define ORN (OP3 == OP3_ORN) -#define XNOR (OP3 == OP3_XNOR) -#define ANDCC (OP3 == OP3_ANDCC) -#define ORCC (OP3 == OP3_ORCC) -#define XORCC (OP3 == OP3_XORCC) -#define ANDNCC (OP3 == OP3_ANDNCC) -#define ORNCC (OP3 == OP3_ORNCC) -#define XNORCC (OP3 == OP3_XNORCC) - -#define SLL (OP3 == OP3_SLL) -#define SRL (OP3 == OP3_SRL) -#define SRA (OP3 == OP3_SRA) - -#define RDASR (OP3 == OP3_RDASR) -#define RDPSR (OP3 == OP3_RDPSR) -#define RDWIM (OP3 == OP3_RDWIM) -#define RDTBR (OP3 == OP3_RDTBR) - -#define WRASR (OP3 == OP3_WRASR) -#define WRPSR (OP3 == OP3_WRPSR) -#define WRWIM (OP3 == OP3_WRWIM) -#define WRTBR (OP3 == OP3_WRTBR) - -#define SAVE (OP3 == OP3_SAVE) -#define RESTORE (OP3 == OP3_RESTORE) - -#define UMUL (OP3 == OP3_UMUL) -#define UMULCC (OP3 == OP3_UMULCC) -#define SMUL (OP3 == OP3_SMUL) -#define SMULCC (OP3 == OP3_SMULCC) - -#define UDIV (OP3 == OP3_UDIV) -#define UDIVCC (OP3 == OP3_UDIVCC) -#define SDIV (OP3 == OP3_SDIV) -#define SDIVCC (OP3 == OP3_SDIVCC) - -#endif // __MB86901_DEFS_H__
\ No newline at end of file +#define USEIMM ((op >> 13) & 1) +#define USEEXT ((op >> 12) & 1) + + +#define COND ((op >> 25) & 15) +#define RCOND ((op >> 10) & 7) +#define MOVCOND ((op >> 14) & 15) +#define PRED ((op >> 19) & 1) +#define ANNUL ((op >> 29) & 1) +#define BRCC ((op >> 20) & 3) +#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4)) +#define OPFCC ((op >> 11) & 7) +#define TCCCC ((op >> 11) & 3) +#define ASI ((op >> 5) & 255) +#define MMASK (op & 15) +#define CMASK ((op >> 4) & 7) + +#define RD ((op >> 25) & 31) +#define RS1 ((op >> 14) & 31) +#define RS2 (op & 31) + +#define FREG(x) m_fpr[(x)] +#define FDREG m_fpr[RD] +#define FSR m_fsr + +#define REG(x) *m_regs[(x)] +#define RDREG *m_regs[RD] +#define RS1REG *m_regs[RS1] +#define RS2REG *m_regs[RS2] +#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0) +#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG)) + +#define PC m_pc +#define nPC m_npc + +#define Y m_y + +#define ET m_et +#define EF m_ef +#define EC m_ec +#define PIL m_pil + +#define MAE m_mae +#define HOLD_BUS m_hold_bus + +#define BIT31(x) ((x) & 0x80000000) + +#define UPDATE_PC true +#define PC_UPDATED false + +#define OP_TYPE0 0 +#define OP_CALL 1 +#define OP_ALU 2 +#define OP_LDST 3 + +#define OP2_UNIMP 0 +#define OP2_BICC 2 +#define OP2_SETHI 4 +#define OP2_FBFCC 6 +#define OP2_CBCCC 7 + +#define OP3_ADD 0 +#define OP3_AND 1 +#define OP3_OR 2 +#define OP3_XOR 3 +#define OP3_SUB 4 +#define OP3_ANDN 5 +#define OP3_ORN 6 +#define OP3_XNOR 7 +#define OP3_ADDX 8 +#define OP3_UMUL 10 +#define OP3_SMUL 11 +#define OP3_SUBX 12 +#define OP3_UDIV 14 +#define OP3_SDIV 15 +#define OP3_ADDCC 16 +#define OP3_ANDCC 17 +#define OP3_ORCC 18 +#define OP3_XORCC 19 +#define OP3_SUBCC 20 +#define OP3_ANDNCC 21 +#define OP3_ORNCC 22 +#define OP3_XNORCC 23 +#define OP3_ADDXCC 24 +#define OP3_UMULCC 26 +#define OP3_SMULCC 27 +#define OP3_SUBXCC 28 +#define OP3_UDIVCC 30 +#define OP3_SDIVCC 31 +#define OP3_TADDCC 32 +#define OP3_TSUBCC 33 +#define OP3_TADDCCTV 34 +#define OP3_TSUBCCTV 35 +#define OP3_MULSCC 36 +#define OP3_SLL 37 +#define OP3_SRL 38 +#define OP3_SRA 39 +#define OP3_RDASR 40 +#define OP3_RDPSR 41 +#define OP3_RDWIM 42 +#define OP3_RDTBR 43 +#define OP3_WRASR 48 +#define OP3_WRPSR 49 +#define OP3_WRWIM 50 +#define OP3_WRTBR 51 +#define OP3_FPOP1 52 +#define OP3_FPOP2 53 +#define OP3_JMPL 56 +#define OP3_RETT 57 +#define OP3_TICC 58 +#define OP3_SAVE 60 +#define OP3_RESTORE 61 + +#define OP3_LD 0 +#define OP3_LDUB 1 +#define OP3_LDUH 2 +#define OP3_LDD 3 +#define OP3_ST 4 +#define OP3_STB 5 +#define OP3_STH 6 +#define OP3_STD 7 +#define OP3_LDSB 9 +#define OP3_LDSH 10 +#define OP3_LDSTUB 13 +#define OP3_SWAP 15 +#define OP3_LDA 16 +#define OP3_LDUBA 17 +#define OP3_LDUHA 18 +#define OP3_LDDA 19 +#define OP3_STA 20 +#define OP3_STBA 21 +#define OP3_STHA 22 +#define OP3_STDA 23 +#define OP3_LDSBA 25 +#define OP3_LDSHA 26 +#define OP3_LDSTUBA 29 +#define OP3_SWAPA 31 +#define OP3_LDFPR 32 +#define OP3_LDFSR 33 +#define OP3_LDDFPR 35 +#define OP3_STFPR 36 +#define OP3_STFSR 37 +#define OP3_STDFQ 38 +#define OP3_STDFPR 39 +#define OP3_LDCPR 40 +#define OP3_LDCSR 41 +#define OP3_LDDCPR 43 +#define OP3_STCPR 44 +#define OP3_STCSR 45 +#define OP3_STDCQ 46 +#define OP3_STDCPR 47 +#define OP3_CPOP1 54 +#define OP3_CPOP2 55 + +#define COND_BN 0 +#define COND_BE 1 +#define COND_BLE 2 +#define COND_BL 3 +#define COND_BLEU 4 +#define COND_BCS 5 +#define COND_BNEG 6 +#define COND_BVS 7 +#define COND_BA 8 +#define COND_BNE 9 +#define COND_BG 10 +#define COND_BGE 11 +#define COND_BGU 12 +#define COND_BCC 13 +#define COND_BPOS 14 +#define COND_BVC 15 + +#define LDD (OP3 == OP3_LDD) +#define LD (OP3 == OP3_LD) +#define LDSH (OP3 == OP3_LDSH) +#define LDUH (OP3 == OP3_LDUH) +#define LDSB (OP3 == OP3_LDSB) +#define LDUB (OP3 == OP3_LDUB) +#define LDDF (OP3 == OP3_LDDFPR) +#define LDF (OP3 == OP3_LDFPR) +#define LDFSR (OP3 == OP3_LDFSR) +#define LDDC (OP3 == OP3_LDDCPR) +#define LDC (OP3 == OP3_LDCPR) +#define LDCSR (OP3 == OP3_LDCSR) +#define LDDA (OP3 == OP3_LDDA) +#define LDA (OP3 == OP3_LDA) +#define LDSHA (OP3 == OP3_LDSHA) +#define LDUHA (OP3 == OP3_LDUHA) +#define LDSBA (OP3 == OP3_LDSBA) +#define LDUBA (OP3 == OP3_LDUBA) + +#define STD (OP3 == OP3_STD) +#define ST (OP3 == OP3_ST) +#define STH (OP3 == OP3_STH) +#define STB (OP3 == OP3_STB) +#define STDA (OP3 == OP3_STDA) +#define STA (OP3 == OP3_STA) +#define STHA (OP3 == OP3_STHA) +#define STBA (OP3 == OP3_STBA) +#define STF (OP3 == OP3_STFPR) +#define STFSR (OP3 == OP3_STFSR) +#define STDFQ (OP3 == OP3_STDFQ) +#define STDF (OP3 == OP3_STDFPR) +#define STC (OP3 == OP3_STCPR) +#define STCSR (OP3 == OP3_STCSR) +#define STDCQ (OP3 == OP3_STDCQ) +#define STDC (OP3 == OP3_STDCPR) + +#define JMPL (OP3 == OP3_JMPL) +#define TICC (OP3 == OP3_TICC) +#define RETT (OP3 == OP3_RETT) + +#define SWAP (OP3 == OP3_SWAP) +#define SWAPA (OP3 == OP3_SWAPA) + +#define FPOP1 (OP3 == OP3_FPOP1) +#define FPOP2 (OP3 == OP3_FPOP2) +#define CPOP1 (OP3 == OP3_CPOP1) +#define CPOP2 (OP3 == OP3_CPOP2) + +#define LDSTUB (OP3 == OP3_LDSTUB) +#define LDSTUBA (OP3 == OP3_LDSTUBA) + +#define ADD (OP3 == OP3_ADD) +#define ADDX (OP3 == OP3_ADDX) +#define ADDCC (OP3 == OP3_ADDCC) +#define ADDXCC (OP3 == OP3_ADDXCC) + +#define SUB (OP3 == OP3_SUB) +#define SUBX (OP3 == OP3_SUBX) +#define SUBCC (OP3 == OP3_SUBCC) +#define SUBXCC (OP3 == OP3_SUBXCC) + +#define TADDCCTV (OP3 == OP3_TADDCCTV) +#define TSUBCCTV (OP3 == OP3_TSUBCCTV) + +#define AND (OP3 == OP3_AND) +#define OR (OP3 == OP3_OR) +#define XOR (OP3 == OP3_XOR) +#define ANDN (OP3 == OP3_ANDN) +#define ORN (OP3 == OP3_ORN) +#define XNOR (OP3 == OP3_XNOR) +#define ANDCC (OP3 == OP3_ANDCC) +#define ORCC (OP3 == OP3_ORCC) +#define XORCC (OP3 == OP3_XORCC) +#define ANDNCC (OP3 == OP3_ANDNCC) +#define ORNCC (OP3 == OP3_ORNCC) +#define XNORCC (OP3 == OP3_XNORCC) + +#define SLL (OP3 == OP3_SLL) +#define SRL (OP3 == OP3_SRL) +#define SRA (OP3 == OP3_SRA) + +#define RDASR (OP3 == OP3_RDASR) +#define RDPSR (OP3 == OP3_RDPSR) +#define RDWIM (OP3 == OP3_RDWIM) +#define RDTBR (OP3 == OP3_RDTBR) + +#define WRASR (OP3 == OP3_WRASR) +#define WRPSR (OP3 == OP3_WRPSR) +#define WRWIM (OP3 == OP3_WRWIM) +#define WRTBR (OP3 == OP3_WRTBR) + +#define SAVE (OP3 == OP3_SAVE) +#define RESTORE (OP3 == OP3_RESTORE) + +#define UMUL (OP3 == OP3_UMUL) +#define UMULCC (OP3 == OP3_UMULCC) +#define SMUL (OP3 == OP3_SMUL) +#define SMULCC (OP3 == OP3_SMULCC) + +#define UDIV (OP3 == OP3_UDIV) +#define UDIVCC (OP3 == OP3_UDIVCC) +#define SDIV (OP3 == OP3_SDIV) +#define SDIVCC (OP3 == OP3_SDIVCC) + +#endif // __MB86901_DEFS_H__ diff --git a/src/devices/cpu/tms32010/tms32010.h b/src/devices/cpu/tms32010/tms32010.h index 61e36279e17..d595b073997 100644 --- a/src/devices/cpu/tms32010/tms32010.h +++ b/src/devices/cpu/tms32010/tms32010.h @@ -45,7 +45,7 @@ public: // construction/destruction tms32010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); tms32010_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int addr_mask); - + // static configuration helpers template<class _Object> static devcb_base & set_bio_in_cb(device_t &device, _Object object) { return downcast<tms32010_device &>(device).m_bio_in.set_callback(object); } @@ -78,7 +78,7 @@ private: address_space_config m_program_config; address_space_config m_data_config; address_space_config m_io_config; - + devcb_read_line m_bio_in; typedef void ( tms32010_device::*opcode_func ) (); diff --git a/src/devices/cpu/tms32025/tms32025.h b/src/devices/cpu/tms32025/tms32025.h index 0d414c1cb4f..e112dafde51 100644 --- a/src/devices/cpu/tms32025/tms32025.h +++ b/src/devices/cpu/tms32025/tms32025.h @@ -31,7 +31,7 @@ #define MCFG_TMS32025_HOLD_ACK_OUT_CB(_devcb) \ devcb = &tms32025_device::set_hold_ack_out_cb(*device, DEVCB_##_devcb); /* HOLD Acknowledge output */ - + #define MCFG_TMS32025_XF_OUT_CB(_devcb) \ devcb = &tms32025_device::set_xf_out_cb(*device, DEVCB_##_devcb); /* XF output */ @@ -41,7 +41,7 @@ #define MCFG_TMS32025_DX_OUT_CB(_devcb) \ devcb = &tms32025_device::set_dx_out_cb(*device, DEVCB_##_devcb); /* Serial Data Transmit output */ - + /**************************************************************************** * Interrupt constants */ @@ -83,7 +83,7 @@ public: // construction/destruction tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); - + // static configuration helpers template<class _Object> static devcb_base & set_bio_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_bio_in.set_callback(object); } template<class _Object> static devcb_base & set_hold_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_hold_in.set_callback(object); } |