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author Ivan Vangelista <mesgnet@yahoo.it>2020-06-18 20:13:33 +0200
committer Ivan Vangelista <mesgnet@yahoo.it>2020-06-18 20:13:33 +0200
commit57cf17dc52bcd4571a68576dd6597ddf9fae41a8 (patch)
tree9fef8bce07d80de37886a6dc44c340da05517388 /src/devices/cpu
parente96ed3b0ebd5920e8aff2914a6ff28b435210717 (diff)
finally retired the READ8/16/32/64 and WRITE8/16/32/64 macros (nw)
Diffstat (limited to 'src/devices/cpu')
-rw-r--r--src/devices/cpu/alto2/a2hw.cpp76
-rw-r--r--src/devices/cpu/alto2/a2hw.h82
-rw-r--r--src/devices/cpu/alto2/a2kbd.cpp2
-rw-r--r--src/devices/cpu/alto2/a2kbd.h2
-rw-r--r--src/devices/cpu/alto2/a2mem.cpp14
-rw-r--r--src/devices/cpu/alto2/a2mem.h10
-rw-r--r--src/devices/cpu/alto2/alto2cpu.cpp14
-rw-r--r--src/devices/cpu/alto2/alto2cpu.h18
-rw-r--r--src/devices/cpu/arcompact/arcompact.cpp14
-rw-r--r--src/devices/cpu/arcompact/arcompact.h16
-rw-r--r--src/devices/cpu/arm7/arm7.cpp14
-rw-r--r--src/devices/cpu/arm7/arm7.h14
-rw-r--r--src/devices/cpu/arm7/arm7ops.cpp6
-rw-r--r--src/devices/cpu/arm7/lpc210x.cpp38
-rw-r--r--src/devices/cpu/arm7/lpc210x.h46
-rw-r--r--src/devices/cpu/dsp16/dsp16.cpp12
-rw-r--r--src/devices/cpu/dsp16/dsp16.h6
-rw-r--r--src/devices/cpu/dsp56156/dsp56156.h6
-rw-r--r--src/devices/cpu/dsp56156/dsp56mem.cpp4
-rw-r--r--src/devices/cpu/dspp/dspp.cpp36
-rw-r--r--src/devices/cpu/dspp/dspp.h36
-rw-r--r--src/devices/cpu/h8/h83002.cpp8
-rw-r--r--src/devices/cpu/h8/h83002.h8
-rw-r--r--src/devices/cpu/h8/h83003.cpp8
-rw-r--r--src/devices/cpu/h8/h83003.h8
-rw-r--r--src/devices/cpu/h8/h83006.cpp4
-rw-r--r--src/devices/cpu/h8/h83006.h4
-rw-r--r--src/devices/cpu/h8/h83008.cpp4
-rw-r--r--src/devices/cpu/h8/h83008.h4
-rw-r--r--src/devices/cpu/h8/h83048.cpp4
-rw-r--r--src/devices/cpu/h8/h83048.h4
-rw-r--r--src/devices/cpu/h8/h83337.cpp16
-rw-r--r--src/devices/cpu/h8/h83337.h16
-rw-r--r--src/devices/cpu/h8/h8_adc.cpp12
-rw-r--r--src/devices/cpu/h8/h8_adc.h12
-rw-r--r--src/devices/cpu/h8/h8_dma.cpp56
-rw-r--r--src/devices/cpu/h8/h8_dma.h56
-rw-r--r--src/devices/cpu/h8/h8_dtc.cpp8
-rw-r--r--src/devices/cpu/h8/h8_dtc.h8
-rw-r--r--src/devices/cpu/h8/h8_intc.cpp44
-rw-r--r--src/devices/cpu/h8/h8_intc.h36
-rw-r--r--src/devices/cpu/h8/h8_port.cpp16
-rw-r--r--src/devices/cpu/h8/h8_port.h16
-rw-r--r--src/devices/cpu/h8/h8_sci.cpp26
-rw-r--r--src/devices/cpu/h8/h8_sci.h26
-rw-r--r--src/devices/cpu/h8/h8_timer16.cpp70
-rw-r--r--src/devices/cpu/h8/h8_timer16.h66
-rw-r--r--src/devices/cpu/h8/h8_timer8.cpp16
-rw-r--r--src/devices/cpu/h8/h8_timer8.h16
-rw-r--r--src/devices/cpu/h8/h8_watchdog.cpp8
-rw-r--r--src/devices/cpu/h8/h8_watchdog.h8
-rw-r--r--src/devices/cpu/h8/h8s2245.cpp8
-rw-r--r--src/devices/cpu/h8/h8s2245.h8
-rw-r--r--src/devices/cpu/h8/h8s2320.cpp4
-rw-r--r--src/devices/cpu/h8/h8s2320.h4
-rw-r--r--src/devices/cpu/h8/h8s2357.cpp4
-rw-r--r--src/devices/cpu/h8/h8s2357.h4
-rw-r--r--src/devices/cpu/h8/h8s2655.cpp4
-rw-r--r--src/devices/cpu/h8/h8s2655.h4
-rw-r--r--src/devices/cpu/i386/athlon.cpp4
-rw-r--r--src/devices/cpu/i386/athlon.h2
-rw-r--r--src/devices/cpu/i86/i186.cpp36
-rw-r--r--src/devices/cpu/i86/i186.h4
-rw-r--r--src/devices/cpu/jaguar/jaguar.cpp30
-rw-r--r--src/devices/cpu/jaguar/jaguar.h30
-rw-r--r--src/devices/cpu/m6502/m3745x.cpp12
-rw-r--r--src/devices/cpu/m6502/m3745x.h12
-rw-r--r--src/devices/cpu/m6502/m5074x.cpp26
-rw-r--r--src/devices/cpu/m6502/m5074x.h10
-rw-r--r--src/devices/cpu/m6502/m6500_1.cpp24
-rw-r--r--src/devices/cpu/m6502/m6500_1.h34
-rw-r--r--src/devices/cpu/m6502/n2a03.cpp8
-rw-r--r--src/devices/cpu/m6502/n2a03.h8
-rw-r--r--src/devices/cpu/m6805/m68705.cpp30
-rw-r--r--src/devices/cpu/m6805/m68705.h26
-rw-r--r--src/devices/cpu/mips/ps2vif1.cpp4
-rw-r--r--src/devices/cpu/mips/ps2vif1.h4
-rw-r--r--src/devices/cpu/mips/ps2vu.cpp4
-rw-r--r--src/devices/cpu/mips/ps2vu.h4
-rw-r--r--src/devices/cpu/pps4/pps4.cpp2
-rw-r--r--src/devices/cpu/pps4/pps4.h2
-rw-r--r--src/devices/cpu/psx/dma.cpp4
-rw-r--r--src/devices/cpu/psx/dma.h4
-rw-r--r--src/devices/cpu/psx/irq.cpp4
-rw-r--r--src/devices/cpu/psx/irq.h4
-rw-r--r--src/devices/cpu/psx/mdec.cpp4
-rw-r--r--src/devices/cpu/psx/mdec.h4
-rw-r--r--src/devices/cpu/psx/psx.cpp56
-rw-r--r--src/devices/cpu/psx/psx.h40
-rw-r--r--src/devices/cpu/psx/rcnt.cpp4
-rw-r--r--src/devices/cpu/psx/rcnt.h4
-rw-r--r--src/devices/cpu/psx/sio.cpp4
-rw-r--r--src/devices/cpu/psx/sio.h4
-rw-r--r--src/devices/cpu/scudsp/scudsp.cpp12
-rw-r--r--src/devices/cpu/scudsp/scudsp.h12
-rw-r--r--src/devices/cpu/sh/sh2.cpp2
-rw-r--r--src/devices/cpu/sh/sh2.h208
-rw-r--r--src/devices/cpu/sh/sh2comn.cpp176
-rw-r--r--src/devices/cpu/sh/sh3comn.cpp8
-rw-r--r--src/devices/cpu/sh/sh4.h12
-rw-r--r--src/devices/cpu/sh/sh4comn.cpp4
-rw-r--r--src/devices/cpu/sh/sh7604_bus.cpp32
-rw-r--r--src/devices/cpu/sh/sh7604_bus.h32
-rw-r--r--src/devices/cpu/sh/sh7604_wdt.cpp4
-rw-r--r--src/devices/cpu/sh/sh7604_wdt.h4
-rw-r--r--src/devices/cpu/sharc/sharc.cpp12
-rw-r--r--src/devices/cpu/sharc/sharc.h12
-rw-r--r--src/devices/cpu/tms32025/tms32025.cpp24
-rw-r--r--src/devices/cpu/tms32025/tms32025.h26
-rw-r--r--src/devices/cpu/tms32031/tms32031.cpp2
-rw-r--r--src/devices/cpu/tms32031/tms32031.h4
-rw-r--r--src/devices/cpu/tms32051/tms32051.cpp4
-rw-r--r--src/devices/cpu/tms32051/tms32051.h4
113 files changed, 1070 insertions, 1070 deletions
diff --git a/src/devices/cpu/alto2/a2hw.cpp b/src/devices/cpu/alto2/a2hw.cpp
index bdb8897d1d7..acb5c913232 100644
--- a/src/devices/cpu/alto2/a2hw.cpp
+++ b/src/devices/cpu/alto2/a2hw.cpp
@@ -13,173 +13,173 @@
* @brief read printer paper ready bit
* Paper ready bit. 0 when the printer is ready for a paper scrolling operation.
*/
-READ16_MEMBER ( alto2_cpu_device::pprdy_r ) { return X_RDBITS(m_hw.utilin,16,0,0); }
+uint16_t alto2_cpu_device::pprdy_r() { return X_RDBITS(m_hw.utilin,16,0,0); }
/**
* @brief read printer check bit
* Printer check bit bit.
* Should the printer find itself in an abnormal state, it sets this bit to 0
*/
-READ16_MEMBER ( alto2_cpu_device::pcheck_r ) { return X_RDBITS(m_hw.utilin,16,1,1); }
+uint16_t alto2_cpu_device::pcheck_r() { return X_RDBITS(m_hw.utilin,16,1,1); }
/**
* @brief read unused bit 2
*/
-READ16_MEMBER ( alto2_cpu_device::unused2_r ) { return X_RDBITS(m_hw.utilin,16,2,2); }
+uint16_t alto2_cpu_device::unused2_r() { return X_RDBITS(m_hw.utilin,16,2,2); }
/**
* @brief read printer daisy ready bit
* Daisy ready bit. 0 when the printer is ready to print a character.
*/
-READ16_MEMBER ( alto2_cpu_device::pchrdy_r ) { return X_RDBITS(m_hw.utilin,16,3,3); }
+uint16_t alto2_cpu_device::pchrdy_r() { return X_RDBITS(m_hw.utilin,16,3,3); }
/**
* @brief read printer carriage ready bit
* Carriage ready bit. 0 when the printer is ready for horizontal positioning.
*/
-READ16_MEMBER ( alto2_cpu_device::parrdy_r ) { return X_RDBITS(m_hw.utilin,16,4,4); }
+uint16_t alto2_cpu_device::parrdy_r() { return X_RDBITS(m_hw.utilin,16,4,4); }
/**
* @brief read printer ready bit
* Ready bit. Both this bit and the appropriate other ready bit (carriage,
* daisy, etc.) must be 0 before attempting any output operation.
*/
-READ16_MEMBER ( alto2_cpu_device::pready_r ) { return X_RDBITS(m_hw.utilin,16,5,5); }
+uint16_t alto2_cpu_device::pready_r() { return X_RDBITS(m_hw.utilin,16,5,5); }
/**
* @brief memory configuration switch
*/
-READ16_MEMBER ( alto2_cpu_device::memconfig_r ) { return X_RDBITS(m_hw.utilin,16,6,6); }
+uint16_t alto2_cpu_device::memconfig_r() { return X_RDBITS(m_hw.utilin,16,6,6); }
/**
* @brief get unused bit 7
*/
-READ16_MEMBER ( alto2_cpu_device::unused7_r ) { return X_RDBITS(m_hw.utilin,16,7,7); }
+uint16_t alto2_cpu_device::unused7_r() { return X_RDBITS(m_hw.utilin,16,7,7); }
/**
* @brief get key set key 0
*/
-READ16_MEMBER ( alto2_cpu_device::keyset_key0_r ) { return X_RDBITS(m_hw.utilin,16,8,8); }
+uint16_t alto2_cpu_device::keyset_key0_r() { return X_RDBITS(m_hw.utilin,16,8,8); }
/**
* @brief get key set key 1
*/
-READ16_MEMBER ( alto2_cpu_device::keyset_key1_r ) { return X_RDBITS(m_hw.utilin,16,9,9); }
+uint16_t alto2_cpu_device::keyset_key1_r() { return X_RDBITS(m_hw.utilin,16,9,9); }
/**
* @brief get key set key 2
*/
-READ16_MEMBER ( alto2_cpu_device::keyset_key2_r ) { return X_RDBITS(m_hw.utilin,16,10,10); }
+uint16_t alto2_cpu_device::keyset_key2_r() { return X_RDBITS(m_hw.utilin,16,10,10); }
/**
* @brief get key set key 3
*/
-READ16_MEMBER ( alto2_cpu_device::keyset_key3_r ) { return X_RDBITS(m_hw.utilin,16,11,11); }
+uint16_t alto2_cpu_device::keyset_key3_r() { return X_RDBITS(m_hw.utilin,16,11,11); }
/**
* @brief get key set key 4
*/
-READ16_MEMBER ( alto2_cpu_device::keyset_key4_r ) { return X_RDBITS(m_hw.utilin,16,12,12); }
+uint16_t alto2_cpu_device::keyset_key4_r() { return X_RDBITS(m_hw.utilin,16,12,12); }
/**
* @brief get mouse red button bit
*/
-READ16_MEMBER ( alto2_cpu_device::mouse_red_r ) { return X_RDBITS(m_hw.utilin,16,13,13); }
+uint16_t alto2_cpu_device::mouse_red_r() { return X_RDBITS(m_hw.utilin,16,13,13); }
/**
* @brief get mouse blue button bit
*/
-READ16_MEMBER ( alto2_cpu_device::mouse_blue_r ) { return X_RDBITS(m_hw.utilin,16,14,14); }
+uint16_t alto2_cpu_device::mouse_blue_r() { return X_RDBITS(m_hw.utilin,16,14,14); }
/**
* @brief get mouse yellow button bit
*/
-READ16_MEMBER ( alto2_cpu_device::mouse_yellow_r ) { return X_RDBITS(m_hw.utilin,16,15,15); }
+uint16_t alto2_cpu_device::mouse_yellow_r() { return X_RDBITS(m_hw.utilin,16,15,15); }
/**
* @brief write printer paper ready bit
*/
-WRITE16_MEMBER( alto2_cpu_device::pprdy_w ) { X_WRBITS(m_hw.utilin,16,0,0,data); }
+void alto2_cpu_device::pprdy_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,0,0,data); }
/**
* @brief write printer check bit
*/
-WRITE16_MEMBER( alto2_cpu_device::pcheck_w ) { X_WRBITS(m_hw.utilin,16,1,1,data); }
+void alto2_cpu_device::pcheck_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,1,1,data); }
/**
* @brief read unused bit 2
*/
-WRITE16_MEMBER( alto2_cpu_device::unused2_w ) { X_WRBITS(m_hw.utilin,16,2,2,data); }
+void alto2_cpu_device::unused2_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,2,2,data); }
/**
* @brief write printer daisy ready bit
*/
-WRITE16_MEMBER( alto2_cpu_device::pchrdy_w ) { X_WRBITS(m_hw.utilin,16,3,3,data); }
+void alto2_cpu_device::pchrdy_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,3,3,data); }
/**
* @brief write printer carriage ready bit
*/
-WRITE16_MEMBER( alto2_cpu_device::parrdy_w ) { X_WRBITS(m_hw.utilin,16,4,4,data); }
+void alto2_cpu_device::parrdy_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,4,4,data); }
/**
* @brief write printer ready bit
*/
-WRITE16_MEMBER( alto2_cpu_device::pready_w ) { X_WRBITS(m_hw.utilin,16,5,5,data); }
+void alto2_cpu_device::pready_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,5,5,data); }
/**
* @brief write memory configuration switch
*/
-WRITE16_MEMBER( alto2_cpu_device::memconfig_w ) { X_WRBITS(m_hw.utilin,16,6,6,data); }
+void alto2_cpu_device::memconfig_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,6,6,data); }
/**
* @brief write unused bit 7
*/
-WRITE16_MEMBER( alto2_cpu_device::unused7_w ) { X_WRBITS(m_hw.utilin,16,7,7,data); }
+void alto2_cpu_device::unused7_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,7,7,data); }
/**
* @brief write key set key 0
*/
-WRITE16_MEMBER( alto2_cpu_device::keyset_key0_w ) { X_WRBITS(m_hw.utilin,16,8,8,data); }
+void alto2_cpu_device::keyset_key0_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,8,8,data); }
/**
* @brief write key set key 1
*/
-WRITE16_MEMBER( alto2_cpu_device::keyset_key1_w ) { X_WRBITS(m_hw.utilin,16,9,9,data); }
+void alto2_cpu_device::keyset_key1_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,9,9,data); }
/**
* @brief write key set key 2
*/
-WRITE16_MEMBER( alto2_cpu_device::keyset_key2_w ) { X_WRBITS(m_hw.utilin,16,10,10,data); }
+void alto2_cpu_device::keyset_key2_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,10,10,data); }
/**
* @brief write key set key 3
*/
-WRITE16_MEMBER( alto2_cpu_device::keyset_key3_w ) { X_WRBITS(m_hw.utilin,16,11,11,data); }
+void alto2_cpu_device::keyset_key3_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,11,11,data); }
/**
* @brief write key set key 4
*/
-WRITE16_MEMBER( alto2_cpu_device::keyset_key4_w ) { X_WRBITS(m_hw.utilin,16,12,12,data); }
+void alto2_cpu_device::keyset_key4_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,12,12,data); }
/**
* @brief write mouse red button bit
*/
-WRITE16_MEMBER( alto2_cpu_device::mouse_red_w ) { X_WRBITS(m_hw.utilin,16,13,13,data); }
+void alto2_cpu_device::mouse_red_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,13,13,data); }
/**
* @brief write mouse blue button bit
*/
-WRITE16_MEMBER( alto2_cpu_device::mouse_blue_w ) { X_WRBITS(m_hw.utilin,16,14,14,data); }
+void alto2_cpu_device::mouse_blue_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,14,14,data); }
/**
* @brief write mouse yellow button bit
*/
-WRITE16_MEMBER( alto2_cpu_device::mouse_yellow_w ) { X_WRBITS(m_hw.utilin,16,15,15,data); }
+void alto2_cpu_device::mouse_yellow_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,15,15,data); }
/**
* @brief write mouse buttons bits
*/
-WRITE16_MEMBER( alto2_cpu_device::mouse_buttons_w ) { X_WRBITS(m_hw.utilin,16,13,15,data); }
+void alto2_cpu_device::mouse_buttons_w(uint16_t data) { X_WRBITS(m_hw.utilin,16,13,15,data); }
/**
* @brief printer paper strobe bit
@@ -234,7 +234,7 @@ WRITE16_MEMBER( alto2_cpu_device::mouse_buttons_w ) { X_WRBITS(m_hw.utilin,16,13
* @param offset memory mapped I/O address to be read
* @return current value on the UTILIN port
*/
-READ16_MEMBER( alto2_cpu_device::utilin_r )
+uint16_t alto2_cpu_device::utilin_r(offs_t offset)
{
uint16_t data;
// FIXME: update the printer status
@@ -254,7 +254,7 @@ READ16_MEMBER( alto2_cpu_device::utilin_r )
* @param offset memory mapped I/O address to be read
* @return current value on the XBUS port latch
*/
-READ16_MEMBER( alto2_cpu_device::xbus_r )
+uint16_t alto2_cpu_device::xbus_r(offs_t offset)
{
uint16_t data = m_hw.xbus[offset & 3];
@@ -272,7 +272,7 @@ READ16_MEMBER( alto2_cpu_device::xbus_r )
* @param addr memory mapped I/O address to be read
* @param data value to write to the XBUS port latch
*/
-WRITE16_MEMBER( alto2_cpu_device::xbus_w )
+void alto2_cpu_device::xbus_w(offs_t offset, uint16_t data)
{
if (!machine().side_effects_disabled()) {
LOG((this,LOG_HW,2," XBUS[%d] wr %#o (%#o)\n", offset & 3, offset, data));
@@ -286,7 +286,7 @@ WRITE16_MEMBER( alto2_cpu_device::xbus_w )
* @param addr memory mapped I/O address to be read
* @return current value on the UTILOUT port latch
*/
-READ16_MEMBER( alto2_cpu_device::utilout_r )
+uint16_t alto2_cpu_device::utilout_r(offs_t offset)
{
uint16_t data = m_hw.utilout ^ 0177777;
if (!machine().side_effects_disabled()) {
@@ -303,7 +303,7 @@ READ16_MEMBER( alto2_cpu_device::utilout_r )
* @param addr memory mapped I/O address to be read
* @param data value to write to the UTILOUT port latch
*/
-WRITE16_MEMBER( alto2_cpu_device::utilout_w )
+void alto2_cpu_device::utilout_w(offs_t offset, uint16_t data)
{
if (!machine().side_effects_disabled()) {
LOG((this,LOG_HW,2," UTILOUT wr %#o (%#o)\n", offset, data));
diff --git a/src/devices/cpu/alto2/a2hw.h b/src/devices/cpu/alto2/a2hw.h
index 18accb36c23..e429ca65699 100644
--- a/src/devices/cpu/alto2/a2hw.h
+++ b/src/devices/cpu/alto2/a2hw.h
@@ -18,49 +18,49 @@ struct {
uint16_t utilin; //!< the UTILIN port at 0177030 to 0177033 (same value on all addresses)
} m_hw;
-DECLARE_READ16_MEMBER ( pprdy_r ); //!< read UTILIN[0] printer paper ready bit
-DECLARE_READ16_MEMBER ( pcheck_r ); //!< read UTILIN[1] printer check bit
-DECLARE_READ16_MEMBER ( unused2_r ); //!< read UTILIN[2] unused bit
-DECLARE_READ16_MEMBER ( pchrdy_r ); //!< read UTILIN[3] printer daisy ready bit
-DECLARE_READ16_MEMBER ( parrdy_r ); //!< read UTILIN[4] printer carriage ready bit
-DECLARE_READ16_MEMBER ( pready_r ); //!< read UTILIN[5] printer ready bit
-DECLARE_READ16_MEMBER ( memconfig_r ); //!< read UTILIN[6] memory config switch
-DECLARE_READ16_MEMBER ( unused7_r ); //!< read UTILIN[7] unused bit
-DECLARE_READ16_MEMBER ( keyset_key0_r ); //!< read UTILIN[8] keyset key #0
-DECLARE_READ16_MEMBER ( keyset_key1_r ); //!< read UTILIN[9] keyset key #1
-DECLARE_READ16_MEMBER ( keyset_key2_r ); //!< read UTILIN[10] keyset key #2
-DECLARE_READ16_MEMBER ( keyset_key3_r ); //!< read UTILIN[11] keyset key #3
-DECLARE_READ16_MEMBER ( keyset_key4_r ); //!< read UTILIN[12] keyset key #4
-DECLARE_READ16_MEMBER ( mouse_red_r ); //!< read UTILIN[13] mouse red button bit
-DECLARE_READ16_MEMBER ( mouse_blue_r ); //!< read UTILIN[14] mouse blue button bit
-DECLARE_READ16_MEMBER ( mouse_yellow_r ); //!< read UTILIN[15] mouse yellow button bit
+uint16_t pprdy_r(); //!< read UTILIN[0] printer paper ready bit
+uint16_t pcheck_r(); //!< read UTILIN[1] printer check bit
+uint16_t unused2_r(); //!< read UTILIN[2] unused bit
+uint16_t pchrdy_r(); //!< read UTILIN[3] printer daisy ready bit
+uint16_t parrdy_r(); //!< read UTILIN[4] printer carriage ready bit
+uint16_t pready_r(); //!< read UTILIN[5] printer ready bit
+uint16_t memconfig_r(); //!< read UTILIN[6] memory config switch
+uint16_t unused7_r(); //!< read UTILIN[7] unused bit
+uint16_t keyset_key0_r(); //!< read UTILIN[8] keyset key #0
+uint16_t keyset_key1_r(); //!< read UTILIN[9] keyset key #1
+uint16_t keyset_key2_r(); //!< read UTILIN[10] keyset key #2
+uint16_t keyset_key3_r(); //!< read UTILIN[11] keyset key #3
+uint16_t keyset_key4_r(); //!< read UTILIN[12] keyset key #4
+uint16_t mouse_red_r(); //!< read UTILIN[13] mouse red button bit
+uint16_t mouse_blue_r(); //!< read UTILIN[14] mouse blue button bit
+uint16_t mouse_yellow_r(); //!< read UTILIN[15] mouse yellow button bit
-DECLARE_WRITE16_MEMBER( pprdy_w ); //!< write UTILIN[0] printer paper ready bit
-DECLARE_WRITE16_MEMBER( pcheck_w ); //!< write UTILIN[1] printer check bit
-DECLARE_WRITE16_MEMBER( unused2_w ); //!< write UTILIN[2] unused bit
-DECLARE_WRITE16_MEMBER( pchrdy_w ); //!< write UTILIN[3] printer daisy ready bit
-DECLARE_WRITE16_MEMBER( parrdy_w ); //!< write UTILIN[4] carriage ready bit
-DECLARE_WRITE16_MEMBER( pready_w ); //!< write UTILIN[5] printer ready bit
-DECLARE_WRITE16_MEMBER( memconfig_w ); //!< write UTILIN[6] memory config switch
-DECLARE_WRITE16_MEMBER( unused7_w ); //!< write UTILIN[7] unused bit
-DECLARE_WRITE16_MEMBER( keyset_key0_w ); //!< write UTILIN[8] keyset key #0
-DECLARE_WRITE16_MEMBER( keyset_key1_w ); //!< write UTILIN[9] keyset key #1
-DECLARE_WRITE16_MEMBER( keyset_key2_w ); //!< write UTILIN[10] keyset key #2
-DECLARE_WRITE16_MEMBER( keyset_key3_w ); //!< write UTILIN[11] keyset key #3
-DECLARE_WRITE16_MEMBER( keyset_key4_w ); //!< write UTILIN[12] keyset key #4
-DECLARE_WRITE16_MEMBER( mouse_red_w ); //!< write UTILIN[13] mouse red button bit
-DECLARE_WRITE16_MEMBER( mouse_blue_w ); //!< write UTILIN[14] mouse blue button bit
-DECLARE_WRITE16_MEMBER( mouse_yellow_w ); //!< write UTILIN[15] mouse yellow button bit
-DECLARE_WRITE16_MEMBER( mouse_buttons_w ); //!< write UTILIN[13-15] mouse buttons bits
+void pprdy_w(uint16_t data); //!< write UTILIN[0] printer paper ready bit
+void pcheck_w(uint16_t data); //!< write UTILIN[1] printer check bit
+void unused2_w(uint16_t data); //!< write UTILIN[2] unused bit
+void pchrdy_w(uint16_t data); //!< write UTILIN[3] printer daisy ready bit
+void parrdy_w(uint16_t data); //!< write UTILIN[4] carriage ready bit
+void pready_w(uint16_t data); //!< write UTILIN[5] printer ready bit
+void memconfig_w(uint16_t data); //!< write UTILIN[6] memory config switch
+void unused7_w(uint16_t data); //!< write UTILIN[7] unused bit
+void keyset_key0_w(uint16_t data); //!< write UTILIN[8] keyset key #0
+void keyset_key1_w(uint16_t data); //!< write UTILIN[9] keyset key #1
+void keyset_key2_w(uint16_t data); //!< write UTILIN[10] keyset key #2
+void keyset_key3_w(uint16_t data); //!< write UTILIN[11] keyset key #3
+void keyset_key4_w(uint16_t data); //!< write UTILIN[12] keyset key #4
+void mouse_red_w(uint16_t data); //!< write UTILIN[13] mouse red button bit
+void mouse_blue_w(uint16_t data); //!< write UTILIN[14] mouse blue button bit
+void mouse_yellow_w(uint16_t data); //!< write UTILIN[15] mouse yellow button bit
+void mouse_buttons_w(uint16_t data); //!< write UTILIN[13-15] mouse buttons bits
-DECLARE_READ16_MEMBER ( utilin_r ); //!< read an UTILIN address
-DECLARE_READ16_MEMBER ( utilout_r ); //!< read the UTILOUT address
-DECLARE_WRITE16_MEMBER( utilout_w ); //!< write the UTILOUT address
-DECLARE_READ16_MEMBER ( xbus_r ); //!< read an XBUS address
-DECLARE_WRITE16_MEMBER( xbus_w ); //!< write an XBUS address (?)
+uint16_t utilin_r(offs_t offset); //!< read an UTILIN address
+uint16_t utilout_r(offs_t offset); //!< read the UTILOUT address
+void utilout_w(offs_t offset, uint16_t data); //!< write the UTILOUT address
+uint16_t xbus_r(offs_t offset); //!< read an XBUS address
+void xbus_w(offs_t offset, uint16_t data); //!< write an XBUS address (?)
-void init_hw(); //!< initialize miscellaneous hardware
-void exit_hw(); //!< deinitialize miscellaneous hardware
-void reset_hw(); //!< reset miscellaneous hardware
+void init_hw(); //!< initialize miscellaneous hardware
+void exit_hw(); //!< deinitialize miscellaneous hardware
+void reset_hw(); //!< reset miscellaneous hardware
#endif // _A2HW_H_
#endif // ALTO2_DEFINE_CONSTANTS
diff --git a/src/devices/cpu/alto2/a2kbd.cpp b/src/devices/cpu/alto2/a2kbd.cpp
index 4f7831beffb..ad94be209b4 100644
--- a/src/devices/cpu/alto2/a2kbd.cpp
+++ b/src/devices/cpu/alto2/a2kbd.cpp
@@ -14,7 +14,7 @@
* @param addr memory mapped I/O address to be read
* @return keyboard matrix value for address modulo 4
*/
-READ16_MEMBER( alto2_cpu_device::kbd_ad_r )
+uint16_t alto2_cpu_device::kbd_ad_r(offs_t offset)
{
uint16_t data = m_kb_read_callback(offset & 3);
m_kbd.matrix[offset & 03] = data;
diff --git a/src/devices/cpu/alto2/a2kbd.h b/src/devices/cpu/alto2/a2kbd.h
index 8f5c9dd2538..856695c4bd6 100644
--- a/src/devices/cpu/alto2/a2kbd.h
+++ b/src/devices/cpu/alto2/a2kbd.h
@@ -100,7 +100,7 @@ struct {
uint16_t matrix[4]; //!< a bit map of the keys pressed (ioports ROW0 ... ROW3)
} m_kbd;
-DECLARE_READ16_MEMBER( kbd_ad_r ); //!< read the keyboard matrix
+uint16_t kbd_ad_r(offs_t offset); //!< read the keyboard matrix
void init_kbd(uint16_t bootkey = 0177777); //!< initialize the keyboard hardware, optionally set the boot key
void exit_kbd(); //!< deinitialize the keyboard hardware
diff --git a/src/devices/cpu/alto2/a2mem.cpp b/src/devices/cpu/alto2/a2mem.cpp
index 036ac05e23e..aff5fcdd908 100644
--- a/src/devices/cpu/alto2/a2mem.cpp
+++ b/src/devices/cpu/alto2/a2mem.cpp
@@ -482,7 +482,7 @@ uint32_t alto2_cpu_device::hamming_code(bool write, uint32_t dw_addr, uint32_t d
* memory access. Note that MEAR is set whenever an error of
* _any kind_ (single-bit or double-bit) is detected.
*/
-READ16_MEMBER( alto2_cpu_device::mear_r )
+uint16_t alto2_cpu_device::mear_r()
{
int data = m_mem.error ? m_mem.mear : m_mem.mar;
if (!machine().side_effects_disabled()) {
@@ -507,7 +507,7 @@ READ16_MEMBER( alto2_cpu_device::mear_r )
* MESR[14-15] Bank number in which error occurred
* </PRE>
*/
-READ16_MEMBER( alto2_cpu_device::mesr_r )
+uint16_t alto2_cpu_device::mesr_r()
{
uint16_t data = m_mem.mesr ^ 0177777;
if (!machine().side_effects_disabled()) {
@@ -521,7 +521,7 @@ READ16_MEMBER( alto2_cpu_device::mesr_r )
return data;
}
-WRITE16_MEMBER( alto2_cpu_device::mesr_w )
+void alto2_cpu_device::mesr_w(uint16_t data)
{
if (!machine().side_effects_disabled()) {
LOG((this,LOG_MEM,2," MESR write %07o (clear MESR; was %07o)\n", data, m_mem.mesr));
@@ -552,7 +552,7 @@ WRITE16_MEMBER( alto2_cpu_device::mesr_w )
* MECR[15] Spare
* </PRE>
*/
-WRITE16_MEMBER( alto2_cpu_device::mecr_w )
+void alto2_cpu_device::mecr_w(uint16_t data)
{
m_mem.mecr = data ^ 0177777;
// clear spare bits
@@ -571,7 +571,7 @@ WRITE16_MEMBER( alto2_cpu_device::mecr_w )
/**
* @brief memory error control register read
*/
-READ16_MEMBER( alto2_cpu_device::mecr_r )
+uint16_t alto2_cpu_device::mecr_r()
{
uint16_t data = m_mem.mecr ^ 0177777;
// all spare bits are set
@@ -591,7 +591,7 @@ READ16_MEMBER( alto2_cpu_device::mecr_r )
* Note: This is for debugger access. Regular memory access is
* only through load_mar, read_mem and write_mem.
*/
-READ16_MEMBER ( alto2_cpu_device::ioram_r )
+uint16_t alto2_cpu_device::ioram_r(offs_t offset)
{
offs_t dw_addr = offset / 2;
return static_cast<uint16_t>(offset & 1 ? GET_ODD(m_mem.ram[dw_addr]) : GET_EVEN(m_mem.ram[dw_addr]));
@@ -602,7 +602,7 @@ READ16_MEMBER ( alto2_cpu_device::ioram_r )
* Note: This is for debugger access. Regular memory access is
* only through load_mar, read_mem and write_mem.
*/
-WRITE16_MEMBER( alto2_cpu_device::ioram_w )
+void alto2_cpu_device::ioram_w(offs_t offset, uint16_t data)
{
offs_t dw_addr = offset / 2;
if (offset & 1)
diff --git a/src/devices/cpu/alto2/a2mem.h b/src/devices/cpu/alto2/a2mem.h
index 8c79c439a6c..631f98cfbc7 100644
--- a/src/devices/cpu/alto2/a2mem.h
+++ b/src/devices/cpu/alto2/a2mem.h
@@ -103,11 +103,11 @@ inline bool check_mem_write_stall() {
}
-DECLARE_READ16_MEMBER ( mear_r ); //!< memory error address register read
-DECLARE_READ16_MEMBER ( mesr_r ); //!< memory error status register read
-DECLARE_WRITE16_MEMBER( mesr_w ); //!< memory error status register write (clear)
-DECLARE_READ16_MEMBER ( mecr_r ); //!< memory error control register read
-DECLARE_WRITE16_MEMBER( mecr_w ); //!< memory error control register write
+uint16_t mear_r(); //!< memory error address register read
+uint16_t mesr_r(); //!< memory error status register read
+void mesr_w(uint16_t data); //!< memory error status register write (clear)
+uint16_t mecr_r(); //!< memory error control register read
+void mecr_w(uint16_t data); //!< memory error control register write
//! Read or write a memory double-word and calculate or compare its Hamming code.
uint32_t hamming_code(bool write, uint32_t dw_addr, uint32_t dw_data);
diff --git a/src/devices/cpu/alto2/alto2cpu.cpp b/src/devices/cpu/alto2/alto2cpu.cpp
index bffe5071192..f5669884a3a 100644
--- a/src/devices/cpu/alto2/alto2cpu.cpp
+++ b/src/devices/cpu/alto2/alto2cpu.cpp
@@ -1006,7 +1006,7 @@ void alto2_cpu_device::state_string_export(const device_state_entry &entry, std:
}
//! read microcode CROM or CRAM
-READ32_MEMBER ( alto2_cpu_device::crom_cram_r )
+uint32_t alto2_cpu_device::crom_cram_r(offs_t offset)
{
if (offset < m_ucode_ram_base)
return *reinterpret_cast<uint32_t *>(m_ucode_crom + offset * 4);
@@ -1014,7 +1014,7 @@ READ32_MEMBER ( alto2_cpu_device::crom_cram_r )
}
//! write microcode CROM or CRAM (CROM of course can't be written)
-WRITE32_MEMBER( alto2_cpu_device::crom_cram_w )
+void alto2_cpu_device::crom_cram_w(offs_t offset, uint32_t data)
{
if (offset < m_ucode_ram_base)
return;
@@ -1022,7 +1022,7 @@ WRITE32_MEMBER( alto2_cpu_device::crom_cram_w )
}
//! read constants PROM
-READ16_MEMBER ( alto2_cpu_device::const_r )
+uint16_t alto2_cpu_device::const_r(offs_t offset)
{
return *reinterpret_cast<uint16_t *>(m_const_data + offset * 2);
}
@@ -1364,7 +1364,7 @@ static const char* memory_range_name(offs_t offset)
/**
* @brief read the open bus for unused MMIO range
*/
-READ16_MEMBER( alto2_cpu_device::noop_r )
+uint16_t alto2_cpu_device::noop_r(offs_t offset)
{
LOG((this,LOG_CPU,0," MMIO rd %s\n", memory_range_name(offset)));
return 0177777;
@@ -1373,7 +1373,7 @@ READ16_MEMBER( alto2_cpu_device::noop_r )
/**
* @brief write nowhere for unused MMIO range
*/
-WRITE16_MEMBER( alto2_cpu_device::noop_w )
+void alto2_cpu_device::noop_w(offs_t offset, uint16_t data)
{
LOG((this,LOG_CPU,0," MMIO wr %s\n", memory_range_name(offset)));
}
@@ -1383,7 +1383,7 @@ WRITE16_MEMBER( alto2_cpu_device::noop_w )
*
* The bank registers are stored in a 16x4-bit RAM 74S189.
*/
-READ16_MEMBER( alto2_cpu_device::bank_reg_r )
+uint16_t alto2_cpu_device::bank_reg_r(offs_t offset)
{
int task = offset & 017;
int bank = m_bank_reg[task] | 0177760;
@@ -1395,7 +1395,7 @@ READ16_MEMBER( alto2_cpu_device::bank_reg_r )
*
* The bank registers are stored in a 16x4-bit RAM 74S189.
*/
-WRITE16_MEMBER( alto2_cpu_device::bank_reg_w )
+void alto2_cpu_device::bank_reg_w(offs_t offset, uint16_t data)
{
int task = offset & 017;
m_bank_reg[task] = data & 017;
diff --git a/src/devices/cpu/alto2/alto2cpu.h b/src/devices/cpu/alto2/alto2cpu.h
index e1e66f5bcaf..603c5ac057a 100644
--- a/src/devices/cpu/alto2/alto2cpu.h
+++ b/src/devices/cpu/alto2/alto2cpu.h
@@ -260,19 +260,19 @@ private:
void iomem_map(address_map &map);
//! read microcode CROM or CRAM, depending on m_ucode_ram_base
- DECLARE_READ32_MEMBER ( crom_cram_r );
+ uint32_t crom_cram_r(offs_t offset);
//! write microcode CRAM, depending on m_ucode_ram_base (ignore writes to CROM)
- DECLARE_WRITE32_MEMBER( crom_cram_w );
+ void crom_cram_w(offs_t offset, uint32_t data);
//! read constants PROM
- DECLARE_READ16_MEMBER ( const_r );
+ uint16_t const_r(offs_t offset);
//! read i/o space RAM
- DECLARE_READ16_MEMBER ( ioram_r );
+ uint16_t ioram_r(offs_t offset);
//!< write i/o space RAM
- DECLARE_WRITE16_MEMBER( ioram_w );
+ void ioram_w(offs_t offset, uint16_t data);
int m_icount;
@@ -875,11 +875,11 @@ private:
[[noreturn]] void f2_early_bad(); //! f2 dummy early function
[[noreturn]] void f2_late_bad(); //! f2 dummy late function
- DECLARE_READ16_MEMBER( noop_r ); //!< read open bus (0177777)
- DECLARE_WRITE16_MEMBER( noop_w ); //!< write open bus
+ uint16_t noop_r (offs_t offset); //!< read open bus (0177777)
+ void noop_w(offs_t offset, uint16_t data); //!< write open bus
- DECLARE_READ16_MEMBER( bank_reg_r ); //!< read bank register in memory mapped I/O range
- DECLARE_WRITE16_MEMBER( bank_reg_w ); //!< write bank register in memory mapped I/O range
+ uint16_t bank_reg_r(offs_t offset); //!< read bank register in memory mapped I/O range
+ void bank_reg_w(offs_t offset, uint16_t data); //!< write bank register in memory mapped I/O range
void bs_early_read_r(); //!< bus source: drive bus by R register
void bs_early_load_r(); //!< bus source: load R places 0 on the BUS
diff --git a/src/devices/cpu/arcompact/arcompact.cpp b/src/devices/cpu/arcompact/arcompact.cpp
index c35798e5b94..7ca4cc02d3a 100644
--- a/src/devices/cpu/arcompact/arcompact.cpp
+++ b/src/devices/cpu/arcompact/arcompact.cpp
@@ -27,15 +27,15 @@
DEFINE_DEVICE_TYPE(ARCA5, arcompact_device, "arc_a5", "Argonaut ARCtangent A5")
-READ32_MEMBER( arcompact_device::arcompact_auxreg002_LPSTART_r) { return m_LP_START&0xfffffffe; }
-WRITE32_MEMBER(arcompact_device::arcompact_auxreg002_LPSTART_w) { m_LP_START = data&0xfffffffe; }
-READ32_MEMBER( arcompact_device::arcompact_auxreg003_LPEND_r) { return m_LP_END&0xfffffffe; }
-WRITE32_MEMBER(arcompact_device::arcompact_auxreg003_LPEND_w) { m_LP_END = data&0xfffffffe; }
+uint32_t arcompact_device::arcompact_auxreg002_LPSTART_r() { return m_LP_START&0xfffffffe; }
+void arcompact_device::arcompact_auxreg002_LPSTART_w(uint32_t data) { m_LP_START = data&0xfffffffe; }
+uint32_t arcompact_device::arcompact_auxreg003_LPEND_r() { return m_LP_END&0xfffffffe; }
+void arcompact_device::arcompact_auxreg003_LPEND_w(uint32_t data) { m_LP_END = data&0xfffffffe; }
-READ32_MEMBER( arcompact_device::arcompact_auxreg00a_STATUS32_r) { return 0xffffdead; /*m_status32;*/ }
+uint32_t arcompact_device::arcompact_auxreg00a_STATUS32_r() { return 0xffffdead; /*m_status32;*/ }
-READ32_MEMBER( arcompact_device::arcompact_auxreg025_INTVECTORBASE_r) { return m_INTVECTORBASE&0xfffffc00; }
-WRITE32_MEMBER(arcompact_device::arcompact_auxreg025_INTVECTORBASE_w) { m_INTVECTORBASE = data&0xfffffc00; }
+uint32_t arcompact_device::arcompact_auxreg025_INTVECTORBASE_r() { return m_INTVECTORBASE&0xfffffc00; }
+void arcompact_device::arcompact_auxreg025_INTVECTORBASE_w(uint32_t data) { m_INTVECTORBASE = data&0xfffffc00; }
diff --git a/src/devices/cpu/arcompact/arcompact.h b/src/devices/cpu/arcompact/arcompact.h
index 7d8be5453f0..d87499bc969 100644
--- a/src/devices/cpu/arcompact/arcompact.h
+++ b/src/devices/cpu/arcompact/arcompact.h
@@ -72,14 +72,14 @@ public:
// construction/destruction
arcompact_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ32_MEMBER( arcompact_auxreg002_LPSTART_r);
- DECLARE_WRITE32_MEMBER(arcompact_auxreg002_LPSTART_w);
- DECLARE_READ32_MEMBER( arcompact_auxreg003_LPEND_r);
- DECLARE_WRITE32_MEMBER(arcompact_auxreg003_LPEND_w);
-
- DECLARE_READ32_MEMBER( arcompact_auxreg00a_STATUS32_r);
- DECLARE_READ32_MEMBER( arcompact_auxreg025_INTVECTORBASE_r);
- DECLARE_WRITE32_MEMBER( arcompact_auxreg025_INTVECTORBASE_w);
+ uint32_t arcompact_auxreg002_LPSTART_r();
+ void arcompact_auxreg002_LPSTART_w(uint32_t data);
+ uint32_t arcompact_auxreg003_LPEND_r();
+ void arcompact_auxreg003_LPEND_w(uint32_t data);
+
+ uint32_t arcompact_auxreg00a_STATUS32_r();
+ uint32_t arcompact_auxreg025_INTVECTORBASE_r();
+ void arcompact_auxreg025_INTVECTORBASE_w(uint32_t data);
void arcompact_auxreg_map(address_map &map);
diff --git a/src/devices/cpu/arm7/arm7.cpp b/src/devices/cpu/arm7/arm7.cpp
index d496265d41d..d76a54a3c91 100644
--- a/src/devices/cpu/arm7/arm7.cpp
+++ b/src/devices/cpu/arm7/arm7.cpp
@@ -1245,13 +1245,13 @@ bool arm7_cpu_device::get_t_flag() const
/* ARM system coprocessor support */
-WRITE32_MEMBER( arm7_cpu_device::arm7_do_callback )
+void arm7_cpu_device::arm7_do_callback(uint32_t data)
{
m_pendingUnd = true;
update_irq_state();
}
-READ32_MEMBER( arm7_cpu_device::arm7_rt_r_callback )
+uint32_t arm7_cpu_device::arm7_rt_r_callback(offs_t offset)
{
uint32_t opcode = offset;
uint8_t cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
@@ -1367,7 +1367,7 @@ READ32_MEMBER( arm7_cpu_device::arm7_rt_r_callback )
return data;
}
-WRITE32_MEMBER( arm7_cpu_device::arm7_rt_w_callback )
+void arm7_cpu_device::arm7_rt_w_callback(offs_t offset, uint32_t data)
{
uint32_t opcode = offset;
uint8_t cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
@@ -1477,7 +1477,7 @@ WRITE32_MEMBER( arm7_cpu_device::arm7_rt_w_callback )
}
}
-READ32_MEMBER( arm946es_cpu_device::arm7_rt_r_callback )
+uint32_t arm946es_cpu_device::arm7_rt_r_callback(offs_t offset)
{
uint32_t opcode = offset;
uint8_t cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
@@ -1531,7 +1531,7 @@ READ32_MEMBER( arm946es_cpu_device::arm7_rt_r_callback )
return data;
}
-WRITE32_MEMBER( arm946es_cpu_device::arm7_rt_w_callback )
+void arm946es_cpu_device::arm7_rt_w_callback(offs_t offset, uint32_t data)
{
uint32_t opcode = offset;
uint8_t cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
@@ -1782,7 +1782,7 @@ void arm7_cpu_device::arm7_dt_w_callback(uint32_t insn, uint32_t *prn)
}
}
-READ32_MEMBER( arm1176jzf_s_cpu_device::arm7_rt_r_callback )
+uint32_t arm1176jzf_s_cpu_device::arm7_rt_r_callback(offs_t offset)
{
uint32_t opcode = offset;
uint8_t crn = (opcode & INSN_COPRO_CREG) >> INSN_COPRO_CREG_SHIFT;
@@ -1803,7 +1803,7 @@ READ32_MEMBER( arm1176jzf_s_cpu_device::arm7_rt_r_callback )
return data;
}
-WRITE32_MEMBER( arm1176jzf_s_cpu_device::arm7_rt_w_callback )
+void arm1176jzf_s_cpu_device::arm7_rt_w_callback(offs_t offset, uint32_t data)
{
uint32_t opcode = offset;
uint8_t crn = (opcode & INSN_COPRO_CREG) >> INSN_COPRO_CREG_SHIFT;
diff --git a/src/devices/cpu/arm7/arm7.h b/src/devices/cpu/arm7/arm7.h
index 0a7a451ccfa..3f6f9c290a5 100644
--- a/src/devices/cpu/arm7/arm7.h
+++ b/src/devices/cpu/arm7/arm7.h
@@ -246,9 +246,9 @@ protected:
virtual uint8_t arm7_cpu_read8(uint32_t addr);
// Coprocessor support
- DECLARE_WRITE32_MEMBER( arm7_do_callback );
- virtual DECLARE_READ32_MEMBER( arm7_rt_r_callback );
- virtual DECLARE_WRITE32_MEMBER( arm7_rt_w_callback );
+ void arm7_do_callback(uint32_t data);
+ virtual uint32_t arm7_rt_r_callback(offs_t offset);
+ virtual void arm7_rt_w_callback(offs_t offset, uint32_t data);
void arm7_dt_r_callback(uint32_t insn, uint32_t *prn);
void arm7_dt_w_callback(uint32_t insn, uint32_t *prn);
@@ -637,8 +637,8 @@ public:
arm946es_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// 946E-S has Protection Unit instead of ARM MMU so CP15 is quite different
- virtual DECLARE_READ32_MEMBER( arm7_rt_r_callback ) override;
- virtual DECLARE_WRITE32_MEMBER( arm7_rt_w_callback ) override;
+ virtual uint32_t arm7_rt_r_callback(offs_t offset) override;
+ virtual void arm7_rt_w_callback(offs_t offset, uint32_t data) override;
virtual void arm7_cpu_write32(uint32_t addr, uint32_t data) override;
virtual void arm7_cpu_write16(uint32_t addr, uint16_t data) override;
@@ -677,8 +677,8 @@ public:
// construction/destruction
arm1176jzf_s_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- virtual DECLARE_READ32_MEMBER( arm7_rt_r_callback ) override;
- virtual DECLARE_WRITE32_MEMBER( arm7_rt_w_callback ) override;
+ virtual uint32_t arm7_rt_r_callback(offs_t offset) override;
+ virtual void arm7_rt_w_callback(offs_t offset, uint32_t data) override;
protected:
virtual void device_reset() override;
diff --git a/src/devices/cpu/arm7/arm7ops.cpp b/src/devices/cpu/arm7/arm7ops.cpp
index 5bea4bbe5bd..f005406765f 100644
--- a/src/devices/cpu/arm7/arm7ops.cpp
+++ b/src/devices/cpu/arm7/arm7ops.cpp
@@ -299,7 +299,7 @@ int arm7_cpu_device::storeDec(uint32_t pat, uint32_t rbv, int mode)
void arm7_cpu_device::HandleCoProcDO(uint32_t insn)
{
// This instruction simply instructs the co-processor to do something, no data is returned to ARM7 core
- arm7_do_callback(*m_program, insn, 0, 0); // simply pass entire opcode to callback - since data format is actually dependent on co-proc implementation
+ arm7_do_callback(0); // simply pass entire opcode to callback - since data format is actually dependent on co-proc implementation
}
// Co-Processor Register Transfer - To/From Arm to Co-Proc
@@ -310,7 +310,7 @@ void arm7_cpu_device::HandleCoProcRT(uint32_t insn)
// Load (MRC) data from Co-Proc to ARM7 register
if (insn & 0x00100000) // Bit 20 = Load or Store
{
- uint32_t res = arm7_rt_r_callback(*m_program, insn, 0); // RT Read handler must parse opcode & return appropriate result
+ uint32_t res = arm7_rt_r_callback(insn); // RT Read handler must parse opcode & return appropriate result
if (!m_pendingUnd)
{
SetRegister((insn >> 12) & 0xf, res);
@@ -319,7 +319,7 @@ void arm7_cpu_device::HandleCoProcRT(uint32_t insn)
// Store (MCR) data from ARM7 to Co-Proc register
else
{
- arm7_rt_w_callback(*m_program, insn, GetRegister((insn >> 12) & 0xf), 0);
+ arm7_rt_w_callback(insn, GetRegister((insn >> 12) & 0xf));
}
}
diff --git a/src/devices/cpu/arm7/lpc210x.cpp b/src/devices/cpu/arm7/lpc210x.cpp
index d2964589e01..9e63b5785d0 100644
--- a/src/devices/cpu/arm7/lpc210x.cpp
+++ b/src/devices/cpu/arm7/lpc210x.cpp
@@ -47,12 +47,12 @@ lpc210x_device::lpc210x_device(const machine_config &mconfig, const char *tag, d
{
}
-READ32_MEMBER(lpc210x_device::arm_E01FC088_r)
+uint32_t lpc210x_device::arm_E01FC088_r()
{
return 0xffffffff;
}
-READ32_MEMBER(lpc210x_device::flash_r)
+uint32_t lpc210x_device::flash_r(offs_t offset)
{
uint32_t ret = (m_flash[offset * 4 + 3] << 24) |
(m_flash[offset * 4 + 2] << 16) |
@@ -61,7 +61,7 @@ READ32_MEMBER(lpc210x_device::flash_r)
return ret;
}
-WRITE32_MEMBER(lpc210x_device::flash_w)
+void lpc210x_device::flash_w(offs_t offset, uint32_t data)
{
//
}
@@ -100,7 +100,7 @@ void lpc210x_device::device_reset()
/* VIC (Vectored Interrupt Controller) */
-READ32_MEMBER( lpc210x_device::vic_r )
+uint32_t lpc210x_device::vic_r(offs_t offset, uint32_t mem_mask)
{
switch (offset*4)
{
@@ -112,7 +112,7 @@ READ32_MEMBER( lpc210x_device::vic_r )
}
-WRITE32_MEMBER( lpc210x_device::vic_w )
+void lpc210x_device::vic_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch (offset * 4)
{
@@ -123,7 +123,7 @@ WRITE32_MEMBER( lpc210x_device::vic_w )
/* PIN Select block */
-READ32_MEMBER( lpc210x_device::pin_r )
+uint32_t lpc210x_device::pin_r(offs_t offset, uint32_t mem_mask)
{
switch (offset*4)
{
@@ -135,7 +135,7 @@ READ32_MEMBER( lpc210x_device::pin_r )
}
-WRITE32_MEMBER( lpc210x_device::pin_w )
+void lpc210x_device::pin_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch (offset * 4)
{
@@ -146,7 +146,7 @@ WRITE32_MEMBER( lpc210x_device::pin_w )
/* MAM block (memory conttroller) */
-READ32_MEMBER( lpc210x_device::mam_r )
+uint32_t lpc210x_device::mam_r(offs_t offset, uint32_t mem_mask)
{
switch (offset*4)
{
@@ -158,7 +158,7 @@ READ32_MEMBER( lpc210x_device::mam_r )
}
-WRITE32_MEMBER( lpc210x_device::mam_w )
+void lpc210x_device::mam_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch (offset * 4)
{
@@ -169,7 +169,7 @@ WRITE32_MEMBER( lpc210x_device::mam_w )
/* FIO block */
-READ32_MEMBER( lpc210x_device::fio_r )
+uint32_t lpc210x_device::fio_r(offs_t offset, uint32_t mem_mask)
{
switch (offset*4)
{
@@ -181,7 +181,7 @@ READ32_MEMBER( lpc210x_device::fio_r )
}
-WRITE32_MEMBER( lpc210x_device::fio_w )
+void lpc210x_device::fio_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch (offset * 4)
{
@@ -193,35 +193,35 @@ WRITE32_MEMBER( lpc210x_device::fio_w )
/* APB Divider */
-READ32_MEMBER( lpc210x_device::apbdiv_r )
+uint32_t lpc210x_device::apbdiv_r(offs_t offset, uint32_t mem_mask)
{
logerror("%s unhandled read from APBDIV offset %08x mem_mask %08x\n", machine().describe_context(), offset * 4, mem_mask);
return 0x00000000;
}
-WRITE32_MEMBER( lpc210x_device::apbdiv_w )
+void lpc210x_device::apbdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
logerror("%s unhandled write APBDIV offset %02x data %08x mem_mask %08x\n", machine().describe_context(),offset * 4, data, mem_mask);
}
/* Syscon misc registers */
-READ32_MEMBER( lpc210x_device::scs_r )
+uint32_t lpc210x_device::scs_r(offs_t offset, uint32_t mem_mask)
{
logerror("%s unhandled read from SCS offset %08x mem_mask %08x\n", machine().describe_context(),offset * 4, mem_mask);
return 0x00000000;
}
-WRITE32_MEMBER( lpc210x_device::scs_w )
+void lpc210x_device::scs_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
logerror("%s unhandled write SCS offset %02x data %08x mem_mask %08x\n", machine().describe_context(),offset * 4, data, mem_mask);
}
/* PLL Phase Locked Loop */
-READ32_MEMBER( lpc210x_device::pll_r )
+uint32_t lpc210x_device::pll_r(offs_t offset, uint32_t mem_mask)
{
switch (offset*4)
{
@@ -233,7 +233,7 @@ READ32_MEMBER( lpc210x_device::pll_r )
}
-WRITE32_MEMBER( lpc210x_device::pll_w )
+void lpc210x_device::pll_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch (offset * 4)
{
@@ -245,7 +245,7 @@ WRITE32_MEMBER( lpc210x_device::pll_w )
/* Timers */
-uint32_t lpc210x_device::read_timer(address_space &space, int timer, int offset, uint32_t mem_mask)
+uint32_t lpc210x_device::read_timer(int timer, int offset, uint32_t mem_mask)
{
switch (offset*4)
{
@@ -260,7 +260,7 @@ uint32_t lpc210x_device::read_timer(address_space &space, int timer, int offset,
}
-void lpc210x_device::write_timer(address_space &space, int timer, int offset, uint32_t data, uint32_t mem_mask)
+void lpc210x_device::write_timer(int timer, int offset, uint32_t data, uint32_t mem_mask)
{
switch (offset * 4)
{
diff --git a/src/devices/cpu/arm7/lpc210x.h b/src/devices/cpu/arm7/lpc210x.h
index afcc4a57795..c21b346a5e3 100644
--- a/src/devices/cpu/arm7/lpc210x.h
+++ b/src/devices/cpu/arm7/lpc210x.h
@@ -23,47 +23,47 @@ class lpc210x_device : public arm7_cpu_device
public:
lpc210x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t);
- DECLARE_READ32_MEMBER(arm_E01FC088_r);
- DECLARE_READ32_MEMBER(flash_r);
- DECLARE_WRITE32_MEMBER(flash_w);
+ uint32_t arm_E01FC088_r();
+ uint32_t flash_r(offs_t offset);
+ void flash_w(offs_t offset, uint32_t data);
// timer 0 / 1
- DECLARE_READ32_MEMBER(timer0_r) { return read_timer(space, 0, offset, mem_mask); }
- DECLARE_WRITE32_MEMBER(timer0_w) { write_timer(space, 0, offset, data, mem_mask); }
+ uint32_t timer0_r(offs_t offset, uint32_t mem_mask = ~0) { return read_timer(0, offset, mem_mask); }
+ void timer0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { write_timer(0, offset, data, mem_mask); }
- DECLARE_READ32_MEMBER(timer1_r) { return read_timer(space, 1, offset, mem_mask); }
- DECLARE_WRITE32_MEMBER(timer1_w) { write_timer(space, 1, offset, data, mem_mask); }
+ uint32_t timer1_r(offs_t offset, uint32_t mem_mask = ~0) { return read_timer(1, offset, mem_mask); }
+ void timer1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { write_timer(1, offset, data, mem_mask); }
- void write_timer(address_space &space, int timer, int offset, uint32_t data, uint32_t mem_mask);
- uint32_t read_timer(address_space &space, int timer, int offset, uint32_t mem_mask);
+ void write_timer(int timer, int offset, uint32_t data, uint32_t mem_mask);
+ uint32_t read_timer(int timer, int offset, uint32_t mem_mask);
// VIC
- DECLARE_READ32_MEMBER(vic_r);
- DECLARE_WRITE32_MEMBER(vic_w);
+ uint32_t vic_r(offs_t offset, uint32_t mem_mask = ~0);
+ void vic_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
// PIN select block
- DECLARE_READ32_MEMBER(pin_r);
- DECLARE_WRITE32_MEMBER(pin_w);
+ uint32_t pin_r(offs_t offset, uint32_t mem_mask = ~0);
+ void pin_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
//PLL Phase Locked Loop
- DECLARE_READ32_MEMBER(pll_r);
- DECLARE_WRITE32_MEMBER(pll_w);
+ uint32_t pll_r(offs_t offset, uint32_t mem_mask = ~0);
+ void pll_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
//MAM memory controller
- DECLARE_READ32_MEMBER(mam_r);
- DECLARE_WRITE32_MEMBER(mam_w);
+ uint32_t mam_r(offs_t offset, uint32_t mem_mask = ~0);
+ void mam_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
//APB divider
- DECLARE_READ32_MEMBER(apbdiv_r);
- DECLARE_WRITE32_MEMBER(apbdiv_w);
+ uint32_t apbdiv_r(offs_t offset, uint32_t mem_mask = ~0);
+ void apbdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
//syscon misc
- DECLARE_READ32_MEMBER(scs_r);
- DECLARE_WRITE32_MEMBER(scs_w);
+ uint32_t scs_r(offs_t offset, uint32_t mem_mask = ~0);
+ void scs_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
// fio
- DECLARE_READ32_MEMBER(fio_r);
- DECLARE_WRITE32_MEMBER(fio_w);
+ uint32_t fio_r(offs_t offset, uint32_t mem_mask = ~0);
+ void fio_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
// todo, use an appropriate flash type instead
uint8_t m_flash[0x8000]; // needs to be public because the harmony/melody device injects contents with memcpy, yuck
diff --git a/src/devices/cpu/dsp16/dsp16.cpp b/src/devices/cpu/dsp16/dsp16.cpp
index 778d2efb701..bd9003fb9b6 100644
--- a/src/devices/cpu/dsp16/dsp16.cpp
+++ b/src/devices/cpu/dsp16/dsp16.cpp
@@ -130,7 +130,7 @@ WRITE_LINE_MEMBER(dsp16_device_base::exm_w)
high-level passive parallel I/O handlers
***********************************************************************/
-READ16_MEMBER(dsp16_device_base::pio_r)
+u16 dsp16_device_base::pio_r()
{
if (!pio_pods_active())
{
@@ -148,7 +148,7 @@ READ16_MEMBER(dsp16_device_base::pio_r)
}
}
-WRITE16_MEMBER(dsp16_device_base::pio_w)
+void dsp16_device_base::pio_w(u16 data)
{
if (!pio_pids_active())
{
@@ -639,7 +639,7 @@ dsp16_disassembler::cpu::predicate dsp16_device_base::check_branch(offs_t pc) co
return predicate::INDETERMINATE;
}
-template <offs_t Base> READ16_MEMBER(dsp16_device_base::external_memory_r)
+template <offs_t Base> u16 dsp16_device_base::external_memory_r(offs_t offset, u16 mem_mask)
{
return m_spaces[AS_IO]->read_word(Base + offset, mem_mask);
}
@@ -2092,7 +2092,7 @@ void dsp16_device::external_memory_enable(address_space &space, bool enable)
// this assumes internal ROM is mirrored above 2KiB, but actual hardware behaviour is unknown
space.unmap_read(0x0000, 0xffff);
if (enable)
- space.install_read_handler(0x0000, 0xffff, read16_delegate(*this, FUNC(dsp16_device::external_memory_r<0x0000>)));
+ space.install_read_handler(0x0000, 0xffff, read16s_delegate(*this, FUNC(dsp16_device::external_memory_r<0x0000>)));
else
space.install_rom(0x0000, 0x07ff, 0xf800, &m_rom[0]);
}
@@ -2123,12 +2123,12 @@ void dsp16a_device::external_memory_enable(address_space &space, bool enable)
space.unmap_read(0x0000, 0xffff);
if (enable)
{
- space.install_read_handler(0x0000, 0xffff, read16_delegate(*this, FUNC(dsp16a_device::external_memory_r<0x0000>)));
+ space.install_read_handler(0x0000, 0xffff, read16s_delegate(*this, FUNC(dsp16a_device::external_memory_r<0x0000>)));
}
else
{
space.install_rom(0x0000, 0x0fff, &m_rom[0]);
- space.install_read_handler(0x1000, 0xffff, read16_delegate(*this, FUNC(dsp16a_device::external_memory_r<0x1000>)));
+ space.install_read_handler(0x1000, 0xffff, read16s_delegate(*this, FUNC(dsp16a_device::external_memory_r<0x1000>)));
}
}
diff --git a/src/devices/cpu/dsp16/dsp16.h b/src/devices/cpu/dsp16/dsp16.h
index 5cc6c6a67f2..3f7ae66dd53 100644
--- a/src/devices/cpu/dsp16/dsp16.h
+++ b/src/devices/cpu/dsp16/dsp16.h
@@ -55,8 +55,8 @@ public:
DECLARE_READ_LINE_MEMBER(ose_r) { return m_ose_out; }
// high-level passive parallel I/O handlers
- DECLARE_READ16_MEMBER(pio_r);
- DECLARE_WRITE16_MEMBER(pio_w);
+ u16 pio_r();
+ void pio_w(u16 data);
// parallel I/O outputs
DECLARE_READ_LINE_MEMBER(psel_r) { return m_psel_out; }
@@ -105,7 +105,7 @@ protected:
// for specialisations to override
virtual void external_memory_enable(address_space &space, bool enable) = 0;
- template <offs_t Base> DECLARE_READ16_MEMBER(external_memory_r);
+ template <offs_t Base> u16 external_memory_r(offs_t offset, u16 mem_mask = ~0);
private:
// state registration indices
diff --git a/src/devices/cpu/dsp56156/dsp56156.h b/src/devices/cpu/dsp56156/dsp56156.h
index 09801c54407..cc8ebe6741d 100644
--- a/src/devices/cpu/dsp56156/dsp56156.h
+++ b/src/devices/cpu/dsp56156/dsp56156.h
@@ -205,10 +205,10 @@ class dsp56156_device : public cpu_device
public:
dsp56156_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
- DECLARE_READ16_MEMBER( peripheral_register_r );
- DECLARE_WRITE16_MEMBER( peripheral_register_w );
+ uint16_t peripheral_register_r(offs_t offset);
+ void peripheral_register_w(offs_t offset, uint16_t data);
- void host_interface_write(uint8_t offset, uint8_t data);
+ void host_interface_write(uint8_t offset, uint8_t data);
uint8_t host_interface_read(uint8_t offset);
uint16_t get_peripheral_memory(uint16_t addr);
diff --git a/src/devices/cpu/dsp56156/dsp56mem.cpp b/src/devices/cpu/dsp56156/dsp56mem.cpp
index 37e249f15ca..9f61089b9b4 100644
--- a/src/devices/cpu/dsp56156/dsp56mem.cpp
+++ b/src/devices/cpu/dsp56156/dsp56mem.cpp
@@ -487,7 +487,7 @@ void dsp56156_io_reset(dsp56156_core* cpustate)
/* Work */
-READ16_MEMBER( dsp56156_device::peripheral_register_r )
+uint16_t dsp56156_device::peripheral_register_r(offs_t offset)
{
dsp56156_core* cpustate = &m_core;
// (printf) cpustate->device->logerror("Peripheral read 0x%04x\n", O2A(offset));
@@ -621,7 +621,7 @@ READ16_MEMBER( dsp56156_device::peripheral_register_r )
return cpustate->peripheral_ram[offset];
}
-WRITE16_MEMBER( dsp56156_device::peripheral_register_w )
+void dsp56156_device::peripheral_register_w(offs_t offset, uint16_t data)
{
dsp56156_core* cpustate = &m_core;
diff --git a/src/devices/cpu/dspp/dspp.cpp b/src/devices/cpu/dspp/dspp.cpp
index d4f889df01a..dded3f028f9 100644
--- a/src/devices/cpu/dspp/dspp.cpp
+++ b/src/devices/cpu/dspp/dspp.cpp
@@ -1638,7 +1638,7 @@ void dspp_device::reset_channel(int32_t channel)
// input_r - Read digital input
//-------------------------------------------------
-READ16_MEMBER( dspp_device::input_r )
+uint16_t dspp_device::input_r()
{
// TODO
return 0;
@@ -1649,7 +1649,7 @@ READ16_MEMBER( dspp_device::input_r )
// output_w - Write to the 8 output registers
//-------------------------------------------------
-WRITE16_MEMBER( dspp_device::output_w )
+void dspp_device::output_w(offs_t offset, uint16_t data)
{
m_outputs[offset] = data;
}
@@ -1659,7 +1659,7 @@ WRITE16_MEMBER( dspp_device::output_w )
// fifo_osc_r -
//-------------------------------------------------
-READ16_MEMBER( dspp_device::fifo_osc_r )
+uint16_t dspp_device::fifo_osc_r(offs_t offset)
{
uint32_t data = 0;
uint32_t channel = offset / 8;
@@ -1729,7 +1729,7 @@ READ16_MEMBER( dspp_device::fifo_osc_r )
// fifo_osc_w -
//-------------------------------------------------
-WRITE16_MEMBER( dspp_device::fifo_osc_w )
+void dspp_device::fifo_osc_w(offs_t offset, uint16_t data)
{
uint32_t channel = offset / 8;
@@ -1785,7 +1785,7 @@ WRITE16_MEMBER( dspp_device::fifo_osc_w )
// input_control_w -
//-------------------------------------------------
-WRITE16_MEMBER( dspp_device::input_control_w )
+void dspp_device::input_control_w(uint16_t data)
{
// TODO
}
@@ -1795,7 +1795,7 @@ WRITE16_MEMBER( dspp_device::input_control_w )
// output_control_w -
//-------------------------------------------------
-WRITE16_MEMBER( dspp_device::output_control_w )
+void dspp_device::output_control_w(uint16_t data)
{
// TODO
if (data & 1)
@@ -1832,7 +1832,7 @@ WRITE16_MEMBER( dspp_device::output_control_w )
// input_status_r - Read input state
//-------------------------------------------------
-READ16_MEMBER( dspp_device::input_status_r )
+uint16_t dspp_device::input_status_r()
{
// TODO: How should this work?
return 1;
@@ -1844,7 +1844,7 @@ READ16_MEMBER( dspp_device::input_status_r )
// entries in the output FIFO
//-------------------------------------------------
-READ16_MEMBER( dspp_device::output_status_r )
+uint16_t dspp_device::output_status_r()
{
return m_output_fifo_count;
}
@@ -1854,7 +1854,7 @@ READ16_MEMBER( dspp_device::output_status_r )
// cpu_int_w - Host CPU soft interrupt
//-------------------------------------------------
-WRITE16_MEMBER( dspp_device::cpu_int_w )
+void dspp_device::cpu_int_w(uint16_t data)
{
m_core->m_partial_int |= (data << DSPX_FLD_INT_SOFT_SHIFT) & DSPX_FLD_INT_SOFT_MASK;
update_host_interrupt();
@@ -1865,7 +1865,7 @@ WRITE16_MEMBER( dspp_device::cpu_int_w )
// pc_r - Read program counter
//-------------------------------------------------
-READ16_MEMBER( dspp_device::pc_r )
+uint16_t dspp_device::pc_r()
{
return m_core->m_pc;
}
@@ -1875,7 +1875,7 @@ READ16_MEMBER( dspp_device::pc_r )
// pc_w - Write program counter
//-------------------------------------------------
-WRITE16_MEMBER(dspp_device:: pc_w )
+void dspp_device::pc_w(uint16_t data)
{
m_core->m_pc = data;
}
@@ -1885,7 +1885,7 @@ WRITE16_MEMBER(dspp_device:: pc_w )
// audlock_r - Read Audio Lock status
//-------------------------------------------------
-READ16_MEMBER( dspp_device::audlock_r )
+uint16_t dspp_device::audlock_r()
{
return m_core->m_flag_audlock;
}
@@ -1895,7 +1895,7 @@ READ16_MEMBER( dspp_device::audlock_r )
// audlock_w - Write Audio Lock status
//-------------------------------------------------
-WRITE16_MEMBER( dspp_device::audlock_w )
+void dspp_device::audlock_w(uint16_t data)
{
m_core->m_flag_audlock = data & 1;
}
@@ -1905,7 +1905,7 @@ WRITE16_MEMBER( dspp_device::audlock_w )
// clock_r - Read CPU tick counter
//-------------------------------------------------
-READ16_MEMBER( dspp_device::clock_r )
+uint16_t dspp_device::clock_r()
{
return m_core->m_tclock;
}
@@ -1915,7 +1915,7 @@ READ16_MEMBER( dspp_device::clock_r )
// clock_w - Write CPU tick counter
//-------------------------------------------------
-WRITE16_MEMBER( dspp_device::clock_w )
+void dspp_device::clock_w(uint16_t data)
{
m_core->m_tclock = data;
}
@@ -1925,7 +1925,7 @@ WRITE16_MEMBER( dspp_device::clock_w )
// noise_r - PRNG noise
//-------------------------------------------------
-READ16_MEMBER( dspp_device::noise_r )
+uint16_t dspp_device::noise_r()
{
// TODO: Obviously this isn't accurate
return machine().rand();
@@ -2334,7 +2334,7 @@ void dspp_device::write_ext_control(offs_t offset, uint32_t data)
// read - host CPU read from DSPP internals
//-------------------------------------------------
-READ32_MEMBER( dspp_device::read )
+uint32_t dspp_device::read(offs_t offset)
{
if (offset < 0x1000/4)
{
@@ -2495,7 +2495,7 @@ void dspp_device::write_dma_stack(offs_t offset, uint32_t data)
// write - host CPU write to DSPP internals
//-------------------------------------------------
-WRITE32_MEMBER( dspp_device::write )
+void dspp_device::write(offs_t offset, uint32_t data)
{
if (offset < 0x1000/4)
{
diff --git a/src/devices/cpu/dspp/dspp.h b/src/devices/cpu/dspp/dspp.h
index 493c88d8ef0..68492fb7f40 100644
--- a/src/devices/cpu/dspp/dspp.h
+++ b/src/devices/cpu/dspp/dspp.h
@@ -41,30 +41,30 @@ public:
auto dma_write_handler() { return m_dma_write_handler.bind(); }
// Public interfaces
- DECLARE_READ32_MEMBER( read );
- DECLARE_WRITE32_MEMBER( write );
+ uint32_t read(offs_t offset);
+ void write(offs_t offset, uint32_t data);
uint16_t read_output_fifo();
void dump_state(); // TODO: DEBUG REMOVE ME
// Internal registers
- DECLARE_READ16_MEMBER( input_r );
- DECLARE_WRITE16_MEMBER( output_w );
- DECLARE_READ16_MEMBER( fifo_osc_r );
- DECLARE_WRITE16_MEMBER( fifo_osc_w );
- DECLARE_WRITE16_MEMBER( input_control_w );
- DECLARE_WRITE16_MEMBER( output_control_w );
- DECLARE_READ16_MEMBER( input_status_r );
- DECLARE_READ16_MEMBER( output_status_r );
- DECLARE_WRITE16_MEMBER( cpu_int_w );
- DECLARE_READ16_MEMBER( pc_r );
- DECLARE_WRITE16_MEMBER( pc_w );
- DECLARE_READ16_MEMBER( audlock_r );
- DECLARE_WRITE16_MEMBER( audlock_w );
- DECLARE_READ16_MEMBER( clock_r );
- DECLARE_WRITE16_MEMBER( clock_w );
- DECLARE_READ16_MEMBER( noise_r );
+ uint16_t input_r();
+ void output_w(offs_t offset, uint16_t data);
+ uint16_t fifo_osc_r(offs_t offset);
+ void fifo_osc_w(offs_t offset, uint16_t data);
+ void input_control_w(uint16_t data);
+ void output_control_w(uint16_t data);
+ uint16_t input_status_r();
+ uint16_t output_status_r();
+ void cpu_int_w(uint16_t data);
+ uint16_t pc_r();
+ void pc_w(uint16_t data);
+ uint16_t audlock_r();
+ void audlock_w(uint16_t data);
+ uint16_t clock_r();
+ void clock_w(uint16_t data);
+ uint16_t noise_r();
void update_fifo_dma();
void print_sums() { printf("%04x: %04x\n", (uint16_t)m_core->m_arg0, (uint16_t)m_core->m_arg1); }
diff --git a/src/devices/cpu/h8/h83002.cpp b/src/devices/cpu/h8/h83002.cpp
index f9b52dc43eb..ec385878f1d 100644
--- a/src/devices/cpu/h8/h83002.cpp
+++ b/src/devices/cpu/h8/h83002.cpp
@@ -251,25 +251,25 @@ void h83002_device::device_reset()
syscr = 0x09;
}
-READ8_MEMBER(h83002_device::syscr_r)
+uint8_t h83002_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h83002_device::syscr_w)
+void h83002_device::syscr_w(uint8_t data)
{
syscr = data;
update_irq_filter();
logerror("syscr = %02x\n", data);
}
-READ8_MEMBER(h83002_device::rtmcsr_r)
+uint8_t h83002_device::rtmcsr_r()
{
// set bit 7 -- Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR values have matched.
return rtmcsr | 0x80;
}
-WRITE8_MEMBER(h83002_device::rtmcsr_w)
+void h83002_device::rtmcsr_w(uint8_t data)
{
rtmcsr = data;
logerror("rtmcsr = %02x\n", data);
diff --git a/src/devices/cpu/h8/h83002.h b/src/devices/cpu/h8/h83002.h
index 304ca673c67..94c1d603230 100644
--- a/src/devices/cpu/h8/h83002.h
+++ b/src/devices/cpu/h8/h83002.h
@@ -35,11 +35,11 @@ public:
void set_mode_a20() { mode_a20 = true; }
void set_mode_a24() { mode_a20 = false; }
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
- DECLARE_READ8_MEMBER(rtmcsr_r);
- DECLARE_WRITE8_MEMBER(rtmcsr_w);
+ uint8_t rtmcsr_r();
+ void rtmcsr_w(uint8_t data);
protected:
required_device<h8h_intc_device> intc;
diff --git a/src/devices/cpu/h8/h83003.cpp b/src/devices/cpu/h8/h83003.cpp
index 79129043b88..c7861618208 100644
--- a/src/devices/cpu/h8/h83003.cpp
+++ b/src/devices/cpu/h8/h83003.cpp
@@ -269,25 +269,25 @@ void h83003_device::device_reset()
syscr = 0x09;
}
-READ8_MEMBER(h83003_device::syscr_r)
+uint8_t h83003_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h83003_device::syscr_w)
+void h83003_device::syscr_w(uint8_t data)
{
syscr = data;
update_irq_filter();
logerror("syscr = %02x\n", data);
}
-READ8_MEMBER(h83003_device::rtmcsr_r)
+uint8_t h83003_device::rtmcsr_r()
{
// set bit 7 -- Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR values have matched.
return rtmcsr | 0x80;
}
-WRITE8_MEMBER(h83003_device::rtmcsr_w)
+void h83003_device::rtmcsr_w(uint8_t data)
{
rtmcsr = data;
logerror("rtmcsr = %02x\n", data);
diff --git a/src/devices/cpu/h8/h83003.h b/src/devices/cpu/h8/h83003.h
index f988f0301cd..6c4f7cfaced 100644
--- a/src/devices/cpu/h8/h83003.h
+++ b/src/devices/cpu/h8/h83003.h
@@ -35,11 +35,11 @@ public:
void set_mode_a20() { mode_a20 = true; }
void set_mode_a24() { mode_a20 = false; }
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
- DECLARE_READ8_MEMBER(rtmcsr_r);
- DECLARE_WRITE8_MEMBER(rtmcsr_w);
+ uint8_t rtmcsr_r();
+ void rtmcsr_w(uint8_t data);
protected:
required_device<h8h_intc_device> intc;
diff --git a/src/devices/cpu/h8/h83006.cpp b/src/devices/cpu/h8/h83006.cpp
index 9a3d96e4773..d19937e93dc 100644
--- a/src/devices/cpu/h8/h83006.cpp
+++ b/src/devices/cpu/h8/h83006.cpp
@@ -242,12 +242,12 @@ void h83006_device::device_reset()
}
-READ8_MEMBER(h83006_device::syscr_r)
+uint8_t h83006_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h83006_device::syscr_w)
+void h83006_device::syscr_w(uint8_t data)
{
syscr = data;
update_irq_filter();
diff --git a/src/devices/cpu/h8/h83006.h b/src/devices/cpu/h8/h83006.h
index 37ff4029476..083b91ea664 100644
--- a/src/devices/cpu/h8/h83006.h
+++ b/src/devices/cpu/h8/h83006.h
@@ -32,8 +32,8 @@ public:
void set_mode_a20() { mode_a20 = true; }
void set_mode_a24() { mode_a20 = false; }
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
protected:
h83006_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start);
diff --git a/src/devices/cpu/h8/h83008.cpp b/src/devices/cpu/h8/h83008.cpp
index b433f28be06..3db7c5a71aa 100644
--- a/src/devices/cpu/h8/h83008.cpp
+++ b/src/devices/cpu/h8/h83008.cpp
@@ -218,12 +218,12 @@ void h83008_device::device_reset()
}
-READ8_MEMBER(h83008_device::syscr_r)
+uint8_t h83008_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h83008_device::syscr_w)
+void h83008_device::syscr_w(uint8_t data)
{
syscr = data;
update_irq_filter();
diff --git a/src/devices/cpu/h8/h83008.h b/src/devices/cpu/h8/h83008.h
index cdab99bd950..bb65adfcc9d 100644
--- a/src/devices/cpu/h8/h83008.h
+++ b/src/devices/cpu/h8/h83008.h
@@ -32,8 +32,8 @@ public:
void set_mode_a20() { mode_a20 = true; }
void set_mode_a24() { mode_a20 = false; }
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
protected:
required_device<h8h_intc_device> intc;
diff --git a/src/devices/cpu/h8/h83048.cpp b/src/devices/cpu/h8/h83048.cpp
index d90f690a4b6..2358914e6cf 100644
--- a/src/devices/cpu/h8/h83048.cpp
+++ b/src/devices/cpu/h8/h83048.cpp
@@ -255,12 +255,12 @@ void h83048_device::device_reset()
syscr = 0x0b;
}
-READ8_MEMBER(h83048_device::syscr_r)
+uint8_t h83048_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h83048_device::syscr_w)
+void h83048_device::syscr_w(uint8_t data)
{
syscr = data;
update_irq_filter();
diff --git a/src/devices/cpu/h8/h83048.h b/src/devices/cpu/h8/h83048.h
index 6876a909c2d..d5afb5e67c8 100644
--- a/src/devices/cpu/h8/h83048.h
+++ b/src/devices/cpu/h8/h83048.h
@@ -37,8 +37,8 @@ public:
void set_mode_a20() { mode_a20 = true; }
void set_mode_a24() { mode_a20 = false; }
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
protected:
h83048_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start);
diff --git a/src/devices/cpu/h8/h83337.cpp b/src/devices/cpu/h8/h83337.cpp
index b3a386835f3..7f9e835513c 100644
--- a/src/devices/cpu/h8/h83337.cpp
+++ b/src/devices/cpu/h8/h83337.cpp
@@ -186,45 +186,45 @@ void h83337_device::device_reset()
syscr = 0x09;
}
-READ8_MEMBER(h83337_device::syscr_r)
+uint8_t h83337_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h83337_device::syscr_w)
+void h83337_device::syscr_w(uint8_t data)
{
syscr = data;
logerror("syscr = %02x\n", data);
}
-READ8_MEMBER(h83337_device::wscr_r)
+uint8_t h83337_device::wscr_r()
{
return 0x00;
}
-WRITE8_MEMBER(h83337_device::wscr_w)
+void h83337_device::wscr_w(uint8_t data)
{
logerror("wscr = %02x\n", data);
}
-READ8_MEMBER(h83337_device::stcr_r)
+uint8_t h83337_device::stcr_r()
{
return 0x00;
}
-WRITE8_MEMBER(h83337_device::stcr_w)
+void h83337_device::stcr_w(uint8_t data)
{
logerror("stcr = %02x\n", data);
timer8_0->set_extra_clock_bit(data & 0x01);
timer8_1->set_extra_clock_bit(data & 0x02);
}
-READ8_MEMBER(h83337_device::mdcr_r)
+uint8_t h83337_device::mdcr_r()
{
return 0x00;
}
-WRITE8_MEMBER(h83337_device::mdcr_w)
+void h83337_device::mdcr_w(uint8_t data)
{
logerror("mdcr = %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h83337.h b/src/devices/cpu/h8/h83337.h
index 0882e623f80..cc0d9735a34 100644
--- a/src/devices/cpu/h8/h83337.h
+++ b/src/devices/cpu/h8/h83337.h
@@ -36,14 +36,14 @@ class h83337_device : public h8_device {
public:
h83337_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ8_MEMBER(wscr_r);
- DECLARE_WRITE8_MEMBER(wscr_w);
- DECLARE_READ8_MEMBER(stcr_r);
- DECLARE_WRITE8_MEMBER(stcr_w);
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
- DECLARE_READ8_MEMBER(mdcr_r);
- DECLARE_WRITE8_MEMBER(mdcr_w);
+ uint8_t wscr_r();
+ void wscr_w(uint8_t data);
+ uint8_t stcr_r();
+ void stcr_w(uint8_t data);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
+ uint8_t mdcr_r();
+ void mdcr_w(uint8_t data);
protected:
h83337_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start);
diff --git a/src/devices/cpu/h8/h8_adc.cpp b/src/devices/cpu/h8/h8_adc.cpp
index 76b03584e6d..3235ac8c6c8 100644
--- a/src/devices/cpu/h8/h8_adc.cpp
+++ b/src/devices/cpu/h8/h8_adc.cpp
@@ -31,31 +31,31 @@ void h8_adc_device::set_info(const char *_intc_tag, int _intc_vector)
intc_vector = _intc_vector;
}
-READ8_MEMBER(h8_adc_device::addr8_r)
+uint8_t h8_adc_device::addr8_r(offs_t offset)
{
if(V>=1) logerror("addr8_r %d %03x\n", offset, addr[offset >> 1]);
return offset & 1 ? addr[offset >> 1] << 6 : addr[offset >> 1] >> 2;
}
-READ16_MEMBER(h8_adc_device::addr16_r)
+uint16_t h8_adc_device::addr16_r(offs_t offset)
{
if(V>=1) logerror("addr16_r %d %03x\n", offset, addr[offset]);
return addr[offset];
}
-READ8_MEMBER(h8_adc_device::adcsr_r)
+uint8_t h8_adc_device::adcsr_r()
{
if(V>=1) logerror("adcsr_r %02x\n", adcsr);
return adcsr;
}
-READ8_MEMBER(h8_adc_device::adcr_r)
+uint8_t h8_adc_device::adcr_r()
{
if(V>=1) logerror("adcr_r %02x\n", adcr);
return adcr;
}
-WRITE8_MEMBER(h8_adc_device::adcsr_w)
+void h8_adc_device::adcsr_w(uint8_t data)
{
if(V>=1) logerror("adcsr_w %02x\n", data);
uint8_t prev = adcsr;
@@ -76,7 +76,7 @@ WRITE8_MEMBER(h8_adc_device::adcsr_w)
start_conversion();
}
-WRITE8_MEMBER(h8_adc_device::adcr_w)
+void h8_adc_device::adcr_w(uint8_t data)
{
if(V>=1) logerror("adcr_w %02x\n", data);
adcr = data;
diff --git a/src/devices/cpu/h8/h8_adc.h b/src/devices/cpu/h8/h8_adc.h
index f0feb82f213..e54d3b747d9 100644
--- a/src/devices/cpu/h8/h8_adc.h
+++ b/src/devices/cpu/h8/h8_adc.h
@@ -21,12 +21,12 @@ class h8_adc_device : public device_t {
public:
void set_info(const char *intc_tag, int vect);
- DECLARE_READ8_MEMBER(addr8_r);
- DECLARE_READ16_MEMBER(addr16_r);
- DECLARE_READ8_MEMBER(adcsr_r);
- DECLARE_READ8_MEMBER(adcr_r);
- DECLARE_WRITE8_MEMBER(adcsr_w);
- DECLARE_WRITE8_MEMBER(adcr_w);
+ uint8_t addr8_r(offs_t offset);
+ uint16_t addr16_r(offs_t offset);
+ uint8_t adcsr_r();
+ uint8_t adcr_r();
+ void adcsr_w(uint8_t data);
+ void adcr_w(uint8_t data);
DECLARE_WRITE_LINE_MEMBER(adtrg_w);
void set_suspend(bool suspend);
diff --git a/src/devices/cpu/h8/h8_dma.cpp b/src/devices/cpu/h8/h8_dma.cpp
index 20f034d63e0..c295b77f330 100644
--- a/src/devices/cpu/h8/h8_dma.cpp
+++ b/src/devices/cpu/h8/h8_dma.cpp
@@ -74,37 +74,37 @@ void h8_dma_device::set_input(int inputnum, int state)
logerror("input line %d not supported for h8_dma_device\n", inputnum);
}
-READ8_MEMBER(h8_dma_device::dmawer_r)
+uint8_t h8_dma_device::dmawer_r()
{
logerror("dmawer_r %02x\n", dmawer);
return dmawer;
}
-WRITE8_MEMBER(h8_dma_device::dmawer_w)
+void h8_dma_device::dmawer_w(uint8_t data)
{
dmawer = data;
logerror("dmawer_w %02x\n", data);
}
-READ8_MEMBER(h8_dma_device::dmatcr_r)
+uint8_t h8_dma_device::dmatcr_r()
{
logerror("dmatcr_r %02x\n", dmatcr);
return dmatcr;
}
-WRITE8_MEMBER(h8_dma_device::dmatcr_w)
+void h8_dma_device::dmatcr_w(uint8_t data)
{
dmatcr = data;
logerror("dmatcr_w %02x\n", data);
}
-READ16_MEMBER(h8_dma_device::dmabcr_r)
+uint16_t h8_dma_device::dmabcr_r()
{
logerror("dmabcr_r %04x\n", dmabcr);
return dmabcr;
}
-WRITE16_MEMBER(h8_dma_device::dmabcr_w)
+void h8_dma_device::dmabcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&dmabcr);
logerror("dmabcr_w %04x\n", dmabcr);
@@ -164,111 +164,111 @@ void h8_dma_channel_device::set_id(int id)
state[1].id = id | 1;
}
-READ16_MEMBER(h8_dma_channel_device::marah_r)
+uint16_t h8_dma_channel_device::marah_r()
{
logerror("marah_r %06x\n", mar[0]);
return mar[0] >> 16;
}
-WRITE16_MEMBER(h8_dma_channel_device::marah_w)
+void h8_dma_channel_device::marah_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if(ACCESSING_BITS_0_7)
mar[0] = ((data & 0x00ff) << 16) | (mar[0] & 0xffff);
logerror("marah_w %06x\n", mar[0]);
}
-READ16_MEMBER(h8_dma_channel_device::maral_r)
+uint16_t h8_dma_channel_device::maral_r()
{
logerror("maral_r %06x\n", mar[0]);
return mar[0];
}
-WRITE16_MEMBER(h8_dma_channel_device::maral_w)
+void h8_dma_channel_device::maral_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
mar[0] = (mar[0] & ~mem_mask) | (data & mem_mask);
logerror("maral_w %06x\n", mar[0]);
}
-READ16_MEMBER(h8_dma_channel_device::ioara_r)
+uint16_t h8_dma_channel_device::ioara_r()
{
logerror("iorar_r %04x\n", ioar[0]);
return ioar[0];
}
-WRITE16_MEMBER(h8_dma_channel_device::ioara_w)
+void h8_dma_channel_device::ioara_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&ioar[0]);
logerror("ioara_w %04x\n", ioar[0]);
}
-READ16_MEMBER(h8_dma_channel_device::etcra_r)
+uint16_t h8_dma_channel_device::etcra_r()
{
logerror("etcra_r %04x\n", etcr[0]);
return etcr[0];
}
-WRITE16_MEMBER(h8_dma_channel_device::etcra_w)
+void h8_dma_channel_device::etcra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&etcr[0]);
logerror("etcra_w %04x\n", etcr[0]);
}
-READ16_MEMBER(h8_dma_channel_device::marbh_r)
+uint16_t h8_dma_channel_device::marbh_r()
{
logerror("marbh_r %06x\n", mar[1]);
return mar[1] >> 16;
}
-WRITE16_MEMBER(h8_dma_channel_device::marbh_w)
+void h8_dma_channel_device::marbh_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if(ACCESSING_BITS_0_7)
mar[1] = ((data & 0x00ff) << 16) | (mar[1] & 0xffff);
logerror("marbh_w %06x\n", mar[1]);
}
-READ16_MEMBER(h8_dma_channel_device::marbl_r)
+uint16_t h8_dma_channel_device::marbl_r()
{
logerror("marbl_r %06x\n", mar[1]);
return mar[1];
}
-WRITE16_MEMBER(h8_dma_channel_device::marbl_w)
+void h8_dma_channel_device::marbl_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
mar[1] = (mar[1] & ~mem_mask) | (data & mem_mask);
logerror("marbl_w %06x\n", mar[1]);
}
-READ16_MEMBER(h8_dma_channel_device::ioarb_r)
+uint16_t h8_dma_channel_device::ioarb_r()
{
logerror("ioarb_r %04x\n", ioar[1]);
return ioar[1];
}
-WRITE16_MEMBER(h8_dma_channel_device::ioarb_w)
+void h8_dma_channel_device::ioarb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&ioar[1]);
logerror("ioarb_w %04x\n", ioar[1]);
}
-READ16_MEMBER(h8_dma_channel_device::etcrb_r)
+uint16_t h8_dma_channel_device::etcrb_r()
{
logerror("etcrb_r %04x\n", etcr[1]);
return etcr[1];
}
-WRITE16_MEMBER(h8_dma_channel_device::etcrb_w)
+void h8_dma_channel_device::etcrb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&etcr[1]);
logerror("etcrb_w %04x\n", etcr[1]);
}
-READ16_MEMBER(h8_dma_channel_device::dmacr_r)
+uint16_t h8_dma_channel_device::dmacr_r()
{
logerror("dmacr_r %04x\n", dmacr);
return dmacr;
}
-WRITE16_MEMBER(h8_dma_channel_device::dmacr_w)
+void h8_dma_channel_device::dmacr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&dmacr);
logerror("dmacr_w %04x\n", dmacr);
@@ -276,13 +276,13 @@ WRITE16_MEMBER(h8_dma_channel_device::dmacr_w)
}
// H8H DMA
-READ8_MEMBER(h8_dma_channel_device::dtcra_r)
+uint8_t h8_dma_channel_device::dtcra_r()
{
logerror("dtcra_r %02x\n", dtcr[0]);
return dtcr[0];
}
-WRITE8_MEMBER(h8_dma_channel_device::dtcra_w)
+void h8_dma_channel_device::dtcra_w(uint8_t data)
{
dtcr[0] = data;
logerror("dtcra_w %02x\n", dtcr[0]);
@@ -291,13 +291,13 @@ WRITE8_MEMBER(h8_dma_channel_device::dtcra_w)
}
}
-READ8_MEMBER(h8_dma_channel_device::dtcrb_r)
+uint8_t h8_dma_channel_device::dtcrb_r()
{
logerror("dtcrb_r %02x\n", dtcr[1]);
return dtcr[1];
}
-WRITE8_MEMBER(h8_dma_channel_device::dtcrb_w)
+void h8_dma_channel_device::dtcrb_w(uint8_t data)
{
dtcr[1] = data;
logerror("dtcrb_w %02x\n", dtcr[1]);
diff --git a/src/devices/cpu/h8/h8_dma.h b/src/devices/cpu/h8/h8_dma.h
index d244f53ebd1..72d33105349 100644
--- a/src/devices/cpu/h8/h8_dma.h
+++ b/src/devices/cpu/h8/h8_dma.h
@@ -45,12 +45,12 @@ class h8_dma_device : public device_t {
public:
h8_dma_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
- DECLARE_READ8_MEMBER(dmawer_r);
- DECLARE_WRITE8_MEMBER(dmawer_w);
- DECLARE_READ8_MEMBER(dmatcr_r);
- DECLARE_WRITE8_MEMBER(dmatcr_w);
- DECLARE_READ16_MEMBER(dmabcr_r);
- DECLARE_WRITE16_MEMBER(dmabcr_w);
+ uint8_t dmawer_r();
+ void dmawer_w(uint8_t data);
+ uint8_t dmatcr_r();
+ void dmatcr_w(uint8_t data);
+ uint16_t dmabcr_r();
+ void dmabcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
bool trigger_dma(int vector);
void count_last(int id);
@@ -104,30 +104,30 @@ public:
}
void set_info(const char *intc, int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf);
- DECLARE_READ16_MEMBER(marah_r);
- DECLARE_WRITE16_MEMBER(marah_w);
- DECLARE_READ16_MEMBER(maral_r);
- DECLARE_WRITE16_MEMBER(maral_w);
- DECLARE_READ16_MEMBER(ioara_r);
- DECLARE_WRITE16_MEMBER(ioara_w);
- DECLARE_READ16_MEMBER(etcra_r);
- DECLARE_WRITE16_MEMBER(etcra_w);
- DECLARE_READ16_MEMBER(marbh_r);
- DECLARE_WRITE16_MEMBER(marbh_w);
- DECLARE_READ16_MEMBER(marbl_r);
- DECLARE_WRITE16_MEMBER(marbl_w);
- DECLARE_READ16_MEMBER(ioarb_r);
- DECLARE_WRITE16_MEMBER(ioarb_w);
- DECLARE_READ16_MEMBER(etcrb_r);
- DECLARE_WRITE16_MEMBER(etcrb_w);
- DECLARE_READ16_MEMBER(dmacr_r);
- DECLARE_WRITE16_MEMBER(dmacr_w);
+ uint16_t marah_r();
+ void marah_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t maral_r();
+ void maral_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t ioara_r();
+ void ioara_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t etcra_r();
+ void etcra_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t marbh_r();
+ void marbh_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t marbl_r();
+ void marbl_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t ioarb_r();
+ void ioarb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t etcrb_r();
+ void etcrb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t dmacr_r();
+ void dmacr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
// H8H DMA
- DECLARE_READ8_MEMBER(dtcra_r);
- DECLARE_WRITE8_MEMBER(dtcra_w);
- DECLARE_READ8_MEMBER(dtcrb_r);
- DECLARE_WRITE8_MEMBER(dtcrb_w);
+ uint8_t dtcra_r();
+ void dtcra_w(uint8_t data);
+ uint8_t dtcrb_r();
+ void dtcrb_w(uint8_t data);
void set_id(int id);
void set_bcr(bool fae, bool sae, uint8_t dta, uint8_t dte, uint8_t dtie);
diff --git a/src/devices/cpu/h8/h8_dtc.cpp b/src/devices/cpu/h8/h8_dtc.cpp
index f600b71c6a8..a2668456414 100644
--- a/src/devices/cpu/h8/h8_dtc.cpp
+++ b/src/devices/cpu/h8/h8_dtc.cpp
@@ -51,25 +51,25 @@ void h8_dtc_device::device_reset()
cur_active_vector = -1;
}
-READ8_MEMBER(h8_dtc_device::dtcer_r)
+uint8_t h8_dtc_device::dtcer_r(offs_t offset)
{
if(V>=2) logerror("dtcer_r %x, %02x\n", offset, dtcer[offset]);
return dtcer[offset];
}
-WRITE8_MEMBER(h8_dtc_device::dtcer_w)
+void h8_dtc_device::dtcer_w(offs_t offset, uint8_t data)
{
dtcer[offset] = data;
if(V>=2) logerror("dtcer_w %x, %02x\n", offset, data);
}
-READ8_MEMBER(h8_dtc_device::dtvecr_r)
+uint8_t h8_dtc_device::dtvecr_r()
{
if(V>=2) logerror("dtvecr_r %02x\n", dtvecr);
return dtvecr;
}
-WRITE8_MEMBER(h8_dtc_device::dtvecr_w)
+void h8_dtc_device::dtvecr_w(uint8_t data)
{
dtvecr = data;
if(V>=2) logerror("dtvecr_w %02x\n", data);
diff --git a/src/devices/cpu/h8/h8_dtc.h b/src/devices/cpu/h8/h8_dtc.h
index f3e33795190..6b1a32b8a9b 100644
--- a/src/devices/cpu/h8/h8_dtc.h
+++ b/src/devices/cpu/h8/h8_dtc.h
@@ -37,10 +37,10 @@ public:
}
void set_info(const char *intc, int irq);
- DECLARE_READ8_MEMBER(dtcer_r);
- DECLARE_WRITE8_MEMBER(dtcer_w);
- DECLARE_READ8_MEMBER(dtvecr_r);
- DECLARE_WRITE8_MEMBER(dtvecr_w);
+ uint8_t dtcer_r(offs_t offset);
+ void dtcer_w(offs_t offset, uint8_t data);
+ uint8_t dtvecr_r();
+ void dtvecr_w(uint8_t data);
bool trigger_dtc(int vector);
void count_done(int id);
diff --git a/src/devices/cpu/h8/h8_intc.cpp b/src/devices/cpu/h8/h8_intc.cpp
index 2dda3b5faa2..94e6e3fdad0 100644
--- a/src/devices/cpu/h8/h8_intc.cpp
+++ b/src/devices/cpu/h8/h8_intc.cpp
@@ -103,12 +103,12 @@ void h8_intc_device::set_filter(int _icr_filter, int _ipr_filter)
update_irq_state();
}
-READ8_MEMBER(h8_intc_device::ier_r)
+uint8_t h8_intc_device::ier_r()
{
return ier;
}
-WRITE8_MEMBER(h8_intc_device::ier_w)
+void h8_intc_device::ier_w(uint8_t data)
{
ier = data;
logerror("ier = %02x\n", data);
@@ -131,12 +131,12 @@ void h8_intc_device::check_level_irqs(bool force_update)
}
-READ8_MEMBER(h8_intc_device::iscr_r)
+uint8_t h8_intc_device::iscr_r()
{
return iscr;
}
-WRITE8_MEMBER(h8_intc_device::iscr_w)
+void h8_intc_device::iscr_w(uint8_t data)
{
iscr = data;
logerror("iscr = %02x\n", iscr);
@@ -216,57 +216,57 @@ void h8h_intc_device::device_reset()
icr = 0x000000;
}
-READ8_MEMBER(h8h_intc_device::isr_r)
+uint8_t h8h_intc_device::isr_r()
{
return isr;
}
-WRITE8_MEMBER(h8h_intc_device::isr_w)
+void h8h_intc_device::isr_w(uint8_t data)
{
isr &= data; // edge/level
logerror("isr = %02x / %02x\n", data, isr);
check_level_irqs(true);
}
-READ8_MEMBER(h8h_intc_device::icr_r)
+uint8_t h8h_intc_device::icr_r(offs_t offset)
{
return icr >> (8*offset);
}
-WRITE8_MEMBER(h8h_intc_device::icr_w)
+void h8h_intc_device::icr_w(offs_t offset, uint8_t data)
{
icr = (icr & (0xff << (8*offset))) | (data << (8*offset));
logerror("icr %d = %02x\n", offset, data);
}
-READ8_MEMBER(h8h_intc_device::icrc_r)
+uint8_t h8h_intc_device::icrc_r()
{
- return icr_r(space, 2, mem_mask);
+ return icr_r(2);
}
-WRITE8_MEMBER(h8h_intc_device::icrc_w)
+void h8h_intc_device::icrc_w(uint8_t data)
{
- icr_w(space, 2, data, mem_mask);
+ icr_w(2, data);
}
-READ8_MEMBER(h8h_intc_device::iscrh_r)
+uint8_t h8h_intc_device::iscrh_r()
{
return iscr >> 8;
}
-WRITE8_MEMBER(h8h_intc_device::iscrh_w)
+void h8h_intc_device::iscrh_w(uint8_t data)
{
iscr = (iscr & 0x00ff) | (data << 8);
logerror("iscr = %04x\n", iscr);
update_irq_types();
}
-READ8_MEMBER(h8h_intc_device::iscrl_r)
+uint8_t h8h_intc_device::iscrl_r()
{
return iscr;
}
-WRITE8_MEMBER(h8h_intc_device::iscrl_w)
+void h8h_intc_device::iscrl_w(uint8_t data)
{
iscr = (iscr & 0xff00) | data;
logerror("iscr = %04x\n", iscr);
@@ -331,25 +331,25 @@ void h8s_intc_device::device_reset()
memset(ipr, 0x77, sizeof(ipr));
}
-READ8_MEMBER(h8s_intc_device::ipr_r)
+uint8_t h8s_intc_device::ipr_r(offs_t offset)
{
return ipr[offset];
}
-WRITE8_MEMBER(h8s_intc_device::ipr_w)
+void h8s_intc_device::ipr_w(offs_t offset, uint8_t data)
{
ipr[offset] = data;
logerror("ipr %d = %02x\n", offset, data);
}
-READ8_MEMBER(h8s_intc_device::iprk_r)
+uint8_t h8s_intc_device::iprk_r()
{
- return ipr_r(space, 10, mem_mask);
+ return ipr_r(10);
}
-WRITE8_MEMBER(h8s_intc_device::iprk_w)
+void h8s_intc_device::iprk_w(uint8_t data)
{
- ipr_w(space, 10, data, mem_mask);
+ ipr_w(10, data);
}
const int h8s_intc_device::vector_to_slot[92] = {
diff --git a/src/devices/cpu/h8/h8_intc.h b/src/devices/cpu/h8/h8_intc.h
index 20bd830f45f..787bafc48cc 100644
--- a/src/devices/cpu/h8/h8_intc.h
+++ b/src/devices/cpu/h8/h8_intc.h
@@ -26,10 +26,10 @@ public:
void set_input(int inputnum, int state);
void set_filter(int icr_filter, int ipr_filter);
- DECLARE_READ8_MEMBER(ier_r);
- DECLARE_WRITE8_MEMBER(ier_w);
- DECLARE_READ8_MEMBER(iscr_r);
- DECLARE_WRITE8_MEMBER(iscr_w);
+ uint8_t ier_r();
+ void ier_w(uint8_t data);
+ uint8_t iscr_r();
+ void iscr_w(uint8_t data);
protected:
enum { IRQ_LEVEL, IRQ_EDGE, IRQ_DUAL_EDGE };
@@ -64,16 +64,16 @@ class h8h_intc_device : public h8_intc_device {
public:
h8h_intc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
- DECLARE_READ8_MEMBER(isr_r);
- DECLARE_WRITE8_MEMBER(isr_w);
- DECLARE_READ8_MEMBER(icr_r);
- DECLARE_WRITE8_MEMBER(icr_w);
- DECLARE_READ8_MEMBER(icrc_r);
- DECLARE_WRITE8_MEMBER(icrc_w);
- DECLARE_READ8_MEMBER(iscrh_r);
- DECLARE_WRITE8_MEMBER(iscrh_w);
- DECLARE_READ8_MEMBER(iscrl_r);
- DECLARE_WRITE8_MEMBER(iscrl_w);
+ uint8_t isr_r();
+ void isr_w(uint8_t data);
+ uint8_t icr_r(offs_t offset);
+ void icr_w(offs_t offset, uint8_t data);
+ uint8_t icrc_r();
+ void icrc_w(uint8_t data);
+ uint8_t iscrh_r();
+ void iscrh_w(uint8_t data);
+ uint8_t iscrl_r();
+ void iscrl_w(uint8_t data);
protected:
static const int vector_to_slot[];
@@ -93,10 +93,10 @@ class h8s_intc_device : public h8h_intc_device {
public:
h8s_intc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
- DECLARE_READ8_MEMBER(ipr_r);
- DECLARE_WRITE8_MEMBER(ipr_w);
- DECLARE_READ8_MEMBER(iprk_r);
- DECLARE_WRITE8_MEMBER(iprk_w);
+ uint8_t ipr_r(offs_t offset);
+ void ipr_w(offs_t offset, uint8_t data);
+ uint8_t iprk_r();
+ void iprk_w(uint8_t data);
private:
static const int vector_to_slot[];
uint8_t ipr[11];
diff --git a/src/devices/cpu/h8/h8_port.cpp b/src/devices/cpu/h8/h8_port.cpp
index bc21c99d6df..078a8c92a84 100644
--- a/src/devices/cpu/h8/h8_port.cpp
+++ b/src/devices/cpu/h8/h8_port.cpp
@@ -18,27 +18,27 @@ void h8_port_device::set_info(int _address, uint8_t _default_ddr, uint8_t _mask)
mask = _mask;
}
-WRITE8_MEMBER(h8_port_device::ddr_w)
+void h8_port_device::ddr_w(uint8_t data)
{
// logerror("ddr_w %02x\n", data);
ddr = data;
update_output();
}
-WRITE8_MEMBER(h8_port_device::dr_w)
+void h8_port_device::dr_w(uint8_t data)
{
// logerror("dr_w %02x\n", data);
dr = data;
update_output();
}
-READ8_MEMBER(h8_port_device::dr_r)
+uint8_t h8_port_device::dr_r()
{
// logerror("dr_r %02x\n", (dr | mask) & 0xff);
return dr | mask;
}
-READ8_MEMBER(h8_port_device::port_r)
+uint8_t h8_port_device::port_r()
{
uint8_t res = mask | (dr & ddr);
if((ddr & ~mask) != uint8_t(~mask))
@@ -48,25 +48,25 @@ READ8_MEMBER(h8_port_device::port_r)
return res;
}
-WRITE8_MEMBER(h8_port_device::pcr_w)
+void h8_port_device::pcr_w(uint8_t data)
{
logerror("pcr_w %02x\n", data);
pcr = data;
}
-READ8_MEMBER(h8_port_device::pcr_r)
+uint8_t h8_port_device::pcr_r()
{
logerror("dr_r %02x\n", (pcr | mask) & 0xff);
return pcr | mask;
}
-WRITE8_MEMBER(h8_port_device::odr_w)
+void h8_port_device::odr_w(uint8_t data)
{
logerror("odr_w %02x\n", data);
odr = data;
}
-READ8_MEMBER(h8_port_device::odr_r)
+uint8_t h8_port_device::odr_r()
{
logerror("odr_r %02x\n", (odr | mask) & 0xff);
return odr | ~mask;
diff --git a/src/devices/cpu/h8/h8_port.h b/src/devices/cpu/h8/h8_port.h
index 033aee4484d..887efcebf47 100644
--- a/src/devices/cpu/h8/h8_port.h
+++ b/src/devices/cpu/h8/h8_port.h
@@ -27,14 +27,14 @@ public:
void set_info(int address, uint8_t default_ddr, uint8_t mask);
- DECLARE_WRITE8_MEMBER(ddr_w);
- DECLARE_WRITE8_MEMBER(dr_w);
- DECLARE_READ8_MEMBER(dr_r);
- DECLARE_READ8_MEMBER(port_r);
- DECLARE_WRITE8_MEMBER(pcr_w);
- DECLARE_READ8_MEMBER(pcr_r);
- DECLARE_WRITE8_MEMBER(odr_w);
- DECLARE_READ8_MEMBER(odr_r);
+ void ddr_w(uint8_t data);
+ void dr_w(uint8_t data);
+ uint8_t dr_r();
+ uint8_t port_r();
+ void pcr_w(uint8_t data);
+ uint8_t pcr_r();
+ void odr_w(uint8_t data);
+ uint8_t odr_r();
protected:
required_device<h8_device> cpu;
diff --git a/src/devices/cpu/h8/h8_sci.cpp b/src/devices/cpu/h8/h8_sci.cpp
index c511ea664f9..b5d8b586f94 100644
--- a/src/devices/cpu/h8/h8_sci.cpp
+++ b/src/devices/cpu/h8/h8_sci.cpp
@@ -40,7 +40,7 @@ void h8_sci_device::set_external_clock_period(const attotime &period)
external_clock_period = period;
}
-WRITE8_MEMBER(h8_sci_device::smr_w)
+void h8_sci_device::smr_w(uint8_t data)
{
smr = data;
if(V>=2) logerror("smr_w %02x %s %c%c%c%s /%d (%06x)\n", data,
@@ -54,20 +54,20 @@ WRITE8_MEMBER(h8_sci_device::smr_w)
clock_update();
}
-READ8_MEMBER(h8_sci_device::smr_r)
+uint8_t h8_sci_device::smr_r()
{
if(V>=2) logerror("smr_r %02x (%06x)\n", smr, cpu->pc());
return smr;
}
-WRITE8_MEMBER(h8_sci_device::brr_w)
+void h8_sci_device::brr_w(uint8_t data)
{
brr = data;
if(V>=2) logerror("brr_w %02x (%06x)\n", data, cpu->pc());
clock_update();
}
-READ8_MEMBER(h8_sci_device::brr_r)
+uint8_t h8_sci_device::brr_r()
{
if(V>=2) logerror("brr_r %02x (%06x)\n", brr, cpu->pc());
return brr;
@@ -83,7 +83,7 @@ bool h8_sci_device::has_recv_error() const
return ssr & (SSR_ORER|SSR_PER|SSR_FER);
}
-WRITE8_MEMBER(h8_sci_device::scr_w)
+void h8_sci_device::scr_w(uint8_t data)
{
if(V>=2) logerror("scr_w %02x%s%s%s%s%s%s clk=%d (%06x)\n", data,
data & SCR_TIE ? " txi" : "",
@@ -116,13 +116,13 @@ WRITE8_MEMBER(h8_sci_device::scr_w)
intc->internal_interrupt(eri_int);
}
-READ8_MEMBER(h8_sci_device::scr_r)
+uint8_t h8_sci_device::scr_r()
{
if(V>=2) logerror("scr_r %02x (%06x)\n", scr, cpu->pc());
return scr;
}
-WRITE8_MEMBER(h8_sci_device::tdr_w)
+void h8_sci_device::tdr_w(uint8_t data)
{
if(V>=2) logerror("tdr_w %02x (%06x)\n", data, cpu->pc());
tdr = data;
@@ -133,13 +133,13 @@ WRITE8_MEMBER(h8_sci_device::tdr_w)
}
}
-READ8_MEMBER(h8_sci_device::tdr_r)
+uint8_t h8_sci_device::tdr_r()
{
if(V>=2) logerror("tdr_r %02x (%06x)\n", tdr, cpu->pc());
return tdr;
}
-WRITE8_MEMBER(h8_sci_device::ssr_w)
+void h8_sci_device::ssr_w(uint8_t data)
{
if(!(scr & SCR_TE)) {
data |= SSR_TDRE;
@@ -157,13 +157,13 @@ WRITE8_MEMBER(h8_sci_device::ssr_w)
rx_start();
}
-READ8_MEMBER(h8_sci_device::ssr_r)
+uint8_t h8_sci_device::ssr_r()
{
if(V>=3) logerror("ssr_r %02x (%06x)\n", ssr, cpu->pc());
return ssr;
}
-READ8_MEMBER(h8_sci_device::rdr_r)
+uint8_t h8_sci_device::rdr_r()
{
if(V>=2) logerror("rdr_r %02x (%06x)\n", rdr, cpu->pc());
if(cpu->access_is_dma())
@@ -171,12 +171,12 @@ READ8_MEMBER(h8_sci_device::rdr_r)
return rdr;
}
-WRITE8_MEMBER(h8_sci_device::scmr_w)
+void h8_sci_device::scmr_w(uint8_t data)
{
if(V>=2) logerror("scmr_w %02x (%06x)\n", data, cpu->pc());
}
-READ8_MEMBER(h8_sci_device::scmr_r)
+uint8_t h8_sci_device::scmr_r()
{
if(V>=2) logerror("scmr_r (%06x)\n", cpu->pc());
return 0x00;
diff --git a/src/devices/cpu/h8/h8_sci.h b/src/devices/cpu/h8/h8_sci.h
index aa15f491160..bf3d5b8bcbb 100644
--- a/src/devices/cpu/h8/h8_sci.h
+++ b/src/devices/cpu/h8/h8_sci.h
@@ -29,19 +29,19 @@ public:
void set_info(const char *intc, int eri, int rxi, int txi, int tei);
void set_external_clock_period(const attotime &_period);
- DECLARE_WRITE8_MEMBER(smr_w);
- DECLARE_READ8_MEMBER(smr_r);
- DECLARE_WRITE8_MEMBER(brr_w);
- DECLARE_READ8_MEMBER(brr_r);
- DECLARE_WRITE8_MEMBER(scr_w);
- DECLARE_READ8_MEMBER(scr_r);
- DECLARE_WRITE8_MEMBER(tdr_w);
- DECLARE_READ8_MEMBER(tdr_r);
- DECLARE_WRITE8_MEMBER(ssr_w);
- DECLARE_READ8_MEMBER(ssr_r);
- DECLARE_READ8_MEMBER(rdr_r);
- DECLARE_WRITE8_MEMBER(scmr_w);
- DECLARE_READ8_MEMBER(scmr_r);
+ void smr_w(uint8_t data);
+ uint8_t smr_r();
+ void brr_w(uint8_t data);
+ uint8_t brr_r();
+ void scr_w(uint8_t data);
+ uint8_t scr_r();
+ void tdr_w(uint8_t data);
+ uint8_t tdr_r();
+ void ssr_w(uint8_t data);
+ uint8_t ssr_r();
+ uint8_t rdr_r();
+ void scmr_w(uint8_t data);
+ uint8_t scmr_r();
DECLARE_WRITE_LINE_MEMBER(rx_w);
DECLARE_WRITE_LINE_MEMBER(clk_w);
diff --git a/src/devices/cpu/h8/h8_timer16.cpp b/src/devices/cpu/h8/h8_timer16.cpp
index 5c4294e542c..fdb0e3ddd05 100644
--- a/src/devices/cpu/h8/h8_timer16.cpp
+++ b/src/devices/cpu/h8/h8_timer16.cpp
@@ -41,12 +41,12 @@ void h8_timer16_channel_device::set_info(int _tgr_count, int _tbr_count, const c
interrupt[5] = irq_base;
}
-READ8_MEMBER(h8_timer16_channel_device::tcr_r)
+uint8_t h8_timer16_channel_device::tcr_r()
{
return tcr;
}
-WRITE8_MEMBER(h8_timer16_channel_device::tcr_w)
+void h8_timer16_channel_device::tcr_w(uint8_t data)
{
update_counter();
tcr = data;
@@ -55,22 +55,22 @@ WRITE8_MEMBER(h8_timer16_channel_device::tcr_w)
recalc_event();
}
-READ8_MEMBER(h8_timer16_channel_device::tmdr_r)
+uint8_t h8_timer16_channel_device::tmdr_r()
{
return 0x00;
}
-WRITE8_MEMBER(h8_timer16_channel_device::tmdr_w)
+void h8_timer16_channel_device::tmdr_w(uint8_t data)
{
if(V>=1) logerror("tmdr_w %02x\n", data);
}
-READ8_MEMBER(h8_timer16_channel_device::tior_r)
+uint8_t h8_timer16_channel_device::tior_r()
{
return 0x00;
}
-WRITE8_MEMBER(h8_timer16_channel_device::tior_w)
+void h8_timer16_channel_device::tior_w(offs_t offset, uint8_t data)
{
if(V>=1) logerror("tior_w %d, %02x\n", offset, data);
}
@@ -89,12 +89,12 @@ void h8_timer16_channel_device::set_enable(bool enable)
recalc_event();
}
-READ8_MEMBER(h8_timer16_channel_device::tier_r)
+uint8_t h8_timer16_channel_device::tier_r()
{
return tier;
}
-WRITE8_MEMBER(h8_timer16_channel_device::tier_w)
+void h8_timer16_channel_device::tier_w(uint8_t data)
{
update_counter();
if(V>=1) logerror("tier_w %02x\n", data);
@@ -111,24 +111,24 @@ WRITE8_MEMBER(h8_timer16_channel_device::tier_w)
recalc_event();
}
-READ8_MEMBER(h8_timer16_channel_device::tsr_r)
+uint8_t h8_timer16_channel_device::tsr_r()
{
return isr_to_sr();
}
-WRITE8_MEMBER(h8_timer16_channel_device::tsr_w)
+void h8_timer16_channel_device::tsr_w(uint8_t data)
{
if(V>=1) logerror("tsr_w %02x\n", data);
isr_update(data);
}
-READ16_MEMBER(h8_timer16_channel_device::tcnt_r)
+uint16_t h8_timer16_channel_device::tcnt_r()
{
update_counter();
return tcnt;
}
-WRITE16_MEMBER(h8_timer16_channel_device::tcnt_w)
+void h8_timer16_channel_device::tcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
update_counter();
COMBINE_DATA(&tcnt);
@@ -136,12 +136,12 @@ WRITE16_MEMBER(h8_timer16_channel_device::tcnt_w)
recalc_event();
}
-READ16_MEMBER(h8_timer16_channel_device::tgr_r)
+uint16_t h8_timer16_channel_device::tgr_r(offs_t offset)
{
return tgr[offset];
}
-WRITE16_MEMBER(h8_timer16_channel_device::tgr_w)
+void h8_timer16_channel_device::tgr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
update_counter();
COMBINE_DATA(tgr + offset);
@@ -149,12 +149,12 @@ WRITE16_MEMBER(h8_timer16_channel_device::tgr_w)
recalc_event();
}
-READ16_MEMBER(h8_timer16_channel_device::tbr_r)
+uint16_t h8_timer16_channel_device::tbr_r(offs_t offset)
{
return tgr[offset+tgr_count];
}
-WRITE16_MEMBER(h8_timer16_channel_device::tbr_w)
+void h8_timer16_channel_device::tbr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(tgr + offset + tgr_count);
if(V>=1) logerror("tbr%c_w %04x\n", 'a'+offset, tgr[offset]);
@@ -345,12 +345,12 @@ void h8_timer16_device::device_reset()
}
-READ8_MEMBER(h8_timer16_device::tstr_r)
+uint8_t h8_timer16_device::tstr_r()
{
return tstr;
}
-WRITE8_MEMBER(h8_timer16_device::tstr_w)
+void h8_timer16_device::tstr_w(uint8_t data)
{
if(V>=1) logerror("tstr_w %02x\n", data);
tstr = data;
@@ -358,57 +358,57 @@ WRITE8_MEMBER(h8_timer16_device::tstr_w)
timer_channel[i]->set_enable((tstr >> i) & 1);
}
-READ8_MEMBER(h8_timer16_device::tsyr_r)
+uint8_t h8_timer16_device::tsyr_r()
{
return 0x00;
}
-WRITE8_MEMBER(h8_timer16_device::tsyr_w)
+void h8_timer16_device::tsyr_w(uint8_t data)
{
if(V>=1) logerror("tsyr_w %02x\n", data);
}
-READ8_MEMBER(h8_timer16_device::tmdr_r)
+uint8_t h8_timer16_device::tmdr_r()
{
return 0x00;
}
-WRITE8_MEMBER(h8_timer16_device::tmdr_w)
+void h8_timer16_device::tmdr_w(uint8_t data)
{
if(V>=1) logerror("tmdr_w %02x\n", data);
}
-READ8_MEMBER(h8_timer16_device::tfcr_r)
+uint8_t h8_timer16_device::tfcr_r()
{
return 0x00;
}
-WRITE8_MEMBER(h8_timer16_device::tfcr_w)
+void h8_timer16_device::tfcr_w(uint8_t data)
{
if(V>=1) logerror("tfcr_w %02x\n", data);
}
-READ8_MEMBER(h8_timer16_device::toer_r)
+uint8_t h8_timer16_device::toer_r()
{
return 0x00;
}
-WRITE8_MEMBER(h8_timer16_device::toer_w)
+void h8_timer16_device::toer_w(uint8_t data)
{
if(V>=1) logerror("toer_w %02x\n", data);
}
-READ8_MEMBER(h8_timer16_device::tocr_r)
+uint8_t h8_timer16_device::tocr_r()
{
return 0x00;
}
-WRITE8_MEMBER(h8_timer16_device::tocr_w)
+void h8_timer16_device::tocr_w(uint8_t data)
{
if(V>=1) logerror("tocr_w %02x\n", data);
}
-READ8_MEMBER(h8_timer16_device::tisr_r)
+uint8_t h8_timer16_device::tisr_r(offs_t offset)
{
uint8_t r = 0;
for(int i=0; i<timer_count; i++)
@@ -421,24 +421,24 @@ READ8_MEMBER(h8_timer16_device::tisr_r)
return r;
}
-WRITE8_MEMBER(h8_timer16_device::tisr_w)
+void h8_timer16_device::tisr_w(offs_t offset, uint8_t data)
{
if(V>=1) logerror("tisr%c_w %02x\n", 'a'+offset, data);
for(int i=0; i<timer_count; i++)
timer_channel[i]->tisr_w(offset, data >> i);
}
-READ8_MEMBER(h8_timer16_device::tisrc_r)
+uint8_t h8_timer16_device::tisrc_r()
{
- return tisr_r(space, 2, mem_mask);
+ return tisr_r(2);
}
-WRITE8_MEMBER(h8_timer16_device::tisrc_w)
+void h8_timer16_device::tisrc_w(uint8_t data)
{
- tisr_w(space, 2, data, mem_mask);
+ tisr_w(2, data);
}
-WRITE8_MEMBER(h8_timer16_device::tolr_w)
+void h8_timer16_device::tolr_w(uint8_t data)
{
if(V>=1) logerror("tocr_w %02x\n", data);
}
diff --git a/src/devices/cpu/h8/h8_timer16.h b/src/devices/cpu/h8/h8_timer16.h
index a22c68eb53d..6543b9ccb7c 100644
--- a/src/devices/cpu/h8/h8_timer16.h
+++ b/src/devices/cpu/h8/h8_timer16.h
@@ -65,22 +65,22 @@ public:
void set_info(int tgr_count, int tbr_count, const char *intc, int irq_base);
- DECLARE_READ8_MEMBER(tcr_r);
- DECLARE_WRITE8_MEMBER(tcr_w);
- DECLARE_READ8_MEMBER(tmdr_r);
- DECLARE_WRITE8_MEMBER(tmdr_w);
- DECLARE_READ8_MEMBER(tior_r);
- DECLARE_WRITE8_MEMBER(tior_w);
- DECLARE_READ8_MEMBER(tier_r);
- DECLARE_WRITE8_MEMBER(tier_w);
- DECLARE_READ8_MEMBER(tsr_r);
- DECLARE_WRITE8_MEMBER(tsr_w);
- DECLARE_READ16_MEMBER(tcnt_r);
- DECLARE_WRITE16_MEMBER(tcnt_w);
- DECLARE_READ16_MEMBER(tgr_r);
- DECLARE_WRITE16_MEMBER(tgr_w);
- DECLARE_READ16_MEMBER(tbr_r);
- DECLARE_WRITE16_MEMBER(tbr_w);
+ uint8_t tcr_r();
+ void tcr_w(uint8_t data);
+ uint8_t tmdr_r();
+ void tmdr_w(uint8_t data);
+ uint8_t tior_r();
+ void tior_w(offs_t offset, uint8_t data);
+ uint8_t tier_r();
+ void tier_w(uint8_t data);
+ uint8_t tsr_r();
+ void tsr_w(uint8_t data);
+ uint16_t tcnt_r();
+ void tcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t tgr_r(offs_t offset);
+ void tgr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t tbr_r(offs_t offset);
+ void tbr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint64_t internal_update(uint64_t current_time);
void set_ier(uint8_t value);
@@ -172,23 +172,23 @@ public:
}
void set_info(int timer_count, uint8_t default_tstr);
- DECLARE_READ8_MEMBER(tstr_r);
- DECLARE_WRITE8_MEMBER(tstr_w);
- DECLARE_READ8_MEMBER(tsyr_r);
- DECLARE_WRITE8_MEMBER(tsyr_w);
- DECLARE_READ8_MEMBER(tmdr_r);
- DECLARE_WRITE8_MEMBER(tmdr_w);
- DECLARE_READ8_MEMBER(tfcr_r);
- DECLARE_WRITE8_MEMBER(tfcr_w);
- DECLARE_READ8_MEMBER(toer_r);
- DECLARE_WRITE8_MEMBER(toer_w);
- DECLARE_READ8_MEMBER(tocr_r);
- DECLARE_WRITE8_MEMBER(tocr_w);
- DECLARE_READ8_MEMBER(tisr_r);
- DECLARE_WRITE8_MEMBER(tisr_w);
- DECLARE_READ8_MEMBER(tisrc_r);
- DECLARE_WRITE8_MEMBER(tisrc_w);
- DECLARE_WRITE8_MEMBER(tolr_w);
+ uint8_t tstr_r();
+ void tstr_w(uint8_t data);
+ uint8_t tsyr_r();
+ void tsyr_w(uint8_t data);
+ uint8_t tmdr_r();
+ void tmdr_w(uint8_t data);
+ uint8_t tfcr_r();
+ void tfcr_w(uint8_t data);
+ uint8_t toer_r();
+ void toer_w(uint8_t data);
+ uint8_t tocr_r();
+ void tocr_w(uint8_t data);
+ uint8_t tisr_r(offs_t offset);
+ void tisr_w(offs_t offset, uint8_t data);
+ uint8_t tisrc_r();
+ void tisrc_w(uint8_t data);
+ void tolr_w(uint8_t data);
protected:
required_device<h8_device> cpu;
diff --git a/src/devices/cpu/h8/h8_timer8.cpp b/src/devices/cpu/h8/h8_timer8.cpp
index 7a95717471d..352b4a7f7d9 100644
--- a/src/devices/cpu/h8/h8_timer8.cpp
+++ b/src/devices/cpu/h8/h8_timer8.cpp
@@ -42,12 +42,12 @@ void h8_timer8_channel_device::set_info(const char *intc, int _irq_ca, int _irq_
div_tab[5] = div6;
}
-READ8_MEMBER(h8_timer8_channel_device::tcr_r)
+uint8_t h8_timer8_channel_device::tcr_r()
{
return tcr;
}
-WRITE8_MEMBER(h8_timer8_channel_device::tcr_w)
+void h8_timer8_channel_device::tcr_w(uint8_t data)
{
update_counter();
tcr = data;
@@ -134,12 +134,12 @@ void h8_timer8_channel_device::update_tcr()
logerror(buf);
}
-READ8_MEMBER(h8_timer8_channel_device::tcsr_r)
+uint8_t h8_timer8_channel_device::tcsr_r()
{
return tcsr;
}
-WRITE8_MEMBER(h8_timer8_channel_device::tcsr_w)
+void h8_timer8_channel_device::tcsr_w(uint8_t data)
{
update_counter();
@@ -152,12 +152,12 @@ WRITE8_MEMBER(h8_timer8_channel_device::tcsr_w)
recalc_event();
}
-READ8_MEMBER(h8_timer8_channel_device::tcor_r)
+uint8_t h8_timer8_channel_device::tcor_r(offs_t offset)
{
return tcor[offset];
}
-WRITE8_MEMBER(h8_timer8_channel_device::tcor_w)
+void h8_timer8_channel_device::tcor_w(offs_t offset, uint8_t data)
{
update_counter();
tcor[offset] = data;
@@ -165,14 +165,14 @@ WRITE8_MEMBER(h8_timer8_channel_device::tcor_w)
recalc_event();
}
-READ8_MEMBER(h8_timer8_channel_device::tcnt_r)
+uint8_t h8_timer8_channel_device::tcnt_r()
{
update_counter();
recalc_event();
return tcnt;
}
-WRITE8_MEMBER(h8_timer8_channel_device::tcnt_w)
+void h8_timer8_channel_device::tcnt_w(uint8_t data)
{
update_counter();
tcnt = data;
diff --git a/src/devices/cpu/h8/h8_timer8.h b/src/devices/cpu/h8/h8_timer8.h
index b08c51556d2..0ba06d933ba 100644
--- a/src/devices/cpu/h8/h8_timer8.h
+++ b/src/devices/cpu/h8/h8_timer8.h
@@ -39,14 +39,14 @@ public:
void set_info(const char *intc, int irq_ca, int irq_cb, int irq_v, int div1, int div2, int div3, int div4, int div5, int div6);
- DECLARE_READ8_MEMBER(tcr_r);
- DECLARE_WRITE8_MEMBER(tcr_w);
- DECLARE_READ8_MEMBER(tcsr_r);
- DECLARE_WRITE8_MEMBER(tcsr_w);
- DECLARE_READ8_MEMBER(tcor_r);
- DECLARE_WRITE8_MEMBER(tcor_w);
- DECLARE_READ8_MEMBER(tcnt_r);
- DECLARE_WRITE8_MEMBER(tcnt_w);
+ uint8_t tcr_r();
+ void tcr_w(uint8_t data);
+ uint8_t tcsr_r();
+ void tcsr_w(uint8_t data);
+ uint8_t tcor_r(offs_t offset);
+ void tcor_w(offs_t offset, uint8_t data);
+ uint8_t tcnt_r();
+ void tcnt_w(uint8_t data);
uint64_t internal_update(uint64_t current_time);
void set_extra_clock_bit(bool bit);
diff --git a/src/devices/cpu/h8/h8_watchdog.cpp b/src/devices/cpu/h8/h8_watchdog.cpp
index b4e5080c104..acbdf3db31c 100644
--- a/src/devices/cpu/h8/h8_watchdog.cpp
+++ b/src/devices/cpu/h8/h8_watchdog.cpp
@@ -65,7 +65,7 @@ void h8_watchdog_device::tcnt_update(uint64_t cur_time)
}
-READ16_MEMBER(h8_watchdog_device::wd_r)
+uint16_t h8_watchdog_device::wd_r()
{
if (!machine().side_effects_disabled())
{
@@ -75,7 +75,7 @@ READ16_MEMBER(h8_watchdog_device::wd_r)
return 0;
}
-WRITE16_MEMBER(h8_watchdog_device::wd_w)
+void h8_watchdog_device::wd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if(mem_mask != 0xffff)
return;
@@ -99,14 +99,14 @@ WRITE16_MEMBER(h8_watchdog_device::wd_w)
}
}
-READ16_MEMBER(h8_watchdog_device::rst_r)
+uint16_t h8_watchdog_device::rst_r()
{
if (!machine().side_effects_disabled())
logerror("rst_r\n");
return 0;
}
-WRITE16_MEMBER(h8_watchdog_device::rst_w)
+void h8_watchdog_device::rst_w(uint16_t data)
{
if((data & 0xff00) == 0xa500)
logerror("wowf_w %02x\n", data & 0xff);
diff --git a/src/devices/cpu/h8/h8_watchdog.h b/src/devices/cpu/h8/h8_watchdog.h
index 0cad0e67020..1cb63025141 100644
--- a/src/devices/cpu/h8/h8_watchdog.h
+++ b/src/devices/cpu/h8/h8_watchdog.h
@@ -60,10 +60,10 @@ public:
uint64_t internal_update(uint64_t current_time);
- DECLARE_READ16_MEMBER(wd_r);
- DECLARE_WRITE16_MEMBER(wd_w);
- DECLARE_READ16_MEMBER(rst_r);
- DECLARE_WRITE16_MEMBER(rst_w);
+ uint16_t wd_r();
+ void wd_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t rst_r();
+ void rst_w(uint16_t data);
protected:
virtual void device_start() override;
diff --git a/src/devices/cpu/h8/h8s2245.cpp b/src/devices/cpu/h8/h8s2245.cpp
index c5e68c9bb4f..b5101017f07 100644
--- a/src/devices/cpu/h8/h8s2245.cpp
+++ b/src/devices/cpu/h8/h8s2245.cpp
@@ -316,24 +316,24 @@ void h8s2245_device::device_reset()
mstpcr = 0x3fff;
}
-READ8_MEMBER(h8s2245_device::syscr_r)
+uint8_t h8s2245_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h8s2245_device::syscr_w)
+void h8s2245_device::syscr_w(uint8_t data)
{
syscr = data;
update_irq_filter();
logerror("syscr = %02x\n", data);
}
-READ16_MEMBER(h8s2245_device::mstpcr_r)
+uint16_t h8s2245_device::mstpcr_r()
{
return mstpcr;
}
-WRITE16_MEMBER(h8s2245_device::mstpcr_w)
+void h8s2245_device::mstpcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
uint16_t omstpcr = mstpcr;
COMBINE_DATA(&mstpcr);
diff --git a/src/devices/cpu/h8/h8s2245.h b/src/devices/cpu/h8/h8s2245.h
index 732f4c02692..4fca522bbc5 100644
--- a/src/devices/cpu/h8/h8s2245.h
+++ b/src/devices/cpu/h8/h8s2245.h
@@ -37,10 +37,10 @@ class h8s2245_device : public h8s2000_device {
public:
h8s2245_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
- DECLARE_READ16_MEMBER(mstpcr_r);
- DECLARE_WRITE16_MEMBER(mstpcr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
+ uint16_t mstpcr_r();
+ void mstpcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
protected:
required_device<h8s_intc_device> intc;
diff --git a/src/devices/cpu/h8/h8s2320.cpp b/src/devices/cpu/h8/h8s2320.cpp
index 48b8a299f63..14cd0e0a396 100644
--- a/src/devices/cpu/h8/h8s2320.cpp
+++ b/src/devices/cpu/h8/h8s2320.cpp
@@ -443,12 +443,12 @@ void h8s2320_device::device_reset()
syscr = 0x01;
}
-READ8_MEMBER(h8s2320_device::syscr_r)
+uint8_t h8s2320_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h8s2320_device::syscr_w)
+void h8s2320_device::syscr_w(uint8_t data)
{
syscr = data;
mac_saturating = syscr & 0x80;
diff --git a/src/devices/cpu/h8/h8s2320.h b/src/devices/cpu/h8/h8s2320.h
index def1cb3ab4c..4ea272d283f 100644
--- a/src/devices/cpu/h8/h8s2320.h
+++ b/src/devices/cpu/h8/h8s2320.h
@@ -43,8 +43,8 @@ class h8s2320_device : public h8s2000_device {
public:
h8s2320_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
protected:
required_device<h8s_intc_device> intc;
diff --git a/src/devices/cpu/h8/h8s2357.cpp b/src/devices/cpu/h8/h8s2357.cpp
index 02b9e7bf09b..eda704291c5 100644
--- a/src/devices/cpu/h8/h8s2357.cpp
+++ b/src/devices/cpu/h8/h8s2357.cpp
@@ -382,12 +382,12 @@ void h8s2357_device::device_reset()
syscr = 0x01;
}
-READ8_MEMBER(h8s2357_device::syscr_r)
+uint8_t h8s2357_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h8s2357_device::syscr_w)
+void h8s2357_device::syscr_w(uint8_t data)
{
syscr = data;
update_irq_filter();
diff --git a/src/devices/cpu/h8/h8s2357.h b/src/devices/cpu/h8/h8s2357.h
index e0e8348256d..3f20c062d01 100644
--- a/src/devices/cpu/h8/h8s2357.h
+++ b/src/devices/cpu/h8/h8s2357.h
@@ -38,8 +38,8 @@ class h8s2357_device : public h8s2000_device {
public:
h8s2357_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
protected:
required_device<h8s_intc_device> intc;
diff --git a/src/devices/cpu/h8/h8s2655.cpp b/src/devices/cpu/h8/h8s2655.cpp
index f09b08bcab0..eb29b29bdc3 100644
--- a/src/devices/cpu/h8/h8s2655.cpp
+++ b/src/devices/cpu/h8/h8s2655.cpp
@@ -394,12 +394,12 @@ void h8s2655_device::device_reset()
syscr = 0x01;
}
-READ8_MEMBER(h8s2655_device::syscr_r)
+uint8_t h8s2655_device::syscr_r()
{
return syscr;
}
-WRITE8_MEMBER(h8s2655_device::syscr_w)
+void h8s2655_device::syscr_w(uint8_t data)
{
syscr = data;
update_irq_filter();
diff --git a/src/devices/cpu/h8/h8s2655.h b/src/devices/cpu/h8/h8s2655.h
index c7841af0c26..aa8384bce73 100644
--- a/src/devices/cpu/h8/h8s2655.h
+++ b/src/devices/cpu/h8/h8s2655.h
@@ -30,8 +30,8 @@ class h8s2655_device : public h8s2600_device {
public:
h8s2655_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ8_MEMBER(syscr_r);
- DECLARE_WRITE8_MEMBER(syscr_w);
+ uint8_t syscr_r();
+ void syscr_w(uint8_t data);
protected:
required_device<h8s_intc_device> intc;
diff --git a/src/devices/cpu/i386/athlon.cpp b/src/devices/cpu/i386/athlon.cpp
index 7da09ef271b..dddfa80fa35 100644
--- a/src/devices/cpu/i386/athlon.cpp
+++ b/src/devices/cpu/i386/athlon.cpp
@@ -32,7 +32,7 @@ void athlonxp_device::device_start()
space(AS_OPCODES).specific(m_opcodes);
space(AS_DATA).cache(mmacache32);
- space(AS_OPCODES).install_read_handler(0, 0xffffffff, read32_delegate(*this, FUNC(athlonxp_device::debug_read_memory)));
+ space(AS_OPCODES).install_read_handler(0, 0xffffffff, read32sm_delegate(*this, FUNC(athlonxp_device::debug_read_memory)));
build_x87_opcode_table();
build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE);
@@ -188,7 +188,7 @@ int athlonxp_device::address_mode(offs_t address)
return 1;
}
-READ32_MEMBER(athlonxp_device::debug_read_memory)
+u32 athlonxp_device::debug_read_memory(offs_t offset)
{
offs_t address = offset << 2;
int mode = check_cacheable(address);
diff --git a/src/devices/cpu/i386/athlon.h b/src/devices/cpu/i386/athlon.h
index f7ee68ce962..69cc6d84794 100644
--- a/src/devices/cpu/i386/athlon.h
+++ b/src/devices/cpu/i386/athlon.h
@@ -52,7 +52,7 @@ private:
uint32_t program_read_cache(offs_t address, uint32_t mask);
void program_write_cache(offs_t address, uint32_t data, uint32_t mask);
- DECLARE_READ32_MEMBER(debug_read_memory);
+ u32 debug_read_memory(offs_t offset);
address_space_config m_data_config;
address_space_config m_opcodes_config;
diff --git a/src/devices/cpu/i86/i186.cpp b/src/devices/cpu/i86/i186.cpp
index 5a9772a9846..b530af629b7 100644
--- a/src/devices/cpu/i86/i186.cpp
+++ b/src/devices/cpu/i86/i186.cpp
@@ -742,9 +742,9 @@ uint8_t i80186_cpu_device::read_port_byte(uint16_t port)
if(!(m_reloc & 0x1000) && (port >> 8) == (m_reloc & 0xff))
{
if(port & 1)
- return internal_port_r(*m_io, (port >> 1) & 0x7f, 0xff00) >> 8;
+ return internal_port_r((port >> 1) & 0x7f, 0xff00) >> 8;
else
- return internal_port_r(*m_io, (port >> 1) & 0x7f, 0x00ff) & 0xff;
+ return internal_port_r((port >> 1) & 0x7f, 0x00ff) & 0xff;
}
return m_io->read_byte(port);
}
@@ -755,9 +755,9 @@ uint16_t i80186_cpu_device::read_port_word(uint16_t port)
{
// Unaligned reads from the internal bus are swapped rather than split
if(port & 1)
- return swapendian_int16(internal_port_r(*m_io, (port >> 1) & 0x7f));
+ return swapendian_int16(internal_port_r((port >> 1) & 0x7f));
else
- return internal_port_r(*m_io, (port >> 1) & 0x7f);
+ return internal_port_r((port >> 1) & 0x7f);
}
return m_io->read_word_unaligned(port);
}
@@ -767,9 +767,9 @@ void i80186_cpu_device::write_port_byte(uint16_t port, uint8_t data)
if(!(m_reloc & 0x1000) && (port >> 8) == (m_reloc & 0xff))
{
if(port & 1)
- internal_port_w(*m_io, (port >> 1) & 0x7f, data << 8, 0xff00);
+ internal_port_w((port >> 1) & 0x7f, data << 8);
else
- internal_port_w(*m_io, (port >> 1) & 0x7f, data, 0x00ff);
+ internal_port_w((port >> 1) & 0x7f, data);
}
else
m_io->write_byte(port, data);
@@ -781,9 +781,9 @@ void i80186_cpu_device::write_port_byte_al(uint16_t port)
{
// Both AH and AL are written onto the internal bus
if(port & 1)
- internal_port_w(*m_io, (port >> 1) & 0x7f, swapendian_int16(m_regs.w[AX]), 0xff00);
+ internal_port_w((port >> 1) & 0x7f, swapendian_int16(m_regs.w[AX]));
else
- internal_port_w(*m_io, (port >> 1) & 0x7f, m_regs.w[AX], 0x00ff);
+ internal_port_w((port >> 1) & 0x7f, m_regs.w[AX]);
}
else
m_io->write_byte(port, m_regs.w[AL]);
@@ -795,9 +795,9 @@ void i80186_cpu_device::write_port_word(uint16_t port, uint16_t data)
{
// Unaligned writes to the internal bus are swapped rather than split
if(port & 1)
- internal_port_w(*m_io, (port >> 1) & 0x7f, swapendian_int16(data));
+ internal_port_w((port >> 1) & 0x7f, swapendian_int16(data));
else
- internal_port_w(*m_io, (port >> 1) & 0x7f, data);
+ internal_port_w((port >> 1) & 0x7f, data);
}
else
m_io->write_word_unaligned(port, data);
@@ -807,7 +807,7 @@ uint8_t i80186_cpu_device::read_byte(uint32_t addr)
{
if((m_reloc & 0x1000) && (addr >> 8) == (m_reloc & 0xfff))
{
- uint16_t ret = internal_port_r(*m_program, (addr >> 1) & 0x7f, (addr & 1) ? 0xff00 : 0x00ff);
+ uint16_t ret = internal_port_r((addr >> 1) & 0x7f, (addr & 1) ? 0xff00 : 0x00ff);
return (addr & 1) ? (ret >> 8) : (ret & 0xff);
}
return m_program->read_byte(addr);
@@ -819,9 +819,9 @@ uint16_t i80186_cpu_device::read_word(uint32_t addr)
{
// Unaligned reads from the internal bus are swapped rather than split
if(addr & 1)
- return swapendian_int16(internal_port_r(*m_program, (addr >> 1) & 0x7f));
+ return swapendian_int16(internal_port_r((addr >> 1) & 0x7f));
else
- return internal_port_r(*m_program, (addr >> 1) & 0x7f);
+ return internal_port_r((addr >> 1) & 0x7f);
}
return m_program->read_word_unaligned(addr);
}
@@ -829,7 +829,7 @@ uint16_t i80186_cpu_device::read_word(uint32_t addr)
void i80186_cpu_device::write_byte(uint32_t addr, uint8_t data)
{
if((m_reloc & 0x1000) && (addr >> 8) == (m_reloc & 0xfff))
- internal_port_w(*m_program, (addr >> 1) & 0x7f, (addr & 1) ? (data << 8) : data, (addr & 1) ? 0xff00 : 0x00ff);
+ internal_port_w((addr >> 1) & 0x7f, (addr & 1) ? (data << 8) : data);
else
m_program->write_byte(addr, data);
}
@@ -840,9 +840,9 @@ void i80186_cpu_device::write_word(uint32_t addr, uint16_t data)
{
// Unaligned writes from the internal bus are swapped rather than split
if(addr & 1)
- internal_port_w(*m_program, (addr >> 1) & 0x7f, swapendian_int16(data));
+ internal_port_w((addr >> 1) & 0x7f, swapendian_int16(data));
else
- internal_port_w(*m_program, (addr >> 1) & 0x7f, data);
+ internal_port_w((addr >> 1) & 0x7f, data);
}
else
m_program->write_word_unaligned(addr, data);
@@ -1555,7 +1555,7 @@ void i80186_cpu_device::drq_callback(int which)
}
}
-READ16_MEMBER(i80186_cpu_device::internal_port_r)
+uint16_t i80186_cpu_device::internal_port_r(offs_t offset, uint16_t mem_mask)
{
int temp, which;
@@ -1759,7 +1759,7 @@ READ16_MEMBER(i80186_cpu_device::internal_port_r)
*
*************************************/
-WRITE16_MEMBER(i80186_cpu_device::internal_port_w)
+void i80186_cpu_device::internal_port_w(offs_t offset, uint16_t data)
{
int which;
diff --git a/src/devices/cpu/i86/i186.h b/src/devices/cpu/i86/i186.h
index 46055622486..f1bd6aa91b5 100644
--- a/src/devices/cpu/i86/i186.h
+++ b/src/devices/cpu/i86/i186.h
@@ -91,8 +91,8 @@ private:
void update_dma_control(int which, int new_control);
void drq_callback(int which);
void inc_timer(int which);
- DECLARE_READ16_MEMBER(internal_port_r);
- DECLARE_WRITE16_MEMBER(internal_port_w);
+ uint16_t internal_port_r(offs_t offset, uint16_t mem_mask = ~0);
+ void internal_port_w(offs_t offset, uint16_t data);
struct mem_state
{
diff --git a/src/devices/cpu/jaguar/jaguar.cpp b/src/devices/cpu/jaguar/jaguar.cpp
index 7aeddda468a..983df1ec4a9 100644
--- a/src/devices/cpu/jaguar/jaguar.cpp
+++ b/src/devices/cpu/jaguar/jaguar.cpp
@@ -1316,12 +1316,12 @@ void jaguardsp_cpu_device::io_map(address_map &map)
map(0x20, 0x23).r(FUNC(jaguardsp_cpu_device::high_accum_r));
}
-READ32_MEMBER(jaguar_cpu_device::flags_r)
+u32 jaguar_cpu_device::flags_r()
{
return (m_flags & 0x1c1f7) | (m_imask << 3);
}
-WRITE32_MEMBER(jaguar_cpu_device::flags_w)
+void jaguar_cpu_device::flags_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_flags);
// clear imask only on bit 3 clear (1 has no effect)
@@ -1345,21 +1345,21 @@ WRITE32_MEMBER(jaguar_cpu_device::flags_w)
check_irqs();
}
-WRITE32_MEMBER(jaguar_cpu_device::matrix_control_w)
+void jaguar_cpu_device::matrix_control_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_io_mtxc);
m_mwidth = m_io_mtxc & 0xf;
m_maddw = BIT(m_io_mtxc, 4);
}
-WRITE32_MEMBER(jaguar_cpu_device::matrix_address_w)
+void jaguar_cpu_device::matrix_address_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_io_mtxa);
// matrix can be long word address only, and only read from internal RAM
m_mtxaddr = m_internal_ram_start | (m_io_mtxa & 0xffc);
}
-WRITE32_MEMBER(jaguar_cpu_device::pc_w)
+void jaguar_cpu_device::pc_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_io_pc);
if (m_go == false)
@@ -1377,7 +1377,7 @@ WRITE32_MEMBER(jaguar_cpu_device::pc_w)
* ---- ---x I/O endianness
*/
// TODO: just log if anything farts for now, change to bit struct once we have something to test out
-WRITE32_MEMBER(jaguar_cpu_device::end_w)
+void jaguar_cpu_device::end_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_io_end);
// sburnout sets bit 1 == 0
@@ -1385,7 +1385,7 @@ WRITE32_MEMBER(jaguar_cpu_device::end_w)
throw emu_fatalerror("%s: fatal endian setup %08x", this->tag(), m_io_end);
}
-WRITE32_MEMBER(jaguardsp_cpu_device::dsp_end_w)
+void jaguardsp_cpu_device::dsp_end_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_io_end);
// wolfn3d writes a '0' to bit 1 (which is a NOP for DSP)
@@ -1405,7 +1405,7 @@ WRITE32_MEMBER(jaguardsp_cpu_device::dsp_end_w)
* - ---- ---- ---- ---x GPUGO or DSPGO flag
*
*/
-READ32_MEMBER(jaguar_cpu_device::status_r)
+u32 jaguar_cpu_device::status_r()
{
u32 result = ((m_version & 0xf)<<12) | (m_bus_hog<<11) | m_go;
result|= (m_int_latch & 0x1f) << 6;
@@ -1422,7 +1422,7 @@ WRITE_LINE_MEMBER(jaguar_cpu_device::go_w)
yield();
}
-WRITE32_MEMBER(jaguar_cpu_device::control_w)
+void jaguar_cpu_device::control_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_io_status);
bool new_go = BIT(m_io_status, 0);
@@ -1447,33 +1447,33 @@ WRITE32_MEMBER(jaguar_cpu_device::control_w)
logerror("%s: bus hog enabled\n", this->tag());
}
-READ32_MEMBER(jaguargpu_cpu_device::hidata_r)
+u32 jaguargpu_cpu_device::hidata_r()
{
return m_hidata;
}
-WRITE32_MEMBER(jaguargpu_cpu_device::hidata_w)
+void jaguargpu_cpu_device::hidata_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_hidata);
}
-READ32_MEMBER(jaguar_cpu_device::div_remainder_r)
+u32 jaguar_cpu_device::div_remainder_r()
{
// TODO: truly 32-bit?
return m_div_remainder;
}
-WRITE32_MEMBER(jaguar_cpu_device::div_control_w)
+void jaguar_cpu_device::div_control_w(u32 data)
{
m_div_offset = BIT(data, 0);
}
-WRITE32_MEMBER(jaguardsp_cpu_device::modulo_w)
+void jaguardsp_cpu_device::modulo_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_modulo);
}
-READ32_MEMBER(jaguardsp_cpu_device::high_accum_r)
+u32 jaguardsp_cpu_device::high_accum_r()
{
printf("%s: high 16-bit accumulator read\n", this->tag());
return (m_accum >> 32) & 0xff;
diff --git a/src/devices/cpu/jaguar/jaguar.h b/src/devices/cpu/jaguar/jaguar.h
index f9e8189b739..5cd4c616a69 100644
--- a/src/devices/cpu/jaguar/jaguar.h
+++ b/src/devices/cpu/jaguar/jaguar.h
@@ -84,16 +84,16 @@ protected:
virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
// I/Os (common)
- DECLARE_READ32_MEMBER(flags_r);
- DECLARE_WRITE32_MEMBER(flags_w);
- DECLARE_WRITE32_MEMBER(matrix_control_w);
- DECLARE_WRITE32_MEMBER(matrix_address_w);
- DECLARE_WRITE32_MEMBER(end_w);
- DECLARE_WRITE32_MEMBER(pc_w);
- DECLARE_READ32_MEMBER(status_r);
- DECLARE_WRITE32_MEMBER(control_w);
- DECLARE_READ32_MEMBER(div_remainder_r);
- DECLARE_WRITE32_MEMBER(div_control_w);
+ u32 flags_r();
+ void flags_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ void matrix_control_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ void matrix_address_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ void end_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ void pc_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ u32 status_r();
+ void control_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ u32 div_remainder_r();
+ void div_control_w(u32 data);
// defines
inline void CLR_Z();
@@ -278,8 +278,8 @@ protected:
virtual void execute_run() override;
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
- DECLARE_WRITE32_MEMBER(hidata_w);
- DECLARE_READ32_MEMBER(hidata_r);
+ void hidata_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ u32 hidata_r();
};
@@ -296,9 +296,9 @@ protected:
virtual void execute_run() override;
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
- DECLARE_WRITE32_MEMBER(modulo_w);
- DECLARE_WRITE32_MEMBER(dsp_end_w);
- DECLARE_READ32_MEMBER(high_accum_r);
+ void modulo_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ void dsp_end_w(offs_t offset, u32 data, u32 mem_mask = ~0);
+ u32 high_accum_r();
};
diff --git a/src/devices/cpu/m6502/m3745x.cpp b/src/devices/cpu/m6502/m3745x.cpp
index 6d75dcfda15..218e16853ec 100644
--- a/src/devices/cpu/m6502/m3745x.cpp
+++ b/src/devices/cpu/m6502/m3745x.cpp
@@ -243,7 +243,7 @@ uint8_t m3745x_device::read_port(uint8_t offset)
return incoming;
}
-READ8_MEMBER(m3745x_device::ports_r)
+uint8_t m3745x_device::ports_r(offs_t offset)
{
switch (offset)
{
@@ -272,7 +272,7 @@ READ8_MEMBER(m3745x_device::ports_r)
return 0xff;
}
-WRITE8_MEMBER(m3745x_device::ports_w)
+void m3745x_device::ports_w(offs_t offset, uint8_t data)
{
switch (offset)
{
@@ -313,7 +313,7 @@ WRITE8_MEMBER(m3745x_device::ports_w)
}
}
-READ8_MEMBER(m3745x_device::intregs_r)
+uint8_t m3745x_device::intregs_r(offs_t offset)
{
switch (offset)
{
@@ -335,7 +335,7 @@ READ8_MEMBER(m3745x_device::intregs_r)
return 0;
}
-WRITE8_MEMBER(m3745x_device::intregs_w)
+void m3745x_device::intregs_w(offs_t offset, uint8_t data)
{
switch (offset)
{
@@ -359,7 +359,7 @@ WRITE8_MEMBER(m3745x_device::intregs_w)
recalc_irqs();
}
-READ8_MEMBER(m3745x_device::adc_r)
+uint8_t m3745x_device::adc_r(offs_t offset)
{
switch (offset)
{
@@ -375,7 +375,7 @@ READ8_MEMBER(m3745x_device::adc_r)
return 0;
}
-WRITE8_MEMBER(m3745x_device::adc_w)
+void m3745x_device::adc_w(offs_t offset, uint8_t data)
{
switch (offset)
{
diff --git a/src/devices/cpu/m6502/m3745x.h b/src/devices/cpu/m6502/m3745x.h
index ff31e3b5a23..92d31030236 100644
--- a/src/devices/cpu/m6502/m3745x.h
+++ b/src/devices/cpu/m6502/m3745x.h
@@ -44,12 +44,12 @@ public:
template<std::size_t Bit> auto write_p() { return m_write_p[Bit-3].bind(); }
template<std::size_t Bit> auto read_ad() { return m_read_ad[Bit].bind(); }
- DECLARE_READ8_MEMBER(ports_r);
- DECLARE_WRITE8_MEMBER(ports_w);
- DECLARE_READ8_MEMBER(adc_r);
- DECLARE_WRITE8_MEMBER(adc_w);
- DECLARE_READ8_MEMBER(intregs_r);
- DECLARE_WRITE8_MEMBER(intregs_w);
+ uint8_t ports_r(offs_t offset);
+ void ports_w(offs_t offset, uint8_t data);
+ uint8_t adc_r(offs_t offset);
+ void adc_w(offs_t offset, uint8_t data);
+ uint8_t intregs_r(offs_t offset);
+ void intregs_w(offs_t offset, uint8_t data);
bool are_port_bits_output(uint8_t port, uint8_t mask) { return ((m_ddrs[port] & mask) == mask) ? true : false; }
diff --git a/src/devices/cpu/m6502/m5074x.cpp b/src/devices/cpu/m6502/m5074x.cpp
index e3f6e43a967..794ef338e31 100644
--- a/src/devices/cpu/m6502/m5074x.cpp
+++ b/src/devices/cpu/m6502/m5074x.cpp
@@ -275,7 +275,7 @@ void m5074x_device::recalc_timer(int timer)
}
}
-void m5074x_device::send_port(address_space &space, uint8_t offset, uint8_t data)
+void m5074x_device::send_port(uint8_t offset, uint8_t data)
{
m_write_p[offset](data);
}
@@ -292,7 +292,7 @@ uint8_t m5074x_device::read_port(uint8_t offset)
return incoming;
}
-READ8_MEMBER(m5074x_device::ports_r)
+uint8_t m5074x_device::ports_r(offs_t offset)
{
switch (offset)
{
@@ -324,53 +324,53 @@ READ8_MEMBER(m5074x_device::ports_r)
return 0xff;
}
-WRITE8_MEMBER(m5074x_device::ports_w)
+void m5074x_device::ports_w(offs_t offset, uint8_t data)
{
switch (offset)
{
case 0: // p0
- send_port(space, 0, data & m_ddrs[0]);
+ send_port(0, data & m_ddrs[0]);
m_ports[0] = data;
break;
case 1: // p0 ddr
- send_port(space, 0, m_ports[0] & data);
+ send_port(0, m_ports[0] & data);
m_ddrs[0] = data;
break;
case 2: // p1
- send_port(space, 1, data & m_ddrs[1]);
+ send_port(1, data & m_ddrs[1]);
m_ports[1] = data;
break;
case 3: // p1 ddr
- send_port(space, 1, m_ports[1] & data);
+ send_port(1, m_ports[1] & data);
m_ddrs[1] = data;
break;
case 4: // p2
- send_port(space, 2, data & m_ddrs[2]);
+ send_port(2, data & m_ddrs[2]);
m_ports[2] = data;
break;
case 5: // p2 ddr
- send_port(space, 2, m_ports[2] & data);
+ send_port(2, m_ports[2] & data);
m_ddrs[2] = data;
break;
case 8: // p3
- send_port(space, 3, data & m_ddrs[3]);
+ send_port(3, data & m_ddrs[3]);
m_ports[3] = data;
break;
case 9: // p3 ddr
- send_port(space, 3, m_ports[3] & data);
+ send_port(3, m_ports[3] & data);
m_ddrs[3] = data;
break;
}
}
-READ8_MEMBER(m5074x_device::tmrirq_r)
+uint8_t m5074x_device::tmrirq_r(offs_t offset)
{
switch (offset)
{
@@ -399,7 +399,7 @@ READ8_MEMBER(m5074x_device::tmrirq_r)
return 0xff;
}
-WRITE8_MEMBER(m5074x_device::tmrirq_w)
+void m5074x_device::tmrirq_w(offs_t offset, uint8_t data)
{
// printf("%02x to tmrirq @ %d\n", data, offset);
diff --git a/src/devices/cpu/m6502/m5074x.h b/src/devices/cpu/m6502/m5074x.h
index d9b39f3cce3..165a7cc7599 100644
--- a/src/devices/cpu/m6502/m5074x.h
+++ b/src/devices/cpu/m6502/m5074x.h
@@ -48,10 +48,10 @@ public:
template <std::size_t Bit> auto read_p() { return m_read_p[Bit].bind(); }
template <std::size_t Bit> auto write_p() { return m_write_p[Bit].bind(); }
- DECLARE_READ8_MEMBER(ports_r);
- DECLARE_WRITE8_MEMBER(ports_w);
- DECLARE_READ8_MEMBER(tmrirq_r);
- DECLARE_WRITE8_MEMBER(tmrirq_w);
+ uint8_t ports_r(offs_t offset);
+ void ports_w(offs_t offset, uint8_t data);
+ uint8_t tmrirq_r(offs_t offset);
+ void tmrirq_w(offs_t offset, uint8_t data);
bool are_port_bits_output(uint8_t port, uint8_t mask) { return ((m_ddrs[port] & mask) == mask) ? true : false; }
@@ -66,7 +66,7 @@ protected:
virtual void execute_set_input(int inputnum, int state) override;
virtual space_config_vector memory_space_config() const override;
- void send_port(address_space &space, uint8_t offset, uint8_t data);
+ void send_port(uint8_t offset, uint8_t data);
uint8_t read_port(uint8_t offset);
void recalc_irqs();
diff --git a/src/devices/cpu/m6502/m6500_1.cpp b/src/devices/cpu/m6502/m6500_1.cpp
index d72c57bdd3a..5d7c2d0b485 100644
--- a/src/devices/cpu/m6502/m6500_1.cpp
+++ b/src/devices/cpu/m6502/m6500_1.cpp
@@ -108,17 +108,17 @@ void m6500_1_device::pa_w(uint8_t data)
machine().scheduler().synchronize(timer_expired_delegate(FUNC(m6500_1_device::set_port_in<0>), this), unsigned(data));
}
-WRITE8_MEMBER(m6500_1_device::pb_w)
+void m6500_1_device::pb_w(u8 data)
{
machine().scheduler().synchronize(timer_expired_delegate(FUNC(m6500_1_device::set_port_in<1>), this), unsigned(data));
}
-WRITE8_MEMBER(m6500_1_device::pc_w)
+void m6500_1_device::pc_w(u8 data)
{
machine().scheduler().synchronize(timer_expired_delegate(FUNC(m6500_1_device::set_port_in<2>), this), unsigned(data));
}
-WRITE8_MEMBER(m6500_1_device::pd_w)
+void m6500_1_device::pd_w(u8 data)
{
machine().scheduler().synchronize(timer_expired_delegate(FUNC(m6500_1_device::set_port_in<3>), this), unsigned(data));
}
@@ -272,13 +272,13 @@ void m6500_1_device::internal_update(u64 current_time)
}
-READ8_MEMBER(m6500_1_device::read_control_register)
+u8 m6500_1_device::read_control_register()
{
internal_update();
return m_cr;
}
-WRITE8_MEMBER(m6500_1_device::write_control_register)
+void m6500_1_device::write_control_register(u8 data)
{
internal_update();
m_cr = (m_cr & (CR_A1ED | CR_A0ED | CR_CTRO)) | (data & (CR_CMC0 | CR_CMC1 | CR_A1IE | CR_A0IE | CR_CIE));
@@ -294,7 +294,7 @@ void m6500_1_device::update_irq()
}
-READ8_MEMBER(m6500_1_device::read_port)
+u8 m6500_1_device::read_port(offs_t offset)
{
if (!machine().side_effects_disabled() && m_port_in_cb[offset])
{
@@ -314,7 +314,7 @@ READ8_MEMBER(m6500_1_device::read_port)
return m_port_in[offset] & m_port_buf[offset];
}
-WRITE8_MEMBER(m6500_1_device::write_port)
+void m6500_1_device::write_port(offs_t offset, u8 data)
{
u8 const prev(m_port_in[offset] & m_port_buf[offset]);
if (m_port_buf[offset] != data)
@@ -334,7 +334,7 @@ WRITE8_MEMBER(m6500_1_device::write_port)
}
}
-WRITE8_MEMBER(m6500_1_device::clear_edge)
+void m6500_1_device::clear_edge(offs_t offset, u8 data)
{
m_cr &= BIT(offset, 0) ? ~CR_A1ED : ~CR_A0ED;
update_irq();
@@ -357,13 +357,13 @@ template <unsigned Port> TIMER_CALLBACK_MEMBER(m6500_1_device::set_port_in)
}
-READ8_MEMBER(m6500_1_device::read_upper_count)
+u8 m6500_1_device::read_upper_count()
{
internal_update();
return u8(m_counter >> 8);
}
-READ8_MEMBER(m6500_1_device::read_lower_count)
+u8 m6500_1_device::read_lower_count()
{
internal_update();
if (!machine().side_effects_disabled())
@@ -375,7 +375,7 @@ READ8_MEMBER(m6500_1_device::read_lower_count)
return u8(m_counter);
}
-template <bool Transfer> WRITE8_MEMBER(m6500_1_device::write_upper_latch)
+template <bool Transfer> void m6500_1_device::write_upper_latch(u8 data)
{
m_latch = (m_latch & 0x00ffU) | u16(data << 8);
if (Transfer)
@@ -389,7 +389,7 @@ template <bool Transfer> WRITE8_MEMBER(m6500_1_device::write_upper_latch)
}
}
-WRITE8_MEMBER(m6500_1_device::write_lower_latch)
+void m6500_1_device::write_lower_latch(u8 data)
{
m_latch = (m_latch & 0xff00U) | u16(data);
}
diff --git a/src/devices/cpu/m6502/m6500_1.h b/src/devices/cpu/m6502/m6500_1.h
index 86f9621463b..0a4a07a6ff9 100644
--- a/src/devices/cpu/m6502/m6500_1.h
+++ b/src/devices/cpu/m6502/m6500_1.h
@@ -56,14 +56,14 @@ public:
auto pd_out_cb() { return m_port_out_cb[3].bind(); }
auto cntr_out_cb() { return m_cntr_out_cb.bind(); }
- DECLARE_READ8_MEMBER(pa_r) { return m_port_buf[0]; }
- DECLARE_READ8_MEMBER(pb_r) { return m_port_buf[1]; }
- DECLARE_READ8_MEMBER(pc_r) { return m_port_buf[2]; }
- DECLARE_READ8_MEMBER(pd_r) { return m_port_buf[3]; }
- void pa_w(uint8_t data);
- DECLARE_WRITE8_MEMBER(pb_w);
- DECLARE_WRITE8_MEMBER(pc_w);
- DECLARE_WRITE8_MEMBER(pd_w);
+ u8 pa_r() { return m_port_buf[0]; }
+ u8 pb_r() { return m_port_buf[1]; }
+ u8 pc_r() { return m_port_buf[2]; }
+ u8 pd_r() { return m_port_buf[3]; }
+ void pa_w(u8 data);
+ void pb_w(u8 data);
+ void pc_w(u8 data);
+ void pd_w(u8 data);
DECLARE_WRITE_LINE_MEMBER(cntr_w);
@@ -90,19 +90,19 @@ protected:
virtual void internal_update(u64 current_time) override;
using m6502_mcu_device::internal_update;
- DECLARE_READ8_MEMBER(read_control_register);
- DECLARE_WRITE8_MEMBER(write_control_register);
+ u8 read_control_register();
+ void write_control_register(u8 data);
void update_irq();
- DECLARE_READ8_MEMBER(read_port);
- DECLARE_WRITE8_MEMBER(write_port);
- DECLARE_WRITE8_MEMBER(clear_edge);
+ u8 read_port(offs_t offset);
+ void write_port(offs_t offset, u8 data);
+ void clear_edge(offs_t offset, u8 data);
template <unsigned Port> TIMER_CALLBACK_MEMBER(set_port_in);
- DECLARE_READ8_MEMBER(read_upper_count);
- DECLARE_READ8_MEMBER(read_lower_count);
- template <bool Transfer> DECLARE_WRITE8_MEMBER(write_upper_latch);
- DECLARE_WRITE8_MEMBER(write_lower_latch);
+ u8 read_upper_count();
+ u8 read_lower_count();
+ template <bool Transfer> void write_upper_latch(u8 data);
+ void write_lower_latch(u8 data);
u64 update_counter(u64 current_time);
bool should_count() const;
bool pulse_generator_mode() const;
diff --git a/src/devices/cpu/m6502/n2a03.cpp b/src/devices/cpu/m6502/n2a03.cpp
index b4c05185441..f303f1bf1b6 100644
--- a/src/devices/cpu/m6502/n2a03.cpp
+++ b/src/devices/cpu/m6502/n2a03.cpp
@@ -14,22 +14,22 @@
DEFINE_DEVICE_TYPE(N2A03, n2a03_device, "n2a03", "Ricoh N2A03")
-READ8_MEMBER(n2a03_device::psg1_4014_r)
+uint8_t n2a03_device::psg1_4014_r()
{
return m_apu->read(0x14);
}
-READ8_MEMBER(n2a03_device::psg1_4015_r)
+uint8_t n2a03_device::psg1_4015_r()
{
return m_apu->read(0x15);
}
-WRITE8_MEMBER(n2a03_device::psg1_4015_w)
+void n2a03_device::psg1_4015_w(uint8_t data)
{
m_apu->write(0x15, data);
}
-WRITE8_MEMBER(n2a03_device::psg1_4017_w)
+void n2a03_device::psg1_4017_w(uint8_t data)
{
m_apu->write(0x17, data);
}
diff --git a/src/devices/cpu/m6502/n2a03.h b/src/devices/cpu/m6502/n2a03.h
index 2eb1128665b..5a57bcbed2b 100644
--- a/src/devices/cpu/m6502/n2a03.h
+++ b/src/devices/cpu/m6502/n2a03.h
@@ -24,10 +24,10 @@ public:
virtual void do_exec_full() override;
virtual void do_exec_partial() override;
- READ8_MEMBER(psg1_4014_r);
- READ8_MEMBER(psg1_4015_r);
- WRITE8_MEMBER(psg1_4015_w);
- WRITE8_MEMBER(psg1_4017_w);
+ uint8_t psg1_4014_r();
+ uint8_t psg1_4015_r();
+ void psg1_4015_w(uint8_t data);
+ void psg1_4017_w(uint8_t data);
void n2a03_map(address_map &map);
protected:
diff --git a/src/devices/cpu/m6805/m68705.cpp b/src/devices/cpu/m6805/m68705.cpp
index 12e3b8d1384..067cd06b811 100644
--- a/src/devices/cpu/m6805/m68705.cpp
+++ b/src/devices/cpu/m6805/m68705.cpp
@@ -239,7 +239,7 @@ m68705_device::m68705_device(machine_config const &mconfig, char const *tag, dev
{
}
-template <offs_t B> READ8_MEMBER(m68705_device::eprom_r)
+template <offs_t B> u8 m68705_device::eprom_r(offs_t offset)
{
if (pcr_vpon() && !pcr_ple())
LOGEPROM("read EPROM %04X prevented when Vpp high and /PLE = 0\n", B + offset);
@@ -248,7 +248,7 @@ template <offs_t B> READ8_MEMBER(m68705_device::eprom_r)
return (!pcr_vpon() || !pcr_ple()) ? m_user_rom[B + offset] : 0xff;
}
-template <offs_t B> WRITE8_MEMBER(m68705_device::eprom_w)
+template <offs_t B> void m68705_device::eprom_w(offs_t offset, u8 data)
{
LOGEPROM("EPROM programming latch write%s%s: %04X = %02X\n",
!pcr_vpon() ? " [Vpp low]" : "", !pcr_ple() ? " [disabled]" : "", B + offset, data);
@@ -281,7 +281,7 @@ template <std::size_t N> void m6805_hmos_device::set_port_mask(u8 mask)
m_port_mask[N] = mask;
}
-template <std::size_t N> READ8_MEMBER(m6805_hmos_device::port_r)
+template <std::size_t N> u8 m6805_hmos_device::port_r()
{
if (!m_port_cb_r[N].isnull())
{
@@ -296,7 +296,7 @@ template <std::size_t N> READ8_MEMBER(m6805_hmos_device::port_r)
return m_port_mask[N] | (m_port_latch[N] & m_port_ddr[N]) | (m_port_input[N] & ~m_port_ddr[N]);
}
-template <std::size_t N> WRITE8_MEMBER(m6805_hmos_device::port_latch_w)
+template <std::size_t N> void m6805_hmos_device::port_latch_w(u8 data)
{
data &= ~m_port_mask[N];
u8 const diff = m_port_latch[N] ^ data;
@@ -307,7 +307,7 @@ template <std::size_t N> WRITE8_MEMBER(m6805_hmos_device::port_latch_w)
port_cb_w<N>();
}
-template <std::size_t N> WRITE8_MEMBER(m6805_hmos_device::port_ddr_w)
+template <std::size_t N> void m6805_hmos_device::port_ddr_w(u8 data)
{
data &= ~m_port_mask[N];
if (data != m_port_ddr[N])
@@ -325,12 +325,12 @@ template <std::size_t N> void m6805_hmos_device::port_cb_w()
m_port_cb_w[N](0, data, mask);
}
-READ8_MEMBER(m68705_device::pcr_r)
+u8 m68705_device::pcr_r()
{
return m_pcr;
}
-WRITE8_MEMBER(m68705_device::pcr_w)
+void m68705_device::pcr_w(u8 data)
{
// 7 1
// 6 1
@@ -358,13 +358,13 @@ WRITE8_MEMBER(m68705_device::pcr_w)
m_pcr = (m_pcr & 0xfc) | (data & 0x03);
}
-READ8_MEMBER(m6805_hmos_device::acr_r)
+u8 m6805_hmos_device::acr_r()
{
logerror("unsupported read ACR\n");
return 0xff;
}
-WRITE8_MEMBER(m6805_hmos_device::acr_w)
+void m6805_hmos_device::acr_w(u8 data)
{
// 7 conversion complete
// 6
@@ -392,13 +392,13 @@ WRITE8_MEMBER(m6805_hmos_device::acr_w)
logerror("unsupported write ACR = %02X\n", data);
}
-READ8_MEMBER(m6805_hmos_device::arr_r)
+u8 m6805_hmos_device::arr_r()
{
logerror("unsupported read ARR\n");
return 0xff;
}
-WRITE8_MEMBER(m6805_hmos_device::arr_w)
+void m6805_hmos_device::arr_w(u8 data)
{
logerror("unsupported write ARR = %02X\n", data);
}
@@ -463,10 +463,10 @@ void m6805_hmos_device::device_reset()
m6805_base_device::device_reset();
// reset digital I/O
- port_ddr_w<0>(space(AS_PROGRAM), 0, 0x00, 0xff);
- port_ddr_w<1>(space(AS_PROGRAM), 0, 0x00, 0xff);
- port_ddr_w<2>(space(AS_PROGRAM), 0, 0x00, 0xff);
- port_ddr_w<3>(space(AS_PROGRAM), 0, 0x00, 0xff);
+ port_ddr_w<0>(0x00);
+ port_ddr_w<1>(0x00);
+ port_ddr_w<2>(0x00);
+ port_ddr_w<3>(0x00);
// reset timer/counter
m_timer.reset();
diff --git a/src/devices/cpu/m6805/m68705.h b/src/devices/cpu/m6805/m68705.h
index d6998c08322..f6e02430acc 100644
--- a/src/devices/cpu/m6805/m68705.h
+++ b/src/devices/cpu/m6805/m68705.h
@@ -172,19 +172,19 @@ protected:
template <std::size_t N> void set_port_open_drain(bool value);
template <std::size_t N> void set_port_mask(u8 mask);
template <std::size_t N> void port_input_w(uint8_t data) { m_port_input[N] = data & ~m_port_mask[N]; }
- template <std::size_t N> DECLARE_READ8_MEMBER(port_r);
- template <std::size_t N> DECLARE_WRITE8_MEMBER(port_latch_w);
- template <std::size_t N> DECLARE_WRITE8_MEMBER(port_ddr_w);
+ template <std::size_t N> u8 port_r();
+ template <std::size_t N> void port_latch_w(u8 data);
+ template <std::size_t N> void port_ddr_w(u8 data);
template <std::size_t N> void port_cb_w();
- DECLARE_READ8_MEMBER(misc_r) { return m_mr; }
- DECLARE_WRITE8_MEMBER(misc_w) { m_mr = data; }
+ u8 misc_r() { return m_mr; }
+ void misc_w(u8 data) { m_mr = data; }
// A/D converter
- DECLARE_READ8_MEMBER(acr_r);
- DECLARE_WRITE8_MEMBER(acr_w);
- DECLARE_READ8_MEMBER(arr_r);
- DECLARE_WRITE8_MEMBER(arr_w);
+ u8 acr_r();
+ void acr_w(u8 data);
+ u8 arr_r();
+ void arr_w(u8 data);
virtual void device_start() override;
virtual void device_reset() override;
@@ -250,11 +250,11 @@ protected:
m68705_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock, device_type type, u32 addr_width, unsigned ram_size);
- template <offs_t B> DECLARE_READ8_MEMBER(eprom_r);
- template <offs_t B> DECLARE_WRITE8_MEMBER(eprom_w);
+ template <offs_t B> u8 eprom_r(offs_t offset);
+ template <offs_t B> void eprom_w(offs_t offset, u8 data);
- DECLARE_READ8_MEMBER(pcr_r);
- DECLARE_WRITE8_MEMBER(pcr_w);
+ u8 pcr_r();
+ void pcr_w(u8 data);
virtual void device_start() override;
virtual void device_reset() override;
diff --git a/src/devices/cpu/mips/ps2vif1.cpp b/src/devices/cpu/mips/ps2vif1.cpp
index 12b8185fe49..b12c39253e6 100644
--- a/src/devices/cpu/mips/ps2vif1.cpp
+++ b/src/devices/cpu/mips/ps2vif1.cpp
@@ -131,7 +131,7 @@ void ps2_vif1_device::device_reset()
m_unpack_format = FMT_S32;
}
-READ32_MEMBER(ps2_vif1_device::regs_r)
+uint32_t ps2_vif1_device::regs_r(offs_t offset)
{
uint32_t ret = 0;
switch (offset)
@@ -235,7 +235,7 @@ READ32_MEMBER(ps2_vif1_device::regs_r)
return ret;
}
-WRITE32_MEMBER(ps2_vif1_device::regs_w)
+void ps2_vif1_device::regs_w(offs_t offset, uint32_t data)
{
logerror("%s: Write: Unknown %08x = %08x\n", machine().describe_context(), 0x10003c00 + (offset << 2), data);
}
diff --git a/src/devices/cpu/mips/ps2vif1.h b/src/devices/cpu/mips/ps2vif1.h
index 1c5ca79547b..171a3839f8f 100644
--- a/src/devices/cpu/mips/ps2vif1.h
+++ b/src/devices/cpu/mips/ps2vif1.h
@@ -36,8 +36,8 @@ public:
uint64_t mmio_r(offs_t offset);
void mmio_w(offs_t offset, uint64_t data);
- DECLARE_READ32_MEMBER(regs_r);
- DECLARE_WRITE32_MEMBER(regs_w);
+ uint32_t regs_r(offs_t offset);
+ void regs_w(offs_t offset, uint32_t data);
void dma_write(const uint64_t hi, const uint64_t lo);
void tag_write(uint32_t *data);
diff --git a/src/devices/cpu/mips/ps2vu.cpp b/src/devices/cpu/mips/ps2vu.cpp
index 1f7e579e0e9..473979587d8 100644
--- a/src/devices/cpu/mips/ps2vu.cpp
+++ b/src/devices/cpu/mips/ps2vu.cpp
@@ -975,12 +975,12 @@ void sonyvu0_device::device_reset()
m_cmsar1 = 0;
}
-READ32_MEMBER(sonyvu0_device::vu1_reg_r)
+uint32_t sonyvu0_device::vu1_reg_r(offs_t offset)
{
return m_vu1_regs[offset];
}
-WRITE32_MEMBER(sonyvu0_device::vu1_reg_w)
+void sonyvu0_device::vu1_reg_w(offs_t offset, uint32_t data)
{
m_vu1_regs[offset] = data;
}
diff --git a/src/devices/cpu/mips/ps2vu.h b/src/devices/cpu/mips/ps2vu.h
index c8d7c7b97e6..cc898ffa58d 100644
--- a/src/devices/cpu/mips/ps2vu.h
+++ b/src/devices/cpu/mips/ps2vu.h
@@ -230,8 +230,8 @@ protected:
void execute_xgkick(uint32_t rs) override;
- DECLARE_READ32_MEMBER(vu1_reg_r);
- DECLARE_WRITE32_MEMBER(vu1_reg_w);
+ uint32_t vu1_reg_r(offs_t offset);
+ void vu1_reg_w(offs_t offset, uint32_t data);
required_device<sonyvu1_device> m_vu1;
diff --git a/src/devices/cpu/pps4/pps4.cpp b/src/devices/cpu/pps4/pps4.cpp
index 7f0b9ba70dd..9de3131ba19 100644
--- a/src/devices/cpu/pps4/pps4.cpp
+++ b/src/devices/cpu/pps4/pps4.cpp
@@ -1656,7 +1656,7 @@ void pps4_2_device::device_reset()
m_DIO = 15; // DIO clamp
}
-READ16_MEMBER(pps4_device::address_bus_r)
+u16 pps4_device::address_bus_r(address_space &space)
{
int id = space.spacenum();
if (id == AS_IO || id == AS_DATA)
diff --git a/src/devices/cpu/pps4/pps4.h b/src/devices/cpu/pps4/pps4.h
index f4047e68e99..ab6e58c5554 100644
--- a/src/devices/cpu/pps4/pps4.h
+++ b/src/devices/cpu/pps4/pps4.h
@@ -47,7 +47,7 @@ public:
auto dib_cb() { return m_dib_cb.bind(); }
auto do_cb() { return m_do_cb.bind(); }
- DECLARE_READ16_MEMBER(address_bus_r);
+ u16 address_bus_r(address_space &space);
protected:
pps4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
diff --git a/src/devices/cpu/psx/dma.cpp b/src/devices/cpu/psx/dma.cpp
index 5ec8e29fdbd..36078c5b499 100644
--- a/src/devices/cpu/psx/dma.cpp
+++ b/src/devices/cpu/psx/dma.cpp
@@ -211,7 +211,7 @@ void psxdma_device::install_write_handler( int index, write_delegate p_fn_dma_wr
m_channel[ index ].fn_write = p_fn_dma_write;
}
-WRITE32_MEMBER( psxdma_device::write )
+void psxdma_device::write(offs_t offset, uint32_t data, uint32_t mem_mask)
{
int index = offset / 4;
psx_dma_channel *dma = &m_channel[ index ];
@@ -382,7 +382,7 @@ WRITE32_MEMBER( psxdma_device::write )
}
}
-READ32_MEMBER( psxdma_device::read )
+uint32_t psxdma_device::read(offs_t offset, uint32_t mem_mask)
{
int index = offset / 4;
psx_dma_channel *dma = &m_channel[ index ];
diff --git a/src/devices/cpu/psx/dma.h b/src/devices/cpu/psx/dma.h
index 3e368c23ad3..1bd743614b2 100644
--- a/src/devices/cpu/psx/dma.h
+++ b/src/devices/cpu/psx/dma.h
@@ -29,8 +29,8 @@ public:
void install_read_handler( int n_channel, read_delegate p_fn_dma_read );
void install_write_handler( int n_channel, write_delegate p_fn_dma_write );
- DECLARE_WRITE32_MEMBER( write );
- DECLARE_READ32_MEMBER( read );
+ void write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t read(offs_t offset, uint32_t mem_mask = ~0);
uint32_t *m_ram;
size_t m_ramsize;
diff --git a/src/devices/cpu/psx/irq.cpp b/src/devices/cpu/psx/irq.cpp
index 94aafc73b2f..ace6d69d4e6 100644
--- a/src/devices/cpu/psx/irq.cpp
+++ b/src/devices/cpu/psx/irq.cpp
@@ -78,7 +78,7 @@ void psxirq_device::psx_irq_update( void )
}
}
-WRITE32_MEMBER( psxirq_device::write )
+void psxirq_device::write(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch( offset )
{
@@ -102,7 +102,7 @@ WRITE32_MEMBER( psxirq_device::write )
}
}
-READ32_MEMBER( psxirq_device::read )
+uint32_t psxirq_device::read(offs_t offset)
{
switch( offset )
{
diff --git a/src/devices/cpu/psx/irq.h b/src/devices/cpu/psx/irq.h
index 11d637921f7..b4ee28e712a 100644
--- a/src/devices/cpu/psx/irq.h
+++ b/src/devices/cpu/psx/irq.h
@@ -23,8 +23,8 @@ public:
// configuration helpers
auto irq() { return m_irq_handler.bind(); }
- DECLARE_READ32_MEMBER( read );
- DECLARE_WRITE32_MEMBER( write );
+ uint32_t read(offs_t offset);
+ void write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
DECLARE_WRITE_LINE_MEMBER( intin0 );
DECLARE_WRITE_LINE_MEMBER( intin1 );
diff --git a/src/devices/cpu/psx/mdec.cpp b/src/devices/cpu/psx/mdec.cpp
index 6a177255da9..826005a52d4 100644
--- a/src/devices/cpu/psx/mdec.cpp
+++ b/src/devices/cpu/psx/mdec.cpp
@@ -542,7 +542,7 @@ void psxmdec_device::dma_read( uint32_t *p_n_psxram, uint32_t n_address, int32_t
n_1_status &= ~( 1L << 29 );
}
-WRITE32_MEMBER( psxmdec_device::write )
+void psxmdec_device::write(offs_t offset, uint32_t data)
{
switch( offset )
{
@@ -557,7 +557,7 @@ WRITE32_MEMBER( psxmdec_device::write )
}
}
-READ32_MEMBER( psxmdec_device::read )
+uint32_t psxmdec_device::read(offs_t offset)
{
switch( offset )
{
diff --git a/src/devices/cpu/psx/mdec.h b/src/devices/cpu/psx/mdec.h
index 941ba2f2f58..8d9da890069 100644
--- a/src/devices/cpu/psx/mdec.h
+++ b/src/devices/cpu/psx/mdec.h
@@ -20,8 +20,8 @@ class psxmdec_device : public device_t
public:
psxmdec_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_WRITE32_MEMBER( write );
- DECLARE_READ32_MEMBER( read );
+ void write(offs_t offset, uint32_t data);
+ uint32_t read(offs_t offset);
void dma_write( uint32_t *ram, uint32_t n_address, int32_t n_size );
void dma_read( uint32_t *ram, uint32_t n_address, int32_t n_size );
diff --git a/src/devices/cpu/psx/psx.cpp b/src/devices/cpu/psx/psx.cpp
index 36f390df5d4..174eb4298d8 100644
--- a/src/devices/cpu/psx/psx.cpp
+++ b/src/devices/cpu/psx/psx.cpp
@@ -205,25 +205,25 @@ static const uint32_t mtc0_writemask[]=
0x00000000 /* PRID */
};
-READ32_MEMBER( psxcpu_device::berr_r )
+uint32_t psxcpu_device::berr_r()
{
if( !machine().side_effects_disabled() )
m_berr = 1;
return 0;
}
-WRITE32_MEMBER( psxcpu_device::berr_w )
+void psxcpu_device::berr_w(uint32_t data)
{
if( !machine().side_effects_disabled() )
m_berr = 1;
}
-READ32_MEMBER( psxcpu_device::exp_base_r )
+uint32_t psxcpu_device::exp_base_r()
{
return m_exp_base;
}
-WRITE32_MEMBER( psxcpu_device::exp_base_w )
+void psxcpu_device::exp_base_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA( &m_exp_base ); // TODO: check byte writes
@@ -235,24 +235,24 @@ uint32_t psxcpu_device::exp_base()
return m_exp_base;
}
-READ32_MEMBER( psxcpu_device::exp_config_r )
+uint32_t psxcpu_device::exp_config_r()
{
return m_exp_config;
}
-WRITE32_MEMBER( psxcpu_device::exp_config_w )
+void psxcpu_device::exp_config_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA( &m_exp_config ); // TODO: check byte writes
m_exp_config &= 0xaf1fffff;
}
-READ32_MEMBER( psxcpu_device::ram_config_r )
+uint32_t psxcpu_device::ram_config_r()
{
return m_ram_config;
}
-WRITE32_MEMBER( psxcpu_device::ram_config_w )
+void psxcpu_device::ram_config_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
uint32_t old = m_ram_config;
@@ -264,12 +264,12 @@ WRITE32_MEMBER( psxcpu_device::ram_config_w )
}
}
-READ32_MEMBER( psxcpu_device::rom_config_r )
+uint32_t psxcpu_device::rom_config_r()
{
return m_rom_config;
}
-WRITE32_MEMBER( psxcpu_device::rom_config_w )
+void psxcpu_device::rom_config_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
uint32_t old = m_rom_config;
@@ -281,24 +281,24 @@ WRITE32_MEMBER( psxcpu_device::rom_config_w )
}
}
-READ32_MEMBER( psxcpu_device::com_delay_r )
+uint32_t psxcpu_device::com_delay_r(offs_t offset, uint32_t mem_mask)
{
//verboselog( p_psx, 1, "psx_com_delay_r( %08x )\n", mem_mask );
return m_com_delay;
}
-WRITE32_MEMBER( psxcpu_device::com_delay_w )
+void psxcpu_device::com_delay_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA( &m_com_delay ); // TODO: check byte writes
//verboselog( p_psx, 1, "psx_com_delay_w( %08x %08x )\n", data, mem_mask );
}
-READ32_MEMBER( psxcpu_device::biu_r )
+uint32_t psxcpu_device::biu_r()
{
return m_biu;
}
-WRITE32_MEMBER( psxcpu_device::biu_w )
+void psxcpu_device::biu_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
uint32_t old = m_biu;
@@ -1338,11 +1338,11 @@ void psxcpu_device::update_scratchpad()
{
if( ( m_biu & BIU_RAM ) == 0 )
{
- m_program->install_readwrite_handler( 0x1f800000, 0x1f8003ff, read32_delegate(*this, FUNC(psxcpu_device::berr_r)), write32_delegate(*this, FUNC(psxcpu_device::berr_w)) );
+ m_program->install_readwrite_handler( 0x1f800000, 0x1f8003ff, read32smo_delegate(*this, FUNC(psxcpu_device::berr_r)), write32smo_delegate(*this, FUNC(psxcpu_device::berr_w)) );
}
else if( ( m_biu & BIU_DS ) == 0 )
{
- m_program->install_read_handler( 0x1f800000, 0x1f8003ff, read32_delegate(*this, FUNC(psxcpu_device::berr_r)) );
+ m_program->install_read_handler( 0x1f800000, 0x1f8003ff, read32smo_delegate(*this, FUNC(psxcpu_device::berr_r)) );
m_program->nop_write( 0x1f800000, 0x1f8003ff );
}
else
@@ -1397,9 +1397,9 @@ void psxcpu_device::update_ram_config()
}
}
- m_program->install_readwrite_handler( 0x00000000 + window_size, 0x1effffff, read32_delegate(*this, FUNC(psxcpu_device::berr_r)), write32_delegate(*this, FUNC(psxcpu_device::berr_w)) );
- m_program->install_readwrite_handler( 0x80000000 + window_size, 0x9effffff, read32_delegate(*this, FUNC(psxcpu_device::berr_r)), write32_delegate(*this, FUNC(psxcpu_device::berr_w)) );
- m_program->install_readwrite_handler( 0xa0000000 + window_size, 0xbeffffff, read32_delegate(*this, FUNC(psxcpu_device::berr_r)), write32_delegate(*this, FUNC(psxcpu_device::berr_w)) );
+ m_program->install_readwrite_handler( 0x00000000 + window_size, 0x1effffff, read32smo_delegate(*this, FUNC(psxcpu_device::berr_r)), write32smo_delegate(*this, FUNC(psxcpu_device::berr_w)) );
+ m_program->install_readwrite_handler( 0x80000000 + window_size, 0x9effffff, read32smo_delegate(*this, FUNC(psxcpu_device::berr_r)), write32smo_delegate(*this, FUNC(psxcpu_device::berr_w)) );
+ m_program->install_readwrite_handler( 0xa0000000 + window_size, 0xbeffffff, read32smo_delegate(*this, FUNC(psxcpu_device::berr_r)), write32smo_delegate(*this, FUNC(psxcpu_device::berr_w)) );
}
void psxcpu_device::update_rom_config()
@@ -1434,9 +1434,9 @@ void psxcpu_device::update_rom_config()
if( window_size < max_window_size && !m_disable_rom_berr)
{
- m_program->install_readwrite_handler( 0x1fc00000 + window_size, 0x1fffffff, read32_delegate(*this, FUNC(psxcpu_device::berr_r)), write32_delegate(*this, FUNC(psxcpu_device::berr_w)) );
- m_program->install_readwrite_handler( 0x9fc00000 + window_size, 0x9fffffff, read32_delegate(*this, FUNC(psxcpu_device::berr_r)), write32_delegate(*this, FUNC(psxcpu_device::berr_w)) );
- m_program->install_readwrite_handler( 0xbfc00000 + window_size, 0xbfffffff, read32_delegate(*this, FUNC(psxcpu_device::berr_r)), write32_delegate(*this, FUNC(psxcpu_device::berr_w)) );
+ m_program->install_readwrite_handler( 0x1fc00000 + window_size, 0x1fffffff, read32smo_delegate(*this, FUNC(psxcpu_device::berr_r)), write32smo_delegate(*this, FUNC(psxcpu_device::berr_w)) );
+ m_program->install_readwrite_handler( 0x9fc00000 + window_size, 0x9fffffff, read32smo_delegate(*this, FUNC(psxcpu_device::berr_r)), write32smo_delegate(*this, FUNC(psxcpu_device::berr_w)) );
+ m_program->install_readwrite_handler( 0xbfc00000 + window_size, 0xbfffffff, read32smo_delegate(*this, FUNC(psxcpu_device::berr_r)), write32smo_delegate(*this, FUNC(psxcpu_device::berr_w)) );
}
}
@@ -3401,32 +3401,32 @@ void psxcpu_device::setcp3cr( int reg, uint32_t value )
{
}
-READ32_MEMBER( psxcpu_device::gpu_r )
+uint32_t psxcpu_device::gpu_r(offs_t offset, uint32_t mem_mask)
{
return m_gpu_read_handler( offset, mem_mask );
}
-WRITE32_MEMBER( psxcpu_device::gpu_w )
+void psxcpu_device::gpu_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
m_gpu_write_handler( offset, data, mem_mask );
}
-READ16_MEMBER( psxcpu_device::spu_r )
+uint16_t psxcpu_device::spu_r(offs_t offset, uint16_t mem_mask)
{
return m_spu_read_handler( offset, mem_mask );
}
-WRITE16_MEMBER( psxcpu_device::spu_w )
+void psxcpu_device::spu_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
m_spu_write_handler( offset, data, mem_mask );
}
-READ8_MEMBER( psxcpu_device::cd_r )
+uint8_t psxcpu_device::cd_r(offs_t offset, uint8_t mem_mask)
{
return m_cd_read_handler( offset, mem_mask );
}
-WRITE8_MEMBER( psxcpu_device::cd_w )
+void psxcpu_device::cd_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
m_cd_write_handler( offset, data, mem_mask );
}
diff --git a/src/devices/cpu/psx/psx.h b/src/devices/cpu/psx/psx.h
index 57be9a19de9..e02c4471bae 100644
--- a/src/devices/cpu/psx/psx.h
+++ b/src/devices/cpu/psx/psx.h
@@ -128,37 +128,37 @@ public:
auto cd_write() { return m_cd_write_handler.bind(); }
// public interfaces
- DECLARE_WRITE32_MEMBER( berr_w );
- DECLARE_READ32_MEMBER( berr_r );
+ void berr_w(uint32_t data);
+ uint32_t berr_r();
uint32_t exp_base();
- DECLARE_WRITE32_MEMBER( exp_base_w );
- DECLARE_READ32_MEMBER( exp_base_r );
+ void exp_base_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t exp_base_r();
- DECLARE_WRITE32_MEMBER( exp_config_w );
- DECLARE_READ32_MEMBER( exp_config_r );
+ void exp_config_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t exp_config_r();
- DECLARE_WRITE32_MEMBER( ram_config_w );
- DECLARE_READ32_MEMBER( ram_config_r );
+ void ram_config_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t ram_config_r();
- DECLARE_WRITE32_MEMBER( rom_config_w );
- DECLARE_READ32_MEMBER( rom_config_r );
+ void rom_config_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t rom_config_r();
- DECLARE_WRITE32_MEMBER( biu_w );
- DECLARE_READ32_MEMBER( biu_r );
+ void biu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t biu_r();
- DECLARE_WRITE32_MEMBER( gpu_w );
- DECLARE_READ32_MEMBER( gpu_r );
+ void gpu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t gpu_r(offs_t offset, uint32_t mem_mask = ~0);
- DECLARE_WRITE16_MEMBER( spu_w );
- DECLARE_READ16_MEMBER( spu_r );
+ void spu_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t spu_r(offs_t offset, uint16_t mem_mask = ~0);
- DECLARE_WRITE8_MEMBER( cd_w );
- DECLARE_READ8_MEMBER( cd_r );
+ void cd_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0);
+ uint8_t cd_r(offs_t offset, uint8_t mem_mask = ~0);
- DECLARE_WRITE32_MEMBER( com_delay_w );
- DECLARE_READ32_MEMBER( com_delay_r );
+ void com_delay_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t com_delay_r(offs_t offset, uint32_t mem_mask = ~0);
static psxcpu_device *getcpu( device_t &device, const char *cputag ) { return downcast<psxcpu_device *>( device.subdevice( cputag ) ); }
void set_disable_rom_berr(bool mode);
diff --git a/src/devices/cpu/psx/rcnt.cpp b/src/devices/cpu/psx/rcnt.cpp
index e0ac985fa0a..37932db2d8d 100644
--- a/src/devices/cpu/psx/rcnt.cpp
+++ b/src/devices/cpu/psx/rcnt.cpp
@@ -70,7 +70,7 @@ void psxrcnt_device::device_start()
}
}
-WRITE32_MEMBER( psxrcnt_device::write )
+void psxrcnt_device::write(offs_t offset, uint32_t data, uint32_t mem_mask)
{
int n_counter = offset / 4;
psx_root *root = &root_counter[ n_counter ];
@@ -115,7 +115,7 @@ WRITE32_MEMBER( psxrcnt_device::write )
root_timer_adjust( n_counter );
}
-READ32_MEMBER( psxrcnt_device::read )
+uint32_t psxrcnt_device::read(offs_t offset, uint32_t mem_mask)
{
int n_counter = offset / 4;
psx_root *root = &root_counter[ n_counter ];
diff --git a/src/devices/cpu/psx/rcnt.h b/src/devices/cpu/psx/rcnt.h
index b6e4e46dab9..4e44e365466 100644
--- a/src/devices/cpu/psx/rcnt.h
+++ b/src/devices/cpu/psx/rcnt.h
@@ -34,8 +34,8 @@ public:
auto irq1() { return m_irq1_handler.bind(); }
auto irq2() { return m_irq2_handler.bind(); }
- DECLARE_WRITE32_MEMBER( write );
- DECLARE_READ32_MEMBER( read );
+ void write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t read(offs_t offset, uint32_t mem_mask = ~0);
protected:
virtual void device_start() override;
diff --git a/src/devices/cpu/psx/sio.cpp b/src/devices/cpu/psx/sio.cpp
index 5ff3e671109..2fac592bb59 100644
--- a/src/devices/cpu/psx/sio.cpp
+++ b/src/devices/cpu/psx/sio.cpp
@@ -209,7 +209,7 @@ void psxsio_device::device_timer(emu_timer &timer, device_timer_id tid, int para
sio_timer_adjust();
}
-WRITE32_MEMBER( psxsio_device::write )
+void psxsio_device::write(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch( offset % 4 )
{
@@ -285,7 +285,7 @@ WRITE32_MEMBER( psxsio_device::write )
}
}
-READ32_MEMBER( psxsio_device::read )
+uint32_t psxsio_device::read(offs_t offset, uint32_t mem_mask)
{
uint32_t data;
diff --git a/src/devices/cpu/psx/sio.h b/src/devices/cpu/psx/sio.h
index 7e02b57330f..3662ea01a53 100644
--- a/src/devices/cpu/psx/sio.h
+++ b/src/devices/cpu/psx/sio.h
@@ -43,8 +43,8 @@ public:
auto dtr_handler() { return m_dtr_handler.bind(); }
auto rts_handler() { return m_rts_handler.bind(); }
- DECLARE_WRITE32_MEMBER( write );
- DECLARE_READ32_MEMBER( read );
+ void write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t read(offs_t offset, uint32_t mem_mask = ~0);
DECLARE_WRITE_LINE_MEMBER(write_rxd);
DECLARE_WRITE_LINE_MEMBER(write_dsr);
diff --git a/src/devices/cpu/scudsp/scudsp.cpp b/src/devices/cpu/scudsp/scudsp.cpp
index 920d75ac4f5..7db8e88cb80 100644
--- a/src/devices/cpu/scudsp/scudsp.cpp
+++ b/src/devices/cpu/scudsp/scudsp.cpp
@@ -340,12 +340,12 @@ uint32_t scudsp_cpu_device::scudsp_get_mem_source_dma( uint32_t memcode, uint32_
}
-READ32_MEMBER( scudsp_cpu_device::program_control_r )
+uint32_t scudsp_cpu_device::program_control_r()
{
return (m_pc & 0xff) | (m_flags & FLAGS_MASK);
}
-WRITE32_MEMBER( scudsp_cpu_device::program_control_w )
+void scudsp_cpu_device::program_control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
uint32_t oldval, newval;
@@ -362,13 +362,13 @@ WRITE32_MEMBER( scudsp_cpu_device::program_control_w )
set_input_line(INPUT_LINE_RESET, (EXF) ? CLEAR_LINE : ASSERT_LINE);
}
-WRITE32_MEMBER( scudsp_cpu_device::program_w )
+void scudsp_cpu_device::program_w(uint32_t data)
{
//printf("%02x %08x PRG\n",m_pc,data);
scudsp_writeop(m_pc++, data);
}
-WRITE32_MEMBER( scudsp_cpu_device::ram_address_control_w )
+void scudsp_cpu_device::ram_address_control_w(uint32_t data)
{
//printf("%02x %08x PRG\n",m_pc,data);
m_ra = data & 0xff;
@@ -382,7 +382,7 @@ WRITE32_MEMBER( scudsp_cpu_device::ram_address_control_w )
}
}
-READ32_MEMBER( scudsp_cpu_device::ram_address_r )
+uint32_t scudsp_cpu_device::ram_address_r()
{
uint32_t data;
@@ -391,7 +391,7 @@ READ32_MEMBER( scudsp_cpu_device::ram_address_r )
return data;
}
-WRITE32_MEMBER( scudsp_cpu_device::ram_address_w )
+void scudsp_cpu_device::ram_address_w(uint32_t data)
{
scudsp_set_dest_mem_reg( (m_ra & 0xc0) >> 6, data );
}
diff --git a/src/devices/cpu/scudsp/scudsp.h b/src/devices/cpu/scudsp/scudsp.h
index 963a2d63871..eba4ed5903c 100644
--- a/src/devices/cpu/scudsp/scudsp.h
+++ b/src/devices/cpu/scudsp/scudsp.h
@@ -49,15 +49,15 @@ public:
auto out_dma_callback() { return m_out_dma_cb.bind(); }
/* port 0 */
- DECLARE_READ32_MEMBER( program_control_r );
- DECLARE_WRITE32_MEMBER( program_control_w );
+ uint32_t program_control_r();
+ void program_control_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
/* port 1 */
- DECLARE_WRITE32_MEMBER( program_w );
+ void program_w(uint32_t data);
/* port 2 */
- DECLARE_WRITE32_MEMBER( ram_address_control_w );
+ void ram_address_control_w(uint32_t data);
/* port 3 */
- DECLARE_READ32_MEMBER( ram_address_r );
- DECLARE_WRITE32_MEMBER( ram_address_w );
+ uint32_t ram_address_r();
+ void ram_address_w(uint32_t data);
void data_map(address_map &map);
void program_map(address_map &map);
diff --git a/src/devices/cpu/sh/sh2.cpp b/src/devices/cpu/sh/sh2.cpp
index 9d1014f1648..d46a2f5fdc0 100644
--- a/src/devices/cpu/sh/sh2.cpp
+++ b/src/devices/cpu/sh/sh2.cpp
@@ -113,7 +113,7 @@ DEFINE_DEVICE_TYPE(SH2A, sh2a_device, "sh21", "Hitachi SH-2A")
SH2 internal map
-------------------------------------------------*/
-READ32_MEMBER(sh2_device::sh2_internal_a5)
+uint32_t sh2_device::sh2_internal_a5()
{
return 0xa5a5a5a5;
}
diff --git a/src/devices/cpu/sh/sh2.h b/src/devices/cpu/sh/sh2.h
index 8eaad7ad6c4..c0ba7340d8b 100644
--- a/src/devices/cpu/sh/sh2.h
+++ b/src/devices/cpu/sh/sh2.h
@@ -66,92 +66,92 @@ public:
template <typename... T> void set_ftcsr_read_callback(T &&... args) { m_ftcsr_read_cb.set(std::forward<T>(args)...); }
- DECLARE_READ32_MEMBER(sh2_internal_a5);
+ uint32_t sh2_internal_a5();
// SCI
- DECLARE_READ8_MEMBER( smr_r );
- DECLARE_WRITE8_MEMBER( smr_w );
- DECLARE_READ8_MEMBER( brr_r );
- DECLARE_WRITE8_MEMBER( brr_w );
- DECLARE_READ8_MEMBER( scr_r );
- DECLARE_WRITE8_MEMBER( scr_w );
- DECLARE_READ8_MEMBER( tdr_r );
- DECLARE_WRITE8_MEMBER( tdr_w );
- DECLARE_READ8_MEMBER( ssr_r );
- DECLARE_WRITE8_MEMBER( ssr_w );
- DECLARE_READ8_MEMBER( rdr_r );
+ uint8_t smr_r();
+ void smr_w(uint8_t data);
+ uint8_t brr_r();
+ void brr_w(uint8_t data);
+ uint8_t scr_r();
+ void scr_w(uint8_t data);
+ uint8_t tdr_r();
+ void tdr_w(uint8_t data);
+ uint8_t ssr_r();
+ void ssr_w(uint8_t data);
+ uint8_t rdr_r();
// FRT / FRC
- DECLARE_READ8_MEMBER( tier_r );
- DECLARE_WRITE8_MEMBER( tier_w );
- DECLARE_READ16_MEMBER( frc_r );
- DECLARE_WRITE16_MEMBER( frc_w );
- DECLARE_READ8_MEMBER( ftcsr_r );
- DECLARE_WRITE8_MEMBER( ftcsr_w );
- DECLARE_READ16_MEMBER( ocra_b_r );
- DECLARE_WRITE16_MEMBER( ocra_b_w );
- DECLARE_READ8_MEMBER( frc_tcr_r );
- DECLARE_WRITE8_MEMBER( frc_tcr_w );
- DECLARE_READ8_MEMBER( tocr_r );
- DECLARE_WRITE8_MEMBER( tocr_w );
- DECLARE_READ16_MEMBER( frc_icr_r );
+ uint8_t tier_r();
+ void tier_w(uint8_t data);
+ uint16_t frc_r();
+ void frc_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint8_t ftcsr_r();
+ void ftcsr_w(uint8_t data);
+ uint16_t ocra_b_r();
+ void ocra_b_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint8_t frc_tcr_r();
+ void frc_tcr_w(uint8_t data);
+ uint8_t tocr_r();
+ void tocr_w(uint8_t data);
+ uint16_t frc_icr_r();
// INTC
- DECLARE_READ16_MEMBER( ipra_r );
- DECLARE_WRITE16_MEMBER( ipra_w );
- DECLARE_READ16_MEMBER( iprb_r );
- DECLARE_WRITE16_MEMBER( iprb_w );
- DECLARE_READ16_MEMBER( vcra_r );
- DECLARE_WRITE16_MEMBER( vcra_w );
- DECLARE_READ16_MEMBER( vcrb_r );
- DECLARE_WRITE16_MEMBER( vcrb_w );
- DECLARE_READ16_MEMBER( vcrc_r );
- DECLARE_WRITE16_MEMBER( vcrc_w );
- DECLARE_READ16_MEMBER( vcrd_r );
- DECLARE_WRITE16_MEMBER( vcrd_w );
- DECLARE_READ16_MEMBER( vcrwdt_r );
- DECLARE_WRITE16_MEMBER( vcrwdt_w );
- DECLARE_READ32_MEMBER( vcrdiv_r );
- DECLARE_WRITE32_MEMBER( vcrdiv_w );
- DECLARE_READ16_MEMBER( intc_icr_r );
- DECLARE_WRITE16_MEMBER( intc_icr_w );
+ uint16_t ipra_r();
+ void ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t iprb_r();
+ void iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t vcra_r();
+ void vcra_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t vcrb_r();
+ void vcrb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t vcrc_r();
+ void vcrc_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t vcrd_r();
+ void vcrd_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t vcrwdt_r();
+ void vcrwdt_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint32_t vcrdiv_r();
+ void vcrdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint16_t intc_icr_r();
+ void intc_icr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
// DIVU
- DECLARE_READ32_MEMBER( dvsr_r );
- DECLARE_WRITE32_MEMBER( dvsr_w );
- DECLARE_READ32_MEMBER( dvdnt_r );
- DECLARE_WRITE32_MEMBER( dvdnt_w );
- DECLARE_READ32_MEMBER( dvdnth_r );
- DECLARE_WRITE32_MEMBER( dvdnth_w );
- DECLARE_READ32_MEMBER( dvdntl_r );
- DECLARE_WRITE32_MEMBER( dvdntl_w );
-
- DECLARE_READ32_MEMBER( dvcr_r );
- DECLARE_WRITE32_MEMBER( dvcr_w );
+ uint32_t dvsr_r();
+ void dvsr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t dvdnt_r();
+ void dvdnt_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t dvdnth_r();
+ void dvdnth_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t dvdntl_r();
+ void dvdntl_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+
+ uint32_t dvcr_r();
+ void dvcr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
// DMAC
- template <int Channel> READ32_MEMBER(vcrdma_r)
+ template <int Channel> uint32_t vcrdma_r()
{
return m_vcrdma[Channel] & 0x7f;
}
- template <int Channel> WRITE32_MEMBER(vcrdma_w)
+ template <int Channel> void vcrdma_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0)
{
COMBINE_DATA(&m_vcrdma[Channel]);
m_irq_vector.dmac[Channel] = m_vcrdma[Channel] & 0x7f;
sh2_recalc_irq();
}
- template <int Channel> READ8_MEMBER(drcr_r) { return m_dmac[Channel].drcr & 3; }
- template <int Channel> WRITE8_MEMBER(drcr_w) { m_dmac[Channel].drcr = data & 3; sh2_recalc_irq(); }
- template <int Channel> READ32_MEMBER(sar_r) { return m_dmac[Channel].sar; }
- template <int Channel> WRITE32_MEMBER(sar_w) { COMBINE_DATA(&m_dmac[Channel].sar); }
- template <int Channel> READ32_MEMBER(dar_r) { return m_dmac[Channel].dar; }
- template <int Channel> WRITE32_MEMBER(dar_w) { COMBINE_DATA(&m_dmac[Channel].dar); }
- template <int Channel> READ32_MEMBER(dmac_tcr_r) { return m_dmac[Channel].tcr; }
- template <int Channel> WRITE32_MEMBER(dmac_tcr_w) { COMBINE_DATA(&m_dmac[Channel].tcr); m_dmac[Channel].tcr &= 0xffffff; }
- template <int Channel> READ32_MEMBER(chcr_r) { return m_dmac[Channel].chcr; }
- template <int Channel> WRITE32_MEMBER(chcr_w)
+ template <int Channel> uint8_t drcr_r() { return m_dmac[Channel].drcr & 3; }
+ template <int Channel> void drcr_w(uint8_t data) { m_dmac[Channel].drcr = data & 3; sh2_recalc_irq(); }
+ template <int Channel> uint32_t sar_r() { return m_dmac[Channel].sar; }
+ template <int Channel> void sar_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { COMBINE_DATA(&m_dmac[Channel].sar); }
+ template <int Channel> uint32_t dar_r() { return m_dmac[Channel].dar; }
+ template <int Channel> void dar_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { COMBINE_DATA(&m_dmac[Channel].dar); }
+ template <int Channel> uint32_t dmac_tcr_r() { return m_dmac[Channel].tcr; }
+ template <int Channel> void dmac_tcr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0) { COMBINE_DATA(&m_dmac[Channel].tcr); m_dmac[Channel].tcr &= 0xffffff; }
+ template <int Channel> uint32_t chcr_r() { return m_dmac[Channel].chcr; }
+ template <int Channel> void chcr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0)
{
uint32_t old;
old = m_dmac[Channel].chcr;
@@ -159,8 +159,8 @@ public:
m_dmac[Channel].chcr = (data & ~2) | (old & m_dmac[Channel].chcr & 2);
sh2_dmac_check(Channel);
}
- READ32_MEMBER( dmaor_r ) { return m_dmaor & 0xf; }
- WRITE32_MEMBER( dmaor_w )
+ uint32_t dmaor_r() { return m_dmaor & 0xf; }
+ void dmaor_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0)
{
if(ACCESSING_BITS_0_7)
{
@@ -173,32 +173,32 @@ public:
}
// WTC
- DECLARE_READ16_MEMBER( wtcnt_r );
- DECLARE_WRITE16_MEMBER( wtcnt_w );
- DECLARE_READ16_MEMBER( rstcsr_r );
- DECLARE_WRITE16_MEMBER( rstcsr_w );
+ uint16_t wtcnt_r();
+ void wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t rstcsr_r();
+ void rstcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
// misc
- DECLARE_READ16_MEMBER( fmr_sbycr_r );
- DECLARE_WRITE16_MEMBER( fmr_sbycr_w );
- DECLARE_READ8_MEMBER( ccr_r );
- DECLARE_WRITE8_MEMBER( ccr_w );
+ uint16_t fmr_sbycr_r();
+ void fmr_sbycr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint8_t ccr_r();
+ void ccr_w(uint8_t data);
// BSC
- DECLARE_READ32_MEMBER( bcr1_r );
- DECLARE_WRITE32_MEMBER( bcr1_w );
- DECLARE_READ32_MEMBER( bcr2_r );
- DECLARE_WRITE32_MEMBER( bcr2_w );
- DECLARE_READ32_MEMBER( wcr_r );
- DECLARE_WRITE32_MEMBER( wcr_w );
- DECLARE_READ32_MEMBER( mcr_r );
- DECLARE_WRITE32_MEMBER( mcr_w );
- DECLARE_READ32_MEMBER( rtcsr_r );
- DECLARE_WRITE32_MEMBER( rtcsr_w );
- DECLARE_READ32_MEMBER( rtcor_r );
- DECLARE_WRITE32_MEMBER( rtcor_w );
- DECLARE_READ32_MEMBER( rtcnt_r );
- DECLARE_WRITE32_MEMBER( rtcnt_w );
+ uint32_t bcr1_r();
+ void bcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t bcr2_r();
+ void bcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t wcr_r();
+ void wcr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t mcr_r();
+ void mcr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t rtcsr_r();
+ void rtcsr_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t rtcor_r();
+ void rtcor_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t rtcnt_r();
+ void rtcnt_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
virtual void set_frt_input(int state) override;
@@ -368,18 +368,18 @@ public:
// construction/destruction
sh2a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ32_MEMBER(dma_sar0_r);
- DECLARE_WRITE32_MEMBER(dma_sar0_w);
- DECLARE_READ32_MEMBER(dma_dar0_r);
- DECLARE_WRITE32_MEMBER(dma_dar0_w);
- DECLARE_READ16_MEMBER(dmaor_r);
- DECLARE_WRITE16_MEMBER(dmaor_w);
- DECLARE_READ16_MEMBER(dma_tcr0_r);
- DECLARE_WRITE16_MEMBER(dma_tcr0_w);
- DECLARE_READ16_MEMBER(dma_chcr0_r);
- DECLARE_WRITE16_MEMBER(dma_chcr0_w);
- DECLARE_READ16_MEMBER(sh7021_r);
- DECLARE_WRITE16_MEMBER(sh7021_w);
+ uint32_t dma_sar0_r();
+ void dma_sar0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t dma_dar0_r();
+ void dma_dar0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint16_t dmaor_r();
+ void dmaor_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t dma_tcr0_r();
+ void dma_tcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t dma_chcr0_r();
+ void dma_chcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t sh7021_r(offs_t offset);
+ void sh7021_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void sh7032_dma_exec(int ch);
void sh7021_map(address_map &map);
@@ -402,8 +402,8 @@ public:
// construction/destruction
sh1_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
- DECLARE_READ16_MEMBER(sh7032_r);
- DECLARE_WRITE16_MEMBER(sh7032_w);
+ uint16_t sh7032_r(offs_t offset);
+ void sh7032_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void sh7032_map(address_map &map);
private:
uint16_t m_sh7032_regs[0x200];
diff --git a/src/devices/cpu/sh/sh2comn.cpp b/src/devices/cpu/sh/sh2comn.cpp
index fc39aacd1f0..6a9286649c2 100644
--- a/src/devices/cpu/sh/sh2comn.cpp
+++ b/src/devices/cpu/sh/sh2comn.cpp
@@ -480,59 +480,59 @@ void sh2_device::sh2_dmac_check(int dmach)
*/
// TODO: identical to H8 counterpart
-READ8_MEMBER( sh2_device::smr_r )
+uint8_t sh2_device::smr_r()
{
return m_smr;
}
-WRITE8_MEMBER( sh2_device::smr_w )
+void sh2_device::smr_w(uint8_t data)
{
m_smr = data;
}
-READ8_MEMBER( sh2_device::brr_r )
+uint8_t sh2_device::brr_r()
{
return m_brr;
}
-WRITE8_MEMBER( sh2_device::brr_w )
+void sh2_device::brr_w(uint8_t data)
{
m_brr = data;
}
-READ8_MEMBER( sh2_device::scr_r )
+uint8_t sh2_device::scr_r()
{
return m_scr;
}
-WRITE8_MEMBER( sh2_device::scr_w )
+void sh2_device::scr_w(uint8_t data)
{
m_scr = data;
}
-READ8_MEMBER( sh2_device::tdr_r )
+uint8_t sh2_device::tdr_r()
{
return m_tdr;
}
-WRITE8_MEMBER( sh2_device::tdr_w )
+void sh2_device::tdr_w(uint8_t data)
{
m_tdr = data;
// printf("%c",data & 0xff);
}
-READ8_MEMBER( sh2_device::ssr_r )
+uint8_t sh2_device::ssr_r()
{
// 0x84 is needed by EGWord on Saturn to make it to boot for some reason.
return m_ssr | 0x84;
}
-WRITE8_MEMBER( sh2_device::ssr_w )
+void sh2_device::ssr_w(uint8_t data)
{
m_ssr = data;
}
-READ8_MEMBER( sh2_device::rdr_r )
+uint8_t sh2_device::rdr_r()
{
return 0;
}
@@ -541,12 +541,12 @@ READ8_MEMBER( sh2_device::rdr_r )
* FRC
*/
-READ8_MEMBER( sh2_device::tier_r )
+uint8_t sh2_device::tier_r()
{
return m_tier;
}
-WRITE8_MEMBER( sh2_device::tier_w )
+void sh2_device::tier_w(uint8_t data)
{
sh2_timer_resync();
m_tier = data;
@@ -554,7 +554,7 @@ WRITE8_MEMBER( sh2_device::tier_w )
sh2_recalc_irq();
}
-READ8_MEMBER( sh2_device::ftcsr_r )
+uint8_t sh2_device::ftcsr_r()
{
// TODO: to be tested
if (!m_ftcsr_read_cb.isnull())
@@ -563,7 +563,7 @@ READ8_MEMBER( sh2_device::ftcsr_r )
return m_ftcsr;
}
-WRITE8_MEMBER( sh2_device::ftcsr_w )
+void sh2_device::ftcsr_w(uint8_t data)
{
uint8_t old;
old = m_ftcsr;
@@ -575,13 +575,13 @@ WRITE8_MEMBER( sh2_device::ftcsr_w )
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::frc_r )
+uint16_t sh2_device::frc_r()
{
sh2_timer_resync();
return m_frc;
}
-WRITE16_MEMBER( sh2_device::frc_w )
+void sh2_device::frc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
sh2_timer_resync();
COMBINE_DATA(&m_frc);
@@ -589,12 +589,12 @@ WRITE16_MEMBER( sh2_device::frc_w )
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::ocra_b_r )
+uint16_t sh2_device::ocra_b_r()
{
return (m_tocr & 0x10) ? m_ocrb : m_ocra;
}
-WRITE16_MEMBER( sh2_device::ocra_b_w )
+void sh2_device::ocra_b_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
sh2_timer_resync();
if(m_tocr & 0x10)
@@ -605,12 +605,12 @@ WRITE16_MEMBER( sh2_device::ocra_b_w )
sh2_recalc_irq();
}
-READ8_MEMBER( sh2_device::frc_tcr_r )
+uint8_t sh2_device::frc_tcr_r()
{
return m_frc_tcr & 0x83;
}
-WRITE8_MEMBER( sh2_device::frc_tcr_w )
+void sh2_device::frc_tcr_w(uint8_t data)
{
sh2_timer_resync();
m_frc_tcr = data & 0x83;
@@ -618,12 +618,12 @@ WRITE8_MEMBER( sh2_device::frc_tcr_w )
sh2_recalc_irq();
}
-READ8_MEMBER( sh2_device::tocr_r )
+uint8_t sh2_device::tocr_r()
{
return (m_tocr & 0x13) | 0xe0;
}
-WRITE8_MEMBER( sh2_device::tocr_w )
+void sh2_device::tocr_w(uint8_t data)
{
sh2_timer_resync();
// TODO: output levels A/B (bits 1-0)
@@ -632,7 +632,7 @@ WRITE8_MEMBER( sh2_device::tocr_w )
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::frc_icr_r )
+uint16_t sh2_device::frc_icr_r()
{
return m_frc_icr;
}
@@ -641,26 +641,26 @@ READ16_MEMBER( sh2_device::frc_icr_r )
* INTC
*/
-READ16_MEMBER( sh2_device::intc_icr_r )
+uint16_t sh2_device::intc_icr_r()
{
// TODO: flip meaning based off NMI edge select bit (NMIE)
uint16_t nmilv = m_nmi_line_state == ASSERT_LINE ? 0 : 0x8000;
return (nmilv) | (m_intc_icr & 0x0101);
}
-WRITE16_MEMBER( sh2_device::intc_icr_w )
+void sh2_device::intc_icr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_intc_icr);
m_nmie = bool(BIT(m_intc_icr, 8));
m_vecmd = bool(BIT(m_intc_icr, 0));
}
-READ16_MEMBER( sh2_device::ipra_r )
+uint16_t sh2_device::ipra_r()
{
return m_ipra & 0xfff0;
}
-WRITE16_MEMBER( sh2_device::ipra_w )
+void sh2_device::ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_ipra);
m_irq_level.divu = (m_ipra >> 12) & 0xf;
@@ -669,12 +669,12 @@ WRITE16_MEMBER( sh2_device::ipra_w )
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::iprb_r )
+uint16_t sh2_device::iprb_r()
{
return m_iprb & 0xff00;
}
-WRITE16_MEMBER( sh2_device::iprb_w )
+void sh2_device::iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_iprb);
m_irq_level.sci = (m_iprb >> 12) & 0xf;
@@ -682,36 +682,36 @@ WRITE16_MEMBER( sh2_device::iprb_w )
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::vcra_r )
+uint16_t sh2_device::vcra_r()
{
return m_vcra & 0x7f7f;
}
-WRITE16_MEMBER( sh2_device::vcra_w )
+void sh2_device::vcra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_vcra);
// ...
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::vcrb_r )
+uint16_t sh2_device::vcrb_r()
{
return m_vcrb;
}
-WRITE16_MEMBER( sh2_device::vcrb_w )
+void sh2_device::vcrb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_vcrb);
// ...
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::vcrc_r )
+uint16_t sh2_device::vcrc_r()
{
return m_vcrc & 0x7f7f;
}
-WRITE16_MEMBER( sh2_device::vcrc_w )
+void sh2_device::vcrc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_vcrc);
m_irq_vector.fic = (m_vcrc >> 8) & 0x7f;
@@ -719,36 +719,36 @@ WRITE16_MEMBER( sh2_device::vcrc_w )
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::vcrd_r )
+uint16_t sh2_device::vcrd_r()
{
return m_vcrd & 0x7f00;
}
-WRITE16_MEMBER( sh2_device::vcrd_w )
+void sh2_device::vcrd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_vcrd);
m_irq_vector.fov = (m_vcrc >> 8) & 0x7f;
sh2_recalc_irq();
}
-READ16_MEMBER( sh2_device::vcrwdt_r )
+uint16_t sh2_device::vcrwdt_r()
{
return m_vcrwdt & 0x7f7f;
}
-WRITE16_MEMBER( sh2_device::vcrwdt_w )
+void sh2_device::vcrwdt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_vcrwdt);
// ...
sh2_recalc_irq();
}
-READ32_MEMBER( sh2_device::vcrdiv_r )
+uint32_t sh2_device::vcrdiv_r()
{
return m_vcrdiv & 0x7f;
}
-WRITE32_MEMBER( sh2_device::vcrdiv_w )
+void sh2_device::vcrdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_vcrdiv);
// TODO: unemulated, level is seemingly not documented/settable?
@@ -760,12 +760,12 @@ WRITE32_MEMBER( sh2_device::vcrdiv_w )
* DIVU
*/
-READ32_MEMBER( sh2_device::dvcr_r )
+uint32_t sh2_device::dvcr_r()
{
return (m_divu_ovfie == true ? 2 : 0) | (m_divu_ovf == true ? 1 : 0);
}
-WRITE32_MEMBER( sh2_device::dvcr_w )
+void sh2_device::dvcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if(ACCESSING_BITS_0_7)
{
@@ -781,22 +781,22 @@ WRITE32_MEMBER( sh2_device::dvcr_w )
}
}
-READ32_MEMBER( sh2_device::dvsr_r )
+uint32_t sh2_device::dvsr_r()
{
return m_dvsr;
}
-WRITE32_MEMBER( sh2_device::dvsr_w )
+void sh2_device::dvsr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dvsr);
}
-READ32_MEMBER( sh2_device::dvdnt_r )
+uint32_t sh2_device::dvdnt_r()
{
return m_dvdntl;
}
-WRITE32_MEMBER( sh2_device::dvdnt_w )
+void sh2_device::dvdnt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dvdntl);
int32_t a = m_dvdntl;
@@ -816,22 +816,22 @@ WRITE32_MEMBER( sh2_device::dvdnt_w )
}
}
-READ32_MEMBER( sh2_device::dvdnth_r )
+uint32_t sh2_device::dvdnth_r()
{
return m_dvdnth;
}
-READ32_MEMBER( sh2_device::dvdntl_r )
+uint32_t sh2_device::dvdntl_r()
{
return m_dvdntl;
}
-WRITE32_MEMBER( sh2_device::dvdnth_w )
+void sh2_device::dvdnth_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dvdnth);
}
-WRITE32_MEMBER( sh2_device::dvdntl_w )
+void sh2_device::dvdntl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dvdntl);
int64_t a = m_dvdntl | ((uint64_t)(m_dvdnth) << 32);
@@ -866,18 +866,18 @@ WRITE32_MEMBER( sh2_device::dvdntl_w )
* WTC
*/
-READ16_MEMBER( sh2_device::wtcnt_r )
+uint16_t sh2_device::wtcnt_r()
{
sh2_wtcnt_recalc();
return ((m_wtcsr | 0x18) << 8) | (m_wtcnt & 0xff);
}
-READ16_MEMBER( sh2_device::rstcsr_r )
+uint16_t sh2_device::rstcsr_r()
{
return (m_rstcsr & 0xe0) | 0x1f;
}
-WRITE16_MEMBER( sh2_device::wtcnt_w )
+void sh2_device::wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_wtcw[0]);
switch (m_wtcw[0] & 0xff00)
@@ -911,7 +911,7 @@ WRITE16_MEMBER( sh2_device::wtcnt_w )
}
}
-WRITE16_MEMBER( sh2_device::rstcsr_w )
+void sh2_device::rstcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_wtcw[1]);
switch (m_wtcw[1] & 0xff00)
@@ -927,12 +927,12 @@ WRITE16_MEMBER( sh2_device::rstcsr_w )
}
}
-READ16_MEMBER( sh2_device::fmr_sbycr_r )
+uint16_t sh2_device::fmr_sbycr_r()
{
return m_sbycr;
}
-WRITE16_MEMBER( sh2_device::fmr_sbycr_w )
+void sh2_device::fmr_sbycr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch (mem_mask)
{
@@ -952,12 +952,12 @@ WRITE16_MEMBER( sh2_device::fmr_sbycr_w )
}
}
-READ8_MEMBER( sh2_device::ccr_r )
+uint8_t sh2_device::ccr_r()
{
return m_ccr & ~0x30;
}
-WRITE8_MEMBER( sh2_device::ccr_w )
+void sh2_device::ccr_w(uint8_t data)
{
/*
xx-- ---- Way 0/1
@@ -970,73 +970,73 @@ WRITE8_MEMBER( sh2_device::ccr_w )
m_ccr = data;
}
-READ32_MEMBER( sh2_device::bcr1_r )
+uint32_t sh2_device::bcr1_r()
{
return (m_bcr1 & ~0xe008) | (m_is_slave ? 0x8000 : 0);
}
-WRITE32_MEMBER( sh2_device::bcr1_w )
+void sh2_device::bcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_bcr1);
}
-READ32_MEMBER( sh2_device::bcr2_r )
+uint32_t sh2_device::bcr2_r()
{
return m_bcr2;
}
-WRITE32_MEMBER( sh2_device::bcr2_w )
+void sh2_device::bcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_bcr2);
}
-READ32_MEMBER( sh2_device::wcr_r )
+uint32_t sh2_device::wcr_r()
{
return m_wcr;
}
-WRITE32_MEMBER( sh2_device::wcr_w )
+void sh2_device::wcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_wcr);
}
-READ32_MEMBER( sh2_device::mcr_r )
+uint32_t sh2_device::mcr_r()
{
return m_mcr & ~0x103;
}
-WRITE32_MEMBER( sh2_device::mcr_w )
+void sh2_device::mcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_mcr);
}
-READ32_MEMBER( sh2_device::rtcsr_r )
+uint32_t sh2_device::rtcsr_r()
{
return m_rtcsr & 0xf8;
}
-WRITE32_MEMBER( sh2_device::rtcsr_w )
+void sh2_device::rtcsr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_rtcsr);
}
-READ32_MEMBER( sh2_device::rtcnt_r )
+uint32_t sh2_device::rtcnt_r()
{
return m_rtcnt & 0xff;
}
-WRITE32_MEMBER( sh2_device::rtcnt_w )
+void sh2_device::rtcnt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_rtcnt);
m_rtcnt &= 0xff;
}
-READ32_MEMBER( sh2_device::rtcor_r )
+uint32_t sh2_device::rtcor_r()
{
return m_rtcor & 0xff;
}
-WRITE32_MEMBER( sh2_device::rtcor_w )
+void sh2_device::rtcor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_rtcor);
m_rtcor &= 0xff;
@@ -1171,55 +1171,55 @@ void sh2a_device::sh7032_dma_exec(int ch)
printf("%02x %02x %02x %1d\n",sm,dm,rs,ts);
}
-READ32_MEMBER(sh2a_device::dma_sar0_r)
+uint32_t sh2a_device::dma_sar0_r()
{
return m_dma[0].sar;
}
-WRITE32_MEMBER(sh2a_device::dma_sar0_w)
+void sh2a_device::dma_sar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dma[0].sar);
}
-READ32_MEMBER(sh2a_device::dma_dar0_r)
+uint32_t sh2a_device::dma_dar0_r()
{
return m_dma[0].dar;
}
-WRITE32_MEMBER(sh2a_device::dma_dar0_w)
+void sh2a_device::dma_dar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dma[0].dar);
}
-READ16_MEMBER(sh2a_device::dma_tcr0_r)
+uint16_t sh2a_device::dma_tcr0_r()
{
return m_dma[0].tcr;
}
-WRITE16_MEMBER(sh2a_device::dma_tcr0_w)
+void sh2a_device::dma_tcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
//printf("%04x\n",data);
COMBINE_DATA(&m_dma[0].tcr);
}
-READ16_MEMBER(sh2a_device::dma_chcr0_r)
+uint16_t sh2a_device::dma_chcr0_r()
{
return m_dma[0].chcr;
}
-WRITE16_MEMBER(sh2a_device::dma_chcr0_w)
+void sh2a_device::dma_chcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
//printf("%04x CHCR0\n",data);
COMBINE_DATA(&m_dma[0].chcr);
sh7032_dma_exec(0);
}
-READ16_MEMBER(sh2a_device::dmaor_r)
+uint16_t sh2a_device::dmaor_r()
{
return m_dmaor;
}
-WRITE16_MEMBER(sh2a_device::dmaor_w)
+void sh2a_device::dmaor_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_dmaor);
sh7032_dma_exec(0);
@@ -1228,7 +1228,7 @@ WRITE16_MEMBER(sh2a_device::dmaor_w)
/*!
@brief Dummy debug interface
*/
-READ16_MEMBER(sh1_device::sh7032_r)
+uint16_t sh1_device::sh7032_r(offs_t offset)
{
return m_sh7032_regs[offset];
}
@@ -1236,12 +1236,12 @@ READ16_MEMBER(sh1_device::sh7032_r)
/*!
@brief Dummy debug interface
*/
-WRITE16_MEMBER(sh1_device::sh7032_w)
+void sh1_device::sh7032_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_sh7032_regs[offset]);
}
-READ16_MEMBER(sh2a_device::sh7021_r)
+uint16_t sh2a_device::sh7021_r(offs_t offset)
{
return m_sh7021_regs[offset];
}
@@ -1249,7 +1249,7 @@ READ16_MEMBER(sh2a_device::sh7021_r)
/*!
@brief Dummy debug interface
*/
-WRITE16_MEMBER(sh2a_device::sh7021_w)
+void sh2a_device::sh7021_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_sh7021_regs[offset]);
}
diff --git a/src/devices/cpu/sh/sh3comn.cpp b/src/devices/cpu/sh/sh3comn.cpp
index 77f4b079414..b8bb6f0b8a4 100644
--- a/src/devices/cpu/sh/sh3comn.cpp
+++ b/src/devices/cpu/sh/sh3comn.cpp
@@ -12,7 +12,7 @@
/* High internal area (ffffxxxx) */
-WRITE32_MEMBER( sh3_base_device::sh3_internal_high_w )
+void sh3_base_device::sh3_internal_high_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_sh3internal_upper[offset]);
@@ -73,7 +73,7 @@ WRITE32_MEMBER( sh3_base_device::sh3_internal_high_w )
}
-READ32_MEMBER( sh3_base_device::sh3_internal_high_r )
+uint32_t sh3_base_device::sh3_internal_high_r(offs_t offset, uint32_t mem_mask)
{
uint32_t ret = 0;
@@ -138,7 +138,7 @@ READ32_MEMBER( sh3_base_device::sh3_internal_high_r )
}
-READ32_MEMBER( sh3_base_device::sh3_internal_r )
+uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (offset<0x1000)
{
@@ -376,7 +376,7 @@ READ32_MEMBER( sh3_base_device::sh3_internal_r )
/* Lower internal area */
-WRITE32_MEMBER( sh3_base_device::sh3_internal_w )
+void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (offset<0x1000)
{
diff --git a/src/devices/cpu/sh/sh4.h b/src/devices/cpu/sh/sh4.h
index 6af65a31b34..87fe2e84f70 100644
--- a/src/devices/cpu/sh/sh4.h
+++ b/src/devices/cpu/sh/sh4.h
@@ -682,11 +682,11 @@ private:
class sh3_base_device : public sh34_base_device
{
public:
- DECLARE_WRITE32_MEMBER( sh3_internal_w );
- DECLARE_READ32_MEMBER( sh3_internal_r );
+ void sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t sh3_internal_r(offs_t offset, uint32_t mem_mask = ~0);
- DECLARE_WRITE32_MEMBER( sh3_internal_high_w );
- DECLARE_READ32_MEMBER( sh3_internal_high_r );
+ void sh3_internal_high_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t sh3_internal_high_r(offs_t offset, uint32_t mem_mask = ~0);
void sh3_internal_map(address_map &map);
protected:
@@ -700,8 +700,8 @@ protected:
class sh4_base_device : public sh34_base_device
{
public:
- DECLARE_WRITE32_MEMBER( sh4_internal_w );
- DECLARE_READ32_MEMBER( sh4_internal_r );
+ void sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t sh4_internal_r(offs_t offset, uint32_t mem_mask = ~0);
uint64_t sh4_utlb_address_array_r(offs_t offset);
void sh4_utlb_address_array_w(offs_t offset, uint64_t data);
diff --git a/src/devices/cpu/sh/sh4comn.cpp b/src/devices/cpu/sh/sh4comn.cpp
index f7678767e68..9c1d3bd3380 100644
--- a/src/devices/cpu/sh/sh4comn.cpp
+++ b/src/devices/cpu/sh/sh4comn.cpp
@@ -673,7 +673,7 @@ void sh34_base_device::sh4_handler_ipra_w(uint32_t data, uint32_t mem_mask)
}
-WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
+void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
int a;
uint32_t addr = (offset << 2) + 0xfe000000;
@@ -980,7 +980,7 @@ WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
}
}
-READ32_MEMBER( sh4_base_device::sh4_internal_r )
+uint32_t sh4_base_device::sh4_internal_r(offs_t offset, uint32_t mem_mask)
{
if (m_cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_internal_r uses m_m[] with SH3\n");
diff --git a/src/devices/cpu/sh/sh7604_bus.cpp b/src/devices/cpu/sh/sh7604_bus.cpp
index 6175fd9a5b2..a4b61bddae6 100644
--- a/src/devices/cpu/sh/sh7604_bus.cpp
+++ b/src/devices/cpu/sh/sh7604_bus.cpp
@@ -30,12 +30,12 @@ DEFINE_DEVICE_TYPE(SH7604_BUS, sh7604_bus_device, "sh7604bus", "SH7604 BUS Contr
// LIVE DEVICE
//**************************************************************************
-READ16_MEMBER(sh7604_bus_device::bus_control_1_r)
+uint16_t sh7604_bus_device::bus_control_1_r()
{
return (m_bcr1 & 0x1ff7) | (m_is_slave == true ? 0x8000 : 0);
}
-WRITE16_MEMBER(sh7604_bus_device::bus_control_1_w)
+void sh7604_bus_device::bus_control_1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_bcr1);
if(m_bcr1 & 0x1000) // ENDIAN
@@ -44,26 +44,26 @@ WRITE16_MEMBER(sh7604_bus_device::bus_control_1_w)
throw emu_fatalerror("%s: enabled partial space share mode\n", tag());
}
-READ16_MEMBER(sh7604_bus_device::bus_control_2_r) { return m_bcr2 & 0x00fc; }
-WRITE16_MEMBER(sh7604_bus_device::bus_control_2_w)
+uint16_t sh7604_bus_device::bus_control_2_r() { return m_bcr2 & 0x00fc; }
+void sh7604_bus_device::bus_control_2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_bcr2);
if(m_bcr2 != 0x00fc)
throw emu_fatalerror("%s: unexpected bus size register set %04x\n", tag(),data);
}
-READ16_MEMBER(sh7604_bus_device::wait_control_r) { return m_wcr; }
-WRITE16_MEMBER(sh7604_bus_device::wait_control_w) { COMBINE_DATA(&m_wcr); }
+uint16_t sh7604_bus_device::wait_control_r() { return m_wcr; }
+void sh7604_bus_device::wait_control_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_wcr); }
-READ16_MEMBER(sh7604_bus_device::memory_control_r) { return m_mcr & 0xfefc; }
-WRITE16_MEMBER(sh7604_bus_device::memory_control_w) { COMBINE_DATA(&m_mcr); }
+uint16_t sh7604_bus_device::memory_control_r() { return m_mcr & 0xfefc; }
+void sh7604_bus_device::memory_control_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_mcr); }
-READ16_MEMBER(sh7604_bus_device::refresh_timer_status_r)
+uint16_t sh7604_bus_device::refresh_timer_status_r()
{
return m_rtcsr & 0x00f8;
}
-WRITE16_MEMBER(sh7604_bus_device::refresh_timer_control_w)
+void sh7604_bus_device::refresh_timer_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_rtcsr);
@@ -71,24 +71,24 @@ WRITE16_MEMBER(sh7604_bus_device::refresh_timer_control_w)
throw emu_fatalerror("%s: enabled timer irq register with clock setting = %02x\n",tag(),data & 0x38);
}
-READ16_MEMBER(sh7604_bus_device::refresh_timer_counter_r)
+uint16_t sh7604_bus_device::refresh_timer_counter_r()
{
throw emu_fatalerror("%s: reading timer counter!\n",tag());
return 0;
}
-WRITE16_MEMBER(sh7604_bus_device::refresh_timer_counter_w)
+void sh7604_bus_device::refresh_timer_counter_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
throw emu_fatalerror("%s: writing timer counter %04x\n",tag(),data);
//COMBINE_DATA(&m_rtcnt);
}
-READ16_MEMBER(sh7604_bus_device::refresh_timer_constant_r)
+uint16_t sh7604_bus_device::refresh_timer_constant_r()
{
return m_rtcor & 0xff;
}
-WRITE16_MEMBER(sh7604_bus_device::refresh_timer_constant_w)
+void sh7604_bus_device::refresh_timer_constant_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_rtcor);
}
@@ -142,13 +142,13 @@ void sh7604_bus_device::device_reset()
// READ/WRITE HANDLERS
//**************************************************************************
-READ32_MEMBER( sh7604_bus_device::read )
+uint32_t sh7604_bus_device::read(address_space &space, offs_t offset)
{
// 16 bit access only, TODO
return space.read_word(offset) & 0xffff;
}
-WRITE32_MEMBER( sh7604_bus_device::write )
+void sh7604_bus_device::write(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask)
{
// TODO: 8 bit access is invalid
// if accessing bits 16-31, one must write ID = 0xa55a
diff --git a/src/devices/cpu/sh/sh7604_bus.h b/src/devices/cpu/sh/sh7604_bus.h
index 672934aa5ae..9d2915b6b6b 100644
--- a/src/devices/cpu/sh/sh7604_bus.h
+++ b/src/devices/cpu/sh/sh7604_bus.h
@@ -28,22 +28,22 @@ public:
// I/O operations
void bus_regs(address_map &map);
- DECLARE_WRITE32_MEMBER( write );
- DECLARE_READ32_MEMBER( read );
- DECLARE_READ16_MEMBER( bus_control_1_r );
- DECLARE_WRITE16_MEMBER( bus_control_1_w );
- DECLARE_READ16_MEMBER( bus_control_2_r );
- DECLARE_WRITE16_MEMBER( bus_control_2_w );
- DECLARE_READ16_MEMBER( wait_control_r );
- DECLARE_WRITE16_MEMBER( wait_control_w );
- DECLARE_READ16_MEMBER( memory_control_r );
- DECLARE_WRITE16_MEMBER( memory_control_w );
- DECLARE_READ16_MEMBER( refresh_timer_status_r );
- DECLARE_WRITE16_MEMBER( refresh_timer_control_w );
- DECLARE_READ16_MEMBER( refresh_timer_counter_r );
- DECLARE_WRITE16_MEMBER( refresh_timer_counter_w );
- DECLARE_READ16_MEMBER( refresh_timer_constant_r );
- DECLARE_WRITE16_MEMBER( refresh_timer_constant_w );
+ void write(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t read(address_space &space, offs_t offset);
+ uint16_t bus_control_1_r();
+ void bus_control_1_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bus_control_2_r();
+ void bus_control_2_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t wait_control_r();
+ void wait_control_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t memory_control_r();
+ void memory_control_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t refresh_timer_status_r();
+ void refresh_timer_control_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t refresh_timer_counter_r();
+ void refresh_timer_counter_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t refresh_timer_constant_r();
+ void refresh_timer_constant_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
protected:
// device-level overrides
diff --git a/src/devices/cpu/sh/sh7604_wdt.cpp b/src/devices/cpu/sh/sh7604_wdt.cpp
index f18ca8ad501..2b5ea9eb499 100644
--- a/src/devices/cpu/sh/sh7604_wdt.cpp
+++ b/src/devices/cpu/sh/sh7604_wdt.cpp
@@ -67,12 +67,12 @@ void sh7604_wdt_device::device_reset()
// READ/WRITE HANDLERS
//**************************************************************************
-READ8_MEMBER( sh7604_wdt_device::read )
+uint8_t sh7604_wdt_device::read(address_space &space, offs_t offset)
{
return space.read_byte(offset);
}
-WRITE16_MEMBER( sh7604_wdt_device::write )
+void sh7604_wdt_device::write(address_space &space, offs_t offset, uint16_t data)
{
uint8_t id_param = data >> 8;
switch(id_param)
diff --git a/src/devices/cpu/sh/sh7604_wdt.h b/src/devices/cpu/sh/sh7604_wdt.h
index 70490ba8153..dd39f4be514 100644
--- a/src/devices/cpu/sh/sh7604_wdt.h
+++ b/src/devices/cpu/sh/sh7604_wdt.h
@@ -28,8 +28,8 @@ public:
// I/O operations
void wdt_regs(address_map &map);
- DECLARE_WRITE16_MEMBER( write );
- DECLARE_READ8_MEMBER( read );
+ void write(address_space &space, offs_t offset, uint16_t data);
+ uint8_t read(address_space &space, offs_t offset);
protected:
// device-level overrides
diff --git a/src/devices/cpu/sharc/sharc.cpp b/src/devices/cpu/sharc/sharc.cpp
index a2e6d9f7b82..d11f7dd96cd 100644
--- a/src/devices/cpu/sharc/sharc.cpp
+++ b/src/devices/cpu/sharc/sharc.cpp
@@ -244,7 +244,7 @@ void adsp21062_device::pm1_w(offs_t offset, uint64_t data, uint64_t mem_mask)
}
}
-READ32_MEMBER( adsp21062_device::dmw0_r)
+uint32_t adsp21062_device::dmw0_r(offs_t offset)
{
if(offset & 1)
return m_block0[offset >> 1] >> 16;
@@ -252,7 +252,7 @@ READ32_MEMBER( adsp21062_device::dmw0_r)
return m_block0[offset >> 1] & 0xffff;
}
-WRITE32_MEMBER(adsp21062_device::dmw0_w)
+void adsp21062_device::dmw0_w(offs_t offset, uint32_t data)
{
if(offset & 1)
m_block0[offset >> 1] = (m_block0[offset >> 1] & 0xffff) | (data << 16);
@@ -260,7 +260,7 @@ WRITE32_MEMBER(adsp21062_device::dmw0_w)
m_block0[offset >> 1] = (m_block0[offset >> 1] & 0xffff0000) | (data & 0xffff);
}
-READ32_MEMBER( adsp21062_device::dmw1_r)
+uint32_t adsp21062_device::dmw1_r(offs_t offset)
{
if(offset & 1)
return m_block1[offset >> 1] >> 16;
@@ -268,7 +268,7 @@ READ32_MEMBER( adsp21062_device::dmw1_r)
return m_block1[offset >> 1] & 0xffff;
}
-WRITE32_MEMBER(adsp21062_device::dmw1_w)
+void adsp21062_device::dmw1_w(offs_t offset, uint32_t data)
{
if(offset & 1)
m_block1[offset >> 1] = (m_block1[offset >> 1] & 0xffff) | (data << 16);
@@ -277,7 +277,7 @@ WRITE32_MEMBER(adsp21062_device::dmw1_w)
}
/* IOP registers */
-READ32_MEMBER( adsp21062_device::iop_r)
+uint32_t adsp21062_device::iop_r(offs_t offset)
{
switch (offset)
{
@@ -295,7 +295,7 @@ READ32_MEMBER( adsp21062_device::iop_r)
}
}
-WRITE32_MEMBER(adsp21062_device::iop_w)
+void adsp21062_device::iop_w(offs_t offset, uint32_t data)
{
switch (offset)
{
diff --git a/src/devices/cpu/sharc/sharc.h b/src/devices/cpu/sharc/sharc.h
index 9cd61fe89a6..6c9292c5193 100644
--- a/src/devices/cpu/sharc/sharc.h
+++ b/src/devices/cpu/sharc/sharc.h
@@ -123,12 +123,12 @@ public:
void pm0_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0);
uint64_t pm1_r(offs_t offset);
void pm1_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0);
- DECLARE_READ32_MEMBER( dmw0_r);
- DECLARE_WRITE32_MEMBER(dmw0_w);
- DECLARE_READ32_MEMBER( dmw1_r);
- DECLARE_WRITE32_MEMBER(dmw1_w);
- DECLARE_READ32_MEMBER( iop_r);
- DECLARE_WRITE32_MEMBER(iop_w);
+ uint32_t dmw0_r(offs_t offset);
+ void dmw0_w(offs_t offset, uint32_t data);
+ uint32_t dmw1_r(offs_t offset);
+ void dmw1_w(offs_t offset, uint32_t data);
+ uint32_t iop_r(offs_t offset);
+ void iop_w(offs_t offset, uint32_t data);
enum ASTAT_FLAGS
{
diff --git a/src/devices/cpu/tms32025/tms32025.cpp b/src/devices/cpu/tms32025/tms32025.cpp
index 7d07c2f43df..11444c83b23 100644
--- a/src/devices/cpu/tms32025/tms32025.cpp
+++ b/src/devices/cpu/tms32025/tms32025.cpp
@@ -292,22 +292,22 @@ std::unique_ptr<util::disasm_interface> tms32025_device::create_disassembler()
return std::make_unique<tms32025_disassembler>();
}
-READ16_MEMBER( tms32025_device::drr_r)
+uint16_t tms32025_device::drr_r()
{
return m_drr;
}
-WRITE16_MEMBER(tms32025_device::drr_w)
+void tms32025_device::drr_w(uint16_t data)
{
m_drr = data;
}
-READ16_MEMBER( tms32025_device::dxr_r)
+uint16_t tms32025_device::dxr_r()
{
return m_dxr;
}
-WRITE16_MEMBER(tms32025_device::dxr_w)
+void tms32025_device::dxr_w(uint16_t data)
{
m_dxr = data;
@@ -319,42 +319,42 @@ WRITE16_MEMBER(tms32025_device::dxr_w)
}
}
-READ16_MEMBER( tms32025_device::tim_r)
+uint16_t tms32025_device::tim_r()
{
return m_tim;
}
-WRITE16_MEMBER(tms32025_device::tim_w)
+void tms32025_device::tim_w(uint16_t data)
{
m_tim = data;
}
-READ16_MEMBER( tms32025_device::prd_r)
+uint16_t tms32025_device::prd_r()
{
return m_prd;
}
-WRITE16_MEMBER(tms32025_device::prd_w)
+void tms32025_device::prd_w(uint16_t data)
{
m_prd = data;
}
-READ16_MEMBER( tms32025_device::imr_r)
+uint16_t tms32025_device::imr_r()
{
return m_imr;
}
-WRITE16_MEMBER(tms32025_device::imr_w)
+void tms32025_device::imr_w(uint16_t data)
{
m_imr = data;
}
-READ16_MEMBER( tms32025_device::greg_r)
+uint16_t tms32025_device::greg_r()
{
return m_greg;
}
-WRITE16_MEMBER(tms32025_device::greg_w)
+void tms32025_device::greg_w(uint16_t data)
{
m_greg = data;
}
diff --git a/src/devices/cpu/tms32025/tms32025.h b/src/devices/cpu/tms32025/tms32025.h
index e2e2c799897..de8b4442c08 100644
--- a/src/devices/cpu/tms32025/tms32025.h
+++ b/src/devices/cpu/tms32025/tms32025.h
@@ -75,19 +75,6 @@ public:
void set_mp_mc(bool state) { m_mp_mc = state; }
- DECLARE_READ16_MEMBER( drr_r);
- DECLARE_WRITE16_MEMBER(drr_w);
- DECLARE_READ16_MEMBER( dxr_r);
- DECLARE_WRITE16_MEMBER(dxr_w);
- DECLARE_READ16_MEMBER( tim_r);
- DECLARE_WRITE16_MEMBER(tim_w);
- DECLARE_READ16_MEMBER( prd_r);
- DECLARE_WRITE16_MEMBER(prd_w);
- DECLARE_READ16_MEMBER( imr_r);
- DECLARE_WRITE16_MEMBER(imr_w);
- DECLARE_READ16_MEMBER( greg_r);
- DECLARE_WRITE16_MEMBER(greg_w);
-
//void tms32025_program(address_map &map);
void tms32025_data(address_map &map);
void tms32026_data(address_map &map);
@@ -185,6 +172,19 @@ protected:
int m_waiting_for_serial_frame;
bool m_mp_mc;
+ uint16_t drr_r();
+ void drr_w(uint16_t data);
+ uint16_t dxr_r();
+ void dxr_w(uint16_t data);
+ uint16_t tim_r();
+ void tim_w(uint16_t data);
+ uint16_t prd_r();
+ void prd_w(uint16_t data);
+ uint16_t imr_r();
+ void imr_w(uint16_t data);
+ uint16_t greg_r();
+ void greg_w(uint16_t data);
+
inline void CLR0(uint16_t flag);
inline void SET0(uint16_t flag);
inline void CLR1(uint16_t flag);
diff --git a/src/devices/cpu/tms32031/tms32031.cpp b/src/devices/cpu/tms32031/tms32031.cpp
index a90455c8bd4..98365fbbc8a 100644
--- a/src/devices/cpu/tms32031/tms32031.cpp
+++ b/src/devices/cpu/tms32031/tms32031.cpp
@@ -983,7 +983,7 @@ void tms3203x_device::execute_run()
}
// internal peripherals
-WRITE32_MEMBER(tms3203x_device::primary_bus_control_w)
+void tms3203x_device::primary_bus_control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// change in internal hold state
if ((m_primary_bus_control ^ data) & HIZ)
diff --git a/src/devices/cpu/tms32031/tms32031.h b/src/devices/cpu/tms32031/tms32031.h
index 5f998920089..f27f0757244 100644
--- a/src/devices/cpu/tms32031/tms32031.h
+++ b/src/devices/cpu/tms32031/tms32031.h
@@ -172,8 +172,8 @@ protected:
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
// internal peripheral device handlers
- DECLARE_READ32_MEMBER(primary_bus_control_r) { return m_primary_bus_control; }
- DECLARE_WRITE32_MEMBER(primary_bus_control_w);
+ uint32_t primary_bus_control_r() { return m_primary_bus_control; }
+ void primary_bus_control_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
// memory helpers
uint32_t ROPCODE(offs_t pc);
diff --git a/src/devices/cpu/tms32051/tms32051.cpp b/src/devices/cpu/tms32051/tms32051.cpp
index 1691c66b2e2..29fb4f14f29 100644
--- a/src/devices/cpu/tms32051/tms32051.cpp
+++ b/src/devices/cpu/tms32051/tms32051.cpp
@@ -444,7 +444,7 @@ void tms32051_device::execute_run()
/*****************************************************************************/
-READ16_MEMBER( tms32051_device::cpuregs_r )
+uint16_t tms32051_device::cpuregs_r(offs_t offset)
{
switch (offset)
{
@@ -529,7 +529,7 @@ READ16_MEMBER( tms32051_device::cpuregs_r )
return 0;
}
-WRITE16_MEMBER( tms32051_device::cpuregs_w )
+void tms32051_device::cpuregs_w(offs_t offset, uint16_t data)
{
switch (offset)
{
diff --git a/src/devices/cpu/tms32051/tms32051.h b/src/devices/cpu/tms32051/tms32051.h
index 06f69489032..63552d7e605 100644
--- a/src/devices/cpu/tms32051/tms32051.h
+++ b/src/devices/cpu/tms32051/tms32051.h
@@ -59,8 +59,8 @@ public:
// construction/destruction
tms32051_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ16_MEMBER( cpuregs_r );
- DECLARE_WRITE16_MEMBER( cpuregs_w );
+ uint16_t cpuregs_r(offs_t offset);
+ void cpuregs_w(offs_t offset, uint16_t data);
void tms32051_internal_data(address_map &map);
void tms32051_internal_pgm(address_map &map);