diff options
author | 2020-05-25 15:58:09 +0100 | |
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committer | 2020-05-25 16:58:09 +0200 | |
commit | ad7a31ad57b09e1e0e9bb1adb03767f9dd386605 (patch) | |
tree | c6ebe406df3e406c93b776b535e9d889bd9f1d1a /src/devices/cpu/unsp | |
parent | 96e2e7ab7e054cad2079afff529759dfb06737c1 (diff) |
unsp20 - fix opcode decode priority, we causing an ASR operation to be decoded as a MUL [David Haywood] (#6740)
Diffstat (limited to 'src/devices/cpu/unsp')
-rw-r--r-- | src/devices/cpu/unsp/unsp_exxx.cpp | 54 | ||||
-rw-r--r-- | src/devices/cpu/unsp/unspdasm_exxx.cpp | 4 |
2 files changed, 18 insertions, 40 deletions
diff --git a/src/devices/cpu/unsp/unsp_exxx.cpp b/src/devices/cpu/unsp/unsp_exxx.cpp index 06ccd2e11f5..89cbb8d95fd 100644 --- a/src/devices/cpu/unsp/unsp_exxx.cpp +++ b/src/devices/cpu/unsp/unsp_exxx.cpp @@ -196,55 +196,33 @@ void unsp_12_device::execute_exxx_group(uint16_t op) } return; } - else if (((op & 0xf0f8) == 0xe008)) + else if (((op & 0xf1f8) == 0xe008)) { // MUL operations // MUL 1 1 1 0* r r r S* 0 0 0 0 1 r r r (* = sign bit, fixed here) /* - print_mul(stream, op); // MUL uu or MUL su + print_mul(stream, op); // MUL uu */ + // only valid if S is 1, otherwise falls through to shifter - if (op & 0x0100) - { - // MUL su ( unsigned * signed ) - const uint16_t opa = (op >> 9) & 7; - const uint16_t opb = op & 7; - m_core->m_icount -= 12; - - LOGMASKED(LOG_UNSP_MULS, "%s: MUL su with %04x (signed) * %04x (unsigned) (fra:%d) :\n", machine().describe_context(), m_core->m_r[opa], m_core->m_r[opb], m_core->m_fra); + // MUL uu (unsigned * unsigned) + uint32_t lres = 0; + const uint16_t opa = (op >> 9) & 7; + const uint16_t opb = op & 7; - uint32_t lres = m_core->m_r[opa] * m_core->m_r[opb]; - if (m_core->m_r[opa] & 0x8000) - { - lres -= m_core->m_r[opb] << 16; - } - m_core->m_r[REG_R4] = lres >> 16; - m_core->m_r[REG_R3] = (uint16_t)lres; - - LOGMASKED(LOG_UNSP_MULS, "result was : %08x\n", lres); - - return; - } - else - { - // MUL uu (unsigned * unsigned) - uint32_t lres = 0; - const uint16_t opa = (op >> 9) & 7; - const uint16_t opb = op & 7; - - m_core->m_icount -= 12; // unknown - lres = m_core->m_r[opa] * m_core->m_r[opb]; - m_core->m_r[REG_R4] = lres >> 16; - m_core->m_r[REG_R3] = (uint16_t)lres; - return; - } + m_core->m_icount -= 12; // unknown + lres = m_core->m_r[opa] * m_core->m_r[opb]; + m_core->m_r[REG_R4] = lres >> 16; + m_core->m_r[REG_R3] = (uint16_t)lres; return; - } - else if (((op & 0xf080) == 0xe080)) + } + else if (((op & 0xf180) == 0xe080)) { // MULS 1 1 1 0* r r r S* 1 s s s s r r r (* = sign bit, fixed here) /* - // MULS uu or MULS su (invalid?) + // MULS uu + // only valid if S is 1? otherwise falls through to shifter + print_muls(stream, op); */ LOGMASKED(LOG_UNSP_MULS, "MULS uu or su\n"); diff --git a/src/devices/cpu/unsp/unspdasm_exxx.cpp b/src/devices/cpu/unsp/unspdasm_exxx.cpp index 43c494cc0a5..c9d95d2d072 100644 --- a/src/devices/cpu/unsp/unspdasm_exxx.cpp +++ b/src/devices/cpu/unsp/unspdasm_exxx.cpp @@ -87,14 +87,14 @@ offs_t unsp_12_disassembler::disassemble_exxx_group(std::ostream& stream, offs_t util::stream_format(stream, "%s ds:[%s],%s", bitops[bitop], regs[rd], regs[rs]); return UNSP_DASM_OK; } - else if (((op & 0xf0f8) == 0xe008)) + else if (((op & 0xf1f8) == 0xe008)) { // MUL operations // MUL 1 1 1 0* r r r S* 0 0 0 0 1 r r r (* = sign bit, fixed here) print_mul(stream, op); // MUL uu or MUL su (invalid?) return UNSP_DASM_OK; } - else if (((op & 0xf080) == 0xe080)) + else if (((op & 0xf180) == 0xe080)) { // MULS 1 1 1 0* r r r S* 1 s s s s r r r (* = sign bit, fixed here) |