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author Olivier Galibert <galibert@pobox.com>2022-06-16 12:47:52 +0200
committer Olivier Galibert <galibert@pobox.com>2025-04-29 23:06:41 +0200
commit45d4cd52a8194f2ef9e0383cfb2e2a35634af6ff (patch)
tree4e8d8fcb7382a5e9e0bce5ec59939bcfbe67155a /src/devices/cpu/tms1000/tms1k_base.cpp
parent5c14bcdfcb4aefb71b5b62387c4ad05dbeb3814e (diff)
full xtal conversionxtal
Diffstat (limited to 'src/devices/cpu/tms1000/tms1k_base.cpp')
-rw-r--r--src/devices/cpu/tms1000/tms1k_base.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/devices/cpu/tms1000/tms1k_base.cpp b/src/devices/cpu/tms1000/tms1k_base.cpp
index 8034c2c7b4c..729e8274476 100644
--- a/src/devices/cpu/tms1000/tms1k_base.cpp
+++ b/src/devices/cpu/tms1000/tms1k_base.cpp
@@ -71,7 +71,7 @@ unknown cycle: CME, SSE, SSS
#include "emu.h"
#include "tms1k_base.h"
-tms1k_base_device::tms1k_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 o_pins, u8 r_pins, u8 pc_bits, u8 byte_bits, u8 x_bits, u8 stack_levels, int rom_width, address_map_constructor rom_map, int ram_width, address_map_constructor ram_map) :
+tms1k_base_device::tms1k_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, const XTAL &clock, u8 o_pins, u8 r_pins, u8 pc_bits, u8 byte_bits, u8 x_bits, u8 stack_levels, int rom_width, address_map_constructor rom_map, int ram_width, address_map_constructor ram_map) :
cpu_device(mconfig, type, tag, owner, clock),
m_program_config("program", ENDIANNESS_BIG, byte_bits > 8 ? 16 : 8, rom_width, byte_bits > 8 ? -1 : 0, rom_map),
m_data_config("data", ENDIANNESS_BIG, 8, ram_width, 0, ram_map),